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authorShawn Guo <shawn.guo@freescale.com>2010-12-18 08:39:33 -0500
committerUwe Kleine-König <u.kleine-koenig@pengutronix.de>2010-12-20 11:30:22 -0500
commit30a7585ff7464ceb1dceb941700654923becb769 (patch)
tree42c060756bdc2eb464ced6e34982da49b9311580 /arch/arm
parentbf985969e27b507f734435a99df8bf745a3dbb2b (diff)
ARM: mxs: Add clock support
Add clock for MXS-based SoCs, MX23 and MX28. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-mxs/clock-mx23.c526
-rw-r--r--arch/arm/mach-mxs/clock-mx28.c734
-rw-r--r--arch/arm/mach-mxs/clock.c200
-rw-r--r--arch/arm/mach-mxs/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-mxs/include/mach/clock.h64
-rw-r--r--arch/arm/mach-mxs/regs-clkctrl-mx23.h455
-rw-r--r--arch/arm/mach-mxs/regs-clkctrl-mx28.h663
7 files changed, 2649 insertions, 0 deletions
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
new file mode 100644
index 000000000000..8f5a19ab558c
--- /dev/null
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -0,0 +1,526 @@
1/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/mm.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23#include <linux/jiffies.h>
24
25#include <asm/clkdev.h>
26#include <asm/div64.h>
27
28#include <mach/mx23.h>
29#include <mach/common.h>
30#include <mach/clock.h>
31
32#include "regs-clkctrl-mx23.h"
33
34#define CLKCTRL_BASE_ADDR MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR)
35#define DIGCTRL_BASE_ADDR MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR)
36
37#define PARENT_RATE_SHIFT 8
38
39static int _raw_clk_enable(struct clk *clk)
40{
41 u32 reg;
42
43 if (clk->enable_reg) {
44 reg = __raw_readl(clk->enable_reg);
45 reg &= ~(1 << clk->enable_shift);
46 __raw_writel(reg, clk->enable_reg);
47 }
48
49 return 0;
50}
51
52static void _raw_clk_disable(struct clk *clk)
53{
54 u32 reg;
55
56 if (clk->enable_reg) {
57 reg = __raw_readl(clk->enable_reg);
58 reg |= 1 << clk->enable_shift;
59 __raw_writel(reg, clk->enable_reg);
60 }
61}
62
63/*
64 * ref_xtal_clk
65 */
66static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
67{
68 return 24000000;
69}
70
71static struct clk ref_xtal_clk = {
72 .get_rate = ref_xtal_clk_get_rate,
73};
74
75/*
76 * pll_clk
77 */
78static unsigned long pll_clk_get_rate(struct clk *clk)
79{
80 return 480000000;
81}
82
83static int pll_clk_enable(struct clk *clk)
84{
85 __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
86 BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
87 CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_SET);
88
89 /* Only a 10us delay is need. PLLCTRL1 LOCK bitfied is only a timer
90 * and is incorrect (excessive). Per definition of the PLLCTRL0
91 * POWER field, waiting at least 10us.
92 */
93 udelay(10);
94
95 return 0;
96}
97
98static void pll_clk_disable(struct clk *clk)
99{
100 __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
101 BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
102 CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_CLR);
103}
104
105static struct clk pll_clk = {
106 .get_rate = pll_clk_get_rate,
107 .enable = pll_clk_enable,
108 .disable = pll_clk_disable,
109 .parent = &ref_xtal_clk,
110};
111
112/*
113 * ref_clk
114 */
115#define _CLK_GET_RATE_REF(name, sr, ss) \
116static unsigned long name##_get_rate(struct clk *clk) \
117{ \
118 unsigned long parent_rate; \
119 u32 reg, div; \
120 \
121 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \
122 div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \
123 parent_rate = clk_get_rate(clk->parent); \
124 \
125 return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18, \
126 div, PARENT_RATE_SHIFT); \
127}
128
129_CLK_GET_RATE_REF(ref_cpu_clk, FRAC, CPU)
130_CLK_GET_RATE_REF(ref_emi_clk, FRAC, EMI)
131_CLK_GET_RATE_REF(ref_pix_clk, FRAC, PIX)
132_CLK_GET_RATE_REF(ref_io_clk, FRAC, IO)
133
134#define _DEFINE_CLOCK_REF(name, er, es) \
135 static struct clk name = { \
136 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
137 .enable_shift = BP_CLKCTRL_##er##_CLKGATE##es, \
138 .get_rate = name##_get_rate, \
139 .enable = _raw_clk_enable, \
140 .disable = _raw_clk_disable, \
141 .parent = &pll_clk, \
142 }
143
144_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC, CPU);
145_DEFINE_CLOCK_REF(ref_emi_clk, FRAC, EMI);
146_DEFINE_CLOCK_REF(ref_pix_clk, FRAC, PIX);
147_DEFINE_CLOCK_REF(ref_io_clk, FRAC, IO);
148
149/*
150 * General clocks
151 *
152 * clk_get_rate
153 */
154static unsigned long rtc_clk_get_rate(struct clk *clk)
155{
156 /* ref_xtal_clk is implemented as the only parent */
157 return clk_get_rate(clk->parent) / 768;
158}
159
160static unsigned long clk32k_clk_get_rate(struct clk *clk)
161{
162 return clk->parent->get_rate(clk->parent) / 750;
163}
164
165#define _CLK_GET_RATE(name, rs) \
166static unsigned long name##_get_rate(struct clk *clk) \
167{ \
168 u32 reg, div; \
169 \
170 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
171 \
172 if (clk->parent == &ref_xtal_clk) \
173 div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \
174 BP_CLKCTRL_##rs##_DIV_XTAL; \
175 else \
176 div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \
177 BP_CLKCTRL_##rs##_DIV_##rs; \
178 \
179 if (!div) \
180 return -EINVAL; \
181 \
182 return clk_get_rate(clk->parent) / div; \
183}
184
185_CLK_GET_RATE(cpu_clk, CPU)
186_CLK_GET_RATE(emi_clk, EMI)
187
188#define _CLK_GET_RATE1(name, rs) \
189static unsigned long name##_get_rate(struct clk *clk) \
190{ \
191 u32 reg, div; \
192 \
193 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
194 div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \
195 \
196 if (!div) \
197 return -EINVAL; \
198 \
199 return clk_get_rate(clk->parent) / div; \
200}
201
202_CLK_GET_RATE1(hbus_clk, HBUS)
203_CLK_GET_RATE1(xbus_clk, XBUS)
204_CLK_GET_RATE1(ssp_clk, SSP)
205_CLK_GET_RATE1(gpmi_clk, GPMI)
206_CLK_GET_RATE1(lcdif_clk, PIX)
207
208#define _CLK_GET_RATE_STUB(name) \
209static unsigned long name##_get_rate(struct clk *clk) \
210{ \
211 return clk_get_rate(clk->parent); \
212}
213
214_CLK_GET_RATE_STUB(uart_clk)
215_CLK_GET_RATE_STUB(audio_clk)
216_CLK_GET_RATE_STUB(pwm_clk)
217
218/*
219 * clk_set_rate
220 */
221static int cpu_clk_set_rate(struct clk *clk, unsigned long rate)
222{
223 u32 reg, bm_busy, div_max, d, f, div, frac;
224 unsigned long diff, parent_rate, calc_rate;
225 int i;
226
227 parent_rate = clk_get_rate(clk->parent);
228
229 if (clk->parent == &ref_xtal_clk) {
230 div_max = BM_CLKCTRL_CPU_DIV_XTAL >> BP_CLKCTRL_CPU_DIV_XTAL;
231 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL;
232 div = DIV_ROUND_UP(parent_rate, rate);
233 if (div == 0 || div > div_max)
234 return -EINVAL;
235 } else {
236 div_max = BM_CLKCTRL_CPU_DIV_CPU >> BP_CLKCTRL_CPU_DIV_CPU;
237 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU;
238 rate >>= PARENT_RATE_SHIFT;
239 parent_rate >>= PARENT_RATE_SHIFT;
240 diff = parent_rate;
241 div = frac = 1;
242 for (d = 1; d <= div_max; d++) {
243 f = parent_rate * 18 / d / rate;
244 if ((parent_rate * 18 / d) % rate)
245 f++;
246 if (f < 18 || f > 35)
247 continue;
248
249 calc_rate = parent_rate * 18 / f / d;
250 if (calc_rate > rate)
251 continue;
252
253 if (rate - calc_rate < diff) {
254 frac = f;
255 div = d;
256 diff = rate - calc_rate;
257 }
258
259 if (diff == 0)
260 break;
261 }
262
263 if (diff == parent_rate)
264 return -EINVAL;
265
266 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
267 reg &= ~BM_CLKCTRL_FRAC_CPUFRAC;
268 reg |= frac;
269 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
270 }
271
272 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
273 reg &= ~BM_CLKCTRL_CPU_DIV_CPU;
274 reg |= div << BP_CLKCTRL_CPU_DIV_CPU;
275 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
276
277 for (i = 10000; i; i--)
278 if (!(__raw_readl(CLKCTRL_BASE_ADDR +
279 HW_CLKCTRL_CPU) & bm_busy))
280 break;
281 if (!i) {
282 pr_err("%s: divider writing timeout\n", __func__);
283 return -ETIMEDOUT;
284 }
285
286 return 0;
287}
288
289#define _CLK_SET_RATE(name, dr) \
290static int name##_set_rate(struct clk *clk, unsigned long rate) \
291{ \
292 u32 reg, div_max, div; \
293 unsigned long parent_rate; \
294 int i; \
295 \
296 parent_rate = clk_get_rate(clk->parent); \
297 div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
298 \
299 div = DIV_ROUND_UP(parent_rate, rate); \
300 if (div == 0 || div > div_max) \
301 return -EINVAL; \
302 \
303 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
304 reg &= ~BM_CLKCTRL_##dr##_DIV; \
305 reg |= div << BP_CLKCTRL_##dr##_DIV; \
306 if (reg | (1 << clk->enable_shift)) { \
307 pr_err("%s: clock is gated\n", __func__); \
308 return -EINVAL; \
309 } \
310 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
311 \
312 for (i = 10000; i; i--) \
313 if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
314 HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY)) \
315 break; \
316 if (!i) { \
317 pr_err("%s: divider writing timeout\n", __func__); \
318 return -ETIMEDOUT; \
319 } \
320 \
321 return 0; \
322}
323
324_CLK_SET_RATE(xbus_clk, XBUS)
325_CLK_SET_RATE(ssp_clk, SSP)
326_CLK_SET_RATE(gpmi_clk, GPMI)
327_CLK_SET_RATE(lcdif_clk, PIX)
328
329#define _CLK_SET_RATE_STUB(name) \
330static int name##_set_rate(struct clk *clk, unsigned long rate) \
331{ \
332 return -EINVAL; \
333}
334
335_CLK_SET_RATE_STUB(emi_clk)
336_CLK_SET_RATE_STUB(uart_clk)
337_CLK_SET_RATE_STUB(audio_clk)
338_CLK_SET_RATE_STUB(pwm_clk)
339_CLK_SET_RATE_STUB(clk32k_clk)
340
341/*
342 * clk_set_parent
343 */
344#define _CLK_SET_PARENT(name, bit) \
345static int name##_set_parent(struct clk *clk, struct clk *parent) \
346{ \
347 if (parent != clk->parent) { \
348 __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
349 HW_CLKCTRL_CLKSEQ_TOG); \
350 clk->parent = parent; \
351 } \
352 \
353 return 0; \
354}
355
356_CLK_SET_PARENT(cpu_clk, CPU)
357_CLK_SET_PARENT(emi_clk, EMI)
358_CLK_SET_PARENT(ssp_clk, SSP)
359_CLK_SET_PARENT(gpmi_clk, GPMI)
360_CLK_SET_PARENT(lcdif_clk, PIX)
361
362#define _CLK_SET_PARENT_STUB(name) \
363static int name##_set_parent(struct clk *clk, struct clk *parent) \
364{ \
365 if (parent != clk->parent) \
366 return -EINVAL; \
367 else \
368 return 0; \
369}
370
371_CLK_SET_PARENT_STUB(uart_clk)
372_CLK_SET_PARENT_STUB(audio_clk)
373_CLK_SET_PARENT_STUB(pwm_clk)
374_CLK_SET_PARENT_STUB(clk32k_clk)
375
376/*
377 * clk definition
378 */
379static struct clk cpu_clk = {
380 .get_rate = cpu_clk_get_rate,
381 .set_rate = cpu_clk_set_rate,
382 .set_parent = cpu_clk_set_parent,
383 .parent = &ref_cpu_clk,
384};
385
386static struct clk hbus_clk = {
387 .get_rate = hbus_clk_get_rate,
388 .parent = &cpu_clk,
389};
390
391static struct clk xbus_clk = {
392 .get_rate = xbus_clk_get_rate,
393 .set_rate = xbus_clk_set_rate,
394 .parent = &ref_xtal_clk,
395};
396
397static struct clk rtc_clk = {
398 .get_rate = rtc_clk_get_rate,
399 .parent = &ref_xtal_clk,
400};
401
402/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
403static struct clk usb_clk = {
404 .enable_reg = DIGCTRL_BASE_ADDR,
405 .enable_shift = 2,
406 .enable = _raw_clk_enable,
407 .disable = _raw_clk_disable,
408 .parent = &pll_clk,
409};
410
411#define _DEFINE_CLOCK(name, er, es, p) \
412 static struct clk name = { \
413 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
414 .enable_shift = BP_CLKCTRL_##er##_##es, \
415 .get_rate = name##_get_rate, \
416 .set_rate = name##_set_rate, \
417 .set_parent = name##_set_parent, \
418 .enable = _raw_clk_enable, \
419 .disable = _raw_clk_disable, \
420 .parent = p, \
421 }
422
423_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
424_DEFINE_CLOCK(ssp_clk, SSP, CLKGATE, &ref_xtal_clk);
425_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
426_DEFINE_CLOCK(lcdif_clk, PIX, CLKGATE, &ref_xtal_clk);
427_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
428_DEFINE_CLOCK(audio_clk, XTAL, FILT_CLK24M_GATE, &ref_xtal_clk);
429_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
430_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
431
432#define _REGISTER_CLOCK(d, n, c) \
433 { \
434 .dev_id = d, \
435 .con_id = n, \
436 .clk = &c, \
437 },
438
439static struct clk_lookup lookups[] = {
440 _REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk)
441 _REGISTER_CLOCK("rtc", NULL, rtc_clk)
442 _REGISTER_CLOCK(NULL, "hclk", hbus_clk)
443 _REGISTER_CLOCK(NULL, "xclk", xbus_clk)
444 _REGISTER_CLOCK(NULL, "usb", usb_clk)
445 _REGISTER_CLOCK(NULL, "audio", audio_clk)
446 _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
447};
448
449static int clk_misc_init(void)
450{
451 u32 reg;
452 int i;
453
454 /* Fix up parent per register setting */
455 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
456 cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
457 &ref_xtal_clk : &ref_cpu_clk;
458 emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
459 &ref_xtal_clk : &ref_emi_clk;
460 ssp_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP) ?
461 &ref_xtal_clk : &ref_io_clk;
462 gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
463 &ref_xtal_clk : &ref_io_clk;
464 lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_PIX) ?
465 &ref_xtal_clk : &ref_pix_clk;
466
467 /* Use int div over frac when both are available */
468 __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
469 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
470 __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
471 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
472 __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
473 CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
474
475 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
476 reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
477 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
478
479 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
480 reg &= ~BM_CLKCTRL_SSP_DIV_FRAC_EN;
481 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
482
483 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
484 reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
485 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
486
487 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
488 reg &= ~BM_CLKCTRL_PIX_DIV_FRAC_EN;
489 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
490
491 /*
492 * Set safe hbus clock divider. A divider of 3 ensure that
493 * the Vddd voltage required for the cpu clock is sufficiently
494 * high for the hbus clock.
495 */
496 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
497 reg &= BM_CLKCTRL_HBUS_DIV;
498 reg |= 3 << BP_CLKCTRL_HBUS_DIV;
499 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
500
501 for (i = 10000; i; i--)
502 if (!(__raw_readl(CLKCTRL_BASE_ADDR +
503 HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_BUSY))
504 break;
505 if (!i) {
506 pr_err("%s: divider writing timeout\n", __func__);
507 return -ETIMEDOUT;
508 }
509
510 /* Gate off cpu clock in WFI for power saving */
511 __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
512 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
513
514 return 0;
515}
516
517int __init mx23_clocks_init(void)
518{
519 clk_misc_init();
520
521 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
522
523 mxs_timer_init(&clk32k_clk, MX23_INT_TIMER0);
524
525 return 0;
526}
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
new file mode 100644
index 000000000000..74e2103c6011
--- /dev/null
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -0,0 +1,734 @@
1/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/mm.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23#include <linux/jiffies.h>
24
25#include <asm/clkdev.h>
26#include <asm/div64.h>
27
28#include <mach/mx28.h>
29#include <mach/common.h>
30#include <mach/clock.h>
31
32#include "regs-clkctrl-mx28.h"
33
34#define CLKCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
35#define DIGCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
36
37#define PARENT_RATE_SHIFT 8
38
39static struct clk pll2_clk;
40static struct clk cpu_clk;
41static struct clk emi_clk;
42static struct clk saif0_clk;
43static struct clk saif1_clk;
44static struct clk clk32k_clk;
45
46static int _raw_clk_enable(struct clk *clk)
47{
48 u32 reg;
49
50 if (clk->enable_reg) {
51 reg = __raw_readl(clk->enable_reg);
52 reg &= ~(1 << clk->enable_shift);
53 __raw_writel(reg, clk->enable_reg);
54 }
55
56 return 0;
57}
58
59static void _raw_clk_disable(struct clk *clk)
60{
61 u32 reg;
62
63 if (clk->enable_reg) {
64 reg = __raw_readl(clk->enable_reg);
65 reg |= 1 << clk->enable_shift;
66 __raw_writel(reg, clk->enable_reg);
67 }
68}
69
70/*
71 * ref_xtal_clk
72 */
73static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
74{
75 return 24000000;
76}
77
78static struct clk ref_xtal_clk = {
79 .get_rate = ref_xtal_clk_get_rate,
80};
81
82/*
83 * pll_clk
84 */
85static unsigned long pll0_clk_get_rate(struct clk *clk)
86{
87 return 480000000;
88}
89
90static unsigned long pll1_clk_get_rate(struct clk *clk)
91{
92 return 480000000;
93}
94
95static unsigned long pll2_clk_get_rate(struct clk *clk)
96{
97 return 50000000;
98}
99
100#define _CLK_ENABLE_PLL(name, r, g) \
101static int name##_enable(struct clk *clk) \
102{ \
103 __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \
104 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
105 udelay(10); \
106 \
107 if (clk == &pll2_clk) \
108 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
109 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
110 else \
111 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
112 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
113 \
114 return 0; \
115}
116
117_CLK_ENABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
118_CLK_ENABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
119_CLK_ENABLE_PLL(pll2_clk, PLL2, CLKGATE)
120
121#define _CLK_DISABLE_PLL(name, r, g) \
122static void name##_disable(struct clk *clk) \
123{ \
124 __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \
125 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
126 \
127 if (clk == &pll2_clk) \
128 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
129 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
130 else \
131 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
132 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
133 \
134}
135
136_CLK_DISABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
137_CLK_DISABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
138_CLK_DISABLE_PLL(pll2_clk, PLL2, CLKGATE)
139
140#define _DEFINE_CLOCK_PLL(name) \
141 static struct clk name = { \
142 .get_rate = name##_get_rate, \
143 .enable = name##_enable, \
144 .disable = name##_disable, \
145 .parent = &ref_xtal_clk, \
146 }
147
148_DEFINE_CLOCK_PLL(pll0_clk);
149_DEFINE_CLOCK_PLL(pll1_clk);
150_DEFINE_CLOCK_PLL(pll2_clk);
151
152/*
153 * ref_clk
154 */
155#define _CLK_GET_RATE_REF(name, sr, ss) \
156static unsigned long name##_get_rate(struct clk *clk) \
157{ \
158 unsigned long parent_rate; \
159 u32 reg, div; \
160 \
161 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \
162 div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \
163 parent_rate = clk_get_rate(clk->parent); \
164 \
165 return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18, \
166 div, PARENT_RATE_SHIFT); \
167}
168
169_CLK_GET_RATE_REF(ref_cpu_clk, FRAC0, CPU)
170_CLK_GET_RATE_REF(ref_emi_clk, FRAC0, EMI)
171_CLK_GET_RATE_REF(ref_io0_clk, FRAC0, IO0)
172_CLK_GET_RATE_REF(ref_io1_clk, FRAC0, IO1)
173_CLK_GET_RATE_REF(ref_pix_clk, FRAC1, PIX)
174_CLK_GET_RATE_REF(ref_gpmi_clk, FRAC1, GPMI)
175
176#define _DEFINE_CLOCK_REF(name, er, es) \
177 static struct clk name = { \
178 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
179 .enable_shift = BP_CLKCTRL_##er##_CLKGATE##es, \
180 .get_rate = name##_get_rate, \
181 .enable = _raw_clk_enable, \
182 .disable = _raw_clk_disable, \
183 .parent = &pll0_clk, \
184 }
185
186_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC0, CPU);
187_DEFINE_CLOCK_REF(ref_emi_clk, FRAC0, EMI);
188_DEFINE_CLOCK_REF(ref_io0_clk, FRAC0, IO0);
189_DEFINE_CLOCK_REF(ref_io1_clk, FRAC0, IO1);
190_DEFINE_CLOCK_REF(ref_pix_clk, FRAC1, PIX);
191_DEFINE_CLOCK_REF(ref_gpmi_clk, FRAC1, GPMI);
192
193/*
194 * General clocks
195 *
196 * clk_get_rate
197 */
198static unsigned long lradc_clk_get_rate(struct clk *clk)
199{
200 return clk_get_rate(clk->parent) / 16;
201}
202
203static unsigned long rtc_clk_get_rate(struct clk *clk)
204{
205 /* ref_xtal_clk is implemented as the only parent */
206 return clk_get_rate(clk->parent) / 768;
207}
208
209static unsigned long clk32k_clk_get_rate(struct clk *clk)
210{
211 return clk->parent->get_rate(clk->parent) / 750;
212}
213
214static unsigned long spdif_clk_get_rate(struct clk *clk)
215{
216 return clk_get_rate(clk->parent) / 4;
217}
218
219#define _CLK_GET_RATE(name, rs) \
220static unsigned long name##_get_rate(struct clk *clk) \
221{ \
222 u32 reg, div; \
223 \
224 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
225 \
226 if (clk->parent == &ref_xtal_clk) \
227 div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \
228 BP_CLKCTRL_##rs##_DIV_XTAL; \
229 else \
230 div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \
231 BP_CLKCTRL_##rs##_DIV_##rs; \
232 \
233 if (!div) \
234 return -EINVAL; \
235 \
236 return clk_get_rate(clk->parent) / div; \
237}
238
239_CLK_GET_RATE(cpu_clk, CPU)
240_CLK_GET_RATE(emi_clk, EMI)
241
242#define _CLK_GET_RATE1(name, rs) \
243static unsigned long name##_get_rate(struct clk *clk) \
244{ \
245 u32 reg, div; \
246 \
247 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
248 div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \
249 \
250 if (!div) \
251 return -EINVAL; \
252 \
253 if (clk == &saif0_clk || clk == &saif1_clk) \
254 return clk_get_rate(clk->parent) >> 16 * div; \
255 else \
256 return clk_get_rate(clk->parent) / div; \
257}
258
259_CLK_GET_RATE1(hbus_clk, HBUS)
260_CLK_GET_RATE1(xbus_clk, XBUS)
261_CLK_GET_RATE1(ssp0_clk, SSP0)
262_CLK_GET_RATE1(ssp1_clk, SSP1)
263_CLK_GET_RATE1(ssp2_clk, SSP2)
264_CLK_GET_RATE1(ssp3_clk, SSP3)
265_CLK_GET_RATE1(gpmi_clk, GPMI)
266_CLK_GET_RATE1(lcdif_clk, DIS_LCDIF)
267_CLK_GET_RATE1(saif0_clk, SAIF0)
268_CLK_GET_RATE1(saif1_clk, SAIF1)
269
270#define _CLK_GET_RATE_STUB(name) \
271static unsigned long name##_get_rate(struct clk *clk) \
272{ \
273 return clk_get_rate(clk->parent); \
274}
275
276_CLK_GET_RATE_STUB(uart_clk)
277_CLK_GET_RATE_STUB(pwm_clk)
278_CLK_GET_RATE_STUB(can0_clk)
279_CLK_GET_RATE_STUB(can1_clk)
280_CLK_GET_RATE_STUB(fec_clk)
281
282/*
283 * clk_set_rate
284 */
285/* fool compiler */
286#define BM_CLKCTRL_CPU_DIV 0
287#define BP_CLKCTRL_CPU_DIV 0
288#define BM_CLKCTRL_CPU_BUSY 0
289
290#define _CLK_SET_RATE(name, dr, fr, fs) \
291static int name##_set_rate(struct clk *clk, unsigned long rate) \
292{ \
293 u32 reg, bm_busy, div_max, d, f, div, frac; \
294 unsigned long diff, parent_rate, calc_rate; \
295 int i; \
296 \
297 parent_rate = clk_get_rate(clk->parent); \
298 div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
299 bm_busy = BM_CLKCTRL_##dr##_BUSY; \
300 \
301 if (clk->parent == &ref_xtal_clk) { \
302 div = DIV_ROUND_UP(parent_rate, rate); \
303 if (clk == &cpu_clk) { \
304 div_max = BM_CLKCTRL_CPU_DIV_XTAL >> \
305 BP_CLKCTRL_CPU_DIV_XTAL; \
306 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL; \
307 } \
308 if (div == 0 || div > div_max) \
309 return -EINVAL; \
310 } else { \
311 rate >>= PARENT_RATE_SHIFT; \
312 parent_rate >>= PARENT_RATE_SHIFT; \
313 diff = parent_rate; \
314 div = frac = 1; \
315 if (clk == &cpu_clk) { \
316 div_max = BM_CLKCTRL_CPU_DIV_CPU >> \
317 BP_CLKCTRL_CPU_DIV_CPU; \
318 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU; \
319 } \
320 for (d = 1; d <= div_max; d++) { \
321 f = parent_rate * 18 / d / rate; \
322 if ((parent_rate * 18 / d) % rate) \
323 f++; \
324 if (f < 18 || f > 35) \
325 continue; \
326 \
327 calc_rate = parent_rate * 18 / f / d; \
328 if (calc_rate > rate) \
329 continue; \
330 \
331 if (rate - calc_rate < diff) { \
332 frac = f; \
333 div = d; \
334 diff = rate - calc_rate; \
335 } \
336 \
337 if (diff == 0) \
338 break; \
339 } \
340 \
341 if (diff == parent_rate) \
342 return -EINVAL; \
343 \
344 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
345 reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC; \
346 reg |= frac; \
347 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
348 } \
349 \
350 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
351 if (clk == &cpu_clk) { \
352 reg &= ~BM_CLKCTRL_CPU_DIV_CPU; \
353 reg |= div << BP_CLKCTRL_CPU_DIV_CPU; \
354 } else { \
355 reg &= ~BM_CLKCTRL_##dr##_DIV; \
356 reg |= div << BP_CLKCTRL_##dr##_DIV; \
357 if (reg | (1 << clk->enable_shift)) { \
358 pr_err("%s: clock is gated\n", __func__); \
359 return -EINVAL; \
360 } \
361 } \
362 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); \
363 \
364 for (i = 10000; i; i--) \
365 if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
366 HW_CLKCTRL_##dr) & bm_busy)) \
367 break; \
368 if (!i) { \
369 pr_err("%s: divider writing timeout\n", __func__); \
370 return -ETIMEDOUT; \
371 } \
372 \
373 return 0; \
374}
375
376_CLK_SET_RATE(cpu_clk, CPU, FRAC0, CPU)
377_CLK_SET_RATE(ssp0_clk, SSP0, FRAC0, IO0)
378_CLK_SET_RATE(ssp1_clk, SSP1, FRAC0, IO0)
379_CLK_SET_RATE(ssp2_clk, SSP2, FRAC0, IO1)
380_CLK_SET_RATE(ssp3_clk, SSP3, FRAC0, IO1)
381_CLK_SET_RATE(lcdif_clk, DIS_LCDIF, FRAC1, PIX)
382_CLK_SET_RATE(gpmi_clk, GPMI, FRAC1, GPMI)
383
384#define _CLK_SET_RATE1(name, dr) \
385static int name##_set_rate(struct clk *clk, unsigned long rate) \
386{ \
387 u32 reg, div_max, div; \
388 unsigned long parent_rate; \
389 int i; \
390 \
391 parent_rate = clk_get_rate(clk->parent); \
392 div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
393 \
394 div = DIV_ROUND_UP(parent_rate, rate); \
395 if (div == 0 || div > div_max) \
396 return -EINVAL; \
397 \
398 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
399 reg &= ~BM_CLKCTRL_##dr##_DIV; \
400 reg |= div << BP_CLKCTRL_##dr##_DIV; \
401 if (reg | (1 << clk->enable_shift)) { \
402 pr_err("%s: clock is gated\n", __func__); \
403 return -EINVAL; \
404 } \
405 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
406 \
407 for (i = 10000; i; i--) \
408 if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
409 HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY)) \
410 break; \
411 if (!i) { \
412 pr_err("%s: divider writing timeout\n", __func__); \
413 return -ETIMEDOUT; \
414 } \
415 \
416 return 0; \
417}
418
419_CLK_SET_RATE1(xbus_clk, XBUS)
420
421/* saif clock uses 16 bits frac div */
422#define _CLK_SET_RATE_SAIF(name, rs) \
423static int name##_set_rate(struct clk *clk, unsigned long rate) \
424{ \
425 u16 div; \
426 u32 reg; \
427 u64 lrate; \
428 unsigned long parent_rate; \
429 int i; \
430 \
431 parent_rate = clk_get_rate(clk->parent); \
432 if (rate > parent_rate) \
433 return -EINVAL; \
434 \
435 lrate = (u64)rate << 16; \
436 do_div(lrate, parent_rate); \
437 div = (u16)lrate; \
438 \
439 if (!div) \
440 return -EINVAL; \
441 \
442 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
443 reg &= ~BM_CLKCTRL_##rs##_DIV; \
444 reg |= div << BP_CLKCTRL_##rs##_DIV; \
445 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
446 \
447 for (i = 10000; i; i--) \
448 if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
449 HW_CLKCTRL_##rs) & BM_CLKCTRL_##rs##_BUSY)) \
450 break; \
451 if (!i) { \
452 pr_err("%s: divider writing timeout\n", __func__); \
453 return -ETIMEDOUT; \
454 } \
455 \
456 return 0; \
457}
458
459_CLK_SET_RATE_SAIF(saif0_clk, SAIF0)
460_CLK_SET_RATE_SAIF(saif1_clk, SAIF1)
461
462#define _CLK_SET_RATE_STUB(name) \
463static int name##_set_rate(struct clk *clk, unsigned long rate) \
464{ \
465 return -EINVAL; \
466}
467
468_CLK_SET_RATE_STUB(emi_clk)
469_CLK_SET_RATE_STUB(uart_clk)
470_CLK_SET_RATE_STUB(pwm_clk)
471_CLK_SET_RATE_STUB(spdif_clk)
472_CLK_SET_RATE_STUB(clk32k_clk)
473_CLK_SET_RATE_STUB(can0_clk)
474_CLK_SET_RATE_STUB(can1_clk)
475_CLK_SET_RATE_STUB(fec_clk)
476
477/*
478 * clk_set_parent
479 */
480#define _CLK_SET_PARENT(name, bit) \
481static int name##_set_parent(struct clk *clk, struct clk *parent) \
482{ \
483 if (parent != clk->parent) { \
484 __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
485 HW_CLKCTRL_CLKSEQ_TOG); \
486 clk->parent = parent; \
487 } \
488 \
489 return 0; \
490}
491
492_CLK_SET_PARENT(cpu_clk, CPU)
493_CLK_SET_PARENT(emi_clk, EMI)
494_CLK_SET_PARENT(ssp0_clk, SSP0)
495_CLK_SET_PARENT(ssp1_clk, SSP1)
496_CLK_SET_PARENT(ssp2_clk, SSP2)
497_CLK_SET_PARENT(ssp3_clk, SSP3)
498_CLK_SET_PARENT(lcdif_clk, DIS_LCDIF)
499_CLK_SET_PARENT(gpmi_clk, GPMI)
500_CLK_SET_PARENT(saif0_clk, SAIF0)
501_CLK_SET_PARENT(saif1_clk, SAIF1)
502
503#define _CLK_SET_PARENT_STUB(name) \
504static int name##_set_parent(struct clk *clk, struct clk *parent) \
505{ \
506 if (parent != clk->parent) \
507 return -EINVAL; \
508 else \
509 return 0; \
510}
511
512_CLK_SET_PARENT_STUB(pwm_clk)
513_CLK_SET_PARENT_STUB(uart_clk)
514_CLK_SET_PARENT_STUB(clk32k_clk)
515_CLK_SET_PARENT_STUB(spdif_clk)
516_CLK_SET_PARENT_STUB(fec_clk)
517_CLK_SET_PARENT_STUB(can0_clk)
518_CLK_SET_PARENT_STUB(can1_clk)
519
520/*
521 * clk definition
522 */
523static struct clk cpu_clk = {
524 .get_rate = cpu_clk_get_rate,
525 .set_rate = cpu_clk_set_rate,
526 .set_parent = cpu_clk_set_parent,
527 .parent = &ref_cpu_clk,
528};
529
530static struct clk hbus_clk = {
531 .get_rate = hbus_clk_get_rate,
532 .parent = &cpu_clk,
533};
534
535static struct clk xbus_clk = {
536 .get_rate = xbus_clk_get_rate,
537 .set_rate = xbus_clk_set_rate,
538 .parent = &ref_xtal_clk,
539};
540
541static struct clk lradc_clk = {
542 .get_rate = lradc_clk_get_rate,
543 .parent = &clk32k_clk,
544};
545
546static struct clk rtc_clk = {
547 .get_rate = rtc_clk_get_rate,
548 .parent = &ref_xtal_clk,
549};
550
551/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
552static struct clk usb0_clk = {
553 .enable_reg = DIGCTRL_BASE_ADDR,
554 .enable_shift = 2,
555 .enable = _raw_clk_enable,
556 .disable = _raw_clk_disable,
557 .parent = &pll0_clk,
558};
559
560static struct clk usb1_clk = {
561 .enable_reg = DIGCTRL_BASE_ADDR,
562 .enable_shift = 16,
563 .enable = _raw_clk_enable,
564 .disable = _raw_clk_disable,
565 .parent = &pll1_clk,
566};
567
568#define _DEFINE_CLOCK(name, er, es, p) \
569 static struct clk name = { \
570 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
571 .enable_shift = BP_CLKCTRL_##er##_##es, \
572 .get_rate = name##_get_rate, \
573 .set_rate = name##_set_rate, \
574 .set_parent = name##_set_parent, \
575 .enable = _raw_clk_enable, \
576 .disable = _raw_clk_disable, \
577 .parent = p, \
578 }
579
580_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
581_DEFINE_CLOCK(ssp0_clk, SSP0, CLKGATE, &ref_xtal_clk);
582_DEFINE_CLOCK(ssp1_clk, SSP1, CLKGATE, &ref_xtal_clk);
583_DEFINE_CLOCK(ssp2_clk, SSP2, CLKGATE, &ref_xtal_clk);
584_DEFINE_CLOCK(ssp3_clk, SSP3, CLKGATE, &ref_xtal_clk);
585_DEFINE_CLOCK(lcdif_clk, DIS_LCDIF, CLKGATE, &ref_xtal_clk);
586_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
587_DEFINE_CLOCK(saif0_clk, SAIF0, CLKGATE, &ref_xtal_clk);
588_DEFINE_CLOCK(saif1_clk, SAIF1, CLKGATE, &ref_xtal_clk);
589_DEFINE_CLOCK(can0_clk, FLEXCAN, STOP_CAN0, &ref_xtal_clk);
590_DEFINE_CLOCK(can1_clk, FLEXCAN, STOP_CAN1, &ref_xtal_clk);
591_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
592_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
593_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
594_DEFINE_CLOCK(spdif_clk, SPDIF, CLKGATE, &pll0_clk);
595_DEFINE_CLOCK(fec_clk, ENET, DISABLE, &hbus_clk);
596
597#define _REGISTER_CLOCK(d, n, c) \
598 { \
599 .dev_id = d, \
600 .con_id = n, \
601 .clk = &c, \
602 },
603
604static struct clk_lookup lookups[] = {
605 _REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk)
606 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
607 _REGISTER_CLOCK("rtc", NULL, rtc_clk)
608 _REGISTER_CLOCK("pll2", NULL, pll2_clk)
609 _REGISTER_CLOCK(NULL, "hclk", hbus_clk)
610 _REGISTER_CLOCK(NULL, "xclk", xbus_clk)
611 _REGISTER_CLOCK(NULL, "can0", can0_clk)
612 _REGISTER_CLOCK(NULL, "can1", can1_clk)
613 _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
614 _REGISTER_CLOCK(NULL, "usb1", usb1_clk)
615 _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
616 _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
617 _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
618};
619
620static int clk_misc_init(void)
621{
622 u32 reg;
623 int i;
624
625 /* Fix up parent per register setting */
626 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
627 cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
628 &ref_xtal_clk : &ref_cpu_clk;
629 emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
630 &ref_xtal_clk : &ref_emi_clk;
631 ssp0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) ?
632 &ref_xtal_clk : &ref_io0_clk;
633 ssp1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP1) ?
634 &ref_xtal_clk : &ref_io0_clk;
635 ssp2_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP2) ?
636 &ref_xtal_clk : &ref_io1_clk;
637 ssp3_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP3) ?
638 &ref_xtal_clk : &ref_io1_clk;
639 lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF) ?
640 &ref_xtal_clk : &ref_pix_clk;
641 gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
642 &ref_xtal_clk : &ref_gpmi_clk;
643 saif0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0) ?
644 &ref_xtal_clk : &pll0_clk;
645 saif1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1) ?
646 &ref_xtal_clk : &pll0_clk;
647
648 /* Use int div over frac when both are available */
649 __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
650 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
651 __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
652 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
653 __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
654 CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
655
656 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
657 reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
658 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
659
660 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
661 reg &= ~BM_CLKCTRL_SSP0_DIV_FRAC_EN;
662 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
663
664 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
665 reg &= ~BM_CLKCTRL_SSP1_DIV_FRAC_EN;
666 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
667
668 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
669 reg &= ~BM_CLKCTRL_SSP2_DIV_FRAC_EN;
670 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
671
672 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
673 reg &= ~BM_CLKCTRL_SSP3_DIV_FRAC_EN;
674 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
675
676 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
677 reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
678 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
679
680 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
681 reg &= ~BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN;
682 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
683
684 /* SAIF has to use frac div for functional operation */
685 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
686 reg &= ~BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
687 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
688
689 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
690 reg &= ~BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
691 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
692
693 /*
694 * Set safe hbus clock divider. A divider of 3 ensure that
695 * the Vddd voltage required for the cpu clock is sufficiently
696 * high for the hbus clock.
697 */
698 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
699 reg &= BM_CLKCTRL_HBUS_DIV;
700 reg |= 3 << BP_CLKCTRL_HBUS_DIV;
701 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
702
703 for (i = 10000; i; i--)
704 if (!(__raw_readl(CLKCTRL_BASE_ADDR +
705 HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_ASM_BUSY))
706 break;
707 if (!i) {
708 pr_err("%s: divider writing timeout\n", __func__);
709 return -ETIMEDOUT;
710 }
711
712 /* Gate off cpu clock in WFI for power saving */
713 __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
714 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
715
716 /* Extra fec clock setting */
717 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
718 reg &= ~BM_CLKCTRL_ENET_SLEEP;
719 reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
720 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
721
722 return 0;
723}
724
725int __init mx28_clocks_init(void)
726{
727 clk_misc_init();
728
729 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
730
731 mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
732
733 return 0;
734}
diff --git a/arch/arm/mach-mxs/clock.c b/arch/arm/mach-mxs/clock.c
new file mode 100644
index 000000000000..e7d2269cf70e
--- /dev/null
+++ b/arch/arm/mach-mxs/clock.c
@@ -0,0 +1,200 @@
1/*
2 * Based on arch/arm/plat-omap/clock.c
3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
7 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
8 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301, USA.
23 */
24
25/* #define DEBUG */
26
27#include <linux/clk.h>
28#include <linux/err.h>
29#include <linux/errno.h>
30#include <linux/init.h>
31#include <linux/io.h>
32#include <linux/kernel.h>
33#include <linux/list.h>
34#include <linux/module.h>
35#include <linux/mutex.h>
36#include <linux/platform_device.h>
37#include <linux/proc_fs.h>
38#include <linux/semaphore.h>
39#include <linux/string.h>
40
41#include <mach/clock.h>
42
43static LIST_HEAD(clocks);
44static DEFINE_MUTEX(clocks_mutex);
45
46/*-------------------------------------------------------------------------
47 * Standard clock functions defined in include/linux/clk.h
48 *-------------------------------------------------------------------------*/
49
50static void __clk_disable(struct clk *clk)
51{
52 if (clk == NULL || IS_ERR(clk))
53 return;
54 WARN_ON(!clk->usecount);
55
56 if (!(--clk->usecount)) {
57 if (clk->disable)
58 clk->disable(clk);
59 __clk_disable(clk->parent);
60 __clk_disable(clk->secondary);
61 }
62}
63
64static int __clk_enable(struct clk *clk)
65{
66 if (clk == NULL || IS_ERR(clk))
67 return -EINVAL;
68
69 if (clk->usecount++ == 0) {
70 __clk_enable(clk->parent);
71 __clk_enable(clk->secondary);
72
73 if (clk->enable)
74 clk->enable(clk);
75 }
76 return 0;
77}
78
79/* This function increments the reference count on the clock and enables the
80 * clock if not already enabled. The parent clock tree is recursively enabled
81 */
82int clk_enable(struct clk *clk)
83{
84 int ret = 0;
85
86 if (clk == NULL || IS_ERR(clk))
87 return -EINVAL;
88
89 mutex_lock(&clocks_mutex);
90 ret = __clk_enable(clk);
91 mutex_unlock(&clocks_mutex);
92
93 return ret;
94}
95EXPORT_SYMBOL(clk_enable);
96
97/* This function decrements the reference count on the clock and disables
98 * the clock when reference count is 0. The parent clock tree is
99 * recursively disabled
100 */
101void clk_disable(struct clk *clk)
102{
103 if (clk == NULL || IS_ERR(clk))
104 return;
105
106 mutex_lock(&clocks_mutex);
107 __clk_disable(clk);
108 mutex_unlock(&clocks_mutex);
109}
110EXPORT_SYMBOL(clk_disable);
111
112/* Retrieve the *current* clock rate. If the clock itself
113 * does not provide a special calculation routine, ask
114 * its parent and so on, until one is able to return
115 * a valid clock rate
116 */
117unsigned long clk_get_rate(struct clk *clk)
118{
119 if (clk == NULL || IS_ERR(clk))
120 return 0UL;
121
122 if (clk->get_rate)
123 return clk->get_rate(clk);
124
125 return clk_get_rate(clk->parent);
126}
127EXPORT_SYMBOL(clk_get_rate);
128
129/* Round the requested clock rate to the nearest supported
130 * rate that is less than or equal to the requested rate.
131 * This is dependent on the clock's current parent.
132 */
133long clk_round_rate(struct clk *clk, unsigned long rate)
134{
135 if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
136 return 0;
137
138 return clk->round_rate(clk, rate);
139}
140EXPORT_SYMBOL(clk_round_rate);
141
142/* Set the clock to the requested clock rate. The rate must
143 * match a supported rate exactly based on what clk_round_rate returns
144 */
145int clk_set_rate(struct clk *clk, unsigned long rate)
146{
147 int ret = -EINVAL;
148
149 if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
150 return ret;
151
152 mutex_lock(&clocks_mutex);
153 ret = clk->set_rate(clk, rate);
154 mutex_unlock(&clocks_mutex);
155
156 return ret;
157}
158EXPORT_SYMBOL(clk_set_rate);
159
160/* Set the clock's parent to another clock source */
161int clk_set_parent(struct clk *clk, struct clk *parent)
162{
163 int ret = -EINVAL;
164 struct clk *old;
165
166 if (clk == NULL || IS_ERR(clk) || parent == NULL ||
167 IS_ERR(parent) || clk->set_parent == NULL)
168 return ret;
169
170 if (clk->usecount)
171 clk_enable(parent);
172
173 mutex_lock(&clocks_mutex);
174 ret = clk->set_parent(clk, parent);
175 if (ret == 0) {
176 old = clk->parent;
177 clk->parent = parent;
178 } else {
179 old = parent;
180 }
181 mutex_unlock(&clocks_mutex);
182
183 if (clk->usecount)
184 clk_disable(old);
185
186 return ret;
187}
188EXPORT_SYMBOL(clk_set_parent);
189
190/* Retrieve the clock's parent clock source */
191struct clk *clk_get_parent(struct clk *clk)
192{
193 struct clk *ret = NULL;
194
195 if (clk == NULL || IS_ERR(clk))
196 return ret;
197
198 return clk->parent;
199}
200EXPORT_SYMBOL(clk_get_parent);
diff --git a/arch/arm/mach-mxs/include/mach/clkdev.h b/arch/arm/mach-mxs/include/mach/clkdev.h
new file mode 100644
index 000000000000..3a8f2e3a6309
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_MXS_CLKDEV_H__
2#define __MACH_MXS_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do { } while (0)
6
7#endif
diff --git a/arch/arm/mach-mxs/include/mach/clock.h b/arch/arm/mach-mxs/include/mach/clock.h
new file mode 100644
index 000000000000..041e276d8a32
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/clock.h
@@ -0,0 +1,64 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __MACH_MXS_CLOCK_H__
21#define __MACH_MXS_CLOCK_H__
22
23#ifndef __ASSEMBLY__
24#include <linux/list.h>
25
26struct module;
27
28struct clk {
29 int id;
30 /* Source clock this clk depends on */
31 struct clk *parent;
32 /* Secondary clock to enable/disable with this clock */
33 struct clk *secondary;
34 /* Reference count of clock enable/disable */
35 __s8 usecount;
36 /* Register bit position for clock's enable/disable control. */
37 u8 enable_shift;
38 /* Register address for clock's enable/disable control. */
39 void __iomem *enable_reg;
40 u32 flags;
41 /* get the current clock rate (always a fresh value) */
42 unsigned long (*get_rate) (struct clk *);
43 /* Function ptr to set the clock to a new rate. The rate must match a
44 supported rate returned from round_rate. Leave blank if clock is not
45 programmable */
46 int (*set_rate) (struct clk *, unsigned long);
47 /* Function ptr to round the requested clock rate to the nearest
48 supported rate that is less than or equal to the requested rate. */
49 unsigned long (*round_rate) (struct clk *, unsigned long);
50 /* Function ptr to enable the clock. Leave blank if clock can not
51 be gated. */
52 int (*enable) (struct clk *);
53 /* Function ptr to disable the clock. Leave blank if clock can not
54 be gated. */
55 void (*disable) (struct clk *);
56 /* Function ptr to set the parent clock of the clock. */
57 int (*set_parent) (struct clk *, struct clk *);
58};
59
60int clk_register(struct clk *clk);
61void clk_unregister(struct clk *clk);
62
63#endif /* __ASSEMBLY__ */
64#endif /* __MACH_MXS_CLOCK_H__ */
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx23.h b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
new file mode 100644
index 000000000000..dbc04747b691
--- /dev/null
+++ b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
@@ -0,0 +1,455 @@
1/*
2 * Freescale CLKCTRL Register Definitions
3 *
4 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
5 * Copyright 2008-2010 Freescale Semiconductor, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 * This file is created by xml file. Don't Edit it.
22 *
23 * Xml Revision: 1.48
24 * Template revision: 26195
25 */
26
27#ifndef __REGS_CLKCTRL_MX23_H__
28#define __REGS_CLKCTRL_MX23_H__
29
30
31#define HW_CLKCTRL_PLLCTRL0 (0x00000000)
32#define HW_CLKCTRL_PLLCTRL0_SET (0x00000004)
33#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008)
34#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c)
35
36#define BP_CLKCTRL_PLLCTRL0_RSRVD6 30
37#define BM_CLKCTRL_PLLCTRL0_RSRVD6 0xC0000000
38#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) \
39 (((v) << 30) & BM_CLKCTRL_PLLCTRL0_RSRVD6)
40#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28
41#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000
42#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \
43 (((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL)
44#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0
45#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1
46#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2
47#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
48#define BP_CLKCTRL_PLLCTRL0_RSRVD5 26
49#define BM_CLKCTRL_PLLCTRL0_RSRVD5 0x0C000000
50#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v) \
51 (((v) << 26) & BM_CLKCTRL_PLLCTRL0_RSRVD5)
52#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24
53#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000
54#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \
55 (((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL)
56#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0
57#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1
58#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2
59#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
60#define BP_CLKCTRL_PLLCTRL0_RSRVD4 22
61#define BM_CLKCTRL_PLLCTRL0_RSRVD4 0x00C00000
62#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v) \
63 (((v) << 22) & BM_CLKCTRL_PLLCTRL0_RSRVD4)
64#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20
65#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000
66#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \
67 (((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL)
68#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0
69#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1
70#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2
71#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
72#define BM_CLKCTRL_PLLCTRL0_RSRVD3 0x00080000
73#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
74#define BM_CLKCTRL_PLLCTRL0_RSRVD2 0x00020000
75#define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000
76#define BP_CLKCTRL_PLLCTRL0_RSRVD1 0
77#define BM_CLKCTRL_PLLCTRL0_RSRVD1 0x0000FFFF
78#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v) \
79 (((v) << 0) & BM_CLKCTRL_PLLCTRL0_RSRVD1)
80
81#define HW_CLKCTRL_PLLCTRL1 (0x00000010)
82
83#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000
84#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000
85#define BP_CLKCTRL_PLLCTRL1_RSRVD1 16
86#define BM_CLKCTRL_PLLCTRL1_RSRVD1 0x3FFF0000
87#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v) \
88 (((v) << 16) & BM_CLKCTRL_PLLCTRL1_RSRVD1)
89#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0
90#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF
91#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \
92 (((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT)
93
94#define HW_CLKCTRL_CPU (0x00000020)
95#define HW_CLKCTRL_CPU_SET (0x00000024)
96#define HW_CLKCTRL_CPU_CLR (0x00000028)
97#define HW_CLKCTRL_CPU_TOG (0x0000002c)
98
99#define BP_CLKCTRL_CPU_RSRVD5 30
100#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000
101#define BF_CLKCTRL_CPU_RSRVD5(v) \
102 (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
103#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
104#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
105#define BM_CLKCTRL_CPU_RSRVD4 0x08000000
106#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
107#define BP_CLKCTRL_CPU_DIV_XTAL 16
108#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
109#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
110 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
111#define BP_CLKCTRL_CPU_RSRVD3 13
112#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000
113#define BF_CLKCTRL_CPU_RSRVD3(v) \
114 (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
115#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
116#define BM_CLKCTRL_CPU_RSRVD2 0x00000800
117#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
118#define BP_CLKCTRL_CPU_RSRVD1 6
119#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0
120#define BF_CLKCTRL_CPU_RSRVD1(v) \
121 (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
122#define BP_CLKCTRL_CPU_DIV_CPU 0
123#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
124#define BF_CLKCTRL_CPU_DIV_CPU(v) \
125 (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
126
127#define HW_CLKCTRL_HBUS (0x00000030)
128#define HW_CLKCTRL_HBUS_SET (0x00000034)
129#define HW_CLKCTRL_HBUS_CLR (0x00000038)
130#define HW_CLKCTRL_HBUS_TOG (0x0000003c)
131
132#define BP_CLKCTRL_HBUS_RSRVD4 30
133#define BM_CLKCTRL_HBUS_RSRVD4 0xC0000000
134#define BF_CLKCTRL_HBUS_RSRVD4(v) \
135 (((v) << 30) & BM_CLKCTRL_HBUS_RSRVD4)
136#define BM_CLKCTRL_HBUS_BUSY 0x20000000
137#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000
138#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000
139#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000
140#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000
141#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000
142#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000
143#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000
144#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000
145#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000
146#define BM_CLKCTRL_HBUS_RSRVD2 0x00080000
147#define BP_CLKCTRL_HBUS_SLOW_DIV 16
148#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000
149#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \
150 (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
151#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0
152#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1
153#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2
154#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
155#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
156#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
157#define BP_CLKCTRL_HBUS_RSRVD1 6
158#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0
159#define BF_CLKCTRL_HBUS_RSRVD1(v) \
160 (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
161#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
162#define BP_CLKCTRL_HBUS_DIV 0
163#define BM_CLKCTRL_HBUS_DIV 0x0000001F
164#define BF_CLKCTRL_HBUS_DIV(v) \
165 (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
166
167#define HW_CLKCTRL_XBUS (0x00000040)
168
169#define BM_CLKCTRL_XBUS_BUSY 0x80000000
170#define BP_CLKCTRL_XBUS_RSRVD1 11
171#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF800
172#define BF_CLKCTRL_XBUS_RSRVD1(v) \
173 (((v) << 11) & BM_CLKCTRL_XBUS_RSRVD1)
174#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
175#define BP_CLKCTRL_XBUS_DIV 0
176#define BM_CLKCTRL_XBUS_DIV 0x000003FF
177#define BF_CLKCTRL_XBUS_DIV(v) \
178 (((v) << 0) & BM_CLKCTRL_XBUS_DIV)
179
180#define HW_CLKCTRL_XTAL (0x00000050)
181#define HW_CLKCTRL_XTAL_SET (0x00000054)
182#define HW_CLKCTRL_XTAL_CLR (0x00000058)
183#define HW_CLKCTRL_XTAL_TOG (0x0000005c)
184
185#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31
186#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000
187#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE 30
188#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000
189#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
190#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
191#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
192#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000
193#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26
194#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
195#define BP_CLKCTRL_XTAL_RSRVD1 2
196#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC
197#define BF_CLKCTRL_XTAL_RSRVD1(v) \
198 (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
199#define BP_CLKCTRL_XTAL_DIV_UART 0
200#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
201#define BF_CLKCTRL_XTAL_DIV_UART(v) \
202 (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
203
204#define HW_CLKCTRL_PIX (0x00000060)
205
206#define BP_CLKCTRL_PIX_CLKGATE 31
207#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
208#define BM_CLKCTRL_PIX_RSRVD2 0x40000000
209#define BM_CLKCTRL_PIX_BUSY 0x20000000
210#define BP_CLKCTRL_PIX_RSRVD1 13
211#define BM_CLKCTRL_PIX_RSRVD1 0x1FFFE000
212#define BF_CLKCTRL_PIX_RSRVD1(v) \
213 (((v) << 13) & BM_CLKCTRL_PIX_RSRVD1)
214#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000
215#define BP_CLKCTRL_PIX_DIV 0
216#define BM_CLKCTRL_PIX_DIV 0x00000FFF
217#define BF_CLKCTRL_PIX_DIV(v) \
218 (((v) << 0) & BM_CLKCTRL_PIX_DIV)
219
220#define HW_CLKCTRL_SSP (0x00000070)
221
222#define BP_CLKCTRL_SSP_CLKGATE 31
223#define BM_CLKCTRL_SSP_CLKGATE 0x80000000
224#define BM_CLKCTRL_SSP_RSRVD2 0x40000000
225#define BM_CLKCTRL_SSP_BUSY 0x20000000
226#define BP_CLKCTRL_SSP_RSRVD1 10
227#define BM_CLKCTRL_SSP_RSRVD1 0x1FFFFC00
228#define BF_CLKCTRL_SSP_RSRVD1(v) \
229 (((v) << 10) & BM_CLKCTRL_SSP_RSRVD1)
230#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200
231#define BP_CLKCTRL_SSP_DIV 0
232#define BM_CLKCTRL_SSP_DIV 0x000001FF
233#define BF_CLKCTRL_SSP_DIV(v) \
234 (((v) << 0) & BM_CLKCTRL_SSP_DIV)
235
236#define HW_CLKCTRL_GPMI (0x00000080)
237
238#define BP_CLKCTRL_GPMI_CLKGATE 31
239#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
240#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000
241#define BM_CLKCTRL_GPMI_BUSY 0x20000000
242#define BP_CLKCTRL_GPMI_RSRVD1 11
243#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800
244#define BF_CLKCTRL_GPMI_RSRVD1(v) \
245 (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
246#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
247#define BP_CLKCTRL_GPMI_DIV 0
248#define BM_CLKCTRL_GPMI_DIV 0x000003FF
249#define BF_CLKCTRL_GPMI_DIV(v) \
250 (((v) << 0) & BM_CLKCTRL_GPMI_DIV)
251
252#define HW_CLKCTRL_SPDIF (0x00000090)
253
254#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
255#define BP_CLKCTRL_SPDIF_RSRVD 0
256#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF
257#define BF_CLKCTRL_SPDIF_RSRVD(v) \
258 (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
259
260#define HW_CLKCTRL_EMI (0x000000a0)
261
262#define BP_CLKCTRL_EMI_CLKGATE 31
263#define BM_CLKCTRL_EMI_CLKGATE 0x80000000
264#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000
265#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
266#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
267#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
268#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
269#define BP_CLKCTRL_EMI_RSRVD3 18
270#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000
271#define BF_CLKCTRL_EMI_RSRVD3(v) \
272 (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
273#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
274#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
275#define BP_CLKCTRL_EMI_RSRVD2 12
276#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000
277#define BF_CLKCTRL_EMI_RSRVD2(v) \
278 (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
279#define BP_CLKCTRL_EMI_DIV_XTAL 8
280#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
281#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
282 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
283#define BP_CLKCTRL_EMI_RSRVD1 6
284#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0
285#define BF_CLKCTRL_EMI_RSRVD1(v) \
286 (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
287#define BP_CLKCTRL_EMI_DIV_EMI 0
288#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
289#define BF_CLKCTRL_EMI_DIV_EMI(v) \
290 (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
291
292#define HW_CLKCTRL_IR (0x000000b0)
293
294#define BM_CLKCTRL_IR_CLKGATE 0x80000000
295#define BM_CLKCTRL_IR_RSRVD3 0x40000000
296#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000
297#define BM_CLKCTRL_IR_IR_BUSY 0x10000000
298#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000
299#define BP_CLKCTRL_IR_RSRVD2 25
300#define BM_CLKCTRL_IR_RSRVD2 0x06000000
301#define BF_CLKCTRL_IR_RSRVD2(v) \
302 (((v) << 25) & BM_CLKCTRL_IR_RSRVD2)
303#define BP_CLKCTRL_IR_IROV_DIV 16
304#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000
305#define BF_CLKCTRL_IR_IROV_DIV(v) \
306 (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV)
307#define BP_CLKCTRL_IR_RSRVD1 10
308#define BM_CLKCTRL_IR_RSRVD1 0x0000FC00
309#define BF_CLKCTRL_IR_RSRVD1(v) \
310 (((v) << 10) & BM_CLKCTRL_IR_RSRVD1)
311#define BP_CLKCTRL_IR_IR_DIV 0
312#define BM_CLKCTRL_IR_IR_DIV 0x000003FF
313#define BF_CLKCTRL_IR_IR_DIV(v) \
314 (((v) << 0) & BM_CLKCTRL_IR_IR_DIV)
315
316#define HW_CLKCTRL_SAIF (0x000000c0)
317
318#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000
319#define BM_CLKCTRL_SAIF_RSRVD2 0x40000000
320#define BM_CLKCTRL_SAIF_BUSY 0x20000000
321#define BP_CLKCTRL_SAIF_RSRVD1 17
322#define BM_CLKCTRL_SAIF_RSRVD1 0x1FFE0000
323#define BF_CLKCTRL_SAIF_RSRVD1(v) \
324 (((v) << 17) & BM_CLKCTRL_SAIF_RSRVD1)
325#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000
326#define BP_CLKCTRL_SAIF_DIV 0
327#define BM_CLKCTRL_SAIF_DIV 0x0000FFFF
328#define BF_CLKCTRL_SAIF_DIV(v) \
329 (((v) << 0) & BM_CLKCTRL_SAIF_DIV)
330
331#define HW_CLKCTRL_TV (0x000000d0)
332
333#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000
334#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000
335#define BP_CLKCTRL_TV_RSRVD 0
336#define BM_CLKCTRL_TV_RSRVD 0x3FFFFFFF
337#define BF_CLKCTRL_TV_RSRVD(v) \
338 (((v) << 0) & BM_CLKCTRL_TV_RSRVD)
339
340#define HW_CLKCTRL_ETM (0x000000e0)
341
342#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
343#define BM_CLKCTRL_ETM_RSRVD2 0x40000000
344#define BM_CLKCTRL_ETM_BUSY 0x20000000
345#define BP_CLKCTRL_ETM_RSRVD1 7
346#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF80
347#define BF_CLKCTRL_ETM_RSRVD1(v) \
348 (((v) << 7) & BM_CLKCTRL_ETM_RSRVD1)
349#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040
350#define BP_CLKCTRL_ETM_DIV 0
351#define BM_CLKCTRL_ETM_DIV 0x0000003F
352#define BF_CLKCTRL_ETM_DIV(v) \
353 (((v) << 0) & BM_CLKCTRL_ETM_DIV)
354
355#define HW_CLKCTRL_FRAC (0x000000f0)
356#define HW_CLKCTRL_FRAC_SET (0x000000f4)
357#define HW_CLKCTRL_FRAC_CLR (0x000000f8)
358#define HW_CLKCTRL_FRAC_TOG (0x000000fc)
359
360#define BP_CLKCTRL_FRAC_CLKGATEIO 31
361#define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000
362#define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000
363#define BP_CLKCTRL_FRAC_IOFRAC 24
364#define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000
365#define BF_CLKCTRL_FRAC_IOFRAC(v) \
366 (((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC)
367#define BP_CLKCTRL_FRAC_CLKGATEPIX 23
368#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
369#define BM_CLKCTRL_FRAC_PIX_STABLE 0x00400000
370#define BP_CLKCTRL_FRAC_PIXFRAC 16
371#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
372#define BF_CLKCTRL_FRAC_PIXFRAC(v) \
373 (((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC)
374#define BP_CLKCTRL_FRAC_CLKGATEEMI 15
375#define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000
376#define BM_CLKCTRL_FRAC_EMI_STABLE 0x00004000
377#define BP_CLKCTRL_FRAC_EMIFRAC 8
378#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
379#define BF_CLKCTRL_FRAC_EMIFRAC(v) \
380 (((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC)
381#define BP_CLKCTRL_FRAC_CLKGATECPU 7
382#define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080
383#define BM_CLKCTRL_FRAC_CPU_STABLE 0x00000040
384#define BP_CLKCTRL_FRAC_CPUFRAC 0
385#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F
386#define BF_CLKCTRL_FRAC_CPUFRAC(v) \
387 (((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC)
388
389#define HW_CLKCTRL_FRAC1 (0x00000100)
390#define HW_CLKCTRL_FRAC1_SET (0x00000104)
391#define HW_CLKCTRL_FRAC1_CLR (0x00000108)
392#define HW_CLKCTRL_FRAC1_TOG (0x0000010c)
393
394#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000
395#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000
396#define BP_CLKCTRL_FRAC1_RSRVD1 0
397#define BM_CLKCTRL_FRAC1_RSRVD1 0x3FFFFFFF
398#define BF_CLKCTRL_FRAC1_RSRVD1(v) \
399 (((v) << 0) & BM_CLKCTRL_FRAC1_RSRVD1)
400
401#define HW_CLKCTRL_CLKSEQ (0x00000110)
402#define HW_CLKCTRL_CLKSEQ_SET (0x00000114)
403#define HW_CLKCTRL_CLKSEQ_CLR (0x00000118)
404#define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c)
405
406#define BP_CLKCTRL_CLKSEQ_RSRVD1 9
407#define BM_CLKCTRL_CLKSEQ_RSRVD1 0xFFFFFE00
408#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
409 (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD1)
410#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
411#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080
412#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040
413#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020
414#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010
415#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008
416#define BM_CLKCTRL_CLKSEQ_RSRVD0 0x00000004
417#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
418#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001
419
420#define HW_CLKCTRL_RESET (0x00000120)
421
422#define BP_CLKCTRL_RESET_RSRVD 2
423#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFFC
424#define BF_CLKCTRL_RESET_RSRVD(v) \
425 (((v) << 2) & BM_CLKCTRL_RESET_RSRVD)
426#define BM_CLKCTRL_RESET_CHIP 0x00000002
427#define BM_CLKCTRL_RESET_DIG 0x00000001
428
429#define HW_CLKCTRL_STATUS (0x00000130)
430
431#define BP_CLKCTRL_STATUS_CPU_LIMIT 30
432#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
433#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
434 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
435#define BP_CLKCTRL_STATUS_RSRVD 0
436#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
437#define BF_CLKCTRL_STATUS_RSRVD(v) \
438 (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
439
440#define HW_CLKCTRL_VERSION (0x00000140)
441
442#define BP_CLKCTRL_VERSION_MAJOR 24
443#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000
444#define BF_CLKCTRL_VERSION_MAJOR(v) \
445 (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
446#define BP_CLKCTRL_VERSION_MINOR 16
447#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000
448#define BF_CLKCTRL_VERSION_MINOR(v) \
449 (((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
450#define BP_CLKCTRL_VERSION_STEP 0
451#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
452#define BF_CLKCTRL_VERSION_STEP(v) \
453 (((v) << 0) & BM_CLKCTRL_VERSION_STEP)
454
455#endif /* __REGS_CLKCTRL_MX23_H__ */
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx28.h b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
new file mode 100644
index 000000000000..661df18755f7
--- /dev/null
+++ b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
@@ -0,0 +1,663 @@
1/*
2 * Freescale CLKCTRL Register Definitions
3 *
4 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * This file is created by xml file. Don't Edit it.
21 *
22 * Xml Revision: 1.48
23 * Template revision: 26195
24 */
25
26#ifndef __REGS_CLKCTRL_MX28_H__
27#define __REGS_CLKCTRL_MX28_H__
28
29#define HW_CLKCTRL_PLL0CTRL0 (0x00000000)
30#define HW_CLKCTRL_PLL0CTRL0_SET (0x00000004)
31#define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008)
32#define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c)
33
34#define BP_CLKCTRL_PLL0CTRL0_RSRVD6 30
35#define BM_CLKCTRL_PLL0CTRL0_RSRVD6 0xC0000000
36#define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \
37 (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6)
38#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28
39#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000
40#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \
41 (((v) << 28) & BM_CLKCTRL_PLL0CTRL0_LFR_SEL)
42#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__DEFAULT 0x0
43#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1
44#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2
45#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3
46#define BP_CLKCTRL_PLL0CTRL0_RSRVD5 26
47#define BM_CLKCTRL_PLL0CTRL0_RSRVD5 0x0C000000
48#define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v) \
49 (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5)
50#define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24
51#define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000
52#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \
53 (((v) << 24) & BM_CLKCTRL_PLL0CTRL0_CP_SEL)
54#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__DEFAULT 0x0
55#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1
56#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2
57#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3
58#define BP_CLKCTRL_PLL0CTRL0_RSRVD4 22
59#define BM_CLKCTRL_PLL0CTRL0_RSRVD4 0x00C00000
60#define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v) \
61 (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4)
62#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20
63#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000
64#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \
65 (((v) << 20) & BM_CLKCTRL_PLL0CTRL0_DIV_SEL)
66#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__DEFAULT 0x0
67#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1
68#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2
69#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3
70#define BM_CLKCTRL_PLL0CTRL0_RSRVD3 0x00080000
71#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000
72#define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000
73#define BP_CLKCTRL_PLL0CTRL0_RSRVD1 0
74#define BM_CLKCTRL_PLL0CTRL0_RSRVD1 0x0001FFFF
75#define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v) \
76 (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1)
77
78#define HW_CLKCTRL_PLL0CTRL1 (0x00000010)
79
80#define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000
81#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000
82#define BP_CLKCTRL_PLL0CTRL1_RSRVD1 16
83#define BM_CLKCTRL_PLL0CTRL1_RSRVD1 0x3FFF0000
84#define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v) \
85 (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1)
86#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0
87#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF
88#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \
89 (((v) << 0) & BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT)
90
91#define HW_CLKCTRL_PLL1CTRL0 (0x00000020)
92#define HW_CLKCTRL_PLL1CTRL0_SET (0x00000024)
93#define HW_CLKCTRL_PLL1CTRL0_CLR (0x00000028)
94#define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c)
95
96#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000
97#define BM_CLKCTRL_PLL1CTRL0_RSRVD6 0x40000000
98#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28
99#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000
100#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \
101 (((v) << 28) & BM_CLKCTRL_PLL1CTRL0_LFR_SEL)
102#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__DEFAULT 0x0
103#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1
104#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2
105#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3
106#define BP_CLKCTRL_PLL1CTRL0_RSRVD5 26
107#define BM_CLKCTRL_PLL1CTRL0_RSRVD5 0x0C000000
108#define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v) \
109 (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5)
110#define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24
111#define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000
112#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \
113 (((v) << 24) & BM_CLKCTRL_PLL1CTRL0_CP_SEL)
114#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__DEFAULT 0x0
115#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1
116#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2
117#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3
118#define BP_CLKCTRL_PLL1CTRL0_RSRVD4 22
119#define BM_CLKCTRL_PLL1CTRL0_RSRVD4 0x00C00000
120#define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v) \
121 (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4)
122#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20
123#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000
124#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \
125 (((v) << 20) & BM_CLKCTRL_PLL1CTRL0_DIV_SEL)
126#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__DEFAULT 0x0
127#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1
128#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2
129#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3
130#define BM_CLKCTRL_PLL1CTRL0_RSRVD3 0x00080000
131#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000
132#define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000
133#define BP_CLKCTRL_PLL1CTRL0_RSRVD1 0
134#define BM_CLKCTRL_PLL1CTRL0_RSRVD1 0x0001FFFF
135#define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v) \
136 (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1)
137
138#define HW_CLKCTRL_PLL1CTRL1 (0x00000030)
139
140#define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000
141#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000
142#define BP_CLKCTRL_PLL1CTRL1_RSRVD1 16
143#define BM_CLKCTRL_PLL1CTRL1_RSRVD1 0x3FFF0000
144#define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v) \
145 (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1)
146#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0
147#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF
148#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \
149 (((v) << 0) & BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT)
150
151#define HW_CLKCTRL_PLL2CTRL0 (0x00000040)
152#define HW_CLKCTRL_PLL2CTRL0_SET (0x00000044)
153#define HW_CLKCTRL_PLL2CTRL0_CLR (0x00000048)
154#define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c)
155
156#define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000
157#define BM_CLKCTRL_PLL2CTRL0_RSRVD3 0x40000000
158#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28
159#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000
160#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \
161 (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL)
162#define BM_CLKCTRL_PLL2CTRL0_RSRVD2 0x08000000
163#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000
164#define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24
165#define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000
166#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \
167 (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL)
168#define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000
169#define BP_CLKCTRL_PLL2CTRL0_RSRVD1 0
170#define BM_CLKCTRL_PLL2CTRL0_RSRVD1 0x007FFFFF
171#define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v) \
172 (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1)
173
174#define HW_CLKCTRL_CPU (0x00000050)
175#define HW_CLKCTRL_CPU_SET (0x00000054)
176#define HW_CLKCTRL_CPU_CLR (0x00000058)
177#define HW_CLKCTRL_CPU_TOG (0x0000005c)
178
179#define BP_CLKCTRL_CPU_RSRVD5 30
180#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000
181#define BF_CLKCTRL_CPU_RSRVD5(v) \
182 (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
183#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
184#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
185#define BM_CLKCTRL_CPU_RSRVD4 0x08000000
186#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
187#define BP_CLKCTRL_CPU_DIV_XTAL 16
188#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
189#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
190 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
191#define BP_CLKCTRL_CPU_RSRVD3 13
192#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000
193#define BF_CLKCTRL_CPU_RSRVD3(v) \
194 (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
195#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
196#define BM_CLKCTRL_CPU_RSRVD2 0x00000800
197#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
198#define BP_CLKCTRL_CPU_RSRVD1 6
199#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0
200#define BF_CLKCTRL_CPU_RSRVD1(v) \
201 (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
202#define BP_CLKCTRL_CPU_DIV_CPU 0
203#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
204#define BF_CLKCTRL_CPU_DIV_CPU(v) \
205 (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
206
207#define HW_CLKCTRL_HBUS (0x00000060)
208#define HW_CLKCTRL_HBUS_SET (0x00000064)
209#define HW_CLKCTRL_HBUS_CLR (0x00000068)
210#define HW_CLKCTRL_HBUS_TOG (0x0000006c)
211
212#define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000
213#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000
214#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000
215#define BM_CLKCTRL_HBUS_RSRVD2 0x10000000
216#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000
217#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000
218#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000
219#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000
220#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000
221#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000
222#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000
223#define BM_CLKCTRL_HBUS_ASM_ENABLE 0x00100000
224#define BM_CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE 0x00080000
225#define BP_CLKCTRL_HBUS_SLOW_DIV 16
226#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000
227#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \
228 (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
229#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0
230#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1
231#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2
232#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
233#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
234#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
235#define BP_CLKCTRL_HBUS_RSRVD1 6
236#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0
237#define BF_CLKCTRL_HBUS_RSRVD1(v) \
238 (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
239#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
240#define BP_CLKCTRL_HBUS_DIV 0
241#define BM_CLKCTRL_HBUS_DIV 0x0000001F
242#define BF_CLKCTRL_HBUS_DIV(v) \
243 (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
244
245#define HW_CLKCTRL_XBUS (0x00000070)
246
247#define BM_CLKCTRL_XBUS_BUSY 0x80000000
248#define BP_CLKCTRL_XBUS_RSRVD1 12
249#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF000
250#define BF_CLKCTRL_XBUS_RSRVD1(v) \
251 (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1)
252#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800
253#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
254#define BP_CLKCTRL_XBUS_DIV 0
255#define BM_CLKCTRL_XBUS_DIV 0x000003FF
256#define BF_CLKCTRL_XBUS_DIV(v) \
257 (((v) << 0) & BM_CLKCTRL_XBUS_DIV)
258
259#define HW_CLKCTRL_XTAL (0x00000080)
260#define HW_CLKCTRL_XTAL_SET (0x00000084)
261#define HW_CLKCTRL_XTAL_CLR (0x00000088)
262#define HW_CLKCTRL_XTAL_TOG (0x0000008c)
263
264#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31
265#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000
266#define BM_CLKCTRL_XTAL_RSRVD3 0x40000000
267#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
268#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
269#define BP_CLKCTRL_XTAL_RSRVD2 27
270#define BM_CLKCTRL_XTAL_RSRVD2 0x18000000
271#define BF_CLKCTRL_XTAL_RSRVD2(v) \
272 (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2)
273#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26
274#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
275#define BP_CLKCTRL_XTAL_RSRVD1 2
276#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC
277#define BF_CLKCTRL_XTAL_RSRVD1(v) \
278 (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
279#define BP_CLKCTRL_XTAL_DIV_UART 0
280#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
281#define BF_CLKCTRL_XTAL_DIV_UART(v) \
282 (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
283
284#define HW_CLKCTRL_SSP0 (0x00000090)
285
286#define BP_CLKCTRL_SSP0_CLKGATE 31
287#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000
288#define BM_CLKCTRL_SSP0_RSRVD2 0x40000000
289#define BM_CLKCTRL_SSP0_BUSY 0x20000000
290#define BP_CLKCTRL_SSP0_RSRVD1 10
291#define BM_CLKCTRL_SSP0_RSRVD1 0x1FFFFC00
292#define BF_CLKCTRL_SSP0_RSRVD1(v) \
293 (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1)
294#define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200
295#define BP_CLKCTRL_SSP0_DIV 0
296#define BM_CLKCTRL_SSP0_DIV 0x000001FF
297#define BF_CLKCTRL_SSP0_DIV(v) \
298 (((v) << 0) & BM_CLKCTRL_SSP0_DIV)
299
300#define HW_CLKCTRL_SSP1 (0x000000a0)
301
302#define BP_CLKCTRL_SSP1_CLKGATE 31
303#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000
304#define BM_CLKCTRL_SSP1_RSRVD2 0x40000000
305#define BM_CLKCTRL_SSP1_BUSY 0x20000000
306#define BP_CLKCTRL_SSP1_RSRVD1 10
307#define BM_CLKCTRL_SSP1_RSRVD1 0x1FFFFC00
308#define BF_CLKCTRL_SSP1_RSRVD1(v) \
309 (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1)
310#define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200
311#define BP_CLKCTRL_SSP1_DIV 0
312#define BM_CLKCTRL_SSP1_DIV 0x000001FF
313#define BF_CLKCTRL_SSP1_DIV(v) \
314 (((v) << 0) & BM_CLKCTRL_SSP1_DIV)
315
316#define HW_CLKCTRL_SSP2 (0x000000b0)
317
318#define BP_CLKCTRL_SSP2_CLKGATE 31
319#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000
320#define BM_CLKCTRL_SSP2_RSRVD2 0x40000000
321#define BM_CLKCTRL_SSP2_BUSY 0x20000000
322#define BP_CLKCTRL_SSP2_RSRVD1 10
323#define BM_CLKCTRL_SSP2_RSRVD1 0x1FFFFC00
324#define BF_CLKCTRL_SSP2_RSRVD1(v) \
325 (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1)
326#define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200
327#define BP_CLKCTRL_SSP2_DIV 0
328#define BM_CLKCTRL_SSP2_DIV 0x000001FF
329#define BF_CLKCTRL_SSP2_DIV(v) \
330 (((v) << 0) & BM_CLKCTRL_SSP2_DIV)
331
332#define HW_CLKCTRL_SSP3 (0x000000c0)
333
334#define BP_CLKCTRL_SSP3_CLKGATE 31
335#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000
336#define BM_CLKCTRL_SSP3_RSRVD2 0x40000000
337#define BM_CLKCTRL_SSP3_BUSY 0x20000000
338#define BP_CLKCTRL_SSP3_RSRVD1 10
339#define BM_CLKCTRL_SSP3_RSRVD1 0x1FFFFC00
340#define BF_CLKCTRL_SSP3_RSRVD1(v) \
341 (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1)
342#define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200
343#define BP_CLKCTRL_SSP3_DIV 0
344#define BM_CLKCTRL_SSP3_DIV 0x000001FF
345#define BF_CLKCTRL_SSP3_DIV(v) \
346 (((v) << 0) & BM_CLKCTRL_SSP3_DIV)
347
348#define HW_CLKCTRL_GPMI (0x000000d0)
349
350#define BP_CLKCTRL_GPMI_CLKGATE 31
351#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
352#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000
353#define BM_CLKCTRL_GPMI_BUSY 0x20000000
354#define BP_CLKCTRL_GPMI_RSRVD1 11
355#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800
356#define BF_CLKCTRL_GPMI_RSRVD1(v) \
357 (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
358#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
359#define BP_CLKCTRL_GPMI_DIV 0
360#define BM_CLKCTRL_GPMI_DIV 0x000003FF
361#define BF_CLKCTRL_GPMI_DIV(v) \
362 (((v) << 0) & BM_CLKCTRL_GPMI_DIV)
363
364#define HW_CLKCTRL_SPDIF (0x000000e0)
365
366#define BP_CLKCTRL_SPDIF_CLKGATE 31
367#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
368#define BP_CLKCTRL_SPDIF_RSRVD 0
369#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF
370#define BF_CLKCTRL_SPDIF_RSRVD(v) \
371 (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
372
373#define HW_CLKCTRL_EMI (0x000000f0)
374
375#define BP_CLKCTRL_EMI_CLKGATE 31
376#define BM_CLKCTRL_EMI_CLKGATE 0x80000000
377#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000
378#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
379#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
380#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
381#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
382#define BP_CLKCTRL_EMI_RSRVD3 18
383#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000
384#define BF_CLKCTRL_EMI_RSRVD3(v) \
385 (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
386#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
387#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
388#define BP_CLKCTRL_EMI_RSRVD2 12
389#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000
390#define BF_CLKCTRL_EMI_RSRVD2(v) \
391 (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
392#define BP_CLKCTRL_EMI_DIV_XTAL 8
393#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
394#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
395 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
396#define BP_CLKCTRL_EMI_RSRVD1 6
397#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0
398#define BF_CLKCTRL_EMI_RSRVD1(v) \
399 (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
400#define BP_CLKCTRL_EMI_DIV_EMI 0
401#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
402#define BF_CLKCTRL_EMI_DIV_EMI(v) \
403 (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
404
405#define HW_CLKCTRL_SAIF0 (0x00000100)
406
407#define BP_CLKCTRL_SAIF0_CLKGATE 31
408#define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000
409#define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000
410#define BM_CLKCTRL_SAIF0_BUSY 0x20000000
411#define BP_CLKCTRL_SAIF0_RSRVD1 17
412#define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000
413#define BF_CLKCTRL_SAIF0_RSRVD1(v) \
414 (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1)
415#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000
416#define BP_CLKCTRL_SAIF0_DIV 0
417#define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF
418#define BF_CLKCTRL_SAIF0_DIV(v) \
419 (((v) << 0) & BM_CLKCTRL_SAIF0_DIV)
420
421#define HW_CLKCTRL_SAIF1 (0x00000110)
422
423#define BP_CLKCTRL_SAIF1_CLKGATE 31
424#define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000
425#define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000
426#define BM_CLKCTRL_SAIF1_BUSY 0x20000000
427#define BP_CLKCTRL_SAIF1_RSRVD1 17
428#define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000
429#define BF_CLKCTRL_SAIF1_RSRVD1(v) \
430 (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1)
431#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000
432#define BP_CLKCTRL_SAIF1_DIV 0
433#define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF
434#define BF_CLKCTRL_SAIF1_DIV(v) \
435 (((v) << 0) & BM_CLKCTRL_SAIF1_DIV)
436
437#define HW_CLKCTRL_DIS_LCDIF (0x00000120)
438
439#define BP_CLKCTRL_DIS_LCDIF_CLKGATE 31
440#define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000
441#define BM_CLKCTRL_DIS_LCDIF_RSRVD2 0x40000000
442#define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000
443#define BP_CLKCTRL_DIS_LCDIF_RSRVD1 14
444#define BM_CLKCTRL_DIS_LCDIF_RSRVD1 0x1FFFC000
445#define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v) \
446 (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1)
447#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000
448#define BP_CLKCTRL_DIS_LCDIF_DIV 0
449#define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF
450#define BF_CLKCTRL_DIS_LCDIF_DIV(v) \
451 (((v) << 0) & BM_CLKCTRL_DIS_LCDIF_DIV)
452
453#define HW_CLKCTRL_ETM (0x00000130)
454
455#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
456#define BM_CLKCTRL_ETM_RSRVD2 0x40000000
457#define BM_CLKCTRL_ETM_BUSY 0x20000000
458#define BP_CLKCTRL_ETM_RSRVD1 8
459#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF00
460#define BF_CLKCTRL_ETM_RSRVD1(v) \
461 (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1)
462#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080
463#define BP_CLKCTRL_ETM_DIV 0
464#define BM_CLKCTRL_ETM_DIV 0x0000007F
465#define BF_CLKCTRL_ETM_DIV(v) \
466 (((v) << 0) & BM_CLKCTRL_ETM_DIV)
467
468#define HW_CLKCTRL_ENET (0x00000140)
469
470#define BM_CLKCTRL_ENET_SLEEP 0x80000000
471#define BP_CLKCTRL_ENET_DISABLE 30
472#define BM_CLKCTRL_ENET_DISABLE 0x40000000
473#define BM_CLKCTRL_ENET_STATUS 0x20000000
474#define BM_CLKCTRL_ENET_RSRVD1 0x10000000
475#define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000
476#define BP_CLKCTRL_ENET_DIV_TIME 21
477#define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000
478#define BF_CLKCTRL_ENET_DIV_TIME(v) \
479 (((v) << 21) & BM_CLKCTRL_ENET_DIV_TIME)
480#define BM_CLKCTRL_ENET_BUSY 0x08000000
481#define BP_CLKCTRL_ENET_DIV 21
482#define BM_CLKCTRL_ENET_DIV 0x07E00000
483#define BF_CLKCTRL_ENET_DIV(v) \
484 (((v) << 21) & BM_CLKCTRL_ENET_DIV)
485#define BP_CLKCTRL_ENET_TIME_SEL 19
486#define BM_CLKCTRL_ENET_TIME_SEL 0x00180000
487#define BF_CLKCTRL_ENET_TIME_SEL(v) \
488 (((v) << 19) & BM_CLKCTRL_ENET_TIME_SEL)
489#define BV_CLKCTRL_ENET_TIME_SEL__XTAL 0x0
490#define BV_CLKCTRL_ENET_TIME_SEL__PLL 0x1
491#define BV_CLKCTRL_ENET_TIME_SEL__RMII_CLK 0x2
492#define BV_CLKCTRL_ENET_TIME_SEL__UNDEFINED 0x3
493#define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000
494#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000
495#define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000
496#define BP_CLKCTRL_ENET_RSRVD0 0
497#define BM_CLKCTRL_ENET_RSRVD0 0x0000FFFF
498#define BF_CLKCTRL_ENET_RSRVD0(v) \
499 (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0)
500
501#define HW_CLKCTRL_HSADC (0x00000150)
502
503#define BM_CLKCTRL_HSADC_RSRVD2 0x80000000
504#define BM_CLKCTRL_HSADC_RESETB 0x40000000
505#define BP_CLKCTRL_HSADC_FREQDIV 28
506#define BM_CLKCTRL_HSADC_FREQDIV 0x30000000
507#define BF_CLKCTRL_HSADC_FREQDIV(v) \
508 (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV)
509#define BP_CLKCTRL_HSADC_RSRVD1 0
510#define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF
511#define BF_CLKCTRL_HSADC_RSRVD1(v) \
512 (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1)
513
514#define HW_CLKCTRL_FLEXCAN (0x00000160)
515
516#define BM_CLKCTRL_FLEXCAN_RSRVD2 0x80000000
517#define BP_CLKCTRL_FLEXCAN_STOP_CAN0 30
518#define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000
519#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000
520#define BP_CLKCTRL_FLEXCAN_STOP_CAN1 28
521#define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000
522#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000
523#define BP_CLKCTRL_FLEXCAN_RSRVD1 0
524#define BM_CLKCTRL_FLEXCAN_RSRVD1 0x07FFFFFF
525#define BF_CLKCTRL_FLEXCAN_RSRVD1(v) \
526 (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1)
527
528#define HW_CLKCTRL_FRAC0 (0x000001b0)
529#define HW_CLKCTRL_FRAC0_SET (0x000001b4)
530#define HW_CLKCTRL_FRAC0_CLR (0x000001b8)
531#define HW_CLKCTRL_FRAC0_TOG (0x000001bc)
532
533#define BP_CLKCTRL_FRAC0_CLKGATEIO0 31
534#define BM_CLKCTRL_FRAC0_CLKGATEIO0 0x80000000
535#define BM_CLKCTRL_FRAC0_IO0_STABLE 0x40000000
536#define BP_CLKCTRL_FRAC0_IO0FRAC 24
537#define BM_CLKCTRL_FRAC0_IO0FRAC 0x3F000000
538#define BF_CLKCTRL_FRAC0_IO0FRAC(v) \
539 (((v) << 24) & BM_CLKCTRL_FRAC0_IO0FRAC)
540#define BP_CLKCTRL_FRAC0_CLKGATEIO1 23
541#define BM_CLKCTRL_FRAC0_CLKGATEIO1 0x00800000
542#define BM_CLKCTRL_FRAC0_IO1_STABLE 0x00400000
543#define BP_CLKCTRL_FRAC0_IO1FRAC 16
544#define BM_CLKCTRL_FRAC0_IO1FRAC 0x003F0000
545#define BF_CLKCTRL_FRAC0_IO1FRAC(v) \
546 (((v) << 16) & BM_CLKCTRL_FRAC0_IO1FRAC)
547#define BP_CLKCTRL_FRAC0_CLKGATEEMI 15
548#define BM_CLKCTRL_FRAC0_CLKGATEEMI 0x00008000
549#define BM_CLKCTRL_FRAC0_EMI_STABLE 0x00004000
550#define BP_CLKCTRL_FRAC0_EMIFRAC 8
551#define BM_CLKCTRL_FRAC0_EMIFRAC 0x00003F00
552#define BF_CLKCTRL_FRAC0_EMIFRAC(v) \
553 (((v) << 8) & BM_CLKCTRL_FRAC0_EMIFRAC)
554#define BP_CLKCTRL_FRAC0_CLKGATECPU 7
555#define BM_CLKCTRL_FRAC0_CLKGATECPU 0x00000080
556#define BM_CLKCTRL_FRAC0_CPU_STABLE 0x00000040
557#define BP_CLKCTRL_FRAC0_CPUFRAC 0
558#define BM_CLKCTRL_FRAC0_CPUFRAC 0x0000003F
559#define BF_CLKCTRL_FRAC0_CPUFRAC(v) \
560 (((v) << 0) & BM_CLKCTRL_FRAC0_CPUFRAC)
561
562#define HW_CLKCTRL_FRAC1 (0x000001c0)
563#define HW_CLKCTRL_FRAC1_SET (0x000001c4)
564#define HW_CLKCTRL_FRAC1_CLR (0x000001c8)
565#define HW_CLKCTRL_FRAC1_TOG (0x000001cc)
566
567#define BP_CLKCTRL_FRAC1_RSRVD2 24
568#define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000
569#define BF_CLKCTRL_FRAC1_RSRVD2(v) \
570 (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2)
571#define BP_CLKCTRL_FRAC1_CLKGATEGPMI 23
572#define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000
573#define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000
574#define BP_CLKCTRL_FRAC1_GPMIFRAC 16
575#define BM_CLKCTRL_FRAC1_GPMIFRAC 0x003F0000
576#define BF_CLKCTRL_FRAC1_GPMIFRAC(v) \
577 (((v) << 16) & BM_CLKCTRL_FRAC1_GPMIFRAC)
578#define BP_CLKCTRL_FRAC1_CLKGATEHSADC 15
579#define BM_CLKCTRL_FRAC1_CLKGATEHSADC 0x00008000
580#define BM_CLKCTRL_FRAC1_HSADC_STABLE 0x00004000
581#define BP_CLKCTRL_FRAC1_HSADCFRAC 8
582#define BM_CLKCTRL_FRAC1_HSADCFRAC 0x00003F00
583#define BF_CLKCTRL_FRAC1_HSADCFRAC(v) \
584 (((v) << 8) & BM_CLKCTRL_FRAC1_HSADCFRAC)
585#define BP_CLKCTRL_FRAC1_CLKGATEPIX 7
586#define BM_CLKCTRL_FRAC1_CLKGATEPIX 0x00000080
587#define BM_CLKCTRL_FRAC1_PIX_STABLE 0x00000040
588#define BP_CLKCTRL_FRAC1_PIXFRAC 0
589#define BM_CLKCTRL_FRAC1_PIXFRAC 0x0000003F
590#define BF_CLKCTRL_FRAC1_PIXFRAC(v) \
591 (((v) << 0) & BM_CLKCTRL_FRAC1_PIXFRAC)
592
593#define HW_CLKCTRL_CLKSEQ (0x000001d0)
594#define HW_CLKCTRL_CLKSEQ_SET (0x000001d4)
595#define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8)
596#define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc)
597
598#define BP_CLKCTRL_CLKSEQ_RSRVD0 19
599#define BM_CLKCTRL_CLKSEQ_RSRVD0 0xFFF80000
600#define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \
601 (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0)
602#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000
603#define BP_CLKCTRL_CLKSEQ_RSRVD1 15
604#define BM_CLKCTRL_CLKSEQ_RSRVD1 0x00038000
605#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
606 (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1)
607#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000
608#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1
609#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0
610#define BP_CLKCTRL_CLKSEQ_RSRVD2 9
611#define BM_CLKCTRL_CLKSEQ_RSRVD2 0x00003E00
612#define BF_CLKCTRL_CLKSEQ_RSRVD2(v) \
613 (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2)
614#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
615#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080
616#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040
617#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP2 0x00000020
618#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP1 0x00000010
619#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP0 0x00000008
620#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000004
621#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1 0x00000002
622#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0 0x00000001
623
624#define HW_CLKCTRL_RESET (0x000001e0)
625
626#define BP_CLKCTRL_RESET_RSRVD 6
627#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFC0
628#define BF_CLKCTRL_RESET_RSRVD(v) \
629 (((v) << 6) & BM_CLKCTRL_RESET_RSRVD)
630#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020
631#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010
632#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008
633#define BM_CLKCTRL_RESET_THERMAL_RESET_DEFAULT 0x00000004
634#define BM_CLKCTRL_RESET_CHIP 0x00000002
635#define BM_CLKCTRL_RESET_DIG 0x00000001
636
637#define HW_CLKCTRL_STATUS (0x000001f0)
638
639#define BP_CLKCTRL_STATUS_CPU_LIMIT 30
640#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
641#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
642 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
643#define BP_CLKCTRL_STATUS_RSRVD 0
644#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
645#define BF_CLKCTRL_STATUS_RSRVD(v) \
646 (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
647
648#define HW_CLKCTRL_VERSION (0x00000200)
649
650#define BP_CLKCTRL_VERSION_MAJOR 24
651#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000
652#define BF_CLKCTRL_VERSION_MAJOR(v) \
653 (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
654#define BP_CLKCTRL_VERSION_MINOR 16
655#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000
656#define BF_CLKCTRL_VERSION_MINOR(v) \
657 (((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
658#define BP_CLKCTRL_VERSION_STEP 0
659#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
660#define BF_CLKCTRL_VERSION_STEP(v) \
661 (((v) << 0) & BM_CLKCTRL_VERSION_STEP)
662
663#endif /* __REGS_CLKCTRL_MX28_H__ */