aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm
diff options
context:
space:
mode:
authorDavid Woodhouse <David.Woodhouse@intel.com>2008-07-11 09:36:25 -0400
committerDavid Woodhouse <David.Woodhouse@intel.com>2008-07-11 09:36:25 -0400
commita8931ef380c92d121ae74ecfb03b2d63f72eea6f (patch)
tree980fb6b019e11e6cb1ece55b7faff184721a8053 /arch/arm
parent90574d0a4d4b73308ae54a2a57a4f3f1fa98e984 (diff)
parente5a5816f7875207cb0a0a7032e39a4686c5e10a4 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/compressed/head-xscale.S4
-rw-r--r--arch/arm/common/dmabounce.c3
-rw-r--r--arch/arm/common/locomo.c66
-rw-r--r--arch/arm/kernel/armksyms.c2
-rw-r--r--arch/arm/kernel/arthur.c2
-rw-r--r--arch/arm/kernel/init_task.c1
-rw-r--r--arch/arm/kernel/sys_arm.c17
-rw-r--r--arch/arm/mach-at91/at91sam9261_devices.c4
-rw-r--r--arch/arm/mach-at91/at91sam9rl_devices.c21
-rw-r--r--arch/arm/mach-at91/at91x40.c18
-rw-r--r--arch/arm/mach-ep93xx/core.c2
-rw-r--r--arch/arm/mach-integrator/impd1.c3
-rw-r--r--arch/arm/mach-integrator/pci_v3.c2
-rw-r--r--arch/arm/mach-ns9xxx/irq.c22
-rw-r--r--arch/arm/mach-omap1/board-palmte.c12
-rw-r--r--arch/arm/mach-omap1/board-palmz71.c2
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c1
-rw-r--r--arch/arm/mach-omap2/board-apollon.c1
-rw-r--r--arch/arm/mach-omap2/board-generic.c1
-rw-r--r--arch/arm/mach-omap2/board-h4.c1
-rw-r--r--arch/arm/mach-omap2/clock.c4
-rw-r--r--arch/arm/mach-omap2/clock34xx.h21
-rw-r--r--arch/arm/mach-omap2/cm-regbits-34xx.h1
-rw-r--r--arch/arm/mach-omap2/gpmc.c2
-rw-r--r--arch/arm/mach-omap2/mailbox.c25
-rw-r--r--arch/arm/mach-omap2/prm.h2
-rw-r--r--arch/arm/mach-orion5x/addr-map.c66
-rw-r--r--arch/arm/mach-orion5x/common.c11
-rw-r--r--arch/arm/mach-orion5x/common.h1
-rw-r--r--arch/arm/mach-orion5x/dns323-setup.c2
-rw-r--r--arch/arm/mach-orion5x/kurobox_pro-setup.c2
-rw-r--r--arch/arm/mach-pxa/Makefile12
-rw-r--r--arch/arm/mach-pxa/cm-x270.c2
-rw-r--r--arch/arm/mach-pxa/colibri.c3
-rw-r--r--arch/arm/mach-pxa/corgi.c4
-rw-r--r--arch/arm/mach-pxa/cpu-pxa.c310
-rw-r--r--arch/arm/mach-pxa/em-x270.c2
-rw-r--r--arch/arm/mach-pxa/lubbock.c2
-rw-r--r--arch/arm/mach-pxa/pm.c10
-rw-r--r--arch/arm/mach-pxa/poodle.c2
-rw-r--r--arch/arm/mach-pxa/pxa25x.c11
-rw-r--r--arch/arm/mach-pxa/pxa27x.c11
-rw-r--r--arch/arm/mach-pxa/pxa3xx.c7
-rw-r--r--arch/arm/mach-pxa/spitz.c2
-rw-r--r--arch/arm/mach-pxa/spitz_pm.c3
-rw-r--r--arch/arm/mach-pxa/ssp.c2
-rw-r--r--arch/arm/mach-pxa/tosa.c6
-rw-r--r--arch/arm/mach-realview/platsmp.c2
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c2
-rw-r--r--arch/arm/mach-s3c2410/mach-vr1000.c4
-rw-r--r--arch/arm/mach-sa1100/collie.c42
-rw-r--r--arch/arm/mach-sa1100/pm.c8
-rw-r--r--arch/arm/mm/proc-arm925.S2
-rw-r--r--arch/arm/mm/proc-arm926.S2
-rw-r--r--arch/arm/mm/proc-arm940.S2
-rw-r--r--arch/arm/mm/proc-arm946.S2
-rw-r--r--arch/arm/plat-omap/clock.c11
-rw-r--r--arch/arm/plat-omap/dma.c4
-rw-r--r--arch/arm/plat-omap/mailbox.c1
-rw-r--r--arch/arm/plat-s3c24xx/clock.c4
-rw-r--r--arch/arm/plat-s3c24xx/s3c244x.c1
61 files changed, 437 insertions, 361 deletions
diff --git a/arch/arm/boot/compressed/head-xscale.S b/arch/arm/boot/compressed/head-xscale.S
index 67ea99ef6521..dd3fbd6766e1 100644
--- a/arch/arm/boot/compressed/head-xscale.S
+++ b/arch/arm/boot/compressed/head-xscale.S
@@ -33,10 +33,6 @@ __XScale_start:
33 bic r0, r0, #0x1000 @ clear Icache 33 bic r0, r0, #0x1000 @ clear Icache
34 mcr p15, 0, r0, c1, c0, 0 34 mcr p15, 0, r0, c1, c0, 0
35 35
36#ifdef CONFIG_ARCH_COTULLA_IDP
37 mov r7, #MACH_TYPE_COTULLA_IDP
38#endif
39
40#ifdef CONFIG_ARCH_IXP2000 36#ifdef CONFIG_ARCH_IXP2000
41 mov r1, #-1 37 mov r1, #-1
42 mov r0, #0xd6000000 38 mov r0, #0xd6000000
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index 52fc6a883281..2744673314b4 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -650,7 +650,8 @@ EXPORT_SYMBOL(dma_map_sg);
650EXPORT_SYMBOL(dma_unmap_sg); 650EXPORT_SYMBOL(dma_unmap_sg);
651EXPORT_SYMBOL(dma_sync_single_for_cpu); 651EXPORT_SYMBOL(dma_sync_single_for_cpu);
652EXPORT_SYMBOL(dma_sync_single_for_device); 652EXPORT_SYMBOL(dma_sync_single_for_device);
653EXPORT_SYMBOL(dma_sync_sg); 653EXPORT_SYMBOL(dma_sync_sg_for_cpu);
654EXPORT_SYMBOL(dma_sync_sg_for_device);
654EXPORT_SYMBOL(dmabounce_register_dev); 655EXPORT_SYMBOL(dmabounce_register_dev);
655EXPORT_SYMBOL(dmabounce_unregister_dev); 656EXPORT_SYMBOL(dmabounce_unregister_dev);
656 657
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c
index ae21755872ed..d973c986f721 100644
--- a/arch/arm/common/locomo.c
+++ b/arch/arm/common/locomo.c
@@ -321,11 +321,42 @@ static void locomo_gpio_unmask_irq(unsigned int irq)
321 locomo_writel(r, mapbase + LOCOMO_GIE); 321 locomo_writel(r, mapbase + LOCOMO_GIE);
322} 322}
323 323
324static int GPIO_IRQ_rising_edge;
325static int GPIO_IRQ_falling_edge;
326
327static int locomo_gpio_type(unsigned int irq, unsigned int type)
328{
329 unsigned int mask;
330 void __iomem *mapbase = get_irq_chip_data(irq);
331
332 mask = 1 << (irq - LOCOMO_IRQ_GPIO_START);
333
334 if (type == IRQT_PROBE) {
335 if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
336 return 0;
337 type = __IRQT_RISEDGE | __IRQT_FALEDGE;
338 }
339
340 if (type & __IRQT_RISEDGE)
341 GPIO_IRQ_rising_edge |= mask;
342 else
343 GPIO_IRQ_rising_edge &= ~mask;
344 if (type & __IRQT_FALEDGE)
345 GPIO_IRQ_falling_edge |= mask;
346 else
347 GPIO_IRQ_falling_edge &= ~mask;
348 locomo_writel(GPIO_IRQ_rising_edge, mapbase + LOCOMO_GRIE);
349 locomo_writel(GPIO_IRQ_falling_edge, mapbase + LOCOMO_GFIE);
350
351 return 0;
352}
353
324static struct irq_chip locomo_gpio_chip = { 354static struct irq_chip locomo_gpio_chip = {
325 .name = "LOCOMO-gpio", 355 .name = "LOCOMO-gpio",
326 .ack = locomo_gpio_ack_irq, 356 .ack = locomo_gpio_ack_irq,
327 .mask = locomo_gpio_mask_irq, 357 .mask = locomo_gpio_mask_irq,
328 .unmask = locomo_gpio_unmask_irq, 358 .unmask = locomo_gpio_unmask_irq,
359 .set_type = locomo_gpio_type,
329}; 360};
330 361
331static void locomo_lt_handler(unsigned int irq, struct irq_desc *desc) 362static void locomo_lt_handler(unsigned int irq, struct irq_desc *desc)
@@ -450,22 +481,18 @@ static void locomo_setup_irq(struct locomo *lchip)
450 set_irq_chip(IRQ_LOCOMO_KEY_BASE, &locomo_chip); 481 set_irq_chip(IRQ_LOCOMO_KEY_BASE, &locomo_chip);
451 set_irq_chip_data(IRQ_LOCOMO_KEY_BASE, irqbase); 482 set_irq_chip_data(IRQ_LOCOMO_KEY_BASE, irqbase);
452 set_irq_chained_handler(IRQ_LOCOMO_KEY_BASE, locomo_key_handler); 483 set_irq_chained_handler(IRQ_LOCOMO_KEY_BASE, locomo_key_handler);
453 set_irq_flags(IRQ_LOCOMO_KEY_BASE, IRQF_VALID | IRQF_PROBE);
454 484
455 set_irq_chip(IRQ_LOCOMO_GPIO_BASE, &locomo_chip); 485 set_irq_chip(IRQ_LOCOMO_GPIO_BASE, &locomo_chip);
456 set_irq_chip_data(IRQ_LOCOMO_GPIO_BASE, irqbase); 486 set_irq_chip_data(IRQ_LOCOMO_GPIO_BASE, irqbase);
457 set_irq_chained_handler(IRQ_LOCOMO_GPIO_BASE, locomo_gpio_handler); 487 set_irq_chained_handler(IRQ_LOCOMO_GPIO_BASE, locomo_gpio_handler);
458 set_irq_flags(IRQ_LOCOMO_GPIO_BASE, IRQF_VALID | IRQF_PROBE);
459 488
460 set_irq_chip(IRQ_LOCOMO_LT_BASE, &locomo_chip); 489 set_irq_chip(IRQ_LOCOMO_LT_BASE, &locomo_chip);
461 set_irq_chip_data(IRQ_LOCOMO_LT_BASE, irqbase); 490 set_irq_chip_data(IRQ_LOCOMO_LT_BASE, irqbase);
462 set_irq_chained_handler(IRQ_LOCOMO_LT_BASE, locomo_lt_handler); 491 set_irq_chained_handler(IRQ_LOCOMO_LT_BASE, locomo_lt_handler);
463 set_irq_flags(IRQ_LOCOMO_LT_BASE, IRQF_VALID | IRQF_PROBE);
464 492
465 set_irq_chip(IRQ_LOCOMO_SPI_BASE, &locomo_chip); 493 set_irq_chip(IRQ_LOCOMO_SPI_BASE, &locomo_chip);
466 set_irq_chip_data(IRQ_LOCOMO_SPI_BASE, irqbase); 494 set_irq_chip_data(IRQ_LOCOMO_SPI_BASE, irqbase);
467 set_irq_chained_handler(IRQ_LOCOMO_SPI_BASE, locomo_spi_handler); 495 set_irq_chained_handler(IRQ_LOCOMO_SPI_BASE, locomo_spi_handler);
468 set_irq_flags(IRQ_LOCOMO_SPI_BASE, IRQF_VALID | IRQF_PROBE);
469 496
470 /* install handlers for IRQ_LOCOMO_KEY_BASE generated interrupts */ 497 /* install handlers for IRQ_LOCOMO_KEY_BASE generated interrupts */
471 set_irq_chip(LOCOMO_IRQ_KEY_START, &locomo_key_chip); 498 set_irq_chip(LOCOMO_IRQ_KEY_START, &locomo_key_chip);
@@ -488,7 +515,7 @@ static void locomo_setup_irq(struct locomo *lchip)
488 set_irq_flags(LOCOMO_IRQ_LT_START, IRQF_VALID | IRQF_PROBE); 515 set_irq_flags(LOCOMO_IRQ_LT_START, IRQF_VALID | IRQF_PROBE);
489 516
490 /* install handlers for IRQ_LOCOMO_SPI_BASE generated interrupts */ 517 /* install handlers for IRQ_LOCOMO_SPI_BASE generated interrupts */
491 for (irq = LOCOMO_IRQ_SPI_START; irq < LOCOMO_IRQ_SPI_START + 3; irq++) { 518 for (irq = LOCOMO_IRQ_SPI_START; irq < LOCOMO_IRQ_SPI_START + 4; irq++) {
492 set_irq_chip(irq, &locomo_spi_chip); 519 set_irq_chip(irq, &locomo_spi_chip);
493 set_irq_chip_data(irq, irqbase); 520 set_irq_chip_data(irq, irqbase);
494 set_irq_handler(irq, handle_edge_irq); 521 set_irq_handler(irq, handle_edge_irq);
@@ -574,20 +601,20 @@ static int locomo_suspend(struct platform_device *dev, pm_message_t state)
574 601
575 save->LCM_GPO = locomo_readl(lchip->base + LOCOMO_GPO); /* GPIO */ 602 save->LCM_GPO = locomo_readl(lchip->base + LOCOMO_GPO); /* GPIO */
576 locomo_writel(0x00, lchip->base + LOCOMO_GPO); 603 locomo_writel(0x00, lchip->base + LOCOMO_GPO);
577 save->LCM_SPICT = locomo_readl(lchip->base + LOCOMO_SPICT); /* SPI */ 604 save->LCM_SPICT = locomo_readl(lchip->base + LOCOMO_SPI + LOCOMO_SPICT); /* SPI */
578 locomo_writel(0x40, lchip->base + LOCOMO_SPICT); 605 locomo_writel(0x40, lchip->base + LOCOMO_SPICT);
579 save->LCM_GPE = locomo_readl(lchip->base + LOCOMO_GPE); /* GPIO */ 606 save->LCM_GPE = locomo_readl(lchip->base + LOCOMO_GPE); /* GPIO */
580 locomo_writel(0x00, lchip->base + LOCOMO_GPE); 607 locomo_writel(0x00, lchip->base + LOCOMO_GPE);
581 save->LCM_ASD = locomo_readl(lchip->base + LOCOMO_ASD); /* ADSTART */ 608 save->LCM_ASD = locomo_readl(lchip->base + LOCOMO_ASD); /* ADSTART */
582 locomo_writel(0x00, lchip->base + LOCOMO_ASD); 609 locomo_writel(0x00, lchip->base + LOCOMO_ASD);
583 save->LCM_SPIMD = locomo_readl(lchip->base + LOCOMO_SPIMD); /* SPI */ 610 save->LCM_SPIMD = locomo_readl(lchip->base + LOCOMO_SPI + LOCOMO_SPIMD); /* SPI */
584 locomo_writel(0x3C14, lchip->base + LOCOMO_SPIMD); 611 locomo_writel(0x3C14, lchip->base + LOCOMO_SPI + LOCOMO_SPIMD);
585 612
586 locomo_writel(0x00, lchip->base + LOCOMO_PAIF); 613 locomo_writel(0x00, lchip->base + LOCOMO_PAIF);
587 locomo_writel(0x00, lchip->base + LOCOMO_DAC); 614 locomo_writel(0x00, lchip->base + LOCOMO_DAC);
588 locomo_writel(0x00, lchip->base + LOCOMO_BACKLIGHT + LOCOMO_TC); 615 locomo_writel(0x00, lchip->base + LOCOMO_BACKLIGHT + LOCOMO_TC);
589 616
590 if ( (locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT0) & 0x88) && (locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT1) & 0x88) ) 617 if ((locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT0) & 0x88) && (locomo_readl(lchip->base + LOCOMO_LED + LOCOMO_LPT1) & 0x88))
591 locomo_writel(0x00, lchip->base + LOCOMO_C32K); /* CLK32 off */ 618 locomo_writel(0x00, lchip->base + LOCOMO_C32K); /* CLK32 off */
592 else 619 else
593 /* 18MHz already enabled, so no wait */ 620 /* 18MHz already enabled, so no wait */
@@ -616,10 +643,10 @@ static int locomo_resume(struct platform_device *dev)
616 spin_lock_irqsave(&lchip->lock, flags); 643 spin_lock_irqsave(&lchip->lock, flags);
617 644
618 locomo_writel(save->LCM_GPO, lchip->base + LOCOMO_GPO); 645 locomo_writel(save->LCM_GPO, lchip->base + LOCOMO_GPO);
619 locomo_writel(save->LCM_SPICT, lchip->base + LOCOMO_SPICT); 646 locomo_writel(save->LCM_SPICT, lchip->base + LOCOMO_SPI + LOCOMO_SPICT);
620 locomo_writel(save->LCM_GPE, lchip->base + LOCOMO_GPE); 647 locomo_writel(save->LCM_GPE, lchip->base + LOCOMO_GPE);
621 locomo_writel(save->LCM_ASD, lchip->base + LOCOMO_ASD); 648 locomo_writel(save->LCM_ASD, lchip->base + LOCOMO_ASD);
622 locomo_writel(save->LCM_SPIMD, lchip->base + LOCOMO_SPIMD); 649 locomo_writel(save->LCM_SPIMD, lchip->base + LOCOMO_SPI + LOCOMO_SPIMD);
623 650
624 locomo_writel(0x00, lchip->base + LOCOMO_C32K); 651 locomo_writel(0x00, lchip->base + LOCOMO_C32K);
625 locomo_writel(0x90, lchip->base + LOCOMO_TADC); 652 locomo_writel(0x90, lchip->base + LOCOMO_TADC);
@@ -688,9 +715,9 @@ __locomo_probe(struct device *me, struct resource *mem, int irq)
688 715
689 /* GPIO */ 716 /* GPIO */
690 locomo_writel(0, lchip->base + LOCOMO_GPO); 717 locomo_writel(0, lchip->base + LOCOMO_GPO);
691 locomo_writel( (LOCOMO_GPIO(2) | LOCOMO_GPIO(3) | LOCOMO_GPIO(13) | LOCOMO_GPIO(14)) 718 locomo_writel((LOCOMO_GPIO(1) | LOCOMO_GPIO(2) | LOCOMO_GPIO(13) | LOCOMO_GPIO(14))
692 , lchip->base + LOCOMO_GPE); 719 , lchip->base + LOCOMO_GPE);
693 locomo_writel( (LOCOMO_GPIO(2) | LOCOMO_GPIO(3) | LOCOMO_GPIO(13) | LOCOMO_GPIO(14)) 720 locomo_writel((LOCOMO_GPIO(1) | LOCOMO_GPIO(2) | LOCOMO_GPIO(13) | LOCOMO_GPIO(14))
694 , lchip->base + LOCOMO_GPD); 721 , lchip->base + LOCOMO_GPD);
695 locomo_writel(0, lchip->base + LOCOMO_GIE); 722 locomo_writel(0, lchip->base + LOCOMO_GIE);
696 723
@@ -833,7 +860,10 @@ void locomo_gpio_set_dir(struct device *dev, unsigned int bits, unsigned int dir
833 spin_lock_irqsave(&lchip->lock, flags); 860 spin_lock_irqsave(&lchip->lock, flags);
834 861
835 r = locomo_readl(lchip->base + LOCOMO_GPD); 862 r = locomo_readl(lchip->base + LOCOMO_GPD);
836 r &= ~bits; 863 if (dir)
864 r |= bits;
865 else
866 r &= ~bits;
837 locomo_writel(r, lchip->base + LOCOMO_GPD); 867 locomo_writel(r, lchip->base + LOCOMO_GPD);
838 868
839 r = locomo_readl(lchip->base + LOCOMO_GPE); 869 r = locomo_readl(lchip->base + LOCOMO_GPE);
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index f73d62e8ab60..688b7b1ee416 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -179,3 +179,5 @@ EXPORT_SYMBOL(_find_next_zero_bit_be);
179EXPORT_SYMBOL(_find_first_bit_be); 179EXPORT_SYMBOL(_find_first_bit_be);
180EXPORT_SYMBOL(_find_next_bit_be); 180EXPORT_SYMBOL(_find_next_bit_be);
181#endif 181#endif
182
183EXPORT_SYMBOL(copy_page);
diff --git a/arch/arm/kernel/arthur.c b/arch/arm/kernel/arthur.c
index 0ee2e9819631..321c5291d05f 100644
--- a/arch/arm/kernel/arthur.c
+++ b/arch/arm/kernel/arthur.c
@@ -90,3 +90,5 @@ static void __exit arthur_exit(void)
90 90
91module_init(arthur_init); 91module_init(arthur_init);
92module_exit(arthur_exit); 92module_exit(arthur_exit);
93
94MODULE_LICENSE("GPL");
diff --git a/arch/arm/kernel/init_task.c b/arch/arm/kernel/init_task.c
index bd4ef53bc6b9..8b8c9d38a761 100644
--- a/arch/arm/kernel/init_task.c
+++ b/arch/arm/kernel/init_task.c
@@ -13,7 +13,6 @@
13#include <asm/pgtable.h> 13#include <asm/pgtable.h>
14 14
15static struct fs_struct init_fs = INIT_FS; 15static struct fs_struct init_fs = INIT_FS;
16static struct files_struct init_files = INIT_FILES;
17static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 16static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
18static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 17static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
19struct mm_struct init_mm = INIT_MM(init_mm); 18struct mm_struct init_mm = INIT_MM(init_mm);
diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c
index 9bd1870d980e..0128687ba0f7 100644
--- a/arch/arm/kernel/sys_arm.c
+++ b/arch/arm/kernel/sys_arm.c
@@ -34,23 +34,6 @@ extern unsigned long do_mremap(unsigned long addr, unsigned long old_len,
34 unsigned long new_len, unsigned long flags, 34 unsigned long new_len, unsigned long flags,
35 unsigned long new_addr); 35 unsigned long new_addr);
36 36
37/*
38 * sys_pipe() is the normal C calling standard for creating
39 * a pipe. It's not the way unix traditionally does this, though.
40 */
41asmlinkage int sys_pipe(unsigned long __user *fildes)
42{
43 int fd[2];
44 int error;
45
46 error = do_pipe(fd);
47 if (!error) {
48 if (copy_to_user(fildes, fd, 2*sizeof(int)))
49 error = -EFAULT;
50 }
51 return error;
52}
53
54/* common code for old and new mmaps */ 37/* common code for old and new mmaps */
55inline long do_mmap2( 38inline long do_mmap2(
56 unsigned long addr, unsigned long len, 39 unsigned long addr, unsigned long len,
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 6b9e423ec474..247e8e7cebea 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -544,10 +544,10 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
544 struct resource *fb_res = &lcdc_resources[2]; 544 struct resource *fb_res = &lcdc_resources[2];
545 size_t fb_len = fb_res->end - fb_res->start + 1; 545 size_t fb_len = fb_res->end - fb_res->start + 1;
546 546
547 fb = ioremap_writecombine(fb_res->start, fb_len); 547 fb = ioremap(fb_res->start, fb_len);
548 if (fb) { 548 if (fb) {
549 memset(fb, 0, fb_len); 549 memset(fb, 0, fb_len);
550 iounmap(fb, fb_len); 550 iounmap(fb);
551 } 551 }
552 } 552 }
553 lcdc_data = *data; 553 lcdc_data = *data;
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index b21f33393269..9945cd25d0ab 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -332,13 +332,6 @@ static struct resource lcdc_resources[] = {
332 .end = AT91SAM9RL_ID_LCDC, 332 .end = AT91SAM9RL_ID_LCDC,
333 .flags = IORESOURCE_IRQ, 333 .flags = IORESOURCE_IRQ,
334 }, 334 },
335#if defined(CONFIG_FB_INTSRAM)
336 [2] = {
337 .start = AT91SAM9RL_SRAM_BASE,
338 .end = AT91SAM9RL_SRAM_BASE + AT91SAM9RL_SRAM_SIZE - 1,
339 .flags = IORESOURCE_MEM,
340 },
341#endif
342}; 335};
343 336
344static struct platform_device at91_lcdc_device = { 337static struct platform_device at91_lcdc_device = {
@@ -381,20 +374,6 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
381 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */ 374 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
382 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */ 375 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
383 376
384#ifdef CONFIG_FB_INTSRAM
385 {
386 void __iomem *fb;
387 struct resource *fb_res = &lcdc_resources[2];
388 size_t fb_len = fb_res->end - fb_res->start + 1;
389
390 fb = ioremap_writecombine(fb_res->start, fb_len);
391 if (fb) {
392 memset(fb, 0, fb_len);
393 iounmap(fb, fb_len);
394 }
395 }
396#endif
397
398 lcdc_data = *data; 377 lcdc_data = *data;
399 platform_device_register(&at91_lcdc_device); 378 platform_device_register(&at91_lcdc_device);
400} 379}
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index 1de121fc55f4..f44647738ee4 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -16,16 +16,32 @@
16#include <asm/mach/arch.h> 16#include <asm/mach/arch.h>
17#include <asm/arch/at91x40.h> 17#include <asm/arch/at91x40.h>
18#include <asm/arch/at91_st.h> 18#include <asm/arch/at91_st.h>
19#include <asm/arch/timex.h>
19#include "generic.h" 20#include "generic.h"
20 21
21/* 22/*
22 * This is used in the gpio code, stub locally. 23 * Export the clock functions for the AT91X40. Some external code common
24 * to all AT91 family parts relys on this, like the gpio and serial support.
23 */ 25 */
24int clk_enable(struct clk *clk) 26int clk_enable(struct clk *clk)
25{ 27{
26 return 0; 28 return 0;
27} 29}
28 30
31void clk_disable(struct clk *clk)
32{
33}
34
35unsigned long clk_get_rate(struct clk *clk)
36{
37 return AT91X40_MASTER_CLOCK;
38}
39
40struct clk *clk_get(struct device *dev, const char *id)
41{
42 return NULL;
43}
44
29void __init at91x40_initialize(unsigned long main_clock) 45void __init at91x40_initialize(unsigned long main_clock)
30{ 46{
31 at91_extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1) 47 at91_extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 8bc187240542..1d7bca6aa441 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -280,7 +280,7 @@ static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
280 const int port = gpio >> 3; 280 const int port = gpio >> 3;
281 const int port_mask = 1 << (gpio & 7); 281 const int port_mask = 1 << (gpio & 7);
282 282
283 gpio_direction_output(gpio, gpio_get_value(gpio)); 283 gpio_direction_input(gpio);
284 284
285 switch (type) { 285 switch (type) {
286 case IRQT_RISING: 286 case IRQT_RISING:
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index 92d79fb39311..62e653a3ea1a 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -369,7 +369,8 @@ static int impd1_probe(struct lm_device *dev)
369 369
370 lm_set_drvdata(dev, impd1); 370 lm_set_drvdata(dev, impd1);
371 371
372 printk("IM-PD1 found at 0x%08lx\n", dev->resource.start); 372 printk("IM-PD1 found at 0x%08lx\n",
373 (unsigned long)dev->resource.start);
373 374
374 for (i = 0; i < ARRAY_SIZE(impd1->vcos); i++) { 375 for (i = 0; i < ARRAY_SIZE(impd1->vcos); i++) {
375 impd1->vcos[i].owner = THIS_MODULE, 376 impd1->vcos[i].owner = THIS_MODULE,
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index d55fa4e9bb43..c07f497000ca 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -405,7 +405,6 @@ v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
405 addr, fsr, pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255, 405 addr, fsr, pc, instr, __raw_readl(SC_LBFADDR), __raw_readl(SC_LBFCODE) & 255,
406 v3_readb(V3_LB_ISTAT)); 406 v3_readb(V3_LB_ISTAT));
407 printk(KERN_DEBUG "%s", buf); 407 printk(KERN_DEBUG "%s", buf);
408 printascii(buf);
409#endif 408#endif
410 409
411 v3_writeb(V3_LB_ISTAT, 0); 410 v3_writeb(V3_LB_ISTAT, 0);
@@ -447,6 +446,7 @@ static irqreturn_t v3_irq(int dummy, void *devid)
447 unsigned long pc = instruction_pointer(regs); 446 unsigned long pc = instruction_pointer(regs);
448 unsigned long instr = *(unsigned long *)pc; 447 unsigned long instr = *(unsigned long *)pc;
449 char buf[128]; 448 char buf[128];
449 extern void printascii(const char *);
450 450
451 sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x " 451 sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x "
452 "ISTAT=%02x\n", IRQ_AP_V3INT, pc, instr, 452 "ISTAT=%02x\n", IRQ_AP_V3INT, pc, instr,
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c
index 36e5835e6097..ca85d24cf39f 100644
--- a/arch/arm/mach-ns9xxx/irq.c
+++ b/arch/arm/mach-ns9xxx/irq.c
@@ -62,7 +62,7 @@ static struct irq_chip ns9xxx_chip = {
62#if 0 62#if 0
63#define handle_irq handle_level_irq 63#define handle_irq handle_level_irq
64#else 64#else
65void handle_prio_irq(unsigned int irq, struct irq_desc *desc) 65static void handle_prio_irq(unsigned int irq, struct irq_desc *desc)
66{ 66{
67 unsigned int cpu = smp_processor_id(); 67 unsigned int cpu = smp_processor_id();
68 struct irqaction *action; 68 struct irqaction *action;
@@ -70,27 +70,35 @@ void handle_prio_irq(unsigned int irq, struct irq_desc *desc)
70 70
71 spin_lock(&desc->lock); 71 spin_lock(&desc->lock);
72 72
73 if (unlikely(desc->status & IRQ_INPROGRESS)) 73 BUG_ON(desc->status & IRQ_INPROGRESS);
74 goto out_unlock;
75 74
76 desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); 75 desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
77 kstat_cpu(cpu).irqs[irq]++; 76 kstat_cpu(cpu).irqs[irq]++;
78 77
79 action = desc->action; 78 action = desc->action;
80 if (unlikely(!action || (desc->status & IRQ_DISABLED))) 79 if (unlikely(!action || (desc->status & IRQ_DISABLED)))
81 goto out_unlock; 80 goto out_mask;
82 81
83 desc->status |= IRQ_INPROGRESS; 82 desc->status |= IRQ_INPROGRESS;
84 spin_unlock(&desc->lock); 83 spin_unlock(&desc->lock);
85 84
86 action_ret = handle_IRQ_event(irq, action); 85 action_ret = handle_IRQ_event(irq, action);
87 86
87 /* XXX: There is no direct way to access noirqdebug, so check
88 * unconditionally for spurious irqs...
89 * Maybe this function should go to kernel/irq/chip.c? */
90 note_interrupt(irq, desc, action_ret);
91
88 spin_lock(&desc->lock); 92 spin_lock(&desc->lock);
89 desc->status &= ~IRQ_INPROGRESS; 93 desc->status &= ~IRQ_INPROGRESS;
90 if (!(desc->status & IRQ_DISABLED) && desc->chip->ack)
91 desc->chip->ack(irq);
92 94
93out_unlock: 95 if (desc->status & IRQ_DISABLED)
96out_mask:
97 desc->chip->mask(irq);
98
99 /* ack unconditionally to unmask lower prio irqs */
100 desc->chip->ack(irq);
101
94 spin_unlock(&desc->lock); 102 spin_unlock(&desc->lock);
95} 103}
96#define handle_irq handle_prio_irq 104#define handle_irq handle_prio_irq
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index ca1a4bf78a10..a4d20127a60e 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -24,7 +24,6 @@
24#include <linux/mtd/mtd.h> 24#include <linux/mtd/mtd.h>
25#include <linux/mtd/partitions.h> 25#include <linux/mtd/partitions.h>
26#include <linux/spi/spi.h> 26#include <linux/spi/spi.h>
27#include <linux/spi/tsc2102.h>
28#include <linux/interrupt.h> 27#include <linux/interrupt.h>
29#include <linux/apm-emulation.h> 28#include <linux/apm-emulation.h>
30 29
@@ -63,7 +62,7 @@ static const int palmte_keymap[] = {
63 KEY(1, 1, KEY_DOWN), 62 KEY(1, 1, KEY_DOWN),
64 KEY(1, 2, KEY_UP), 63 KEY(1, 2, KEY_UP),
65 KEY(1, 3, KEY_RIGHT), 64 KEY(1, 3, KEY_RIGHT),
66 KEY(1, 4, KEY_CENTER), 65 KEY(1, 4, KEY_ENTER),
67 0, 66 0,
68}; 67};
69 68
@@ -315,14 +314,6 @@ static void palmte_get_power_status(struct apm_power_info *info, int *battery)
315#define palmte_get_power_status NULL 314#define palmte_get_power_status NULL
316#endif 315#endif
317 316
318static struct tsc2102_config palmte_tsc2102_config = {
319 .use_internal = 0,
320 .monitor = TSC_BAT1 | TSC_AUX | TSC_TEMP,
321 .temp_at25c = { 2200, 2615 },
322 .apm_report = palmte_get_power_status,
323 .alsa_config = &palmte_alsa_config,
324};
325
326static struct omap_board_config_kernel palmte_config[] __initdata = { 317static struct omap_board_config_kernel palmte_config[] __initdata = {
327 { OMAP_TAG_USB, &palmte_usb_config }, 318 { OMAP_TAG_USB, &palmte_usb_config },
328 { OMAP_TAG_MMC, &palmte_mmc_config }, 319 { OMAP_TAG_MMC, &palmte_mmc_config },
@@ -336,7 +327,6 @@ static struct spi_board_info palmte_spi_info[] __initdata = {
336 .bus_num = 2, /* uWire (officially) */ 327 .bus_num = 2, /* uWire (officially) */
337 .chip_select = 0, /* As opposed to 3 */ 328 .chip_select = 0, /* As opposed to 3 */
338 .irq = OMAP_GPIO_IRQ(PALMTE_PINTDAV_GPIO), 329 .irq = OMAP_GPIO_IRQ(PALMTE_PINTDAV_GPIO),
339 .platform_data = &palmte_tsc2102_config,
340 .max_speed_hz = 8000000, 330 .max_speed_hz = 8000000,
341 }, 331 },
342}; 332};
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 156510777ffe..e020c2774606 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -65,7 +65,7 @@ static int palmz71_keymap[] = {
65 KEY(1, 1, KEY_DOWN), 65 KEY(1, 1, KEY_DOWN),
66 KEY(1, 2, KEY_UP), 66 KEY(1, 2, KEY_UP),
67 KEY(1, 3, KEY_RIGHT), 67 KEY(1, 3, KEY_RIGHT),
68 KEY(1, 4, KEY_CENTER), 68 KEY(1, 4, KEY_ENTER),
69 KEY(2, 0, KEY_CAMERA), 69 KEY(2, 0, KEY_CAMERA),
70 0, 70 0,
71}; 71};
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 1c12d7c6c7fc..1682eb77c46d 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -208,6 +208,7 @@ static void __init omap_2430sdp_init(void)
208 208
209static void __init omap_2430sdp_map_io(void) 209static void __init omap_2430sdp_map_io(void)
210{ 210{
211 omap2_set_globals_243x();
211 omap2_map_common_io(); 212 omap2_map_common_io();
212} 213}
213 214
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index a1e1e6765b5b..620fa0f120ee 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -394,6 +394,7 @@ static void __init omap_apollon_init(void)
394 394
395static void __init omap_apollon_map_io(void) 395static void __init omap_apollon_map_io(void)
396{ 396{
397 omap2_set_globals_242x();
397 omap2_map_common_io(); 398 omap2_map_common_io();
398} 399}
399 400
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 90938151bcf1..df8be081e159 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -65,6 +65,7 @@ static void __init omap_generic_init(void)
65 65
66static void __init omap_generic_map_io(void) 66static void __init omap_generic_map_io(void)
67{ 67{
68 omap2_set_globals_242x(); /* should be 242x, 243x, or 343x */
68 omap2_map_common_io(); 69 omap2_map_common_io();
69} 70}
70 71
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index d1915f99a5fa..0d28f6897c8e 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -420,6 +420,7 @@ static void __init omap_h4_init(void)
420 420
421static void __init omap_h4_map_io(void) 421static void __init omap_h4_map_io(void)
422{ 422{
423 omap2_set_globals_242x();
423 omap2_map_common_io(); 424 omap2_map_common_io();
424} 425}
425 426
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index b57ffb5a22a5..ab9fc57d25f1 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -205,7 +205,9 @@ static void omap2_clk_wait_ready(struct clk *clk)
205 /* REVISIT: What are the appropriate exclusions for 34XX? */ 205 /* REVISIT: What are the appropriate exclusions for 34XX? */
206 /* OMAP3: ignore DSS-mod clocks */ 206 /* OMAP3: ignore DSS-mod clocks */
207 if (cpu_is_omap34xx() && 207 if (cpu_is_omap34xx() &&
208 (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0))) 208 (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
209 ((((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(CORE_MOD, 0)) &&
210 clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
209 return; 211 return;
210 212
211 /* Check if both functional and interface clocks 213 /* Check if both functional and interface clocks
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index cf4644a94b9b..c9c5972a2e25 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -836,7 +836,8 @@ static struct clk dpll5_m2_ck = {
836 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), 836 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
837 .clksel_mask = OMAP3430ES2_DIV_120M_MASK, 837 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
838 .clksel = div16_dpll5_clksel, 838 .clksel = div16_dpll5_clksel,
839 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, 839 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
840 PARENT_CONTROLS_CLOCK,
840 .recalc = &omap2_clksel_recalc, 841 .recalc = &omap2_clksel_recalc,
841}; 842};
842 843
@@ -1046,12 +1047,13 @@ static struct clk iva2_ck = {
1046 .name = "iva2_ck", 1047 .name = "iva2_ck",
1047 .parent = &dpll2_m2_ck, 1048 .parent = &dpll2_m2_ck,
1048 .init = &omap2_init_clksel_parent, 1049 .init = &omap2_init_clksel_parent,
1050 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1051 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1049 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, 1052 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1050 OMAP3430_CM_IDLEST_PLL), 1053 OMAP3430_CM_IDLEST_PLL),
1051 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, 1054 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
1052 .clksel = iva2_clksel, 1055 .clksel = iva2_clksel,
1053 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 1056 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1054 PARENT_CONTROLS_CLOCK,
1055 .recalc = &omap2_clksel_recalc, 1057 .recalc = &omap2_clksel_recalc,
1056}; 1058};
1057 1059
@@ -1836,7 +1838,8 @@ static struct clk omapctrl_ick = {
1836static struct clk ssi_l4_ick = { 1838static struct clk ssi_l4_ick = {
1837 .name = "ssi_l4_ick", 1839 .name = "ssi_l4_ick",
1838 .parent = &l4_ick, 1840 .parent = &l4_ick,
1839 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, 1841 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1842 PARENT_CONTROLS_CLOCK,
1840 .recalc = &followparent_recalc, 1843 .recalc = &followparent_recalc,
1841}; 1844};
1842 1845
@@ -2344,7 +2347,7 @@ static struct clk gpio6_fck = {
2344 .name = "gpio6_fck", 2347 .name = "gpio6_fck",
2345 .parent = &per_32k_alwon_fck, 2348 .parent = &per_32k_alwon_fck,
2346 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2349 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2347 .enable_bit = OMAP3430_EN_GPT6_SHIFT, 2350 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2348 .flags = CLOCK_IN_OMAP343X, 2351 .flags = CLOCK_IN_OMAP343X,
2349 .recalc = &followparent_recalc, 2352 .recalc = &followparent_recalc,
2350}; 2353};
@@ -2353,7 +2356,7 @@ static struct clk gpio5_fck = {
2353 .name = "gpio5_fck", 2356 .name = "gpio5_fck",
2354 .parent = &per_32k_alwon_fck, 2357 .parent = &per_32k_alwon_fck,
2355 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2358 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2356 .enable_bit = OMAP3430_EN_GPT5_SHIFT, 2359 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2357 .flags = CLOCK_IN_OMAP343X, 2360 .flags = CLOCK_IN_OMAP343X,
2358 .recalc = &followparent_recalc, 2361 .recalc = &followparent_recalc,
2359}; 2362};
@@ -2362,7 +2365,7 @@ static struct clk gpio4_fck = {
2362 .name = "gpio4_fck", 2365 .name = "gpio4_fck",
2363 .parent = &per_32k_alwon_fck, 2366 .parent = &per_32k_alwon_fck,
2364 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2367 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2365 .enable_bit = OMAP3430_EN_GPT4_SHIFT, 2368 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2366 .flags = CLOCK_IN_OMAP343X, 2369 .flags = CLOCK_IN_OMAP343X,
2367 .recalc = &followparent_recalc, 2370 .recalc = &followparent_recalc,
2368}; 2371};
@@ -2371,7 +2374,7 @@ static struct clk gpio3_fck = {
2371 .name = "gpio3_fck", 2374 .name = "gpio3_fck",
2372 .parent = &per_32k_alwon_fck, 2375 .parent = &per_32k_alwon_fck,
2373 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2376 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2374 .enable_bit = OMAP3430_EN_GPT3_SHIFT, 2377 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2375 .flags = CLOCK_IN_OMAP343X, 2378 .flags = CLOCK_IN_OMAP343X,
2376 .recalc = &followparent_recalc, 2379 .recalc = &followparent_recalc,
2377}; 2380};
@@ -2380,7 +2383,7 @@ static struct clk gpio2_fck = {
2380 .name = "gpio2_fck", 2383 .name = "gpio2_fck",
2381 .parent = &per_32k_alwon_fck, 2384 .parent = &per_32k_alwon_fck,
2382 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2385 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2383 .enable_bit = OMAP3430_EN_GPT2_SHIFT, 2386 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2384 .flags = CLOCK_IN_OMAP343X, 2387 .flags = CLOCK_IN_OMAP343X,
2385 .recalc = &followparent_recalc, 2388 .recalc = &followparent_recalc,
2386}; 2389};
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 9249129a5f46..3c38395f6442 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -56,6 +56,7 @@
56 56
57/* CM_FCLKEN_IVA2 */ 57/* CM_FCLKEN_IVA2 */
58#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0) 58#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2 (1 << 0)
59#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0
59 60
60/* CM_CLKEN_PLL_IVA2 */ 61/* CM_CLKEN_PLL_IVA2 */
61#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 62#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 02cede295e89..dbf68dc50ae2 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -42,7 +42,7 @@
42#define GPMC_STATUS 0x54 42#define GPMC_STATUS 0x54
43#define GPMC_PREFETCH_CONFIG1 0x1e0 43#define GPMC_PREFETCH_CONFIG1 0x1e0
44#define GPMC_PREFETCH_CONFIG2 0x1e4 44#define GPMC_PREFETCH_CONFIG2 0x1e4
45#define GPMC_PREFETCH_CONTROL 0x1e8 45#define GPMC_PREFETCH_CONTROL 0x1ec
46#define GPMC_PREFETCH_STATUS 0x1f0 46#define GPMC_PREFETCH_STATUS 0x1f0
47#define GPMC_ECC_CONFIG 0x1f4 47#define GPMC_ECC_CONFIG 0x1f4
48#define GPMC_ECC_CONTROL 0x1f8 48#define GPMC_ECC_CONTROL 0x1f8
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index b03cd06e055b..4799561c5a9e 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -70,6 +70,9 @@ struct omap_mbox2_priv {
70 70
71static struct clk *mbox_ick_handle; 71static struct clk *mbox_ick_handle;
72 72
73static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
74 omap_mbox_type_t irq);
75
73static inline unsigned int mbox_read_reg(unsigned int reg) 76static inline unsigned int mbox_read_reg(unsigned int reg)
74{ 77{
75 return __raw_readl(mbox_base + reg); 78 return __raw_readl(mbox_base + reg);
@@ -81,7 +84,7 @@ static inline void mbox_write_reg(unsigned int val, unsigned int reg)
81} 84}
82 85
83/* Mailbox H/W preparations */ 86/* Mailbox H/W preparations */
84static inline int omap2_mbox_startup(struct omap_mbox *mbox) 87static int omap2_mbox_startup(struct omap_mbox *mbox)
85{ 88{
86 unsigned int l; 89 unsigned int l;
87 90
@@ -97,38 +100,40 @@ static inline int omap2_mbox_startup(struct omap_mbox *mbox)
97 l |= 0x00000011; 100 l |= 0x00000011;
98 mbox_write_reg(l, MAILBOX_SYSCONFIG); 101 mbox_write_reg(l, MAILBOX_SYSCONFIG);
99 102
103 omap2_mbox_enable_irq(mbox, IRQ_RX);
104
100 return 0; 105 return 0;
101} 106}
102 107
103static inline void omap2_mbox_shutdown(struct omap_mbox *mbox) 108static void omap2_mbox_shutdown(struct omap_mbox *mbox)
104{ 109{
105 clk_disable(mbox_ick_handle); 110 clk_disable(mbox_ick_handle);
106 clk_put(mbox_ick_handle); 111 clk_put(mbox_ick_handle);
107} 112}
108 113
109/* Mailbox FIFO handle functions */ 114/* Mailbox FIFO handle functions */
110static inline mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox) 115static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
111{ 116{
112 struct omap_mbox2_fifo *fifo = 117 struct omap_mbox2_fifo *fifo =
113 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo; 118 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
114 return (mbox_msg_t) mbox_read_reg(fifo->msg); 119 return (mbox_msg_t) mbox_read_reg(fifo->msg);
115} 120}
116 121
117static inline void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg) 122static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
118{ 123{
119 struct omap_mbox2_fifo *fifo = 124 struct omap_mbox2_fifo *fifo =
120 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo; 125 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
121 mbox_write_reg(msg, fifo->msg); 126 mbox_write_reg(msg, fifo->msg);
122} 127}
123 128
124static inline int omap2_mbox_fifo_empty(struct omap_mbox *mbox) 129static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
125{ 130{
126 struct omap_mbox2_fifo *fifo = 131 struct omap_mbox2_fifo *fifo =
127 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo; 132 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
128 return (mbox_read_reg(fifo->msg_stat) == 0); 133 return (mbox_read_reg(fifo->msg_stat) == 0);
129} 134}
130 135
131static inline int omap2_mbox_fifo_full(struct omap_mbox *mbox) 136static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
132{ 137{
133 struct omap_mbox2_fifo *fifo = 138 struct omap_mbox2_fifo *fifo =
134 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo; 139 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
@@ -136,7 +141,7 @@ static inline int omap2_mbox_fifo_full(struct omap_mbox *mbox)
136} 141}
137 142
138/* Mailbox IRQ handle functions */ 143/* Mailbox IRQ handle functions */
139static inline void omap2_mbox_enable_irq(struct omap_mbox *mbox, 144static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
140 omap_mbox_type_t irq) 145 omap_mbox_type_t irq)
141{ 146{
142 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; 147 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
@@ -147,7 +152,7 @@ static inline void omap2_mbox_enable_irq(struct omap_mbox *mbox,
147 mbox_write_reg(l, p->irqenable); 152 mbox_write_reg(l, p->irqenable);
148} 153}
149 154
150static inline void omap2_mbox_disable_irq(struct omap_mbox *mbox, 155static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
151 omap_mbox_type_t irq) 156 omap_mbox_type_t irq)
152{ 157{
153 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; 158 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
@@ -158,7 +163,7 @@ static inline void omap2_mbox_disable_irq(struct omap_mbox *mbox,
158 mbox_write_reg(l, p->irqenable); 163 mbox_write_reg(l, p->irqenable);
159} 164}
160 165
161static inline void omap2_mbox_ack_irq(struct omap_mbox *mbox, 166static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
162 omap_mbox_type_t irq) 167 omap_mbox_type_t irq)
163{ 168{
164 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; 169 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
@@ -167,7 +172,7 @@ static inline void omap2_mbox_ack_irq(struct omap_mbox *mbox,
167 mbox_write_reg(bit, p->irqstatus); 172 mbox_write_reg(bit, p->irqstatus);
168} 173}
169 174
170static inline int omap2_mbox_is_irq(struct omap_mbox *mbox, 175static int omap2_mbox_is_irq(struct omap_mbox *mbox,
171 omap_mbox_type_t irq) 176 omap_mbox_type_t irq)
172{ 177{
173 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv; 178 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index ab7649afd891..618f8111658a 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -30,7 +30,7 @@
30 30
31/* 31/*
32 * Architecture-specific global PRM registers 32 * Architecture-specific global PRM registers
33 * Use prm_{read,write}_reg() with these registers. 33 * Use __raw_{read,write}l() with these registers.
34 * 34 *
35 * With a few exceptions, these are the register names beginning with 35 * With a few exceptions, these are the register names beginning with
36 * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the 36 * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index 9608503d67f5..e63fb05dc893 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -34,11 +34,7 @@
34 * Non-CPU Masters address decoding -- 34 * Non-CPU Masters address decoding --
35 * Unlike the CPU, we setup the access from Orion's master interfaces to DDR 35 * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
36 * banks only (the typical use case). 36 * banks only (the typical use case).
37 * Setup access for each master to DDR is issued by common.c. 37 * Setup access for each master to DDR is issued by platform device setup.
38 *
39 * Note: although orion_setbits() and orion_clrbits() are not atomic
40 * no locking is necessary here since code in this file is only called
41 * at boot time when there is no concurrency issues.
42 */ 38 */
43 39
44/* 40/*
@@ -48,10 +44,6 @@
48#define TARGET_DEV_BUS 1 44#define TARGET_DEV_BUS 1
49#define TARGET_PCI 3 45#define TARGET_PCI 3
50#define TARGET_PCIE 4 46#define TARGET_PCIE 4
51#define ATTR_DDR_CS(n) (((n) ==0) ? 0xe : \
52 ((n) == 1) ? 0xd : \
53 ((n) == 2) ? 0xb : \
54 ((n) == 3) ? 0x7 : 0xf)
55#define ATTR_PCIE_MEM 0x59 47#define ATTR_PCIE_MEM 0x59
56#define ATTR_PCIE_IO 0x51 48#define ATTR_PCIE_IO 0x51
57#define ATTR_PCIE_WA 0x79 49#define ATTR_PCIE_WA 0x79
@@ -61,17 +53,12 @@
61#define ATTR_DEV_CS1 0x1d 53#define ATTR_DEV_CS1 0x1d
62#define ATTR_DEV_CS2 0x1b 54#define ATTR_DEV_CS2 0x1b
63#define ATTR_DEV_BOOT 0xf 55#define ATTR_DEV_BOOT 0xf
64#define WIN_EN 1
65 56
66/* 57/*
67 * Helpers to get DDR bank info 58 * Helpers to get DDR bank info
68 */ 59 */
69#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) * 8)) 60#define DDR_BASE_CS(n) ORION5X_DDR_REG(0x1500 + ((n) << 3))
70#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) * 8)) 61#define DDR_SIZE_CS(n) ORION5X_DDR_REG(0x1504 + ((n) << 3))
71#define DDR_MAX_CS 4
72#define DDR_REG_TO_SIZE(reg) (((reg) | 0xffffff) + 1)
73#define DDR_REG_TO_BASE(reg) ((reg) & 0xff000000)
74#define DDR_BANK_EN 1
75 62
76/* 63/*
77 * CPU Address Decode Windows registers 64 * CPU Address Decode Windows registers
@@ -81,17 +68,6 @@
81#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4)) 68#define CPU_WIN_REMAP_LO(n) ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
82#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4)) 69#define CPU_WIN_REMAP_HI(n) ORION5X_BRIDGE_REG(0x00c | ((n) << 4))
83 70
84/*
85 * Gigabit Ethernet Address Decode Windows registers
86 */
87#define ETH_WIN_BASE(win) ORION5X_ETH_REG(0x200 + ((win) * 8))
88#define ETH_WIN_SIZE(win) ORION5X_ETH_REG(0x204 + ((win) * 8))
89#define ETH_WIN_REMAP(win) ORION5X_ETH_REG(0x280 + ((win) * 4))
90#define ETH_WIN_EN ORION5X_ETH_REG(0x290)
91#define ETH_WIN_PROT ORION5X_ETH_REG(0x294)
92#define ETH_MAX_WIN 6
93#define ETH_MAX_REMAP_WIN 4
94
95 71
96struct mbus_dram_target_info orion5x_mbus_dram_info; 72struct mbus_dram_target_info orion5x_mbus_dram_info;
97 73
@@ -202,39 +178,3 @@ void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
202{ 178{
203 setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); 179 setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
204} 180}
205
206void __init orion5x_setup_eth_wins(void)
207{
208 int i;
209
210 /*
211 * First, disable and clear windows
212 */
213 for (i = 0; i < ETH_MAX_WIN; i++) {
214 orion5x_write(ETH_WIN_BASE(i), 0);
215 orion5x_write(ETH_WIN_SIZE(i), 0);
216 orion5x_setbits(ETH_WIN_EN, 1 << i);
217 orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
218 if (i < ETH_MAX_REMAP_WIN)
219 orion5x_write(ETH_WIN_REMAP(i), 0);
220 }
221
222 /*
223 * Setup windows for DDR banks.
224 */
225 for (i = 0; i < DDR_MAX_CS; i++) {
226 u32 base, size;
227 size = orion5x_read(DDR_SIZE_CS(i));
228 base = orion5x_read(DDR_BASE_CS(i));
229 if (size & DDR_BANK_EN) {
230 base = DDR_REG_TO_BASE(base);
231 size = DDR_REG_TO_SIZE(size);
232 orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
233 orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
234 (ATTR_DDR_CS(i) << 8) |
235 TARGET_DDR);
236 orion5x_clrbits(ETH_WIN_EN, 1 << i);
237 orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
238 }
239 }
240}
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 968deb58be01..4f13fd037f04 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -190,6 +190,11 @@ static struct platform_device orion5x_ehci1 = {
190 * (The Orion and Discovery (MV643xx) families use the same Ethernet driver) 190 * (The Orion and Discovery (MV643xx) families use the same Ethernet driver)
191 ****************************************************************************/ 191 ****************************************************************************/
192 192
193struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
194 .dram = &orion5x_mbus_dram_info,
195 .t_clk = ORION5X_TCLK,
196};
197
193static struct resource orion5x_eth_shared_resources[] = { 198static struct resource orion5x_eth_shared_resources[] = {
194 { 199 {
195 .start = ORION5X_ETH_PHYS_BASE + 0x2000, 200 .start = ORION5X_ETH_PHYS_BASE + 0x2000,
@@ -201,6 +206,9 @@ static struct resource orion5x_eth_shared_resources[] = {
201static struct platform_device orion5x_eth_shared = { 206static struct platform_device orion5x_eth_shared = {
202 .name = MV643XX_ETH_SHARED_NAME, 207 .name = MV643XX_ETH_SHARED_NAME,
203 .id = 0, 208 .id = 0,
209 .dev = {
210 .platform_data = &orion5x_eth_shared_data,
211 },
204 .num_resources = 1, 212 .num_resources = 1,
205 .resource = orion5x_eth_shared_resources, 213 .resource = orion5x_eth_shared_resources,
206}; 214};
@@ -223,7 +231,9 @@ static struct platform_device orion5x_eth = {
223 231
224void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data) 232void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
225{ 233{
234 eth_data->shared = &orion5x_eth_shared;
226 orion5x_eth.dev.platform_data = eth_data; 235 orion5x_eth.dev.platform_data = eth_data;
236
227 platform_device_register(&orion5x_eth_shared); 237 platform_device_register(&orion5x_eth_shared);
228 platform_device_register(&orion5x_eth); 238 platform_device_register(&orion5x_eth);
229} 239}
@@ -360,7 +370,6 @@ void __init orion5x_init(void)
360 * Setup Orion address map 370 * Setup Orion address map
361 */ 371 */
362 orion5x_setup_cpu_mbus_bridge(); 372 orion5x_setup_cpu_mbus_bridge();
363 orion5x_setup_eth_wins();
364 373
365 /* 374 /*
366 * Register devices. 375 * Register devices.
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 14adf8d1a54a..bd0f05de6e18 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -22,7 +22,6 @@ void orion5x_setup_dev0_win(u32 base, u32 size);
22void orion5x_setup_dev1_win(u32 base, u32 size); 22void orion5x_setup_dev1_win(u32 base, u32 size);
23void orion5x_setup_dev2_win(u32 base, u32 size); 23void orion5x_setup_dev2_win(u32 base, u32 size);
24void orion5x_setup_pcie_wa_win(u32 base, u32 size); 24void orion5x_setup_pcie_wa_win(u32 base, u32 size);
25void orion5x_setup_eth_wins(void);
26 25
27/* 26/*
28 * Shared code used internally by other Orion core functions. 27 * Shared code used internally by other Orion core functions.
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index f9430f5ca9a8..27ce967ab9e5 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -58,7 +58,7 @@ static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
58} 58}
59 59
60static struct hw_pci dns323_pci __initdata = { 60static struct hw_pci dns323_pci __initdata = {
61 .nr_controllers = 1, 61 .nr_controllers = 2,
62 .swizzle = pci_std_swizzle, 62 .swizzle = pci_std_swizzle,
63 .setup = orion5x_pci_sys_setup, 63 .setup = orion5x_pci_sys_setup,
64 .scan = orion5x_pci_sys_scan_bus, 64 .scan = orion5x_pci_sys_scan_bus,
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 88410862feef..f5074b877b7f 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -138,7 +138,7 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
138} 138}
139 139
140static struct hw_pci kurobox_pro_pci __initdata = { 140static struct hw_pci kurobox_pro_pci __initdata = {
141 .nr_controllers = 1, 141 .nr_controllers = 2,
142 .swizzle = pci_std_swizzle, 142 .swizzle = pci_std_swizzle,
143 .setup = orion5x_pci_sys_setup, 143 .setup = orion5x_pci_sys_setup,
144 .scan = orion5x_pci_sys_scan_bus, 144 .scan = orion5x_pci_sys_scan_bus,
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 6a830853aa6a..0e6d05bb81aa 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -5,6 +5,13 @@
5# Common support (must be linked before board specific support) 5# Common support (must be linked before board specific support)
6obj-y += clock.o devices.o generic.o irq.o dma.o \ 6obj-y += clock.o devices.o generic.o irq.o dma.o \
7 time.o gpio.o 7 time.o gpio.o
8obj-$(CONFIG_PM) += pm.o sleep.o standby.o
9obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o
10
11# Generic drivers that other drivers may depend upon
12obj-$(CONFIG_PXA_SSP) += ssp.o
13
14# SoC-specific code
8obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa25x.o 15obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa25x.o
9obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa27x.o 16obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa27x.o
10obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o 17obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o
@@ -48,11 +55,6 @@ led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o
48 55
49obj-$(CONFIG_LEDS) += $(led-y) 56obj-$(CONFIG_LEDS) += $(led-y)
50 57
51# Misc features
52obj-$(CONFIG_PM) += pm.o sleep.o standby.o
53obj-$(CONFIG_CPU_FREQ) += cpu-pxa.o
54obj-$(CONFIG_PXA_SSP) += ssp.o
55
56ifeq ($(CONFIG_PCI),y) 58ifeq ($(CONFIG_PCI),y)
57obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o 59obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o
58endif 60endif
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index 6d4416a4f378..f5851d1adc25 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -59,7 +59,7 @@ static struct resource cmx270_dm9k_resource[] = {
59 [2] = { 59 [2] = {
60 .start = CMX270_ETHIRQ, 60 .start = CMX270_ETHIRQ,
61 .end = CMX270_ETHIRQ, 61 .end = CMX270_ETHIRQ,
62 .flags = IORESOURCE_IRQ, 62 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
63 } 63 }
64}; 64};
65 65
diff --git a/arch/arm/mach-pxa/colibri.c b/arch/arm/mach-pxa/colibri.c
index 43bf5a183e90..574839d7c132 100644
--- a/arch/arm/mach-pxa/colibri.c
+++ b/arch/arm/mach-pxa/colibri.c
@@ -98,7 +98,7 @@ static struct resource dm9000_resources[] = {
98 [2] = { 98 [2] = {
99 .start = COLIBRI_ETH_IRQ, 99 .start = COLIBRI_ETH_IRQ,
100 .end = COLIBRI_ETH_IRQ, 100 .end = COLIBRI_ETH_IRQ,
101 .flags = IORESOURCE_IRQ, 101 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING,
102 }, 102 },
103}; 103};
104 104
@@ -119,7 +119,6 @@ static void __init colibri_init(void)
119 /* DM9000 LAN */ 119 /* DM9000 LAN */
120 pxa_gpio_mode(GPIO78_nCS_2_MD); 120 pxa_gpio_mode(GPIO78_nCS_2_MD);
121 pxa_gpio_mode(GPIO_DM9000 | GPIO_IN); 121 pxa_gpio_mode(GPIO_DM9000 | GPIO_IN);
122 set_irq_type(COLIBRI_ETH_IRQ, IRQT_FALLING);
123 122
124 platform_add_devices(colibri_devices, ARRAY_SIZE(colibri_devices)); 123 platform_add_devices(colibri_devices, ARRAY_SIZE(colibri_devices));
125} 124}
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 259ca821e464..b757dd756655 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -493,8 +493,6 @@ static struct platform_device *devices[] __initdata = {
493 493
494static void corgi_poweroff(void) 494static void corgi_poweroff(void)
495{ 495{
496 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
497
498 if (!machine_is_corgi()) 496 if (!machine_is_corgi())
499 /* Green LED off tells the bootloader to halt */ 497 /* Green LED off tells the bootloader to halt */
500 reset_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_LED_GREEN); 498 reset_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_LED_GREEN);
@@ -503,8 +501,6 @@ static void corgi_poweroff(void)
503 501
504static void corgi_restart(char mode) 502static void corgi_restart(char mode)
505{ 503{
506 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
507
508 if (!machine_is_corgi()) 504 if (!machine_is_corgi())
509 /* Green LED on tells the bootloader to reboot */ 505 /* Green LED on tells the bootloader to reboot */
510 set_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_LED_GREEN); 506 set_scoop_gpio(&corgiscoop_device.dev, CORGI_SCP_LED_GREEN);
diff --git a/arch/arm/mach-pxa/cpu-pxa.c b/arch/arm/mach-pxa/cpu-pxa.c
index 4b21479332ae..fb9ba1ab2826 100644
--- a/arch/arm/mach-pxa/cpu-pxa.c
+++ b/arch/arm/mach-pxa/cpu-pxa.c
@@ -49,125 +49,216 @@ MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
49#define freq_debug 0 49#define freq_debug 0
50#endif 50#endif
51 51
52static unsigned int pxa27x_maxfreq;
53module_param(pxa27x_maxfreq, uint, 0);
54MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
55 "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
56
52typedef struct { 57typedef struct {
53 unsigned int khz; 58 unsigned int khz;
54 unsigned int membus; 59 unsigned int membus;
55 unsigned int cccr; 60 unsigned int cccr;
56 unsigned int div2; 61 unsigned int div2;
62 unsigned int cclkcfg;
57} pxa_freqs_t; 63} pxa_freqs_t;
58 64
59/* Define the refresh period in mSec for the SDRAM and the number of rows */ 65/* Define the refresh period in mSec for the SDRAM and the number of rows */
60#define SDRAM_TREF 64 /* standard 64ms SDRAM */ 66#define SDRAM_TREF 64 /* standard 64ms SDRAM */
61#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */ 67#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */
62#define MDREFR_DRI(x) (((x) * SDRAM_TREF) / (SDRAM_ROWS * 32))
63
64#define CCLKCFG_TURBO 0x1
65#define CCLKCFG_FCS 0x2
66#define PXA25x_MIN_FREQ 99500
67#define PXA25x_MAX_FREQ 398100
68#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
69#define MDREFR_DRI_MASK 0xFFF
70 68
69#define CCLKCFG_TURBO 0x1
70#define CCLKCFG_FCS 0x2
71#define CCLKCFG_HALFTURBO 0x4
72#define CCLKCFG_FASTBUS 0x8
73#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
74#define MDREFR_DRI_MASK 0xFFF
71 75
76/*
77 * PXA255 definitions
78 */
72/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */ 79/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
80#define CCLKCFG CCLKCFG_TURBO | CCLKCFG_FCS
81
73static pxa_freqs_t pxa255_run_freqs[] = 82static pxa_freqs_t pxa255_run_freqs[] =
74{ 83{
75 /* CPU MEMBUS CCCR DIV2*/ 84 /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
76 { 99500, 99500, 0x121, 1}, /* run= 99, turbo= 99, PXbus=50, SDRAM=50 */ 85 { 99500, 99500, 0x121, 1, CCLKCFG}, /* 99, 99, 50, 50 */
77 {132700, 132700, 0x123, 1}, /* run=133, turbo=133, PXbus=66, SDRAM=66 */ 86 {132700, 132700, 0x123, 1, CCLKCFG}, /* 133, 133, 66, 66 */
78 {199100, 99500, 0x141, 0}, /* run=199, turbo=199, PXbus=99, SDRAM=99 */ 87 {199100, 99500, 0x141, 0, CCLKCFG}, /* 199, 199, 99, 99 */
79 {265400, 132700, 0x143, 1}, /* run=265, turbo=265, PXbus=133, SDRAM=66 */ 88 {265400, 132700, 0x143, 1, CCLKCFG}, /* 265, 265, 133, 66 */
80 {331800, 165900, 0x145, 1}, /* run=331, turbo=331, PXbus=166, SDRAM=83 */ 89 {331800, 165900, 0x145, 1, CCLKCFG}, /* 331, 331, 166, 83 */
81 {398100, 99500, 0x161, 0}, /* run=398, turbo=398, PXbus=196, SDRAM=99 */ 90 {398100, 99500, 0x161, 0, CCLKCFG}, /* 398, 398, 196, 99 */
82 {0,}
83}; 91};
84#define NUM_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
85
86static struct cpufreq_frequency_table pxa255_run_freq_table[NUM_RUN_FREQS+1];
87 92
88/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */ 93/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
89static pxa_freqs_t pxa255_turbo_freqs[] = 94static pxa_freqs_t pxa255_turbo_freqs[] =
90{ 95{
91 /* CPU MEMBUS CCCR DIV2*/ 96 /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
92 { 99500, 99500, 0x121, 1}, /* run=99, turbo= 99, PXbus=50, SDRAM=50 */ 97 { 99500, 99500, 0x121, 1, CCLKCFG}, /* 99, 99, 50, 50 */
93 {199100, 99500, 0x221, 0}, /* run=99, turbo=199, PXbus=50, SDRAM=99 */ 98 {199100, 99500, 0x221, 0, CCLKCFG}, /* 99, 199, 50, 99 */
94 {298500, 99500, 0x321, 0}, /* run=99, turbo=287, PXbus=50, SDRAM=99 */ 99 {298500, 99500, 0x321, 0, CCLKCFG}, /* 99, 287, 50, 99 */
95 {298600, 99500, 0x1c1, 0}, /* run=199, turbo=287, PXbus=99, SDRAM=99 */ 100 {298600, 99500, 0x1c1, 0, CCLKCFG}, /* 199, 287, 99, 99 */
96 {398100, 99500, 0x241, 0}, /* run=199, turbo=398, PXbus=99, SDRAM=99 */ 101 {398100, 99500, 0x241, 0, CCLKCFG}, /* 199, 398, 99, 99 */
97 {0,} 102};
103
104#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
105#define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
106
107static struct cpufreq_frequency_table
108 pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
109static struct cpufreq_frequency_table
110 pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
111
112/*
113 * PXA270 definitions
114 *
115 * For the PXA27x:
116 * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
117 *
118 * A = 0 => memory controller clock from table 3-7,
119 * A = 1 => memory controller clock = system bus clock
120 * Run mode frequency = 13 MHz * L
121 * Turbo mode frequency = 13 MHz * L * N
122 * System bus frequency = 13 MHz * L / (B + 1)
123 *
124 * In CCCR:
125 * A = 1
126 * L = 16 oscillator to run mode ratio
127 * 2N = 6 2 * (turbo mode to run mode ratio)
128 *
129 * In CCLKCFG:
130 * B = 1 Fast bus mode
131 * HT = 0 Half-Turbo mode
132 * T = 1 Turbo mode
133 *
134 * For now, just support some of the combinations in table 3-7 of
135 * PXA27x Processor Family Developer's Manual to simplify frequency
136 * change sequences.
137 */
138#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
139#define CCLKCFG2(B, HT, T) \
140 (CCLKCFG_FCS | \
141 ((B) ? CCLKCFG_FASTBUS : 0) | \
142 ((HT) ? CCLKCFG_HALFTURBO : 0) | \
143 ((T) ? CCLKCFG_TURBO : 0))
144
145static pxa_freqs_t pxa27x_freqs[] = {
146 {104000, 104000, PXA27x_CCCR(1, 8, 2), 0, CCLKCFG2(1, 0, 1)},
147 {156000, 104000, PXA27x_CCCR(1, 8, 6), 0, CCLKCFG2(1, 1, 1)},
148 {208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1)},
149 {312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1)},
150 {416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1)},
151 {520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1)},
152 {624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1)}
98}; 153};
99#define NUM_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
100 154
101static struct cpufreq_frequency_table pxa255_turbo_freq_table[NUM_TURBO_FREQS+1]; 155#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
156static struct cpufreq_frequency_table
157 pxa27x_freq_table[NUM_PXA27x_FREQS+1];
102 158
103extern unsigned get_clk_frequency_khz(int info); 159extern unsigned get_clk_frequency_khz(int info);
104 160
161static void find_freq_tables(struct cpufreq_policy *policy,
162 struct cpufreq_frequency_table **freq_table,
163 pxa_freqs_t **pxa_freqs)
164{
165 if (cpu_is_pxa25x()) {
166 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
167 *pxa_freqs = pxa255_run_freqs;
168 *freq_table = pxa255_run_freq_table;
169 } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
170 *pxa_freqs = pxa255_turbo_freqs;
171 *freq_table = pxa255_turbo_freq_table;
172 } else {
173 printk("CPU PXA: Unknown policy found. "
174 "Using CPUFREQ_POLICY_PERFORMANCE\n");
175 *pxa_freqs = pxa255_run_freqs;
176 *freq_table = pxa255_run_freq_table;
177 }
178 }
179 if (cpu_is_pxa27x()) {
180 *pxa_freqs = pxa27x_freqs;
181 *freq_table = pxa27x_freq_table;
182 }
183}
184
185static void pxa27x_guess_max_freq(void)
186{
187 if (!pxa27x_maxfreq) {
188 pxa27x_maxfreq = 416000;
189 printk(KERN_INFO "PXA CPU 27x max frequency not defined "
190 "(pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
191 pxa27x_maxfreq);
192 } else {
193 pxa27x_maxfreq *= 1000;
194 }
195}
196
197static u32 mdrefr_dri(unsigned int freq)
198{
199 u32 dri = 0;
200
201 if (cpu_is_pxa25x())
202 dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS * 32));
203 if (cpu_is_pxa27x())
204 dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS - 31)) / 32;
205 return dri;
206}
207
105/* find a valid frequency point */ 208/* find a valid frequency point */
106static int pxa_verify_policy(struct cpufreq_policy *policy) 209static int pxa_verify_policy(struct cpufreq_policy *policy)
107{ 210{
108 struct cpufreq_frequency_table *pxa_freqs_table; 211 struct cpufreq_frequency_table *pxa_freqs_table;
212 pxa_freqs_t *pxa_freqs;
109 int ret; 213 int ret;
110 214
111 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { 215 find_freq_tables(policy, &pxa_freqs_table, &pxa_freqs);
112 pxa_freqs_table = pxa255_run_freq_table;
113 } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
114 pxa_freqs_table = pxa255_turbo_freq_table;
115 } else {
116 printk("CPU PXA: Unknown policy found. "
117 "Using CPUFREQ_POLICY_PERFORMANCE\n");
118 pxa_freqs_table = pxa255_run_freq_table;
119 }
120
121 ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table); 216 ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
122 217
123 if (freq_debug) 218 if (freq_debug)
124 pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n", 219 pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n",
125 policy->min, policy->max); 220 policy->min, policy->max);
126 221
127 return ret; 222 return ret;
128} 223}
129 224
225static unsigned int pxa_cpufreq_get(unsigned int cpu)
226{
227 return get_clk_frequency_khz(0);
228}
229
130static int pxa_set_target(struct cpufreq_policy *policy, 230static int pxa_set_target(struct cpufreq_policy *policy,
131 unsigned int target_freq, 231 unsigned int target_freq,
132 unsigned int relation) 232 unsigned int relation)
133{ 233{
134 struct cpufreq_frequency_table *pxa_freqs_table; 234 struct cpufreq_frequency_table *pxa_freqs_table;
135 pxa_freqs_t *pxa_freq_settings; 235 pxa_freqs_t *pxa_freq_settings;
136 struct cpufreq_freqs freqs; 236 struct cpufreq_freqs freqs;
137 unsigned int idx; 237 unsigned int idx;
138 unsigned long flags; 238 unsigned long flags;
139 unsigned int unused, preset_mdrefr, postset_mdrefr; 239 unsigned int new_freq_cpu, new_freq_mem;
140 void *ramstart = phys_to_virt(0xa0000000); 240 unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
141 241
142 /* Get the current policy */ 242 /* Get the current policy */
143 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) { 243 find_freq_tables(policy, &pxa_freqs_table, &pxa_freq_settings);
144 pxa_freq_settings = pxa255_run_freqs;
145 pxa_freqs_table = pxa255_run_freq_table;
146 } else if (policy->policy == CPUFREQ_POLICY_POWERSAVE) {
147 pxa_freq_settings = pxa255_turbo_freqs;
148 pxa_freqs_table = pxa255_turbo_freq_table;
149 } else {
150 printk("CPU PXA: Unknown policy found. "
151 "Using CPUFREQ_POLICY_PERFORMANCE\n");
152 pxa_freq_settings = pxa255_run_freqs;
153 pxa_freqs_table = pxa255_run_freq_table;
154 }
155 244
156 /* Lookup the next frequency */ 245 /* Lookup the next frequency */
157 if (cpufreq_frequency_table_target(policy, pxa_freqs_table, 246 if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
158 target_freq, relation, &idx)) { 247 target_freq, relation, &idx)) {
159 return -EINVAL; 248 return -EINVAL;
160 } 249 }
161 250
251 new_freq_cpu = pxa_freq_settings[idx].khz;
252 new_freq_mem = pxa_freq_settings[idx].membus;
162 freqs.old = policy->cur; 253 freqs.old = policy->cur;
163 freqs.new = pxa_freq_settings[idx].khz; 254 freqs.new = new_freq_cpu;
164 freqs.cpu = policy->cpu; 255 freqs.cpu = policy->cpu;
165 256
166 if (freq_debug) 257 if (freq_debug)
167 pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, (SDRAM %d Mhz)\n", 258 pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, "
168 freqs.new / 1000, (pxa_freq_settings[idx].div2) ? 259 "(SDRAM %d Mhz)\n",
169 (pxa_freq_settings[idx].membus / 2000) : 260 freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
170 (pxa_freq_settings[idx].membus / 1000)); 261 (new_freq_mem / 2000) : (new_freq_mem / 1000));
171 262
172 /* 263 /*
173 * Tell everyone what we're about to do... 264 * Tell everyone what we're about to do...
@@ -177,16 +268,16 @@ static int pxa_set_target(struct cpufreq_policy *policy,
177 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 268 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
178 269
179 /* Calculate the next MDREFR. If we're slowing down the SDRAM clock 270 /* Calculate the next MDREFR. If we're slowing down the SDRAM clock
180 * we need to preset the smaller DRI before the change. If we're speeding 271 * we need to preset the smaller DRI before the change. If we're
181 * up we need to set the larger DRI value after the change. 272 * speeding up we need to set the larger DRI value after the change.
182 */ 273 */
183 preset_mdrefr = postset_mdrefr = MDREFR; 274 preset_mdrefr = postset_mdrefr = MDREFR;
184 if ((MDREFR & MDREFR_DRI_MASK) > MDREFR_DRI(pxa_freq_settings[idx].membus)) { 275 if ((MDREFR & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
185 preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK) | 276 preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
186 MDREFR_DRI(pxa_freq_settings[idx].membus); 277 preset_mdrefr |= mdrefr_dri(new_freq_mem);
187 } 278 }
188 postset_mdrefr = (postset_mdrefr & ~MDREFR_DRI_MASK) | 279 postset_mdrefr =
189 MDREFR_DRI(pxa_freq_settings[idx].membus); 280 (postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem);
190 281
191 /* If we're dividing the memory clock by two for the SDRAM clock, this 282 /* If we're dividing the memory clock by two for the SDRAM clock, this
192 * must be set prior to the change. Clearing the divide must be done 283 * must be set prior to the change. Clearing the divide must be done
@@ -201,26 +292,27 @@ static int pxa_set_target(struct cpufreq_policy *policy,
201 292
202 local_irq_save(flags); 293 local_irq_save(flags);
203 294
204 /* Set new the CCCR */ 295 /* Set new the CCCR and prepare CCLKCFG */
205 CCCR = pxa_freq_settings[idx].cccr; 296 CCCR = pxa_freq_settings[idx].cccr;
297 cclkcfg = pxa_freq_settings[idx].cclkcfg;
206 298
207 asm volatile(" \n\ 299 asm volatile(" \n\
208 ldr r4, [%1] /* load MDREFR */ \n\ 300 ldr r4, [%1] /* load MDREFR */ \n\
209 b 2f \n\ 301 b 2f \n\
210 .align 5 \n\ 302 .align 5 \n\
2111: \n\ 3031: \n\
212 str %4, [%1] /* preset the MDREFR */ \n\ 304 str %3, [%1] /* preset the MDREFR */ \n\
213 mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\ 305 mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\
214 str %5, [%1] /* postset the MDREFR */ \n\ 306 str %4, [%1] /* postset the MDREFR */ \n\
215 \n\ 307 \n\
216 b 3f \n\ 308 b 3f \n\
2172: b 1b \n\ 3092: b 1b \n\
2183: nop \n\ 3103: nop \n\
219 " 311 "
220 : "=&r" (unused) 312 : "=&r" (unused)
221 : "r" (&MDREFR), "r" (CCLKCFG_TURBO|CCLKCFG_FCS), "r" (ramstart), 313 : "r" (&MDREFR), "r" (cclkcfg),
222 "r" (preset_mdrefr), "r" (postset_mdrefr) 314 "r" (preset_mdrefr), "r" (postset_mdrefr)
223 : "r4", "r5"); 315 : "r4", "r5");
224 local_irq_restore(flags); 316 local_irq_restore(flags);
225 317
226 /* 318 /*
@@ -233,38 +325,57 @@ static int pxa_set_target(struct cpufreq_policy *policy,
233 return 0; 325 return 0;
234} 326}
235 327
236static unsigned int pxa_cpufreq_get(unsigned int cpu) 328static __init int pxa_cpufreq_init(struct cpufreq_policy *policy)
237{
238 return get_clk_frequency_khz(0);
239}
240
241static int pxa_cpufreq_init(struct cpufreq_policy *policy)
242{ 329{
243 int i; 330 int i;
331 unsigned int freq;
332
333 /* try to guess pxa27x cpu */
334 if (cpu_is_pxa27x())
335 pxa27x_guess_max_freq();
244 336
245 /* set default policy and cpuinfo */ 337 /* set default policy and cpuinfo */
246 policy->governor = CPUFREQ_DEFAULT_GOVERNOR; 338 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
247 policy->policy = CPUFREQ_POLICY_PERFORMANCE; 339 if (cpu_is_pxa25x())
248 policy->cpuinfo.max_freq = PXA25x_MAX_FREQ; 340 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
249 policy->cpuinfo.min_freq = PXA25x_MIN_FREQ;
250 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ 341 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
251 policy->cur = get_clk_frequency_khz(0); /* current freq */ 342 policy->cur = get_clk_frequency_khz(0); /* current freq */
252 policy->min = policy->max = policy->cur; 343 policy->min = policy->max = policy->cur;
253 344
254 /* Generate the run cpufreq_frequency_table struct */ 345 /* Generate pxa25x the run cpufreq_frequency_table struct */
255 for (i = 0; i < NUM_RUN_FREQS; i++) { 346 for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
256 pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz; 347 pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
257 pxa255_run_freq_table[i].index = i; 348 pxa255_run_freq_table[i].index = i;
258 } 349 }
259
260 pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END; 350 pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
261 /* Generate the turbo cpufreq_frequency_table struct */ 351
262 for (i = 0; i < NUM_TURBO_FREQS; i++) { 352 /* Generate pxa25x the turbo cpufreq_frequency_table struct */
263 pxa255_turbo_freq_table[i].frequency = pxa255_turbo_freqs[i].khz; 353 for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
354 pxa255_turbo_freq_table[i].frequency =
355 pxa255_turbo_freqs[i].khz;
264 pxa255_turbo_freq_table[i].index = i; 356 pxa255_turbo_freq_table[i].index = i;
265 } 357 }
266 pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END; 358 pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
267 359
360 /* Generate the pxa27x cpufreq_frequency_table struct */
361 for (i = 0; i < NUM_PXA27x_FREQS; i++) {
362 freq = pxa27x_freqs[i].khz;
363 if (freq > pxa27x_maxfreq)
364 break;
365 pxa27x_freq_table[i].frequency = freq;
366 pxa27x_freq_table[i].index = i;
367 }
368 pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;
369
370 /*
371 * Set the policy's minimum and maximum frequencies from the tables
372 * just constructed. This sets cpuinfo.mxx_freq, min and max.
373 */
374 if (cpu_is_pxa25x())
375 cpufreq_frequency_table_cpuinfo(policy, pxa255_run_freq_table);
376 else if (cpu_is_pxa27x())
377 cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table);
378
268 printk(KERN_INFO "PXA CPU frequency change support initialized\n"); 379 printk(KERN_INFO "PXA CPU frequency change support initialized\n");
269 380
270 return 0; 381 return 0;
@@ -275,26 +386,25 @@ static struct cpufreq_driver pxa_cpufreq_driver = {
275 .target = pxa_set_target, 386 .target = pxa_set_target,
276 .init = pxa_cpufreq_init, 387 .init = pxa_cpufreq_init,
277 .get = pxa_cpufreq_get, 388 .get = pxa_cpufreq_get,
278 .name = "PXA25x", 389 .name = "PXA2xx",
279}; 390};
280 391
281static int __init pxa_cpu_init(void) 392static int __init pxa_cpu_init(void)
282{ 393{
283 int ret = -ENODEV; 394 int ret = -ENODEV;
284 if (cpu_is_pxa25x()) 395 if (cpu_is_pxa25x() || cpu_is_pxa27x())
285 ret = cpufreq_register_driver(&pxa_cpufreq_driver); 396 ret = cpufreq_register_driver(&pxa_cpufreq_driver);
286 return ret; 397 return ret;
287} 398}
288 399
289static void __exit pxa_cpu_exit(void) 400static void __exit pxa_cpu_exit(void)
290{ 401{
291 if (cpu_is_pxa25x()) 402 cpufreq_unregister_driver(&pxa_cpufreq_driver);
292 cpufreq_unregister_driver(&pxa_cpufreq_driver);
293} 403}
294 404
295 405
296MODULE_AUTHOR ("Intrinsyc Software Inc."); 406MODULE_AUTHOR("Intrinsyc Software Inc.");
297MODULE_DESCRIPTION ("CPU frequency changing driver for the PXA architecture"); 407MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
298MODULE_LICENSE("GPL"); 408MODULE_LICENSE("GPL");
299module_init(pxa_cpu_init); 409module_init(pxa_cpu_init);
300module_exit(pxa_cpu_exit); 410module_exit(pxa_cpu_exit);
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index edc4f07a230d..9c57700ee5c2 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -50,7 +50,7 @@ static struct resource em_x270_dm9k_resource[] = {
50 [2] = { 50 [2] = {
51 .start = EM_X270_ETHIRQ, 51 .start = EM_X270_ETHIRQ,
52 .end = EM_X270_ETHIRQ, 52 .end = EM_X270_ETHIRQ,
53 .flags = IORESOURCE_IRQ, 53 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
54 } 54 }
55}; 55};
56 56
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 0993f4d1a0bc..7b9bdd0c6665 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -396,7 +396,7 @@ static struct pxafb_mach_info sharp_lm8v31 = {
396 .cmap_inverse = 0, 396 .cmap_inverse = 0,
397 .cmap_static = 0, 397 .cmap_static = 0,
398 .lcd_conn = LCD_COLOR_DSTN_16BPP | LCD_PCLK_EDGE_FALL | 398 .lcd_conn = LCD_COLOR_DSTN_16BPP | LCD_PCLK_EDGE_FALL |
399 LCD_AC_BIAS_FREQ(255); 399 LCD_AC_BIAS_FREQ(255),
400}; 400};
401 401
402#define MMC_POLL_RATE msecs_to_jiffies(1000) 402#define MMC_POLL_RATE msecs_to_jiffies(1000)
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index ec1bbf333a3a..7d4debbdcca3 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -42,20 +42,17 @@ int pxa_pm_enter(suspend_state_t state)
42 if (state != PM_SUSPEND_STANDBY) { 42 if (state != PM_SUSPEND_STANDBY) {
43 pxa_cpu_pm_fns->save(sleep_save); 43 pxa_cpu_pm_fns->save(sleep_save);
44 /* before sleeping, calculate and save a checksum */ 44 /* before sleeping, calculate and save a checksum */
45 for (i = 0; i < pxa_cpu_pm_fns->save_size - 1; i++) 45 for (i = 0; i < pxa_cpu_pm_fns->save_count - 1; i++)
46 sleep_save_checksum += sleep_save[i]; 46 sleep_save_checksum += sleep_save[i];
47 } 47 }
48 48
49 /* Clear reset status */
50 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
51
52 /* *** go zzz *** */ 49 /* *** go zzz *** */
53 pxa_cpu_pm_fns->enter(state); 50 pxa_cpu_pm_fns->enter(state);
54 cpu_init(); 51 cpu_init();
55 52
56 if (state != PM_SUSPEND_STANDBY) { 53 if (state != PM_SUSPEND_STANDBY) {
57 /* after sleeping, validate the checksum */ 54 /* after sleeping, validate the checksum */
58 for (i = 0; i < pxa_cpu_pm_fns->save_size - 1; i++) 55 for (i = 0; i < pxa_cpu_pm_fns->save_count - 1; i++)
59 checksum += sleep_save[i]; 56 checksum += sleep_save[i];
60 57
61 /* if invalid, display message and wait for a hardware reset */ 58 /* if invalid, display message and wait for a hardware reset */
@@ -101,7 +98,8 @@ static int __init pxa_pm_init(void)
101 return -EINVAL; 98 return -EINVAL;
102 } 99 }
103 100
104 sleep_save = kmalloc(pxa_cpu_pm_fns->save_size, GFP_KERNEL); 101 sleep_save = kmalloc(pxa_cpu_pm_fns->save_count * sizeof(unsigned long),
102 GFP_KERNEL);
105 if (!sleep_save) { 103 if (!sleep_save) {
106 printk(KERN_ERR "failed to alloc memory for pm save\n"); 104 printk(KERN_ERR "failed to alloc memory for pm save\n");
107 return -ENOMEM; 105 return -ENOMEM;
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index ca5ac196b47b..0b30f25cff3c 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -326,13 +326,11 @@ static struct platform_device *devices[] __initdata = {
326 326
327static void poodle_poweroff(void) 327static void poodle_poweroff(void)
328{ 328{
329 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
330 arm_machine_restart('h'); 329 arm_machine_restart('h');
331} 330}
332 331
333static void poodle_restart(char mode) 332static void poodle_restart(char mode)
334{ 333{
335 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
336 arm_machine_restart('h'); 334 arm_machine_restart('h');
337} 335}
338 336
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index d9b5450aee5b..e5b417d14bb0 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -150,9 +150,7 @@ static struct clk pxa25x_clks[] = {
150 * More ones like CP and general purpose register values are preserved 150 * More ones like CP and general purpose register values are preserved
151 * with the stack pointer in sleep.S. 151 * with the stack pointer in sleep.S.
152 */ 152 */
153enum { SLEEP_SAVE_START = 0, 153enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
154
155 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
156 154
157 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, 155 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
158 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, 156 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
@@ -162,7 +160,7 @@ enum { SLEEP_SAVE_START = 0,
162 160
163 SLEEP_SAVE_CKEN, 161 SLEEP_SAVE_CKEN,
164 162
165 SLEEP_SAVE_SIZE 163 SLEEP_SAVE_COUNT
166}; 164};
167 165
168 166
@@ -200,6 +198,9 @@ static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
200 198
201static void pxa25x_cpu_pm_enter(suspend_state_t state) 199static void pxa25x_cpu_pm_enter(suspend_state_t state)
202{ 200{
201 /* Clear reset status */
202 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
203
203 switch (state) { 204 switch (state) {
204 case PM_SUSPEND_MEM: 205 case PM_SUSPEND_MEM:
205 /* set resume return address */ 206 /* set resume return address */
@@ -210,7 +211,7 @@ static void pxa25x_cpu_pm_enter(suspend_state_t state)
210} 211}
211 212
212static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = { 213static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
213 .save_size = SLEEP_SAVE_SIZE, 214 .save_count = SLEEP_SAVE_COUNT,
214 .valid = suspend_valid_only_mem, 215 .valid = suspend_valid_only_mem,
215 .save = pxa25x_cpu_pm_save, 216 .save = pxa25x_cpu_pm_save,
216 .restore = pxa25x_cpu_pm_restore, 217 .restore = pxa25x_cpu_pm_restore,
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 7a2449dd0fd4..7e945836e129 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -181,9 +181,7 @@ static struct clk pxa27x_clks[] = {
181 * More ones like CP and general purpose register values are preserved 181 * More ones like CP and general purpose register values are preserved
182 * with the stack pointer in sleep.S. 182 * with the stack pointer in sleep.S.
183 */ 183 */
184enum { SLEEP_SAVE_START = 0, 184enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
185
186 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
187 185
188 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U, 186 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
189 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U, 187 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
@@ -198,7 +196,7 @@ enum { SLEEP_SAVE_START = 0,
198 SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER, 196 SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
199 SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR, 197 SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
200 198
201 SLEEP_SAVE_SIZE 199 SLEEP_SAVE_COUNT
202}; 200};
203 201
204void pxa27x_cpu_pm_save(unsigned long *sleep_save) 202void pxa27x_cpu_pm_save(unsigned long *sleep_save)
@@ -251,6 +249,9 @@ void pxa27x_cpu_pm_enter(suspend_state_t state)
251 /* Clear edge-detect status register. */ 249 /* Clear edge-detect status register. */
252 PEDR = 0xDF12FE1B; 250 PEDR = 0xDF12FE1B;
253 251
252 /* Clear reset status */
253 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
254
254 switch (state) { 255 switch (state) {
255 case PM_SUSPEND_STANDBY: 256 case PM_SUSPEND_STANDBY:
256 pxa_cpu_standby(); 257 pxa_cpu_standby();
@@ -269,7 +270,7 @@ static int pxa27x_cpu_pm_valid(suspend_state_t state)
269} 270}
270 271
271static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = { 272static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
272 .save_size = SLEEP_SAVE_SIZE, 273 .save_count = SLEEP_SAVE_COUNT,
273 .save = pxa27x_cpu_pm_save, 274 .save = pxa27x_cpu_pm_save,
274 .restore = pxa27x_cpu_pm_restore, 275 .restore = pxa27x_cpu_pm_restore,
275 .valid = pxa27x_cpu_pm_valid, 276 .valid = pxa27x_cpu_pm_valid,
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index b6a6f5fcc77a..644550bfa330 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -256,12 +256,11 @@ static unsigned long wakeup_src;
256#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 256#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
257#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 257#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
258 258
259enum { SLEEP_SAVE_START = 0, 259enum { SLEEP_SAVE_CKENA,
260 SLEEP_SAVE_CKENA,
261 SLEEP_SAVE_CKENB, 260 SLEEP_SAVE_CKENB,
262 SLEEP_SAVE_ACCR, 261 SLEEP_SAVE_ACCR,
263 262
264 SLEEP_SAVE_SIZE, 263 SLEEP_SAVE_COUNT,
265}; 264};
266 265
267static void pxa3xx_cpu_pm_save(unsigned long *sleep_save) 266static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
@@ -376,7 +375,7 @@ static int pxa3xx_cpu_pm_valid(suspend_state_t state)
376} 375}
377 376
378static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { 377static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
379 .save_size = SLEEP_SAVE_SIZE, 378 .save_count = SLEEP_SAVE_COUNT,
380 .save = pxa3xx_cpu_pm_save, 379 .save = pxa3xx_cpu_pm_save,
381 .restore = pxa3xx_cpu_pm_restore, 380 .restore = pxa3xx_cpu_pm_restore,
382 .valid = pxa3xx_cpu_pm_valid, 381 .valid = pxa3xx_cpu_pm_valid,
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 62a02c3927c5..e7d0fcd9b43f 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -529,8 +529,6 @@ static struct platform_device *devices[] __initdata = {
529 529
530static void spitz_poweroff(void) 530static void spitz_poweroff(void)
531{ 531{
532 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
533
534 pxa_gpio_mode(SPITZ_GPIO_ON_RESET | GPIO_OUT); 532 pxa_gpio_mode(SPITZ_GPIO_ON_RESET | GPIO_OUT);
535 GPSR(SPITZ_GPIO_ON_RESET) = GPIO_bit(SPITZ_GPIO_ON_RESET); 533 GPSR(SPITZ_GPIO_ON_RESET) = GPIO_bit(SPITZ_GPIO_ON_RESET);
536 534
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 7a7f5f947cc5..23f050feb208 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -119,9 +119,6 @@ static void spitz_presuspend(void)
119 /* nRESET_OUT Disable */ 119 /* nRESET_OUT Disable */
120 PSLR |= PSLR_SL_ROD; 120 PSLR |= PSLR_SL_ROD;
121 121
122 /* Clear reset status */
123 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
124
125 /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */ 122 /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
126 PCFR = PCFR_GPR_EN | PCFR_OPDE; 123 PCFR = PCFR_GPR_EN | PCFR_OPDE;
127} 124}
diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c
index 00af7f2fed66..0bb31982fb6f 100644
--- a/arch/arm/mach-pxa/ssp.c
+++ b/arch/arm/mach-pxa/ssp.c
@@ -330,7 +330,7 @@ struct ssp_device *ssp_request(int port, const char *label)
330 330
331 mutex_unlock(&ssp_lock); 331 mutex_unlock(&ssp_lock);
332 332
333 if (ssp->port_id != port) 333 if (&ssp->node == &ssp_list)
334 return NULL; 334 return NULL;
335 335
336 return ssp; 336 return ssp;
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 6458f6d371d9..ab4a9f579913 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -467,10 +467,8 @@ static struct platform_device *devices[] __initdata = {
467 467
468static void tosa_poweroff(void) 468static void tosa_poweroff(void)
469{ 469{
470 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR; 470 gpio_direction_output(TOSA_GPIO_ON_RESET, 0);
471 471 gpio_set_value(TOSA_GPIO_ON_RESET, 1);
472 pxa_gpio_mode(TOSA_GPIO_ON_RESET | GPIO_OUT);
473 GPSR(TOSA_GPIO_ON_RESET) = GPIO_bit(TOSA_GPIO_ON_RESET);
474 472
475 mdelay(1000); 473 mdelay(1000);
476 arm_machine_restart('h'); 474 arm_machine_restart('h');
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index 3e57428affee..8e813ed57519 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -74,6 +74,8 @@ static DEFINE_SPINLOCK(boot_lock);
74 74
75void __cpuinit platform_secondary_init(unsigned int cpu) 75void __cpuinit platform_secondary_init(unsigned int cpu)
76{ 76{
77 trace_hardirqs_off();
78
77 /* 79 /*
78 * the primary core may have used a "cross call" soft interrupt 80 * the primary core may have used a "cross call" soft interrupt
79 * to get this processor out of WFI in the BootMonitor - make 81 * to get this processor out of WFI in the BootMonitor - make
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 661a2358ac22..27f63d5d3a7b 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -374,7 +374,7 @@ static struct resource bast_dm9k_resource[] = {
374 [2] = { 374 [2] = {
375 .start = IRQ_DM9000, 375 .start = IRQ_DM9000,
376 .end = IRQ_DM9000, 376 .end = IRQ_DM9000,
377 .flags = IORESOURCE_IRQ, 377 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
378 } 378 }
379 379
380}; 380};
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index c56423373ff3..4c4b5c4207c4 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -263,7 +263,7 @@ static struct resource vr1000_dm9k0_resource[] = {
263 [2] = { 263 [2] = {
264 .start = IRQ_VR1000_DM9000A, 264 .start = IRQ_VR1000_DM9000A,
265 .end = IRQ_VR1000_DM9000A, 265 .end = IRQ_VR1000_DM9000A,
266 .flags = IORESOURCE_IRQ 266 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
267 } 267 }
268 268
269}; 269};
@@ -282,7 +282,7 @@ static struct resource vr1000_dm9k1_resource[] = {
282 [2] = { 282 [2] = {
283 .start = IRQ_VR1000_DM9000N, 283 .start = IRQ_VR1000_DM9000N,
284 .end = IRQ_VR1000_DM9000N, 284 .end = IRQ_VR1000_DM9000N,
285 .flags = IORESOURCE_IRQ 285 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
286 } 286 }
287}; 287};
288 288
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index 6496eb645cee..2f772a3965c4 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -225,26 +225,28 @@ static void __init collie_init(void)
225 int ret = 0; 225 int ret = 0;
226 226
227 /* cpu initialize */ 227 /* cpu initialize */
228 GAFR = ( GPIO_SSP_TXD | \ 228 GAFR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM | GPIO_SSP_CLK |
229 GPIO_SSP_SCLK | GPIO_SSP_SFRM | GPIO_SSP_CLK | GPIO_TIC_ACK | \ 229 GPIO_MCP_CLK | GPIO_32_768kHz;
230 GPIO_32_768kHz ); 230
231 231 GPDR = GPIO_LDD8 | GPIO_LDD9 | GPIO_LDD10 | GPIO_LDD11 | GPIO_LDD12 |
232 GPDR = ( GPIO_LDD8 | GPIO_LDD9 | GPIO_LDD10 | GPIO_LDD11 | GPIO_LDD12 | \ 232 GPIO_LDD13 | GPIO_LDD14 | GPIO_LDD15 | GPIO_SSP_TXD |
233 GPIO_LDD13 | GPIO_LDD14 | GPIO_LDD15 | GPIO_SSP_TXD | \ 233 GPIO_SSP_SCLK | GPIO_SSP_SFRM | GPIO_SDLC_SCLK |
234 GPIO_SSP_SCLK | GPIO_SSP_SFRM | GPIO_SDLC_SCLK | \ 234 COLLIE_GPIO_UCB1x00_RESET | COLLIE_GPIO_nMIC_ON |
235 GPIO_SDLC_AAF | GPIO_UART_SCLK1 | GPIO_32_768kHz ); 235 COLLIE_GPIO_nREMOCON_ON | GPIO_32_768kHz;
236 GPLR = GPIO_GPIO18; 236
237 237 PPDR = PPC_LDD0 | PPC_LDD1 | PPC_LDD2 | PPC_LDD3 | PPC_LDD4 | PPC_LDD5 |
238 // PPC pin setting 238 PPC_LDD6 | PPC_LDD7 | PPC_L_PCLK | PPC_L_LCLK | PPC_L_FCLK | PPC_L_BIAS |
239 PPDR = ( PPC_LDD0 | PPC_LDD1 | PPC_LDD2 | PPC_LDD3 | PPC_LDD4 | PPC_LDD5 | \ 239 PPC_TXD1 | PPC_TXD2 | PPC_TXD3 | PPC_TXD4 | PPC_SCLK | PPC_SFRM;
240 PPC_LDD6 | PPC_LDD7 | PPC_L_PCLK | PPC_L_LCLK | PPC_L_FCLK | PPC_L_BIAS | \ 240
241 PPC_TXD1 | PPC_TXD2 | PPC_RXD2 | PPC_TXD3 | PPC_TXD4 | PPC_SCLK | PPC_SFRM ); 241 PWER = COLLIE_GPIO_AC_IN | COLLIE_GPIO_CO | COLLIE_GPIO_ON_KEY |
242 242 COLLIE_GPIO_WAKEUP | COLLIE_GPIO_nREMOCON_INT | PWER_RTC;
243 PSDR = ( PPC_RXD1 | PPC_RXD2 | PPC_RXD3 | PPC_RXD4 ); 243
244 244 PGSR = COLLIE_GPIO_nREMOCON_ON;
245 GAFR |= GPIO_32_768kHz; 245
246 GPDR |= GPIO_32_768kHz; 246 PSDR = PPC_RXD1 | PPC_RXD2 | PPC_RXD3 | PPC_RXD4;
247 TUCR = TUCR_32_768kHz; 247
248 PCFR = PCFR_OPDE;
249
248 250
249 platform_scoop_config = &collie_pcmcia_config; 251 platform_scoop_config = &collie_pcmcia_config;
250 252
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index 246c573e7252..1693d447a224 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -43,20 +43,18 @@ extern void sa1100_cpu_resume(void);
43 * More ones like CP and general purpose register values are preserved 43 * More ones like CP and general purpose register values are preserved
44 * on the stack and then the stack pointer is stored last in sleep.S. 44 * on the stack and then the stack pointer is stored last in sleep.S.
45 */ 45 */
46enum { SLEEP_SAVE_SP = 0, 46enum { SLEEP_SAVE_GPDR, SLEEP_SAVE_GAFR,
47
48 SLEEP_SAVE_GPDR, SLEEP_SAVE_GAFR,
49 SLEEP_SAVE_PPDR, SLEEP_SAVE_PPSR, SLEEP_SAVE_PPAR, SLEEP_SAVE_PSDR, 47 SLEEP_SAVE_PPDR, SLEEP_SAVE_PPSR, SLEEP_SAVE_PPAR, SLEEP_SAVE_PSDR,
50 48
51 SLEEP_SAVE_Ser1SDCR0, 49 SLEEP_SAVE_Ser1SDCR0,
52 50
53 SLEEP_SAVE_SIZE 51 SLEEP_SAVE_COUNT
54}; 52};
55 53
56 54
57static int sa11x0_pm_enter(suspend_state_t state) 55static int sa11x0_pm_enter(suspend_state_t state)
58{ 56{
59 unsigned long gpio, sleep_save[SLEEP_SAVE_SIZE]; 57 unsigned long gpio, sleep_save[SLEEP_SAVE_COUNT];
60 58
61 gpio = GPLR; 59 gpio = GPLR;
62 60
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 065087afb772..d045812f3399 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -332,7 +332,7 @@ ENTRY(arm925_dma_flush_range)
332#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 332#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
333 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 333 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
334#else 334#else
335 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 335 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
336#endif 336#endif
337 add r0, r0, #CACHE_DLINESIZE 337 add r0, r0, #CACHE_DLINESIZE
338 cmp r0, r1 338 cmp r0, r1
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 997db8472b5c..4cd33169a7c9 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -295,7 +295,7 @@ ENTRY(arm926_dma_flush_range)
295#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 295#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
296 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 296 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
297#else 297#else
298 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 298 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
299#endif 299#endif
300 add r0, r0, #CACHE_DLINESIZE 300 add r0, r0, #CACHE_DLINESIZE
301 cmp r0, r1 301 cmp r0, r1
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 44ead902bd54..1a3d63df8e90 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -222,7 +222,7 @@ ENTRY(arm940_dma_flush_range)
222#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 222#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
223 mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry 223 mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry
224#else 224#else
225 mcr p15, 0, r3, c7, c10, 2 @ clean D entry 225 mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
226#endif 226#endif
227 subs r3, r3, #1 << 26 227 subs r3, r3, #1 << 26
228 bcs 2b @ entries 63 to 0 228 bcs 2b @ entries 63 to 0
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 2218b0c01330..82d579ac9b98 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -265,7 +265,7 @@ ENTRY(arm946_dma_flush_range)
265#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH 265#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
266 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 266 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
267#else 267#else
268 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 268 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
269#endif 269#endif
270 add r0, r0, #CACHE_DLINESIZE 270 add r0, r0, #CACHE_DLINESIZE
271 cmp r0, r1 271 cmp r0, r1
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 72d34a23a2ec..2db5580048d8 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -21,6 +21,7 @@
21#include <linux/clk.h> 21#include <linux/clk.h>
22#include <linux/mutex.h> 22#include <linux/mutex.h>
23#include <linux/platform_device.h> 23#include <linux/platform_device.h>
24#include <linux/cpufreq.h>
24 25
25#include <asm/io.h> 26#include <asm/io.h>
26 27
@@ -134,9 +135,17 @@ void clk_disable(struct clk *clk)
134 return; 135 return;
135 136
136 spin_lock_irqsave(&clockfw_lock, flags); 137 spin_lock_irqsave(&clockfw_lock, flags);
137 BUG_ON(clk->usecount == 0); 138 if (clk->usecount == 0) {
139 printk(KERN_ERR "Trying disable clock %s with 0 usecount\n",
140 clk->name);
141 WARN_ON(1);
142 goto out;
143 }
144
138 if (arch_clock->clk_disable) 145 if (arch_clock->clk_disable)
139 arch_clock->clk_disable(clk); 146 arch_clock->clk_disable(clk);
147
148out:
140 spin_unlock_irqrestore(&clockfw_lock, flags); 149 spin_unlock_irqrestore(&clockfw_lock, flags);
141} 150}
142EXPORT_SYMBOL(clk_disable); 151EXPORT_SYMBOL(clk_disable);
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 793740686be2..39c637b0ffea 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -501,8 +501,6 @@ static inline void omap_enable_channel_irq(int lch)
501 501
502 /* Enable some nice interrupts. */ 502 /* Enable some nice interrupts. */
503 OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs; 503 OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs;
504
505 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
506} 504}
507 505
508static void omap_disable_channel_irq(int lch) 506static void omap_disable_channel_irq(int lch)
@@ -604,6 +602,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
604 chan->data = data; 602 chan->data = data;
605#ifndef CONFIG_ARCH_OMAP1 603#ifndef CONFIG_ARCH_OMAP1
606 chan->chain_id = -1; 604 chan->chain_id = -1;
605 chan->next_linked_ch = -1;
607#endif 606#endif
608 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; 607 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
609 608
@@ -1087,7 +1086,6 @@ int omap_request_dma_chain(int dev_id, const char *dev_name,
1087 printk(KERN_ERR "omap_dma: Request failed %d\n", err); 1086 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1088 return err; 1087 return err;
1089 } 1088 }
1090 dma_chan[channels[i]].next_linked_ch = -1;
1091 dma_chan[channels[i]].prev_linked_ch = -1; 1089 dma_chan[channels[i]].prev_linked_ch = -1;
1092 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED; 1090 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1093 1091
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 1945ddfec18d..6f33f58bca45 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -355,7 +355,6 @@ static int omap_mbox_init(struct omap_mbox *mbox)
355 "failed to register mailbox interrupt:%d\n", ret); 355 "failed to register mailbox interrupt:%d\n", ret);
356 goto fail_request_irq; 356 goto fail_request_irq;
357 } 357 }
358 enable_mbox_irq(mbox, IRQ_RX);
359 358
360 mq = mbox_queue_alloc(mbox, mbox_txq_fn, mbox_tx_work); 359 mq = mbox_queue_alloc(mbox, mbox_txq_fn, mbox_tx_work);
361 if (!mq) { 360 if (!mq) {
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c
index d84167fb33b1..3ac8d8d781b3 100644
--- a/arch/arm/plat-s3c24xx/clock.c
+++ b/arch/arm/plat-s3c24xx/clock.c
@@ -411,7 +411,7 @@ static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
411 411
412 clk->parent = parent; 412 clk->parent = parent;
413 413
414 if (clk == &s3c24xx_dclk0) 414 if (clk == &s3c24xx_clkout0)
415 mask = S3C2410_MISCCR_CLK0_MASK; 415 mask = S3C2410_MISCCR_CLK0_MASK;
416 else { 416 else {
417 source <<= 4; 417 source <<= 4;
@@ -437,7 +437,7 @@ struct clk s3c24xx_dclk0 = {
437struct clk s3c24xx_dclk1 = { 437struct clk s3c24xx_dclk1 = {
438 .name = "dclk1", 438 .name = "dclk1",
439 .id = -1, 439 .id = -1,
440 .ctrlbit = S3C2410_DCLKCON_DCLK0EN, 440 .ctrlbit = S3C2410_DCLKCON_DCLK1EN,
441 .enable = s3c24xx_dclk_enable, 441 .enable = s3c24xx_dclk_enable,
442 .set_parent = s3c24xx_dclk_setparent, 442 .set_parent = s3c24xx_dclk_setparent,
443 .set_rate = s3c24xx_set_dclk_rate, 443 .set_rate = s3c24xx_set_dclk_rate,
diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c
index f197bb3a2366..2f01af5f64c4 100644
--- a/arch/arm/plat-s3c24xx/s3c244x.c
+++ b/arch/arm/plat-s3c24xx/s3c244x.c
@@ -65,6 +65,7 @@ void __init s3c244x_map_io(struct map_desc *mach_desc, int size)
65 65
66 /* rename any peripherals used differing from the s3c2410 */ 66 /* rename any peripherals used differing from the s3c2410 */
67 67
68 s3c_device_sdi.name = "s3c2440-sdi";
68 s3c_device_i2c.name = "s3c2440-i2c"; 69 s3c_device_i2c.name = "s3c2440-i2c";
69 s3c_device_nand.name = "s3c2440-nand"; 70 s3c_device_nand.name = "s3c2440-nand";
70 s3c_device_usbgadget.name = "s3c2440-usbgadget"; 71 s3c_device_usbgadget.name = "s3c2440-usbgadget";
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-08 20:34:41 -0400