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authorTony Lindgren <tony@atomide.com>2011-02-25 15:27:14 -0500
committerTony Lindgren <tony@atomide.com>2011-02-25 15:27:14 -0500
commit02fa9f0451ac639a687bfc145eefe58703ff220e (patch)
treefe984acc78f22f6eb8fb98efaba8b1ac2f3ad8d9 /arch/arm
parentcbc9438075ca9dee3f39a2e7310f81c304b40359 (diff)
parent51c404b2c514930e98e81e0b9294f19892a4f871 (diff)
Merge branch 'patches_for_2.6.38rc' of git://git.pwsan.com/linux-2.6 into devel-fixes
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig27
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/boot/compressed/.gitignore6
-rw-r--r--arch/arm/include/asm/hardware/cache-l2x0.h1
-rw-r--r--arch/arm/include/asm/hardware/sp810.h3
-rw-r--r--arch/arm/include/asm/io.h33
-rw-r--r--arch/arm/include/asm/tlb.h105
-rw-r--r--arch/arm/include/asm/tlbflush.h7
-rw-r--r--arch/arm/kernel/head.S60
-rw-r--r--arch/arm/kernel/hw_breakpoint.c44
-rw-r--r--arch/arm/kernel/kprobes-decode.c2
-rw-r--r--arch/arm/kernel/module.c22
-rw-r--r--arch/arm/kernel/perf_event.c2
-rw-r--r--arch/arm/kernel/pmu.c22
-rw-r--r--arch/arm/kernel/setup.c4
-rw-r--r--arch/arm/kernel/signal.c4
-rw-r--r--arch/arm/kernel/vmlinux.lds.S11
-rw-r--r--arch/arm/mach-ep93xx/core.c2
-rw-r--r--arch/arm/mach-footbridge/include/mach/debug-macro.S4
-rw-r--r--arch/arm/mach-imx/mach-mx25_3ds.c2
-rw-r--r--arch/arm/mach-ixp4xx/common.c4
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/timex.h5
-rw-r--r--arch/arm/mach-ixp4xx/ixp4xx_qmgr.c9
-rw-r--r--arch/arm/mach-mxs/clock-mx23.c4
-rw-r--r--arch/arm/mach-mxs/clock-mx28.c7
-rw-r--r--arch/arm/mach-mxs/clock.c2
-rw-r--r--arch/arm/mach-mxs/gpio.c2
-rw-r--r--arch/arm/mach-mxs/include/mach/clock.h2
-rw-r--r--arch/arm/mach-omap2/clkt_dpll.c2
-rw-r--r--arch/arm/mach-omap2/prcm_mpu44xx.h4
-rw-r--r--arch/arm/mach-pxa/colibri-evalboard.c2
-rw-r--r--arch/arm/mach-pxa/colibri-pxa300.c2
-rw-r--r--arch/arm/mach-pxa/include/mach/colibri.h2
-rw-r--r--arch/arm/mach-pxa/palm27x.c2
-rw-r--r--arch/arm/mach-pxa/pm.c4
-rw-r--r--arch/arm/mach-s5p6442/include/mach/map.h69
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/map.h83
-rw-r--r--arch/arm/mach-s5pc100/include/mach/map.h193
-rw-r--r--arch/arm/mach-s5pv210/include/mach/map.h168
-rw-r--r--arch/arm/mach-s5pv210/mach-aquila.c15
-rw-r--r--arch/arm/mach-s5pv210/mach-goni.c15
-rw-r--r--arch/arm/mach-s5pv310/Kconfig1
-rw-r--r--arch/arm/mach-s5pv310/include/mach/map.h151
-rw-r--r--arch/arm/mach-s5pv310/include/mach/sysmmu.h5
-rw-r--r--arch/arm/mach-sa1100/collie.c3
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear320.h2
-rw-r--r--arch/arm/mach-tegra/gpio.c4
-rw-r--r--arch/arm/mach-tegra/include/mach/clk.h2
-rw-r--r--arch/arm/mach-tegra/include/mach/clkdev.h2
-rw-r--r--arch/arm/mach-tegra/irq.c18
-rw-r--r--arch/arm/mm/Kconfig6
-rw-r--r--arch/arm/mm/cache-l2x0.c6
-rw-r--r--arch/arm/mm/init.c6
-rw-r--r--arch/arm/mm/proc-v7.S6
-rw-r--r--arch/arm/oprofile/common.c14
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h2
-rw-r--r--arch/arm/plat-pxa/mfp.c8
-rw-r--r--arch/arm/plat-s5p/Kconfig24
-rw-r--r--arch/arm/plat-s5p/Makefile2
-rw-r--r--arch/arm/plat-s5p/dev-uart.c12
-rw-r--r--arch/arm/plat-s5p/include/plat/sysmmu.h23
-rw-r--r--arch/arm/plat-s5p/sysmmu.c4
-rw-r--r--arch/arm/plat-samsung/dev-ts.c1
-rw-r--r--arch/arm/plat-samsung/include/plat/pm.h2
-rw-r--r--arch/arm/plat-spear/include/plat/uncompress.h4
-rw-r--r--arch/arm/plat-spear/include/plat/vmalloc.h2
-rw-r--r--arch/arm/tools/mach-types105
67 files changed, 805 insertions, 569 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5cff165b7eb0..166efa2a19cd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1177,6 +1177,31 @@ config ARM_ERRATA_743622
1177 visible impact on the overall performance or power consumption of the 1177 visible impact on the overall performance or power consumption of the
1178 processor. 1178 processor.
1179 1179
1180config ARM_ERRATA_751472
1181 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1182 depends on CPU_V7 && SMP
1183 help
1184 This option enables the workaround for the 751472 Cortex-A9 (prior
1185 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1186 completion of a following broadcasted operation if the second
1187 operation is received by a CPU before the ICIALLUIS has completed,
1188 potentially leading to corrupted entries in the cache or TLB.
1189
1190config ARM_ERRATA_753970
1191 bool "ARM errata: cache sync operation may be faulty"
1192 depends on CACHE_PL310
1193 help
1194 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1195
1196 Under some condition the effect of cache sync operation on
1197 the store buffer still remains when the operation completes.
1198 This means that the store buffer is always asked to drain and
1199 this prevents it from merging any further writes. The workaround
1200 is to replace the normal offset of cache sync operation (0x730)
1201 by another offset targeting an unmapped PL310 register 0x740.
1202 This has the same effect as the cache sync operation: store buffer
1203 drain and waiting for all buffers empty.
1204
1180endmenu 1205endmenu
1181 1206
1182source "arch/arm/common/Kconfig" 1207source "arch/arm/common/Kconfig"
@@ -1391,7 +1416,7 @@ config AEABI
1391 1416
1392config OABI_COMPAT 1417config OABI_COMPAT
1393 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1418 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1394 depends on AEABI && EXPERIMENTAL 1419 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1395 default y 1420 default y
1396 help 1421 help
1397 This option preserves the old syscall interface along with the 1422 This option preserves the old syscall interface along with the
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c22c1adfedd6..6f7b29294c80 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -15,7 +15,7 @@ ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
15LDFLAGS_vmlinux += --be8 15LDFLAGS_vmlinux += --be8
16endif 16endif
17 17
18OBJCOPYFLAGS :=-O binary -R .note -R .note.gnu.build-id -R .comment -S 18OBJCOPYFLAGS :=-O binary -R .comment -S
19GZFLAGS :=-9 19GZFLAGS :=-9
20#KBUILD_CFLAGS +=-pipe 20#KBUILD_CFLAGS +=-pipe
21# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb: 21# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore
index ab204db594d3..c6028967d336 100644
--- a/arch/arm/boot/compressed/.gitignore
+++ b/arch/arm/boot/compressed/.gitignore
@@ -1,3 +1,7 @@
1font.c 1font.c
2piggy.gz 2lib1funcs.S
3piggy.gzip
4piggy.lzo
5piggy.lzma
6vmlinux
3vmlinux.lds 7vmlinux.lds
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 5aeec1e1735c..16bd48031583 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -36,6 +36,7 @@
36#define L2X0_RAW_INTR_STAT 0x21C 36#define L2X0_RAW_INTR_STAT 0x21C
37#define L2X0_INTR_CLEAR 0x220 37#define L2X0_INTR_CLEAR 0x220
38#define L2X0_CACHE_SYNC 0x730 38#define L2X0_CACHE_SYNC 0x730
39#define L2X0_DUMMY_REG 0x740
39#define L2X0_INV_LINE_PA 0x770 40#define L2X0_INV_LINE_PA 0x770
40#define L2X0_INV_WAY 0x77C 41#define L2X0_INV_WAY 0x77C
41#define L2X0_CLEAN_LINE_PA 0x7B0 42#define L2X0_CLEAN_LINE_PA 0x7B0
diff --git a/arch/arm/include/asm/hardware/sp810.h b/arch/arm/include/asm/hardware/sp810.h
index 721847dc68ab..e0d1c0cfa548 100644
--- a/arch/arm/include/asm/hardware/sp810.h
+++ b/arch/arm/include/asm/hardware/sp810.h
@@ -58,6 +58,9 @@
58 58
59static inline void sysctl_soft_reset(void __iomem *base) 59static inline void sysctl_soft_reset(void __iomem *base)
60{ 60{
61 /* switch to slow mode */
62 writel(0x2, base + SCCTRL);
63
61 /* writing any value to SCSYSSTAT reg will reset system */ 64 /* writing any value to SCSYSSTAT reg will reset system */
62 writel(0, base + SCSYSSTAT); 65 writel(0, base + SCSYSSTAT);
63} 66}
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 20e0f7c9e03e..d66605dea55a 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -95,6 +95,15 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
95 return (void __iomem *)addr; 95 return (void __iomem *)addr;
96} 96}
97 97
98/* IO barriers */
99#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
100#define __iormb() rmb()
101#define __iowmb() wmb()
102#else
103#define __iormb() do { } while (0)
104#define __iowmb() do { } while (0)
105#endif
106
98/* 107/*
99 * Now, pick up the machine-defined IO definitions 108 * Now, pick up the machine-defined IO definitions
100 */ 109 */
@@ -125,17 +134,17 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
125 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. 134 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
126 */ 135 */
127#ifdef __io 136#ifdef __io
128#define outb(v,p) __raw_writeb(v,__io(p)) 137#define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); })
129#define outw(v,p) __raw_writew((__force __u16) \ 138#define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \
130 cpu_to_le16(v),__io(p)) 139 cpu_to_le16(v),__io(p)); })
131#define outl(v,p) __raw_writel((__force __u32) \ 140#define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
132 cpu_to_le32(v),__io(p)) 141 cpu_to_le32(v),__io(p)); })
133 142
134#define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __v; }) 143#define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
135#define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \ 144#define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
136 __raw_readw(__io(p))); __v; }) 145 __raw_readw(__io(p))); __iormb(); __v; })
137#define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \ 146#define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
138 __raw_readl(__io(p))); __v; }) 147 __raw_readl(__io(p))); __iormb(); __v; })
139 148
140#define outsb(p,d,l) __raw_writesb(__io(p),d,l) 149#define outsb(p,d,l) __raw_writesb(__io(p),d,l)
141#define outsw(p,d,l) __raw_writesw(__io(p),d,l) 150#define outsw(p,d,l) __raw_writesw(__io(p),d,l)
@@ -192,14 +201,6 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
192#define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \ 201#define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \
193 cpu_to_le32(v),__mem_pci(c))) 202 cpu_to_le32(v),__mem_pci(c)))
194 203
195#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
196#define __iormb() rmb()
197#define __iowmb() wmb()
198#else
199#define __iormb() do { } while (0)
200#define __iowmb() do { } while (0)
201#endif
202
203#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; }) 204#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
204#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; }) 205#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
205#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; }) 206#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index f41a6f57cd12..82dfe5d0c41e 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -18,16 +18,34 @@
18#define __ASMARM_TLB_H 18#define __ASMARM_TLB_H
19 19
20#include <asm/cacheflush.h> 20#include <asm/cacheflush.h>
21#include <asm/tlbflush.h>
22 21
23#ifndef CONFIG_MMU 22#ifndef CONFIG_MMU
24 23
25#include <linux/pagemap.h> 24#include <linux/pagemap.h>
25
26#define tlb_flush(tlb) ((void) tlb)
27
26#include <asm-generic/tlb.h> 28#include <asm-generic/tlb.h>
27 29
28#else /* !CONFIG_MMU */ 30#else /* !CONFIG_MMU */
29 31
32#include <linux/swap.h>
30#include <asm/pgalloc.h> 33#include <asm/pgalloc.h>
34#include <asm/tlbflush.h>
35
36/*
37 * We need to delay page freeing for SMP as other CPUs can access pages
38 * which have been removed but not yet had their TLB entries invalidated.
39 * Also, as ARMv7 speculative prefetch can drag new entries into the TLB,
40 * we need to apply this same delaying tactic to ensure correct operation.
41 */
42#if defined(CONFIG_SMP) || defined(CONFIG_CPU_32v7)
43#define tlb_fast_mode(tlb) 0
44#define FREE_PTE_NR 500
45#else
46#define tlb_fast_mode(tlb) 1
47#define FREE_PTE_NR 0
48#endif
31 49
32/* 50/*
33 * TLB handling. This allows us to remove pages from the page 51 * TLB handling. This allows us to remove pages from the page
@@ -36,12 +54,58 @@
36struct mmu_gather { 54struct mmu_gather {
37 struct mm_struct *mm; 55 struct mm_struct *mm;
38 unsigned int fullmm; 56 unsigned int fullmm;
57 struct vm_area_struct *vma;
39 unsigned long range_start; 58 unsigned long range_start;
40 unsigned long range_end; 59 unsigned long range_end;
60 unsigned int nr;
61 struct page *pages[FREE_PTE_NR];
41}; 62};
42 63
43DECLARE_PER_CPU(struct mmu_gather, mmu_gathers); 64DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
44 65
66/*
67 * This is unnecessarily complex. There's three ways the TLB shootdown
68 * code is used:
69 * 1. Unmapping a range of vmas. See zap_page_range(), unmap_region().
70 * tlb->fullmm = 0, and tlb_start_vma/tlb_end_vma will be called.
71 * tlb->vma will be non-NULL.
72 * 2. Unmapping all vmas. See exit_mmap().
73 * tlb->fullmm = 1, and tlb_start_vma/tlb_end_vma will be called.
74 * tlb->vma will be non-NULL. Additionally, page tables will be freed.
75 * 3. Unmapping argument pages. See shift_arg_pages().
76 * tlb->fullmm = 0, but tlb_start_vma/tlb_end_vma will not be called.
77 * tlb->vma will be NULL.
78 */
79static inline void tlb_flush(struct mmu_gather *tlb)
80{
81 if (tlb->fullmm || !tlb->vma)
82 flush_tlb_mm(tlb->mm);
83 else if (tlb->range_end > 0) {
84 flush_tlb_range(tlb->vma, tlb->range_start, tlb->range_end);
85 tlb->range_start = TASK_SIZE;
86 tlb->range_end = 0;
87 }
88}
89
90static inline void tlb_add_flush(struct mmu_gather *tlb, unsigned long addr)
91{
92 if (!tlb->fullmm) {
93 if (addr < tlb->range_start)
94 tlb->range_start = addr;
95 if (addr + PAGE_SIZE > tlb->range_end)
96 tlb->range_end = addr + PAGE_SIZE;
97 }
98}
99
100static inline void tlb_flush_mmu(struct mmu_gather *tlb)
101{
102 tlb_flush(tlb);
103 if (!tlb_fast_mode(tlb)) {
104 free_pages_and_swap_cache(tlb->pages, tlb->nr);
105 tlb->nr = 0;
106 }
107}
108
45static inline struct mmu_gather * 109static inline struct mmu_gather *
46tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush) 110tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
47{ 111{
@@ -49,6 +113,8 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
49 113
50 tlb->mm = mm; 114 tlb->mm = mm;
51 tlb->fullmm = full_mm_flush; 115 tlb->fullmm = full_mm_flush;
116 tlb->vma = NULL;
117 tlb->nr = 0;
52 118
53 return tlb; 119 return tlb;
54} 120}
@@ -56,8 +122,7 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
56static inline void 122static inline void
57tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end) 123tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
58{ 124{
59 if (tlb->fullmm) 125 tlb_flush_mmu(tlb);
60 flush_tlb_mm(tlb->mm);
61 126
62 /* keep the page table cache within bounds */ 127 /* keep the page table cache within bounds */
63 check_pgt_cache(); 128 check_pgt_cache();
@@ -71,12 +136,7 @@ tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
71static inline void 136static inline void
72tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep, unsigned long addr) 137tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep, unsigned long addr)
73{ 138{
74 if (!tlb->fullmm) { 139 tlb_add_flush(tlb, addr);
75 if (addr < tlb->range_start)
76 tlb->range_start = addr;
77 if (addr + PAGE_SIZE > tlb->range_end)
78 tlb->range_end = addr + PAGE_SIZE;
79 }
80} 140}
81 141
82/* 142/*
@@ -89,6 +149,7 @@ tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
89{ 149{
90 if (!tlb->fullmm) { 150 if (!tlb->fullmm) {
91 flush_cache_range(vma, vma->vm_start, vma->vm_end); 151 flush_cache_range(vma, vma->vm_start, vma->vm_end);
152 tlb->vma = vma;
92 tlb->range_start = TASK_SIZE; 153 tlb->range_start = TASK_SIZE;
93 tlb->range_end = 0; 154 tlb->range_end = 0;
94 } 155 }
@@ -97,12 +158,30 @@ tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
97static inline void 158static inline void
98tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma) 159tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
99{ 160{
100 if (!tlb->fullmm && tlb->range_end > 0) 161 if (!tlb->fullmm)
101 flush_tlb_range(vma, tlb->range_start, tlb->range_end); 162 tlb_flush(tlb);
163}
164
165static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
166{
167 if (tlb_fast_mode(tlb)) {
168 free_page_and_swap_cache(page);
169 } else {
170 tlb->pages[tlb->nr++] = page;
171 if (tlb->nr >= FREE_PTE_NR)
172 tlb_flush_mmu(tlb);
173 }
174}
175
176static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
177 unsigned long addr)
178{
179 pgtable_page_dtor(pte);
180 tlb_add_flush(tlb, addr);
181 tlb_remove_page(tlb, pte);
102} 182}
103 183
104#define tlb_remove_page(tlb,page) free_page_and_swap_cache(page) 184#define pte_free_tlb(tlb, ptep, addr) __pte_free_tlb(tlb, ptep, addr)
105#define pte_free_tlb(tlb, ptep, addr) pte_free((tlb)->mm, ptep)
106#define pmd_free_tlb(tlb, pmdp, addr) pmd_free((tlb)->mm, pmdp) 185#define pmd_free_tlb(tlb, pmdp, addr) pmd_free((tlb)->mm, pmdp)
107 186
108#define tlb_migrate_finish(mm) do { } while (0) 187#define tlb_migrate_finish(mm) do { } while (0)
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index ce7378ea15a2..d2005de383b8 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -10,12 +10,7 @@
10#ifndef _ASMARM_TLBFLUSH_H 10#ifndef _ASMARM_TLBFLUSH_H
11#define _ASMARM_TLBFLUSH_H 11#define _ASMARM_TLBFLUSH_H
12 12
13 13#ifdef CONFIG_MMU
14#ifndef CONFIG_MMU
15
16#define tlb_flush(tlb) ((void) tlb)
17
18#else /* CONFIG_MMU */
19 14
20#include <asm/glue.h> 15#include <asm/glue.h>
21 16
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index f17d9a09e8fb..f06ff9feb0db 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -391,25 +391,24 @@ ENDPROC(__turn_mmu_on)
391 391
392 392
393#ifdef CONFIG_SMP_ON_UP 393#ifdef CONFIG_SMP_ON_UP
394 __INIT
394__fixup_smp: 395__fixup_smp:
395 mov r4, #0x00070000 396 and r3, r9, #0x000f0000 @ architecture version
396 orr r3, r4, #0xff000000 @ mask 0xff070000 397 teq r3, #0x000f0000 @ CPU ID supported?
397 orr r4, r4, #0x41000000 @ val 0x41070000
398 and r0, r9, r3
399 teq r0, r4 @ ARM CPU and ARMv6/v7?
400 bne __fixup_smp_on_up @ no, assume UP 398 bne __fixup_smp_on_up @ no, assume UP
401 399
402 orr r3, r3, #0x0000ff00 400 bic r3, r9, #0x00ff0000
403 orr r3, r3, #0x000000f0 @ mask 0xff07fff0 401 bic r3, r3, #0x0000000f @ mask 0xff00fff0
402 mov r4, #0x41000000
404 orr r4, r4, #0x0000b000 403 orr r4, r4, #0x0000b000
405 orr r4, r4, #0x00000020 @ val 0x4107b020 404 orr r4, r4, #0x00000020 @ val 0x4100b020
406 and r0, r9, r3 405 teq r3, r4 @ ARM 11MPCore?
407 teq r0, r4 @ ARM 11MPCore?
408 moveq pc, lr @ yes, assume SMP 406 moveq pc, lr @ yes, assume SMP
409 407
410 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR 408 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
411 tst r0, #1 << 31 409 and r0, r0, #0xc0000000 @ multiprocessing extensions and
412 movne pc, lr @ bit 31 => SMP 410 teq r0, #0x80000000 @ not part of a uniprocessor system?
411 moveq pc, lr @ yes, assume SMP
413 412
414__fixup_smp_on_up: 413__fixup_smp_on_up:
415 adr r0, 1f 414 adr r0, 1f
@@ -417,18 +416,7 @@ __fixup_smp_on_up:
417 sub r3, r0, r3 416 sub r3, r0, r3
418 add r4, r4, r3 417 add r4, r4, r3
419 add r5, r5, r3 418 add r5, r5, r3
4202: cmp r4, r5 419 b __do_fixup_smp_on_up
421 movhs pc, lr
422 ldmia r4!, {r0, r6}
423 ARM( str r6, [r0, r3] )
424 THUMB( add r0, r0, r3 )
425#ifdef __ARMEB__
426 THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian.
427#endif
428 THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords
429 THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3.
430 THUMB( strh r6, [r0] )
431 b 2b
432ENDPROC(__fixup_smp) 420ENDPROC(__fixup_smp)
433 421
434 .align 422 .align
@@ -442,7 +430,31 @@ smp_on_up:
442 ALT_SMP(.long 1) 430 ALT_SMP(.long 1)
443 ALT_UP(.long 0) 431 ALT_UP(.long 0)
444 .popsection 432 .popsection
433#endif
445 434
435 .text
436__do_fixup_smp_on_up:
437 cmp r4, r5
438 movhs pc, lr
439 ldmia r4!, {r0, r6}
440 ARM( str r6, [r0, r3] )
441 THUMB( add r0, r0, r3 )
442#ifdef __ARMEB__
443 THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian.
446#endif 444#endif
445 THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords
446 THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3.
447 THUMB( strh r6, [r0] )
448 b __do_fixup_smp_on_up
449ENDPROC(__do_fixup_smp_on_up)
450
451ENTRY(fixup_smp)
452 stmfd sp!, {r4 - r6, lr}
453 mov r4, r0
454 add r5, r0, r1
455 mov r3, #0
456 bl __do_fixup_smp_on_up
457 ldmfd sp!, {r4 - r6, pc}
458ENDPROC(fixup_smp)
447 459
448#include "head-common.S" 460#include "head-common.S"
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index c9f3f0467570..d600bd350704 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -137,11 +137,10 @@ static u8 get_debug_arch(void)
137 u32 didr; 137 u32 didr;
138 138
139 /* Do we implement the extended CPUID interface? */ 139 /* Do we implement the extended CPUID interface? */
140 if (((read_cpuid_id() >> 16) & 0xf) != 0xf) { 140 if (WARN_ONCE((((read_cpuid_id() >> 16) & 0xf) != 0xf),
141 pr_warning("CPUID feature registers not supported. " 141 "CPUID feature registers not supported. "
142 "Assuming v6 debug is present.\n"); 142 "Assuming v6 debug is present.\n"))
143 return ARM_DEBUG_ARCH_V6; 143 return ARM_DEBUG_ARCH_V6;
144 }
145 144
146 ARM_DBG_READ(c0, 0, didr); 145 ARM_DBG_READ(c0, 0, didr);
147 return (didr >> 16) & 0xf; 146 return (didr >> 16) & 0xf;
@@ -152,6 +151,12 @@ u8 arch_get_debug_arch(void)
152 return debug_arch; 151 return debug_arch;
153} 152}
154 153
154static int debug_arch_supported(void)
155{
156 u8 arch = get_debug_arch();
157 return arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14;
158}
159
155/* Determine number of BRP register available. */ 160/* Determine number of BRP register available. */
156static int get_num_brp_resources(void) 161static int get_num_brp_resources(void)
157{ 162{
@@ -268,6 +273,9 @@ out:
268 273
269int hw_breakpoint_slots(int type) 274int hw_breakpoint_slots(int type)
270{ 275{
276 if (!debug_arch_supported())
277 return 0;
278
271 /* 279 /*
272 * We can be called early, so don't rely on 280 * We can be called early, so don't rely on
273 * our static variables being initialised. 281 * our static variables being initialised.
@@ -834,11 +842,11 @@ static void reset_ctrl_regs(void *unused)
834 842
835 /* 843 /*
836 * v7 debug contains save and restore registers so that debug state 844 * v7 debug contains save and restore registers so that debug state
837 * can be maintained across low-power modes without leaving 845 * can be maintained across low-power modes without leaving the debug
838 * the debug logic powered up. It is IMPLEMENTATION DEFINED whether 846 * logic powered up. It is IMPLEMENTATION DEFINED whether we can access
839 * we can write to the debug registers out of reset, so we must 847 * the debug registers out of reset, so we must unlock the OS Lock
840 * unlock the OS Lock Access Register to avoid taking undefined 848 * Access Register to avoid taking undefined instruction exceptions
841 * instruction exceptions later on. 849 * later on.
842 */ 850 */
843 if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) { 851 if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) {
844 /* 852 /*
@@ -882,7 +890,7 @@ static int __init arch_hw_breakpoint_init(void)
882 890
883 debug_arch = get_debug_arch(); 891 debug_arch = get_debug_arch();
884 892
885 if (debug_arch > ARM_DEBUG_ARCH_V7_ECP14) { 893 if (!debug_arch_supported()) {
886 pr_info("debug architecture 0x%x unsupported.\n", debug_arch); 894 pr_info("debug architecture 0x%x unsupported.\n", debug_arch);
887 return 0; 895 return 0;
888 } 896 }
@@ -899,18 +907,18 @@ static int __init arch_hw_breakpoint_init(void)
899 pr_info("%d breakpoint(s) reserved for watchpoint " 907 pr_info("%d breakpoint(s) reserved for watchpoint "
900 "single-step.\n", core_num_reserved_brps); 908 "single-step.\n", core_num_reserved_brps);
901 909
910 /*
911 * Reset the breakpoint resources. We assume that a halting
912 * debugger will leave the world in a nice state for us.
913 */
914 on_each_cpu(reset_ctrl_regs, NULL, 1);
915
902 ARM_DBG_READ(c1, 0, dscr); 916 ARM_DBG_READ(c1, 0, dscr);
903 if (dscr & ARM_DSCR_HDBGEN) { 917 if (dscr & ARM_DSCR_HDBGEN) {
918 max_watchpoint_len = 4;
904 pr_warning("halting debug mode enabled. Assuming maximum " 919 pr_warning("halting debug mode enabled. Assuming maximum "
905 "watchpoint size of 4 bytes."); 920 "watchpoint size of %u bytes.", max_watchpoint_len);
906 } else { 921 } else {
907 /*
908 * Reset the breakpoint resources. We assume that a halting
909 * debugger will leave the world in a nice state for us.
910 */
911 smp_call_function(reset_ctrl_regs, NULL, 1);
912 reset_ctrl_regs(NULL);
913
914 /* Work out the maximum supported watchpoint length. */ 922 /* Work out the maximum supported watchpoint length. */
915 max_watchpoint_len = get_max_wp_len(); 923 max_watchpoint_len = get_max_wp_len();
916 pr_info("maximum watchpoint size is %u bytes.\n", 924 pr_info("maximum watchpoint size is %u bytes.\n",
diff --git a/arch/arm/kernel/kprobes-decode.c b/arch/arm/kernel/kprobes-decode.c
index 2c1f0050c9c4..8f6ed43861f1 100644
--- a/arch/arm/kernel/kprobes-decode.c
+++ b/arch/arm/kernel/kprobes-decode.c
@@ -1437,7 +1437,7 @@ arm_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
1437 1437
1438 return space_cccc_1100_010x(insn, asi); 1438 return space_cccc_1100_010x(insn, asi);
1439 1439
1440 } else if ((insn & 0x0e000000) == 0x0c400000) { 1440 } else if ((insn & 0x0e000000) == 0x0c000000) {
1441 1441
1442 return space_cccc_110x(insn, asi); 1442 return space_cccc_110x(insn, asi);
1443 1443
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index 2cfe8161b478..6d4105e6872f 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -22,6 +22,7 @@
22 22
23#include <asm/pgtable.h> 23#include <asm/pgtable.h>
24#include <asm/sections.h> 24#include <asm/sections.h>
25#include <asm/smp_plat.h>
25#include <asm/unwind.h> 26#include <asm/unwind.h>
26 27
27#ifdef CONFIG_XIP_KERNEL 28#ifdef CONFIG_XIP_KERNEL
@@ -268,12 +269,28 @@ struct mod_unwind_map {
268 const Elf_Shdr *txt_sec; 269 const Elf_Shdr *txt_sec;
269}; 270};
270 271
272static const Elf_Shdr *find_mod_section(const Elf32_Ehdr *hdr,
273 const Elf_Shdr *sechdrs, const char *name)
274{
275 const Elf_Shdr *s, *se;
276 const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
277
278 for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++)
279 if (strcmp(name, secstrs + s->sh_name) == 0)
280 return s;
281
282 return NULL;
283}
284
285extern void fixup_smp(const void *, unsigned long);
286
271int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs, 287int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
272 struct module *mod) 288 struct module *mod)
273{ 289{
290 const Elf_Shdr * __maybe_unused s = NULL;
274#ifdef CONFIG_ARM_UNWIND 291#ifdef CONFIG_ARM_UNWIND
275 const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; 292 const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
276 const Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum; 293 const Elf_Shdr *sechdrs_end = sechdrs + hdr->e_shnum;
277 struct mod_unwind_map maps[ARM_SEC_MAX]; 294 struct mod_unwind_map maps[ARM_SEC_MAX];
278 int i; 295 int i;
279 296
@@ -315,6 +332,9 @@ int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
315 maps[i].txt_sec->sh_addr, 332 maps[i].txt_sec->sh_addr,
316 maps[i].txt_sec->sh_size); 333 maps[i].txt_sec->sh_size);
317#endif 334#endif
335 s = find_mod_section(hdr, sechdrs, ".alt.smp.init");
336 if (s && !is_smp())
337 fixup_smp((void *)s->sh_addr, s->sh_size);
318 return 0; 338 return 0;
319} 339}
320 340
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 5efa2647a2fb..d150ad1ccb5d 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -700,7 +700,7 @@ user_backtrace(struct frame_tail __user *tail,
700 * Frame pointers should strictly progress back up the stack 700 * Frame pointers should strictly progress back up the stack
701 * (towards higher addresses). 701 * (towards higher addresses).
702 */ 702 */
703 if (tail >= buftail.fp) 703 if (tail + 1 >= buftail.fp)
704 return NULL; 704 return NULL;
705 705
706 return buftail.fp - 1; 706 return buftail.fp - 1;
diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c
index b8af96ea62e6..2c79eec19262 100644
--- a/arch/arm/kernel/pmu.c
+++ b/arch/arm/kernel/pmu.c
@@ -97,28 +97,34 @@ set_irq_affinity(int irq,
97 irq, cpu); 97 irq, cpu);
98 return err; 98 return err;
99#else 99#else
100 return 0; 100 return -EINVAL;
101#endif 101#endif
102} 102}
103 103
104static int 104static int
105init_cpu_pmu(void) 105init_cpu_pmu(void)
106{ 106{
107 int i, err = 0; 107 int i, irqs, err = 0;
108 struct platform_device *pdev = pmu_devices[ARM_PMU_DEVICE_CPU]; 108 struct platform_device *pdev = pmu_devices[ARM_PMU_DEVICE_CPU];
109 109
110 if (!pdev) { 110 if (!pdev)
111 err = -ENODEV; 111 return -ENODEV;
112 goto out; 112
113 } 113 irqs = pdev->num_resources;
114
115 /*
116 * If we have a single PMU interrupt that we can't shift, assume that
117 * we're running on a uniprocessor machine and continue.
118 */
119 if (irqs == 1 && !irq_can_set_affinity(platform_get_irq(pdev, 0)))
120 return 0;
114 121
115 for (i = 0; i < pdev->num_resources; ++i) { 122 for (i = 0; i < irqs; ++i) {
116 err = set_irq_affinity(platform_get_irq(pdev, i), i); 123 err = set_irq_affinity(platform_get_irq(pdev, i), i);
117 if (err) 124 if (err)
118 break; 125 break;
119 } 126 }
120 127
121out:
122 return err; 128 return err;
123} 129}
124 130
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 420b8d6485d6..5ea4fb718b97 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -226,8 +226,8 @@ int cpu_architecture(void)
226 * Register 0 and check for VMSAv7 or PMSAv7 */ 226 * Register 0 and check for VMSAv7 or PMSAv7 */
227 asm("mrc p15, 0, %0, c0, c1, 4" 227 asm("mrc p15, 0, %0, c0, c1, 4"
228 : "=r" (mmfr0)); 228 : "=r" (mmfr0));
229 if ((mmfr0 & 0x0000000f) == 0x00000003 || 229 if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
230 (mmfr0 & 0x000000f0) == 0x00000030) 230 (mmfr0 & 0x000000f0) >= 0x00000030)
231 cpu_arch = CPU_ARCH_ARMv7; 231 cpu_arch = CPU_ARCH_ARMv7;
232 else if ((mmfr0 & 0x0000000f) == 0x00000002 || 232 else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
233 (mmfr0 & 0x000000f0) == 0x00000020) 233 (mmfr0 & 0x000000f0) == 0x00000020)
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 907d5a620bca..abaf8445ce25 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -474,7 +474,9 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
474 unsigned long handler = (unsigned long)ka->sa.sa_handler; 474 unsigned long handler = (unsigned long)ka->sa.sa_handler;
475 unsigned long retcode; 475 unsigned long retcode;
476 int thumb = 0; 476 int thumb = 0;
477 unsigned long cpsr = regs->ARM_cpsr & ~PSR_f; 477 unsigned long cpsr = regs->ARM_cpsr & ~(PSR_f | PSR_E_BIT);
478
479 cpsr |= PSR_ENDSTATE;
478 480
479 /* 481 /*
480 * Maybe we need to deliver a 32-bit signal to a 26-bit task. 482 * Maybe we need to deliver a 32-bit signal to a 26-bit task.
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 86b66f3f2031..61462790757f 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -21,6 +21,12 @@
21#define ARM_CPU_KEEP(x) 21#define ARM_CPU_KEEP(x)
22#endif 22#endif
23 23
24#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
25#define ARM_EXIT_KEEP(x) x
26#else
27#define ARM_EXIT_KEEP(x)
28#endif
29
24OUTPUT_ARCH(arm) 30OUTPUT_ARCH(arm)
25ENTRY(stext) 31ENTRY(stext)
26 32
@@ -43,6 +49,7 @@ SECTIONS
43 _sinittext = .; 49 _sinittext = .;
44 HEAD_TEXT 50 HEAD_TEXT
45 INIT_TEXT 51 INIT_TEXT
52 ARM_EXIT_KEEP(EXIT_TEXT)
46 _einittext = .; 53 _einittext = .;
47 ARM_CPU_DISCARD(PROC_INFO) 54 ARM_CPU_DISCARD(PROC_INFO)
48 __arch_info_begin = .; 55 __arch_info_begin = .;
@@ -67,6 +74,7 @@ SECTIONS
67#ifndef CONFIG_XIP_KERNEL 74#ifndef CONFIG_XIP_KERNEL
68 __init_begin = _stext; 75 __init_begin = _stext;
69 INIT_DATA 76 INIT_DATA
77 ARM_EXIT_KEEP(EXIT_DATA)
70#endif 78#endif
71 } 79 }
72 80
@@ -162,6 +170,7 @@ SECTIONS
162 . = ALIGN(PAGE_SIZE); 170 . = ALIGN(PAGE_SIZE);
163 __init_begin = .; 171 __init_begin = .;
164 INIT_DATA 172 INIT_DATA
173 ARM_EXIT_KEEP(EXIT_DATA)
165 . = ALIGN(PAGE_SIZE); 174 . = ALIGN(PAGE_SIZE);
166 __init_end = .; 175 __init_end = .;
167#endif 176#endif
@@ -247,6 +256,8 @@ SECTIONS
247 } 256 }
248#endif 257#endif
249 258
259 NOTES
260
250 BSS_SECTION(0, 0, 0) 261 BSS_SECTION(0, 0, 0)
251 _end = .; 262 _end = .;
252 263
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index ffdf87be2958..82079545adc4 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -838,7 +838,7 @@ EXPORT_SYMBOL(ep93xx_i2s_release);
838static struct resource ep93xx_ac97_resources[] = { 838static struct resource ep93xx_ac97_resources[] = {
839 { 839 {
840 .start = EP93XX_AAC_PHYS_BASE, 840 .start = EP93XX_AAC_PHYS_BASE,
841 .end = EP93XX_AAC_PHYS_BASE + 0xb0 - 1, 841 .end = EP93XX_AAC_PHYS_BASE + 0xac - 1,
842 .flags = IORESOURCE_MEM, 842 .flags = IORESOURCE_MEM,
843 }, 843 },
844 { 844 {
diff --git a/arch/arm/mach-footbridge/include/mach/debug-macro.S b/arch/arm/mach-footbridge/include/mach/debug-macro.S
index 3c9e0c40c679..30b971d65815 100644
--- a/arch/arm/mach-footbridge/include/mach/debug-macro.S
+++ b/arch/arm/mach-footbridge/include/mach/debug-macro.S
@@ -17,8 +17,8 @@
17 /* For NetWinder debugging */ 17 /* For NetWinder debugging */
18 .macro addruart, rp, rv 18 .macro addruart, rp, rv
19 mov \rp, #0x000003f8 19 mov \rp, #0x000003f8
20 orr \rv, \rp, #0x7c000000 @ physical 20 orr \rv, \rp, #0xff000000 @ virtual
21 orr \rp, \rp, #0xff000000 @ virtual 21 orr \rp, \rp, #0x7c000000 @ physical
22 .endm 22 .endm
23 23
24#define UART_SHIFT 0 24#define UART_SHIFT 0
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index aa76cfd9f348..8382e7902078 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -180,7 +180,7 @@ static const uint32_t mx25pdk_keymap[] = {
180 KEY(3, 3, KEY_POWER), 180 KEY(3, 3, KEY_POWER),
181}; 181};
182 182
183static const struct matrix_keymap_data mx25pdk_keymap_data __initdata = { 183static const struct matrix_keymap_data mx25pdk_keymap_data __initconst = {
184 .keymap = mx25pdk_keymap, 184 .keymap = mx25pdk_keymap,
185 .keymap_size = ARRAY_SIZE(mx25pdk_keymap), 185 .keymap_size = ARRAY_SIZE(mx25pdk_keymap),
186}; 186};
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 4dc68d6bb6be..9fd894271d5d 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -432,7 +432,7 @@ static struct clocksource clocksource_ixp4xx = {
432 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 432 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
433}; 433};
434 434
435unsigned long ixp4xx_timer_freq = FREQ; 435unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
436EXPORT_SYMBOL(ixp4xx_timer_freq); 436EXPORT_SYMBOL(ixp4xx_timer_freq);
437static void __init ixp4xx_clocksource_init(void) 437static void __init ixp4xx_clocksource_init(void)
438{ 438{
@@ -496,7 +496,7 @@ static struct clock_event_device clockevent_ixp4xx = {
496 496
497static void __init ixp4xx_clockevent_init(void) 497static void __init ixp4xx_clockevent_init(void)
498{ 498{
499 clockevent_ixp4xx.mult = div_sc(FREQ, NSEC_PER_SEC, 499 clockevent_ixp4xx.mult = div_sc(IXP4XX_TIMER_FREQ, NSEC_PER_SEC,
500 clockevent_ixp4xx.shift); 500 clockevent_ixp4xx.shift);
501 clockevent_ixp4xx.max_delta_ns = 501 clockevent_ixp4xx.max_delta_ns =
502 clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx); 502 clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx);
diff --git a/arch/arm/mach-ixp4xx/include/mach/timex.h b/arch/arm/mach-ixp4xx/include/mach/timex.h
index 2c3f93c3eb79..c9e930f29339 100644
--- a/arch/arm/mach-ixp4xx/include/mach/timex.h
+++ b/arch/arm/mach-ixp4xx/include/mach/timex.h
@@ -10,6 +10,7 @@
10 * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the 10 * 66.66... MHz. We do a convulted calculation of CLOCK_TICK_RATE b/c the
11 * timer register ignores the bottom 2 bits of the LATCH value. 11 * timer register ignores the bottom 2 bits of the LATCH value.
12 */ 12 */
13#define FREQ 66666000 13#define IXP4XX_TIMER_FREQ 66666000
14#define CLOCK_TICK_RATE (((FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ) 14#define CLOCK_TICK_RATE \
15 (((IXP4XX_TIMER_FREQ / HZ & ~IXP4XX_OST_RELOAD_MASK) + 1) * HZ)
15 16
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
index bfdbe4b5a3cc..852f7c9f87d0 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx_qmgr.c
@@ -265,6 +265,11 @@ void qmgr_release_queue(unsigned int queue)
265 qmgr_queue_descs[queue], queue); 265 qmgr_queue_descs[queue], queue);
266 qmgr_queue_descs[queue][0] = '\x0'; 266 qmgr_queue_descs[queue][0] = '\x0';
267#endif 267#endif
268
269 while ((addr = qmgr_get_entry(queue)))
270 printk(KERN_ERR "qmgr: released queue %i not empty: 0x%08X\n",
271 queue, addr);
272
268 __raw_writel(0, &qmgr_regs->sram[queue]); 273 __raw_writel(0, &qmgr_regs->sram[queue]);
269 274
270 used_sram_bitmap[0] &= ~mask[0]; 275 used_sram_bitmap[0] &= ~mask[0];
@@ -275,10 +280,6 @@ void qmgr_release_queue(unsigned int queue)
275 spin_unlock_irq(&qmgr_lock); 280 spin_unlock_irq(&qmgr_lock);
276 281
277 module_put(THIS_MODULE); 282 module_put(THIS_MODULE);
278
279 while ((addr = qmgr_get_entry(queue)))
280 printk(KERN_ERR "qmgr: released queue %i not empty: 0x%08X\n",
281 queue, addr);
282} 283}
283 284
284static int qmgr_init(void) 285static int qmgr_init(void)
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
index b1a362ebfded..ca72a05ed9c1 100644
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -304,7 +304,7 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \
304 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \ 304 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
305 reg &= ~BM_CLKCTRL_##dr##_DIV; \ 305 reg &= ~BM_CLKCTRL_##dr##_DIV; \
306 reg |= div << BP_CLKCTRL_##dr##_DIV; \ 306 reg |= div << BP_CLKCTRL_##dr##_DIV; \
307 if (reg | (1 << clk->enable_shift)) { \ 307 if (reg & (1 << clk->enable_shift)) { \
308 pr_err("%s: clock is gated\n", __func__); \ 308 pr_err("%s: clock is gated\n", __func__); \
309 return -EINVAL; \ 309 return -EINVAL; \
310 } \ 310 } \
@@ -347,7 +347,7 @@ static int name##_set_parent(struct clk *clk, struct clk *parent) \
347{ \ 347{ \
348 if (parent != clk->parent) { \ 348 if (parent != clk->parent) { \
349 __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \ 349 __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
350 HW_CLKCTRL_CLKSEQ_TOG); \ 350 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ_TOG); \
351 clk->parent = parent; \ 351 clk->parent = parent; \
352 } \ 352 } \
353 \ 353 \
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 56312c092a9e..fd1c4c54b8e5 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -355,12 +355,12 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \
355 } else { \ 355 } else { \
356 reg &= ~BM_CLKCTRL_##dr##_DIV; \ 356 reg &= ~BM_CLKCTRL_##dr##_DIV; \
357 reg |= div << BP_CLKCTRL_##dr##_DIV; \ 357 reg |= div << BP_CLKCTRL_##dr##_DIV; \
358 if (reg | (1 << clk->enable_shift)) { \ 358 if (reg & (1 << clk->enable_shift)) { \
359 pr_err("%s: clock is gated\n", __func__); \ 359 pr_err("%s: clock is gated\n", __func__); \
360 return -EINVAL; \ 360 return -EINVAL; \
361 } \ 361 } \
362 } \ 362 } \
363 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); \ 363 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
364 \ 364 \
365 for (i = 10000; i; i--) \ 365 for (i = 10000; i; i--) \
366 if (!(__raw_readl(CLKCTRL_BASE_ADDR + \ 366 if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
@@ -483,7 +483,7 @@ static int name##_set_parent(struct clk *clk, struct clk *parent) \
483{ \ 483{ \
484 if (parent != clk->parent) { \ 484 if (parent != clk->parent) { \
485 __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \ 485 __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
486 HW_CLKCTRL_CLKSEQ_TOG); \ 486 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ_TOG); \
487 clk->parent = parent; \ 487 clk->parent = parent; \
488 } \ 488 } \
489 \ 489 \
@@ -609,7 +609,6 @@ static struct clk_lookup lookups[] = {
609 _REGISTER_CLOCK("duart", NULL, uart_clk) 609 _REGISTER_CLOCK("duart", NULL, uart_clk)
610 _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk) 610 _REGISTER_CLOCK("imx28-fec.0", NULL, fec_clk)
611 _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk) 611 _REGISTER_CLOCK("imx28-fec.1", NULL, fec_clk)
612 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
613 _REGISTER_CLOCK("rtc", NULL, rtc_clk) 612 _REGISTER_CLOCK("rtc", NULL, rtc_clk)
614 _REGISTER_CLOCK("pll2", NULL, pll2_clk) 613 _REGISTER_CLOCK("pll2", NULL, pll2_clk)
615 _REGISTER_CLOCK(NULL, "hclk", hbus_clk) 614 _REGISTER_CLOCK(NULL, "hclk", hbus_clk)
diff --git a/arch/arm/mach-mxs/clock.c b/arch/arm/mach-mxs/clock.c
index e7d2269cf70e..a7093c88e6a6 100644
--- a/arch/arm/mach-mxs/clock.c
+++ b/arch/arm/mach-mxs/clock.c
@@ -57,7 +57,6 @@ static void __clk_disable(struct clk *clk)
57 if (clk->disable) 57 if (clk->disable)
58 clk->disable(clk); 58 clk->disable(clk);
59 __clk_disable(clk->parent); 59 __clk_disable(clk->parent);
60 __clk_disable(clk->secondary);
61 } 60 }
62} 61}
63 62
@@ -68,7 +67,6 @@ static int __clk_enable(struct clk *clk)
68 67
69 if (clk->usecount++ == 0) { 68 if (clk->usecount++ == 0) {
70 __clk_enable(clk->parent); 69 __clk_enable(clk->parent);
71 __clk_enable(clk->secondary);
72 70
73 if (clk->enable) 71 if (clk->enable)
74 clk->enable(clk); 72 clk->enable(clk);
diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c
index d7ad7a61366d..cb0c0e83a527 100644
--- a/arch/arm/mach-mxs/gpio.c
+++ b/arch/arm/mach-mxs/gpio.c
@@ -139,6 +139,8 @@ static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
139 struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq); 139 struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq);
140 u32 gpio_irq_no_base = port->virtual_irq_start; 140 u32 gpio_irq_no_base = port->virtual_irq_start;
141 141
142 desc->irq_data.chip->irq_ack(&desc->irq_data);
143
142 irq_stat = __raw_readl(port->base + PINCTRL_IRQSTAT(port->id)) & 144 irq_stat = __raw_readl(port->base + PINCTRL_IRQSTAT(port->id)) &
143 __raw_readl(port->base + PINCTRL_IRQEN(port->id)); 145 __raw_readl(port->base + PINCTRL_IRQEN(port->id));
144 146
diff --git a/arch/arm/mach-mxs/include/mach/clock.h b/arch/arm/mach-mxs/include/mach/clock.h
index 041e276d8a32..592c9ab5d760 100644
--- a/arch/arm/mach-mxs/include/mach/clock.h
+++ b/arch/arm/mach-mxs/include/mach/clock.h
@@ -29,8 +29,6 @@ struct clk {
29 int id; 29 int id;
30 /* Source clock this clk depends on */ 30 /* Source clock this clk depends on */
31 struct clk *parent; 31 struct clk *parent;
32 /* Secondary clock to enable/disable with this clock */
33 struct clk *secondary;
34 /* Reference count of clock enable/disable */ 32 /* Reference count of clock enable/disable */
35 __s8 usecount; 33 __s8 usecount;
36 /* Register bit position for clock's enable/disable control. */ 34 /* Register bit position for clock's enable/disable control. */
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 337392c3f549..acb7ae5b0a25 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -77,7 +77,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
77 dd = clk->dpll_data; 77 dd = clk->dpll_data;
78 78
79 /* DPLL divider must result in a valid jitter correction val */ 79 /* DPLL divider must result in a valid jitter correction val */
80 fint = clk->parent->rate / (n + 1); 80 fint = clk->parent->rate / n;
81 if (fint < DPLL_FINT_BAND1_MIN) { 81 if (fint < DPLL_FINT_BAND1_MIN) {
82 82
83 pr_debug("rejecting n=%d due to Fint failure, " 83 pr_debug("rejecting n=%d due to Fint failure, "
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 729a644ce852..3300ff6e3cfe 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -38,8 +38,8 @@
38#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800 38#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
39 39
40/* PRCM_MPU clockdomain register offsets (from instance start) */ 40/* PRCM_MPU clockdomain register offsets (from instance start) */
41#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS 0x0000 41#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS 0x0018
42#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS 0x0000 42#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS 0x0018
43 43
44 44
45/* 45/*
diff --git a/arch/arm/mach-pxa/colibri-evalboard.c b/arch/arm/mach-pxa/colibri-evalboard.c
index 6b2c800a1133..28f667e52ef9 100644
--- a/arch/arm/mach-pxa/colibri-evalboard.c
+++ b/arch/arm/mach-pxa/colibri-evalboard.c
@@ -50,7 +50,7 @@ static void __init colibri_mmc_init(void)
50 GPIO0_COLIBRI_PXA270_SD_DETECT; 50 GPIO0_COLIBRI_PXA270_SD_DETECT;
51 if (machine_is_colibri300()) /* PXA300 Colibri */ 51 if (machine_is_colibri300()) /* PXA300 Colibri */
52 colibri_mci_platform_data.gpio_card_detect = 52 colibri_mci_platform_data.gpio_card_detect =
53 GPIO39_COLIBRI_PXA300_SD_DETECT; 53 GPIO13_COLIBRI_PXA300_SD_DETECT;
54 else /* PXA320 Colibri */ 54 else /* PXA320 Colibri */
55 colibri_mci_platform_data.gpio_card_detect = 55 colibri_mci_platform_data.gpio_card_detect =
56 GPIO28_COLIBRI_PXA320_SD_DETECT; 56 GPIO28_COLIBRI_PXA320_SD_DETECT;
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
index fddb16d07eb0..66dd81cbc8a0 100644
--- a/arch/arm/mach-pxa/colibri-pxa300.c
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -41,7 +41,7 @@ static mfp_cfg_t colibri_pxa300_evalboard_pin_config[] __initdata = {
41 GPIO4_MMC1_DAT1, 41 GPIO4_MMC1_DAT1,
42 GPIO5_MMC1_DAT2, 42 GPIO5_MMC1_DAT2,
43 GPIO6_MMC1_DAT3, 43 GPIO6_MMC1_DAT3,
44 GPIO39_GPIO, /* SD detect */ 44 GPIO13_GPIO, /* GPIO13_COLIBRI_PXA300_SD_DETECT */
45 45
46 /* UHC */ 46 /* UHC */
47 GPIO0_2_USBH_PEN, 47 GPIO0_2_USBH_PEN,
diff --git a/arch/arm/mach-pxa/include/mach/colibri.h b/arch/arm/mach-pxa/include/mach/colibri.h
index 388a96f1ef93..cb4236e98a0f 100644
--- a/arch/arm/mach-pxa/include/mach/colibri.h
+++ b/arch/arm/mach-pxa/include/mach/colibri.h
@@ -60,7 +60,7 @@ static inline void colibri_pxa3xx_init_nand(void) {}
60#define GPIO113_COLIBRI_PXA270_TS_IRQ 113 60#define GPIO113_COLIBRI_PXA270_TS_IRQ 113
61 61
62/* GPIO definitions for Colibri PXA300/310 */ 62/* GPIO definitions for Colibri PXA300/310 */
63#define GPIO39_COLIBRI_PXA300_SD_DETECT 39 63#define GPIO13_COLIBRI_PXA300_SD_DETECT 13
64 64
65/* GPIO definitions for Colibri PXA320 */ 65/* GPIO definitions for Colibri PXA320 */
66#define GPIO28_COLIBRI_PXA320_SD_DETECT 28 66#define GPIO28_COLIBRI_PXA320_SD_DETECT 28
diff --git a/arch/arm/mach-pxa/palm27x.c b/arch/arm/mach-pxa/palm27x.c
index 405b92a29793..35572c427fa8 100644
--- a/arch/arm/mach-pxa/palm27x.c
+++ b/arch/arm/mach-pxa/palm27x.c
@@ -323,7 +323,7 @@ static struct platform_pwm_backlight_data palm27x_backlight_data = {
323 .pwm_id = 0, 323 .pwm_id = 0,
324 .max_brightness = 0xfe, 324 .max_brightness = 0xfe,
325 .dft_brightness = 0x7e, 325 .dft_brightness = 0x7e,
326 .pwm_period_ns = 3500, 326 .pwm_period_ns = 3500 * 1024,
327 .init = palm27x_backlight_init, 327 .init = palm27x_backlight_init,
328 .notify = palm27x_backlight_notify, 328 .notify = palm27x_backlight_notify,
329 .exit = palm27x_backlight_exit, 329 .exit = palm27x_backlight_exit,
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index 978e1b289544..1807c9abdde0 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -33,7 +33,7 @@ int pxa_pm_enter(suspend_state_t state)
33#endif 33#endif
34 34
35 /* skip registers saving for standby */ 35 /* skip registers saving for standby */
36 if (state != PM_SUSPEND_STANDBY) { 36 if (state != PM_SUSPEND_STANDBY && pxa_cpu_pm_fns->save) {
37 pxa_cpu_pm_fns->save(sleep_save); 37 pxa_cpu_pm_fns->save(sleep_save);
38 /* before sleeping, calculate and save a checksum */ 38 /* before sleeping, calculate and save a checksum */
39 for (i = 0; i < pxa_cpu_pm_fns->save_count - 1; i++) 39 for (i = 0; i < pxa_cpu_pm_fns->save_count - 1; i++)
@@ -44,7 +44,7 @@ int pxa_pm_enter(suspend_state_t state)
44 pxa_cpu_pm_fns->enter(state); 44 pxa_cpu_pm_fns->enter(state);
45 cpu_init(); 45 cpu_init();
46 46
47 if (state != PM_SUSPEND_STANDBY) { 47 if (state != PM_SUSPEND_STANDBY && pxa_cpu_pm_fns->restore) {
48 /* after sleeping, validate the checksum */ 48 /* after sleeping, validate the checksum */
49 for (i = 0; i < pxa_cpu_pm_fns->save_count - 1; i++) 49 for (i = 0; i < pxa_cpu_pm_fns->save_count - 1; i++)
50 checksum += sleep_save[i]; 50 checksum += sleep_save[i];
diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h
index 203dd5a18bd5..058dab4482a1 100644
--- a/arch/arm/mach-s5p6442/include/mach/map.h
+++ b/arch/arm/mach-s5p6442/include/mach/map.h
@@ -1,6 +1,6 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/map.h 1/* linux/arch/arm/mach-s5p6442/include/mach/map.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com/
5 * 5 *
6 * S5P6442 - Memory map definitions 6 * S5P6442 - Memory map definitions
@@ -16,56 +16,61 @@
16#include <plat/map-base.h> 16#include <plat/map-base.h>
17#include <plat/map-s5p.h> 17#include <plat/map-s5p.h>
18 18
19#define S5P6442_PA_CHIPID (0xE0000000) 19#define S5P6442_PA_SDRAM 0x20000000
20#define S5P_PA_CHIPID S5P6442_PA_CHIPID
21 20
22#define S5P6442_PA_SYSCON (0xE0100000) 21#define S5P6442_PA_I2S0 0xC0B00000
23#define S5P_PA_SYSCON S5P6442_PA_SYSCON 22#define S5P6442_PA_I2S1 0xF2200000
24 23
25#define S5P6442_PA_GPIO (0xE0200000) 24#define S5P6442_PA_CHIPID 0xE0000000
26 25
27#define S5P6442_PA_VIC0 (0xE4000000) 26#define S5P6442_PA_SYSCON 0xE0100000
28#define S5P6442_PA_VIC1 (0xE4100000)
29#define S5P6442_PA_VIC2 (0xE4200000)
30 27
31#define S5P6442_PA_SROMC (0xE7000000) 28#define S5P6442_PA_GPIO 0xE0200000
32#define S5P_PA_SROMC S5P6442_PA_SROMC
33 29
34#define S5P6442_PA_MDMA 0xE8000000 30#define S5P6442_PA_VIC0 0xE4000000
35#define S5P6442_PA_PDMA 0xE9000000 31#define S5P6442_PA_VIC1 0xE4100000
32#define S5P6442_PA_VIC2 0xE4200000
36 33
37#define S5P6442_PA_TIMER (0xEA000000) 34#define S5P6442_PA_SROMC 0xE7000000
38#define S5P_PA_TIMER S5P6442_PA_TIMER
39 35
40#define S5P6442_PA_SYSTIMER (0xEA100000) 36#define S5P6442_PA_MDMA 0xE8000000
37#define S5P6442_PA_PDMA 0xE9000000
41 38
42#define S5P6442_PA_WATCHDOG (0xEA200000) 39#define S5P6442_PA_TIMER 0xEA000000
43 40
44#define S5P6442_PA_UART (0xEC000000) 41#define S5P6442_PA_SYSTIMER 0xEA100000
45 42
46#define S5P_PA_UART0 (S5P6442_PA_UART + 0x0) 43#define S5P6442_PA_WATCHDOG 0xEA200000
47#define S5P_PA_UART1 (S5P6442_PA_UART + 0x400)
48#define S5P_PA_UART2 (S5P6442_PA_UART + 0x800)
49#define S5P_SZ_UART SZ_256
50 44
51#define S5P6442_PA_IIC0 (0xEC100000) 45#define S5P6442_PA_UART 0xEC000000
52 46
53#define S5P6442_PA_SDRAM (0x20000000) 47#define S5P6442_PA_IIC0 0xEC100000
54#define S5P_PA_SDRAM S5P6442_PA_SDRAM
55 48
56#define S5P6442_PA_SPI 0xEC300000 49#define S5P6442_PA_SPI 0xEC300000
57 50
58/* I2S */
59#define S5P6442_PA_I2S0 0xC0B00000
60#define S5P6442_PA_I2S1 0xF2200000
61
62/* PCM */
63#define S5P6442_PA_PCM0 0xF2400000 51#define S5P6442_PA_PCM0 0xF2400000
64#define S5P6442_PA_PCM1 0xF2500000 52#define S5P6442_PA_PCM1 0xF2500000
65 53
66/* compatibiltiy defines. */ 54/* Compatibiltiy Defines */
55
56#define S3C_PA_IIC S5P6442_PA_IIC0
67#define S3C_PA_WDT S5P6442_PA_WATCHDOG 57#define S3C_PA_WDT S5P6442_PA_WATCHDOG
58
59#define S5P_PA_CHIPID S5P6442_PA_CHIPID
60#define S5P_PA_SDRAM S5P6442_PA_SDRAM
61#define S5P_PA_SROMC S5P6442_PA_SROMC
62#define S5P_PA_SYSCON S5P6442_PA_SYSCON
63#define S5P_PA_TIMER S5P6442_PA_TIMER
64
65/* UART */
66
68#define S3C_PA_UART S5P6442_PA_UART 67#define S3C_PA_UART S5P6442_PA_UART
69#define S3C_PA_IIC S5P6442_PA_IIC0 68
69#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
70#define S5P_PA_UART0 S5P_PA_UART(0)
71#define S5P_PA_UART1 S5P_PA_UART(1)
72#define S5P_PA_UART2 S5P_PA_UART(2)
73
74#define S5P_SZ_UART SZ_256
70 75
71#endif /* __ASM_ARCH_MAP_H */ 76#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index a9365e5ba614..95c91257c7ca 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -1,6 +1,6 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/map.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/map.h
2 * 2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5P64X0 - Memory map definitions 6 * S5P64X0 - Memory map definitions
@@ -16,64 +16,46 @@
16#include <plat/map-base.h> 16#include <plat/map-base.h>
17#include <plat/map-s5p.h> 17#include <plat/map-s5p.h>
18 18
19#define S5P64X0_PA_SDRAM (0x20000000) 19#define S5P64X0_PA_SDRAM 0x20000000
20 20
21#define S5P64X0_PA_CHIPID (0xE0000000) 21#define S5P64X0_PA_CHIPID 0xE0000000
22#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
23
24#define S5P64X0_PA_SYSCON (0xE0100000)
25#define S5P_PA_SYSCON S5P64X0_PA_SYSCON
26
27#define S5P64X0_PA_GPIO (0xE0308000)
28
29#define S5P64X0_PA_VIC0 (0xE4000000)
30#define S5P64X0_PA_VIC1 (0xE4100000)
31 22
32#define S5P64X0_PA_SROMC (0xE7000000) 23#define S5P64X0_PA_SYSCON 0xE0100000
33#define S5P_PA_SROMC S5P64X0_PA_SROMC
34
35#define S5P64X0_PA_PDMA (0xE9000000)
36
37#define S5P64X0_PA_TIMER (0xEA000000)
38#define S5P_PA_TIMER S5P64X0_PA_TIMER
39 24
40#define S5P64X0_PA_RTC (0xEA100000) 25#define S5P64X0_PA_GPIO 0xE0308000
41 26
42#define S5P64X0_PA_WDT (0xEA200000) 27#define S5P64X0_PA_VIC0 0xE4000000
28#define S5P64X0_PA_VIC1 0xE4100000
43 29
44#define S5P6440_PA_UART(x) (0xEC000000 + ((x) * S3C_UART_OFFSET)) 30#define S5P64X0_PA_SROMC 0xE7000000
45#define S5P6450_PA_UART(x) ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
46 31
47#define S5P_PA_UART0 S5P6450_PA_UART(0) 32#define S5P64X0_PA_PDMA 0xE9000000
48#define S5P_PA_UART1 S5P6450_PA_UART(1)
49#define S5P_PA_UART2 S5P6450_PA_UART(2)
50#define S5P_PA_UART3 S5P6450_PA_UART(3)
51#define S5P_PA_UART4 S5P6450_PA_UART(4)
52#define S5P_PA_UART5 S5P6450_PA_UART(5)
53 33
54#define S5P_SZ_UART SZ_256 34#define S5P64X0_PA_TIMER 0xEA000000
35#define S5P64X0_PA_RTC 0xEA100000
36#define S5P64X0_PA_WDT 0xEA200000
55 37
56#define S5P6440_PA_IIC0 (0xEC104000) 38#define S5P6440_PA_IIC0 0xEC104000
57#define S5P6440_PA_IIC1 (0xEC20F000) 39#define S5P6440_PA_IIC1 0xEC20F000
58#define S5P6450_PA_IIC0 (0xEC100000) 40#define S5P6450_PA_IIC0 0xEC100000
59#define S5P6450_PA_IIC1 (0xEC200000) 41#define S5P6450_PA_IIC1 0xEC200000
60 42
61#define S5P64X0_PA_SPI0 (0xEC400000) 43#define S5P64X0_PA_SPI0 0xEC400000
62#define S5P64X0_PA_SPI1 (0xEC500000) 44#define S5P64X0_PA_SPI1 0xEC500000
63 45
64#define S5P64X0_PA_HSOTG (0xED100000) 46#define S5P64X0_PA_HSOTG 0xED100000
65 47
66#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) 48#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
67 49
68#define S5P64X0_PA_I2S (0xF2000000) 50#define S5P64X0_PA_I2S 0xF2000000
69#define S5P6450_PA_I2S1 0xF2800000 51#define S5P6450_PA_I2S1 0xF2800000
70#define S5P6450_PA_I2S2 0xF2900000 52#define S5P6450_PA_I2S2 0xF2900000
71 53
72#define S5P64X0_PA_PCM (0xF2100000) 54#define S5P64X0_PA_PCM 0xF2100000
73 55
74#define S5P64X0_PA_ADC (0xF3000000) 56#define S5P64X0_PA_ADC 0xF3000000
75 57
76/* compatibiltiy defines. */ 58/* Compatibiltiy Defines */
77 59
78#define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0) 60#define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0)
79#define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1) 61#define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1)
@@ -83,6 +65,25 @@
83#define S3C_PA_RTC S5P64X0_PA_RTC 65#define S3C_PA_RTC S5P64X0_PA_RTC
84#define S3C_PA_WDT S5P64X0_PA_WDT 66#define S3C_PA_WDT S5P64X0_PA_WDT
85 67
68#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
69#define S5P_PA_SROMC S5P64X0_PA_SROMC
70#define S5P_PA_SYSCON S5P64X0_PA_SYSCON
71#define S5P_PA_TIMER S5P64X0_PA_TIMER
72
86#define SAMSUNG_PA_ADC S5P64X0_PA_ADC 73#define SAMSUNG_PA_ADC S5P64X0_PA_ADC
87 74
75/* UART */
76
77#define S5P6440_PA_UART(x) (0xEC000000 + ((x) * S3C_UART_OFFSET))
78#define S5P6450_PA_UART(x) ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
79
80#define S5P_PA_UART0 S5P6450_PA_UART(0)
81#define S5P_PA_UART1 S5P6450_PA_UART(1)
82#define S5P_PA_UART2 S5P6450_PA_UART(2)
83#define S5P_PA_UART3 S5P6450_PA_UART(3)
84#define S5P_PA_UART4 S5P6450_PA_UART(4)
85#define S5P_PA_UART5 S5P6450_PA_UART(5)
86
87#define S5P_SZ_UART SZ_256
88
88#endif /* __ASM_ARCH_MAP_H */ 89#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 328467b346aa..ccbe6b767f7d 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -1,5 +1,8 @@
1/* linux/arch/arm/mach-s5pc100/include/mach/map.h 1/* linux/arch/arm/mach-s5pc100/include/mach/map.h
2 * 2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
3 * Copyright 2009 Samsung Electronics Co. 6 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com> 7 * Byungho Min <bhmin@samsung.com>
5 * 8 *
@@ -16,145 +19,115 @@
16#include <plat/map-base.h> 19#include <plat/map-base.h>
17#include <plat/map-s5p.h> 20#include <plat/map-s5p.h>
18 21
19/* 22#define S5PC100_PA_SDRAM 0x20000000
20 * map-base.h has already defined virtual memory address 23
21 * S3C_VA_IRQ S3C_ADDR(0x00000000) irq controller(s) 24#define S5PC100_PA_ONENAND 0xE7100000
22 * S3C_VA_SYS S3C_ADDR(0x00100000) system control 25#define S5PC100_PA_ONENAND_BUF 0xB0000000
23 * S3C_VA_MEM S3C_ADDR(0x00200000) system control (not used) 26
24 * S3C_VA_TIMER S3C_ADDR(0x00300000) timer block 27#define S5PC100_PA_CHIPID 0xE0000000
25 * S3C_VA_WATCHDOG S3C_ADDR(0x00400000) watchdog
26 * S3C_VA_UART S3C_ADDR(0x01000000) UART
27 *
28 * S5PC100 specific virtual memory address can be defined here
29 * S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) GPIO
30 *
31 */
32 28
33#define S5PC100_PA_ONENAND_BUF (0xB0000000) 29#define S5PC100_PA_SYSCON 0xE0100000
34#define S5PC100_SZ_ONENAND_BUF (SZ_256M - SZ_32M)
35 30
36/* Chip ID */ 31#define S5PC100_PA_OTHERS 0xE0200000
37 32
38#define S5PC100_PA_CHIPID (0xE0000000) 33#define S5PC100_PA_GPIO 0xE0300000
39#define S5P_PA_CHIPID S5PC100_PA_CHIPID
40 34
41#define S5PC100_PA_SYSCON (0xE0100000) 35#define S5PC100_PA_VIC0 0xE4000000
42#define S5P_PA_SYSCON S5PC100_PA_SYSCON 36#define S5PC100_PA_VIC1 0xE4100000
37#define S5PC100_PA_VIC2 0xE4200000
43 38
44#define S5PC100_PA_OTHERS (0xE0200000) 39#define S5PC100_PA_SROMC 0xE7000000
45#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
46 40
47#define S5PC100_PA_GPIO (0xE0300000) 41#define S5PC100_PA_CFCON 0xE7800000
48#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000)
49 42
50/* Interrupt */ 43#define S5PC100_PA_MDMA 0xE8100000
51#define S5PC100_PA_VIC0 (0xE4000000) 44#define S5PC100_PA_PDMA0 0xE9000000
52#define S5PC100_PA_VIC1 (0xE4100000) 45#define S5PC100_PA_PDMA1 0xE9200000
53#define S5PC100_PA_VIC2 (0xE4200000)
54#define S5PC100_VA_VIC S3C_VA_IRQ
55#define S5PC100_VA_VIC_OFFSET 0x10000
56#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
57 46
58#define S5PC100_PA_SROMC (0xE7000000) 47#define S5PC100_PA_TIMER 0xEA000000
59#define S5P_PA_SROMC S5PC100_PA_SROMC 48#define S5PC100_PA_SYSTIMER 0xEA100000
49#define S5PC100_PA_WATCHDOG 0xEA200000
50#define S5PC100_PA_RTC 0xEA300000
60 51
61#define S5PC100_PA_ONENAND (0xE7100000) 52#define S5PC100_PA_UART 0xEC000000
62 53
63#define S5PC100_PA_CFCON (0xE7800000) 54#define S5PC100_PA_IIC0 0xEC100000
55#define S5PC100_PA_IIC1 0xEC200000
64 56
65/* DMA */ 57#define S5PC100_PA_SPI0 0xEC300000
66#define S5PC100_PA_MDMA (0xE8100000) 58#define S5PC100_PA_SPI1 0xEC400000
67#define S5PC100_PA_PDMA0 (0xE9000000) 59#define S5PC100_PA_SPI2 0xEC500000
68#define S5PC100_PA_PDMA1 (0xE9200000)
69 60
70/* Timer */ 61#define S5PC100_PA_USB_HSOTG 0xED200000
71#define S5PC100_PA_TIMER (0xEA000000) 62#define S5PC100_PA_USB_HSPHY 0xED300000
72#define S5P_PA_TIMER S5PC100_PA_TIMER
73 63
74#define S5PC100_PA_SYSTIMER (0xEA100000) 64#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
75 65
76#define S5PC100_PA_WATCHDOG (0xEA200000) 66#define S5PC100_PA_FB 0xEE000000
77#define S5PC100_PA_RTC (0xEA300000)
78 67
79#define S5PC100_PA_UART (0xEC000000) 68#define S5PC100_PA_FIMC0 0xEE200000
69#define S5PC100_PA_FIMC1 0xEE300000
70#define S5PC100_PA_FIMC2 0xEE400000
80 71
81#define S5P_PA_UART0 (S5PC100_PA_UART + 0x0) 72#define S5PC100_PA_I2S0 0xF2000000
82#define S5P_PA_UART1 (S5PC100_PA_UART + 0x400) 73#define S5PC100_PA_I2S1 0xF2100000
83#define S5P_PA_UART2 (S5PC100_PA_UART + 0x800) 74#define S5PC100_PA_I2S2 0xF2200000
84#define S5P_PA_UART3 (S5PC100_PA_UART + 0xC00)
85#define S5P_SZ_UART SZ_256
86 75
87#define S5PC100_PA_IIC0 (0xEC100000) 76#define S5PC100_PA_AC97 0xF2300000
88#define S5PC100_PA_IIC1 (0xEC200000)
89 77
90/* SPI */ 78#define S5PC100_PA_PCM0 0xF2400000
91#define S5PC100_PA_SPI0 0xEC300000 79#define S5PC100_PA_PCM1 0xF2500000
92#define S5PC100_PA_SPI1 0xEC400000
93#define S5PC100_PA_SPI2 0xEC500000
94 80
95/* USB HS OTG */ 81#define S5PC100_PA_SPDIF 0xF2600000
96#define S5PC100_PA_USB_HSOTG (0xED200000)
97#define S5PC100_PA_USB_HSPHY (0xED300000)
98 82
99#define S5PC100_PA_FB (0xEE000000) 83#define S5PC100_PA_TSADC 0xF3000000
100 84
101#define S5PC100_PA_FIMC0 (0xEE200000) 85#define S5PC100_PA_KEYPAD 0xF3100000
102#define S5PC100_PA_FIMC1 (0xEE300000)
103#define S5PC100_PA_FIMC2 (0xEE400000)
104 86
105#define S5PC100_PA_I2S0 (0xF2000000) 87/* Compatibiltiy Defines */
106#define S5PC100_PA_I2S1 (0xF2100000)
107#define S5PC100_PA_I2S2 (0xF2200000)
108 88
109#define S5PC100_PA_AC97 0xF2300000 89#define S3C_PA_FB S5PC100_PA_FB
90#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0)
91#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1)
92#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2)
93#define S3C_PA_IIC S5PC100_PA_IIC0
94#define S3C_PA_IIC1 S5PC100_PA_IIC1
95#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
96#define S3C_PA_ONENAND S5PC100_PA_ONENAND
97#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF
98#define S3C_PA_RTC S5PC100_PA_RTC
99#define S3C_PA_TSADC S5PC100_PA_TSADC
100#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
101#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
102#define S3C_PA_WDT S5PC100_PA_WATCHDOG
110 103
111/* PCM */ 104#define S5P_PA_CHIPID S5PC100_PA_CHIPID
112#define S5PC100_PA_PCM0 0xF2400000 105#define S5P_PA_FIMC0 S5PC100_PA_FIMC0
113#define S5PC100_PA_PCM1 0xF2500000 106#define S5P_PA_FIMC1 S5PC100_PA_FIMC1
107#define S5P_PA_FIMC2 S5PC100_PA_FIMC2
108#define S5P_PA_SDRAM S5PC100_PA_SDRAM
109#define S5P_PA_SROMC S5PC100_PA_SROMC
110#define S5P_PA_SYSCON S5PC100_PA_SYSCON
111#define S5P_PA_TIMER S5PC100_PA_TIMER
114 112
115#define S5PC100_PA_SPDIF 0xF2600000 113#define SAMSUNG_PA_ADC S5PC100_PA_TSADC
114#define SAMSUNG_PA_CFCON S5PC100_PA_CFCON
115#define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD
116 116
117#define S5PC100_PA_TSADC (0xF3000000) 117#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
118 118
119/* KEYPAD */ 119#define S3C_SZ_ONENAND_BUF (SZ_256M - SZ_32M)
120#define S5PC100_PA_KEYPAD (0xF3100000)
121 120
122#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) 121/* UART */
123 122
124#define S5PC100_PA_SDRAM (0x20000000) 123#define S3C_PA_UART S5PC100_PA_UART
125#define S5P_PA_SDRAM S5PC100_PA_SDRAM
126 124
127/* compatibiltiy defines. */ 125#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
128#define S3C_PA_UART S5PC100_PA_UART 126#define S5P_PA_UART0 S5P_PA_UART(0)
129#define S3C_PA_IIC S5PC100_PA_IIC0 127#define S5P_PA_UART1 S5P_PA_UART(1)
130#define S3C_PA_IIC1 S5PC100_PA_IIC1 128#define S5P_PA_UART2 S5P_PA_UART(2)
131#define S3C_PA_FB S5PC100_PA_FB 129#define S5P_PA_UART3 S5P_PA_UART(3)
132#define S3C_PA_G2D S5PC100_PA_G2D
133#define S3C_PA_G3D S5PC100_PA_G3D
134#define S3C_PA_JPEG S5PC100_PA_JPEG
135#define S3C_PA_ROTATOR S5PC100_PA_ROTATOR
136#define S5P_VA_VIC0 S5PC1XX_VA_VIC(0)
137#define S5P_VA_VIC1 S5PC1XX_VA_VIC(1)
138#define S5P_VA_VIC2 S5PC1XX_VA_VIC(2)
139#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
140#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
141#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0)
142#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1)
143#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2)
144#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
145#define S3C_PA_WDT S5PC100_PA_WATCHDOG
146#define S3C_PA_TSADC S5PC100_PA_TSADC
147#define S3C_PA_ONENAND S5PC100_PA_ONENAND
148#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF
149#define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF
150#define S3C_PA_RTC S5PC100_PA_RTC
151
152#define SAMSUNG_PA_ADC S5PC100_PA_TSADC
153#define SAMSUNG_PA_CFCON S5PC100_PA_CFCON
154#define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD
155 130
156#define S5P_PA_FIMC0 S5PC100_PA_FIMC0 131#define S5P_SZ_UART SZ_256
157#define S5P_PA_FIMC1 S5PC100_PA_FIMC1
158#define S5P_PA_FIMC2 S5PC100_PA_FIMC2
159 132
160#endif /* __ASM_ARCH_C100_MAP_H */ 133#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 3611492ad681..1dd58836fd4f 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -1,6 +1,6 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/map.h 1/* linux/arch/arm/mach-s5pv210/include/mach/map.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com/
5 * 5 *
6 * S5PV210 - Memory map definitions 6 * S5PV210 - Memory map definitions
@@ -16,122 +16,120 @@
16#include <plat/map-base.h> 16#include <plat/map-base.h>
17#include <plat/map-s5p.h> 17#include <plat/map-s5p.h>
18 18
19#define S5PV210_PA_SROM_BANK5 (0xA8000000) 19#define S5PV210_PA_SDRAM 0x20000000
20 20
21#define S5PC110_PA_ONENAND (0xB0000000) 21#define S5PV210_PA_SROM_BANK5 0xA8000000
22#define S5P_PA_ONENAND S5PC110_PA_ONENAND
23 22
24#define S5PC110_PA_ONENAND_DMA (0xB0600000) 23#define S5PC110_PA_ONENAND 0xB0000000
25#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA 24#define S5PC110_PA_ONENAND_DMA 0xB0600000
26 25
27#define S5PV210_PA_CHIPID (0xE0000000) 26#define S5PV210_PA_CHIPID 0xE0000000
28#define S5P_PA_CHIPID S5PV210_PA_CHIPID
29 27
30#define S5PV210_PA_SYSCON (0xE0100000) 28#define S5PV210_PA_SYSCON 0xE0100000
31#define S5P_PA_SYSCON S5PV210_PA_SYSCON
32 29
33#define S5PV210_PA_GPIO (0xE0200000) 30#define S5PV210_PA_GPIO 0xE0200000
34 31
35/* SPI */ 32#define S5PV210_PA_SPDIF 0xE1100000
36#define S5PV210_PA_SPI0 0xE1300000
37#define S5PV210_PA_SPI1 0xE1400000
38 33
39#define S5PV210_PA_KEYPAD (0xE1600000) 34#define S5PV210_PA_SPI0 0xE1300000
35#define S5PV210_PA_SPI1 0xE1400000
40 36
41#define S5PV210_PA_IIC0 (0xE1800000) 37#define S5PV210_PA_KEYPAD 0xE1600000
42#define S5PV210_PA_IIC1 (0xFAB00000)
43#define S5PV210_PA_IIC2 (0xE1A00000)
44 38
45#define S5PV210_PA_TIMER (0xE2500000) 39#define S5PV210_PA_ADC 0xE1700000
46#define S5P_PA_TIMER S5PV210_PA_TIMER
47 40
48#define S5PV210_PA_SYSTIMER (0xE2600000) 41#define S5PV210_PA_IIC0 0xE1800000
42#define S5PV210_PA_IIC1 0xFAB00000
43#define S5PV210_PA_IIC2 0xE1A00000
49 44
50#define S5PV210_PA_WATCHDOG (0xE2700000) 45#define S5PV210_PA_AC97 0xE2200000
51 46
52#define S5PV210_PA_RTC (0xE2800000) 47#define S5PV210_PA_PCM0 0xE2300000
53#define S5PV210_PA_UART (0xE2900000) 48#define S5PV210_PA_PCM1 0xE1200000
49#define S5PV210_PA_PCM2 0xE2B00000
54 50
55#define S5P_PA_UART0 (S5PV210_PA_UART + 0x0) 51#define S5PV210_PA_TIMER 0xE2500000
56#define S5P_PA_UART1 (S5PV210_PA_UART + 0x400) 52#define S5PV210_PA_SYSTIMER 0xE2600000
57#define S5P_PA_UART2 (S5PV210_PA_UART + 0x800) 53#define S5PV210_PA_WATCHDOG 0xE2700000
58#define S5P_PA_UART3 (S5PV210_PA_UART + 0xC00) 54#define S5PV210_PA_RTC 0xE2800000
59 55
60#define S5P_SZ_UART SZ_256 56#define S5PV210_PA_UART 0xE2900000
61 57
62#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) 58#define S5PV210_PA_SROMC 0xE8000000
63 59
64#define S5PV210_PA_SROMC (0xE8000000) 60#define S5PV210_PA_CFCON 0xE8200000
65#define S5P_PA_SROMC S5PV210_PA_SROMC
66 61
67#define S5PV210_PA_CFCON (0xE8200000) 62#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
68 63
69#define S5PV210_PA_MDMA 0xFA200000 64#define S5PV210_PA_HSOTG 0xEC000000
70#define S5PV210_PA_PDMA0 0xE0900000 65#define S5PV210_PA_HSPHY 0xEC100000
71#define S5PV210_PA_PDMA1 0xE0A00000
72 66
73#define S5PV210_PA_FB (0xF8000000) 67#define S5PV210_PA_IIS0 0xEEE30000
68#define S5PV210_PA_IIS1 0xE2100000
69#define S5PV210_PA_IIS2 0xE2A00000
74 70
75#define S5PV210_PA_FIMC0 (0xFB200000) 71#define S5PV210_PA_DMC0 0xF0000000
76#define S5PV210_PA_FIMC1 (0xFB300000) 72#define S5PV210_PA_DMC1 0xF1400000
77#define S5PV210_PA_FIMC2 (0xFB400000)
78 73
79#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) 74#define S5PV210_PA_VIC0 0xF2000000
75#define S5PV210_PA_VIC1 0xF2100000
76#define S5PV210_PA_VIC2 0xF2200000
77#define S5PV210_PA_VIC3 0xF2300000
80 78
81#define S5PV210_PA_HSOTG (0xEC000000) 79#define S5PV210_PA_FB 0xF8000000
82#define S5PV210_PA_HSPHY (0xEC100000)
83 80
84#define S5PV210_PA_VIC0 (0xF2000000) 81#define S5PV210_PA_MDMA 0xFA200000
85#define S5PV210_PA_VIC1 (0xF2100000) 82#define S5PV210_PA_PDMA0 0xE0900000
86#define S5PV210_PA_VIC2 (0xF2200000) 83#define S5PV210_PA_PDMA1 0xE0A00000
87#define S5PV210_PA_VIC3 (0xF2300000)
88 84
89#define S5PV210_PA_SDRAM (0x20000000) 85#define S5PV210_PA_MIPI_CSIS 0xFA600000
90#define S5P_PA_SDRAM S5PV210_PA_SDRAM
91 86
92/* S/PDIF */ 87#define S5PV210_PA_FIMC0 0xFB200000
93#define S5PV210_PA_SPDIF 0xE1100000 88#define S5PV210_PA_FIMC1 0xFB300000
89#define S5PV210_PA_FIMC2 0xFB400000
94 90
95/* I2S */ 91/* Compatibiltiy Defines */
96#define S5PV210_PA_IIS0 0xEEE30000
97#define S5PV210_PA_IIS1 0xE2100000
98#define S5PV210_PA_IIS2 0xE2A00000
99 92
100/* PCM */ 93#define S3C_PA_FB S5PV210_PA_FB
101#define S5PV210_PA_PCM0 0xE2300000 94#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0)
102#define S5PV210_PA_PCM1 0xE1200000 95#define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1)
103#define S5PV210_PA_PCM2 0xE2B00000 96#define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2)
97#define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3)
98#define S3C_PA_IIC S5PV210_PA_IIC0
99#define S3C_PA_IIC1 S5PV210_PA_IIC1
100#define S3C_PA_IIC2 S5PV210_PA_IIC2
101#define S3C_PA_RTC S5PV210_PA_RTC
102#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
103#define S3C_PA_WDT S5PV210_PA_WATCHDOG
104 104
105/* AC97 */ 105#define S5P_PA_CHIPID S5PV210_PA_CHIPID
106#define S5PV210_PA_AC97 0xE2200000 106#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
107#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
108#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
109#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
110#define S5P_PA_ONENAND S5PC110_PA_ONENAND
111#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
112#define S5P_PA_SDRAM S5PV210_PA_SDRAM
113#define S5P_PA_SROMC S5PV210_PA_SROMC
114#define S5P_PA_SYSCON S5PV210_PA_SYSCON
115#define S5P_PA_TIMER S5PV210_PA_TIMER
107 116
108#define S5PV210_PA_ADC (0xE1700000) 117#define SAMSUNG_PA_ADC S5PV210_PA_ADC
118#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON
119#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD
109 120
110#define S5PV210_PA_DMC0 (0xF0000000) 121/* UART */
111#define S5PV210_PA_DMC1 (0xF1400000)
112 122
113#define S5PV210_PA_MIPI_CSIS 0xFA600000 123#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
114 124
115/* compatibiltiy defines. */ 125#define S3C_PA_UART S5PV210_PA_UART
116#define S3C_PA_UART S5PV210_PA_UART
117#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0)
118#define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1)
119#define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2)
120#define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3)
121#define S3C_PA_IIC S5PV210_PA_IIC0
122#define S3C_PA_IIC1 S5PV210_PA_IIC1
123#define S3C_PA_IIC2 S5PV210_PA_IIC2
124#define S3C_PA_FB S5PV210_PA_FB
125#define S3C_PA_RTC S5PV210_PA_RTC
126#define S3C_PA_WDT S5PV210_PA_WATCHDOG
127#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
128#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
129#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
130#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
131#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
132 126
133#define SAMSUNG_PA_ADC S5PV210_PA_ADC 127#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
134#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON 128#define S5P_PA_UART0 S5P_PA_UART(0)
135#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD 129#define S5P_PA_UART1 S5P_PA_UART(1)
130#define S5P_PA_UART2 S5P_PA_UART(2)
131#define S5P_PA_UART3 S5P_PA_UART(3)
132
133#define S5P_SZ_UART SZ_256
136 134
137#endif /* __ASM_ARCH_MAP_H */ 135#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 461aa035afc0..557add4fc56c 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -149,7 +149,7 @@ static struct regulator_init_data aquila_ldo2_data = {
149 149
150static struct regulator_init_data aquila_ldo3_data = { 150static struct regulator_init_data aquila_ldo3_data = {
151 .constraints = { 151 .constraints = {
152 .name = "VUSB/MIPI_1.1V", 152 .name = "VUSB+MIPI_1.1V",
153 .min_uV = 1100000, 153 .min_uV = 1100000,
154 .max_uV = 1100000, 154 .max_uV = 1100000,
155 .apply_uV = 1, 155 .apply_uV = 1,
@@ -197,7 +197,7 @@ static struct regulator_init_data aquila_ldo7_data = {
197 197
198static struct regulator_init_data aquila_ldo8_data = { 198static struct regulator_init_data aquila_ldo8_data = {
199 .constraints = { 199 .constraints = {
200 .name = "VUSB/VADC_3.3V", 200 .name = "VUSB+VADC_3.3V",
201 .min_uV = 3300000, 201 .min_uV = 3300000,
202 .max_uV = 3300000, 202 .max_uV = 3300000,
203 .apply_uV = 1, 203 .apply_uV = 1,
@@ -207,7 +207,7 @@ static struct regulator_init_data aquila_ldo8_data = {
207 207
208static struct regulator_init_data aquila_ldo9_data = { 208static struct regulator_init_data aquila_ldo9_data = {
209 .constraints = { 209 .constraints = {
210 .name = "VCC/VCAM_2.8V", 210 .name = "VCC+VCAM_2.8V",
211 .min_uV = 2800000, 211 .min_uV = 2800000,
212 .max_uV = 2800000, 212 .max_uV = 2800000,
213 .apply_uV = 1, 213 .apply_uV = 1,
@@ -381,9 +381,12 @@ static struct max8998_platform_data aquila_max8998_pdata = {
381 .buck1_set1 = S5PV210_GPH0(3), 381 .buck1_set1 = S5PV210_GPH0(3),
382 .buck1_set2 = S5PV210_GPH0(4), 382 .buck1_set2 = S5PV210_GPH0(4),
383 .buck2_set3 = S5PV210_GPH0(5), 383 .buck2_set3 = S5PV210_GPH0(5),
384 .buck1_max_voltage1 = 1200000, 384 .buck1_voltage1 = 1200000,
385 .buck1_max_voltage2 = 1200000, 385 .buck1_voltage2 = 1200000,
386 .buck2_max_voltage = 1200000, 386 .buck1_voltage3 = 1200000,
387 .buck1_voltage4 = 1200000,
388 .buck2_voltage1 = 1200000,
389 .buck2_voltage2 = 1200000,
387}; 390};
388#endif 391#endif
389 392
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index e22d5112fd44..056f5c769b0a 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -288,7 +288,7 @@ static struct regulator_init_data goni_ldo2_data = {
288 288
289static struct regulator_init_data goni_ldo3_data = { 289static struct regulator_init_data goni_ldo3_data = {
290 .constraints = { 290 .constraints = {
291 .name = "VUSB/MIPI_1.1V", 291 .name = "VUSB+MIPI_1.1V",
292 .min_uV = 1100000, 292 .min_uV = 1100000,
293 .max_uV = 1100000, 293 .max_uV = 1100000,
294 .apply_uV = 1, 294 .apply_uV = 1,
@@ -337,7 +337,7 @@ static struct regulator_init_data goni_ldo7_data = {
337 337
338static struct regulator_init_data goni_ldo8_data = { 338static struct regulator_init_data goni_ldo8_data = {
339 .constraints = { 339 .constraints = {
340 .name = "VUSB/VADC_3.3V", 340 .name = "VUSB+VADC_3.3V",
341 .min_uV = 3300000, 341 .min_uV = 3300000,
342 .max_uV = 3300000, 342 .max_uV = 3300000,
343 .apply_uV = 1, 343 .apply_uV = 1,
@@ -347,7 +347,7 @@ static struct regulator_init_data goni_ldo8_data = {
347 347
348static struct regulator_init_data goni_ldo9_data = { 348static struct regulator_init_data goni_ldo9_data = {
349 .constraints = { 349 .constraints = {
350 .name = "VCC/VCAM_2.8V", 350 .name = "VCC+VCAM_2.8V",
351 .min_uV = 2800000, 351 .min_uV = 2800000,
352 .max_uV = 2800000, 352 .max_uV = 2800000,
353 .apply_uV = 1, 353 .apply_uV = 1,
@@ -521,9 +521,12 @@ static struct max8998_platform_data goni_max8998_pdata = {
521 .buck1_set1 = S5PV210_GPH0(3), 521 .buck1_set1 = S5PV210_GPH0(3),
522 .buck1_set2 = S5PV210_GPH0(4), 522 .buck1_set2 = S5PV210_GPH0(4),
523 .buck2_set3 = S5PV210_GPH0(5), 523 .buck2_set3 = S5PV210_GPH0(5),
524 .buck1_max_voltage1 = 1200000, 524 .buck1_voltage1 = 1200000,
525 .buck1_max_voltage2 = 1200000, 525 .buck1_voltage2 = 1200000,
526 .buck2_max_voltage = 1200000, 526 .buck1_voltage3 = 1200000,
527 .buck1_voltage4 = 1200000,
528 .buck2_voltage1 = 1200000,
529 .buck2_voltage2 = 1200000,
527}; 530};
528#endif 531#endif
529 532
diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig
index 09c4c21b70cc..b2a9acc5185f 100644
--- a/arch/arm/mach-s5pv310/Kconfig
+++ b/arch/arm/mach-s5pv310/Kconfig
@@ -122,6 +122,7 @@ config MACH_SMDKV310
122 select S3C_DEV_HSMMC2 122 select S3C_DEV_HSMMC2
123 select S3C_DEV_HSMMC3 123 select S3C_DEV_HSMMC3
124 select S5PV310_DEV_PD 124 select S5PV310_DEV_PD
125 select S5PV310_DEV_SYSMMU
125 select S5PV310_SETUP_I2C1 126 select S5PV310_SETUP_I2C1
126 select S5PV310_SETUP_SDHCI 127 select S5PV310_SETUP_SDHCI
127 help 128 help
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
index 74d400625a23..901657fa7a12 100644
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -1,6 +1,6 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/map.h 1/* linux/arch/arm/mach-s5pv310/include/mach/map.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com/
5 * 5 *
6 * S5PV310 - Memory map definitions 6 * S5PV310 - Memory map definitions
@@ -23,90 +23,43 @@
23 23
24#include <plat/map-s5p.h> 24#include <plat/map-s5p.h>
25 25
26#define S5PV310_PA_SYSRAM (0x02025000) 26#define S5PV310_PA_SYSRAM 0x02025000
27 27
28#define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000)) 28#define S5PV310_PA_I2S0 0x03830000
29 29#define S5PV310_PA_I2S1 0xE3100000
30#define S5PC210_PA_ONENAND (0x0C000000) 30#define S5PV310_PA_I2S2 0xE2A00000
31#define S5P_PA_ONENAND S5PC210_PA_ONENAND
32
33#define S5PC210_PA_ONENAND_DMA (0x0C600000)
34#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
35
36#define S5PV310_PA_CHIPID (0x10000000)
37#define S5P_PA_CHIPID S5PV310_PA_CHIPID
38
39#define S5PV310_PA_SYSCON (0x10010000)
40#define S5P_PA_SYSCON S5PV310_PA_SYSCON
41 31
42#define S5PV310_PA_PMU (0x10020000) 32#define S5PV310_PA_PCM0 0x03840000
33#define S5PV310_PA_PCM1 0x13980000
34#define S5PV310_PA_PCM2 0x13990000
43 35
44#define S5PV310_PA_CMU (0x10030000) 36#define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
45
46#define S5PV310_PA_WATCHDOG (0x10060000)
47#define S5PV310_PA_RTC (0x10070000)
48
49#define S5PV310_PA_DMC0 (0x10400000)
50
51#define S5PV310_PA_COMBINER (0x10448000)
52
53#define S5PV310_PA_COREPERI (0x10500000)
54#define S5PV310_PA_GIC_CPU (0x10500100)
55#define S5PV310_PA_TWD (0x10500600)
56#define S5PV310_PA_GIC_DIST (0x10501000)
57#define S5PV310_PA_L2CC (0x10502000)
58
59/* DMA */
60#define S5PV310_PA_MDMA 0x10810000
61#define S5PV310_PA_PDMA0 0x12680000
62#define S5PV310_PA_PDMA1 0x12690000
63
64#define S5PV310_PA_GPIO1 (0x11400000)
65#define S5PV310_PA_GPIO2 (0x11000000)
66#define S5PV310_PA_GPIO3 (0x03860000)
67
68#define S5PV310_PA_MIPI_CSIS0 0x11880000
69#define S5PV310_PA_MIPI_CSIS1 0x11890000
70 37
71#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) 38#define S5PC210_PA_ONENAND 0x0C000000
39#define S5PC210_PA_ONENAND_DMA 0x0C600000
72 40
73#define S5PV310_PA_SROMC (0x12570000) 41#define S5PV310_PA_CHIPID 0x10000000
74#define S5P_PA_SROMC S5PV310_PA_SROMC
75 42
76/* S/PDIF */ 43#define S5PV310_PA_SYSCON 0x10010000
77#define S5PV310_PA_SPDIF 0xE1100000 44#define S5PV310_PA_PMU 0x10020000
45#define S5PV310_PA_CMU 0x10030000
78 46
79/* I2S */ 47#define S5PV310_PA_WATCHDOG 0x10060000
80#define S5PV310_PA_I2S0 0x03830000 48#define S5PV310_PA_RTC 0x10070000
81#define S5PV310_PA_I2S1 0xE3100000
82#define S5PV310_PA_I2S2 0xE2A00000
83 49
84/* PCM */ 50#define S5PV310_PA_DMC0 0x10400000
85#define S5PV310_PA_PCM0 0x03840000
86#define S5PV310_PA_PCM1 0x13980000
87#define S5PV310_PA_PCM2 0x13990000
88 51
89/* AC97 */ 52#define S5PV310_PA_COMBINER 0x10448000
90#define S5PV310_PA_AC97 0x139A0000
91 53
92#define S5PV310_PA_UART (0x13800000) 54#define S5PV310_PA_COREPERI 0x10500000
55#define S5PV310_PA_GIC_CPU 0x10500100
56#define S5PV310_PA_TWD 0x10500600
57#define S5PV310_PA_GIC_DIST 0x10501000
58#define S5PV310_PA_L2CC 0x10502000
93 59
94#define S5P_PA_UART(x) (S5PV310_PA_UART + ((x) * S3C_UART_OFFSET)) 60#define S5PV310_PA_MDMA 0x10810000
95#define S5P_PA_UART0 S5P_PA_UART(0) 61#define S5PV310_PA_PDMA0 0x12680000
96#define S5P_PA_UART1 S5P_PA_UART(1) 62#define S5PV310_PA_PDMA1 0x12690000
97#define S5P_PA_UART2 S5P_PA_UART(2)
98#define S5P_PA_UART3 S5P_PA_UART(3)
99#define S5P_PA_UART4 S5P_PA_UART(4)
100
101#define S5P_SZ_UART SZ_256
102
103#define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
104
105#define S5PV310_PA_TIMER (0x139D0000)
106#define S5P_PA_TIMER S5PV310_PA_TIMER
107
108#define S5PV310_PA_SDRAM (0x40000000)
109#define S5P_PA_SDRAM S5PV310_PA_SDRAM
110 63
111#define S5PV310_PA_SYSMMU_MDMA 0x10A40000 64#define S5PV310_PA_SYSMMU_MDMA 0x10A40000
112#define S5PV310_PA_SYSMMU_SSS 0x10A50000 65#define S5PV310_PA_SYSMMU_SSS 0x10A50000
@@ -124,11 +77,32 @@
124#define S5PV310_PA_SYSMMU_TV 0x12E20000 77#define S5PV310_PA_SYSMMU_TV 0x12E20000
125#define S5PV310_PA_SYSMMU_MFC_L 0x13620000 78#define S5PV310_PA_SYSMMU_MFC_L 0x13620000
126#define S5PV310_PA_SYSMMU_MFC_R 0x13630000 79#define S5PV310_PA_SYSMMU_MFC_R 0x13630000
127#define S5PV310_SYSMMU_TOTAL_IPNUM 16
128#define S5P_SYSMMU_TOTAL_IPNUM S5PV310_SYSMMU_TOTAL_IPNUM
129 80
130/* compatibiltiy defines. */ 81#define S5PV310_PA_GPIO1 0x11400000
131#define S3C_PA_UART S5PV310_PA_UART 82#define S5PV310_PA_GPIO2 0x11000000
83#define S5PV310_PA_GPIO3 0x03860000
84
85#define S5PV310_PA_MIPI_CSIS0 0x11880000
86#define S5PV310_PA_MIPI_CSIS1 0x11890000
87
88#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
89
90#define S5PV310_PA_SROMC 0x12570000
91
92#define S5PV310_PA_UART 0x13800000
93
94#define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
95
96#define S5PV310_PA_AC97 0x139A0000
97
98#define S5PV310_PA_TIMER 0x139D0000
99
100#define S5PV310_PA_SDRAM 0x40000000
101
102#define S5PV310_PA_SPDIF 0xE1100000
103
104/* Compatibiltiy Defines */
105
132#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0) 106#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
133#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1) 107#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
134#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2) 108#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
@@ -143,7 +117,28 @@
143#define S3C_PA_IIC7 S5PV310_PA_IIC(7) 117#define S3C_PA_IIC7 S5PV310_PA_IIC(7)
144#define S3C_PA_RTC S5PV310_PA_RTC 118#define S3C_PA_RTC S5PV310_PA_RTC
145#define S3C_PA_WDT S5PV310_PA_WATCHDOG 119#define S3C_PA_WDT S5PV310_PA_WATCHDOG
120
121#define S5P_PA_CHIPID S5PV310_PA_CHIPID
146#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0 122#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0
147#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1 123#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1
124#define S5P_PA_ONENAND S5PC210_PA_ONENAND
125#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
126#define S5P_PA_SDRAM S5PV310_PA_SDRAM
127#define S5P_PA_SROMC S5PV310_PA_SROMC
128#define S5P_PA_SYSCON S5PV310_PA_SYSCON
129#define S5P_PA_TIMER S5PV310_PA_TIMER
130
131/* UART */
132
133#define S3C_PA_UART S5PV310_PA_UART
134
135#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
136#define S5P_PA_UART0 S5P_PA_UART(0)
137#define S5P_PA_UART1 S5P_PA_UART(1)
138#define S5P_PA_UART2 S5P_PA_UART(2)
139#define S5P_PA_UART3 S5P_PA_UART(3)
140#define S5P_PA_UART4 S5P_PA_UART(4)
141
142#define S5P_SZ_UART SZ_256
148 143
149#endif /* __ASM_ARCH_MAP_H */ 144#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/sysmmu.h b/arch/arm/mach-s5pv310/include/mach/sysmmu.h
index 662fe85ff4d5..598fc5c9211b 100644
--- a/arch/arm/mach-s5pv310/include/mach/sysmmu.h
+++ b/arch/arm/mach-s5pv310/include/mach/sysmmu.h
@@ -13,6 +13,9 @@
13#ifndef __ASM_ARM_ARCH_SYSMMU_H 13#ifndef __ASM_ARM_ARCH_SYSMMU_H
14#define __ASM_ARM_ARCH_SYSMMU_H __FILE__ 14#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
15 15
16#define S5PV310_SYSMMU_TOTAL_IPNUM 16
17#define S5P_SYSMMU_TOTAL_IPNUM S5PV310_SYSMMU_TOTAL_IPNUM
18
16enum s5pv310_sysmmu_ips { 19enum s5pv310_sysmmu_ips {
17 SYSMMU_MDMA, 20 SYSMMU_MDMA,
18 SYSMMU_SSS, 21 SYSMMU_SSS,
@@ -32,7 +35,7 @@ enum s5pv310_sysmmu_ips {
32 SYSMMU_MFC_R, 35 SYSMMU_MFC_R,
33}; 36};
34 37
35static char *sysmmu_ips_name[S5P_SYSMMU_TOTAL_IPNUM] = { 38static char *sysmmu_ips_name[S5PV310_SYSMMU_TOTAL_IPNUM] = {
36 "SYSMMU_MDMA" , 39 "SYSMMU_MDMA" ,
37 "SYSMMU_SSS" , 40 "SYSMMU_SSS" ,
38 "SYSMMU_FIMC0" , 41 "SYSMMU_FIMC0" ,
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index d43c5ef58eb6..bd3e1bfdd6aa 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -241,6 +241,9 @@ static struct locomo_platform_data locomo_info = {
241struct platform_device collie_locomo_device = { 241struct platform_device collie_locomo_device = {
242 .name = "locomo", 242 .name = "locomo",
243 .id = 0, 243 .id = 0,
244 .dev = {
245 .platform_data = &locomo_info,
246 },
244 .num_resources = ARRAY_SIZE(locomo_resources), 247 .num_resources = ARRAY_SIZE(locomo_resources),
245 .resource = locomo_resources, 248 .resource = locomo_resources,
246}; 249};
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index cacf17a958cd..53677e464d4b 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -62,7 +62,7 @@
62#define SPEAR320_SMII1_BASE 0xAB000000 62#define SPEAR320_SMII1_BASE 0xAB000000
63#define SPEAR320_SMII1_SIZE 0x01000000 63#define SPEAR320_SMII1_SIZE 0x01000000
64 64
65#define SPEAR320_SOC_CONFIG_BASE 0xB4000000 65#define SPEAR320_SOC_CONFIG_BASE 0xB3000000
66#define SPEAR320_SOC_CONFIG_SIZE 0x00000070 66#define SPEAR320_SOC_CONFIG_SIZE 0x00000070
67/* Interrupt registers offsets and masks */ 67/* Interrupt registers offsets and masks */
68#define INT_STS_MASK_REG 0x04 68#define INT_STS_MASK_REG 0x04
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c
index bd066206e110..ad8048801513 100644
--- a/arch/arm/mach-tegra/gpio.c
+++ b/arch/arm/mach-tegra/gpio.c
@@ -207,9 +207,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
207 spin_unlock_irqrestore(&bank->lvl_lock[port], flags); 207 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
208 208
209 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 209 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
210 __set_irq_handler_unlocked(irq, handle_level_irq); 210 __set_irq_handler_unlocked(d->irq, handle_level_irq);
211 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 211 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
212 __set_irq_handler_unlocked(irq, handle_edge_irq); 212 __set_irq_handler_unlocked(d->irq, handle_edge_irq);
213 213
214 return 0; 214 return 0;
215} 215}
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index d7723955dac7..a217f68ba57c 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -20,6 +20,8 @@
20#ifndef __MACH_CLK_H 20#ifndef __MACH_CLK_H
21#define __MACH_CLK_H 21#define __MACH_CLK_H
22 22
23struct clk;
24
23void tegra_periph_reset_deassert(struct clk *c); 25void tegra_periph_reset_deassert(struct clk *c);
24void tegra_periph_reset_assert(struct clk *c); 26void tegra_periph_reset_assert(struct clk *c);
25 27
diff --git a/arch/arm/mach-tegra/include/mach/clkdev.h b/arch/arm/mach-tegra/include/mach/clkdev.h
index 412f5c63e65a..66cd3f4fc896 100644
--- a/arch/arm/mach-tegra/include/mach/clkdev.h
+++ b/arch/arm/mach-tegra/include/mach/clkdev.h
@@ -20,6 +20,8 @@
20#ifndef __MACH_CLKDEV_H 20#ifndef __MACH_CLKDEV_H
21#define __MACH_CLKDEV_H 21#define __MACH_CLKDEV_H
22 22
23struct clk;
24
23static inline int __clk_get(struct clk *clk) 25static inline int __clk_get(struct clk *clk)
24{ 26{
25 return 1; 27 return 1;
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index de7dfad6f769..17c74d21077c 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -46,24 +46,24 @@
46#define ICTLR_COP_IER_CLR 0x38 46#define ICTLR_COP_IER_CLR 0x38
47#define ICTLR_COP_IEP_CLASS 0x3c 47#define ICTLR_COP_IEP_CLASS 0x3c
48 48
49static void (*gic_mask_irq)(struct irq_data *d); 49static void (*tegra_gic_mask_irq)(struct irq_data *d);
50static void (*gic_unmask_irq)(struct irq_data *d); 50static void (*tegra_gic_unmask_irq)(struct irq_data *d);
51 51
52#define irq_to_ictlr(irq) (((irq)-32) >> 5) 52#define irq_to_ictlr(irq) (((irq) - 32) >> 5)
53static void __iomem *tegra_ictlr_base = IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE); 53static void __iomem *tegra_ictlr_base = IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE);
54#define ictlr_to_virt(ictlr) (tegra_ictlr_base + (ictlr)*0x100) 54#define ictlr_to_virt(ictlr) (tegra_ictlr_base + (ictlr) * 0x100)
55 55
56static void tegra_mask(struct irq_data *d) 56static void tegra_mask(struct irq_data *d)
57{ 57{
58 void __iomem *addr = ictlr_to_virt(irq_to_ictlr(d->irq)); 58 void __iomem *addr = ictlr_to_virt(irq_to_ictlr(d->irq));
59 gic_mask_irq(d); 59 tegra_gic_mask_irq(d);
60 writel(1<<(d->irq&31), addr+ICTLR_CPU_IER_CLR); 60 writel(1 << (d->irq & 31), addr+ICTLR_CPU_IER_CLR);
61} 61}
62 62
63static void tegra_unmask(struct irq_data *d) 63static void tegra_unmask(struct irq_data *d)
64{ 64{
65 void __iomem *addr = ictlr_to_virt(irq_to_ictlr(d->irq)); 65 void __iomem *addr = ictlr_to_virt(irq_to_ictlr(d->irq));
66 gic_unmask_irq(d); 66 tegra_gic_unmask_irq(d);
67 writel(1<<(d->irq&31), addr+ICTLR_CPU_IER_SET); 67 writel(1<<(d->irq&31), addr+ICTLR_CPU_IER_SET);
68} 68}
69 69
@@ -98,8 +98,8 @@ void __init tegra_init_irq(void)
98 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); 98 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
99 99
100 gic = get_irq_chip(29); 100 gic = get_irq_chip(29);
101 gic_unmask_irq = gic->irq_unmask; 101 tegra_gic_unmask_irq = gic->irq_unmask;
102 gic_mask_irq = gic->irq_mask; 102 tegra_gic_mask_irq = gic->irq_mask;
103 tegra_irq.irq_ack = gic->irq_ack; 103 tegra_irq.irq_ack = gic->irq_ack;
104#ifdef CONFIG_SMP 104#ifdef CONFIG_SMP
105 tegra_irq.irq_set_affinity = gic->irq_set_affinity; 105 tegra_irq.irq_set_affinity = gic->irq_set_affinity;
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 9d30c6f804b9..e4509bae8fc4 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -405,7 +405,7 @@ config CPU_V6
405config CPU_32v6K 405config CPU_32v6K
406 bool "Support ARM V6K processor extensions" if !SMP 406 bool "Support ARM V6K processor extensions" if !SMP
407 depends on CPU_V6 || CPU_V7 407 depends on CPU_V6 || CPU_V7
408 default y if SMP && !(ARCH_MX3 || ARCH_OMAP2) 408 default y if SMP
409 help 409 help
410 Say Y here if your ARMv6 processor supports the 'K' extension. 410 Say Y here if your ARMv6 processor supports the 'K' extension.
411 This enables the kernel to use some instructions not present 411 This enables the kernel to use some instructions not present
@@ -416,7 +416,7 @@ config CPU_32v6K
416# ARMv7 416# ARMv7
417config CPU_V7 417config CPU_V7
418 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX 418 bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
419 select CPU_32v6K if !ARCH_OMAP2 419 select CPU_32v6K
420 select CPU_32v7 420 select CPU_32v7
421 select CPU_ABRT_EV7 421 select CPU_ABRT_EV7
422 select CPU_PABRT_V7 422 select CPU_PABRT_V7
@@ -644,7 +644,7 @@ config ARM_THUMBEE
644 644
645config SWP_EMULATE 645config SWP_EMULATE
646 bool "Emulate SWP/SWPB instructions" 646 bool "Emulate SWP/SWPB instructions"
647 depends on CPU_V7 && !CPU_V6 647 depends on !CPU_USE_DOMAINS && CPU_V7 && !CPU_V6
648 select HAVE_PROC_CPU if PROC_FS 648 select HAVE_PROC_CPU if PROC_FS
649 default y if SMP 649 default y if SMP
650 help 650 help
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 170c9bb95866..f2ce38e085d2 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -49,7 +49,13 @@ static inline void cache_wait(void __iomem *reg, unsigned long mask)
49static inline void cache_sync(void) 49static inline void cache_sync(void)
50{ 50{
51 void __iomem *base = l2x0_base; 51 void __iomem *base = l2x0_base;
52
53#ifdef CONFIG_ARM_ERRATA_753970
54 /* write to an unmmapped register */
55 writel_relaxed(0, base + L2X0_DUMMY_REG);
56#else
52 writel_relaxed(0, base + L2X0_CACHE_SYNC); 57 writel_relaxed(0, base + L2X0_CACHE_SYNC);
58#endif
53 cache_wait(base + L2X0_CACHE_SYNC, 1); 59 cache_wait(base + L2X0_CACHE_SYNC, 1);
54} 60}
55 61
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 5164069ced42..cddd684364da 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -297,6 +297,12 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
297 memblock_reserve(__pa(_stext), _end - _stext); 297 memblock_reserve(__pa(_stext), _end - _stext);
298#endif 298#endif
299#ifdef CONFIG_BLK_DEV_INITRD 299#ifdef CONFIG_BLK_DEV_INITRD
300 if (phys_initrd_size &&
301 memblock_is_region_reserved(phys_initrd_start, phys_initrd_size)) {
302 pr_err("INITRD: 0x%08lx+0x%08lx overlaps in-use memory region - disabling initrd\n",
303 phys_initrd_start, phys_initrd_size);
304 phys_initrd_start = phys_initrd_size = 0;
305 }
300 if (phys_initrd_size) { 306 if (phys_initrd_size) {
301 memblock_reserve(phys_initrd_start, phys_initrd_size); 307 memblock_reserve(phys_initrd_start, phys_initrd_size);
302 308
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 0c1172b56b4e..8e3356239136 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -264,6 +264,12 @@ __v7_setup:
264 orreq r10, r10, #1 << 6 @ set bit #6 264 orreq r10, r10, #1 << 6 @ set bit #6
265 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 265 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
266#endif 266#endif
267#ifdef CONFIG_ARM_ERRATA_751472
268 cmp r6, #0x30 @ present prior to r3p0
269 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
270 orrlt r10, r10, #1 << 11 @ set bit #11
271 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
272#endif
267 273
2683: mov r10, #0 2743: mov r10, #0
269#ifdef HARVARD_CACHE 275#ifdef HARVARD_CACHE
diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c
index 8aa974491dfc..c074e66ad224 100644
--- a/arch/arm/oprofile/common.c
+++ b/arch/arm/oprofile/common.c
@@ -10,8 +10,6 @@
10 */ 10 */
11 11
12#include <linux/cpumask.h> 12#include <linux/cpumask.h>
13#include <linux/err.h>
14#include <linux/errno.h>
15#include <linux/init.h> 13#include <linux/init.h>
16#include <linux/mutex.h> 14#include <linux/mutex.h>
17#include <linux/oprofile.h> 15#include <linux/oprofile.h>
@@ -46,6 +44,7 @@ char *op_name_from_perf_id(void)
46 return NULL; 44 return NULL;
47 } 45 }
48} 46}
47#endif
49 48
50static int report_trace(struct stackframe *frame, void *d) 49static int report_trace(struct stackframe *frame, void *d)
51{ 50{
@@ -85,7 +84,7 @@ static struct frame_tail* user_backtrace(struct frame_tail *tail)
85 84
86 /* frame pointers should strictly progress back up the stack 85 /* frame pointers should strictly progress back up the stack
87 * (towards higher addresses) */ 86 * (towards higher addresses) */
88 if (tail >= buftail[0].fp) 87 if (tail + 1 >= buftail[0].fp)
89 return NULL; 88 return NULL;
90 89
91 return buftail[0].fp-1; 90 return buftail[0].fp-1;
@@ -111,6 +110,7 @@ static void arm_backtrace(struct pt_regs * const regs, unsigned int depth)
111 110
112int __init oprofile_arch_init(struct oprofile_operations *ops) 111int __init oprofile_arch_init(struct oprofile_operations *ops)
113{ 112{
113 /* provide backtrace support also in timer mode: */
114 ops->backtrace = arm_backtrace; 114 ops->backtrace = arm_backtrace;
115 115
116 return oprofile_perf_init(ops); 116 return oprofile_perf_init(ops);
@@ -120,11 +120,3 @@ void __exit oprofile_arch_exit(void)
120{ 120{
121 oprofile_perf_exit(); 121 oprofile_perf_exit();
122} 122}
123#else
124int __init oprofile_arch_init(struct oprofile_operations *ops)
125{
126 pr_info("oprofile: hardware counters not available\n");
127 return -ENODEV;
128}
129void __exit oprofile_arch_exit(void) {}
130#endif /* CONFIG_HW_PERF_EVENTS */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index 3a70ebf0477f..ff469c4f1d76 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -95,6 +95,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
95 case MACH_TYPE_MX35_3DS: 95 case MACH_TYPE_MX35_3DS:
96 case MACH_TYPE_PCM043: 96 case MACH_TYPE_PCM043:
97 case MACH_TYPE_LILLY1131: 97 case MACH_TYPE_LILLY1131:
98 case MACH_TYPE_VPR200:
98 uart_base = MX3X_UART1_BASE_ADDR; 99 uart_base = MX3X_UART1_BASE_ADDR;
99 break; 100 break;
100 case MACH_TYPE_MAGX_ZN5: 101 case MACH_TYPE_MAGX_ZN5:
@@ -102,6 +103,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
102 break; 103 break;
103 case MACH_TYPE_MX51_BABBAGE: 104 case MACH_TYPE_MX51_BABBAGE:
104 case MACH_TYPE_EUKREA_CPUIMX51SD: 105 case MACH_TYPE_EUKREA_CPUIMX51SD:
106 case MACH_TYPE_MX51_3DS:
105 uart_base = MX51_UART1_BASE_ADDR; 107 uart_base = MX51_UART1_BASE_ADDR;
106 break; 108 break;
107 case MACH_TYPE_MX50_RDP: 109 case MACH_TYPE_MX50_RDP:
diff --git a/arch/arm/plat-pxa/mfp.c b/arch/arm/plat-pxa/mfp.c
index b77e018d36c1..a9aa5ad3f4eb 100644
--- a/arch/arm/plat-pxa/mfp.c
+++ b/arch/arm/plat-pxa/mfp.c
@@ -139,10 +139,11 @@ static const unsigned long mfpr_edge[] = {
139#define mfp_configured(p) ((p)->config != -1) 139#define mfp_configured(p) ((p)->config != -1)
140 140
141/* 141/*
142 * perform a read-back of any MFPR register to make sure the 142 * perform a read-back of any valid MFPR register to make sure the
143 * previous writings are finished 143 * previous writings are finished
144 */ 144 */
145#define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + 0) 145static unsigned long mfpr_off_readback;
146#define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + mfpr_off_readback)
146 147
147static inline void __mfp_config_run(struct mfp_pin *p) 148static inline void __mfp_config_run(struct mfp_pin *p)
148{ 149{
@@ -248,6 +249,9 @@ void __init mfp_init_addr(struct mfp_addr_map *map)
248 249
249 spin_lock_irqsave(&mfp_spin_lock, flags); 250 spin_lock_irqsave(&mfp_spin_lock, flags);
250 251
252 /* mfp offset for readback */
253 mfpr_off_readback = map[0].offset;
254
251 for (p = map; p->start != MFP_PIN_INVALID; p++) { 255 for (p = map; p->start != MFP_PIN_INVALID; p++) {
252 offset = p->offset; 256 offset = p->offset;
253 i = p->start; 257 i = p->start;
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index deb39951a22e..557f8c507f6d 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -37,6 +37,14 @@ config S5P_GPIO_INT
37 help 37 help
38 Common code for the GPIO interrupts (other than external interrupts.) 38 Common code for the GPIO interrupts (other than external interrupts.)
39 39
40comment "System MMU"
41
42config S5P_SYSTEM_MMU
43 bool "S5P SYSTEM MMU"
44 depends on ARCH_S5PV310
45 help
46 Say Y here if you want to enable System MMU
47
40config S5P_DEV_FIMC0 48config S5P_DEV_FIMC0
41 bool 49 bool
42 help 50 help
@@ -66,19 +74,3 @@ config S5P_DEV_CSIS1
66 bool 74 bool
67 help 75 help
68 Compile in platform device definitions for MIPI-CSIS channel 1 76 Compile in platform device definitions for MIPI-CSIS channel 1
69
70menuconfig S5P_SYSMMU
71 bool "SYSMMU support"
72 depends on ARCH_S5PV310
73 help
74 This is a System MMU driver for Samsung ARM based Soc.
75
76if S5P_SYSMMU
77
78config S5P_SYSMMU_DEBUG
79 bool "Enables debug messages"
80 depends on S5P_SYSMMU
81 help
82 This enables SYSMMU driver debug massages.
83
84endif
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 92efe1adcfd6..4bd5cf908977 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -19,6 +19,7 @@ obj-y += clock.o
19obj-y += irq.o 19obj-y += irq.o
20obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o 20obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o
21obj-$(CONFIG_S5P_GPIO_INT) += irq-gpioint.o 21obj-$(CONFIG_S5P_GPIO_INT) += irq-gpioint.o
22obj-$(CONFIG_S5P_SYSTEM_MMU) += sysmmu.o
22obj-$(CONFIG_PM) += pm.o 23obj-$(CONFIG_PM) += pm.o
23obj-$(CONFIG_PM) += irq-pm.o 24obj-$(CONFIG_PM) += irq-pm.o
24 25
@@ -30,4 +31,3 @@ obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o
30obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o 31obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o
31obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o 32obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o
32obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o 33obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o
33obj-$(CONFIG_S5P_SYSMMU) += sysmmu.o
diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-s5p/dev-uart.c
index 6a7342886171..afaf87fdb93e 100644
--- a/arch/arm/plat-s5p/dev-uart.c
+++ b/arch/arm/plat-s5p/dev-uart.c
@@ -28,7 +28,7 @@
28static struct resource s5p_uart0_resource[] = { 28static struct resource s5p_uart0_resource[] = {
29 [0] = { 29 [0] = {
30 .start = S5P_PA_UART0, 30 .start = S5P_PA_UART0,
31 .end = S5P_PA_UART0 + S5P_SZ_UART, 31 .end = S5P_PA_UART0 + S5P_SZ_UART - 1,
32 .flags = IORESOURCE_MEM, 32 .flags = IORESOURCE_MEM,
33 }, 33 },
34 [1] = { 34 [1] = {
@@ -51,7 +51,7 @@ static struct resource s5p_uart0_resource[] = {
51static struct resource s5p_uart1_resource[] = { 51static struct resource s5p_uart1_resource[] = {
52 [0] = { 52 [0] = {
53 .start = S5P_PA_UART1, 53 .start = S5P_PA_UART1,
54 .end = S5P_PA_UART1 + S5P_SZ_UART, 54 .end = S5P_PA_UART1 + S5P_SZ_UART - 1,
55 .flags = IORESOURCE_MEM, 55 .flags = IORESOURCE_MEM,
56 }, 56 },
57 [1] = { 57 [1] = {
@@ -74,7 +74,7 @@ static struct resource s5p_uart1_resource[] = {
74static struct resource s5p_uart2_resource[] = { 74static struct resource s5p_uart2_resource[] = {
75 [0] = { 75 [0] = {
76 .start = S5P_PA_UART2, 76 .start = S5P_PA_UART2,
77 .end = S5P_PA_UART2 + S5P_SZ_UART, 77 .end = S5P_PA_UART2 + S5P_SZ_UART - 1,
78 .flags = IORESOURCE_MEM, 78 .flags = IORESOURCE_MEM,
79 }, 79 },
80 [1] = { 80 [1] = {
@@ -98,7 +98,7 @@ static struct resource s5p_uart3_resource[] = {
98#if CONFIG_SERIAL_SAMSUNG_UARTS > 3 98#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
99 [0] = { 99 [0] = {
100 .start = S5P_PA_UART3, 100 .start = S5P_PA_UART3,
101 .end = S5P_PA_UART3 + S5P_SZ_UART, 101 .end = S5P_PA_UART3 + S5P_SZ_UART - 1,
102 .flags = IORESOURCE_MEM, 102 .flags = IORESOURCE_MEM,
103 }, 103 },
104 [1] = { 104 [1] = {
@@ -123,7 +123,7 @@ static struct resource s5p_uart4_resource[] = {
123#if CONFIG_SERIAL_SAMSUNG_UARTS > 4 123#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
124 [0] = { 124 [0] = {
125 .start = S5P_PA_UART4, 125 .start = S5P_PA_UART4,
126 .end = S5P_PA_UART4 + S5P_SZ_UART, 126 .end = S5P_PA_UART4 + S5P_SZ_UART - 1,
127 .flags = IORESOURCE_MEM, 127 .flags = IORESOURCE_MEM,
128 }, 128 },
129 [1] = { 129 [1] = {
@@ -148,7 +148,7 @@ static struct resource s5p_uart5_resource[] = {
148#if CONFIG_SERIAL_SAMSUNG_UARTS > 5 148#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
149 [0] = { 149 [0] = {
150 .start = S5P_PA_UART5, 150 .start = S5P_PA_UART5,
151 .end = S5P_PA_UART5 + S5P_SZ_UART, 151 .end = S5P_PA_UART5 + S5P_SZ_UART - 1,
152 .flags = IORESOURCE_MEM, 152 .flags = IORESOURCE_MEM,
153 }, 153 },
154 [1] = { 154 [1] = {
diff --git a/arch/arm/plat-s5p/include/plat/sysmmu.h b/arch/arm/plat-s5p/include/plat/sysmmu.h
deleted file mode 100644
index db298fc5438a..000000000000
--- a/arch/arm/plat-s5p/include/plat/sysmmu.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/* linux/arch/arm/plat-s5p/include/plat/sysmmu.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Samsung sysmmu driver
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_PLAT_S5P_SYSMMU_H
14#define __ASM_PLAT_S5P_SYSMMU_H __FILE__
15
16/* debug macro */
17#ifdef CONFIG_S5P_SYSMMU_DEBUG
18#define sysmmu_debug(fmt, arg...) printk(KERN_INFO "[%s] " fmt, __func__, ## arg)
19#else
20#define sysmmu_debug(fmt, arg...) do { } while (0)
21#endif
22
23#endif /* __ASM_PLAT_S5P_SYSMMU_H */
diff --git a/arch/arm/plat-s5p/sysmmu.c b/arch/arm/plat-s5p/sysmmu.c
index d804914dc2e2..ffe8a48bc3c1 100644
--- a/arch/arm/plat-s5p/sysmmu.c
+++ b/arch/arm/plat-s5p/sysmmu.c
@@ -16,8 +16,6 @@
16#include <mach/regs-sysmmu.h> 16#include <mach/regs-sysmmu.h>
17#include <mach/sysmmu.h> 17#include <mach/sysmmu.h>
18 18
19#include <plat/sysmmu.h>
20
21struct sysmmu_controller s5p_sysmmu_cntlrs[S5P_SYSMMU_TOTAL_IPNUM]; 19struct sysmmu_controller s5p_sysmmu_cntlrs[S5P_SYSMMU_TOTAL_IPNUM];
22 20
23void s5p_sysmmu_register(struct sysmmu_controller *sysmmuconp) 21void s5p_sysmmu_register(struct sysmmu_controller *sysmmuconp)
@@ -123,7 +121,7 @@ static int s5p_sysmmu_set_tablebase(sysmmu_ips ips)
123 : "=r" (pg) : : "cc"); \ 121 : "=r" (pg) : : "cc"); \
124 pg &= ~0x3fff; 122 pg &= ~0x3fff;
125 123
126 sysmmu_debug("CP15 TTBR0 : 0x%x\n", pg); 124 printk(KERN_INFO "%s: CP15 TTBR0 : 0x%x\n", __func__, pg);
127 125
128 /* Set sysmmu page table base address */ 126 /* Set sysmmu page table base address */
129 __raw_writel(pg, sysmmuconp->regs + S5P_PT_BASE_ADDR); 127 __raw_writel(pg, sysmmuconp->regs + S5P_PT_BASE_ADDR);
diff --git a/arch/arm/plat-samsung/dev-ts.c b/arch/arm/plat-samsung/dev-ts.c
index 236ef8427d7d..3e4bd8147bf4 100644
--- a/arch/arm/plat-samsung/dev-ts.c
+++ b/arch/arm/plat-samsung/dev-ts.c
@@ -58,4 +58,3 @@ void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
58 58
59 s3c_device_ts.dev.platform_data = npd; 59 s3c_device_ts.dev.platform_data = npd;
60} 60}
61EXPORT_SYMBOL(s3c24xx_ts_set_platdata);
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index d9025e377675..30518cc9a67c 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -17,6 +17,8 @@
17 17
18#include <linux/irq.h> 18#include <linux/irq.h>
19 19
20struct sys_device;
21
20#ifdef CONFIG_PM 22#ifdef CONFIG_PM
21 23
22extern __init int s3c_pm_init(void); 24extern __init int s3c_pm_init(void);
diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h
index 99ba6789cc97..6dd455bafdfd 100644
--- a/arch/arm/plat-spear/include/plat/uncompress.h
+++ b/arch/arm/plat-spear/include/plat/uncompress.h
@@ -24,10 +24,10 @@ static inline void putc(int c)
24{ 24{
25 void __iomem *base = (void __iomem *)SPEAR_DBG_UART_BASE; 25 void __iomem *base = (void __iomem *)SPEAR_DBG_UART_BASE;
26 26
27 while (readl(base + UART01x_FR) & UART01x_FR_TXFF) 27 while (readl_relaxed(base + UART01x_FR) & UART01x_FR_TXFF)
28 barrier(); 28 barrier();
29 29
30 writel(c, base + UART01x_DR); 30 writel_relaxed(c, base + UART01x_DR);
31} 31}
32 32
33static inline void flush(void) 33static inline void flush(void)
diff --git a/arch/arm/plat-spear/include/plat/vmalloc.h b/arch/arm/plat-spear/include/plat/vmalloc.h
index 09e9372aea21..8c8b24d07046 100644
--- a/arch/arm/plat-spear/include/plat/vmalloc.h
+++ b/arch/arm/plat-spear/include/plat/vmalloc.h
@@ -14,6 +14,6 @@
14#ifndef __PLAT_VMALLOC_H 14#ifndef __PLAT_VMALLOC_H
15#define __PLAT_VMALLOC_H 15#define __PLAT_VMALLOC_H
16 16
17#define VMALLOC_END 0xF0000000 17#define VMALLOC_END 0xF0000000UL
18 18
19#endif /* __PLAT_VMALLOC_H */ 19#endif /* __PLAT_VMALLOC_H */
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 2fea897ebeb1..9d6feaabbe7d 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
12# 12#
13# http://www.arm.linux.org.uk/developer/machines/?action=new 13# http://www.arm.linux.org.uk/developer/machines/?action=new
14# 14#
15# Last update: Sun Dec 12 23:24:27 2010 15# Last update: Mon Feb 7 08:59:27 2011
16# 16#
17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number 17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
18# 18#
@@ -2240,7 +2240,7 @@ arm_ultimator2 MACH_ARM_ULTIMATOR2 ARM_ULTIMATOR2 2250
2240vs_v210 MACH_VS_V210 VS_V210 2252 2240vs_v210 MACH_VS_V210 VS_V210 2252
2241vs_v212 MACH_VS_V212 VS_V212 2253 2241vs_v212 MACH_VS_V212 VS_V212 2253
2242hmt MACH_HMT HMT 2254 2242hmt MACH_HMT HMT 2254
2243suen3 MACH_SUEN3 SUEN3 2255 2243km_kirkwood MACH_KM_KIRKWOOD KM_KIRKWOOD 2255
2244vesper MACH_VESPER VESPER 2256 2244vesper MACH_VESPER VESPER 2256
2245str9 MACH_STR9 STR9 2257 2245str9 MACH_STR9 STR9 2257
2246omap3_wl_ff MACH_OMAP3_WL_FF OMAP3_WL_FF 2258 2246omap3_wl_ff MACH_OMAP3_WL_FF OMAP3_WL_FF 2258
@@ -2987,7 +2987,7 @@ pxwnas_500_1000 MACH_PXWNAS_500_1000 PXWNAS_500_1000 3001
2987ea20 MACH_EA20 EA20 3002 2987ea20 MACH_EA20 EA20 3002
2988awm2 MACH_AWM2 AWM2 3003 2988awm2 MACH_AWM2 AWM2 3003
2989ti8148evm MACH_TI8148EVM TI8148EVM 3004 2989ti8148evm MACH_TI8148EVM TI8148EVM 3004
2990tegra_seaboard MACH_TEGRA_SEABOARD TEGRA_SEABOARD 3005 2990seaboard MACH_SEABOARD SEABOARD 3005
2991linkstation_chlv2 MACH_LINKSTATION_CHLV2 LINKSTATION_CHLV2 3006 2991linkstation_chlv2 MACH_LINKSTATION_CHLV2 LINKSTATION_CHLV2 3006
2992tera_pro2_rack MACH_TERA_PRO2_RACK TERA_PRO2_RACK 3007 2992tera_pro2_rack MACH_TERA_PRO2_RACK TERA_PRO2_RACK 3007
2993rubys MACH_RUBYS RUBYS 3008 2993rubys MACH_RUBYS RUBYS 3008
@@ -3190,7 +3190,7 @@ synergy MACH_SYNERGY SYNERGY 3205
3190ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206 3190ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206
3191wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207 3191wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207
3192punica MACH_PUNICA PUNICA 3208 3192punica MACH_PUNICA PUNICA 3208
3193sbc_nt250 MACH_SBC_NT250 SBC_NT250 3209 3193trimslice MACH_TRIMSLICE TRIMSLICE 3209
3194mx27_wmultra MACH_MX27_WMULTRA MX27_WMULTRA 3210 3194mx27_wmultra MACH_MX27_WMULTRA MX27_WMULTRA 3210
3195mackerel MACH_MACKEREL MACKEREL 3211 3195mackerel MACH_MACKEREL MACKEREL 3211
3196fa9x27 MACH_FA9X27 FA9X27 3213 3196fa9x27 MACH_FA9X27 FA9X27 3213
@@ -3219,3 +3219,100 @@ pivicc MACH_PIVICC PIVICC 3235
3219pcm048 MACH_PCM048 PCM048 3236 3219pcm048 MACH_PCM048 PCM048 3236
3220dds MACH_DDS DDS 3237 3220dds MACH_DDS DDS 3237
3221chalten_xa1 MACH_CHALTEN_XA1 CHALTEN_XA1 3238 3221chalten_xa1 MACH_CHALTEN_XA1 CHALTEN_XA1 3238
3222ts48xx MACH_TS48XX TS48XX 3239
3223tonga2_tfttimer MACH_TONGA2_TFTTIMER TONGA2_TFTTIMER 3240
3224whistler MACH_WHISTLER WHISTLER 3241
3225asl_phoenix MACH_ASL_PHOENIX ASL_PHOENIX 3242
3226at91sam9263otlite MACH_AT91SAM9263OTLITE AT91SAM9263OTLITE 3243
3227ddplug MACH_DDPLUG DDPLUG 3244
3228d2plug MACH_D2PLUG D2PLUG 3245
3229kzm9d MACH_KZM9D KZM9D 3246
3230verdi_lte MACH_VERDI_LTE VERDI_LTE 3247
3231nanozoom MACH_NANOZOOM NANOZOOM 3248
3232dm3730_som_lv MACH_DM3730_SOM_LV DM3730_SOM_LV 3249
3233dm3730_torpedo MACH_DM3730_TORPEDO DM3730_TORPEDO 3250
3234anchovy MACH_ANCHOVY ANCHOVY 3251
3235re2rev20 MACH_RE2REV20 RE2REV20 3253
3236re2rev21 MACH_RE2REV21 RE2REV21 3254
3237cns21xx MACH_CNS21XX CNS21XX 3255
3238rider MACH_RIDER RIDER 3257
3239nsk330 MACH_NSK330 NSK330 3258
3240cns2133evb MACH_CNS2133EVB CNS2133EVB 3259
3241z3_816x_mod MACH_Z3_816X_MOD Z3_816X_MOD 3260
3242z3_814x_mod MACH_Z3_814X_MOD Z3_814X_MOD 3261
3243beect MACH_BEECT BEECT 3262
3244dma_thunderbug MACH_DMA_THUNDERBUG DMA_THUNDERBUG 3263
3245omn_at91sam9g20 MACH_OMN_AT91SAM9G20 OMN_AT91SAM9G20 3264
3246mx25_e2s_uc MACH_MX25_E2S_UC MX25_E2S_UC 3265
3247mione MACH_MIONE MIONE 3266
3248top9000_tcu MACH_TOP9000_TCU TOP9000_TCU 3267
3249top9000_bsl MACH_TOP9000_BSL TOP9000_BSL 3268
3250kingdom MACH_KINGDOM KINGDOM 3269
3251armadillo460 MACH_ARMADILLO460 ARMADILLO460 3270
3252lq2 MACH_LQ2 LQ2 3271
3253sweda_tms2 MACH_SWEDA_TMS2 SWEDA_TMS2 3272
3254mx53_loco MACH_MX53_LOCO MX53_LOCO 3273
3255acer_a8 MACH_ACER_A8 ACER_A8 3275
3256acer_gauguin MACH_ACER_GAUGUIN ACER_GAUGUIN 3276
3257guppy MACH_GUPPY GUPPY 3277
3258mx61_ard MACH_MX61_ARD MX61_ARD 3278
3259tx53 MACH_TX53 TX53 3279
3260omapl138_case_a3 MACH_OMAPL138_CASE_A3 OMAPL138_CASE_A3 3280
3261uemd MACH_UEMD UEMD 3281
3262ccwmx51mut MACH_CCWMX51MUT CCWMX51MUT 3282
3263rockhopper MACH_ROCKHOPPER ROCKHOPPER 3283
3264nookcolor MACH_NOOKCOLOR NOOKCOLOR 3284
3265hkdkc100 MACH_HKDKC100 HKDKC100 3285
3266ts42xx MACH_TS42XX TS42XX 3286
3267aebl MACH_AEBL AEBL 3287
3268wario MACH_WARIO WARIO 3288
3269gfs_spm MACH_GFS_SPM GFS_SPM 3289
3270cm_t3730 MACH_CM_T3730 CM_T3730 3290
3271isc3 MACH_ISC3 ISC3 3291
3272rascal MACH_RASCAL RASCAL 3292
3273hrefv60 MACH_HREFV60 HREFV60 3293
3274tpt_2_0 MACH_TPT_2_0 TPT_2_0 3294
3275pyramid_td MACH_PYRAMID_TD PYRAMID_TD 3295
3276splendor MACH_SPLENDOR SPLENDOR 3296
3277guf_planet MACH_GUF_PLANET GUF_PLANET 3297
3278msm8x60_qt MACH_MSM8X60_QT MSM8X60_QT 3298
3279htc_hd_mini MACH_HTC_HD_MINI HTC_HD_MINI 3299
3280athene MACH_ATHENE ATHENE 3300
3281deep_r_ek_1 MACH_DEEP_R_EK_1 DEEP_R_EK_1 3301
3282vivow_ct MACH_VIVOW_CT VIVOW_CT 3302
3283nery_1000 MACH_NERY_1000 NERY_1000 3303
3284rfl109145_ssrv MACH_RFL109145_SSRV RFL109145_SSRV 3304
3285nmh MACH_NMH NMH 3305
3286wn802t MACH_WN802T WN802T 3306
3287dragonet MACH_DRAGONET DRAGONET 3307
3288geneva_b MACH_GENEVA_B GENEVA_B 3308
3289at91sam9263desk16l MACH_AT91SAM9263DESK16L AT91SAM9263DESK16L 3309
3290bcmhana_sv MACH_BCMHANA_SV BCMHANA_SV 3310
3291bcmhana_tablet MACH_BCMHANA_TABLET BCMHANA_TABLET 3311
3292koi MACH_KOI KOI 3312
3293ts4800 MACH_TS4800 TS4800 3313
3294tqma9263 MACH_TQMA9263 TQMA9263 3314
3295holiday MACH_HOLIDAY HOLIDAY 3315
3296dma_6410 MACH_DMA6410 DMA6410 3316
3297pcats_overlay MACH_PCATS_OVERLAY PCATS_OVERLAY 3317
3298hwgw6410 MACH_HWGW6410 HWGW6410 3318
3299shenzhou MACH_SHENZHOU SHENZHOU 3319
3300cwme9210 MACH_CWME9210 CWME9210 3320
3301cwme9210js MACH_CWME9210JS CWME9210JS 3321
3302pgs_v1 MACH_PGS_SITARA PGS_SITARA 3322
3303colibri_tegra2 MACH_COLIBRI_TEGRA2 COLIBRI_TEGRA2 3323
3304w21 MACH_W21 W21 3324
3305polysat1 MACH_POLYSAT1 POLYSAT1 3325
3306dataway MACH_DATAWAY DATAWAY 3326
3307cobral138 MACH_COBRAL138 COBRAL138 3327
3308roverpcs8 MACH_ROVERPCS8 ROVERPCS8 3328
3309marvelc MACH_MARVELC MARVELC 3329
3310navefihid MACH_NAVEFIHID NAVEFIHID 3330
3311dm365_cv100 MACH_DM365_CV100 DM365_CV100 3331
3312able MACH_ABLE ABLE 3332
3313legacy MACH_LEGACY LEGACY 3333
3314icong MACH_ICONG ICONG 3334
3315rover_g8 MACH_ROVER_G8 ROVER_G8 3335
3316t5388p MACH_T5388P T5388P 3336
3317dingo MACH_DINGO DINGO 3337
3318goflexhome MACH_GOFLEXHOME GOFLEXHOME 3338
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 23:22:25 -0500