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authorLinus Walleij <linus.walleij@stericsson.com>2009-04-23 05:22:13 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-04-28 17:44:15 -0400
commitbb3cee2b35d2b9edab71997bd06040ff37483e08 (patch)
tree59fbdd7076981906e705e63d09b3d42ff8873242 /arch/arm
parentcd27e485410aa7e7464b0126d968fe8c2a5c045b (diff)
[ARM] 5473/1: U300 core machine support
This adds core support for the ST-Ericsson U300 series platforms: U300, U330, U335 and U365. Supports memory mappings, interrupt controller, system timer (clocksource and clockevents), and binds to the existing drivers for the PrimeCells used in this design: PL190 (VIC), PL180 (MMC/SD host) and PL011 (UART). This is intented to serve as starting point for our mainling work, more patches to follow. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-u300/Kconfig105
-rw-r--r--arch/arm/mach-u300/Makefile11
-rw-r--r--arch/arm/mach-u300/core.c649
-rw-r--r--arch/arm/mach-u300/include/mach/debug-macro.S22
-rw-r--r--arch/arm/mach-u300/include/mach/entry-macro.S40
-rw-r--r--arch/arm/mach-u300/include/mach/memory.h42
-rw-r--r--arch/arm/mach-u300/include/mach/platform.h19
-rw-r--r--arch/arm/mach-u300/include/mach/system.h42
-rw-r--r--arch/arm/mach-u300/include/mach/timex.h17
-rw-r--r--arch/arm/mach-u300/include/mach/uncompress.h46
-rw-r--r--arch/arm/mach-u300/include/mach/vmalloc.h12
-rw-r--r--arch/arm/mach-u300/mmc.c216
-rw-r--r--arch/arm/mach-u300/mmc.h18
-rw-r--r--arch/arm/mach-u300/timer.c422
-rw-r--r--arch/arm/mach-u300/u300.c55
15 files changed, 1716 insertions, 0 deletions
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
new file mode 100644
index 000000000000..337b9aabce49
--- /dev/null
+++ b/arch/arm/mach-u300/Kconfig
@@ -0,0 +1,105 @@
1if ARCH_U300
2
3menu "ST-Ericsson AB U300/U330/U335/U365 Platform"
4
5comment "ST-Ericsson Mobile Platform Products"
6
7config MACH_U300
8 bool "U300"
9
10comment "ST-Ericsson U300/U330/U335/U365 Feature Selections"
11
12choice
13 prompt "U300/U330/U335/U365 system type"
14 default MACH_U300_BS2X
15 ---help---
16 You need to select the target system, i.e. the
17 U300/U330/U335/U365 board that you want to compile your kernel
18 for.
19
20config MACH_U300_BS2X
21 bool "S26/S26/B25/B26 Test Products"
22 depends on MACH_U300
23 help
24 Select this if you're developing on the
25 S26/S25 test products. (Also works on
26 B26/B25 big boards.)
27
28config MACH_U300_BS330
29 bool "S330/B330 Test Products"
30 depends on MACH_U300
31 help
32 Select this if you're developing on the
33 S330/B330 test products.
34
35config MACH_U300_BS335
36 bool "S335/B335 Test Products"
37 depends on MACH_U300
38 help
39 Select this if you're developing on the
40 S335/B335 test products.
41
42config MACH_U300_BS365
43 bool "S365/B365 Test Products"
44 depends on MACH_U300
45 help
46 Select this if you're developing on the
47 S365/B365 test products.
48
49endchoice
50
51choice
52 prompt "Memory configuration"
53 default MACH_U300_SINGLE_RAM
54 ---help---
55 You have to config the kernel according to the physical memory
56 configuration.
57
58config MACH_U300_SINGLE_RAM
59 bool "Single RAM"
60 help
61 Select this if you want support for Single RAM phones.
62
63config MACH_U300_DUAL_RAM
64 bool "Dual RAM"
65 help
66 Select this if you want support for Dual RAM phones.
67 This is two RAM memorys on different EMIFs.
68endchoice
69
70config U300_DEBUG
71 bool "Debug support for U300"
72 depends on PM
73 help
74 Debug support for U300 in sysfs, procfs etc.
75
76config MACH_U300_SEMI_IS_SHARED
77 bool "The SEMI is used by both the access and application side"
78 depends on MACH_U300
79 help
80 This makes it possible to use the SEMI (Shared External
81 Memory Interface) from both from access and application
82 side.
83
84comment "All the settings below must match the bootloader's settings"
85
86config MACH_U300_ACCESS_MEM_SIZE
87 int "Access CPU memory allocation"
88 range 7 25
89 depends on MACH_U300_SINGLE_RAM
90 default 13
91 help
92 How much memory in MiB that the Access side CPU has allocated
93
94config MACH_U300_2MB_ALIGNMENT_FIX
95 bool "2MiB alignment fix"
96 depends on MACH_U300_SINGLE_RAM
97 default y
98 help
99 If yes and the Access side CPU has allocated an odd size in
100 MiB, this fix gives you one MiB extra that would otherwise be
101 lost due to Linux 2 MiB alignment policy.
102
103endmenu
104
105endif
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
new file mode 100644
index 000000000000..24950e0df4b4
--- /dev/null
+++ b/arch/arm/mach-u300/Makefile
@@ -0,0 +1,11 @@
1#
2# Makefile for the linux kernel, U300 machine.
3#
4
5obj-y := core.o clock.o timer.o gpio.o padmux.o
6obj-m :=
7obj-n :=
8obj- :=
9
10obj-$(CONFIG_ARCH_U300) += u300.o
11obj-$(CONFIG_MMC) += mmc.o
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
new file mode 100644
index 000000000000..1f2ed21a0ab1
--- /dev/null
+++ b/arch/arm/mach-u300/core.c
@@ -0,0 +1,649 @@
1/*
2 *
3 * arch/arm/mach-u300/core.c
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Core platform support, IRQ handling and device definitions.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/interrupt.h>
15#include <linux/bitops.h>
16#include <linux/device.h>
17#include <linux/mm.h>
18#include <linux/termios.h>
19#include <linux/amba/bus.h>
20#include <linux/platform_device.h>
21#include <linux/gpio.h>
22
23#include <asm/types.h>
24#include <asm/setup.h>
25#include <asm/memory.h>
26#include <asm/hardware/vic.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <mach/hardware.h>
31#include <mach/syscon.h>
32
33#include "clock.h"
34#include "mmc.h"
35
36/*
37 * Static I/O mappings that are needed for booting the U300 platforms. The
38 * only things we need are the areas where we find the timer, syscon and
39 * intcon, since the remaining device drivers will map their own memory
40 * physical to virtual as the need arise.
41 */
42static struct map_desc u300_io_desc[] __initdata = {
43 {
44 .virtual = U300_SLOW_PER_VIRT_BASE,
45 .pfn = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
46 .length = SZ_64K,
47 .type = MT_DEVICE,
48 },
49 {
50 .virtual = U300_AHB_PER_VIRT_BASE,
51 .pfn = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
52 .length = SZ_32K,
53 .type = MT_DEVICE,
54 },
55 {
56 .virtual = U300_FAST_PER_VIRT_BASE,
57 .pfn = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
58 .length = SZ_32K,
59 .type = MT_DEVICE,
60 },
61 {
62 .virtual = 0xffff2000, /* TCM memory */
63 .pfn = __phys_to_pfn(0xffff2000),
64 .length = SZ_16K,
65 .type = MT_DEVICE,
66 },
67
68 /*
69 * This overlaps with the IRQ vectors etc at 0xffff0000, so these
70 * may have to be moved to 0x00000000 in order to use the ROM.
71 */
72 /*
73 {
74 .virtual = U300_BOOTROM_VIRT_BASE,
75 .pfn = __phys_to_pfn(U300_BOOTROM_PHYS_BASE),
76 .length = SZ_64K,
77 .type = MT_ROM,
78 },
79 */
80};
81
82void __init u300_map_io(void)
83{
84 iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
85}
86
87/*
88 * Declaration of devices found on the U300 board and
89 * their respective memory locations.
90 */
91static struct amba_device uart0_device = {
92 .dev = {
93 .init_name = "uart0", /* Slow device at 0x3000 offset */
94 .platform_data = NULL,
95 },
96 .res = {
97 .start = U300_UART0_BASE,
98 .end = U300_UART0_BASE + SZ_4K - 1,
99 .flags = IORESOURCE_MEM,
100 },
101 .irq = { IRQ_U300_UART0, NO_IRQ },
102};
103
104/* The U335 have an additional UART1 on the APP CPU */
105#ifdef CONFIG_MACH_U300_BS335
106static struct amba_device uart1_device = {
107 .dev = {
108 .init_name = "uart1", /* Fast device at 0x7000 offset */
109 .platform_data = NULL,
110 },
111 .res = {
112 .start = U300_UART1_BASE,
113 .end = U300_UART1_BASE + SZ_4K - 1,
114 .flags = IORESOURCE_MEM,
115 },
116 .irq = { IRQ_U300_UART1, NO_IRQ },
117};
118#endif
119
120static struct amba_device pl172_device = {
121 .dev = {
122 .init_name = "pl172", /* AHB device at 0x4000 offset */
123 .platform_data = NULL,
124 },
125 .res = {
126 .start = U300_EMIF_CFG_BASE,
127 .end = U300_EMIF_CFG_BASE + SZ_4K - 1,
128 .flags = IORESOURCE_MEM,
129 },
130};
131
132
133/*
134 * Everything within this next ifdef deals with external devices connected to
135 * the APP SPI bus.
136 */
137static struct amba_device pl022_device = {
138 .dev = {
139 .coherent_dma_mask = ~0,
140 .init_name = "pl022", /* Fast device at 0x6000 offset */
141 },
142 .res = {
143 .start = U300_SPI_BASE,
144 .end = U300_SPI_BASE + SZ_4K - 1,
145 .flags = IORESOURCE_MEM,
146 },
147 .irq = {IRQ_U300_SPI, NO_IRQ },
148 /*
149 * This device has a DMA channel but the Linux driver does not use
150 * it currently.
151 */
152};
153
154static struct amba_device mmcsd_device = {
155 .dev = {
156 .init_name = "mmci", /* Fast device at 0x1000 offset */
157 .platform_data = NULL, /* Added later */
158 },
159 .res = {
160 .start = U300_MMCSD_BASE,
161 .end = U300_MMCSD_BASE + SZ_4K - 1,
162 .flags = IORESOURCE_MEM,
163 },
164 .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
165 /*
166 * This device has a DMA channel but the Linux driver does not use
167 * it currently.
168 */
169};
170
171/*
172 * The order of device declaration may be important, since some devices
173 * have dependencies on other devices being initialized first.
174 */
175static struct amba_device *amba_devs[] __initdata = {
176 &uart0_device,
177#ifdef CONFIG_MACH_U300_BS335
178 &uart1_device,
179#endif
180 &pl022_device,
181 &pl172_device,
182 &mmcsd_device,
183};
184
185/* Here follows a list of all hw resources that the platform devices
186 * allocate. Note, clock dependencies are not included
187 */
188
189static struct resource gpio_resources[] = {
190 {
191 .start = U300_GPIO_BASE,
192 .end = (U300_GPIO_BASE + SZ_4K - 1),
193 .flags = IORESOURCE_MEM,
194 },
195 {
196 .name = "gpio0",
197 .start = IRQ_U300_GPIO_PORT0,
198 .end = IRQ_U300_GPIO_PORT0,
199 .flags = IORESOURCE_IRQ,
200 },
201 {
202 .name = "gpio1",
203 .start = IRQ_U300_GPIO_PORT1,
204 .end = IRQ_U300_GPIO_PORT1,
205 .flags = IORESOURCE_IRQ,
206 },
207 {
208 .name = "gpio2",
209 .start = IRQ_U300_GPIO_PORT2,
210 .end = IRQ_U300_GPIO_PORT2,
211 .flags = IORESOURCE_IRQ,
212 },
213#ifdef U300_COH901571_3
214 {
215 .name = "gpio3",
216 .start = IRQ_U300_GPIO_PORT3,
217 .end = IRQ_U300_GPIO_PORT3,
218 .flags = IORESOURCE_IRQ,
219 },
220 {
221 .name = "gpio4",
222 .start = IRQ_U300_GPIO_PORT4,
223 .end = IRQ_U300_GPIO_PORT4,
224 .flags = IORESOURCE_IRQ,
225 },
226#ifdef CONFIG_MACH_U300_BS335
227 {
228 .name = "gpio5",
229 .start = IRQ_U300_GPIO_PORT5,
230 .end = IRQ_U300_GPIO_PORT5,
231 .flags = IORESOURCE_IRQ,
232 },
233 {
234 .name = "gpio6",
235 .start = IRQ_U300_GPIO_PORT6,
236 .end = IRQ_U300_GPIO_PORT6,
237 .flags = IORESOURCE_IRQ,
238 },
239#endif /* CONFIG_MACH_U300_BS335 */
240#endif /* U300_COH901571_3 */
241};
242
243static struct resource keypad_resources[] = {
244 {
245 .start = U300_KEYPAD_BASE,
246 .end = U300_KEYPAD_BASE + SZ_4K - 1,
247 .flags = IORESOURCE_MEM,
248 },
249 {
250 .name = "coh901461-press",
251 .start = IRQ_U300_KEYPAD_KEYBF,
252 .end = IRQ_U300_KEYPAD_KEYBF,
253 .flags = IORESOURCE_IRQ,
254 },
255 {
256 .name = "coh901461-release",
257 .start = IRQ_U300_KEYPAD_KEYBR,
258 .end = IRQ_U300_KEYPAD_KEYBR,
259 .flags = IORESOURCE_IRQ,
260 },
261};
262
263static struct resource rtc_resources[] = {
264 {
265 .start = U300_RTC_BASE,
266 .end = U300_RTC_BASE + SZ_4K - 1,
267 .flags = IORESOURCE_MEM,
268 },
269 {
270 .start = IRQ_U300_RTC,
271 .end = IRQ_U300_RTC,
272 .flags = IORESOURCE_IRQ,
273 },
274};
275
276/*
277 * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
278 * but these are not yet used by the driver.
279 */
280static struct resource fsmc_resources[] = {
281 {
282 .start = U300_NAND_IF_PHYS_BASE,
283 .end = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
284 .flags = IORESOURCE_MEM,
285 },
286};
287
288static struct resource i2c0_resources[] = {
289 {
290 .start = U300_I2C0_BASE,
291 .end = U300_I2C0_BASE + SZ_4K - 1,
292 .flags = IORESOURCE_MEM,
293 },
294 {
295 .start = IRQ_U300_I2C0,
296 .end = IRQ_U300_I2C0,
297 .flags = IORESOURCE_IRQ,
298 },
299};
300
301static struct resource i2c1_resources[] = {
302 {
303 .start = U300_I2C1_BASE,
304 .end = U300_I2C1_BASE + SZ_4K - 1,
305 .flags = IORESOURCE_MEM,
306 },
307 {
308 .start = IRQ_U300_I2C1,
309 .end = IRQ_U300_I2C1,
310 .flags = IORESOURCE_IRQ,
311 },
312
313};
314
315static struct resource wdog_resources[] = {
316 {
317 .start = U300_WDOG_BASE,
318 .end = U300_WDOG_BASE + SZ_4K - 1,
319 .flags = IORESOURCE_MEM,
320 },
321 {
322 .start = IRQ_U300_WDOG,
323 .end = IRQ_U300_WDOG,
324 .flags = IORESOURCE_IRQ,
325 }
326};
327
328/* TODO: These should be protected by suitable #ifdef's */
329static struct resource ave_resources[] = {
330 {
331 .name = "AVE3e I/O Area",
332 .start = U300_VIDEOENC_BASE,
333 .end = U300_VIDEOENC_BASE + SZ_512K - 1,
334 .flags = IORESOURCE_MEM,
335 },
336 {
337 .name = "AVE3e IRQ0",
338 .start = IRQ_U300_VIDEO_ENC_0,
339 .end = IRQ_U300_VIDEO_ENC_0,
340 .flags = IORESOURCE_IRQ,
341 },
342 {
343 .name = "AVE3e IRQ1",
344 .start = IRQ_U300_VIDEO_ENC_1,
345 .end = IRQ_U300_VIDEO_ENC_1,
346 .flags = IORESOURCE_IRQ,
347 },
348 {
349 .name = "AVE3e Physmem Area",
350 .start = 0, /* 0 will be remapped to reserved memory */
351 .end = SZ_1M - 1,
352 .flags = IORESOURCE_MEM,
353 },
354 /*
355 * The AVE3e requires two regions of 256MB that it considers
356 * "invisible". The hardware will not be able to access these
357 * adresses, so they should never point to system RAM.
358 */
359 {
360 .name = "AVE3e Reserved 0",
361 .start = 0xd0000000,
362 .end = 0xd0000000 + SZ_256M - 1,
363 .flags = IORESOURCE_MEM,
364 },
365 {
366 .name = "AVE3e Reserved 1",
367 .start = 0xe0000000,
368 .end = 0xe0000000 + SZ_256M - 1,
369 .flags = IORESOURCE_MEM,
370 },
371};
372
373static struct platform_device wdog_device = {
374 .name = "wdog",
375 .id = -1,
376 .num_resources = ARRAY_SIZE(wdog_resources),
377 .resource = wdog_resources,
378};
379
380static struct platform_device i2c0_device = {
381 .name = "stddci2c",
382 .id = 0,
383 .num_resources = ARRAY_SIZE(i2c0_resources),
384 .resource = i2c0_resources,
385};
386
387static struct platform_device i2c1_device = {
388 .name = "stddci2c",
389 .id = 1,
390 .num_resources = ARRAY_SIZE(i2c1_resources),
391 .resource = i2c1_resources,
392};
393
394static struct platform_device gpio_device = {
395 .name = "u300-gpio",
396 .id = -1,
397 .num_resources = ARRAY_SIZE(gpio_resources),
398 .resource = gpio_resources,
399};
400
401static struct platform_device keypad_device = {
402 .name = "keypad",
403 .id = -1,
404 .num_resources = ARRAY_SIZE(keypad_resources),
405 .resource = keypad_resources,
406};
407
408static struct platform_device rtc_device = {
409 .name = "rtc0",
410 .id = -1,
411 .num_resources = ARRAY_SIZE(rtc_resources),
412 .resource = rtc_resources,
413};
414
415static struct platform_device fsmc_device = {
416 .name = "nandif",
417 .id = -1,
418 .num_resources = ARRAY_SIZE(fsmc_resources),
419 .resource = fsmc_resources,
420};
421
422static struct platform_device ave_device = {
423 .name = "video_enc",
424 .id = -1,
425 .num_resources = ARRAY_SIZE(ave_resources),
426 .resource = ave_resources,
427};
428
429/*
430 * Notice that AMBA devices are initialized before platform devices.
431 *
432 */
433static struct platform_device *platform_devs[] __initdata = {
434 &i2c0_device,
435 &i2c1_device,
436 &keypad_device,
437 &rtc_device,
438 &gpio_device,
439 &fsmc_device,
440 &wdog_device,
441 &ave_device
442};
443
444
445/*
446 * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
447 * together so some interrupts are connected to the first one and some
448 * to the second one.
449 */
450void __init u300_init_irq(void)
451{
452 u32 mask[2] = {0, 0};
453 int i;
454
455 for (i = 0; i < NR_IRQS; i++)
456 set_bit(i, (unsigned long *) &mask[0]);
457 u300_enable_intcon_clock();
458 vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0]);
459 vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1]);
460}
461
462
463/*
464 * U300 platforms peripheral handling
465 */
466struct db_chip {
467 u16 chipid;
468 const char *name;
469};
470
471/*
472 * This is a list of the Digital Baseband chips used in the U300 platform.
473 */
474static struct db_chip db_chips[] __initdata = {
475 {
476 .chipid = 0xb800,
477 .name = "DB3000",
478 },
479 {
480 .chipid = 0xc000,
481 .name = "DB3100",
482 },
483 {
484 .chipid = 0xc800,
485 .name = "DB3150",
486 },
487 {
488 .chipid = 0xd800,
489 .name = "DB3200",
490 },
491 {
492 .chipid = 0xe000,
493 .name = "DB3250",
494 },
495 {
496 .chipid = 0xe800,
497 .name = "DB3210",
498 },
499 {
500 .chipid = 0xf000,
501 .name = "DB3350 P1x",
502 },
503 {
504 .chipid = 0xf100,
505 .name = "DB3350 P2x",
506 },
507 {
508 .chipid = 0x0000, /* List terminator */
509 .name = NULL,
510 }
511};
512
513static void u300_init_check_chip(void)
514{
515
516 u16 val;
517 struct db_chip *chip;
518 const char *chipname;
519 const char unknown[] = "UNKNOWN";
520
521 /* Read out and print chip ID */
522 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
523 /* This is in funky bigendian order... */
524 val = (val & 0xFFU) << 8 | (val >> 8);
525 chip = db_chips;
526 chipname = unknown;
527
528 for ( ; chip->chipid; chip++) {
529 if (chip->chipid == (val & 0xFF00U)) {
530 chipname = chip->name;
531 break;
532 }
533 }
534 printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
535 "(chip ID 0x%04x)\n", chipname, val);
536
537#ifdef CONFIG_MACH_U300_BS26
538 if ((val & 0xFF00U) != 0xc800) {
539 printk(KERN_ERR "Platform configured for BS25/BS26 " \
540 "with DB3150 but %s detected, expect problems!",
541 chipname);
542 }
543#endif
544#ifdef CONFIG_MACH_U300_BS330
545 if ((val & 0xFF00U) != 0xd800) {
546 printk(KERN_ERR "Platform configured for BS330 " \
547 "with DB3200 but %s detected, expect problems!",
548 chipname);
549 }
550#endif
551#ifdef CONFIG_MACH_U300_BS335
552 if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
553 printk(KERN_ERR "Platform configured for BS365 " \
554 " with DB3350 but %s detected, expect problems!",
555 chipname);
556 }
557#endif
558#ifdef CONFIG_MACH_U300_BS365
559 if ((val & 0xFF00U) != 0xe800) {
560 printk(KERN_ERR "Platform configured for BS365 " \
561 "with DB3210 but %s detected, expect problems!",
562 chipname);
563 }
564#endif
565
566
567}
568
569/*
570 * Some devices and their resources require reserved physical memory from
571 * the end of the available RAM. This function traverses the list of devices
572 * and assigns actual adresses to these.
573 */
574static void __init u300_assign_physmem(void)
575{
576 unsigned long curr_start = __pa(high_memory);
577 int i, j;
578
579 for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
580 for (j = 0; j < platform_devs[i]->num_resources; j++) {
581 struct resource *const res =
582 &platform_devs[i]->resource[j];
583
584 if (IORESOURCE_MEM == res->flags &&
585 0 == res->start) {
586 res->start = curr_start;
587 res->end += curr_start;
588 curr_start += (res->end - res->start + 1);
589
590 printk(KERN_INFO "core.c: Mapping RAM " \
591 "%#x-%#x to device %s:%s\n",
592 res->start, res->end,
593 platform_devs[i]->name, res->name);
594 }
595 }
596 }
597}
598
599void __init u300_init_devices(void)
600{
601 int i;
602 u16 val;
603
604 /* Check what platform we run and print some status information */
605 u300_init_check_chip();
606
607 /* Set system to run at PLL208, max performance, a known state. */
608 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
609 val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
610 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
611 /* Wait for the PLL208 to lock if not locked in yet */
612 while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
613 U300_SYSCON_CSR_PLL208_LOCK_IND));
614
615 /* Register the AMBA devices in the AMBA bus abstraction layer */
616 u300_clock_primecells();
617 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
618 struct amba_device *d = amba_devs[i];
619 amba_device_register(d, &iomem_resource);
620 }
621 u300_unclock_primecells();
622
623 u300_assign_physmem();
624
625 /* Register the platform devices */
626 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
627
628#ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
629 /*
630 * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
631 * both subsystems are requesting this mode.
632 * If we not share the Acc SDRAM, this is never the case. Therefore
633 * enable it here from the App side.
634 */
635 val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
636 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
637 writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
638#endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */
639}
640
641static int core_module_init(void)
642{
643 /*
644 * This needs to be initialized later: it needs the input framework
645 * to be initialized first.
646 */
647 return mmc_init(&mmcsd_device);
648}
649module_init(core_module_init);
diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/mach-u300/include/mach/debug-macro.S
new file mode 100644
index 000000000000..f3a1cbbeeab3
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/debug-macro.S
@@ -0,0 +1,22 @@
1/*
2 *
3 * arch-arm/mach-u300/include/mach/debug-macro.S
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Debugging macro include header.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <mach/hardware.h>
12
13 .macro addruart,rx
14 /* If we move the adress using MMU, use this. */
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ MMU enabled?
17 ldreq \rx, = U300_SLOW_PER_PHYS_BASE @ MMU off, physical address
18 ldrne \rx, = U300_SLOW_PER_VIRT_BASE @ MMU on, virtual address
19 orr \rx, \rx, #0x00003000
20 .endm
21
22#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-u300/include/mach/entry-macro.S b/arch/arm/mach-u300/include/mach/entry-macro.S
new file mode 100644
index 000000000000..20731ae39d38
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/entry-macro.S
@@ -0,0 +1,40 @@
1/*
2 *
3 * arch-arm/mach-u300/include/mach/entry-macro.S
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Low-level IRQ helper macros for ST-Ericsson U300
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <mach/hardware.h>
12#include <asm/hardware/vic.h>
13
14 .macro disable_fiq
15 .endm
16
17 .macro get_irqnr_preamble, base, tmp
18 .endm
19
20 .macro arch_ret_to_user, tmp1, tmp2
21 .endm
22
23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
24 ldr \base, = U300_AHB_PER_VIRT_BASE-U300_AHB_PER_PHYS_BASE+U300_INTCON0_BASE
25 ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status
26 mov \irqnr, #0
27 teq \irqstat, #0
28 bne 1002f
291001: ldr \base, = U300_AHB_PER_VIRT_BASE-U300_AHB_PER_PHYS_BASE+U300_INTCON1_BASE
30 ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status
31 mov \irqnr, #32
32 teq \irqstat, #0
33 beq 1003f
341002: tst \irqstat, #1
35 bne 1003f
36 add \irqnr, \irqnr, #1
37 movs \irqstat, \irqstat, lsr #1
38 bne 1002b
391003: /* EQ will be set if no irqs pending */
40 .endm
diff --git a/arch/arm/mach-u300/include/mach/memory.h b/arch/arm/mach-u300/include/mach/memory.h
new file mode 100644
index 000000000000..bf134bcc129d
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/memory.h
@@ -0,0 +1,42 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/memory.h
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Memory virtual/physical mapping constants.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
11 */
12
13#ifndef __MACH_MEMORY_H
14#define __MACH_MEMORY_H
15
16#ifdef CONFIG_MACH_U300_DUAL_RAM
17
18#define PHYS_OFFSET UL(0x48000000)
19#define BOOT_PARAMS_OFFSET (PHYS_OFFSET + 0x100)
20
21#else
22
23#ifdef CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
24#define PHYS_OFFSET (0x28000000 + \
25 (CONFIG_MACH_U300_ACCESS_MEM_SIZE - \
26 (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024)
27#else
28#define PHYS_OFFSET (0x28000000 + \
29 (CONFIG_MACH_U300_ACCESS_MEM_SIZE + \
30 (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024)
31#endif
32#define BOOT_PARAMS_OFFSET (0x28000000 + \
33 (CONFIG_MACH_U300_ACCESS_MEM_SIZE + \
34 (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024 + 0x100)
35#endif
36
37/*
38 * We enable a real big DMA buffer if need be.
39 */
40#define CONSISTENT_DMA_SIZE SZ_4M
41
42#endif
diff --git a/arch/arm/mach-u300/include/mach/platform.h b/arch/arm/mach-u300/include/mach/platform.h
new file mode 100644
index 000000000000..77d9210a82e2
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/platform.h
@@ -0,0 +1,19 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/platform.h
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Basic platform init and mapping functions.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11
12#ifndef __ASSEMBLY__
13
14void u300_map_io(void);
15void u300_init_irq(void);
16void u300_init_devices(void);
17extern struct sys_timer u300_timer;
18
19#endif
diff --git a/arch/arm/mach-u300/include/mach/system.h b/arch/arm/mach-u300/include/mach/system.h
new file mode 100644
index 000000000000..8daf13634ce0
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/system.h
@@ -0,0 +1,42 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/system.h
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * System shutdown and reset functions.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <mach/hardware.h>
12#include <asm/io.h>
13#include <asm/hardware/vic.h>
14#include <asm/irq.h>
15
16/* Forward declare this function from the watchdog */
17void coh901327_watchdog_reset(void);
18
19static inline void arch_idle(void)
20{
21 cpu_do_idle();
22}
23
24static void arch_reset(char mode, const char *cmd)
25{
26 switch (mode) {
27 case 's':
28 case 'h':
29 printk(KERN_CRIT "RESET: shutting down/rebooting system\n");
30 /* Disable interrupts */
31 local_irq_disable();
32#ifdef CONFIG_COH901327_WATCHDOG
33 coh901327_watchdog_reset();
34#endif
35 break;
36 default:
37 /* Do nothing */
38 break;
39 }
40 /* Wait for system do die/reset. */
41 while (1);
42}
diff --git a/arch/arm/mach-u300/include/mach/timex.h b/arch/arm/mach-u300/include/mach/timex.h
new file mode 100644
index 000000000000..f233b72633f6
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/timex.h
@@ -0,0 +1,17 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/timex.h
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Platform tick rate definition.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#ifndef __MACH_TIMEX_H
12#define __MACH_TIMEX_H
13
14/* This is for the APP OS GP1 (General Purpose 1) timer */
15#define CLOCK_TICK_RATE 1000000
16
17#endif
diff --git a/arch/arm/mach-u300/include/mach/uncompress.h b/arch/arm/mach-u300/include/mach/uncompress.h
new file mode 100644
index 000000000000..29acb718acf7
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/uncompress.h
@@ -0,0 +1,46 @@
1/*
2 * arch/arm/mach-u300/include/mach/uncompress.h
3 *
4 * Copyright (C) 2003 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#define AMBA_UART_DR (*(volatile unsigned char *)0xc0013000)
21#define AMBA_UART_LCRH (*(volatile unsigned char *)0xc001302C)
22#define AMBA_UART_CR (*(volatile unsigned char *)0xc0013030)
23#define AMBA_UART_FR (*(volatile unsigned char *)0xc0013018)
24
25/*
26 * This does not append a newline
27 */
28static inline void putc(int c)
29{
30 while (AMBA_UART_FR & (1 << 5))
31 barrier();
32
33 AMBA_UART_DR = c;
34}
35
36static inline void flush(void)
37{
38 while (AMBA_UART_FR & (1 << 3))
39 barrier();
40}
41
42/*
43 * nothing to do
44 */
45#define arch_decomp_setup()
46#define arch_decomp_wdog()
diff --git a/arch/arm/mach-u300/include/mach/vmalloc.h b/arch/arm/mach-u300/include/mach/vmalloc.h
new file mode 100644
index 000000000000..b00c51a66fbe
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/vmalloc.h
@@ -0,0 +1,12 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/vmalloc.h
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Virtual memory allocations
9 * End must be above the I/O registers and on an even 2MiB boundary.
10 * Author: Linus Walleij <linus.walleij@stericsson.com>
11 */
12#define VMALLOC_END 0xfe800000
diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c
new file mode 100644
index 000000000000..3138d3955c9e
--- /dev/null
+++ b/arch/arm/mach-u300/mmc.c
@@ -0,0 +1,216 @@
1/*
2 *
3 * arch/arm/mach-u300/mmc.c
4 *
5 *
6 * Copyright (C) 2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 *
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 * Author: Johan Lundin <johan.lundin@stericsson.com>
11 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
12 */
13#include <linux/device.h>
14#include <linux/amba/bus.h>
15#include <linux/mmc/host.h>
16#include <linux/input.h>
17#include <linux/workqueue.h>
18#include <linux/delay.h>
19#include <linux/regulator/consumer.h>
20#include <linux/regulator/machine.h>
21#include <linux/gpio.h>
22
23#include <asm/mach/mmc.h>
24#include "mmc.h"
25
26struct mmci_card_event {
27 struct input_dev *mmc_input;
28 int mmc_inserted;
29 struct work_struct workq;
30 struct mmc_platform_data mmc0_plat_data;
31};
32
33static unsigned int mmc_status(struct device *dev)
34{
35 struct mmci_card_event *mmci_card = container_of(
36 dev->platform_data,
37 struct mmci_card_event, mmc0_plat_data);
38
39 return mmci_card->mmc_inserted;
40}
41
42/*
43 * Here follows a large chunk of code which will only be enabled if you
44 * have both the AB3100 chip mounted and the MMC subsystem activated.
45 */
46
47static u32 mmc_translate_vdd(struct device *dev, unsigned int voltage)
48{
49 int v;
50
51 /*
52 * MMC Spec:
53 * bit 7: 1.70 - 1.95V
54 * bit 8 - 14: 2.0 - 2.6V
55 * bit 15 - 23: 2.7 - 3.6V
56 *
57 * ab3100 voltages:
58 * 000 - 2.85V
59 * 001 - 2.75V
60 * 010 - 1.8V
61 * 011 - 1.5V
62 */
63 switch (voltage) {
64 case 8:
65 v = 3;
66 break;
67 case 9:
68 case 10:
69 case 11:
70 case 12:
71 case 13:
72 case 14:
73 case 15:
74 v = 1;
75 break;
76 case 16:
77 v = 1;
78 break;
79 case 17:
80 case 18:
81 case 19:
82 case 20:
83 case 21:
84 case 22:
85 case 23:
86 case 24:
87 v = 0;
88 break;
89 default:
90 v = 0;
91 break;
92 }
93
94 /* PL180 voltage register bits */
95 return v << 2;
96}
97
98
99
100static int mmci_callback(void *data)
101{
102 struct mmci_card_event *mmci_card = data;
103
104 disable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD);
105 schedule_work(&mmci_card->workq);
106
107 return 0;
108}
109
110
111static ssize_t gpio_show(struct device *dev, struct device_attribute *attr,
112 char *buf)
113{
114 struct mmci_card_event *mmci_card = container_of(
115 dev->platform_data,
116 struct mmci_card_event, mmc0_plat_data);
117
118
119 return sprintf(buf, "%d\n", !mmci_card->mmc_inserted);
120}
121
122static DEVICE_ATTR(mmc_inserted, S_IRUGO, gpio_show, NULL);
123
124static void _mmci_callback(struct work_struct *ws)
125{
126
127 struct mmci_card_event *mmci_card = container_of(
128 ws,
129 struct mmci_card_event, workq);
130
131 mdelay(20);
132
133 mmci_card->mmc_inserted = !!gpio_get_value(U300_GPIO_PIN_MMC_CD);
134
135 input_report_switch(mmci_card->mmc_input, KEY_INSERT,
136 !mmci_card->mmc_inserted);
137 input_sync(mmci_card->mmc_input);
138
139 pr_debug("MMC/SD card was %s\n",
140 mmci_card->mmc_inserted ? "removed" : "inserted");
141
142 enable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD, !mmci_card->mmc_inserted);
143}
144
145int __devinit mmc_init(struct amba_device *adev)
146{
147 struct mmci_card_event *mmci_card;
148 struct device *mmcsd_device = &adev->dev;
149 int ret = 0;
150
151 mmci_card = kzalloc(sizeof(struct mmci_card_event), GFP_KERNEL);
152 if (!mmci_card)
153 return -ENOMEM;
154
155 /* Nominally 2.85V on our platform */
156 mmci_card->mmc0_plat_data.ocr_mask = MMC_VDD_28_29;
157 mmci_card->mmc0_plat_data.translate_vdd = mmc_translate_vdd;
158 mmci_card->mmc0_plat_data.status = mmc_status;
159
160 mmcsd_device->platform_data = (void *) &mmci_card->mmc0_plat_data;
161
162 INIT_WORK(&mmci_card->workq, _mmci_callback);
163
164 ret = gpio_request(U300_GPIO_PIN_MMC_CD, "MMC card detection");
165 if (ret) {
166 printk(KERN_CRIT "Could not allocate MMC card detection " \
167 "GPIO pin\n");
168 goto out;
169 }
170
171 ret = gpio_direction_input(U300_GPIO_PIN_MMC_CD);
172 if (ret) {
173 printk(KERN_CRIT "Invalid GPIO pin requested\n");
174 goto out;
175 }
176
177 ret = sysfs_create_file(&mmcsd_device->kobj,
178 &dev_attr_mmc_inserted.attr);
179 if (ret)
180 goto out;
181
182 mmci_card->mmc_input = input_allocate_device();
183 if (!mmci_card->mmc_input) {
184 printk(KERN_CRIT "Could not allocate MMC input device\n");
185 return -ENOMEM;
186 }
187
188 mmci_card->mmc_input->name = "MMC insert notification";
189 mmci_card->mmc_input->id.bustype = BUS_HOST;
190 mmci_card->mmc_input->id.vendor = 0;
191 mmci_card->mmc_input->id.product = 0;
192 mmci_card->mmc_input->id.version = 0x0100;
193 mmci_card->mmc_input->dev.parent = mmcsd_device;
194 input_set_capability(mmci_card->mmc_input, EV_SW, KEY_INSERT);
195
196 /*
197 * Since this must always be compiled into the kernel, this input
198 * is never unregistered or free:ed.
199 */
200 ret = input_register_device(mmci_card->mmc_input);
201 if (ret) {
202 input_free_device(mmci_card->mmc_input);
203 goto out;
204 }
205
206 input_set_drvdata(mmci_card->mmc_input, mmci_card);
207
208 ret = gpio_register_callback(U300_GPIO_PIN_MMC_CD, mmci_callback,
209 mmci_card);
210
211 schedule_work(&mmci_card->workq);
212
213 printk(KERN_INFO "Registered MMC insert/remove notification\n");
214out:
215 return ret;
216}
diff --git a/arch/arm/mach-u300/mmc.h b/arch/arm/mach-u300/mmc.h
new file mode 100644
index 000000000000..92b85125abb3
--- /dev/null
+++ b/arch/arm/mach-u300/mmc.h
@@ -0,0 +1,18 @@
1/*
2 *
3 * arch/arm/mach-u300/mmc.h
4 *
5 *
6 * Copyright (C) 2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 *
9 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
10 */
11#ifndef MMC_H
12#define MMC_H
13
14#include <linux/amba/bus.h>
15
16int __devinit mmc_init(struct amba_device *adev);
17
18#endif
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
new file mode 100644
index 000000000000..57b5351b1816
--- /dev/null
+++ b/arch/arm/mach-u300/timer.c
@@ -0,0 +1,422 @@
1/*
2 *
3 * arch/arm/mach-u300/timer.c
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Timer COH 901 328, runs the OS timer interrupt.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <linux/interrupt.h>
12#include <linux/time.h>
13#include <linux/timex.h>
14#include <linux/clockchips.h>
15#include <linux/clocksource.h>
16#include <linux/types.h>
17#include <linux/io.h>
18
19#include <mach/hardware.h>
20
21/* Generic stuff */
22#include <asm/mach/map.h>
23#include <asm/mach/time.h>
24#include <asm/mach/irq.h>
25
26#include "clock.h"
27
28/*
29 * APP side special timer registers
30 * This timer contains four timers which can fire an interrupt each.
31 * OS (operating system) timer @ 32768 Hz
32 * DD (device driver) timer @ 1 kHz
33 * GP1 (general purpose 1) timer @ 1MHz
34 * GP2 (general purpose 2) timer @ 1MHz
35 */
36
37/* Reset OS Timer 32bit (-/W) */
38#define U300_TIMER_APP_ROST (0x0000)
39#define U300_TIMER_APP_ROST_TIMER_RESET (0x00000000)
40/* Enable OS Timer 32bit (-/W) */
41#define U300_TIMER_APP_EOST (0x0004)
42#define U300_TIMER_APP_EOST_TIMER_ENABLE (0x00000000)
43/* Disable OS Timer 32bit (-/W) */
44#define U300_TIMER_APP_DOST (0x0008)
45#define U300_TIMER_APP_DOST_TIMER_DISABLE (0x00000000)
46/* OS Timer Mode Register 32bit (-/W) */
47#define U300_TIMER_APP_SOSTM (0x000c)
48#define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS (0x00000000)
49#define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT (0x00000001)
50/* OS Timer Status Register 32bit (R/-) */
51#define U300_TIMER_APP_OSTS (0x0010)
52#define U300_TIMER_APP_OSTS_TIMER_STATE_MASK (0x0000000F)
53#define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE (0x00000001)
54#define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE (0x00000002)
55#define U300_TIMER_APP_OSTS_ENABLE_IND (0x00000010)
56#define U300_TIMER_APP_OSTS_MODE_MASK (0x00000020)
57#define U300_TIMER_APP_OSTS_MODE_CONTINUOUS (0x00000000)
58#define U300_TIMER_APP_OSTS_MODE_ONE_SHOT (0x00000020)
59#define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND (0x00000040)
60#define U300_TIMER_APP_OSTS_IRQ_PENDING_IND (0x00000080)
61/* OS Timer Current Count Register 32bit (R/-) */
62#define U300_TIMER_APP_OSTCC (0x0014)
63/* OS Timer Terminal Count Register 32bit (R/W) */
64#define U300_TIMER_APP_OSTTC (0x0018)
65/* OS Timer Interrupt Enable Register 32bit (-/W) */
66#define U300_TIMER_APP_OSTIE (0x001c)
67#define U300_TIMER_APP_OSTIE_IRQ_DISABLE (0x00000000)
68#define U300_TIMER_APP_OSTIE_IRQ_ENABLE (0x00000001)
69/* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
70#define U300_TIMER_APP_OSTIA (0x0020)
71#define U300_TIMER_APP_OSTIA_IRQ_ACK (0x00000080)
72
73/* Reset DD Timer 32bit (-/W) */
74#define U300_TIMER_APP_RDDT (0x0040)
75#define U300_TIMER_APP_RDDT_TIMER_RESET (0x00000000)
76/* Enable DD Timer 32bit (-/W) */
77#define U300_TIMER_APP_EDDT (0x0044)
78#define U300_TIMER_APP_EDDT_TIMER_ENABLE (0x00000000)
79/* Disable DD Timer 32bit (-/W) */
80#define U300_TIMER_APP_DDDT (0x0048)
81#define U300_TIMER_APP_DDDT_TIMER_DISABLE (0x00000000)
82/* DD Timer Mode Register 32bit (-/W) */
83#define U300_TIMER_APP_SDDTM (0x004c)
84#define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS (0x00000000)
85#define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT (0x00000001)
86/* DD Timer Status Register 32bit (R/-) */
87#define U300_TIMER_APP_DDTS (0x0050)
88#define U300_TIMER_APP_DDTS_TIMER_STATE_MASK (0x0000000F)
89#define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE (0x00000001)
90#define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE (0x00000002)
91#define U300_TIMER_APP_DDTS_ENABLE_IND (0x00000010)
92#define U300_TIMER_APP_DDTS_MODE_MASK (0x00000020)
93#define U300_TIMER_APP_DDTS_MODE_CONTINUOUS (0x00000000)
94#define U300_TIMER_APP_DDTS_MODE_ONE_SHOT (0x00000020)
95#define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND (0x00000040)
96#define U300_TIMER_APP_DDTS_IRQ_PENDING_IND (0x00000080)
97/* DD Timer Current Count Register 32bit (R/-) */
98#define U300_TIMER_APP_DDTCC (0x0054)
99/* DD Timer Terminal Count Register 32bit (R/W) */
100#define U300_TIMER_APP_DDTTC (0x0058)
101/* DD Timer Interrupt Enable Register 32bit (-/W) */
102#define U300_TIMER_APP_DDTIE (0x005c)
103#define U300_TIMER_APP_DDTIE_IRQ_DISABLE (0x00000000)
104#define U300_TIMER_APP_DDTIE_IRQ_ENABLE (0x00000001)
105/* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
106#define U300_TIMER_APP_DDTIA (0x0060)
107#define U300_TIMER_APP_DDTIA_IRQ_ACK (0x00000080)
108
109/* Reset GP1 Timer 32bit (-/W) */
110#define U300_TIMER_APP_RGPT1 (0x0080)
111#define U300_TIMER_APP_RGPT1_TIMER_RESET (0x00000000)
112/* Enable GP1 Timer 32bit (-/W) */
113#define U300_TIMER_APP_EGPT1 (0x0084)
114#define U300_TIMER_APP_EGPT1_TIMER_ENABLE (0x00000000)
115/* Disable GP1 Timer 32bit (-/W) */
116#define U300_TIMER_APP_DGPT1 (0x0088)
117#define U300_TIMER_APP_DGPT1_TIMER_DISABLE (0x00000000)
118/* GP1 Timer Mode Register 32bit (-/W) */
119#define U300_TIMER_APP_SGPT1M (0x008c)
120#define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS (0x00000000)
121#define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT (0x00000001)
122/* GP1 Timer Status Register 32bit (R/-) */
123#define U300_TIMER_APP_GPT1S (0x0090)
124#define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK (0x0000000F)
125#define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE (0x00000001)
126#define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE (0x00000002)
127#define U300_TIMER_APP_GPT1S_ENABLE_IND (0x00000010)
128#define U300_TIMER_APP_GPT1S_MODE_MASK (0x00000020)
129#define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS (0x00000000)
130#define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT (0x00000020)
131#define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND (0x00000040)
132#define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND (0x00000080)
133/* GP1 Timer Current Count Register 32bit (R/-) */
134#define U300_TIMER_APP_GPT1CC (0x0094)
135/* GP1 Timer Terminal Count Register 32bit (R/W) */
136#define U300_TIMER_APP_GPT1TC (0x0098)
137/* GP1 Timer Interrupt Enable Register 32bit (-/W) */
138#define U300_TIMER_APP_GPT1IE (0x009c)
139#define U300_TIMER_APP_GPT1IE_IRQ_DISABLE (0x00000000)
140#define U300_TIMER_APP_GPT1IE_IRQ_ENABLE (0x00000001)
141/* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
142#define U300_TIMER_APP_GPT1IA (0x00a0)
143#define U300_TIMER_APP_GPT1IA_IRQ_ACK (0x00000080)
144
145/* Reset GP2 Timer 32bit (-/W) */
146#define U300_TIMER_APP_RGPT2 (0x00c0)
147#define U300_TIMER_APP_RGPT2_TIMER_RESET (0x00000000)
148/* Enable GP2 Timer 32bit (-/W) */
149#define U300_TIMER_APP_EGPT2 (0x00c4)
150#define U300_TIMER_APP_EGPT2_TIMER_ENABLE (0x00000000)
151/* Disable GP2 Timer 32bit (-/W) */
152#define U300_TIMER_APP_DGPT2 (0x00c8)
153#define U300_TIMER_APP_DGPT2_TIMER_DISABLE (0x00000000)
154/* GP2 Timer Mode Register 32bit (-/W) */
155#define U300_TIMER_APP_SGPT2M (0x00cc)
156#define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS (0x00000000)
157#define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT (0x00000001)
158/* GP2 Timer Status Register 32bit (R/-) */
159#define U300_TIMER_APP_GPT2S (0x00d0)
160#define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK (0x0000000F)
161#define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE (0x00000001)
162#define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE (0x00000002)
163#define U300_TIMER_APP_GPT2S_ENABLE_IND (0x00000010)
164#define U300_TIMER_APP_GPT2S_MODE_MASK (0x00000020)
165#define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS (0x00000000)
166#define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT (0x00000020)
167#define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND (0x00000040)
168#define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND (0x00000080)
169/* GP2 Timer Current Count Register 32bit (R/-) */
170#define U300_TIMER_APP_GPT2CC (0x00d4)
171/* GP2 Timer Terminal Count Register 32bit (R/W) */
172#define U300_TIMER_APP_GPT2TC (0x00d8)
173/* GP2 Timer Interrupt Enable Register 32bit (-/W) */
174#define U300_TIMER_APP_GPT2IE (0x00dc)
175#define U300_TIMER_APP_GPT2IE_IRQ_DISABLE (0x00000000)
176#define U300_TIMER_APP_GPT2IE_IRQ_ENABLE (0x00000001)
177/* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
178#define U300_TIMER_APP_GPT2IA (0x00e0)
179#define U300_TIMER_APP_GPT2IA_IRQ_ACK (0x00000080)
180
181/* Clock request control register - all four timers */
182#define U300_TIMER_APP_CRC (0x100)
183#define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE (0x00000001)
184
185#define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
186#define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
187
188/*
189 * The u300_set_mode() function is always called first, if we
190 * have oneshot timer active, the oneshot scheduling function
191 * u300_set_next_event() is called immediately after.
192 */
193static void u300_set_mode(enum clock_event_mode mode,
194 struct clock_event_device *evt)
195{
196 switch (mode) {
197 case CLOCK_EVT_MODE_PERIODIC:
198 /* Disable interrupts on GPT1 */
199 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
200 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
201 /* Disable GP1 while we're reprogramming it. */
202 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
203 U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
204 /*
205 * Set the periodic mode to a certain number of ticks per
206 * jiffy.
207 */
208 writel(TICKS_PER_JIFFY,
209 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
210 /*
211 * Set continuous mode, so the timer keeps triggering
212 * interrupts.
213 */
214 writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
215 U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
216 /* Enable timer interrupts */
217 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
218 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
219 /* Then enable the OS timer again */
220 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
221 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
222 break;
223 case CLOCK_EVT_MODE_ONESHOT:
224 /* Just break; here? */
225 /*
226 * The actual event will be programmed by the next event hook,
227 * so we just set a dummy value somewhere at the end of the
228 * universe here.
229 */
230 /* Disable interrupts on GPT1 */
231 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
232 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
233 /* Disable GP1 while we're reprogramming it. */
234 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
235 U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
236 /*
237 * Expire far in the future, u300_set_next_event() will be
238 * called soon...
239 */
240 writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
241 /* We run one shot per tick here! */
242 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
243 U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
244 /* Enable interrupts for this timer */
245 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
246 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
247 /* Enable timer */
248 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
249 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
250 break;
251 case CLOCK_EVT_MODE_UNUSED:
252 case CLOCK_EVT_MODE_SHUTDOWN:
253 /* Disable interrupts on GP1 */
254 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
255 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
256 /* Disable GP1 */
257 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
258 U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
259 break;
260 case CLOCK_EVT_MODE_RESUME:
261 /* Ignore this call */
262 break;
263 }
264}
265
266/*
267 * The app timer in one shot mode obviously has to be reprogrammed
268 * in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
269 * the interrupt disable + timer disable commands with a reset command,
270 * it will fail miserably. Apparently (and I found this the hard way)
271 * the timer is very sensitive to the instruction order, though you don't
272 * get that impression from the data sheet.
273 */
274static int u300_set_next_event(unsigned long cycles,
275 struct clock_event_device *evt)
276
277{
278 /* Disable interrupts on GPT1 */
279 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
280 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
281 /* Disable GP1 while we're reprogramming it. */
282 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
283 U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
284 /* Reset the General Purpose timer 1. */
285 writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
286 U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
287 /* IRQ in n * cycles */
288 writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
289 /*
290 * We run one shot per tick here! (This is necessary to reconfigure,
291 * the timer will tilt if you don't!)
292 */
293 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
294 U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
295 /* Enable timer interrupts */
296 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
297 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
298 /* Then enable the OS timer again */
299 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
300 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
301 return 0;
302}
303
304
305/* Use general purpose timer 1 as clock event */
306static struct clock_event_device clockevent_u300_1mhz = {
307 .name = "GPT1",
308 .rating = 300, /* Reasonably fast and accurate clock event */
309 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
310 /* 22 calculated using the algorithm in arch/mips/kernel/time.c */
311 .shift = 22,
312 .set_next_event = u300_set_next_event,
313 .set_mode = u300_set_mode,
314};
315
316/* Clock event timer interrupt handler */
317static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
318{
319 struct clock_event_device *evt = &clockevent_u300_1mhz;
320 /* ACK/Clear timer IRQ for the APP GPT1 Timer */
321 writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
322 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA);
323 evt->event_handler(evt);
324 return IRQ_HANDLED;
325}
326
327static struct irqaction u300_timer_irq = {
328 .name = "U300 Timer Tick",
329 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
330 .handler = u300_timer_interrupt,
331};
332
333/* Use general purpose timer 2 as clock source */
334static cycle_t u300_get_cycles(void)
335{
336 return (cycles_t) readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
337}
338
339static struct clocksource clocksource_u300_1mhz = {
340 .name = "GPT2",
341 .rating = 300, /* Reasonably fast and accurate clock source */
342 .read = u300_get_cycles,
343 .mask = CLOCKSOURCE_MASK(32), /* 32 bits */
344 /* 22 calculated using the algorithm in arch/mips/kernel/time.c */
345 .shift = 22,
346 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
347};
348
349
350/*
351 * This sets up the system timers, clock source and clock event.
352 */
353static void __init u300_timer_init(void)
354{
355 u300_enable_timer_clock();
356 /*
357 * Disable the "OS" and "DD" timers - these are designed for Symbian!
358 * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
359 */
360 writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
361 U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC);
362 writel(U300_TIMER_APP_ROST_TIMER_RESET,
363 U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST);
364 writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
365 U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST);
366 writel(U300_TIMER_APP_RDDT_TIMER_RESET,
367 U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT);
368 writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
369 U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT);
370
371 /* Reset the General Purpose timer 1. */
372 writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
373 U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
374
375 /* Set up the IRQ handler */
376 setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq);
377
378 /* Reset the General Purpose timer 2 */
379 writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
380 U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2);
381 /* Set this timer to run around forever */
382 writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC);
383 /* Set continuous mode so it wraps around */
384 writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
385 U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M);
386 /* Disable timer interrupts */
387 writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
388 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE);
389 /* Then enable the GP2 timer to use as a free running us counter */
390 writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
391 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
392
393 /* This is a pure microsecond clock source */
394 clocksource_u300_1mhz.mult =
395 clocksource_khz2mult(1000, clocksource_u300_1mhz.shift);
396 if (clocksource_register(&clocksource_u300_1mhz))
397 printk(KERN_ERR "timer: failed to initialize clock "
398 "source %s\n", clocksource_u300_1mhz.name);
399
400 clockevent_u300_1mhz.mult =
401 div_sc(1000000, NSEC_PER_SEC, clockevent_u300_1mhz.shift);
402 /* 32bit counter, so 32bits delta is max */
403 clockevent_u300_1mhz.max_delta_ns =
404 clockevent_delta2ns(0xffffffff, &clockevent_u300_1mhz);
405 /* This timer is slow enough to set for 1 cycle == 1 MHz */
406 clockevent_u300_1mhz.min_delta_ns =
407 clockevent_delta2ns(1, &clockevent_u300_1mhz);
408 clockevent_u300_1mhz.cpumask = cpumask_of(0);
409 clockevents_register_device(&clockevent_u300_1mhz);
410 /*
411 * TODO: init and register the rest of the timers too, they can be
412 * used by hrtimers!
413 */
414}
415
416/*
417 * Very simple system timer that only register the clock event and
418 * clock source.
419 */
420struct sys_timer u300_timer = {
421 .init = u300_timer_init,
422};
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
new file mode 100644
index 000000000000..d2a0b8847a18
--- /dev/null
+++ b/arch/arm/mach-u300/u300.c
@@ -0,0 +1,55 @@
1/*
2 *
3 * arch/arm/mach-u300/u300.c
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Platform machine definition.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mm.h>
14#include <linux/sched.h>
15#include <linux/interrupt.h>
16#include <linux/ioport.h>
17#include <linux/platform_device.h>
18#include <linux/io.h>
19#include <mach/hardware.h>
20#include <mach/platform.h>
21#include <mach/memory.h>
22#include <asm/mach-types.h>
23#include <asm/mach/arch.h>
24
25static void __init u300_init_machine(void)
26{
27 u300_init_devices();
28}
29
30#ifdef CONFIG_MACH_U300_BS2X
31#define MACH_U300_STRING "Ericsson AB U300 S25/S26/B25/B26 Prototype Board"
32#endif
33
34#ifdef CONFIG_MACH_U300_BS330
35#define MACH_U300_STRING "Ericsson AB U330 S330/B330 Prototype Board"
36#endif
37
38#ifdef CONFIG_MACH_U300_BS335
39#define MACH_U300_STRING "Ericsson AB U335 S335/B335 Prototype Board"
40#endif
41
42#ifdef CONFIG_MACH_U300_BS365
43#define MACH_U300_STRING "Ericsson AB U365 S365/B365 Prototype Board"
44#endif
45
46MACHINE_START(U300, MACH_U300_STRING)
47 /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
48 .phys_io = U300_AHB_PER_PHYS_BASE,
49 .io_pg_offst = ((U300_AHB_PER_VIRT_BASE) >> 18) & 0xfffc,
50 .boot_params = BOOT_PARAMS_OFFSET,
51 .map_io = u300_map_io,
52 .init_irq = u300_init_irq,
53 .timer = &u300_timer,
54 .init_machine = u300_init_machine,
55MACHINE_END
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 06:24:56 -0500