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authorLinus Torvalds <torvalds@linux-foundation.org>2010-09-19 14:05:05 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-09-19 14:05:05 -0400
commitf1c9c9797a7c519a70b8e4607f41d97ec59fc8f0 (patch)
tree42b0cbfeb946a76844d20c7aae39037f5e1c7ba3 /arch/arm
parent112d421df2fddc0278584b084f4fcfedd144c5f4 (diff)
parent4d89ecaae9c145e60b920acb1120f1de3d6eac6e (diff)
Merge branch 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung
* 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: S3C64XX: Add IORESOURCE_IRQ_HIGHLEVEL flag to dm9000 on mach-real6410 ARM: S3C64XX: Fix coding style errors on mach-real6410 ARM: S3C64XX: Prototype SPI devices ARM: S3C64XX: Fix dev-spi build ARM: SAMSUNG: Fix on s5p_gpio_[get,set]_drvstr ARM: SAMSUNG: Fix on drive strength value ARM: S5PV210: Add FIMC clocks ARM: S5PV210: Reduce the iodesc length of systimer ARM: S5PV210: Update I2C-1 Clock Register Property. ARM: S5P: Decrease IO Registers memory region size on FIMC ARM: S5P: Fix DMA coherent mask for FIMC
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-s3c64xx/dev-spi.c3
-rw-r--r--arch/arm/mach-s3c64xx/mach-real6410.c104
-rw-r--r--arch/arm/mach-s5pv210/clock.c20
-rw-r--r--arch/arm/mach-s5pv210/cpu.c2
-rw-r--r--arch/arm/plat-s5p/dev-fimc0.c9
-rw-r--r--arch/arm/plat-s5p/dev-fimc1.c9
-rw-r--r--arch/arm/plat-s5p/dev-fimc2.c9
-rw-r--r--arch/arm/plat-samsung/gpio-config.c7
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-cfg.h10
9 files changed, 107 insertions, 66 deletions
diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c
index a492b982aa06..405e62128917 100644
--- a/arch/arm/mach-s3c64xx/dev-spi.c
+++ b/arch/arm/mach-s3c64xx/dev-spi.c
@@ -18,10 +18,11 @@
18#include <mach/map.h> 18#include <mach/map.h>
19#include <mach/gpio-bank-c.h> 19#include <mach/gpio-bank-c.h>
20#include <mach/spi-clocks.h> 20#include <mach/spi-clocks.h>
21#include <mach/irqs.h>
21 22
22#include <plat/s3c64xx-spi.h> 23#include <plat/s3c64xx-spi.h>
23#include <plat/gpio-cfg.h> 24#include <plat/gpio-cfg.h>
24#include <plat/irqs.h> 25#include <plat/devs.h>
25 26
26static char *spi_src_clks[] = { 27static char *spi_src_clks[] = {
27 [S3C64XX_SPI_SRCCLK_PCLK] = "pclk", 28 [S3C64XX_SPI_SRCCLK_PCLK] = "pclk",
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 5c07d013b23d..e130379ba0e8 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -30,73 +30,73 @@
30#include <plat/devs.h> 30#include <plat/devs.h>
31#include <plat/regs-serial.h> 31#include <plat/regs-serial.h>
32 32
33#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK 33#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
34#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB 34#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
35#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE 35#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
36 36
37static struct s3c2410_uartcfg real6410_uartcfgs[] __initdata = { 37static struct s3c2410_uartcfg real6410_uartcfgs[] __initdata = {
38 [0] = { 38 [0] = {
39 .hwport = 0, 39 .hwport = 0,
40 .flags = 0, 40 .flags = 0,
41 .ucon = UCON, 41 .ucon = UCON,
42 .ulcon = ULCON, 42 .ulcon = ULCON,
43 .ufcon = UFCON, 43 .ufcon = UFCON,
44 }, 44 },
45 [1] = { 45 [1] = {
46 .hwport = 1, 46 .hwport = 1,
47 .flags = 0, 47 .flags = 0,
48 .ucon = UCON, 48 .ucon = UCON,
49 .ulcon = ULCON, 49 .ulcon = ULCON,
50 .ufcon = UFCON, 50 .ufcon = UFCON,
51 }, 51 },
52 [2] = { 52 [2] = {
53 .hwport = 2, 53 .hwport = 2,
54 .flags = 0, 54 .flags = 0,
55 .ucon = UCON, 55 .ucon = UCON,
56 .ulcon = ULCON, 56 .ulcon = ULCON,
57 .ufcon = UFCON, 57 .ufcon = UFCON,
58 }, 58 },
59 [3] = { 59 [3] = {
60 .hwport = 3, 60 .hwport = 3,
61 .flags = 0, 61 .flags = 0,
62 .ucon = UCON, 62 .ucon = UCON,
63 .ulcon = ULCON, 63 .ulcon = ULCON,
64 .ufcon = UFCON, 64 .ufcon = UFCON,
65 }, 65 },
66}; 66};
67 67
68/* DM9000AEP 10/100 ethernet controller */ 68/* DM9000AEP 10/100 ethernet controller */
69 69
70static struct resource real6410_dm9k_resource[] = { 70static struct resource real6410_dm9k_resource[] = {
71 [0] = { 71 [0] = {
72 .start = S3C64XX_PA_XM0CSN1, 72 .start = S3C64XX_PA_XM0CSN1,
73 .end = S3C64XX_PA_XM0CSN1 + 1, 73 .end = S3C64XX_PA_XM0CSN1 + 1,
74 .flags = IORESOURCE_MEM 74 .flags = IORESOURCE_MEM
75 }, 75 },
76 [1] = { 76 [1] = {
77 .start = S3C64XX_PA_XM0CSN1 + 4, 77 .start = S3C64XX_PA_XM0CSN1 + 4,
78 .end = S3C64XX_PA_XM0CSN1 + 5, 78 .end = S3C64XX_PA_XM0CSN1 + 5,
79 .flags = IORESOURCE_MEM 79 .flags = IORESOURCE_MEM
80 }, 80 },
81 [2] = { 81 [2] = {
82 .start = S3C_EINT(7), 82 .start = S3C_EINT(7),
83 .end = S3C_EINT(7), 83 .end = S3C_EINT(7),
84 .flags = IORESOURCE_IRQ, 84 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
85 } 85 }
86}; 86};
87 87
88static struct dm9000_plat_data real6410_dm9k_pdata = { 88static struct dm9000_plat_data real6410_dm9k_pdata = {
89 .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM), 89 .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
90}; 90};
91 91
92static struct platform_device real6410_device_eth = { 92static struct platform_device real6410_device_eth = {
93 .name = "dm9000", 93 .name = "dm9000",
94 .id = -1, 94 .id = -1,
95 .num_resources = ARRAY_SIZE(real6410_dm9k_resource), 95 .num_resources = ARRAY_SIZE(real6410_dm9k_resource),
96 .resource = real6410_dm9k_resource, 96 .resource = real6410_dm9k_resource,
97 .dev = { 97 .dev = {
98 .platform_data = &real6410_dm9k_pdata, 98 .platform_data = &real6410_dm9k_pdata,
99 }, 99 },
100}; 100};
101 101
102static struct platform_device *real6410_devices[] __initdata = { 102static struct platform_device *real6410_devices[] __initdata = {
@@ -129,12 +129,12 @@ static void __init real6410_machine_init(void)
129 /* set timing for nCS1 suitable for ethernet chip */ 129 /* set timing for nCS1 suitable for ethernet chip */
130 130
131 __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) | 131 __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
132 (6 << S3C64XX_SROM_BCX__TACP__SHIFT) | 132 (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
133 (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) | 133 (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
134 (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) | 134 (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
135 (13 << S3C64XX_SROM_BCX__TACC__SHIFT) | 135 (13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
136 (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) | 136 (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
137 (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1); 137 (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
138 138
139 platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices)); 139 platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices));
140} 140}
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index af91fefef2c6..cfecd70657cb 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -281,6 +281,24 @@ static struct clk init_clocks_disable[] = {
281 .enable = s5pv210_clk_ip0_ctrl, 281 .enable = s5pv210_clk_ip0_ctrl,
282 .ctrlbit = (1<<29), 282 .ctrlbit = (1<<29),
283 }, { 283 }, {
284 .name = "fimc",
285 .id = 0,
286 .parent = &clk_hclk_dsys.clk,
287 .enable = s5pv210_clk_ip0_ctrl,
288 .ctrlbit = (1 << 24),
289 }, {
290 .name = "fimc",
291 .id = 1,
292 .parent = &clk_hclk_dsys.clk,
293 .enable = s5pv210_clk_ip0_ctrl,
294 .ctrlbit = (1 << 25),
295 }, {
296 .name = "fimc",
297 .id = 2,
298 .parent = &clk_hclk_dsys.clk,
299 .enable = s5pv210_clk_ip0_ctrl,
300 .ctrlbit = (1 << 26),
301 }, {
284 .name = "otg", 302 .name = "otg",
285 .id = -1, 303 .id = -1,
286 .parent = &clk_hclk_psys.clk, 304 .parent = &clk_hclk_psys.clk,
@@ -357,7 +375,7 @@ static struct clk init_clocks_disable[] = {
357 .id = 1, 375 .id = 1,
358 .parent = &clk_pclk_psys.clk, 376 .parent = &clk_pclk_psys.clk,
359 .enable = s5pv210_clk_ip3_ctrl, 377 .enable = s5pv210_clk_ip3_ctrl,
360 .ctrlbit = (1<<8), 378 .ctrlbit = (1 << 10),
361 }, { 379 }, {
362 .name = "i2c", 380 .name = "i2c",
363 .id = 2, 381 .id = 2,
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index b9f4d677cf55..77f456c91ad3 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -47,7 +47,7 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
47 { 47 {
48 .virtual = (unsigned long)S5P_VA_SYSTIMER, 48 .virtual = (unsigned long)S5P_VA_SYSTIMER,
49 .pfn = __phys_to_pfn(S5PV210_PA_SYSTIMER), 49 .pfn = __phys_to_pfn(S5PV210_PA_SYSTIMER),
50 .length = SZ_1M, 50 .length = SZ_4K,
51 .type = MT_DEVICE, 51 .type = MT_DEVICE,
52 }, { 52 }, {
53 .virtual = (unsigned long)VA_VIC2, 53 .virtual = (unsigned long)VA_VIC2,
diff --git a/arch/arm/plat-s5p/dev-fimc0.c b/arch/arm/plat-s5p/dev-fimc0.c
index d3f1a9b5d2b5..608770fc1531 100644
--- a/arch/arm/plat-s5p/dev-fimc0.c
+++ b/arch/arm/plat-s5p/dev-fimc0.c
@@ -10,6 +10,7 @@
10 */ 10 */
11 11
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/dma-mapping.h>
13#include <linux/platform_device.h> 14#include <linux/platform_device.h>
14#include <linux/interrupt.h> 15#include <linux/interrupt.h>
15#include <linux/ioport.h> 16#include <linux/ioport.h>
@@ -18,7 +19,7 @@
18static struct resource s5p_fimc0_resource[] = { 19static struct resource s5p_fimc0_resource[] = {
19 [0] = { 20 [0] = {
20 .start = S5P_PA_FIMC0, 21 .start = S5P_PA_FIMC0,
21 .end = S5P_PA_FIMC0 + SZ_1M - 1, 22 .end = S5P_PA_FIMC0 + SZ_4K - 1,
22 .flags = IORESOURCE_MEM, 23 .flags = IORESOURCE_MEM,
23 }, 24 },
24 [1] = { 25 [1] = {
@@ -28,9 +29,15 @@ static struct resource s5p_fimc0_resource[] = {
28 }, 29 },
29}; 30};
30 31
32static u64 s5p_fimc0_dma_mask = DMA_BIT_MASK(32);
33
31struct platform_device s5p_device_fimc0 = { 34struct platform_device s5p_device_fimc0 = {
32 .name = "s5p-fimc", 35 .name = "s5p-fimc",
33 .id = 0, 36 .id = 0,
34 .num_resources = ARRAY_SIZE(s5p_fimc0_resource), 37 .num_resources = ARRAY_SIZE(s5p_fimc0_resource),
35 .resource = s5p_fimc0_resource, 38 .resource = s5p_fimc0_resource,
39 .dev = {
40 .dma_mask = &s5p_fimc0_dma_mask,
41 .coherent_dma_mask = DMA_BIT_MASK(32),
42 },
36}; 43};
diff --git a/arch/arm/plat-s5p/dev-fimc1.c b/arch/arm/plat-s5p/dev-fimc1.c
index 41bd6986d0ad..76e3a97a87d3 100644
--- a/arch/arm/plat-s5p/dev-fimc1.c
+++ b/arch/arm/plat-s5p/dev-fimc1.c
@@ -10,6 +10,7 @@
10 */ 10 */
11 11
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/dma-mapping.h>
13#include <linux/platform_device.h> 14#include <linux/platform_device.h>
14#include <linux/interrupt.h> 15#include <linux/interrupt.h>
15#include <linux/ioport.h> 16#include <linux/ioport.h>
@@ -18,7 +19,7 @@
18static struct resource s5p_fimc1_resource[] = { 19static struct resource s5p_fimc1_resource[] = {
19 [0] = { 20 [0] = {
20 .start = S5P_PA_FIMC1, 21 .start = S5P_PA_FIMC1,
21 .end = S5P_PA_FIMC1 + SZ_1M - 1, 22 .end = S5P_PA_FIMC1 + SZ_4K - 1,
22 .flags = IORESOURCE_MEM, 23 .flags = IORESOURCE_MEM,
23 }, 24 },
24 [1] = { 25 [1] = {
@@ -28,9 +29,15 @@ static struct resource s5p_fimc1_resource[] = {
28 }, 29 },
29}; 30};
30 31
32static u64 s5p_fimc1_dma_mask = DMA_BIT_MASK(32);
33
31struct platform_device s5p_device_fimc1 = { 34struct platform_device s5p_device_fimc1 = {
32 .name = "s5p-fimc", 35 .name = "s5p-fimc",
33 .id = 1, 36 .id = 1,
34 .num_resources = ARRAY_SIZE(s5p_fimc1_resource), 37 .num_resources = ARRAY_SIZE(s5p_fimc1_resource),
35 .resource = s5p_fimc1_resource, 38 .resource = s5p_fimc1_resource,
39 .dev = {
40 .dma_mask = &s5p_fimc1_dma_mask,
41 .coherent_dma_mask = DMA_BIT_MASK(32),
42 },
36}; 43};
diff --git a/arch/arm/plat-s5p/dev-fimc2.c b/arch/arm/plat-s5p/dev-fimc2.c
index dfddeda6d4a3..24d29816fa2c 100644
--- a/arch/arm/plat-s5p/dev-fimc2.c
+++ b/arch/arm/plat-s5p/dev-fimc2.c
@@ -10,6 +10,7 @@
10 */ 10 */
11 11
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/dma-mapping.h>
13#include <linux/platform_device.h> 14#include <linux/platform_device.h>
14#include <linux/interrupt.h> 15#include <linux/interrupt.h>
15#include <linux/ioport.h> 16#include <linux/ioport.h>
@@ -18,7 +19,7 @@
18static struct resource s5p_fimc2_resource[] = { 19static struct resource s5p_fimc2_resource[] = {
19 [0] = { 20 [0] = {
20 .start = S5P_PA_FIMC2, 21 .start = S5P_PA_FIMC2,
21 .end = S5P_PA_FIMC2 + SZ_1M - 1, 22 .end = S5P_PA_FIMC2 + SZ_4K - 1,
22 .flags = IORESOURCE_MEM, 23 .flags = IORESOURCE_MEM,
23 }, 24 },
24 [1] = { 25 [1] = {
@@ -28,9 +29,15 @@ static struct resource s5p_fimc2_resource[] = {
28 }, 29 },
29}; 30};
30 31
32static u64 s5p_fimc2_dma_mask = DMA_BIT_MASK(32);
33
31struct platform_device s5p_device_fimc2 = { 34struct platform_device s5p_device_fimc2 = {
32 .name = "s5p-fimc", 35 .name = "s5p-fimc",
33 .id = 2, 36 .id = 2,
34 .num_resources = ARRAY_SIZE(s5p_fimc2_resource), 37 .num_resources = ARRAY_SIZE(s5p_fimc2_resource),
35 .resource = s5p_fimc2_resource, 38 .resource = s5p_fimc2_resource,
39 .dev = {
40 .dma_mask = &s5p_fimc2_dma_mask,
41 .coherent_dma_mask = DMA_BIT_MASK(32),
42 },
36}; 43};
diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c
index 57b68a50f45e..e3d41eaed1ff 100644
--- a/arch/arm/plat-samsung/gpio-config.c
+++ b/arch/arm/plat-samsung/gpio-config.c
@@ -273,13 +273,13 @@ s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
273 if (!chip) 273 if (!chip)
274 return -EINVAL; 274 return -EINVAL;
275 275
276 off = chip->chip.base - pin; 276 off = pin - chip->chip.base;
277 shift = off * 2; 277 shift = off * 2;
278 reg = chip->base + 0x0C; 278 reg = chip->base + 0x0C;
279 279
280 drvstr = __raw_readl(reg); 280 drvstr = __raw_readl(reg);
281 drvstr = 0xffff & (0x3 << shift);
282 drvstr = drvstr >> shift; 281 drvstr = drvstr >> shift;
282 drvstr &= 0x3;
283 283
284 return (__force s5p_gpio_drvstr_t)drvstr; 284 return (__force s5p_gpio_drvstr_t)drvstr;
285} 285}
@@ -296,11 +296,12 @@ int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
296 if (!chip) 296 if (!chip)
297 return -EINVAL; 297 return -EINVAL;
298 298
299 off = chip->chip.base - pin; 299 off = pin - chip->chip.base;
300 shift = off * 2; 300 shift = off * 2;
301 reg = chip->base + 0x0C; 301 reg = chip->base + 0x0C;
302 302
303 tmp = __raw_readl(reg); 303 tmp = __raw_readl(reg);
304 tmp &= ~(0x3 << shift);
304 tmp |= drvstr << shift; 305 tmp |= drvstr << shift;
305 306
306 __raw_writel(tmp, reg); 307 __raw_writel(tmp, reg);
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index db4112c6f2be..1c6b92947c5d 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -143,12 +143,12 @@ extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin);
143/* Define values for the drvstr available for each gpio pin. 143/* Define values for the drvstr available for each gpio pin.
144 * 144 *
145 * These values control the value of the output signal driver strength, 145 * These values control the value of the output signal driver strength,
146 * configurable on most pins on the S5C series. 146 * configurable on most pins on the S5P series.
147 */ 147 */
148#define S5P_GPIO_DRVSTR_LV1 ((__force s5p_gpio_drvstr_t)0x00) 148#define S5P_GPIO_DRVSTR_LV1 ((__force s5p_gpio_drvstr_t)0x0)
149#define S5P_GPIO_DRVSTR_LV2 ((__force s5p_gpio_drvstr_t)0x01) 149#define S5P_GPIO_DRVSTR_LV2 ((__force s5p_gpio_drvstr_t)0x2)
150#define S5P_GPIO_DRVSTR_LV3 ((__force s5p_gpio_drvstr_t)0x10) 150#define S5P_GPIO_DRVSTR_LV3 ((__force s5p_gpio_drvstr_t)0x1)
151#define S5P_GPIO_DRVSTR_LV4 ((__force s5p_gpio_drvstr_t)0x11) 151#define S5P_GPIO_DRVSTR_LV4 ((__force s5p_gpio_drvstr_t)0x3)
152 152
153/** 153/**
154 * s5c_gpio_get_drvstr() - get the driver streght value of a gpio pin 154 * s5c_gpio_get_drvstr() - get the driver streght value of a gpio pin
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 04:26:24 -0500