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authorJaroslav Kysela <perex@hera.kernel.org>2005-06-21 10:39:41 -0400
committerJaroslav Kysela <perex@hera.kernel.org>2005-06-21 10:39:41 -0400
commitfae6ec69c84d71b1d5bda9ede1a262c1681684aa (patch)
treeeb4aff9a5c2b7d04ce09a3717bb1dd4a79fe7595 /arch/arm
parentbbc0274e9bb2e3f1d724d445a2bd32566b9b66f7 (diff)
parent1d345dac1f30af1cd9f3a1faa12f9f18f17f236e (diff)
Merge with /pub/scm/linux/kernel/git/torvalds/linux-2.6.git
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig19
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/compressed/head-xscale.S7
-rw-r--r--arch/arm/common/amba.c2
-rw-r--r--arch/arm/common/dmabounce.c18
-rw-r--r--arch/arm/common/sharpsl_param.c2
-rw-r--r--arch/arm/configs/badge4_defconfig29
-rw-r--r--arch/arm/configs/enp2611_defconfig8
-rw-r--r--arch/arm/configs/h3600_defconfig24
-rw-r--r--arch/arm/configs/hackkit_defconfig22
-rw-r--r--arch/arm/configs/ixdp2400_defconfig8
-rw-r--r--arch/arm/configs/ixdp2401_defconfig8
-rw-r--r--arch/arm/configs/ixdp2800_defconfig8
-rw-r--r--arch/arm/configs/ixdp2801_defconfig8
-rw-r--r--arch/arm/kernel/Makefile2
-rw-r--r--arch/arm/kernel/arch.c46
-rw-r--r--arch/arm/kernel/ecard.c12
-rw-r--r--arch/arm/kernel/entry-armv.S272
-rw-r--r--arch/arm/kernel/entry-header.S7
-rw-r--r--arch/arm/kernel/head.S44
-rw-r--r--arch/arm/kernel/setup.c52
-rw-r--r--arch/arm/kernel/smp.c110
-rw-r--r--arch/arm/kernel/traps.c49
-rw-r--r--arch/arm/lib/ashldi3.c47
-rw-r--r--arch/arm/lib/ashrdi3.c48
-rw-r--r--arch/arm/lib/gcclib.h27
-rw-r--r--arch/arm/lib/io-writesw-armv4.S6
-rw-r--r--arch/arm/lib/longlong.h68
-rw-r--r--arch/arm/lib/lshrdi3.c47
-rw-r--r--arch/arm/lib/muldi3.c31
-rw-r--r--arch/arm/lib/ucmpdi2.c30
-rw-r--r--arch/arm/lib/udivdi3.c372
-rw-r--r--arch/arm/mach-aaec2000/Kconfig11
-rw-r--r--arch/arm/mach-aaec2000/Makefile9
-rw-r--r--arch/arm/mach-aaec2000/aaed2000.c48
-rw-r--r--arch/arm/mach-aaec2000/core.c157
-rw-r--r--arch/arm/mach-aaec2000/core.h16
-rw-r--r--arch/arm/mach-integrator/Makefile1
-rw-r--r--arch/arm/mach-integrator/core.c19
-rw-r--r--arch/arm/mach-integrator/headsmp.S37
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c1
-rw-r--r--arch/arm/mach-integrator/leds.c4
-rw-r--r--arch/arm/mach-integrator/platsmp.c192
-rw-r--r--arch/arm/mach-ixp2000/core.c34
-rw-r--r--arch/arm/mach-pxa/lubbock.c30
-rw-r--r--arch/arm/mach-pxa/mainstone.c40
-rw-r--r--arch/arm/mach-pxa/pm.c34
-rw-r--r--arch/arm/mach-pxa/pxa25x.c33
-rw-r--r--arch/arm/mach-pxa/pxa27x.c36
-rw-r--r--arch/arm/mach-s3c2410/dma.c4
-rw-r--r--arch/arm/mach-sa1100/Kconfig2
-rw-r--r--arch/arm/mach-sa1100/pm.c2
-rw-r--r--arch/arm/mach-versatile/Makefile1
-rw-r--r--arch/arm/mach-versatile/core.c16
-rw-r--r--arch/arm/mach-versatile/pci.c360
-rw-r--r--arch/arm/mm/Kconfig17
-rw-r--r--arch/arm/mm/Makefile2
-rw-r--r--arch/arm/mm/copypage-v6.c6
-rw-r--r--arch/arm/mm/copypage-xscale.S113
-rw-r--r--arch/arm/mm/copypage-xscale.c131
-rw-r--r--arch/arm/mm/fault-armv.c31
-rw-r--r--arch/arm/mm/flush.c44
-rw-r--r--arch/arm/mm/ioremap.c47
-rw-r--r--arch/arm/mm/minicache.c73
64 files changed, 2117 insertions, 868 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bf397a9f8ac2..ee8a9ad7bbd9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -67,10 +67,6 @@ config GENERIC_BUST_SPINLOCK
67config GENERIC_ISA_DMA 67config GENERIC_ISA_DMA
68 bool 68 bool
69 69
70config GENERIC_IOMAP
71 bool
72 default y
73
74config FIQ 70config FIQ
75 bool 71 bool
76 72
@@ -202,6 +198,11 @@ config ARCH_H720X
202 help 198 help
203 This enables support for systems based on the Hynix HMS720x 199 This enables support for systems based on the Hynix HMS720x
204 200
201config ARCH_AAEC2000
202 bool "Agilent AAEC-2000 based"
203 help
204 This enables support for systems based on the Agilent AAEC-2000
205
205endchoice 206endchoice
206 207
207source "arch/arm/mach-clps711x/Kconfig" 208source "arch/arm/mach-clps711x/Kconfig"
@@ -234,6 +235,8 @@ source "arch/arm/mach-h720x/Kconfig"
234 235
235source "arch/arm/mach-versatile/Kconfig" 236source "arch/arm/mach-versatile/Kconfig"
236 237
238source "arch/arm/mach-aaec2000/Kconfig"
239
237# Definitions to make life easier 240# Definitions to make life easier
238config ARCH_ACORN 241config ARCH_ACORN
239 bool 242 bool
@@ -277,7 +280,7 @@ config ISA_DMA_API
277 default y 280 default y
278 281
279config PCI 282config PCI
280 bool "PCI support" if ARCH_INTEGRATOR_AP 283 bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB
281 help 284 help
282 Find out whether you have a PCI motherboard. PCI is the name of a 285 Find out whether you have a PCI motherboard. PCI is the name of a
283 bus system, i.e. the way the CPU talks to the other stuff inside 286 bus system, i.e. the way the CPU talks to the other stuff inside
@@ -497,7 +500,7 @@ source "drivers/cpufreq/Kconfig"
497 500
498config CPU_FREQ_SA1100 501config CPU_FREQ_SA1100
499 bool 502 bool
500 depends on CPU_FREQ && (SA1100_LART || SA1100_PLEB) 503 depends on CPU_FREQ && (SA1100_H3100 || SA1100_H3600 || SA1100_H3800 || SA1100_LART || SA1100_PLEB || SA1100_BADGE4 || SA1100_HACKKIT)
501 default y 504 default y
502 505
503config CPU_FREQ_SA1110 506config CPU_FREQ_SA1110
@@ -689,7 +692,9 @@ source "drivers/block/Kconfig"
689 692
690source "drivers/acorn/block/Kconfig" 693source "drivers/acorn/block/Kconfig"
691 694
692if ARCH_CLPS7500 || ARCH_IOP3XX || ARCH_IXP4XX || ARCH_L7200 || ARCH_LH7A40X || ARCH_PXA || ARCH_RPC || ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE 695if PCMCIA || ARCH_CLPS7500 || ARCH_IOP3XX || ARCH_IXP4XX \
696 || ARCH_L7200 || ARCH_LH7A40X || ARCH_PXA || ARCH_RPC \
697 || ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE
693source "drivers/ide/Kconfig" 698source "drivers/ide/Kconfig"
694endif 699endif
695 700
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 2277e3d179cc..8330495e2448 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -97,6 +97,7 @@ textaddr-$(CONFIG_ARCH_FORTUNET) := 0xc0008000
97 machine-$(CONFIG_ARCH_VERSATILE) := versatile 97 machine-$(CONFIG_ARCH_VERSATILE) := versatile
98 machine-$(CONFIG_ARCH_IMX) := imx 98 machine-$(CONFIG_ARCH_IMX) := imx
99 machine-$(CONFIG_ARCH_H720X) := h720x 99 machine-$(CONFIG_ARCH_H720X) := h720x
100 machine-$(CONFIG_ARCH_AAEC2000) := aaec2000
100 101
101ifeq ($(CONFIG_ARCH_EBSA110),y) 102ifeq ($(CONFIG_ARCH_EBSA110),y)
102# This is what happens if you forget the IOCS16 line. 103# This is what happens if you forget the IOCS16 line.
diff --git a/arch/arm/boot/compressed/head-xscale.S b/arch/arm/boot/compressed/head-xscale.S
index 665bd2c20743..d3fe2533907e 100644
--- a/arch/arm/boot/compressed/head-xscale.S
+++ b/arch/arm/boot/compressed/head-xscale.S
@@ -47,3 +47,10 @@ __XScale_start:
47 orr r7, r7, #(MACH_TYPE_GTWX5715 & 0xff00) 47 orr r7, r7, #(MACH_TYPE_GTWX5715 & 0xff00)
48#endif 48#endif
49 49
50#ifdef CONFIG_ARCH_IXP2000
51 mov r1, #-1
52 mov r0, #0xd6000000
53 str r1, [r0, #0x14]
54 str r1, [r0, #0x18]
55#endif
56
diff --git a/arch/arm/common/amba.c b/arch/arm/common/amba.c
index a0507f8c33fe..c6beb751f2a9 100644
--- a/arch/arm/common/amba.c
+++ b/arch/arm/common/amba.c
@@ -169,7 +169,7 @@ static void amba_device_release(struct device *dev)
169} 169}
170 170
171#define amba_attr(name,fmt,arg...) \ 171#define amba_attr(name,fmt,arg...) \
172static ssize_t show_##name(struct device *_dev, char *buf) \ 172static ssize_t show_##name(struct device *_dev, struct device_attribute *attr, char *buf) \
173{ \ 173{ \
174 struct amba_device *dev = to_amba_device(_dev); \ 174 struct amba_device *dev = to_amba_device(_dev); \
175 return sprintf(buf, fmt, arg); \ 175 return sprintf(buf, fmt, arg); \
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index 5797b1b100a1..9d63a01214eb 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -30,6 +30,8 @@
30#include <linux/dmapool.h> 30#include <linux/dmapool.h>
31#include <linux/list.h> 31#include <linux/list.h>
32 32
33#include <asm/cacheflush.h>
34
33#undef DEBUG 35#undef DEBUG
34 36
35#undef STATS 37#undef STATS
@@ -302,12 +304,24 @@ unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
302 304
303 DO_STATS ( device_info->bounce_count++ ); 305 DO_STATS ( device_info->bounce_count++ );
304 306
305 if ((dir == DMA_FROM_DEVICE) || 307 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) {
306 (dir == DMA_BIDIRECTIONAL)) { 308 unsigned long ptr;
309
307 dev_dbg(dev, 310 dev_dbg(dev,
308 "%s: copy back safe %p to unsafe %p size %d\n", 311 "%s: copy back safe %p to unsafe %p size %d\n",
309 __func__, buf->safe, buf->ptr, size); 312 __func__, buf->safe, buf->ptr, size);
310 memcpy(buf->ptr, buf->safe, size); 313 memcpy(buf->ptr, buf->safe, size);
314
315 /*
316 * DMA buffers must have the same cache properties
317 * as if they were really used for DMA - which means
318 * data must be written back to RAM. Note that
319 * we don't use dmac_flush_range() here for the
320 * bidirectional case because we know the cache
321 * lines will be coherent with the data written.
322 */
323 ptr = (unsigned long)buf->ptr;
324 dmac_clean_range(ptr, ptr + size);
311 } 325 }
312 free_safe_buffer(device_info, buf); 326 free_safe_buffer(device_info, buf);
313 } 327 }
diff --git a/arch/arm/common/sharpsl_param.c b/arch/arm/common/sharpsl_param.c
index c2c557a224c2..c94864c5b1af 100644
--- a/arch/arm/common/sharpsl_param.c
+++ b/arch/arm/common/sharpsl_param.c
@@ -22,7 +22,7 @@
22 * them early in the boot process, then pass them to the appropriate drivers. 22 * them early in the boot process, then pass them to the appropriate drivers.
23 * Not all devices use all paramaters but the format is common to all. 23 * Not all devices use all paramaters but the format is common to all.
24 */ 24 */
25#ifdef ARCH_SA1100 25#ifdef CONFIG_ARCH_SA1100
26#define PARAM_BASE 0xe8ffc000 26#define PARAM_BASE 0xe8ffc000
27#else 27#else
28#define PARAM_BASE 0xa0000a00 28#define PARAM_BASE 0xa0000a00
diff --git a/arch/arm/configs/badge4_defconfig b/arch/arm/configs/badge4_defconfig
index 2b4059d2f8e4..5d92af975d87 100644
--- a/arch/arm/configs/badge4_defconfig
+++ b/arch/arm/configs/badge4_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc1-bk2 3# Linux kernel version: 2.6.12-rc6-git3
4# Sat Mar 26 21:32:26 2005 4# Thu Jun 9 19:00:50 2005
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_MMU=y 7CONFIG_MMU=y
@@ -16,6 +16,7 @@ CONFIG_GENERIC_IOMAP=y
16CONFIG_EXPERIMENTAL=y 16CONFIG_EXPERIMENTAL=y
17CONFIG_CLEAN_COMPILE=y 17CONFIG_CLEAN_COMPILE=y
18CONFIG_BROKEN_ON_SMP=y 18CONFIG_BROKEN_ON_SMP=y
19CONFIG_INIT_ENV_ARG_LIMIT=32
19 20
20# 21#
21# General setup 22# General setup
@@ -34,6 +35,8 @@ CONFIG_EMBEDDED=y
34CONFIG_KALLSYMS=y 35CONFIG_KALLSYMS=y
35# CONFIG_KALLSYMS_ALL is not set 36# CONFIG_KALLSYMS_ALL is not set
36# CONFIG_KALLSYMS_EXTRA_PASS is not set 37# CONFIG_KALLSYMS_EXTRA_PASS is not set
38CONFIG_PRINTK=y
39CONFIG_BUG=y
37CONFIG_BASE_FULL=y 40CONFIG_BASE_FULL=y
38CONFIG_FUTEX=y 41CONFIG_FUTEX=y
39CONFIG_EPOLL=y 42CONFIG_EPOLL=y
@@ -109,7 +112,6 @@ CONFIG_CPU_ABRT_EV4=y
109CONFIG_CPU_CACHE_V4WB=y 112CONFIG_CPU_CACHE_V4WB=y
110CONFIG_CPU_CACHE_VIVT=y 113CONFIG_CPU_CACHE_VIVT=y
111CONFIG_CPU_TLB_V4WB=y 114CONFIG_CPU_TLB_V4WB=y
112CONFIG_CPU_MINICACHE=y
113 115
114# 116#
115# Processor Features 117# Processor Features
@@ -122,6 +124,7 @@ CONFIG_FORCE_MAX_ZONEORDER=9
122# Bus support 124# Bus support
123# 125#
124CONFIG_ISA=y 126CONFIG_ISA=y
127CONFIG_ISA_DMA_API=y
125 128
126# 129#
127# PCCARD (PCMCIA/CardBus) support 130# PCCARD (PCMCIA/CardBus) support
@@ -131,6 +134,7 @@ CONFIG_ISA=y
131# 134#
132# Kernel Features 135# Kernel Features
133# 136#
137# CONFIG_SMP is not set
134# CONFIG_PREEMPT is not set 138# CONFIG_PREEMPT is not set
135CONFIG_DISCONTIGMEM=y 139CONFIG_DISCONTIGMEM=y
136# CONFIG_LEDS is not set 140# CONFIG_LEDS is not set
@@ -152,12 +156,14 @@ CONFIG_CPU_FREQ_TABLE=y
152# CONFIG_CPU_FREQ_DEBUG is not set 156# CONFIG_CPU_FREQ_DEBUG is not set
153CONFIG_CPU_FREQ_STAT=y 157CONFIG_CPU_FREQ_STAT=y
154# CONFIG_CPU_FREQ_STAT_DETAILS is not set 158# CONFIG_CPU_FREQ_STAT_DETAILS is not set
155CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y 159# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
156# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set 160CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
157CONFIG_CPU_FREQ_GOV_PERFORMANCE=y 161CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
158# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set 162# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
159# CONFIG_CPU_FREQ_GOV_USERSPACE is not set 163CONFIG_CPU_FREQ_GOV_USERSPACE=y
160# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set 164# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
165# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
166CONFIG_CPU_FREQ_SA1100=y
161 167
162# 168#
163# Floating point emulation 169# Floating point emulation
@@ -294,7 +300,6 @@ CONFIG_PARPORT_NOT_PC=y
294# 300#
295# Block devices 301# Block devices
296# 302#
297# CONFIG_BLK_DEV_FD is not set
298# CONFIG_BLK_DEV_XD is not set 303# CONFIG_BLK_DEV_XD is not set
299# CONFIG_PARIDE is not set 304# CONFIG_PARIDE is not set
300# CONFIG_BLK_DEV_COW_COMMON is not set 305# CONFIG_BLK_DEV_COW_COMMON is not set
@@ -428,7 +433,6 @@ CONFIG_NET=y
428# 433#
429CONFIG_PACKET=y 434CONFIG_PACKET=y
430# CONFIG_PACKET_MMAP is not set 435# CONFIG_PACKET_MMAP is not set
431# CONFIG_NETLINK_DEV is not set
432CONFIG_UNIX=y 436CONFIG_UNIX=y
433# CONFIG_NET_KEY is not set 437# CONFIG_NET_KEY is not set
434CONFIG_INET=y 438CONFIG_INET=y
@@ -526,6 +530,7 @@ CONFIG_IRDA_ULTRA=y
526# CONFIG_SMC_IRCC_FIR is not set 530# CONFIG_SMC_IRCC_FIR is not set
527# CONFIG_ALI_FIR is not set 531# CONFIG_ALI_FIR is not set
528CONFIG_SA1100_FIR=y 532CONFIG_SA1100_FIR=y
533# CONFIG_VIA_FIR is not set
529CONFIG_BT=m 534CONFIG_BT=m
530CONFIG_BT_L2CAP=m 535CONFIG_BT_L2CAP=m
531# CONFIG_BT_SCO is not set 536# CONFIG_BT_SCO is not set
@@ -618,7 +623,6 @@ CONFIG_NET_WIRELESS=y
618# 623#
619# CONFIG_SERIO is not set 624# CONFIG_SERIO is not set
620# CONFIG_GAMEPORT is not set 625# CONFIG_GAMEPORT is not set
621CONFIG_SOUND_GAMEPORT=y
622 626
623# 627#
624# Character devices 628# Character devices
@@ -687,7 +691,6 @@ CONFIG_RTC=m
687# 691#
688# TPM devices 692# TPM devices
689# 693#
690# CONFIG_TCG_TPM is not set
691 694
692# 695#
693# I2C support 696# I2C support
@@ -736,6 +739,7 @@ CONFIG_I2C_ELEKTOR=m
736# CONFIG_SENSORS_LM85 is not set 739# CONFIG_SENSORS_LM85 is not set
737# CONFIG_SENSORS_LM87 is not set 740# CONFIG_SENSORS_LM87 is not set
738# CONFIG_SENSORS_LM90 is not set 741# CONFIG_SENSORS_LM90 is not set
742# CONFIG_SENSORS_LM92 is not set
739# CONFIG_SENSORS_MAX1619 is not set 743# CONFIG_SENSORS_MAX1619 is not set
740# CONFIG_SENSORS_PC87360 is not set 744# CONFIG_SENSORS_PC87360 is not set
741# CONFIG_SENSORS_SMSC47B397 is not set 745# CONFIG_SENSORS_SMSC47B397 is not set
@@ -747,6 +751,7 @@ CONFIG_I2C_ELEKTOR=m
747# 751#
748# Other I2C Chip support 752# Other I2C Chip support
749# 753#
754# CONFIG_SENSORS_DS1337 is not set
750# CONFIG_SENSORS_EEPROM is not set 755# CONFIG_SENSORS_EEPROM is not set
751# CONFIG_SENSORS_PCF8574 is not set 756# CONFIG_SENSORS_PCF8574 is not set
752# CONFIG_SENSORS_PCF8591 is not set 757# CONFIG_SENSORS_PCF8591 is not set
@@ -871,7 +876,6 @@ CONFIG_USB_PRINTER=m
871# 876#
872CONFIG_USB_STORAGE=y 877CONFIG_USB_STORAGE=y
873CONFIG_USB_STORAGE_DEBUG=y 878CONFIG_USB_STORAGE_DEBUG=y
874# CONFIG_USB_STORAGE_RW_DETECT is not set
875# CONFIG_USB_STORAGE_DATAFAB is not set 879# CONFIG_USB_STORAGE_DATAFAB is not set
876# CONFIG_USB_STORAGE_FREECOM is not set 880# CONFIG_USB_STORAGE_FREECOM is not set
877# CONFIG_USB_STORAGE_ISD200 is not set 881# CONFIG_USB_STORAGE_ISD200 is not set
@@ -954,9 +958,11 @@ CONFIG_USB_USS720=m
954# 958#
955CONFIG_USB_SERIAL=m 959CONFIG_USB_SERIAL=m
956CONFIG_USB_SERIAL_GENERIC=y 960CONFIG_USB_SERIAL_GENERIC=y
961# CONFIG_USB_SERIAL_AIRPRIME is not set
957CONFIG_USB_SERIAL_BELKIN=m 962CONFIG_USB_SERIAL_BELKIN=m
958CONFIG_USB_SERIAL_WHITEHEAT=m 963CONFIG_USB_SERIAL_WHITEHEAT=m
959CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m 964CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
965# CONFIG_USB_SERIAL_CP2101 is not set
960# CONFIG_USB_SERIAL_CYPRESS_M8 is not set 966# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
961CONFIG_USB_SERIAL_EMPEG=m 967CONFIG_USB_SERIAL_EMPEG=m
962CONFIG_USB_SERIAL_FTDI_SIO=m 968CONFIG_USB_SERIAL_FTDI_SIO=m
@@ -985,6 +991,7 @@ CONFIG_USB_SERIAL_KEYSPAN=m
985# CONFIG_USB_SERIAL_KOBIL_SCT is not set 991# CONFIG_USB_SERIAL_KOBIL_SCT is not set
986CONFIG_USB_SERIAL_MCT_U232=m 992CONFIG_USB_SERIAL_MCT_U232=m
987CONFIG_USB_SERIAL_PL2303=m 993CONFIG_USB_SERIAL_PL2303=m
994# CONFIG_USB_SERIAL_HP4X is not set
988# CONFIG_USB_SERIAL_SAFE is not set 995# CONFIG_USB_SERIAL_SAFE is not set
989# CONFIG_USB_SERIAL_TI is not set 996# CONFIG_USB_SERIAL_TI is not set
990CONFIG_USB_SERIAL_CYBERJACK=m 997CONFIG_USB_SERIAL_CYBERJACK=m
diff --git a/arch/arm/configs/enp2611_defconfig b/arch/arm/configs/enp2611_defconfig
index e8f9fccffe84..06fae4b62774 100644
--- a/arch/arm/configs/enp2611_defconfig
+++ b/arch/arm/configs/enp2611_defconfig
@@ -50,7 +50,13 @@ CONFIG_BASE_SMALL=0
50# 50#
51# Loadable module support 51# Loadable module support
52# 52#
53# CONFIG_MODULES is not set 53CONFIG_MODULES=y
54CONFIG_MODULE_UNLOAD=y
55# CONFIG_MODULE_FORCE_UNLOAD is not set
56CONFIG_OBSOLETE_MODPARM=y
57# CONFIG_MODVERSIONS is not set
58# CONFIG_MODULE_SRCVERSION_ALL is not set
59CONFIG_KMOD=y
54 60
55# 61#
56# System Type 62# System Type
diff --git a/arch/arm/configs/h3600_defconfig b/arch/arm/configs/h3600_defconfig
index b4e297dd54b2..b9de07de80fe 100644
--- a/arch/arm/configs/h3600_defconfig
+++ b/arch/arm/configs/h3600_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc1-bk2 3# Linux kernel version: 2.6.12-rc4
4# Mon Mar 28 00:02:26 2005 4# Thu Jun 9 01:59:03 2005
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_MMU=y 7CONFIG_MMU=y
@@ -16,6 +16,7 @@ CONFIG_GENERIC_IOMAP=y
16CONFIG_EXPERIMENTAL=y 16CONFIG_EXPERIMENTAL=y
17CONFIG_CLEAN_COMPILE=y 17CONFIG_CLEAN_COMPILE=y
18CONFIG_BROKEN_ON_SMP=y 18CONFIG_BROKEN_ON_SMP=y
19CONFIG_INIT_ENV_ARG_LIMIT=32
19 20
20# 21#
21# General setup 22# General setup
@@ -33,6 +34,8 @@ CONFIG_KOBJECT_UEVENT=y
33# CONFIG_EMBEDDED is not set 34# CONFIG_EMBEDDED is not set
34CONFIG_KALLSYMS=y 35CONFIG_KALLSYMS=y
35# CONFIG_KALLSYMS_EXTRA_PASS is not set 36# CONFIG_KALLSYMS_EXTRA_PASS is not set
37CONFIG_PRINTK=y
38CONFIG_BUG=y
36CONFIG_BASE_FULL=y 39CONFIG_BASE_FULL=y
37CONFIG_FUTEX=y 40CONFIG_FUTEX=y
38CONFIG_EPOLL=y 41CONFIG_EPOLL=y
@@ -120,6 +123,7 @@ CONFIG_CPU_MINICACHE=y
120# Bus support 123# Bus support
121# 124#
122CONFIG_ISA=y 125CONFIG_ISA=y
126CONFIG_ISA_DMA_API=y
123 127
124# 128#
125# PCCARD (PCMCIA/CardBus) support 129# PCCARD (PCMCIA/CardBus) support
@@ -138,6 +142,7 @@ CONFIG_PCMCIA_SA1100=y
138# 142#
139# Kernel Features 143# Kernel Features
140# 144#
145# CONFIG_SMP is not set
141# CONFIG_PREEMPT is not set 146# CONFIG_PREEMPT is not set
142CONFIG_DISCONTIGMEM=y 147CONFIG_DISCONTIGMEM=y
143# CONFIG_LEDS is not set 148# CONFIG_LEDS is not set
@@ -159,12 +164,13 @@ CONFIG_CPU_FREQ_TABLE=y
159# CONFIG_CPU_FREQ_DEBUG is not set 164# CONFIG_CPU_FREQ_DEBUG is not set
160CONFIG_CPU_FREQ_STAT=y 165CONFIG_CPU_FREQ_STAT=y
161# CONFIG_CPU_FREQ_STAT_DETAILS is not set 166# CONFIG_CPU_FREQ_STAT_DETAILS is not set
162CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y 167# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
163# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set 168CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
164CONFIG_CPU_FREQ_GOV_PERFORMANCE=y 169# CONFIG_CPU_FREQ_GOV_PERFORMANCE is not set
165# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set 170# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
166# CONFIG_CPU_FREQ_GOV_USERSPACE is not set 171CONFIG_CPU_FREQ_GOV_USERSPACE=y
167# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set 172# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
173CONFIG_CPU_FREQ_SA1100=y
168 174
169# 175#
170# Floating point emulation 176# Floating point emulation
@@ -298,7 +304,6 @@ CONFIG_MTD_SA1100=y
298# 304#
299# Block devices 305# Block devices
300# 306#
301# CONFIG_BLK_DEV_FD is not set
302# CONFIG_BLK_DEV_XD is not set 307# CONFIG_BLK_DEV_XD is not set
303# CONFIG_BLK_DEV_COW_COMMON is not set 308# CONFIG_BLK_DEV_COW_COMMON is not set
304CONFIG_BLK_DEV_LOOP=m 309CONFIG_BLK_DEV_LOOP=m
@@ -379,7 +384,6 @@ CONFIG_NET=y
379# Networking options 384# Networking options
380# 385#
381# CONFIG_PACKET is not set 386# CONFIG_PACKET is not set
382# CONFIG_NETLINK_DEV is not set
383CONFIG_UNIX=y 387CONFIG_UNIX=y
384# CONFIG_NET_KEY is not set 388# CONFIG_NET_KEY is not set
385CONFIG_INET=y 389CONFIG_INET=y
@@ -476,6 +480,7 @@ CONFIG_IRCOMM=m
476# CONFIG_SMC_IRCC_FIR is not set 480# CONFIG_SMC_IRCC_FIR is not set
477# CONFIG_ALI_FIR is not set 481# CONFIG_ALI_FIR is not set
478CONFIG_SA1100_FIR=m 482CONFIG_SA1100_FIR=m
483# CONFIG_VIA_FIR is not set
479# CONFIG_BT is not set 484# CONFIG_BT is not set
480CONFIG_NETDEVICES=y 485CONFIG_NETDEVICES=y
481# CONFIG_DUMMY is not set 486# CONFIG_DUMMY is not set
@@ -647,7 +652,6 @@ CONFIG_LEGACY_PTY_COUNT=256
647# 652#
648# TPM devices 653# TPM devices
649# 654#
650# CONFIG_TCG_TPM is not set
651 655
652# 656#
653# I2C support 657# I2C support
@@ -676,9 +680,11 @@ CONFIG_FB_CFB_FILLRECT=y
676CONFIG_FB_CFB_COPYAREA=y 680CONFIG_FB_CFB_COPYAREA=y
677CONFIG_FB_CFB_IMAGEBLIT=y 681CONFIG_FB_CFB_IMAGEBLIT=y
678CONFIG_FB_SOFT_CURSOR=y 682CONFIG_FB_SOFT_CURSOR=y
683# CONFIG_FB_MACMODES is not set
679# CONFIG_FB_MODE_HELPERS is not set 684# CONFIG_FB_MODE_HELPERS is not set
680# CONFIG_FB_TILEBLITTING is not set 685# CONFIG_FB_TILEBLITTING is not set
681CONFIG_FB_SA1100=y 686CONFIG_FB_SA1100=y
687# CONFIG_FB_S1D13XXX is not set
682# CONFIG_FB_VIRTUAL is not set 688# CONFIG_FB_VIRTUAL is not set
683 689
684# 690#
diff --git a/arch/arm/configs/hackkit_defconfig b/arch/arm/configs/hackkit_defconfig
index 6987c8c5ddb4..fb41a36a5a68 100644
--- a/arch/arm/configs/hackkit_defconfig
+++ b/arch/arm/configs/hackkit_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc1-bk2 3# Linux kernel version: 2.6.12-rc6-git3
4# Mon Mar 28 00:22:34 2005 4# Thu Jun 9 20:58:58 2005
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_MMU=y 7CONFIG_MMU=y
@@ -16,6 +16,7 @@ CONFIG_GENERIC_IOMAP=y
16CONFIG_EXPERIMENTAL=y 16CONFIG_EXPERIMENTAL=y
17CONFIG_CLEAN_COMPILE=y 17CONFIG_CLEAN_COMPILE=y
18CONFIG_BROKEN_ON_SMP=y 18CONFIG_BROKEN_ON_SMP=y
19CONFIG_INIT_ENV_ARG_LIMIT=32
19 20
20# 21#
21# General setup 22# General setup
@@ -34,6 +35,8 @@ CONFIG_KOBJECT_UEVENT=y
34CONFIG_KALLSYMS=y 35CONFIG_KALLSYMS=y
35# CONFIG_KALLSYMS_ALL is not set 36# CONFIG_KALLSYMS_ALL is not set
36# CONFIG_KALLSYMS_EXTRA_PASS is not set 37# CONFIG_KALLSYMS_EXTRA_PASS is not set
38CONFIG_PRINTK=y
39CONFIG_BUG=y
37CONFIG_BASE_FULL=y 40CONFIG_BASE_FULL=y
38CONFIG_FUTEX=y 41CONFIG_FUTEX=y
39CONFIG_EPOLL=y 42CONFIG_EPOLL=y
@@ -109,7 +112,6 @@ CONFIG_CPU_ABRT_EV4=y
109CONFIG_CPU_CACHE_V4WB=y 112CONFIG_CPU_CACHE_V4WB=y
110CONFIG_CPU_CACHE_VIVT=y 113CONFIG_CPU_CACHE_VIVT=y
111CONFIG_CPU_TLB_V4WB=y 114CONFIG_CPU_TLB_V4WB=y
112CONFIG_CPU_MINICACHE=y
113 115
114# 116#
115# Processor Features 117# Processor Features
@@ -119,6 +121,7 @@ CONFIG_CPU_MINICACHE=y
119# Bus support 121# Bus support
120# 122#
121CONFIG_ISA=y 123CONFIG_ISA=y
124CONFIG_ISA_DMA_API=y
122 125
123# 126#
124# PCCARD (PCMCIA/CardBus) support 127# PCCARD (PCMCIA/CardBus) support
@@ -128,6 +131,7 @@ CONFIG_ISA=y
128# 131#
129# Kernel Features 132# Kernel Features
130# 133#
134# CONFIG_SMP is not set
131# CONFIG_PREEMPT is not set 135# CONFIG_PREEMPT is not set
132CONFIG_DISCONTIGMEM=y 136CONFIG_DISCONTIGMEM=y
133CONFIG_LEDS=y 137CONFIG_LEDS=y
@@ -151,12 +155,14 @@ CONFIG_CPU_FREQ_TABLE=y
151# CONFIG_CPU_FREQ_DEBUG is not set 155# CONFIG_CPU_FREQ_DEBUG is not set
152CONFIG_CPU_FREQ_STAT=y 156CONFIG_CPU_FREQ_STAT=y
153# CONFIG_CPU_FREQ_STAT_DETAILS is not set 157# CONFIG_CPU_FREQ_STAT_DETAILS is not set
154CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y 158# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
155# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set 159CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
156CONFIG_CPU_FREQ_GOV_PERFORMANCE=y 160CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
157# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set 161# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
158# CONFIG_CPU_FREQ_GOV_USERSPACE is not set 162CONFIG_CPU_FREQ_GOV_USERSPACE=y
159# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set 163# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
164# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
165CONFIG_CPU_FREQ_SA1100=y
160 166
161# 167#
162# Floating point emulation 168# Floating point emulation
@@ -280,7 +286,6 @@ CONFIG_MTD_CFI_UTIL=y
280# 286#
281# Block devices 287# Block devices
282# 288#
283# CONFIG_BLK_DEV_FD is not set
284# CONFIG_BLK_DEV_XD is not set 289# CONFIG_BLK_DEV_XD is not set
285# CONFIG_BLK_DEV_COW_COMMON is not set 290# CONFIG_BLK_DEV_COW_COMMON is not set
286# CONFIG_BLK_DEV_LOOP is not set 291# CONFIG_BLK_DEV_LOOP is not set
@@ -338,7 +343,6 @@ CONFIG_NET=y
338# 343#
339CONFIG_PACKET=y 344CONFIG_PACKET=y
340# CONFIG_PACKET_MMAP is not set 345# CONFIG_PACKET_MMAP is not set
341# CONFIG_NETLINK_DEV is not set
342CONFIG_UNIX=y 346CONFIG_UNIX=y
343# CONFIG_NET_KEY is not set 347# CONFIG_NET_KEY is not set
344CONFIG_INET=y 348CONFIG_INET=y
@@ -484,7 +488,6 @@ CONFIG_SERIO=y
484CONFIG_SERIO_SERPORT=y 488CONFIG_SERIO_SERPORT=y
485# CONFIG_SERIO_RAW is not set 489# CONFIG_SERIO_RAW is not set
486# CONFIG_GAMEPORT is not set 490# CONFIG_GAMEPORT is not set
487CONFIG_SOUND_GAMEPORT=y
488 491
489# 492#
490# Character devices 493# Character devices
@@ -533,7 +536,6 @@ CONFIG_LEGACY_PTY_COUNT=256
533# 536#
534# TPM devices 537# TPM devices
535# 538#
536# CONFIG_TCG_TPM is not set
537 539
538# 540#
539# I2C support 541# I2C support
diff --git a/arch/arm/configs/ixdp2400_defconfig b/arch/arm/configs/ixdp2400_defconfig
index 4fd663ecbe39..810a450a55d2 100644
--- a/arch/arm/configs/ixdp2400_defconfig
+++ b/arch/arm/configs/ixdp2400_defconfig
@@ -50,7 +50,13 @@ CONFIG_BASE_SMALL=0
50# 50#
51# Loadable module support 51# Loadable module support
52# 52#
53# CONFIG_MODULES is not set 53CONFIG_MODULES=y
54CONFIG_MODULE_UNLOAD=y
55# CONFIG_MODULE_FORCE_UNLOAD is not set
56CONFIG_OBSOLETE_MODPARM=y
57# CONFIG_MODVERSIONS is not set
58# CONFIG_MODULE_SRCVERSION_ALL is not set
59CONFIG_KMOD=y
54 60
55# 61#
56# System Type 62# System Type
diff --git a/arch/arm/configs/ixdp2401_defconfig b/arch/arm/configs/ixdp2401_defconfig
index 6f51c98084a3..72e1b940e975 100644
--- a/arch/arm/configs/ixdp2401_defconfig
+++ b/arch/arm/configs/ixdp2401_defconfig
@@ -50,7 +50,13 @@ CONFIG_BASE_SMALL=0
50# 50#
51# Loadable module support 51# Loadable module support
52# 52#
53# CONFIG_MODULES is not set 53CONFIG_MODULES=y
54CONFIG_MODULE_UNLOAD=y
55# CONFIG_MODULE_FORCE_UNLOAD is not set
56CONFIG_OBSOLETE_MODPARM=y
57# CONFIG_MODVERSIONS is not set
58# CONFIG_MODULE_SRCVERSION_ALL is not set
59CONFIG_KMOD=y
54 60
55# 61#
56# System Type 62# System Type
diff --git a/arch/arm/configs/ixdp2800_defconfig b/arch/arm/configs/ixdp2800_defconfig
index 7be3521f91fc..1592e45f0278 100644
--- a/arch/arm/configs/ixdp2800_defconfig
+++ b/arch/arm/configs/ixdp2800_defconfig
@@ -50,7 +50,13 @@ CONFIG_BASE_SMALL=0
50# 50#
51# Loadable module support 51# Loadable module support
52# 52#
53# CONFIG_MODULES is not set 53CONFIG_MODULES=y
54CONFIG_MODULE_UNLOAD=y
55# CONFIG_MODULE_FORCE_UNLOAD is not set
56CONFIG_OBSOLETE_MODPARM=y
57# CONFIG_MODVERSIONS is not set
58# CONFIG_MODULE_SRCVERSION_ALL is not set
59CONFIG_KMOD=y
54 60
55# 61#
56# System Type 62# System Type
diff --git a/arch/arm/configs/ixdp2801_defconfig b/arch/arm/configs/ixdp2801_defconfig
index cd84a20f30f1..f1afe3d09ec6 100644
--- a/arch/arm/configs/ixdp2801_defconfig
+++ b/arch/arm/configs/ixdp2801_defconfig
@@ -50,7 +50,13 @@ CONFIG_BASE_SMALL=0
50# 50#
51# Loadable module support 51# Loadable module support
52# 52#
53# CONFIG_MODULES is not set 53CONFIG_MODULES=y
54CONFIG_MODULE_UNLOAD=y
55# CONFIG_MODULE_FORCE_UNLOAD is not set
56CONFIG_OBSOLETE_MODPARM=y
57# CONFIG_MODVERSIONS is not set
58# CONFIG_MODULE_SRCVERSION_ALL is not set
59CONFIG_KMOD=y
54 60
55# 61#
56# System Type 62# System Type
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 4a2af55e134b..3e1b0327e4d7 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -6,7 +6,7 @@ AFLAGS_head.o := -DTEXTADDR=$(TEXTADDR) -DDATAADDR=$(DATAADDR)
6 6
7# Object file lists. 7# Object file lists.
8 8
9obj-y := arch.o compat.o dma.o entry-armv.o entry-common.o irq.o \ 9obj-y := compat.o dma.o entry-armv.o entry-common.o irq.o \
10 process.o ptrace.o semaphore.o setup.o signal.o sys_arm.o \ 10 process.o ptrace.o semaphore.o setup.o signal.o sys_arm.o \
11 time.o traps.o 11 time.o traps.o
12 12
diff --git a/arch/arm/kernel/arch.c b/arch/arm/kernel/arch.c
deleted file mode 100644
index 4e02fbeb10a6..000000000000
--- a/arch/arm/kernel/arch.c
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * linux/arch/arm/kernel/arch.c
3 *
4 * Architecture specific fixups.
5 */
6#include <linux/config.h>
7#include <linux/init.h>
8#include <linux/types.h>
9
10#include <asm/elf.h>
11#include <asm/page.h>
12#include <asm/setup.h>
13#include <asm/mach/arch.h>
14
15unsigned int vram_size;
16
17#ifdef CONFIG_ARCH_ACORN
18
19unsigned int memc_ctrl_reg;
20unsigned int number_mfm_drives;
21
22static int __init parse_tag_acorn(const struct tag *tag)
23{
24 memc_ctrl_reg = tag->u.acorn.memc_control_reg;
25 number_mfm_drives = tag->u.acorn.adfsdrives;
26
27 switch (tag->u.acorn.vram_pages) {
28 case 512:
29 vram_size += PAGE_SIZE * 256;
30 case 256:
31 vram_size += PAGE_SIZE * 256;
32 default:
33 break;
34 }
35#if 0
36 if (vram_size) {
37 desc->video_start = 0x02000000;
38 desc->video_end = 0x02000000 + vram_size;
39 }
40#endif
41 return 0;
42}
43
44__tagtable(ATAG_ACORN, parse_tag_acorn);
45
46#endif
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c
index 3dc15b131f53..6540db691338 100644
--- a/arch/arm/kernel/ecard.c
+++ b/arch/arm/kernel/ecard.c
@@ -866,19 +866,19 @@ static struct expansion_card *__init ecard_alloc_card(int type, int slot)
866 return ec; 866 return ec;
867} 867}
868 868
869static ssize_t ecard_show_irq(struct device *dev, char *buf) 869static ssize_t ecard_show_irq(struct device *dev, struct device_attribute *attr, char *buf)
870{ 870{
871 struct expansion_card *ec = ECARD_DEV(dev); 871 struct expansion_card *ec = ECARD_DEV(dev);
872 return sprintf(buf, "%u\n", ec->irq); 872 return sprintf(buf, "%u\n", ec->irq);
873} 873}
874 874
875static ssize_t ecard_show_dma(struct device *dev, char *buf) 875static ssize_t ecard_show_dma(struct device *dev, struct device_attribute *attr, char *buf)
876{ 876{
877 struct expansion_card *ec = ECARD_DEV(dev); 877 struct expansion_card *ec = ECARD_DEV(dev);
878 return sprintf(buf, "%u\n", ec->dma); 878 return sprintf(buf, "%u\n", ec->dma);
879} 879}
880 880
881static ssize_t ecard_show_resources(struct device *dev, char *buf) 881static ssize_t ecard_show_resources(struct device *dev, struct device_attribute *attr, char *buf)
882{ 882{
883 struct expansion_card *ec = ECARD_DEV(dev); 883 struct expansion_card *ec = ECARD_DEV(dev);
884 char *str = buf; 884 char *str = buf;
@@ -893,19 +893,19 @@ static ssize_t ecard_show_resources(struct device *dev, char *buf)
893 return str - buf; 893 return str - buf;
894} 894}
895 895
896static ssize_t ecard_show_vendor(struct device *dev, char *buf) 896static ssize_t ecard_show_vendor(struct device *dev, struct device_attribute *attr, char *buf)
897{ 897{
898 struct expansion_card *ec = ECARD_DEV(dev); 898 struct expansion_card *ec = ECARD_DEV(dev);
899 return sprintf(buf, "%u\n", ec->cid.manufacturer); 899 return sprintf(buf, "%u\n", ec->cid.manufacturer);
900} 900}
901 901
902static ssize_t ecard_show_device(struct device *dev, char *buf) 902static ssize_t ecard_show_device(struct device *dev, struct device_attribute *attr, char *buf)
903{ 903{
904 struct expansion_card *ec = ECARD_DEV(dev); 904 struct expansion_card *ec = ECARD_DEV(dev);
905 return sprintf(buf, "%u\n", ec->cid.product); 905 return sprintf(buf, "%u\n", ec->cid.product);
906} 906}
907 907
908static ssize_t ecard_show_type(struct device *dev, char *buf) 908static ssize_t ecard_show_type(struct device *dev, struct device_attribute *attr, char *buf)
909{ 909{
910 struct expansion_card *ec = ECARD_DEV(dev); 910 struct expansion_card *ec = ECARD_DEV(dev);
911 return sprintf(buf, "%s\n", ec->type == ECARD_EASI ? "EASI" : "IOC"); 911 return sprintf(buf, "%s\n", ec->type == ECARD_EASI ? "EASI" : "IOC");
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 4eb36155dc93..39a6c1b0b9a3 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -24,48 +24,91 @@
24#include "entry-header.S" 24#include "entry-header.S"
25 25
26/* 26/*
27 * Interrupt handling. Preserves r7, r8, r9
28 */
29 .macro irq_handler
301: get_irqnr_and_base r0, r6, r5, lr
31 movne r1, sp
32 @
33 @ routine called with r0 = irq number, r1 = struct pt_regs *
34 @
35 adrne lr, 1b
36 bne asm_do_IRQ
37
38#ifdef CONFIG_SMP
39 /*
40 * XXX
41 *
42 * this macro assumes that irqstat (r6) and base (r5) are
43 * preserved from get_irqnr_and_base above
44 */
45 test_for_ipi r0, r6, r5, lr
46 movne r0, sp
47 adrne lr, 1b
48 bne do_IPI
49#endif
50
51 .endm
52
53/*
27 * Invalid mode handlers 54 * Invalid mode handlers
28 */ 55 */
29 .macro inv_entry, sym, reason 56 .macro inv_entry, reason
30 sub sp, sp, #S_FRAME_SIZE @ Allocate frame size in one go 57 sub sp, sp, #S_FRAME_SIZE
31 stmia sp, {r0 - lr} @ Save XXX r0 - lr 58 stmib sp, {r1 - lr}
32 ldr r4, .LC\sym
33 mov r1, #\reason 59 mov r1, #\reason
34 .endm 60 .endm
35 61
36__pabt_invalid: 62__pabt_invalid:
37 inv_entry abt, BAD_PREFETCH 63 inv_entry BAD_PREFETCH
38 b 1f 64 b common_invalid
39 65
40__dabt_invalid: 66__dabt_invalid:
41 inv_entry abt, BAD_DATA 67 inv_entry BAD_DATA
42 b 1f 68 b common_invalid
43 69
44__irq_invalid: 70__irq_invalid:
45 inv_entry irq, BAD_IRQ 71 inv_entry BAD_IRQ
46 b 1f 72 b common_invalid
47 73
48__und_invalid: 74__und_invalid:
49 inv_entry und, BAD_UNDEFINSTR 75 inv_entry BAD_UNDEFINSTR
76
77 @
78 @ XXX fall through to common_invalid
79 @
80
81@
82@ common_invalid - generic code for failed exception (re-entrant version of handlers)
83@
84common_invalid:
85 zero_fp
86
87 ldmia r0, {r4 - r6}
88 add r0, sp, #S_PC @ here for interlock avoidance
89 mov r7, #-1 @ "" "" "" ""
90 str r4, [sp] @ save preserved r0
91 stmia r0, {r5 - r7} @ lr_<exception>,
92 @ cpsr_<exception>, "old_r0"
50 93
511: zero_fp
52 ldmia r4, {r5 - r7} @ Get XXX pc, cpsr, old_r0
53 add r4, sp, #S_PC
54 stmia r4, {r5 - r7} @ Save XXX pc, cpsr, old_r0
55 mov r0, sp 94 mov r0, sp
56 and r2, r6, #31 @ int mode 95 and r2, r6, #0x1f
57 b bad_mode 96 b bad_mode
58 97
59/* 98/*
60 * SVC mode handlers 99 * SVC mode handlers
61 */ 100 */
62 .macro svc_entry, sym 101 .macro svc_entry
63 sub sp, sp, #S_FRAME_SIZE 102 sub sp, sp, #S_FRAME_SIZE
64 stmia sp, {r0 - r12} @ save r0 - r12 103 stmib sp, {r1 - r12}
65 ldr r2, .LC\sym 104
66 add r0, sp, #S_FRAME_SIZE 105 ldmia r0, {r1 - r3}
67 ldmia r2, {r2 - r4} @ get pc, cpsr 106 add r5, sp, #S_SP @ here for interlock avoidance
68 add r5, sp, #S_SP 107 mov r4, #-1 @ "" "" "" ""
108 add r0, sp, #S_FRAME_SIZE @ "" "" "" ""
109 str r1, [sp] @ save the "real" r0 copied
110 @ from the exception stack
111
69 mov r1, lr 112 mov r1, lr
70 113
71 @ 114 @
@@ -82,7 +125,7 @@ __und_invalid:
82 125
83 .align 5 126 .align 5
84__dabt_svc: 127__dabt_svc:
85 svc_entry abt 128 svc_entry
86 129
87 @ 130 @
88 @ get ready to re-enable interrupts if appropriate 131 @ get ready to re-enable interrupts if appropriate
@@ -129,28 +172,24 @@ __dabt_svc:
129 172
130 .align 5 173 .align 5
131__irq_svc: 174__irq_svc:
132 svc_entry irq 175 svc_entry
176
133#ifdef CONFIG_PREEMPT 177#ifdef CONFIG_PREEMPT
134 get_thread_info r8 178 get_thread_info tsk
135 ldr r9, [r8, #TI_PREEMPT] @ get preempt count 179 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
136 add r7, r9, #1 @ increment it 180 add r7, r8, #1 @ increment it
137 str r7, [r8, #TI_PREEMPT] 181 str r7, [tsk, #TI_PREEMPT]
138#endif 182#endif
1391: get_irqnr_and_base r0, r6, r5, lr 183
140 movne r1, sp 184 irq_handler
141 @
142 @ routine called with r0 = irq number, r1 = struct pt_regs *
143 @
144 adrne lr, 1b
145 bne asm_do_IRQ
146#ifdef CONFIG_PREEMPT 185#ifdef CONFIG_PREEMPT
147 ldr r0, [r8, #TI_FLAGS] @ get flags 186 ldr r0, [tsk, #TI_FLAGS] @ get flags
148 tst r0, #_TIF_NEED_RESCHED 187 tst r0, #_TIF_NEED_RESCHED
149 blne svc_preempt 188 blne svc_preempt
150preempt_return: 189preempt_return:
151 ldr r0, [r8, #TI_PREEMPT] @ read preempt value 190 ldr r0, [tsk, #TI_PREEMPT] @ read preempt value
191 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
152 teq r0, r7 192 teq r0, r7
153 str r9, [r8, #TI_PREEMPT] @ restore preempt count
154 strne r0, [r0, -r0] @ bug() 193 strne r0, [r0, -r0] @ bug()
155#endif 194#endif
156 ldr r0, [sp, #S_PSR] @ irqs are already disabled 195 ldr r0, [sp, #S_PSR] @ irqs are already disabled
@@ -161,7 +200,7 @@ preempt_return:
161 200
162#ifdef CONFIG_PREEMPT 201#ifdef CONFIG_PREEMPT
163svc_preempt: 202svc_preempt:
164 teq r9, #0 @ was preempt count = 0 203 teq r8, #0 @ was preempt count = 0
165 ldreq r6, .LCirq_stat 204 ldreq r6, .LCirq_stat
166 movne pc, lr @ no 205 movne pc, lr @ no
167 ldr r0, [r6, #4] @ local_irq_count 206 ldr r0, [r6, #4] @ local_irq_count
@@ -169,9 +208,9 @@ svc_preempt:
169 adds r0, r0, r1 208 adds r0, r0, r1
170 movne pc, lr 209 movne pc, lr
171 mov r7, #0 @ preempt_schedule_irq 210 mov r7, #0 @ preempt_schedule_irq
172 str r7, [r8, #TI_PREEMPT] @ expects preempt_count == 0 211 str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0
1731: bl preempt_schedule_irq @ irq en/disable is done inside 2121: bl preempt_schedule_irq @ irq en/disable is done inside
174 ldr r0, [r8, #TI_FLAGS] @ get new tasks TI_FLAGS 213 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
175 tst r0, #_TIF_NEED_RESCHED 214 tst r0, #_TIF_NEED_RESCHED
176 beq preempt_return @ go again 215 beq preempt_return @ go again
177 b 1b 216 b 1b
@@ -179,7 +218,7 @@ svc_preempt:
179 218
180 .align 5 219 .align 5
181__und_svc: 220__und_svc:
182 svc_entry und 221 svc_entry
183 222
184 @ 223 @
185 @ call emulation code, which returns using r9 if it has emulated 224 @ call emulation code, which returns using r9 if it has emulated
@@ -209,7 +248,7 @@ __und_svc:
209 248
210 .align 5 249 .align 5
211__pabt_svc: 250__pabt_svc:
212 svc_entry abt 251 svc_entry
213 252
214 @ 253 @
215 @ re-enable interrupts if appropriate 254 @ re-enable interrupts if appropriate
@@ -242,12 +281,8 @@ __pabt_svc:
242 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr 281 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
243 282
244 .align 5 283 .align 5
245.LCirq: 284.LCcralign:
246 .word __temp_irq 285 .word cr_alignment
247.LCund:
248 .word __temp_und
249.LCabt:
250 .word __temp_abt
251#ifdef MULTI_ABORT 286#ifdef MULTI_ABORT
252.LCprocfns: 287.LCprocfns:
253 .word processor 288 .word processor
@@ -262,14 +297,18 @@ __pabt_svc:
262/* 297/*
263 * User mode handlers 298 * User mode handlers
264 */ 299 */
265 .macro usr_entry, sym 300 .macro usr_entry
266 sub sp, sp, #S_FRAME_SIZE @ Allocate frame size in one go 301 sub sp, sp, #S_FRAME_SIZE
267 stmia sp, {r0 - r12} @ save r0 - r12 302 stmib sp, {r1 - r12}
268 ldr r7, .LC\sym 303
269 add r5, sp, #S_PC 304 ldmia r0, {r1 - r3}
270 ldmia r7, {r2 - r4} @ Get USR pc, cpsr 305 add r0, sp, #S_PC @ here for interlock avoidance
271 306 mov r4, #-1 @ "" "" "" ""
272#if __LINUX_ARM_ARCH__ < 6 307
308 str r1, [sp] @ save the "real" r0 copied
309 @ from the exception stack
310
311#if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
273 @ make sure our user space atomic helper is aborted 312 @ make sure our user space atomic helper is aborted
274 cmp r2, #VIRT_OFFSET 313 cmp r2, #VIRT_OFFSET
275 bichs r3, r3, #PSR_Z_BIT 314 bichs r3, r3, #PSR_Z_BIT
@@ -284,13 +323,13 @@ __pabt_svc:
284 @ 323 @
285 @ Also, separately save sp_usr and lr_usr 324 @ Also, separately save sp_usr and lr_usr
286 @ 325 @
287 stmia r5, {r2 - r4} 326 stmia r0, {r2 - r4}
288 stmdb r5, {sp, lr}^ 327 stmdb r0, {sp, lr}^
289 328
290 @ 329 @
291 @ Enable the alignment trap while in kernel mode 330 @ Enable the alignment trap while in kernel mode
292 @ 331 @
293 alignment_trap r7, r0, __temp_\sym 332 alignment_trap r0
294 333
295 @ 334 @
296 @ Clear FP to mark the first stack frame 335 @ Clear FP to mark the first stack frame
@@ -300,7 +339,7 @@ __pabt_svc:
300 339
301 .align 5 340 .align 5
302__dabt_usr: 341__dabt_usr:
303 usr_entry abt 342 usr_entry
304 343
305 @ 344 @
306 @ Call the processor-specific abort handler: 345 @ Call the processor-specific abort handler:
@@ -329,30 +368,23 @@ __dabt_usr:
329 368
330 .align 5 369 .align 5
331__irq_usr: 370__irq_usr:
332 usr_entry irq 371 usr_entry
333 372
373 get_thread_info tsk
334#ifdef CONFIG_PREEMPT 374#ifdef CONFIG_PREEMPT
335 get_thread_info r8 375 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
336 ldr r9, [r8, #TI_PREEMPT] @ get preempt count 376 add r7, r8, #1 @ increment it
337 add r7, r9, #1 @ increment it 377 str r7, [tsk, #TI_PREEMPT]
338 str r7, [r8, #TI_PREEMPT]
339#endif 378#endif
3401: get_irqnr_and_base r0, r6, r5, lr 379
341 movne r1, sp 380 irq_handler
342 adrne lr, 1b
343 @
344 @ routine called with r0 = irq number, r1 = struct pt_regs *
345 @
346 bne asm_do_IRQ
347#ifdef CONFIG_PREEMPT 381#ifdef CONFIG_PREEMPT
348 ldr r0, [r8, #TI_PREEMPT] 382 ldr r0, [tsk, #TI_PREEMPT]
383 str r8, [tsk, #TI_PREEMPT]
349 teq r0, r7 384 teq r0, r7
350 str r9, [r8, #TI_PREEMPT]
351 strne r0, [r0, -r0] 385 strne r0, [r0, -r0]
352 mov tsk, r8
353#else
354 get_thread_info tsk
355#endif 386#endif
387
356 mov why, #0 388 mov why, #0
357 b ret_to_user 389 b ret_to_user
358 390
@@ -360,7 +392,7 @@ __irq_usr:
360 392
361 .align 5 393 .align 5
362__und_usr: 394__und_usr:
363 usr_entry und 395 usr_entry
364 396
365 tst r3, #PSR_T_BIT @ Thumb mode? 397 tst r3, #PSR_T_BIT @ Thumb mode?
366 bne fpundefinstr @ ignore FP 398 bne fpundefinstr @ ignore FP
@@ -476,7 +508,7 @@ fpundefinstr:
476 508
477 .align 5 509 .align 5
478__pabt_usr: 510__pabt_usr:
479 usr_entry abt 511 usr_entry
480 512
481 enable_irq @ Enable interrupts 513 enable_irq @ Enable interrupts
482 mov r0, r2 @ address (pc) 514 mov r0, r2 @ address (pc)
@@ -616,11 +648,17 @@ __kuser_helper_start:
616 648
617__kuser_cmpxchg: @ 0xffff0fc0 649__kuser_cmpxchg: @ 0xffff0fc0
618 650
619#if __LINUX_ARM_ARCH__ < 6 651#if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
620 652
621#ifdef CONFIG_SMP /* sanity check */ 653 /*
622#error "CONFIG_SMP on a machine supporting pre-ARMv6 processors?" 654 * Poor you. No fast solution possible...
623#endif 655 * The kernel itself must perform the operation.
656 * A special ghost syscall is used for that (see traps.c).
657 */
658 swi #0x9ffff0
659 mov pc, lr
660
661#elif __LINUX_ARM_ARCH__ < 6
624 662
625 /* 663 /*
626 * Theory of operation: 664 * Theory of operation:
@@ -735,29 +773,41 @@ __kuser_helper_end:
735 * 773 *
736 * Common stub entry macro: 774 * Common stub entry macro:
737 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 775 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
776 *
777 * SP points to a minimal amount of processor-private memory, the address
778 * of which is copied into r0 for the mode specific abort handler.
738 */ 779 */
739 .macro vector_stub, name, sym, correction=0 780 .macro vector_stub, name, correction=0
740 .align 5 781 .align 5
741 782
742vector_\name: 783vector_\name:
743 ldr r13, .LCs\sym
744 .if \correction 784 .if \correction
745 sub lr, lr, #\correction 785 sub lr, lr, #\correction
746 .endif 786 .endif
747 str lr, [r13] @ save lr_IRQ 787
788 @
789 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
790 @ (parent CPSR)
791 @
792 stmia sp, {r0, lr} @ save r0, lr
748 mrs lr, spsr 793 mrs lr, spsr
749 str lr, [r13, #4] @ save spsr_IRQ 794 str lr, [sp, #8] @ save spsr
795
750 @ 796 @
751 @ now branch to the relevant MODE handling routine 797 @ Prepare for SVC32 mode. IRQs remain disabled.
752 @ 798 @
753 mrs r13, cpsr 799 mrs r0, cpsr
754 bic r13, r13, #MODE_MASK 800 bic r0, r0, #MODE_MASK
755 orr r13, r13, #SVC_MODE 801 orr r0, r0, #SVC_MODE
756 msr spsr_cxsf, r13 @ switch to SVC_32 mode 802 msr spsr_cxsf, r0
757 803
758 and lr, lr, #15 804 @
805 @ the branch table must immediately follow this code
806 @
807 mov r0, sp
808 and lr, lr, #0x0f
759 ldr lr, [pc, lr, lsl #2] 809 ldr lr, [pc, lr, lsl #2]
760 movs pc, lr @ Changes mode and branches 810 movs pc, lr @ branch to handler in SVC mode
761 .endm 811 .endm
762 812
763 .globl __stubs_start 813 .globl __stubs_start
@@ -765,7 +815,7 @@ __stubs_start:
765/* 815/*
766 * Interrupt dispatcher 816 * Interrupt dispatcher
767 */ 817 */
768 vector_stub irq, irq, 4 818 vector_stub irq, 4
769 819
770 .long __irq_usr @ 0 (USR_26 / USR_32) 820 .long __irq_usr @ 0 (USR_26 / USR_32)
771 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) 821 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
@@ -788,7 +838,7 @@ __stubs_start:
788 * Data abort dispatcher 838 * Data abort dispatcher
789 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 839 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
790 */ 840 */
791 vector_stub dabt, abt, 8 841 vector_stub dabt, 8
792 842
793 .long __dabt_usr @ 0 (USR_26 / USR_32) 843 .long __dabt_usr @ 0 (USR_26 / USR_32)
794 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) 844 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
@@ -811,7 +861,7 @@ __stubs_start:
811 * Prefetch abort dispatcher 861 * Prefetch abort dispatcher
812 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC 862 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
813 */ 863 */
814 vector_stub pabt, abt, 4 864 vector_stub pabt, 4
815 865
816 .long __pabt_usr @ 0 (USR_26 / USR_32) 866 .long __pabt_usr @ 0 (USR_26 / USR_32)
817 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) 867 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
@@ -834,7 +884,7 @@ __stubs_start:
834 * Undef instr entry dispatcher 884 * Undef instr entry dispatcher
835 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC 885 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
836 */ 886 */
837 vector_stub und, und 887 vector_stub und
838 888
839 .long __und_usr @ 0 (USR_26 / USR_32) 889 .long __und_usr @ 0 (USR_26 / USR_32)
840 .long __und_invalid @ 1 (FIQ_26 / FIQ_32) 890 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
@@ -888,13 +938,6 @@ vector_addrexcptn:
888.LCvswi: 938.LCvswi:
889 .word vector_swi 939 .word vector_swi
890 940
891.LCsirq:
892 .word __temp_irq
893.LCsund:
894 .word __temp_und
895.LCsabt:
896 .word __temp_abt
897
898 .globl __stubs_end 941 .globl __stubs_end
899__stubs_end: 942__stubs_end:
900 943
@@ -916,23 +959,6 @@ __vectors_end:
916 959
917 .data 960 .data
918 961
919/*
920 * Do not reorder these, and do not insert extra data between...
921 */
922
923__temp_irq:
924 .word 0 @ saved lr_irq
925 .word 0 @ saved spsr_irq
926 .word -1 @ old_r0
927__temp_und:
928 .word 0 @ Saved lr_und
929 .word 0 @ Saved spsr_und
930 .word -1 @ old_r0
931__temp_abt:
932 .word 0 @ Saved lr_abt
933 .word 0 @ Saved spsr_abt
934 .word -1 @ old_r0
935
936 .globl cr_alignment 962 .globl cr_alignment
937 .globl cr_no_alignment 963 .globl cr_no_alignment
938cr_alignment: 964cr_alignment:
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index a3d40a0e2b04..afef21273963 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -59,11 +59,10 @@
59 mov \rd, \rd, lsl #13 59 mov \rd, \rd, lsl #13
60 .endm 60 .endm
61 61
62 .macro alignment_trap, rbase, rtemp, sym 62 .macro alignment_trap, rtemp
63#ifdef CONFIG_ALIGNMENT_TRAP 63#ifdef CONFIG_ALIGNMENT_TRAP
64#define OFF_CR_ALIGNMENT(x) cr_alignment - x 64 ldr \rtemp, .LCcralign
65 65 ldr \rtemp, [\rtemp]
66 ldr \rtemp, [\rbase, #OFF_CR_ALIGNMENT(\sym)]
67 mcr p15, 0, \rtemp, c1, c0 66 mcr p15, 0, \rtemp, c1, c0
68#endif 67#endif
69 .endm 68 .endm
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 4733877296d4..bd4823c74645 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -2,6 +2,8 @@
2 * linux/arch/arm/kernel/head.S 2 * linux/arch/arm/kernel/head.S
3 * 3 *
4 * Copyright (C) 1994-2002 Russell King 4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (c) 2003 ARM Limited
6 * All Rights Reserved
5 * 7 *
6 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -165,6 +167,48 @@ __mmap_switched:
165 stmia r6, {r0, r4} @ Save control register values 167 stmia r6, {r0, r4} @ Save control register values
166 b start_kernel 168 b start_kernel
167 169
170#if defined(CONFIG_SMP)
171 .type secondary_startup, #function
172ENTRY(secondary_startup)
173 /*
174 * Common entry point for secondary CPUs.
175 *
176 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
177 * the processor type - there is no need to check the machine type
178 * as it has already been validated by the primary processor.
179 */
180 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
181 bl __lookup_processor_type
182 movs r10, r5 @ invalid processor?
183 moveq r0, #'p' @ yes, error 'p'
184 beq __error
185
186 /*
187 * Use the page tables supplied from __cpu_up.
188 */
189 adr r4, __secondary_data
190 ldmia r4, {r5, r6, r13} @ address to jump to after
191 sub r4, r4, r5 @ mmu has been enabled
192 ldr r4, [r6, r4] @ get secondary_data.pgdir
193 adr lr, __enable_mmu @ return address
194 add pc, r10, #12 @ initialise processor
195 @ (return control reg)
196
197 /*
198 * r6 = &secondary_data
199 */
200ENTRY(__secondary_switched)
201 ldr sp, [r6, #4] @ get secondary_data.stack
202 mov fp, #0
203 b secondary_start_kernel
204
205 .type __secondary_data, %object
206__secondary_data:
207 .long .
208 .long secondary_data
209 .long __secondary_switched
210#endif /* defined(CONFIG_SMP) */
211
168 212
169 213
170/* 214/*
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index c2a7da3ac0f1..9fed5fa194d9 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -92,6 +92,14 @@ struct cpu_user_fns cpu_user;
92struct cpu_cache_fns cpu_cache; 92struct cpu_cache_fns cpu_cache;
93#endif 93#endif
94 94
95struct stack {
96 u32 irq[3];
97 u32 abt[3];
98 u32 und[3];
99} ____cacheline_aligned;
100
101static struct stack stacks[NR_CPUS];
102
95char elf_platform[ELF_PLATFORM_SIZE]; 103char elf_platform[ELF_PLATFORM_SIZE];
96EXPORT_SYMBOL(elf_platform); 104EXPORT_SYMBOL(elf_platform);
97 105
@@ -307,8 +315,6 @@ static void __init setup_processor(void)
307 cpu_name, processor_id, (int)processor_id & 15, 315 cpu_name, processor_id, (int)processor_id & 15,
308 proc_arch[cpu_architecture()]); 316 proc_arch[cpu_architecture()]);
309 317
310 dump_cpu_info(smp_processor_id());
311
312 sprintf(system_utsname.machine, "%s%c", list->arch_name, ENDIANNESS); 318 sprintf(system_utsname.machine, "%s%c", list->arch_name, ENDIANNESS);
313 sprintf(elf_platform, "%s%c", list->elf_name, ENDIANNESS); 319 sprintf(elf_platform, "%s%c", list->elf_name, ENDIANNESS);
314 elf_hwcap = list->elf_hwcap; 320 elf_hwcap = list->elf_hwcap;
@@ -316,6 +322,46 @@ static void __init setup_processor(void)
316 cpu_proc_init(); 322 cpu_proc_init();
317} 323}
318 324
325/*
326 * cpu_init - initialise one CPU.
327 *
328 * cpu_init dumps the cache information, initialises SMP specific
329 * information, and sets up the per-CPU stacks.
330 */
331void cpu_init(void)
332{
333 unsigned int cpu = smp_processor_id();
334 struct stack *stk = &stacks[cpu];
335
336 if (cpu >= NR_CPUS) {
337 printk(KERN_CRIT "CPU%u: bad primary CPU number\n", cpu);
338 BUG();
339 }
340
341 dump_cpu_info(cpu);
342
343 /*
344 * setup stacks for re-entrant exception handlers
345 */
346 __asm__ (
347 "msr cpsr_c, %1\n\t"
348 "add sp, %0, %2\n\t"
349 "msr cpsr_c, %3\n\t"
350 "add sp, %0, %4\n\t"
351 "msr cpsr_c, %5\n\t"
352 "add sp, %0, %6\n\t"
353 "msr cpsr_c, %7"
354 :
355 : "r" (stk),
356 "I" (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
357 "I" (offsetof(struct stack, irq[0])),
358 "I" (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
359 "I" (offsetof(struct stack, abt[0])),
360 "I" (PSR_F_BIT | PSR_I_BIT | UND_MODE),
361 "I" (offsetof(struct stack, und[0])),
362 "I" (PSR_F_BIT | PSR_I_BIT | SVC_MODE));
363}
364
319static struct machine_desc * __init setup_machine(unsigned int nr) 365static struct machine_desc * __init setup_machine(unsigned int nr)
320{ 366{
321 struct machine_desc *list; 367 struct machine_desc *list;
@@ -715,6 +761,8 @@ void __init setup_arch(char **cmdline_p)
715 paging_init(&meminfo, mdesc); 761 paging_init(&meminfo, mdesc);
716 request_standard_resources(&meminfo, mdesc); 762 request_standard_resources(&meminfo, mdesc);
717 763
764 cpu_init();
765
718 /* 766 /*
719 * Set up various architecture-specific pointers 767 * Set up various architecture-specific pointers
720 */ 768 */
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index ecc8c3332408..34892758f098 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -24,6 +24,9 @@
24#include <asm/atomic.h> 24#include <asm/atomic.h>
25#include <asm/cacheflush.h> 25#include <asm/cacheflush.h>
26#include <asm/cpu.h> 26#include <asm/cpu.h>
27#include <asm/mmu_context.h>
28#include <asm/pgtable.h>
29#include <asm/pgalloc.h>
27#include <asm/processor.h> 30#include <asm/processor.h>
28#include <asm/tlbflush.h> 31#include <asm/tlbflush.h>
29#include <asm/ptrace.h> 32#include <asm/ptrace.h>
@@ -37,6 +40,13 @@ cpumask_t cpu_present_mask;
37cpumask_t cpu_online_map; 40cpumask_t cpu_online_map;
38 41
39/* 42/*
43 * as from 2.5, kernels no longer have an init_tasks structure
44 * so we need some other way of telling a new secondary core
45 * where to place its SVC stack
46 */
47struct secondary_data secondary_data;
48
49/*
40 * structures for inter-processor calls 50 * structures for inter-processor calls
41 * - A collection of single bit ipi messages. 51 * - A collection of single bit ipi messages.
42 */ 52 */
@@ -71,6 +81,8 @@ static DEFINE_SPINLOCK(smp_call_function_lock);
71int __init __cpu_up(unsigned int cpu) 81int __init __cpu_up(unsigned int cpu)
72{ 82{
73 struct task_struct *idle; 83 struct task_struct *idle;
84 pgd_t *pgd;
85 pmd_t *pmd;
74 int ret; 86 int ret;
75 87
76 /* 88 /*
@@ -84,11 +96,57 @@ int __init __cpu_up(unsigned int cpu)
84 } 96 }
85 97
86 /* 98 /*
99 * Allocate initial page tables to allow the new CPU to
100 * enable the MMU safely. This essentially means a set
101 * of our "standard" page tables, with the addition of
102 * a 1:1 mapping for the physical address of the kernel.
103 */
104 pgd = pgd_alloc(&init_mm);
105 pmd = pmd_offset(pgd, PHYS_OFFSET);
106 *pmd = __pmd((PHYS_OFFSET & PGDIR_MASK) |
107 PMD_TYPE_SECT | PMD_SECT_AP_WRITE);
108
109 /*
110 * We need to tell the secondary core where to find
111 * its stack and the page tables.
112 */
113 secondary_data.stack = (void *)idle->thread_info + THREAD_SIZE - 8;
114 secondary_data.pgdir = virt_to_phys(pgd);
115 wmb();
116
117 /*
87 * Now bring the CPU into our world. 118 * Now bring the CPU into our world.
88 */ 119 */
89 ret = boot_secondary(cpu, idle); 120 ret = boot_secondary(cpu, idle);
121 if (ret == 0) {
122 unsigned long timeout;
123
124 /*
125 * CPU was successfully started, wait for it
126 * to come online or time out.
127 */
128 timeout = jiffies + HZ;
129 while (time_before(jiffies, timeout)) {
130 if (cpu_online(cpu))
131 break;
132
133 udelay(10);
134 barrier();
135 }
136
137 if (!cpu_online(cpu))
138 ret = -EIO;
139 }
140
141 secondary_data.stack = 0;
142 secondary_data.pgdir = 0;
143
144 *pmd_offset(pgd, PHYS_OFFSET) = __pmd(0);
145 pgd_free(pgd);
146
90 if (ret) { 147 if (ret) {
91 printk(KERN_CRIT "cpu_up: processor %d failed to boot\n", cpu); 148 printk(KERN_CRIT "CPU%u: processor failed to boot\n", cpu);
149
92 /* 150 /*
93 * FIXME: We need to clean up the new idle thread. --rmk 151 * FIXME: We need to clean up the new idle thread. --rmk
94 */ 152 */
@@ -98,6 +156,56 @@ int __init __cpu_up(unsigned int cpu)
98} 156}
99 157
100/* 158/*
159 * This is the secondary CPU boot entry. We're using this CPUs
160 * idle thread stack, but a set of temporary page tables.
161 */
162asmlinkage void __init secondary_start_kernel(void)
163{
164 struct mm_struct *mm = &init_mm;
165 unsigned int cpu = smp_processor_id();
166
167 printk("CPU%u: Booted secondary processor\n", cpu);
168
169 /*
170 * All kernel threads share the same mm context; grab a
171 * reference and switch to it.
172 */
173 atomic_inc(&mm->mm_users);
174 atomic_inc(&mm->mm_count);
175 current->active_mm = mm;
176 cpu_set(cpu, mm->cpu_vm_mask);
177 cpu_switch_mm(mm->pgd, mm);
178 enter_lazy_tlb(mm, current);
179
180 cpu_init();
181
182 /*
183 * Give the platform a chance to do its own initialisation.
184 */
185 platform_secondary_init(cpu);
186
187 /*
188 * Enable local interrupts.
189 */
190 local_irq_enable();
191 local_fiq_enable();
192
193 calibrate_delay();
194
195 smp_store_cpu_info(cpu);
196
197 /*
198 * OK, now it's safe to let the boot CPU continue
199 */
200 cpu_set(cpu, cpu_online_map);
201
202 /*
203 * OK, it's off to the idle thread for us
204 */
205 cpu_idle();
206}
207
208/*
101 * Called by both boot and secondaries to move global data into 209 * Called by both boot and secondaries to move global data into
102 * per-processor storage. 210 * per-processor storage.
103 */ 211 */
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 14df16b983f4..45d2a032d890 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -464,6 +464,55 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
464#endif 464#endif
465 return 0; 465 return 0;
466 466
467#ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG
468 /*
469 * Atomically store r1 in *r2 if *r2 is equal to r0 for user space.
470 * Return zero in r0 if *MEM was changed or non-zero if no exchange
471 * happened. Also set the user C flag accordingly.
472 * If access permissions have to be fixed up then non-zero is
473 * returned and the operation has to be re-attempted.
474 *
475 * *NOTE*: This is a ghost syscall private to the kernel. Only the
476 * __kuser_cmpxchg code in entry-armv.S should be aware of its
477 * existence. Don't ever use this from user code.
478 */
479 case 0xfff0:
480 {
481 extern void do_DataAbort(unsigned long addr, unsigned int fsr,
482 struct pt_regs *regs);
483 unsigned long val;
484 unsigned long addr = regs->ARM_r2;
485 struct mm_struct *mm = current->mm;
486 pgd_t *pgd; pmd_t *pmd; pte_t *pte;
487
488 regs->ARM_cpsr &= ~PSR_C_BIT;
489 spin_lock(&mm->page_table_lock);
490 pgd = pgd_offset(mm, addr);
491 if (!pgd_present(*pgd))
492 goto bad_access;
493 pmd = pmd_offset(pgd, addr);
494 if (!pmd_present(*pmd))
495 goto bad_access;
496 pte = pte_offset_map(pmd, addr);
497 if (!pte_present(*pte) || !pte_write(*pte))
498 goto bad_access;
499 val = *(unsigned long *)addr;
500 val -= regs->ARM_r0;
501 if (val == 0) {
502 *(unsigned long *)addr = regs->ARM_r1;
503 regs->ARM_cpsr |= PSR_C_BIT;
504 }
505 spin_unlock(&mm->page_table_lock);
506 return val;
507
508 bad_access:
509 spin_unlock(&mm->page_table_lock);
510 /* simulate a read access fault */
511 do_DataAbort(addr, 15 + (1 << 11), regs);
512 return -1;
513 }
514#endif
515
467 default: 516 default:
468 /* Calls 9f00xx..9f07ff are defined to return -ENOSYS 517 /* Calls 9f00xx..9f07ff are defined to return -ENOSYS
469 if not implemented, rather than raising SIGILL. This 518 if not implemented, rather than raising SIGILL. This
diff --git a/arch/arm/lib/ashldi3.c b/arch/arm/lib/ashldi3.c
index 130f5a839669..b62875cfd8f8 100644
--- a/arch/arm/lib/ashldi3.c
+++ b/arch/arm/lib/ashldi3.c
@@ -31,31 +31,26 @@ Boston, MA 02111-1307, USA. */
31 31
32#include "gcclib.h" 32#include "gcclib.h"
33 33
34DItype 34s64 __ashldi3(s64 u, int b)
35__ashldi3 (DItype u, word_type b)
36{ 35{
37 DIunion w; 36 DIunion w;
38 word_type bm; 37 int bm;
39 DIunion uu; 38 DIunion uu;
40 39
41 if (b == 0) 40 if (b == 0)
42 return u; 41 return u;
43 42
44 uu.ll = u; 43 uu.ll = u;
45 44
46 bm = (sizeof (SItype) * BITS_PER_UNIT) - b; 45 bm = (sizeof(s32) * BITS_PER_UNIT) - b;
47 if (bm <= 0) 46 if (bm <= 0) {
48 { 47 w.s.low = 0;
49 w.s.low = 0; 48 w.s.high = (u32) uu.s.low << -bm;
50 w.s.high = (USItype)uu.s.low << -bm; 49 } else {
51 } 50 u32 carries = (u32) uu.s.low >> bm;
52 else 51 w.s.low = (u32) uu.s.low << b;
53 { 52 w.s.high = ((u32) uu.s.high << b) | carries;
54 USItype carries = (USItype)uu.s.low >> bm; 53 }
55 w.s.low = (USItype)uu.s.low << b; 54
56 w.s.high = ((USItype)uu.s.high << b) | carries; 55 return w.ll;
57 }
58
59 return w.ll;
60} 56}
61
diff --git a/arch/arm/lib/ashrdi3.c b/arch/arm/lib/ashrdi3.c
index 71625d218f8d..9a8600a7543f 100644
--- a/arch/arm/lib/ashrdi3.c
+++ b/arch/arm/lib/ashrdi3.c
@@ -31,31 +31,27 @@ Boston, MA 02111-1307, USA. */
31 31
32#include "gcclib.h" 32#include "gcclib.h"
33 33
34DItype 34s64 __ashrdi3(s64 u, int b)
35__ashrdi3 (DItype u, word_type b)
36{ 35{
37 DIunion w; 36 DIunion w;
38 word_type bm; 37 int bm;
39 DIunion uu; 38 DIunion uu;
40 39
41 if (b == 0) 40 if (b == 0)
42 return u; 41 return u;
43 42
44 uu.ll = u; 43 uu.ll = u;
45 44
46 bm = (sizeof (SItype) * BITS_PER_UNIT) - b; 45 bm = (sizeof(s32) * BITS_PER_UNIT) - b;
47 if (bm <= 0) 46 if (bm <= 0) {
48 { 47 /* w.s.high = 1..1 or 0..0 */
49 /* w.s.high = 1..1 or 0..0 */ 48 w.s.high = uu.s.high >> (sizeof(s32) * BITS_PER_UNIT - 1);
50 w.s.high = uu.s.high >> (sizeof (SItype) * BITS_PER_UNIT - 1); 49 w.s.low = uu.s.high >> -bm;
51 w.s.low = uu.s.high >> -bm; 50 } else {
52 } 51 u32 carries = (u32) uu.s.high << bm;
53 else 52 w.s.high = uu.s.high >> b;
54 { 53 w.s.low = ((u32) uu.s.low >> b) | carries;
55 USItype carries = (USItype)uu.s.high << bm; 54 }
56 w.s.high = uu.s.high >> b; 55
57 w.s.low = ((USItype)uu.s.low >> b) | carries; 56 return w.ll;
58 }
59
60 return w.ll;
61} 57}
diff --git a/arch/arm/lib/gcclib.h b/arch/arm/lib/gcclib.h
index 65314a3d9e27..8b6dcc656de7 100644
--- a/arch/arm/lib/gcclib.h
+++ b/arch/arm/lib/gcclib.h
@@ -1,25 +1,22 @@
1/* gcclib.h -- definitions for various functions 'borrowed' from gcc-2.95.3 */ 1/* gcclib.h -- definitions for various functions 'borrowed' from gcc-2.95.3 */
2/* I Molton 29/07/01 */ 2/* I Molton 29/07/01 */
3 3
4#define BITS_PER_UNIT 8 4#include <linux/types.h>
5#define SI_TYPE_SIZE (sizeof (SItype) * BITS_PER_UNIT)
6 5
7typedef unsigned int UQItype __attribute__ ((mode (QI))); 6#define BITS_PER_UNIT 8
8typedef int SItype __attribute__ ((mode (SI))); 7#define SI_TYPE_SIZE (sizeof(s32) * BITS_PER_UNIT)
9typedef unsigned int USItype __attribute__ ((mode (SI)));
10typedef int DItype __attribute__ ((mode (DI)));
11typedef int word_type __attribute__ ((mode (__word__)));
12typedef unsigned int UDItype __attribute__ ((mode (DI)));
13 8
14#ifdef __ARMEB__ 9#ifdef __ARMEB__
15 struct DIstruct {SItype high, low;}; 10struct DIstruct {
11 s32 high, low;
12};
16#else 13#else
17 struct DIstruct {SItype low, high;}; 14struct DIstruct {
15 s32 low, high;
16};
18#endif 17#endif
19 18
20typedef union 19typedef union {
21{ 20 struct DIstruct s;
22 struct DIstruct s; 21 s64 ll;
23 DItype ll;
24} DIunion; 22} DIunion;
25
diff --git a/arch/arm/lib/io-writesw-armv4.S b/arch/arm/lib/io-writesw-armv4.S
index 6d1d7c27806e..5e240e452af6 100644
--- a/arch/arm/lib/io-writesw-armv4.S
+++ b/arch/arm/lib/io-writesw-armv4.S
@@ -87,9 +87,9 @@ ENTRY(__raw_writesw)
87 subs r2, r2, #2 87 subs r2, r2, #2
88 orr ip, ip, r3, push_hbyte1 88 orr ip, ip, r3, push_hbyte1
89 strh ip, [r0] 89 strh ip, [r0]
90 bpl 2b 90 bpl 1b
91 91
923: tst r2, #1 92 tst r2, #1
932: movne ip, r3, lsr #8 933: movne ip, r3, lsr #8
94 strneh ip, [r0] 94 strneh ip, [r0]
95 mov pc, lr 95 mov pc, lr
diff --git a/arch/arm/lib/longlong.h b/arch/arm/lib/longlong.h
index 179eea4edc35..90ae647e4d76 100644
--- a/arch/arm/lib/longlong.h
+++ b/arch/arm/lib/longlong.h
@@ -26,18 +26,18 @@
26 26
27#define __BITS4 (SI_TYPE_SIZE / 4) 27#define __BITS4 (SI_TYPE_SIZE / 4)
28#define __ll_B (1L << (SI_TYPE_SIZE / 2)) 28#define __ll_B (1L << (SI_TYPE_SIZE / 2))
29#define __ll_lowpart(t) ((USItype) (t) % __ll_B) 29#define __ll_lowpart(t) ((u32) (t) % __ll_B)
30#define __ll_highpart(t) ((USItype) (t) / __ll_B) 30#define __ll_highpart(t) ((u32) (t) / __ll_B)
31 31
32/* Define auxiliary asm macros. 32/* Define auxiliary asm macros.
33 33
34 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) 34 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand)
35 multiplies two USItype integers MULTIPLER and MULTIPLICAND, 35 multiplies two u32 integers MULTIPLER and MULTIPLICAND,
36 and generates a two-part USItype product in HIGH_PROD and 36 and generates a two-part u32 product in HIGH_PROD and
37 LOW_PROD. 37 LOW_PROD.
38 38
39 2) __umulsidi3(a,b) multiplies two USItype integers A and B, 39 2) __umulsidi3(a,b) multiplies two u32 integers A and B,
40 and returns a UDItype product. This is just a variant of umul_ppmm. 40 and returns a u64 product. This is just a variant of umul_ppmm.
41 41
42 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator, 42 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
43 denominator) divides a two-word unsigned integer, composed by the 43 denominator) divides a two-word unsigned integer, composed by the
@@ -77,23 +77,23 @@
77#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ 77#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
78 __asm__ ("adds %1, %4, %5 \n\ 78 __asm__ ("adds %1, %4, %5 \n\
79 adc %0, %2, %3" \ 79 adc %0, %2, %3" \
80 : "=r" ((USItype) (sh)), \ 80 : "=r" ((u32) (sh)), \
81 "=&r" ((USItype) (sl)) \ 81 "=&r" ((u32) (sl)) \
82 : "%r" ((USItype) (ah)), \ 82 : "%r" ((u32) (ah)), \
83 "rI" ((USItype) (bh)), \ 83 "rI" ((u32) (bh)), \
84 "%r" ((USItype) (al)), \ 84 "%r" ((u32) (al)), \
85 "rI" ((USItype) (bl))) 85 "rI" ((u32) (bl)))
86#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ 86#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
87 __asm__ ("subs %1, %4, %5 \n\ 87 __asm__ ("subs %1, %4, %5 \n\
88 sbc %0, %2, %3" \ 88 sbc %0, %2, %3" \
89 : "=r" ((USItype) (sh)), \ 89 : "=r" ((u32) (sh)), \
90 "=&r" ((USItype) (sl)) \ 90 "=&r" ((u32) (sl)) \
91 : "r" ((USItype) (ah)), \ 91 : "r" ((u32) (ah)), \
92 "rI" ((USItype) (bh)), \ 92 "rI" ((u32) (bh)), \
93 "r" ((USItype) (al)), \ 93 "r" ((u32) (al)), \
94 "rI" ((USItype) (bl))) 94 "rI" ((u32) (bl)))
95#define umul_ppmm(xh, xl, a, b) \ 95#define umul_ppmm(xh, xl, a, b) \
96{register USItype __t0, __t1, __t2; \ 96{register u32 __t0, __t1, __t2; \
97 __asm__ ("%@ Inlined umul_ppmm \n\ 97 __asm__ ("%@ Inlined umul_ppmm \n\
98 mov %2, %5, lsr #16 \n\ 98 mov %2, %5, lsr #16 \n\
99 mov %0, %6, lsr #16 \n\ 99 mov %0, %6, lsr #16 \n\
@@ -107,14 +107,14 @@
107 addcs %0, %0, #65536 \n\ 107 addcs %0, %0, #65536 \n\
108 adds %1, %1, %3, lsl #16 \n\ 108 adds %1, %1, %3, lsl #16 \n\
109 adc %0, %0, %3, lsr #16" \ 109 adc %0, %0, %3, lsr #16" \
110 : "=&r" ((USItype) (xh)), \ 110 : "=&r" ((u32) (xh)), \
111 "=r" ((USItype) (xl)), \ 111 "=r" ((u32) (xl)), \
112 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \ 112 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
113 : "r" ((USItype) (a)), \ 113 : "r" ((u32) (a)), \
114 "r" ((USItype) (b)));} 114 "r" ((u32) (b)));}
115#define UMUL_TIME 20 115#define UMUL_TIME 20
116#define UDIV_TIME 100 116#define UDIV_TIME 100
117#endif /* __arm__ */ 117#endif /* __arm__ */
118 118
119#define __umulsidi3(u, v) \ 119#define __umulsidi3(u, v) \
120 ({DIunion __w; \ 120 ({DIunion __w; \
@@ -123,14 +123,14 @@
123 123
124#define __udiv_qrnnd_c(q, r, n1, n0, d) \ 124#define __udiv_qrnnd_c(q, r, n1, n0, d) \
125 do { \ 125 do { \
126 USItype __d1, __d0, __q1, __q0; \ 126 u32 __d1, __d0, __q1, __q0; \
127 USItype __r1, __r0, __m; \ 127 u32 __r1, __r0, __m; \
128 __d1 = __ll_highpart (d); \ 128 __d1 = __ll_highpart (d); \
129 __d0 = __ll_lowpart (d); \ 129 __d0 = __ll_lowpart (d); \
130 \ 130 \
131 __r1 = (n1) % __d1; \ 131 __r1 = (n1) % __d1; \
132 __q1 = (n1) / __d1; \ 132 __q1 = (n1) / __d1; \
133 __m = (USItype) __q1 * __d0; \ 133 __m = (u32) __q1 * __d0; \
134 __r1 = __r1 * __ll_B | __ll_highpart (n0); \ 134 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
135 if (__r1 < __m) \ 135 if (__r1 < __m) \
136 { \ 136 { \
@@ -143,7 +143,7 @@
143 \ 143 \
144 __r0 = __r1 % __d1; \ 144 __r0 = __r1 % __d1; \
145 __q0 = __r1 / __d1; \ 145 __q0 = __r1 / __d1; \
146 __m = (USItype) __q0 * __d0; \ 146 __m = (u32) __q0 * __d0; \
147 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \ 147 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
148 if (__r0 < __m) \ 148 if (__r0 < __m) \
149 { \ 149 { \
@@ -154,7 +154,7 @@
154 } \ 154 } \
155 __r0 -= __m; \ 155 __r0 -= __m; \
156 \ 156 \
157 (q) = (USItype) __q1 * __ll_B | __q0; \ 157 (q) = (u32) __q1 * __ll_B | __q0; \
158 (r) = __r0; \ 158 (r) = __r0; \
159 } while (0) 159 } while (0)
160 160
@@ -163,14 +163,14 @@
163 163
164#define count_leading_zeros(count, x) \ 164#define count_leading_zeros(count, x) \
165 do { \ 165 do { \
166 USItype __xr = (x); \ 166 u32 __xr = (x); \
167 USItype __a; \ 167 u32 __a; \
168 \ 168 \
169 if (SI_TYPE_SIZE <= 32) \ 169 if (SI_TYPE_SIZE <= 32) \
170 { \ 170 { \
171 __a = __xr < ((USItype)1<<2*__BITS4) \ 171 __a = __xr < ((u32)1<<2*__BITS4) \
172 ? (__xr < ((USItype)1<<__BITS4) ? 0 : __BITS4) \ 172 ? (__xr < ((u32)1<<__BITS4) ? 0 : __BITS4) \
173 : (__xr < ((USItype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \ 173 : (__xr < ((u32)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
174 } \ 174 } \
175 else \ 175 else \
176 { \ 176 { \
diff --git a/arch/arm/lib/lshrdi3.c b/arch/arm/lib/lshrdi3.c
index b666f1bad451..3681f49d2b6e 100644
--- a/arch/arm/lib/lshrdi3.c
+++ b/arch/arm/lib/lshrdi3.c
@@ -31,31 +31,26 @@ Boston, MA 02111-1307, USA. */
31 31
32#include "gcclib.h" 32#include "gcclib.h"
33 33
34DItype 34s64 __lshrdi3(s64 u, int b)
35__lshrdi3 (DItype u, word_type b)
36{ 35{
37 DIunion w; 36 DIunion w;
38 word_type bm; 37 int bm;
39 DIunion uu; 38 DIunion uu;
40 39
41 if (b == 0) 40 if (b == 0)
42 return u; 41 return u;
43 42
44 uu.ll = u; 43 uu.ll = u;
45 44
46 bm = (sizeof (SItype) * BITS_PER_UNIT) - b; 45 bm = (sizeof(s32) * BITS_PER_UNIT) - b;
47 if (bm <= 0) 46 if (bm <= 0) {
48 { 47 w.s.high = 0;
49 w.s.high = 0; 48 w.s.low = (u32) uu.s.high >> -bm;
50 w.s.low = (USItype)uu.s.high >> -bm; 49 } else {
51 } 50 u32 carries = (u32) uu.s.high << bm;
52 else 51 w.s.high = (u32) uu.s.high >> b;
53 { 52 w.s.low = ((u32) uu.s.low >> b) | carries;
54 USItype carries = (USItype)uu.s.high << bm; 53 }
55 w.s.high = (USItype)uu.s.high >> b; 54
56 w.s.low = ((USItype)uu.s.low >> b) | carries; 55 return w.ll;
57 }
58
59 return w.ll;
60} 56}
61
diff --git a/arch/arm/lib/muldi3.c b/arch/arm/lib/muldi3.c
index 44d611b1cfdb..0a3b93313f18 100644
--- a/arch/arm/lib/muldi3.c
+++ b/arch/arm/lib/muldi3.c
@@ -32,7 +32,7 @@ Boston, MA 02111-1307, USA. */
32#include "gcclib.h" 32#include "gcclib.h"
33 33
34#define umul_ppmm(xh, xl, a, b) \ 34#define umul_ppmm(xh, xl, a, b) \
35{register USItype __t0, __t1, __t2; \ 35{register u32 __t0, __t1, __t2; \
36 __asm__ ("%@ Inlined umul_ppmm \n\ 36 __asm__ ("%@ Inlined umul_ppmm \n\
37 mov %2, %5, lsr #16 \n\ 37 mov %2, %5, lsr #16 \n\
38 mov %0, %6, lsr #16 \n\ 38 mov %0, %6, lsr #16 \n\
@@ -46,32 +46,27 @@ Boston, MA 02111-1307, USA. */
46 addcs %0, %0, #65536 \n\ 46 addcs %0, %0, #65536 \n\
47 adds %1, %1, %3, lsl #16 \n\ 47 adds %1, %1, %3, lsl #16 \n\
48 adc %0, %0, %3, lsr #16" \ 48 adc %0, %0, %3, lsr #16" \
49 : "=&r" ((USItype) (xh)), \ 49 : "=&r" ((u32) (xh)), \
50 "=r" ((USItype) (xl)), \ 50 "=r" ((u32) (xl)), \
51 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \ 51 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
52 : "r" ((USItype) (a)), \ 52 : "r" ((u32) (a)), \
53 "r" ((USItype) (b)));} 53 "r" ((u32) (b)));}
54
55 54
56#define __umulsidi3(u, v) \ 55#define __umulsidi3(u, v) \
57 ({DIunion __w; \ 56 ({DIunion __w; \
58 umul_ppmm (__w.s.high, __w.s.low, u, v); \ 57 umul_ppmm (__w.s.high, __w.s.low, u, v); \
59 __w.ll; }) 58 __w.ll; })
60 59
61 60s64 __muldi3(s64 u, s64 v)
62DItype
63__muldi3 (DItype u, DItype v)
64{ 61{
65 DIunion w; 62 DIunion w;
66 DIunion uu, vv; 63 DIunion uu, vv;
67 64
68 uu.ll = u, 65 uu.ll = u, vv.ll = v;
69 vv.ll = v;
70 66
71 w.ll = __umulsidi3 (uu.s.low, vv.s.low); 67 w.ll = __umulsidi3(uu.s.low, vv.s.low);
72 w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high 68 w.s.high += ((u32) uu.s.low * (u32) vv.s.high
73 + (USItype) uu.s.high * (USItype) vv.s.low); 69 + (u32) uu.s.high * (u32) vv.s.low);
74 70
75 return w.ll; 71 return w.ll;
76} 72}
77
diff --git a/arch/arm/lib/ucmpdi2.c b/arch/arm/lib/ucmpdi2.c
index 6c6ae63efa02..57f3f2df3850 100644
--- a/arch/arm/lib/ucmpdi2.c
+++ b/arch/arm/lib/ucmpdi2.c
@@ -31,21 +31,19 @@ Boston, MA 02111-1307, USA. */
31 31
32#include "gcclib.h" 32#include "gcclib.h"
33 33
34word_type 34int __ucmpdi2(s64 a, s64 b)
35__ucmpdi2 (DItype a, DItype b)
36{ 35{
37 DIunion au, bu; 36 DIunion au, bu;
38 37
39 au.ll = a, bu.ll = b; 38 au.ll = a, bu.ll = b;
40 39
41 if ((USItype) au.s.high < (USItype) bu.s.high) 40 if ((u32) au.s.high < (u32) bu.s.high)
42 return 0; 41 return 0;
43 else if ((USItype) au.s.high > (USItype) bu.s.high) 42 else if ((u32) au.s.high > (u32) bu.s.high)
44 return 2; 43 return 2;
45 if ((USItype) au.s.low < (USItype) bu.s.low) 44 if ((u32) au.s.low < (u32) bu.s.low)
46 return 0; 45 return 0;
47 else if ((USItype) au.s.low > (USItype) bu.s.low) 46 else if ((u32) au.s.low > (u32) bu.s.low)
48 return 2; 47 return 2;
49 return 1; 48 return 1;
50} 49}
51
diff --git a/arch/arm/lib/udivdi3.c b/arch/arm/lib/udivdi3.c
index d25195f673f4..e343be4c6642 100644
--- a/arch/arm/lib/udivdi3.c
+++ b/arch/arm/lib/udivdi3.c
@@ -32,211 +32,191 @@ Boston, MA 02111-1307, USA. */
32#include "gcclib.h" 32#include "gcclib.h"
33#include "longlong.h" 33#include "longlong.h"
34 34
35static const UQItype __clz_tab[] = 35static const u8 __clz_tab[] = {
36{ 36 0, 1, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 5, 5, 5,
37 0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5, 37 5, 5, 5, 5, 5, 5, 5, 5,
38 6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6, 38 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,
39 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7, 39 6, 6, 6, 6, 6, 6, 6, 6,
40 7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7, 40 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
41 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 41 7, 7, 7, 7, 7, 7, 7, 7,
42 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 42 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
43 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 43 7, 7, 7, 7, 7, 7, 7, 7,
44 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8, 44 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
45 8, 8, 8, 8, 8, 8, 8, 8,
46 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
47 8, 8, 8, 8, 8, 8, 8, 8,
48 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
49 8, 8, 8, 8, 8, 8, 8, 8,
50 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
51 8, 8, 8, 8, 8, 8, 8, 8,
45}; 52};
46 53
47UDItype 54u64 __udivmoddi4(u64 n, u64 d, u64 * rp)
48__udivmoddi4 (UDItype n, UDItype d, UDItype *rp)
49{ 55{
50 DIunion ww; 56 DIunion ww;
51 DIunion nn, dd; 57 DIunion nn, dd;
52 DIunion rr; 58 DIunion rr;
53 USItype d0, d1, n0, n1, n2; 59 u32 d0, d1, n0, n1, n2;
54 USItype q0, q1; 60 u32 q0, q1;
55 USItype b, bm; 61 u32 b, bm;
56 62
57 nn.ll = n; 63 nn.ll = n;
58 dd.ll = d; 64 dd.ll = d;
59 65
60 d0 = dd.s.low; 66 d0 = dd.s.low;
61 d1 = dd.s.high; 67 d1 = dd.s.high;
62 n0 = nn.s.low; 68 n0 = nn.s.low;
63 n1 = nn.s.high; 69 n1 = nn.s.high;
64 70
65 if (d1 == 0) 71 if (d1 == 0) {
66 { 72 if (d0 > n1) {
67 if (d0 > n1) 73 /* 0q = nn / 0D */
68 { 74
69 /* 0q = nn / 0D */ 75 count_leading_zeros(bm, d0);
70 76
71 count_leading_zeros (bm, d0); 77 if (bm != 0) {
72 78 /* Normalize, i.e. make the most significant bit of the
73 if (bm != 0) 79 denominator set. */
74 { 80
75 /* Normalize, i.e. make the most significant bit of the 81 d0 = d0 << bm;
76 denominator set. */ 82 n1 = (n1 << bm) | (n0 >> (SI_TYPE_SIZE - bm));
77 83 n0 = n0 << bm;
78 d0 = d0 << bm; 84 }
79 n1 = (n1 << bm) | (n0 >> (SI_TYPE_SIZE - bm)); 85
80 n0 = n0 << bm; 86 udiv_qrnnd(q0, n0, n1, n0, d0);
81 } 87 q1 = 0;
82 88
83 udiv_qrnnd (q0, n0, n1, n0, d0); 89 /* Remainder in n0 >> bm. */
84 q1 = 0; 90 } else {
85 91 /* qq = NN / 0d */
86 /* Remainder in n0 >> bm. */ 92
87 } 93 if (d0 == 0)
88 else 94 d0 = 1 / d0; /* Divide intentionally by zero. */
89 { 95
90 /* qq = NN / 0d */ 96 count_leading_zeros(bm, d0);
91 97
92 if (d0 == 0) 98 if (bm == 0) {
93 d0 = 1 / d0; /* Divide intentionally by zero. */ 99 /* From (n1 >= d0) /\ (the most significant bit of d0 is set),
94 100 conclude (the most significant bit of n1 is set) /\ (the
95 count_leading_zeros (bm, d0); 101 leading quotient digit q1 = 1).
96 102
97 if (bm == 0) 103 This special case is necessary, not an optimization.
98 { 104 (Shifts counts of SI_TYPE_SIZE are undefined.) */
99 /* From (n1 >= d0) /\ (the most significant bit of d0 is set), 105
100 conclude (the most significant bit of n1 is set) /\ (the 106 n1 -= d0;
101 leading quotient digit q1 = 1). 107 q1 = 1;
102 108 } else {
103 This special case is necessary, not an optimization. 109 /* Normalize. */
104 (Shifts counts of SI_TYPE_SIZE are undefined.) */ 110
105 111 b = SI_TYPE_SIZE - bm;
106 n1 -= d0; 112
107 q1 = 1; 113 d0 = d0 << bm;
108 } 114 n2 = n1 >> b;
109 else 115 n1 = (n1 << bm) | (n0 >> b);
110 { 116 n0 = n0 << bm;
111 /* Normalize. */ 117
112 118 udiv_qrnnd(q1, n1, n2, n1, d0);
113 b = SI_TYPE_SIZE - bm; 119 }
114 120
115 d0 = d0 << bm; 121 /* n1 != d0... */
116 n2 = n1 >> b; 122
117 n1 = (n1 << bm) | (n0 >> b); 123 udiv_qrnnd(q0, n0, n1, n0, d0);
118 n0 = n0 << bm; 124
119 125 /* Remainder in n0 >> bm. */
120 udiv_qrnnd (q1, n1, n2, n1, d0); 126 }
121 } 127
122 128 if (rp != 0) {
123 /* n1 != d0... */ 129 rr.s.low = n0 >> bm;
124 130 rr.s.high = 0;
125 udiv_qrnnd (q0, n0, n1, n0, d0); 131 *rp = rr.ll;
126 132 }
127 /* Remainder in n0 >> bm. */ 133 } else {
128 } 134 if (d1 > n1) {
129 135 /* 00 = nn / DD */
130 if (rp != 0) 136
131 { 137 q0 = 0;
132 rr.s.low = n0 >> bm; 138 q1 = 0;
133 rr.s.high = 0; 139
134 *rp = rr.ll; 140 /* Remainder in n1n0. */
135 } 141 if (rp != 0) {
136 } 142 rr.s.low = n0;
137 else 143 rr.s.high = n1;
138 { 144 *rp = rr.ll;
139 if (d1 > n1) 145 }
140 { 146 } else {
141 /* 00 = nn / DD */ 147 /* 0q = NN / dd */
142 148
143 q0 = 0; 149 count_leading_zeros(bm, d1);
144 q1 = 0; 150 if (bm == 0) {
145 151 /* From (n1 >= d1) /\ (the most significant bit of d1 is set),
146 /* Remainder in n1n0. */ 152 conclude (the most significant bit of n1 is set) /\ (the
147 if (rp != 0) 153 quotient digit q0 = 0 or 1).
148 { 154
149 rr.s.low = n0; 155 This special case is necessary, not an optimization. */
150 rr.s.high = n1; 156
151 *rp = rr.ll; 157 /* The condition on the next line takes advantage of that
152 } 158 n1 >= d1 (true due to program flow). */
153 } 159 if (n1 > d1 || n0 >= d0) {
154 else 160 q0 = 1;
155 { 161 sub_ddmmss(n1, n0, n1, n0, d1, d0);
156 /* 0q = NN / dd */ 162 } else
157 163 q0 = 0;
158 count_leading_zeros (bm, d1); 164
159 if (bm == 0) 165 q1 = 0;
160 { 166
161 /* From (n1 >= d1) /\ (the most significant bit of d1 is set), 167 if (rp != 0) {
162 conclude (the most significant bit of n1 is set) /\ (the 168 rr.s.low = n0;
163 quotient digit q0 = 0 or 1). 169 rr.s.high = n1;
164 170 *rp = rr.ll;
165 This special case is necessary, not an optimization. */ 171 }
166 172 } else {
167 /* The condition on the next line takes advantage of that 173 u32 m1, m0;
168 n1 >= d1 (true due to program flow). */ 174 /* Normalize. */
169 if (n1 > d1 || n0 >= d0) 175
170 { 176 b = SI_TYPE_SIZE - bm;
171 q0 = 1; 177
172 sub_ddmmss (n1, n0, n1, n0, d1, d0); 178 d1 = (d1 << bm) | (d0 >> b);
173 } 179 d0 = d0 << bm;
174 else 180 n2 = n1 >> b;
175 q0 = 0; 181 n1 = (n1 << bm) | (n0 >> b);
176 182 n0 = n0 << bm;
177 q1 = 0; 183
178 184 udiv_qrnnd(q0, n1, n2, n1, d1);
179 if (rp != 0) 185 umul_ppmm(m1, m0, q0, d0);
180 { 186
181 rr.s.low = n0; 187 if (m1 > n1 || (m1 == n1 && m0 > n0)) {
182 rr.s.high = n1; 188 q0--;
183 *rp = rr.ll; 189 sub_ddmmss(m1, m0, m1, m0, d1, d0);
184 } 190 }
185 } 191
186 else 192 q1 = 0;
187 { 193
188 USItype m1, m0; 194 /* Remainder in (n1n0 - m1m0) >> bm. */
189 /* Normalize. */ 195 if (rp != 0) {
190 196 sub_ddmmss(n1, n0, n1, n0, m1, m0);
191 b = SI_TYPE_SIZE - bm; 197 rr.s.low = (n1 << b) | (n0 >> bm);
192 198 rr.s.high = n1 >> bm;
193 d1 = (d1 << bm) | (d0 >> b); 199 *rp = rr.ll;
194 d0 = d0 << bm; 200 }
195 n2 = n1 >> b; 201 }
196 n1 = (n1 << bm) | (n0 >> b); 202 }
197 n0 = n0 << bm; 203 }
198 204
199 udiv_qrnnd (q0, n1, n2, n1, d1); 205 ww.s.low = q0;
200 umul_ppmm (m1, m0, q0, d0); 206 ww.s.high = q1;
201 207 return ww.ll;
202 if (m1 > n1 || (m1 == n1 && m0 > n0))
203 {
204 q0--;
205 sub_ddmmss (m1, m0, m1, m0, d1, d0);
206 }
207
208 q1 = 0;
209
210 /* Remainder in (n1n0 - m1m0) >> bm. */
211 if (rp != 0)
212 {
213 sub_ddmmss (n1, n0, n1, n0, m1, m0);
214 rr.s.low = (n1 << b) | (n0 >> bm);
215 rr.s.high = n1 >> bm;
216 *rp = rr.ll;
217 }
218 }
219 }
220 }
221
222 ww.s.low = q0;
223 ww.s.high = q1;
224 return ww.ll;
225} 208}
226 209
227UDItype 210u64 __udivdi3(u64 n, u64 d)
228__udivdi3 (UDItype n, UDItype d)
229{ 211{
230 return __udivmoddi4 (n, d, (UDItype *) 0); 212 return __udivmoddi4(n, d, (u64 *) 0);
231} 213}
232 214
233UDItype 215u64 __umoddi3(u64 u, u64 v)
234__umoddi3 (UDItype u, UDItype v)
235{ 216{
236 UDItype w; 217 u64 w;
237 218
238 (void) __udivmoddi4 (u ,v, &w); 219 (void)__udivmoddi4(u, v, &w);
239 220
240 return w; 221 return w;
241} 222}
242
diff --git a/arch/arm/mach-aaec2000/Kconfig b/arch/arm/mach-aaec2000/Kconfig
new file mode 100644
index 000000000000..5e4bef93754c
--- /dev/null
+++ b/arch/arm/mach-aaec2000/Kconfig
@@ -0,0 +1,11 @@
1if ARCH_AAEC2000
2
3menu "Agilent AAEC-2000 Implementations"
4
5config MACH_AAED2000
6 bool "Agilent AAED-2000 Development Platform"
7 select CPU_ARM920T
8
9endmenu
10
11endif
diff --git a/arch/arm/mach-aaec2000/Makefile b/arch/arm/mach-aaec2000/Makefile
new file mode 100644
index 000000000000..20ec83896c37
--- /dev/null
+++ b/arch/arm/mach-aaec2000/Makefile
@@ -0,0 +1,9 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Common support (must be linked before board specific support)
6obj-y += core.o
7
8# Specific board support
9obj-$(CONFIG_MACH_AAED2000) += aaed2000.o
diff --git a/arch/arm/mach-aaec2000/aaed2000.c b/arch/arm/mach-aaec2000/aaed2000.c
new file mode 100644
index 000000000000..5417ca3f4621
--- /dev/null
+++ b/arch/arm/mach-aaec2000/aaed2000.c
@@ -0,0 +1,48 @@
1/*
2 * linux/arch/arm/mach-aaec2000/aaed2000.c
3 *
4 * Support for the Agilent AAED-2000 Development Platform.
5 *
6 * Copyright (c) 2005 Nicolas Bellido Y Ortega
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/device.h>
17#include <linux/major.h>
18#include <linux/interrupt.h>
19
20#include <asm/setup.h>
21#include <asm/memory.h>
22#include <asm/mach-types.h>
23#include <asm/hardware.h>
24#include <asm/irq.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include "core.h"
31
32static void __init aaed2000_init_irq(void)
33{
34 aaec2000_init_irq();
35}
36
37static void __init aaed2000_map_io(void)
38{
39 aaec2000_map_io();
40}
41
42MACHINE_START(AAED2000, "Agilent AAED-2000 Development Platform")
43 MAINTAINER("Nicolas Bellido Y Ortega")
44 BOOT_MEM(0xf0000000, PIO_BASE, VIO_BASE)
45 MAPIO(aaed2000_map_io)
46 INITIRQ(aaed2000_init_irq)
47 .timer = &aaec2000_timer,
48MACHINE_END
diff --git a/arch/arm/mach-aaec2000/core.c b/arch/arm/mach-aaec2000/core.c
new file mode 100644
index 000000000000..fc145b3768fa
--- /dev/null
+++ b/arch/arm/mach-aaec2000/core.c
@@ -0,0 +1,157 @@
1/*
2 * linux/arch/arm/mach-aaec2000/core.c
3 *
4 * Code common to all AAEC-2000 machines
5 *
6 * Copyright (c) 2005 Nicolas Bellido Y Ortega
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/config.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/interrupt.h>
19#include <linux/timex.h>
20#include <linux/signal.h>
21
22#include <asm/hardware.h>
23#include <asm/irq.h>
24
25#include <asm/mach/irq.h>
26#include <asm/mach/time.h>
27#include <asm/mach/map.h>
28
29/*
30 * Common I/O mapping:
31 *
32 * Static virtual address mappings are as follow:
33 *
34 * 0xf8000000-0xf8001ffff: Devices connected to APB bus
35 * 0xf8002000-0xf8003ffff: Devices connected to AHB bus
36 *
37 * Below 0xe8000000 is reserved for vm allocation.
38 *
39 * The machine specific code must provide the extra mapping beside the
40 * default mapping provided here.
41 */
42static struct map_desc standard_io_desc[] __initdata = {
43 /* virtual physical length type */
44 { VIO_APB_BASE, PIO_APB_BASE, IO_APB_LENGTH, MT_DEVICE },
45 { VIO_AHB_BASE, PIO_AHB_BASE, IO_AHB_LENGTH, MT_DEVICE }
46};
47
48void __init aaec2000_map_io(void)
49{
50 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
51}
52
53/*
54 * Interrupt handling routines
55 */
56static void aaec2000_int_ack(unsigned int irq)
57{
58 IRQ_INTSR = 1 << irq;
59}
60
61static void aaec2000_int_mask(unsigned int irq)
62{
63 IRQ_INTENC |= (1 << irq);
64}
65
66static void aaec2000_int_unmask(unsigned int irq)
67{
68 IRQ_INTENS |= (1 << irq);
69}
70
71static struct irqchip aaec2000_irq_chip = {
72 .ack = aaec2000_int_ack,
73 .mask = aaec2000_int_mask,
74 .unmask = aaec2000_int_unmask,
75};
76
77void __init aaec2000_init_irq(void)
78{
79 unsigned int i;
80
81 for (i = 0; i < NR_IRQS; i++) {
82 set_irq_handler(i, do_level_IRQ);
83 set_irq_chip(i, &aaec2000_irq_chip);
84 set_irq_flags(i, IRQF_VALID);
85 }
86
87 /* Disable all interrupts */
88 IRQ_INTENC = 0xffffffff;
89
90 /* Clear any pending interrupts */
91 IRQ_INTSR = IRQ_INTSR;
92}
93
94/*
95 * Time keeping
96 */
97/* IRQs are disabled before entering here from do_gettimeofday() */
98static unsigned long aaec2000_gettimeoffset(void)
99{
100 unsigned long ticks_to_match, elapsed, usec;
101
102 /* Get ticks before next timer match */
103 ticks_to_match = TIMER1_LOAD - TIMER1_VAL;
104
105 /* We need elapsed ticks since last match */
106 elapsed = LATCH - ticks_to_match;
107
108 /* Now, convert them to usec */
109 usec = (unsigned long)(elapsed * (tick_nsec / 1000))/LATCH;
110
111 return usec;
112}
113
114/* We enter here with IRQs enabled */
115static irqreturn_t
116aaec2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
117{
118 /* TODO: Check timer accuracy */
119 write_seqlock(&xtime_lock);
120
121 timer_tick(regs);
122 TIMER1_CLEAR = 1;
123
124 write_sequnlock(&xtime_lock);
125
126 return IRQ_HANDLED;
127}
128
129static struct irqaction aaec2000_timer_irq = {
130 .name = "AAEC-2000 Timer Tick",
131 .flags = SA_INTERRUPT,
132 .handler = aaec2000_timer_interrupt
133};
134
135static void __init aaec2000_timer_init(void)
136{
137 /* Disable timer 1 */
138 TIMER1_CTRL = 0;
139
140 /* We have somehow to generate a 100Hz clock.
141 * We then use the 508KHz timer in periodic mode.
142 */
143 TIMER1_LOAD = LATCH;
144 TIMER1_CLEAR = 1; /* Clear interrupt */
145
146 setup_irq(INT_TMR1_OFL, &aaec2000_timer_irq);
147
148 TIMER1_CTRL = TIMER_CTRL_ENABLE |
149 TIMER_CTRL_PERIODIC |
150 TIMER_CTRL_CLKSEL_508K;
151}
152
153struct sys_timer aaec2000_timer = {
154 .init = aaec2000_timer_init,
155 .offset = aaec2000_gettimeoffset,
156};
157
diff --git a/arch/arm/mach-aaec2000/core.h b/arch/arm/mach-aaec2000/core.h
new file mode 100644
index 000000000000..91893d848c16
--- /dev/null
+++ b/arch/arm/mach-aaec2000/core.h
@@ -0,0 +1,16 @@
1/*
2 * linux/arch/arm/mach-aaec2000/core.h
3 *
4 * Copyright (c) 2005 Nicolas Bellido Y Ortega
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12struct sys_timer;
13
14extern struct sys_timer aaec2000_timer;
15extern void __init aaec2000_map_io(void);
16extern void __init aaec2000_init_irq(void);
diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index 158daaf9e3b0..ebb255bdce8a 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_LEDS) += leds.o
12obj-$(CONFIG_PCI) += pci_v3.o pci.o 12obj-$(CONFIG_PCI) += pci_v3.o pci.o
13obj-$(CONFIG_CPU_FREQ_INTEGRATOR) += cpu.o 13obj-$(CONFIG_CPU_FREQ_INTEGRATOR) += cpu.o
14obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o 14obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o
15obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index bd17b5154311..bd1e5e3c9d34 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -14,6 +14,7 @@
14#include <linux/spinlock.h> 14#include <linux/spinlock.h>
15#include <linux/interrupt.h> 15#include <linux/interrupt.h>
16#include <linux/sched.h> 16#include <linux/sched.h>
17#include <linux/smp.h>
17 18
18#include <asm/hardware.h> 19#include <asm/hardware.h>
19#include <asm/irq.h> 20#include <asm/irq.h>
@@ -221,7 +222,23 @@ integrator_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
221 */ 222 */
222 timer1->TimerClear = 1; 223 timer1->TimerClear = 1;
223 224
224 timer_tick(regs); 225 /*
226 * the clock tick routines are only processed on the
227 * primary CPU
228 */
229 if (hard_smp_processor_id() == 0) {
230 timer_tick(regs);
231#ifdef CONFIG_SMP
232 smp_send_timer();
233#endif
234 }
235
236#ifdef CONFIG_SMP
237 /*
238 * this is the ARM equivalent of the APIC timer interrupt
239 */
240 update_process_times(user_mode(regs));
241#endif /* CONFIG_SMP */
225 242
226 write_sequnlock(&xtime_lock); 243 write_sequnlock(&xtime_lock);
227 244
diff --git a/arch/arm/mach-integrator/headsmp.S b/arch/arm/mach-integrator/headsmp.S
new file mode 100644
index 000000000000..ceaa88e30d70
--- /dev/null
+++ b/arch/arm/mach-integrator/headsmp.S
@@ -0,0 +1,37 @@
1/*
2 * linux/arch/arm/mach-integrator/headsmp.S
3 *
4 * Copyright (c) 2003 ARM Limited
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/linkage.h>
12#include <linux/init.h>
13
14 __INIT
15
16/*
17 * Integrator specific entry point for secondary CPUs. This provides
18 * a "holding pen" into which all secondary cores are held until we're
19 * ready for them to initialise.
20 */
21ENTRY(integrator_secondary_startup)
22 adr r4, 1f
23 ldmia r4, {r5, r6}
24 sub r4, r4, r5
25 ldr r6, [r6, r4]
26pen: ldr r7, [r6]
27 cmp r7, r0
28 bne pen
29
30 /*
31 * we've been released from the holding pen: secondary_stack
32 * should now contain the SVC stack for this core
33 */
34 b secondary_startup
35
361: .long .
37 .long phys_pen_release
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 3b948e8c2751..e0a01eef0993 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -83,7 +83,6 @@ static struct map_desc intcp_io_desc[] __initdata = {
83 { IO_ADDRESS(INTEGRATOR_UART1_BASE), INTEGRATOR_UART1_BASE, SZ_4K, MT_DEVICE }, 83 { IO_ADDRESS(INTEGRATOR_UART1_BASE), INTEGRATOR_UART1_BASE, SZ_4K, MT_DEVICE },
84 { IO_ADDRESS(INTEGRATOR_DBG_BASE), INTEGRATOR_DBG_BASE, SZ_4K, MT_DEVICE }, 84 { IO_ADDRESS(INTEGRATOR_DBG_BASE), INTEGRATOR_DBG_BASE, SZ_4K, MT_DEVICE },
85 { IO_ADDRESS(INTEGRATOR_GPIO_BASE), INTEGRATOR_GPIO_BASE, SZ_4K, MT_DEVICE }, 85 { IO_ADDRESS(INTEGRATOR_GPIO_BASE), INTEGRATOR_GPIO_BASE, SZ_4K, MT_DEVICE },
86 { 0xfc900000, 0xc9000000, SZ_4K, MT_DEVICE },
87 { 0xfca00000, 0xca000000, SZ_4K, MT_DEVICE }, 86 { 0xfca00000, 0xca000000, SZ_4K, MT_DEVICE },
88 { 0xfcb00000, 0xcb000000, SZ_4K, MT_DEVICE }, 87 { 0xfcb00000, 0xcb000000, SZ_4K, MT_DEVICE },
89}; 88};
diff --git a/arch/arm/mach-integrator/leds.c b/arch/arm/mach-integrator/leds.c
index d2c0ab21150c..f1436e683b49 100644
--- a/arch/arm/mach-integrator/leds.c
+++ b/arch/arm/mach-integrator/leds.c
@@ -22,6 +22,8 @@
22 */ 22 */
23#include <linux/kernel.h> 23#include <linux/kernel.h>
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/smp.h>
26#include <linux/spinlock.h>
25 27
26#include <asm/hardware.h> 28#include <asm/hardware.h>
27#include <asm/io.h> 29#include <asm/io.h>
@@ -85,4 +87,4 @@ static int __init leds_init(void)
85 return 0; 87 return 0;
86} 88}
87 89
88__initcall(leds_init); 90core_initcall(leds_init);
diff --git a/arch/arm/mach-integrator/platsmp.c b/arch/arm/mach-integrator/platsmp.c
new file mode 100644
index 000000000000..ead15dfcb53d
--- /dev/null
+++ b/arch/arm/mach-integrator/platsmp.c
@@ -0,0 +1,192 @@
1/*
2 * linux/arch/arm/mach-cintegrator/platsmp.c
3 *
4 * Copyright (C) 2002 ARM Ltd.
5 * All Rights Reserved
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/sched.h>
14#include <linux/errno.h>
15#include <linux/mm.h>
16
17#include <asm/atomic.h>
18#include <asm/delay.h>
19#include <asm/mmu_context.h>
20#include <asm/procinfo.h>
21#include <asm/ptrace.h>
22#include <asm/smp.h>
23
24extern void integrator_secondary_startup(void);
25
26/*
27 * control for which core is the next to come out of the secondary
28 * boot "holding pen"
29 */
30volatile int __initdata pen_release = -1;
31unsigned long __initdata phys_pen_release = 0;
32
33static DEFINE_SPINLOCK(boot_lock);
34
35void __init platform_secondary_init(unsigned int cpu)
36{
37 /*
38 * the primary core may have used a "cross call" soft interrupt
39 * to get this processor out of WFI in the BootMonitor - make
40 * sure that we are no longer being sent this soft interrupt
41 */
42 smp_cross_call_done(cpumask_of_cpu(cpu));
43
44 /*
45 * if any interrupts are already enabled for the primary
46 * core (e.g. timer irq), then they will not have been enabled
47 * for us: do so
48 */
49 secondary_scan_irqs();
50
51 /*
52 * let the primary processor know we're out of the
53 * pen, then head off into the C entry point
54 */
55 pen_release = -1;
56
57 /*
58 * Synchronise with the boot thread.
59 */
60 spin_lock(&boot_lock);
61 spin_unlock(&boot_lock);
62}
63
64int __init boot_secondary(unsigned int cpu, struct task_struct *idle)
65{
66 unsigned long timeout;
67
68 /*
69 * set synchronisation state between this boot processor
70 * and the secondary one
71 */
72 spin_lock(&boot_lock);
73
74 /*
75 * The secondary processor is waiting to be released from
76 * the holding pen - release it, then wait for it to flag
77 * that it has been released by resetting pen_release.
78 *
79 * Note that "pen_release" is the hardware CPU ID, whereas
80 * "cpu" is Linux's internal ID.
81 */
82 pen_release = cpu;
83
84 /*
85 * XXX
86 *
87 * This is a later addition to the booting protocol: the
88 * bootMonitor now puts secondary cores into WFI, so
89 * poke_milo() no longer gets the cores moving; we need
90 * to send a soft interrupt to wake the secondary core.
91 * Use smp_cross_call() for this, since there's little
92 * point duplicating the code here
93 */
94 smp_cross_call(cpumask_of_cpu(cpu));
95
96 timeout = jiffies + (1 * HZ);
97 while (time_before(jiffies, timeout)) {
98 if (pen_release == -1)
99 break;
100
101 udelay(10);
102 }
103
104 /*
105 * now the secondary core is starting up let it run its
106 * calibrations, then wait for it to finish
107 */
108 spin_unlock(&boot_lock);
109
110 return pen_release != -1 ? -ENOSYS : 0;
111}
112
113static void __init poke_milo(void)
114{
115 extern void secondary_startup(void);
116
117 /* nobody is to be released from the pen yet */
118 pen_release = -1;
119
120 phys_pen_release = virt_to_phys(&pen_release);
121
122 /*
123 * write the address of secondary startup into the system-wide
124 * flags register, then clear the bottom two bits, which is what
125 * BootMonitor is waiting for
126 */
127#if 1
128#define CINTEGRATOR_HDR_FLAGSS_OFFSET 0x30
129 __raw_writel(virt_to_phys(integrator_secondary_startup),
130 (IO_ADDRESS(INTEGRATOR_HDR_BASE) +
131 CINTEGRATOR_HDR_FLAGSS_OFFSET));
132#define CINTEGRATOR_HDR_FLAGSC_OFFSET 0x34
133 __raw_writel(3,
134 (IO_ADDRESS(INTEGRATOR_HDR_BASE) +
135 CINTEGRATOR_HDR_FLAGSC_OFFSET));
136#endif
137
138 mb();
139}
140
141void __init smp_prepare_cpus(unsigned int max_cpus)
142{
143 unsigned int ncores = get_core_count();
144 unsigned int cpu = smp_processor_id();
145 int i;
146
147 /* sanity check */
148 if (ncores == 0) {
149 printk(KERN_ERR
150 "Integrator/CP: strange CM count of 0? Default to 1\n");
151
152 ncores = 1;
153 }
154
155 if (ncores > NR_CPUS) {
156 printk(KERN_WARNING
157 "Integrator/CP: no. of cores (%d) greater than configured "
158 "maximum of %d - clipping\n",
159 ncores, NR_CPUS);
160 ncores = NR_CPUS;
161 }
162
163 /*
164 * start with some more config for the Boot CPU, now that
165 * the world is a bit more alive (which was not the case
166 * when smp_prepare_boot_cpu() was called)
167 */
168 smp_store_cpu_info(cpu);
169
170 /*
171 * are we trying to boot more cores than exist?
172 */
173 if (max_cpus > ncores)
174 max_cpus = ncores;
175
176 /*
177 * Initialise the present mask - this tells us which CPUs should
178 * be present.
179 */
180 for (i = 0; i < max_cpus; i++) {
181 cpu_set(i, cpu_present_mask);
182 }
183
184 /*
185 * Do we need any more CPUs? If so, then let them know where
186 * to start. Note that, on modern versions of MILO, the "poke"
187 * doesn't actually do anything until each individual core is
188 * sent a soft interrupt to get it out of WFI
189 */
190 if (max_cpus > 1)
191 poke_milo();
192}
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index 4f3c3d5c781c..fc0555596d6d 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -162,12 +162,13 @@ void __init ixp2000_map_io(void)
162static unsigned ticks_per_jiffy; 162static unsigned ticks_per_jiffy;
163static unsigned ticks_per_usec; 163static unsigned ticks_per_usec;
164static unsigned next_jiffy_time; 164static unsigned next_jiffy_time;
165static volatile unsigned long *missing_jiffy_timer_csr;
165 166
166unsigned long ixp2000_gettimeoffset (void) 167unsigned long ixp2000_gettimeoffset (void)
167{ 168{
168 unsigned long offset; 169 unsigned long offset;
169 170
170 offset = next_jiffy_time - *IXP2000_T4_CSR; 171 offset = next_jiffy_time - *missing_jiffy_timer_csr;
171 172
172 return offset / ticks_per_usec; 173 return offset / ticks_per_usec;
173} 174}
@@ -179,7 +180,7 @@ static int ixp2000_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
179 /* clear timer 1 */ 180 /* clear timer 1 */
180 ixp2000_reg_write(IXP2000_T1_CLR, 1); 181 ixp2000_reg_write(IXP2000_T1_CLR, 1);
181 182
182 while ((next_jiffy_time - *IXP2000_T4_CSR) > ticks_per_jiffy) { 183 while ((next_jiffy_time - *missing_jiffy_timer_csr) > ticks_per_jiffy) {
183 timer_tick(regs); 184 timer_tick(regs);
184 next_jiffy_time -= ticks_per_jiffy; 185 next_jiffy_time -= ticks_per_jiffy;
185 } 186 }
@@ -197,20 +198,37 @@ static struct irqaction ixp2000_timer_irq = {
197 198
198void __init ixp2000_init_time(unsigned long tick_rate) 199void __init ixp2000_init_time(unsigned long tick_rate)
199{ 200{
200 ixp2000_reg_write(IXP2000_T1_CLR, 0);
201 ixp2000_reg_write(IXP2000_T4_CLR, 0);
202
203 ticks_per_jiffy = (tick_rate + HZ/2) / HZ; 201 ticks_per_jiffy = (tick_rate + HZ/2) / HZ;
204 ticks_per_usec = tick_rate / 1000000; 202 ticks_per_usec = tick_rate / 1000000;
205 203
204 /*
205 * We use timer 1 as our timer interrupt.
206 */
207 ixp2000_reg_write(IXP2000_T1_CLR, 0);
206 ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1); 208 ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1);
207 ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7)); 209 ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7));
208 210
209 /* 211 /*
210 * We use T4 as a monotonic counter to track missed jiffies 212 * We use a second timer as a monotonic counter for tracking
213 * missed jiffies. The IXP2000 has four timers, but if we're
214 * on an A-step IXP2800, timer 2 and 3 don't work, so on those
215 * chips we use timer 4. Timer 4 is the only timer that can
216 * be used for the watchdog, so we use timer 2 if we're on a
217 * non-buggy chip.
211 */ 218 */
212 ixp2000_reg_write(IXP2000_T4_CLD, -1); 219 if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) {
213 ixp2000_reg_write(IXP2000_T4_CTL, (1 << 7)); 220 printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n");
221
222 ixp2000_reg_write(IXP2000_T4_CLR, 0);
223 ixp2000_reg_write(IXP2000_T4_CLD, -1);
224 ixp2000_reg_write(IXP2000_T4_CTL, (1 << 7));
225 missing_jiffy_timer_csr = IXP2000_T4_CSR;
226 } else {
227 ixp2000_reg_write(IXP2000_T2_CLR, 0);
228 ixp2000_reg_write(IXP2000_T2_CLD, -1);
229 ixp2000_reg_write(IXP2000_T2_CTL, (1 << 7));
230 missing_jiffy_timer_csr = IXP2000_T2_CSR;
231 }
214 next_jiffy_time = 0xffffffff; 232 next_jiffy_time = 0xffffffff;
215 233
216 /* register for interrupt */ 234 /* register for interrupt */
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index dd012d6e2f5c..f2c9e0d2b24b 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -15,6 +15,7 @@
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/device.h> 17#include <linux/device.h>
18#include <linux/sysdev.h>
18#include <linux/major.h> 19#include <linux/major.h>
19#include <linux/fb.h> 20#include <linux/fb.h>
20#include <linux/interrupt.h> 21#include <linux/interrupt.h>
@@ -106,6 +107,35 @@ static void __init lubbock_init_irq(void)
106 set_irq_type(IRQ_GPIO(0), IRQT_FALLING); 107 set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
107} 108}
108 109
110#ifdef CONFIG_PM
111
112static int lubbock_irq_resume(struct sys_device *dev)
113{
114 LUB_IRQ_MASK_EN = lubbock_irq_enabled;
115 return 0;
116}
117
118static struct sysdev_class lubbock_irq_sysclass = {
119 set_kset_name("cpld_irq"),
120 .resume = lubbock_irq_resume,
121};
122
123static struct sys_device lubbock_irq_device = {
124 .cls = &lubbock_irq_sysclass,
125};
126
127static int __init lubbock_irq_device_init(void)
128{
129 int ret = sysdev_class_register(&lubbock_irq_sysclass);
130 if (ret == 0)
131 ret = sysdev_register(&lubbock_irq_device);
132 return ret;
133}
134
135device_initcall(lubbock_irq_device_init);
136
137#endif
138
109static int lubbock_udc_is_connected(void) 139static int lubbock_udc_is_connected(void)
110{ 140{
111 return (LUB_MISC_RD & (1 << 9)) == 0; 141 return (LUB_MISC_RD & (1 << 9)) == 0;
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 3f952237ae3d..9896afca751f 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -15,6 +15,7 @@
15 15
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/device.h> 17#include <linux/device.h>
18#include <linux/sysdev.h>
18#include <linux/interrupt.h> 19#include <linux/interrupt.h>
19#include <linux/sched.h> 20#include <linux/sched.h>
20#include <linux/bitops.h> 21#include <linux/bitops.h>
@@ -62,7 +63,6 @@ static struct irqchip mainstone_irq_chip = {
62 .unmask = mainstone_unmask_irq, 63 .unmask = mainstone_unmask_irq,
63}; 64};
64 65
65
66static void mainstone_irq_handler(unsigned int irq, struct irqdesc *desc, 66static void mainstone_irq_handler(unsigned int irq, struct irqdesc *desc,
67 struct pt_regs *regs) 67 struct pt_regs *regs)
68{ 68{
@@ -100,6 +100,35 @@ static void __init mainstone_init_irq(void)
100 set_irq_type(IRQ_GPIO(0), IRQT_FALLING); 100 set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
101} 101}
102 102
103#ifdef CONFIG_PM
104
105static int mainstone_irq_resume(struct sys_device *dev)
106{
107 MST_INTMSKENA = mainstone_irq_enabled;
108 return 0;
109}
110
111static struct sysdev_class mainstone_irq_sysclass = {
112 set_kset_name("cpld_irq"),
113 .resume = mainstone_irq_resume,
114};
115
116static struct sys_device mainstone_irq_device = {
117 .cls = &mainstone_irq_sysclass,
118};
119
120static int __init mainstone_irq_device_init(void)
121{
122 int ret = sysdev_class_register(&mainstone_irq_sysclass);
123 if (ret == 0)
124 ret = sysdev_register(&mainstone_irq_device);
125 return ret;
126}
127
128device_initcall(mainstone_irq_device_init);
129
130#endif
131
103 132
104static struct resource smc91x_resources[] = { 133static struct resource smc91x_resources[] = {
105 [0] = { 134 [0] = {
@@ -304,6 +333,15 @@ static void __init mainstone_map_io(void)
304 PWER = 0xC0000002; 333 PWER = 0xC0000002;
305 PRER = 0x00000002; 334 PRER = 0x00000002;
306 PFER = 0x00000002; 335 PFER = 0x00000002;
336 /* for use I SRAM as framebuffer. */
337 PSLR |= 0xF04;
338 PCFR = 0x66;
339 /* For Keypad wakeup. */
340 KPC &=~KPC_ASACT;
341 KPC |=KPC_AS;
342 PKWR = 0x000FD000;
343 /* Need read PKWR back after set it. */
344 PKWR;
307} 345}
308 346
309MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)") 347MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c
index 82a4bf34c251..ac4dd4336160 100644
--- a/arch/arm/mach-pxa/pm.c
+++ b/arch/arm/mach-pxa/pm.c
@@ -29,9 +29,6 @@
29 */ 29 */
30#undef DEBUG 30#undef DEBUG
31 31
32extern void pxa_cpu_suspend(void);
33extern void pxa_cpu_resume(void);
34
35#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x 32#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
36#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x] 33#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
37 34
@@ -63,6 +60,12 @@ enum { SLEEP_SAVE_START = 0,
63 SLEEP_SAVE_ICMR, 60 SLEEP_SAVE_ICMR,
64 SLEEP_SAVE_CKEN, 61 SLEEP_SAVE_CKEN,
65 62
63#ifdef CONFIG_PXA27x
64 SLEEP_SAVE_MDREFR,
65 SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
66 SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
67#endif
68
66 SLEEP_SAVE_CKSUM, 69 SLEEP_SAVE_CKSUM,
67 70
68 SLEEP_SAVE_SIZE 71 SLEEP_SAVE_SIZE
@@ -75,9 +78,7 @@ static int pxa_pm_enter(suspend_state_t state)
75 unsigned long checksum = 0; 78 unsigned long checksum = 0;
76 struct timespec delta, rtc; 79 struct timespec delta, rtc;
77 int i; 80 int i;
78 81 extern void pxa_cpu_pm_enter(suspend_state_t state);
79 if (state != PM_SUSPEND_MEM)
80 return -EINVAL;
81 82
82#ifdef CONFIG_IWMMXT 83#ifdef CONFIG_IWMMXT
83 /* force any iWMMXt context to ram **/ 84 /* force any iWMMXt context to ram **/
@@ -100,16 +101,17 @@ static int pxa_pm_enter(suspend_state_t state)
100 SAVE(GAFR2_L); SAVE(GAFR2_U); 101 SAVE(GAFR2_L); SAVE(GAFR2_U);
101 102
102#ifdef CONFIG_PXA27x 103#ifdef CONFIG_PXA27x
104 SAVE(MDREFR);
103 SAVE(GPLR3); SAVE(GPDR3); SAVE(GRER3); SAVE(GFER3); SAVE(PGSR3); 105 SAVE(GPLR3); SAVE(GPDR3); SAVE(GRER3); SAVE(GFER3); SAVE(PGSR3);
104 SAVE(GAFR3_L); SAVE(GAFR3_U); 106 SAVE(GAFR3_L); SAVE(GAFR3_U);
107 SAVE(PWER); SAVE(PCFR); SAVE(PRER);
108 SAVE(PFER); SAVE(PKWR);
105#endif 109#endif
106 110
107 SAVE(ICMR); 111 SAVE(ICMR);
108 ICMR = 0; 112 ICMR = 0;
109 113
110 SAVE(CKEN); 114 SAVE(CKEN);
111 CKEN = 0;
112
113 SAVE(PSTR); 115 SAVE(PSTR);
114 116
115 /* Note: wake up source are set up in each machine specific files */ 117 /* Note: wake up source are set up in each machine specific files */
@@ -123,16 +125,15 @@ static int pxa_pm_enter(suspend_state_t state)
123 /* Clear sleep reset status */ 125 /* Clear sleep reset status */
124 RCSR = RCSR_SMR; 126 RCSR = RCSR_SMR;
125 127
126 /* set resume return address */
127 PSPR = virt_to_phys(pxa_cpu_resume);
128
129 /* before sleeping, calculate and save a checksum */ 128 /* before sleeping, calculate and save a checksum */
130 for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++) 129 for (i = 0; i < SLEEP_SAVE_SIZE - 1; i++)
131 checksum += sleep_save[i]; 130 checksum += sleep_save[i];
132 sleep_save[SLEEP_SAVE_CKSUM] = checksum; 131 sleep_save[SLEEP_SAVE_CKSUM] = checksum;
133 132
134 /* *** go zzz *** */ 133 /* *** go zzz *** */
135 pxa_cpu_suspend(); 134 pxa_cpu_pm_enter(state);
135
136 cpu_init();
136 137
137 /* after sleeping, validate the checksum */ 138 /* after sleeping, validate the checksum */
138 checksum = 0; 139 checksum = 0;
@@ -145,7 +146,7 @@ static int pxa_pm_enter(suspend_state_t state)
145 LUB_HEXLED = 0xbadbadc5; 146 LUB_HEXLED = 0xbadbadc5;
146#endif 147#endif
147 while (1) 148 while (1)
148 pxa_cpu_suspend(); 149 pxa_cpu_pm_enter(state);
149 } 150 }
150 151
151 /* ensure not to come back here if it wasn't intended */ 152 /* ensure not to come back here if it wasn't intended */
@@ -162,8 +163,11 @@ static int pxa_pm_enter(suspend_state_t state)
162 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); 163 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
163 164
164#ifdef CONFIG_PXA27x 165#ifdef CONFIG_PXA27x
166 RESTORE(MDREFR);
165 RESTORE(GAFR3_L); RESTORE(GAFR3_U); RESTORE_GPLEVEL(3); 167 RESTORE(GAFR3_L); RESTORE(GAFR3_U); RESTORE_GPLEVEL(3);
166 RESTORE(GPDR3); RESTORE(GRER3); RESTORE(GFER3); RESTORE(PGSR3); 168 RESTORE(GPDR3); RESTORE(GRER3); RESTORE(GFER3); RESTORE(PGSR3);
169 RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
170 RESTORE(PFER); RESTORE(PKWR);
167#endif 171#endif
168 172
169 PSSR = PSSR_RDH | PSSR_PH; 173 PSSR = PSSR_RDH | PSSR_PH;
@@ -197,7 +201,9 @@ unsigned long sleep_phys_sp(void *sp)
197 */ 201 */
198static int pxa_pm_prepare(suspend_state_t state) 202static int pxa_pm_prepare(suspend_state_t state)
199{ 203{
200 return 0; 204 extern int pxa_cpu_pm_prepare(suspend_state_t state);
205
206 return pxa_cpu_pm_prepare(state);
201} 207}
202 208
203/* 209/*
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index e887b7175ef3..7869c3b4e62f 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -16,6 +16,7 @@
16 * initialization stuff for PXA machines which can be overridden later if 16 * initialization stuff for PXA machines which can be overridden later if
17 * need be. 17 * need be.
18 */ 18 */
19#include <linux/config.h>
19#include <linux/module.h> 20#include <linux/module.h>
20#include <linux/kernel.h> 21#include <linux/kernel.h>
21#include <linux/init.h> 22#include <linux/init.h>
@@ -102,3 +103,35 @@ unsigned int get_lcdclk_frequency_10khz(void)
102} 103}
103 104
104EXPORT_SYMBOL(get_lcdclk_frequency_10khz); 105EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
106
107#ifdef CONFIG_PM
108
109int pxa_cpu_pm_prepare(suspend_state_t state)
110{
111 switch (state) {
112 case PM_SUSPEND_MEM:
113 break;
114 default:
115 return -EINVAL;
116 }
117
118 return 0;
119}
120
121void pxa_cpu_pm_enter(suspend_state_t state)
122{
123 extern void pxa_cpu_suspend(unsigned int);
124 extern void pxa_cpu_resume(void);
125
126 CKEN = 0;
127
128 switch (state) {
129 case PM_SUSPEND_MEM:
130 /* set resume return address */
131 PSPR = virt_to_phys(pxa_cpu_resume);
132 pxa_cpu_suspend(3);
133 break;
134 }
135}
136
137#endif
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 7e863afefb53..893964fb9659 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -120,6 +120,42 @@ EXPORT_SYMBOL(get_clk_frequency_khz);
120EXPORT_SYMBOL(get_memclk_frequency_10khz); 120EXPORT_SYMBOL(get_memclk_frequency_10khz);
121EXPORT_SYMBOL(get_lcdclk_frequency_10khz); 121EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
122 122
123#ifdef CONFIG_PM
124
125int pxa_cpu_pm_prepare(suspend_state_t state)
126{
127 switch (state) {
128 case PM_SUSPEND_MEM:
129 return 0;
130 default:
131 return -EINVAL;
132 }
133}
134
135void pxa_cpu_pm_enter(suspend_state_t state)
136{
137 extern void pxa_cpu_standby(void);
138 extern void pxa_cpu_suspend(unsigned int);
139 extern void pxa_cpu_resume(void);
140
141 CKEN = CKEN22_MEMC | CKEN9_OSTIMER;
142
143 /* ensure voltage-change sequencer not initiated, which hangs */
144 PCFR &= ~PCFR_FVC;
145
146 /* Clear edge-detect status register. */
147 PEDR = 0xDF12FE1B;
148
149 switch (state) {
150 case PM_SUSPEND_MEM:
151 /* set resume return address */
152 PSPR = virt_to_phys(pxa_cpu_resume);
153 pxa_cpu_suspend(3);
154 break;
155 }
156}
157
158#endif
123 159
124/* 160/*
125 * device registration specific to PXA27x. 161 * device registration specific to PXA27x.
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index bc229fab86d4..c7c28890d406 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -785,6 +785,10 @@ int s3c2410_dma_free(dmach_t channel, s3c2410_dma_client_t *client)
785 chan->client = NULL; 785 chan->client = NULL;
786 chan->in_use = 0; 786 chan->in_use = 0;
787 787
788 if (chan->irq_claimed)
789 free_irq(chan->irq, (void *)chan);
790 chan->irq_claimed = 0;
791
788 local_irq_restore(flags); 792 local_irq_restore(flags);
789 793
790 return 0; 794 return 0;
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index 50cde576dadf..6923316b3d0d 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -150,7 +150,7 @@ config SA1100_SSP
150 150
151config H3600_SLEEVE 151config H3600_SLEEVE
152 tristate "Compaq iPAQ Handheld sleeve support" 152 tristate "Compaq iPAQ Handheld sleeve support"
153 depends on SA1100_H3600 153 depends on SA1100_H3100 || SA1100_H3600
154 help 154 help
155 Choose this option to enable support for extension packs (sleeves) 155 Choose this option to enable support for extension packs (sleeves)
156 for the Compaq iPAQ H3XXX series of handheld computers. This option 156 for the Compaq iPAQ H3XXX series of handheld computers. This option
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index 379ea5e3950f..59c7964cfe11 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -88,6 +88,8 @@ static int sa11x0_pm_enter(suspend_state_t state)
88 /* go zzz */ 88 /* go zzz */
89 sa1100_cpu_suspend(); 89 sa1100_cpu_suspend();
90 90
91 cpu_init();
92
91 /* 93 /*
92 * Ensure not to come back here if it wasn't intended 94 * Ensure not to come back here if it wasn't intended
93 */ 95 */
diff --git a/arch/arm/mach-versatile/Makefile b/arch/arm/mach-versatile/Makefile
index 5d608837757a..ba81e70ed813 100644
--- a/arch/arm/mach-versatile/Makefile
+++ b/arch/arm/mach-versatile/Makefile
@@ -5,3 +5,4 @@
5obj-y := core.o clock.o 5obj-y := core.o clock.o
6obj-$(CONFIG_ARCH_VERSATILE_PB) += versatile_pb.o 6obj-$(CONFIG_ARCH_VERSATILE_PB) += versatile_pb.o
7obj-$(CONFIG_MACH_VERSATILE_AB) += versatile_ab.o 7obj-$(CONFIG_MACH_VERSATILE_AB) += versatile_ab.o
8obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 554e1bd30d6e..6a7cbea5e098 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -196,11 +196,15 @@ static struct map_desc versatile_io_desc[] __initdata = {
196#ifdef CONFIG_DEBUG_LL 196#ifdef CONFIG_DEBUG_LL
197 { IO_ADDRESS(VERSATILE_UART0_BASE), VERSATILE_UART0_BASE, SZ_4K, MT_DEVICE }, 197 { IO_ADDRESS(VERSATILE_UART0_BASE), VERSATILE_UART0_BASE, SZ_4K, MT_DEVICE },
198#endif 198#endif
199#ifdef FIXME 199#ifdef CONFIG_PCI
200 { PCI_MEMORY_VADDR, PHYS_PCI_MEM_BASE, SZ_16M, MT_DEVICE }, 200 { IO_ADDRESS(VERSATILE_PCI_CORE_BASE), VERSATILE_PCI_CORE_BASE, SZ_4K, MT_DEVICE },
201 { PCI_CONFIG_VADDR, PHYS_PCI_CONFIG_BASE, SZ_16M, MT_DEVICE }, 201 { VERSATILE_PCI_VIRT_BASE, VERSATILE_PCI_BASE, VERSATILE_PCI_BASE_SIZE, MT_DEVICE },
202 { PCI_V3_VADDR, PHYS_PCI_V3_BASE, SZ_512K, MT_DEVICE }, 202 { VERSATILE_PCI_CFG_VIRT_BASE, VERSATILE_PCI_CFG_BASE, VERSATILE_PCI_CFG_BASE_SIZE, MT_DEVICE },
203 { PCI_IO_VADDR, PHYS_PCI_IO_BASE, SZ_64K, MT_DEVICE }, 203#if 0
204 { VERSATILE_PCI_VIRT_MEM_BASE0, VERSATILE_PCI_MEM_BASE0, SZ_16M, MT_DEVICE },
205 { VERSATILE_PCI_VIRT_MEM_BASE1, VERSATILE_PCI_MEM_BASE1, SZ_16M, MT_DEVICE },
206 { VERSATILE_PCI_VIRT_MEM_BASE2, VERSATILE_PCI_MEM_BASE2, SZ_16M, MT_DEVICE },
207#endif
204#endif 208#endif
205}; 209};
206 210
@@ -543,7 +547,7 @@ static void versatile_clcd_enable(struct clcd_fb *fb)
543 val |= SYS_CLCD_MODE_5551; 547 val |= SYS_CLCD_MODE_5551;
544 break; 548 break;
545 case 6: 549 case 6:
546 val |= SYS_CLCD_MODE_565_BLSB; 550 val |= SYS_CLCD_MODE_565_RLSB;
547 break; 551 break;
548 case 8: 552 case 8:
549 val |= SYS_CLCD_MODE_888; 553 val |= SYS_CLCD_MODE_888;
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
new file mode 100644
index 000000000000..d1565e851f0e
--- /dev/null
+++ b/arch/arm/mach-versatile/pci.c
@@ -0,0 +1,360 @@
1/*
2 * linux/arch/arm/mach-versatile/pci.c
3 *
4 * (C) Copyright Koninklijke Philips Electronics NV 2004. All rights reserved.
5 * You can redistribute and/or modify this software under the terms of version 2
6 * of the GNU General Public License as published by the Free Software Foundation.
7 * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
8 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
9 * General Public License for more details.
10 * Koninklijke Philips Electronics nor its subsidiaries is obligated to provide any support for this software.
11 *
12 * ARM Versatile PCI driver.
13 *
14 * 14/04/2005 Initial version, colin.king@philips.com
15 *
16 */
17#include <linux/config.h>
18#include <linux/kernel.h>
19#include <linux/pci.h>
20#include <linux/ptrace.h>
21#include <linux/slab.h>
22#include <linux/ioport.h>
23#include <linux/interrupt.h>
24#include <linux/spinlock.h>
25#include <linux/init.h>
26
27#include <asm/hardware.h>
28#include <asm/io.h>
29#include <asm/irq.h>
30#include <asm/system.h>
31#include <asm/mach/pci.h>
32#include <asm/mach-types.h>
33
34/*
35 * these spaces are mapped using the following base registers:
36 *
37 * Usage Local Bus Memory Base/Map registers used
38 *
39 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0, non prefetch
40 * Mem 60000000 - 6FFFFFFF LB_BASE1/LB_MAP1, prefetch
41 * IO 44000000 - 4FFFFFFF LB_BASE2/LB_MAP2, IO
42 * Cfg 42000000 - 42FFFFFF PCI config
43 *
44 */
45#define SYS_PCICTL IO_ADDRESS(VERSATILE_SYS_PCICTL)
46#define PCI_IMAP0 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
47#define PCI_IMAP1 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
48#define PCI_IMAP2 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
49#define PCI_SMAP0 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10)
50#define PCI_SMAP1 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
51#define PCI_SMAP2 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
52#define PCI_SELFID IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)
53
54#define DEVICE_ID_OFFSET 0x00
55#define CSR_OFFSET 0x04
56#define CLASS_ID_OFFSET 0x08
57
58#define VP_PCI_DEVICE_ID 0x030010ee
59#define VP_PCI_CLASS_ID 0x0b400000
60
61static unsigned long pci_slot_ignore = 0;
62
63static int __init versatile_pci_slot_ignore(char *str)
64{
65 int retval;
66 int slot;
67
68 while ((retval = get_option(&str,&slot))) {
69 if ((slot < 0) || (slot > 31)) {
70 printk("Illegal slot value: %d\n",slot);
71 } else {
72 pci_slot_ignore |= (1 << slot);
73 }
74 }
75 return 1;
76}
77
78__setup("pci_slot_ignore=", versatile_pci_slot_ignore);
79
80
81static unsigned long __pci_addr(struct pci_bus *bus,
82 unsigned int devfn, int offset)
83{
84 unsigned int busnr = bus->number;
85
86 /*
87 * Trap out illegal values
88 */
89 if (offset > 255)
90 BUG();
91 if (busnr > 255)
92 BUG();
93 if (devfn > 255)
94 BUG();
95
96 return (VERSATILE_PCI_CFG_VIRT_BASE | (busnr << 16) |
97 (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset);
98}
99
100static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
101 int size, u32 *val)
102{
103 unsigned long addr = __pci_addr(bus, devfn, where);
104 u32 v;
105 int slot = PCI_SLOT(devfn);
106
107 if (pci_slot_ignore & (1 << slot)) {
108 /* Ignore this slot */
109 switch (size) {
110 case 1:
111 v = 0xff;
112 break;
113 case 2:
114 v = 0xffff;
115 break;
116 default:
117 v = 0xffffffff;
118 }
119 } else {
120 switch (size) {
121 case 1:
122 addr &= ~3;
123 v = __raw_readb(addr);
124 break;
125
126 case 2:
127 v = __raw_readl(addr & ~3);
128 if (addr & 2) v >>= 16;
129 v &= 0xffff;
130 break;
131
132 default:
133 addr &= ~3;
134 v = __raw_readl(addr);
135 break;
136 }
137 }
138
139 *val = v;
140 return PCIBIOS_SUCCESSFUL;
141}
142
143static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
144 int size, u32 val)
145{
146 unsigned long addr = __pci_addr(bus, devfn, where);
147 int slot = PCI_SLOT(devfn);
148
149 if (pci_slot_ignore & (1 << slot)) {
150 return PCIBIOS_SUCCESSFUL;
151 }
152
153 switch (size) {
154 case 1:
155 __raw_writeb((u8)val, addr);
156 break;
157
158 case 2:
159 __raw_writew((u16)val, addr);
160 break;
161
162 case 4:
163 __raw_writel(val, addr);
164 break;
165 }
166
167 return PCIBIOS_SUCCESSFUL;
168}
169
170static struct pci_ops pci_versatile_ops = {
171 .read = versatile_read_config,
172 .write = versatile_write_config,
173};
174
175static struct resource io_mem = {
176 .name = "PCI I/O space",
177 .start = VERSATILE_PCI_MEM_BASE0,
178 .end = VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
179 .flags = IORESOURCE_IO,
180};
181
182static struct resource non_mem = {
183 .name = "PCI non-prefetchable",
184 .start = VERSATILE_PCI_MEM_BASE1,
185 .end = VERSATILE_PCI_MEM_BASE1+VERSATILE_PCI_MEM_BASE1_SIZE-1,
186 .flags = IORESOURCE_MEM,
187};
188
189static struct resource pre_mem = {
190 .name = "PCI prefetchable",
191 .start = VERSATILE_PCI_MEM_BASE2,
192 .end = VERSATILE_PCI_MEM_BASE2+VERSATILE_PCI_MEM_BASE2_SIZE-1,
193 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
194};
195
196static int __init pci_versatile_setup_resources(struct resource **resource)
197{
198 int ret = 0;
199
200 ret = request_resource(&iomem_resource, &io_mem);
201 if (ret) {
202 printk(KERN_ERR "PCI: unable to allocate I/O "
203 "memory region (%d)\n", ret);
204 goto out;
205 }
206 ret = request_resource(&iomem_resource, &non_mem);
207 if (ret) {
208 printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
209 "memory region (%d)\n", ret);
210 goto release_io_mem;
211 }
212 ret = request_resource(&iomem_resource, &pre_mem);
213 if (ret) {
214 printk(KERN_ERR "PCI: unable to allocate prefetchable "
215 "memory region (%d)\n", ret);
216 goto release_non_mem;
217 }
218
219 /*
220 * bus->resource[0] is the IO resource for this bus
221 * bus->resource[1] is the mem resource for this bus
222 * bus->resource[2] is the prefetch mem resource for this bus
223 */
224 resource[0] = &io_mem;
225 resource[1] = &non_mem;
226 resource[2] = &pre_mem;
227
228 goto out;
229
230 release_non_mem:
231 release_resource(&non_mem);
232 release_io_mem:
233 release_resource(&io_mem);
234 out:
235 return ret;
236}
237
238int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
239{
240 int ret = 0;
241 int i;
242 int myslot = -1;
243 unsigned long val;
244
245 if (nr == 0) {
246 sys->mem_offset = 0;
247 ret = pci_versatile_setup_resources(sys->resource);
248 if (ret < 0) {
249 printk("pci_versatile_setup: resources... oops?\n");
250 goto out;
251 }
252 } else {
253 printk("pci_versatile_setup: resources... nr == 0??\n");
254 goto out;
255 }
256
257 __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28,PCI_IMAP0);
258 __raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28,PCI_IMAP1);
259 __raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28,PCI_IMAP2);
260
261 __raw_writel(1, SYS_PCICTL);
262
263 val = __raw_readl(SYS_PCICTL);
264 if (!(val & 1)) {
265 printk("Not plugged into PCI backplane!\n");
266 ret = -EIO;
267 goto out;
268 }
269
270 /*
271 * We need to discover the PCI core first to configure itself
272 * before the main PCI probing is performed
273 */
274 for (i=0; i<32; i++) {
275 if ((__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+DEVICE_ID_OFFSET) == VP_PCI_DEVICE_ID) &&
276 (__raw_readl(VERSATILE_PCI_VIRT_BASE+(i<<11)+CLASS_ID_OFFSET) == VP_PCI_CLASS_ID)) {
277 myslot = i;
278
279 __raw_writel(myslot, PCI_SELFID);
280 val = __raw_readl(VERSATILE_PCI_CFG_VIRT_BASE+(myslot<<11)+CSR_OFFSET);
281 val |= (1<<2);
282 __raw_writel(val, VERSATILE_PCI_CFG_VIRT_BASE+(myslot<<11)+CSR_OFFSET);
283 break;
284 }
285 }
286
287 if (myslot == -1) {
288 printk("Cannot find PCI core!\n");
289 ret = -EIO;
290 } else {
291 printk("PCI core found (slot %d)\n",myslot);
292 /* Do not to map Versatile FPGA PCI device
293 into memory space as we are short of
294 mappable memory */
295 pci_slot_ignore |= (1 << myslot);
296 ret = 1;
297 }
298
299 out:
300 return ret;
301}
302
303
304struct pci_bus *pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
305{
306 return pci_scan_bus(sys->busnr, &pci_versatile_ops, sys);
307}
308
309/*
310 * V3_LB_BASE? - local bus address
311 * V3_LB_MAP? - pci bus address
312 */
313void __init pci_versatile_preinit(void)
314{
315}
316
317void __init pci_versatile_postinit(void)
318{
319}
320
321
322/*
323 * map the specified device/slot/pin to an IRQ. Different backplanes may need to modify this.
324 */
325static int __init versatile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
326{
327 int irq;
328 int devslot = PCI_SLOT(dev->devfn);
329
330 /* slot, pin, irq
331 24 1 27
332 25 1 28 untested
333 26 1 29
334 27 1 30 untested
335 */
336
337 irq = 27 + ((slot + pin + 2) % 3); /* Fudged */
338
339 printk("map irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq);
340
341 return irq;
342}
343
344static struct hw_pci versatile_pci __initdata = {
345 .swizzle = NULL,
346 .map_irq = versatile_map_irq,
347 .nr_controllers = 1,
348 .setup = pci_versatile_setup,
349 .scan = pci_versatile_scan_bus,
350 .preinit = pci_versatile_preinit,
351 .postinit = pci_versatile_postinit,
352};
353
354static int __init versatile_pci_init(void)
355{
356 pci_common_init(&versatile_pci);
357 return 0;
358}
359
360subsys_initcall(versatile_pci_init);
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 48bac7da8c70..95606b4a3ba6 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -62,7 +62,7 @@ config CPU_ARM720T
62# ARM920T 62# ARM920T
63config CPU_ARM920T 63config CPU_ARM920T
64 bool "Support ARM920T processor" if !ARCH_S3C2410 64 bool "Support ARM920T processor" if !ARCH_S3C2410
65 depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX 65 depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000
66 default y if ARCH_S3C2410 66 default y if ARCH_S3C2410
67 select CPU_32v4 67 select CPU_32v4
68 select CPU_ABRT_EV4T 68 select CPU_ABRT_EV4T
@@ -228,7 +228,6 @@ config CPU_SA1100
228 select CPU_CACHE_V4WB 228 select CPU_CACHE_V4WB
229 select CPU_CACHE_VIVT 229 select CPU_CACHE_VIVT
230 select CPU_TLB_V4WB 230 select CPU_TLB_V4WB
231 select CPU_MINICACHE
232 231
233# XScale 232# XScale
234config CPU_XSCALE 233config CPU_XSCALE
@@ -239,7 +238,6 @@ config CPU_XSCALE
239 select CPU_ABRT_EV5T 238 select CPU_ABRT_EV5T
240 select CPU_CACHE_VIVT 239 select CPU_CACHE_VIVT
241 select CPU_TLB_V4WBI 240 select CPU_TLB_V4WBI
242 select CPU_MINICACHE
243 241
244# ARMv6 242# ARMv6
245config CPU_V6 243config CPU_V6
@@ -345,11 +343,6 @@ config CPU_TLB_V4WBI
345config CPU_TLB_V6 343config CPU_TLB_V6
346 bool 344 bool
347 345
348config CPU_MINICACHE
349 bool
350 help
351 Processor has a minicache.
352
353comment "Processor Features" 346comment "Processor Features"
354 347
355config ARM_THUMB 348config ARM_THUMB
@@ -429,3 +422,11 @@ config HAS_TLS_REG
429 assume directly accessing that register and always obtain the 422 assume directly accessing that register and always obtain the
430 expected value only on ARMv7 and above. 423 expected value only on ARMv7 and above.
431 424
425config NEEDS_SYSCALL_FOR_CMPXCHG
426 bool
427 default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
428 help
429 SMP on a pre-ARMv6 processor? Well OK then.
430 Forget about fast user space cmpxchg support.
431 It is just not possible.
432
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index ccf316c11e02..59f47d4c2dfe 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -31,8 +31,6 @@ obj-$(CONFIG_CPU_COPY_V6) += copypage-v6.o mmu.o
31obj-$(CONFIG_CPU_SA1100) += copypage-v4mc.o 31obj-$(CONFIG_CPU_SA1100) += copypage-v4mc.o
32obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o 32obj-$(CONFIG_CPU_XSCALE) += copypage-xscale.o
33 33
34obj-$(CONFIG_CPU_MINICACHE) += minicache.o
35
36obj-$(CONFIG_CPU_TLB_V3) += tlb-v3.o 34obj-$(CONFIG_CPU_TLB_V3) += tlb-v3.o
37obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o 35obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o
38obj-$(CONFIG_CPU_TLB_V4WB) += tlb-v4wb.o 36obj-$(CONFIG_CPU_TLB_V4WB) += tlb-v4wb.o
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index a8c00236bd3d..27d041574ea7 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -30,8 +30,6 @@
30 30
31static DEFINE_SPINLOCK(v6_lock); 31static DEFINE_SPINLOCK(v6_lock);
32 32
33#define DCACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
34
35/* 33/*
36 * Copy the user page. No aliasing to deal with so we can just 34 * Copy the user page. No aliasing to deal with so we can just
37 * attack the kernel's existing mapping of these pages. 35 * attack the kernel's existing mapping of these pages.
@@ -55,7 +53,7 @@ void v6_clear_user_page_nonaliasing(void *kaddr, unsigned long vaddr)
55 */ 53 */
56void v6_copy_user_page_aliasing(void *kto, const void *kfrom, unsigned long vaddr) 54void v6_copy_user_page_aliasing(void *kto, const void *kfrom, unsigned long vaddr)
57{ 55{
58 unsigned int offset = DCACHE_COLOUR(vaddr); 56 unsigned int offset = CACHE_COLOUR(vaddr);
59 unsigned long from, to; 57 unsigned long from, to;
60 58
61 /* 59 /*
@@ -95,7 +93,7 @@ void v6_copy_user_page_aliasing(void *kto, const void *kfrom, unsigned long vadd
95 */ 93 */
96void v6_clear_user_page_aliasing(void *kaddr, unsigned long vaddr) 94void v6_clear_user_page_aliasing(void *kaddr, unsigned long vaddr)
97{ 95{
98 unsigned int offset = DCACHE_COLOUR(vaddr); 96 unsigned int offset = CACHE_COLOUR(vaddr);
99 unsigned long to = to_address + (offset << PAGE_SHIFT); 97 unsigned long to = to_address + (offset << PAGE_SHIFT);
100 98
101 /* 99 /*
diff --git a/arch/arm/mm/copypage-xscale.S b/arch/arm/mm/copypage-xscale.S
deleted file mode 100644
index bb277316ef52..000000000000
--- a/arch/arm/mm/copypage-xscale.S
+++ /dev/null
@@ -1,113 +0,0 @@
1/*
2 * linux/arch/arm/lib/copypage-xscale.S
3 *
4 * Copyright (C) 2001 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/linkage.h>
11#include <linux/init.h>
12#include <asm/constants.h>
13
14/*
15 * General note:
16 * We don't really want write-allocate cache behaviour for these functions
17 * since that will just eat through 8K of the cache.
18 */
19
20 .text
21 .align 5
22/*
23 * XScale optimised copy_user_page
24 * r0 = destination
25 * r1 = source
26 * r2 = virtual user address of ultimate destination page
27 *
28 * The source page may have some clean entries in the cache already, but we
29 * can safely ignore them - break_cow() will flush them out of the cache
30 * if we eventually end up using our copied page.
31 *
32 * What we could do is use the mini-cache to buffer reads from the source
33 * page. We rely on the mini-cache being smaller than one page, so we'll
34 * cycle through the complete cache anyway.
35 */
36ENTRY(xscale_mc_copy_user_page)
37 stmfd sp!, {r4, r5, lr}
38 mov r5, r0
39 mov r0, r1
40 bl map_page_minicache
41 mov r1, r5
42 mov lr, #PAGE_SZ/64-1
43
44 /*
45 * Strangely enough, best performance is achieved
46 * when prefetching destination as well. (NP)
47 */
48 pld [r0, #0]
49 pld [r0, #32]
50 pld [r1, #0]
51 pld [r1, #32]
52
531: pld [r0, #64]
54 pld [r0, #96]
55 pld [r1, #64]
56 pld [r1, #96]
57
582: ldrd r2, [r0], #8
59 ldrd r4, [r0], #8
60 mov ip, r1
61 strd r2, [r1], #8
62 ldrd r2, [r0], #8
63 strd r4, [r1], #8
64 ldrd r4, [r0], #8
65 strd r2, [r1], #8
66 strd r4, [r1], #8
67 mcr p15, 0, ip, c7, c10, 1 @ clean D line
68 ldrd r2, [r0], #8
69 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line
70 ldrd r4, [r0], #8
71 mov ip, r1
72 strd r2, [r1], #8
73 ldrd r2, [r0], #8
74 strd r4, [r1], #8
75 ldrd r4, [r0], #8
76 strd r2, [r1], #8
77 strd r4, [r1], #8
78 mcr p15, 0, ip, c7, c10, 1 @ clean D line
79 subs lr, lr, #1
80 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line
81 bgt 1b
82 beq 2b
83
84 ldmfd sp!, {r4, r5, pc}
85
86 .align 5
87/*
88 * XScale optimised clear_user_page
89 * r0 = destination
90 * r1 = virtual user address of ultimate destination page
91 */
92ENTRY(xscale_mc_clear_user_page)
93 mov r1, #PAGE_SZ/32
94 mov r2, #0
95 mov r3, #0
961: mov ip, r0
97 strd r2, [r0], #8
98 strd r2, [r0], #8
99 strd r2, [r0], #8
100 strd r2, [r0], #8
101 mcr p15, 0, ip, c7, c10, 1 @ clean D line
102 subs r1, r1, #1
103 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line
104 bne 1b
105 mov pc, lr
106
107 __INITDATA
108
109 .type xscale_mc_user_fns, #object
110ENTRY(xscale_mc_user_fns)
111 .long xscale_mc_clear_user_page
112 .long xscale_mc_copy_user_page
113 .size xscale_mc_user_fns, . - xscale_mc_user_fns
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
new file mode 100644
index 000000000000..42a6ee255ce0
--- /dev/null
+++ b/arch/arm/mm/copypage-xscale.c
@@ -0,0 +1,131 @@
1/*
2 * linux/arch/arm/lib/copypage-xscale.S
3 *
4 * Copyright (C) 1995-2005 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This handles the mini data cache, as found on SA11x0 and XScale
11 * processors. When we copy a user page page, we map it in such a way
12 * that accesses to this page will not touch the main data cache, but
13 * will be cached in the mini data cache. This prevents us thrashing
14 * the main data cache on page faults.
15 */
16#include <linux/init.h>
17#include <linux/mm.h>
18
19#include <asm/page.h>
20#include <asm/pgtable.h>
21#include <asm/tlbflush.h>
22
23/*
24 * 0xffff8000 to 0xffffffff is reserved for any ARM architecture
25 * specific hacks for copying pages efficiently.
26 */
27#define COPYPAGE_MINICACHE 0xffff8000
28
29#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
30 L_PTE_CACHEABLE)
31
32#define TOP_PTE(x) pte_offset_kernel(top_pmd, x)
33
34static DEFINE_SPINLOCK(minicache_lock);
35
36/*
37 * XScale mini-dcache optimised copy_user_page
38 *
39 * We flush the destination cache lines just before we write the data into the
40 * corresponding address. Since the Dcache is read-allocate, this removes the
41 * Dcache aliasing issue. The writes will be forwarded to the write buffer,
42 * and merged as appropriate.
43 */
44static void __attribute__((naked))
45mc_copy_user_page(void *from, void *to)
46{
47 /*
48 * Strangely enough, best performance is achieved
49 * when prefetching destination as well. (NP)
50 */
51 asm volatile(
52 "stmfd sp!, {r4, r5, lr} \n\
53 mov lr, %2 \n\
54 pld [r0, #0] \n\
55 pld [r0, #32] \n\
56 pld [r1, #0] \n\
57 pld [r1, #32] \n\
581: pld [r0, #64] \n\
59 pld [r0, #96] \n\
60 pld [r1, #64] \n\
61 pld [r1, #96] \n\
622: ldrd r2, [r0], #8 \n\
63 ldrd r4, [r0], #8 \n\
64 mov ip, r1 \n\
65 strd r2, [r1], #8 \n\
66 ldrd r2, [r0], #8 \n\
67 strd r4, [r1], #8 \n\
68 ldrd r4, [r0], #8 \n\
69 strd r2, [r1], #8 \n\
70 strd r4, [r1], #8 \n\
71 mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
72 ldrd r2, [r0], #8 \n\
73 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
74 ldrd r4, [r0], #8 \n\
75 mov ip, r1 \n\
76 strd r2, [r1], #8 \n\
77 ldrd r2, [r0], #8 \n\
78 strd r4, [r1], #8 \n\
79 ldrd r4, [r0], #8 \n\
80 strd r2, [r1], #8 \n\
81 strd r4, [r1], #8 \n\
82 mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
83 subs lr, lr, #1 \n\
84 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
85 bgt 1b \n\
86 beq 2b \n\
87 ldmfd sp!, {r4, r5, pc} "
88 :
89 : "r" (from), "r" (to), "I" (PAGE_SIZE / 64 - 1));
90}
91
92void xscale_mc_copy_user_page(void *kto, const void *kfrom, unsigned long vaddr)
93{
94 spin_lock(&minicache_lock);
95
96 set_pte(TOP_PTE(COPYPAGE_MINICACHE), pfn_pte(__pa(kfrom) >> PAGE_SHIFT, minicache_pgprot));
97 flush_tlb_kernel_page(COPYPAGE_MINICACHE);
98
99 mc_copy_user_page((void *)COPYPAGE_MINICACHE, kto);
100
101 spin_unlock(&minicache_lock);
102}
103
104/*
105 * XScale optimised clear_user_page
106 */
107void __attribute__((naked))
108xscale_mc_clear_user_page(void *kaddr, unsigned long vaddr)
109{
110 asm volatile(
111 "mov r1, %0 \n\
112 mov r2, #0 \n\
113 mov r3, #0 \n\
1141: mov ip, r0 \n\
115 strd r2, [r0], #8 \n\
116 strd r2, [r0], #8 \n\
117 strd r2, [r0], #8 \n\
118 strd r2, [r0], #8 \n\
119 mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\
120 subs r1, r1, #1 \n\
121 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\
122 bne 1b \n\
123 mov pc, lr"
124 :
125 : "I" (PAGE_SIZE / 32));
126}
127
128struct cpu_user_fns xscale_mc_user_fns __initdata = {
129 .cpu_clear_user_page = xscale_mc_clear_user_page,
130 .cpu_copy_user_page = xscale_mc_copy_user_page,
131};
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 01967ddeef53..be4ab3d73c91 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -77,9 +77,8 @@ no_pmd:
77} 77}
78 78
79static void 79static void
80make_coherent(struct vm_area_struct *vma, unsigned long addr, struct page *page, int dirty) 80make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
81{ 81{
82 struct address_space *mapping = page_mapping(page);
83 struct mm_struct *mm = vma->vm_mm; 82 struct mm_struct *mm = vma->vm_mm;
84 struct vm_area_struct *mpnt; 83 struct vm_area_struct *mpnt;
85 struct prio_tree_iter iter; 84 struct prio_tree_iter iter;
@@ -87,9 +86,6 @@ make_coherent(struct vm_area_struct *vma, unsigned long addr, struct page *page,
87 pgoff_t pgoff; 86 pgoff_t pgoff;
88 int aliases = 0; 87 int aliases = 0;
89 88
90 if (!mapping)
91 return;
92
93 pgoff = vma->vm_pgoff + ((addr - vma->vm_start) >> PAGE_SHIFT); 89 pgoff = vma->vm_pgoff + ((addr - vma->vm_start) >> PAGE_SHIFT);
94 90
95 /* 91 /*
@@ -115,9 +111,11 @@ make_coherent(struct vm_area_struct *vma, unsigned long addr, struct page *page,
115 if (aliases) 111 if (aliases)
116 adjust_pte(vma, addr); 112 adjust_pte(vma, addr);
117 else 113 else
118 flush_cache_page(vma, addr, page_to_pfn(page)); 114 flush_cache_page(vma, addr, pfn);
119} 115}
120 116
117void __flush_dcache_page(struct address_space *mapping, struct page *page);
118
121/* 119/*
122 * Take care of architecture specific things when placing a new PTE into 120 * Take care of architecture specific things when placing a new PTE into
123 * a page table, or changing an existing PTE. Basically, there are two 121 * a page table, or changing an existing PTE. Basically, there are two
@@ -134,29 +132,22 @@ make_coherent(struct vm_area_struct *vma, unsigned long addr, struct page *page,
134void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte) 132void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
135{ 133{
136 unsigned long pfn = pte_pfn(pte); 134 unsigned long pfn = pte_pfn(pte);
135 struct address_space *mapping;
137 struct page *page; 136 struct page *page;
138 137
139 if (!pfn_valid(pfn)) 138 if (!pfn_valid(pfn))
140 return; 139 return;
140
141 page = pfn_to_page(pfn); 141 page = pfn_to_page(pfn);
142 if (page_mapping(page)) { 142 mapping = page_mapping(page);
143 if (mapping) {
143 int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags); 144 int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
144 145
145 if (dirty) { 146 if (dirty)
146 /* 147 __flush_dcache_page(mapping, page);
147 * This is our first userspace mapping of this page.
148 * Ensure that the physical page is coherent with
149 * the kernel mapping.
150 *
151 * FIXME: only need to do this on VIVT and aliasing
152 * VIPT cache architectures. We can do that
153 * by choosing whether to set this bit...
154 */
155 __cpuc_flush_dcache_page(page_address(page));
156 }
157 148
158 if (cache_is_vivt()) 149 if (cache_is_vivt())
159 make_coherent(vma, addr, page, dirty); 150 make_coherent(mapping, vma, addr, pfn);
160 } 151 }
161} 152}
162 153
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 4085ed983e46..191788fb18d1 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -37,13 +37,8 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
37#define flush_pfn_alias(pfn,vaddr) do { } while (0) 37#define flush_pfn_alias(pfn,vaddr) do { } while (0)
38#endif 38#endif
39 39
40static void __flush_dcache_page(struct address_space *mapping, struct page *page) 40void __flush_dcache_page(struct address_space *mapping, struct page *page)
41{ 41{
42 struct mm_struct *mm = current->active_mm;
43 struct vm_area_struct *mpnt;
44 struct prio_tree_iter iter;
45 pgoff_t pgoff;
46
47 /* 42 /*
48 * Writeback any data associated with the kernel mapping of this 43 * Writeback any data associated with the kernel mapping of this
49 * page. This ensures that data in the physical page is mutually 44 * page. This ensures that data in the physical page is mutually
@@ -52,24 +47,21 @@ static void __flush_dcache_page(struct address_space *mapping, struct page *page
52 __cpuc_flush_dcache_page(page_address(page)); 47 __cpuc_flush_dcache_page(page_address(page));
53 48
54 /* 49 /*
55 * If there's no mapping pointer here, then this page isn't 50 * If this is a page cache page, and we have an aliasing VIPT cache,
56 * visible to userspace yet, so there are no cache lines 51 * we only need to do one flush - which would be at the relevant
57 * associated with any other aliases.
58 */
59 if (!mapping)
60 return;
61
62 /*
63 * This is a page cache page. If we have a VIPT cache, we
64 * only need to do one flush - which would be at the relevant
65 * userspace colour, which is congruent with page->index. 52 * userspace colour, which is congruent with page->index.
66 */ 53 */
67 if (cache_is_vipt()) { 54 if (mapping && cache_is_vipt_aliasing())
68 if (cache_is_vipt_aliasing()) 55 flush_pfn_alias(page_to_pfn(page),
69 flush_pfn_alias(page_to_pfn(page), 56 page->index << PAGE_CACHE_SHIFT);
70 page->index << PAGE_CACHE_SHIFT); 57}
71 return; 58
72 } 59static void __flush_dcache_aliases(struct address_space *mapping, struct page *page)
60{
61 struct mm_struct *mm = current->active_mm;
62 struct vm_area_struct *mpnt;
63 struct prio_tree_iter iter;
64 pgoff_t pgoff;
73 65
74 /* 66 /*
75 * There are possible user space mappings of this page: 67 * There are possible user space mappings of this page:
@@ -116,12 +108,12 @@ void flush_dcache_page(struct page *page)
116{ 108{
117 struct address_space *mapping = page_mapping(page); 109 struct address_space *mapping = page_mapping(page);
118 110
119 if (cache_is_vipt_nonaliasing())
120 return;
121
122 if (mapping && !mapping_mapped(mapping)) 111 if (mapping && !mapping_mapped(mapping))
123 set_bit(PG_dcache_dirty, &page->flags); 112 set_bit(PG_dcache_dirty, &page->flags);
124 else 113 else {
125 __flush_dcache_page(mapping, page); 114 __flush_dcache_page(mapping, page);
115 if (mapping && cache_is_vivt())
116 __flush_dcache_aliases(mapping, page);
117 }
126} 118}
127EXPORT_SYMBOL(flush_dcache_page); 119EXPORT_SYMBOL(flush_dcache_page);
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 00bb8fd37a59..7110e54182b1 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -170,3 +170,50 @@ void __iounmap(void __iomem *addr)
170 vfree((void *) (PAGE_MASK & (unsigned long) addr)); 170 vfree((void *) (PAGE_MASK & (unsigned long) addr));
171} 171}
172EXPORT_SYMBOL(__iounmap); 172EXPORT_SYMBOL(__iounmap);
173
174#ifdef __io
175void __iomem *ioport_map(unsigned long port, unsigned int nr)
176{
177 return __io(port);
178}
179EXPORT_SYMBOL(ioport_map);
180
181void ioport_unmap(void __iomem *addr)
182{
183}
184EXPORT_SYMBOL(ioport_unmap);
185#endif
186
187#ifdef CONFIG_PCI
188#include <linux/pci.h>
189#include <linux/ioport.h>
190
191void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
192{
193 unsigned long start = pci_resource_start(dev, bar);
194 unsigned long len = pci_resource_len(dev, bar);
195 unsigned long flags = pci_resource_flags(dev, bar);
196
197 if (!len || !start)
198 return NULL;
199 if (maxlen && len > maxlen)
200 len = maxlen;
201 if (flags & IORESOURCE_IO)
202 return ioport_map(start, len);
203 if (flags & IORESOURCE_MEM) {
204 if (flags & IORESOURCE_CACHEABLE)
205 return ioremap(start, len);
206 return ioremap_nocache(start, len);
207 }
208 return NULL;
209}
210EXPORT_SYMBOL(pci_iomap);
211
212void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
213{
214 if ((unsigned long)addr >= VMALLOC_START &&
215 (unsigned long)addr < VMALLOC_END)
216 iounmap(addr);
217}
218EXPORT_SYMBOL(pci_iounmap);
219#endif
diff --git a/arch/arm/mm/minicache.c b/arch/arm/mm/minicache.c
deleted file mode 100644
index dedf2ab01b2a..000000000000
--- a/arch/arm/mm/minicache.c
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * linux/arch/arm/mm/minicache.c
3 *
4 * Copyright (C) 2001 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This handles the mini data cache, as found on SA11x0 and XScale
11 * processors. When we copy a user page page, we map it in such a way
12 * that accesses to this page will not touch the main data cache, but
13 * will be cached in the mini data cache. This prevents us thrashing
14 * the main data cache on page faults.
15 */
16#include <linux/init.h>
17#include <linux/mm.h>
18
19#include <asm/page.h>
20#include <asm/pgtable.h>
21#include <asm/tlbflush.h>
22
23/*
24 * 0xffff8000 to 0xffffffff is reserved for any ARM architecture
25 * specific hacks for copying pages efficiently.
26 */
27#define minicache_address (0xffff8000)
28#define minicache_pgprot __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | \
29 L_PTE_CACHEABLE)
30
31static pte_t *minicache_pte;
32
33/*
34 * Note that this is intended to be called only from the copy_user_page
35 * asm code; anything else will require special locking to prevent the
36 * mini-cache space being re-used. (Note: probably preempt unsafe).
37 *
38 * We rely on the fact that the minicache is 2K, and we'll be pushing
39 * 4K of data through it, so we don't actually have to specifically
40 * flush the minicache when we change the mapping.
41 *
42 * Note also: assert(PAGE_OFFSET <= virt < high_memory).
43 * Unsafe: preempt, kmap.
44 */
45unsigned long map_page_minicache(unsigned long virt)
46{
47 set_pte(minicache_pte, pfn_pte(__pa(virt) >> PAGE_SHIFT, minicache_pgprot));
48 flush_tlb_kernel_page(minicache_address);
49
50 return minicache_address;
51}
52
53static int __init minicache_init(void)
54{
55 pgd_t *pgd;
56 pmd_t *pmd;
57
58 spin_lock(&init_mm.page_table_lock);
59
60 pgd = pgd_offset_k(minicache_address);
61 pmd = pmd_alloc(&init_mm, pgd, minicache_address);
62 if (!pmd)
63 BUG();
64 minicache_pte = pte_alloc_kernel(&init_mm, pmd, minicache_address);
65 if (!minicache_pte)
66 BUG();
67
68 spin_unlock(&init_mm.page_table_lock);
69
70 return 0;
71}
72
73core_initcall(minicache_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 17:02:05 -0500