Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6 into devel

9 files changed, 480 insertions, 34 deletions

diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 85ed0b33331f..0ccc91c92c44 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -24,6 +24,7 @@
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
+#include <asm/mach-types.h>
 
 #include <mach/pxa-regs.h>
 #include <mach/reset.h>
@@ -39,6 +40,21 @@ void clear_reset_status(unsigned int mask)
                 pxa3xx_clear_reset_status(mask);
 }
 
+unsigned long get_clock_tick_rate(void)
+{
+        unsigned long clock_tick_rate;
+
+        if (cpu_is_pxa25x())
+                clock_tick_rate = 3686400;
+        else if (machine_is_mainstone())
+                clock_tick_rate = 3249600;
+        else
+                clock_tick_rate = 3250000;
+
+        return clock_tick_rate;
+}
+EXPORT_SYMBOL(get_clock_tick_rate);
+
 /*
  * Get the clock frequency as reflected by CCCR and the turbo flag.
  * We assume these values have been applied via a fcs.
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index 4e782ec38668..16ab79547dae 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -291,6 +291,8 @@
  */
 extern unsigned int get_memclk_frequency_10khz(void);
 
+/* return the clock tick rate of the OS timer */
+extern unsigned long get_clock_tick_rate(void);
 #endif
 
 #if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
index fabd9b4df827..fa73f56a1372 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
@@ -421,6 +421,7 @@
 #define GPIO20_PWM0             MFP_CFG_LPM(GPIO20, AF2, PULL_LOW)
 #define GPIO21_PWM2             MFP_CFG_LPM(GPIO21, AF3, PULL_LOW)
 #define GPIO22_PWM3             MFP_CFG_LPM(GPIO22, AF3, PULL_LOW)
+#define GPIO32_PWM0             MFP_CFG_LPM(GPIO32, AF4, PULL_LOW)
 
 /* CIR */
 #define GPIO46_CIR_OUT          MFP_CFG(GPIO46, AF1)
diff --git a/arch/arm/mach-pxa/include/mach/pxafb.h b/arch/arm/mach-pxa/include/mach/pxafb.h
index 4201a889ff4e..6932720ba04e 100644
--- a/arch/arm/mach-pxa/include/mach/pxafb.h
+++ b/arch/arm/mach-pxa/include/mach/pxafb.h
@@ -113,6 +113,7 @@ struct pxafb_mach_info {
         unsigned int num_modes;
 
         unsigned int    lcd_conn;
+        unsigned long   video_mem_size;
 
         u_int           fixed_modes:1,
                         cmap_inverse:1,
diff --git a/arch/arm/mach-pxa/include/mach/regs-lcd.h b/arch/arm/mach-pxa/include/mach/regs-lcd.h
index f817878d256b..f82dcea792d9 100644
--- a/arch/arm/mach-pxa/include/mach/regs-lcd.h
+++ b/arch/arm/mach-pxa/include/mach/regs-lcd.h
@@ -12,27 +12,29 @@
 #define LCCR3           (0x00C) /* LCD Controller Control Register 3 */
 #define LCCR4           (0x010) /* LCD Controller Control Register 4 */
 #define LCCR5           (0x014) /* LCD Controller Control Register 5 */
-#define DFBR0           (0x020) /* DMA Channel 0 Frame Branch Register */
-#define DFBR1           (0x024) /* DMA Channel 1 Frame Branch Register */
-#define LCSR            (0x038) /* LCD Controller Status Register */
+#define LCSR            (0x038) /* LCD Controller Status Register 0 */
+#define LCSR1           (0x034) /* LCD Controller Status Register 1 */
 #define LIIDR           (0x03C) /* LCD Controller Interrupt ID Register */
 #define TMEDRGBR        (0x040) /* TMED RGB Seed Register */
 #define TMEDCR          (0x044) /* TMED Control Register */
 
+#define FBR0            (0x020) /* DMA Channel 0 Frame Branch Register */
+#define FBR1            (0x024) /* DMA Channel 1 Frame Branch Register */
+#define FBR2            (0x028) /* DMA Channel 2 Frame Branch Register */
+#define FBR3            (0x02C) /* DMA Channel 2 Frame Branch Register */
+#define FBR4            (0x030) /* DMA Channel 2 Frame Branch Register */
+#define FBR5            (0x110) /* DMA Channel 2 Frame Branch Register */
+#define FBR6            (0x114) /* DMA Channel 2 Frame Branch Register */
+
+#define OVL1C1          (0x050) /* Overlay 1 Control Register 1 */
+#define OVL1C2          (0x060) /* Overlay 1 Control Register 2 */
+#define OVL2C1          (0x070) /* Overlay 2 Control Register 1 */
+#define OVL2C2          (0x080) /* Overlay 2 Control Register 2 */
+
 #define CMDCR           (0x100) /* Command Control Register */
 #define PRSR            (0x104) /* Panel Read Status Register */
 
-#define LCCR3_1BPP      (0 << 24)
-#define LCCR3_2BPP      (1 << 24)
-#define LCCR3_4BPP      (2 << 24)
-#define LCCR3_8BPP      (3 << 24)
-#define LCCR3_16BPP     (4 << 24)
-#define LCCR3_18BPP     (5 << 24)
-#define LCCR3_18BPP_P   (6 << 24)
-#define LCCR3_19BPP     (7 << 24)
-#define LCCR3_19BPP_P   (1 << 29)
-#define LCCR3_24BPP     ((1 << 29) | (1 << 24))
-#define LCCR3_25BPP     ((1 << 29) | (2 << 24))
+#define LCCR3_BPP(x)    ((((x) & 0x7) << 24) | (((x) & 0x8) ? (1 << 29) : 0))
 
 #define LCCR3_PDFOR_0   (0 << 30)
 #define LCCR3_PDFOR_1   (1 << 30)
@@ -42,19 +44,16 @@
 #define LCCR4_PAL_FOR_0 (0 << 15)
 #define LCCR4_PAL_FOR_1 (1 << 15)
 #define LCCR4_PAL_FOR_2 (2 << 15)
+#define LCCR4_PAL_FOR_3 (3 << 15)
 #define LCCR4_PAL_FOR_MASK      (3 << 15)
 
 #define FDADR0          (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
-#define FSADR0          (0x204) /* DMA Channel 0 Frame Source Address Register */
-#define FIDR0           (0x208) /* DMA Channel 0 Frame ID Register */
-#define LDCMD0          (0x20C) /* DMA Channel 0 Command Register */
 #define FDADR1          (0x210) /* DMA Channel 1 Frame Descriptor Address Register */
-#define FSADR1          (0x214) /* DMA Channel 1 Frame Source Address Register */
-#define FIDR1           (0x218) /* DMA Channel 1 Frame ID Register */
-#define LDCMD1          (0x21C) /* DMA Channel 1 Command Register */
+#define FDADR2          (0x220) /* DMA Channel 2 Frame Descriptor Address Register */
+#define FDADR3          (0x230) /* DMA Channel 3 Frame Descriptor Address Register */
+#define FDADR4          (0x240) /* DMA Channel 4 Frame Descriptor Address Register */
+#define FDADR5          (0x250) /* DMA Channel 5 Frame Descriptor Address Register */
 #define FDADR6          (0x260) /* DMA Channel 6 Frame Descriptor Address Register */
-#define FSADR6          (0x264) /* DMA Channel 6 Frame Source Address Register */
-#define FIDR6           (0x268) /* DMA Channel 6 Frame ID Register */
 
 #define LCCR0_ENB       (1 << 0)        /* LCD Controller enable */
 #define LCCR0_CMS       (1 << 1)        /* Color/Monochrome Display Select */
@@ -126,9 +125,6 @@
 #define LCCR3_PCD       Fld (8, 0)      /* Pixel Clock Divisor */
 #define LCCR3_PixClkDiv(Div)    (((Div) << FShft (LCCR3_PCD)))
 
-#define LCCR3_BPP       Fld (3, 24)     /* Bit Per Pixel */
-#define LCCR3_Bpp(Bpp)  (((Bpp) << FShft (LCCR3_BPP)))
-
 #define LCCR3_ACB       Fld (8, 8)      /* AC Bias */
 #define LCCR3_Acb(Acb)  (((Acb) << FShft (LCCR3_ACB)))
 
@@ -157,8 +153,22 @@
 #define LCSR_RD_ST      (1 << 11)       /* read status */
 #define LCSR_CMD_INT    (1 << 12)       /* command interrupt */
 
+#define LCSR1_IU(x)     (1 << ((x) + 23)) /* Input FIFO underrun */
+#define LCSR1_BS(x)     (1 << ((x) + 15)) /* Branch Status */
+#define LCSR1_EOF(x)    (1 << ((x) + 7))  /* End of Frame Status */
+#define LCSR1_SOF(x)    (1 << ((x) - 1))  /* Start of Frame Status */
+
 #define LDCMD_PAL       (1 << 26)       /* instructs DMA to load palette buffer */
 
+/* overlay control registers */
+#define OVLxC1_PPL(x)   ((((x) - 1) & 0x3ff) << 0)      /* Pixels Per Line */
+#define OVLxC1_LPO(x)   ((((x) - 1) & 0x3ff) << 10)     /* Number of Lines */
+#define OVLxC1_BPP(x)   (((x) & 0xf) << 20)     /* Bits Per Pixel */
+#define OVLxC1_OEN      (1 << 31)               /* Enable bit for Overlay */
+#define OVLxC2_XPOS(x)  (((x) & 0x3ff) << 0)    /* Horizontal Position */
+#define OVLxC2_YPOS(x)  (((x) & 0x3ff) << 10)   /* Vertical Position */
+#define OVL2C2_PFOR(x)  (((x) & 0x7) << 20)     /* Pixel Format */
+
 /* smartpanel related */
 #define PRSR_DATA(x)    ((x) & 0xff)    /* Panel Data */
 #define PRSR_A0         (1 << 8)        /* Read Data Source */
diff --git a/arch/arm/mach-pxa/include/mach/timex.h b/arch/arm/mach-pxa/include/mach/timex.h
index b05fc6683c47..af6760a50e1a 100644
--- a/arch/arm/mach-pxa/include/mach/timex.h
+++ b/arch/arm/mach-pxa/include/mach/timex.h
@@ -10,6 +10,14 @@
  * published by the Free Software Foundation.
  */
 
+/* Various drivers are still using the constant of CLOCK_TICK_RATE, for
+ * those drivers to at least work, the definition is provided here.
+ *
+ * NOTE: this is no longer accurate when multiple processors and boards
+ * are selected, newer drivers should not depend on this any more.  Use
+ * either the clocksource/clockevent or get this at run-time by calling
+ * get_clock_tick_rate() (as defined in generic.c).
+ */
 
 #if defined(CONFIG_PXA25x)
 /* PXA250/210 timer base */
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index 589d32b4fc46..58ef08a5224b 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -18,12 +18,15 @@
 #include <linux/clk.h>
 #include <linux/gpio.h>
 #include <linux/smc91x.h>
+#include <linux/pwm_backlight.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/hardware.h>
 #include <mach/pxa3xx-regs.h>
 #include <mach/mfp-pxa930.h>
+#include <mach/pxafb.h>
+#include <mach/pxa27x_keypad.h>
 
 #include "devices.h"
 #include "generic.h"
@@ -33,6 +36,45 @@ static mfp_cfg_t tavorevb_mfp_cfg[] __initdata = {
         /* Ethernet */
         DF_nCS1_nCS3,
         GPIO47_GPIO,
+
+        /* LCD */
+        GPIO23_LCD_DD0,
+        GPIO24_LCD_DD1,
+        GPIO25_LCD_DD2,
+        GPIO26_LCD_DD3,
+        GPIO27_LCD_DD4,
+        GPIO28_LCD_DD5,
+        GPIO29_LCD_DD6,
+        GPIO44_LCD_DD7,
+        GPIO21_LCD_CS,
+        GPIO22_LCD_CS2,
+
+        GPIO17_LCD_FCLK_RD,
+        GPIO18_LCD_LCLK_A0,
+        GPIO19_LCD_PCLK_WR,
+
+        /* LCD Backlight */
+        GPIO43_PWM3,    /* primary backlight */
+        GPIO32_PWM0,    /* secondary backlight */
+
+        /* Keypad */
+        GPIO0_KP_MKIN_0,
+        GPIO2_KP_MKIN_1,
+        GPIO4_KP_MKIN_2,
+        GPIO6_KP_MKIN_3,
+        GPIO8_KP_MKIN_4,
+        GPIO10_KP_MKIN_5,
+        GPIO12_KP_MKIN_6,
+        GPIO1_KP_MKOUT_0,
+        GPIO3_KP_MKOUT_1,
+        GPIO5_KP_MKOUT_2,
+        GPIO7_KP_MKOUT_3,
+        GPIO9_KP_MKOUT_4,
+        GPIO11_KP_MKOUT_5,
+        GPIO13_KP_MKOUT_6,
+
+        GPIO14_KP_DKIN_2,
+        GPIO15_KP_DKIN_3,
 };
 
 #define TAVOREVB_ETH_PHYS       (0x14000000)
@@ -64,12 +106,382 @@ static struct platform_device smc91x_device = {
         },
 };
 
+#if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
+static unsigned int tavorevb_matrix_key_map[] = {
+        /* KEY(row, col, key_code) */
+        KEY(0, 4, KEY_A), KEY(0, 5, KEY_B), KEY(0, 6, KEY_C),
+        KEY(1, 4, KEY_E), KEY(1, 5, KEY_F), KEY(1, 6, KEY_G),
+        KEY(2, 4, KEY_I), KEY(2, 5, KEY_J), KEY(2, 6, KEY_K),
+        KEY(3, 4, KEY_M), KEY(3, 5, KEY_N), KEY(3, 6, KEY_O),
+        KEY(4, 5, KEY_R), KEY(4, 6, KEY_S),
+        KEY(5, 4, KEY_U), KEY(5, 4, KEY_V), KEY(5, 6, KEY_W),
+
+        KEY(6, 4, KEY_Y), KEY(6, 5, KEY_Z),
+
+        KEY(0, 3, KEY_0), KEY(2, 0, KEY_1), KEY(2, 1, KEY_2), KEY(2, 2, KEY_3),
+        KEY(2, 3, KEY_4), KEY(1, 0, KEY_5), KEY(1, 1, KEY_6), KEY(1, 2, KEY_7),
+        KEY(1, 3, KEY_8), KEY(0, 2, KEY_9),
+
+        KEY(6, 6, KEY_SPACE),
+        KEY(0, 0, KEY_KPASTERISK),      /* * */
+        KEY(0, 1, KEY_KPDOT),           /* # */
+
+        KEY(4, 1, KEY_UP),
+        KEY(4, 3, KEY_DOWN),
+        KEY(4, 0, KEY_LEFT),
+        KEY(4, 2, KEY_RIGHT),
+        KEY(6, 0, KEY_HOME),
+        KEY(3, 2, KEY_END),
+        KEY(6, 1, KEY_DELETE),
+        KEY(5, 2, KEY_BACK),
+        KEY(6, 3, KEY_CAPSLOCK),        /* KEY_LEFTSHIFT), */
+
+        KEY(4, 4, KEY_ENTER),           /* scroll push */
+        KEY(6, 2, KEY_ENTER),           /* keypad action */
+
+        KEY(3, 1, KEY_SEND),
+        KEY(5, 3, KEY_RECORD),
+        KEY(5, 0, KEY_VOLUMEUP),
+        KEY(5, 1, KEY_VOLUMEDOWN),
+
+        KEY(3, 0, KEY_F22),     /* soft1 */
+        KEY(3, 3, KEY_F23),     /* soft2 */
+};
+
+static struct pxa27x_keypad_platform_data tavorevb_keypad_info = {
+        .matrix_key_rows        = 7,
+        .matrix_key_cols        = 7,
+        .matrix_key_map         = tavorevb_matrix_key_map,
+        .matrix_key_map_size    = ARRAY_SIZE(tavorevb_matrix_key_map),
+        .debounce_interval      = 30,
+};
+
+static void __init tavorevb_init_keypad(void)
+{
+        pxa_set_keypad_info(&tavorevb_keypad_info);
+}
+#else
+static inline void tavorevb_init_keypad(void) {}
+#endif /* CONFIG_KEYBOARD_PXA27x || CONFIG_KEYBOARD_PXA27x_MODULE */
+
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+static struct platform_pwm_backlight_data tavorevb_backlight_data[] = {
+        [0] = {
+                /* primary backlight */
+                .pwm_id         = 2,
+                .max_brightness = 100,
+                .dft_brightness = 100,
+                .pwm_period_ns  = 100000,
+        },
+        [1] = {
+                /* secondary backlight */
+                .pwm_id         = 0,
+                .max_brightness = 100,
+                .dft_brightness = 100,
+                .pwm_period_ns  = 100000,
+        },
+};
+
+static struct platform_device tavorevb_backlight_devices[] = {
+        [0] = {
+                .name           = "pwm-backlight",
+                .id             = 0,
+                .dev            = {
+                        .platform_data = &tavorevb_backlight_data[0],
+                },
+        },
+        [1] = {
+                .name           = "pwm-backlight",
+                .id             = 1,
+                .dev            = {
+                        .platform_data = &tavorevb_backlight_data[1],
+                },
+        },
+};
+
+static uint16_t panel_init[] = {
+        /* DSTB OUT */
+        SMART_CMD(0x00),
+        SMART_CMD_NOOP,
+        SMART_DELAY(1),
+
+        SMART_CMD(0x00),
+        SMART_CMD_NOOP,
+        SMART_DELAY(1),
+
+        SMART_CMD(0x00),
+        SMART_CMD_NOOP,
+        SMART_DELAY(1),
+
+        /* STB OUT */
+        SMART_CMD(0x00),
+        SMART_CMD(0x1D),
+        SMART_DAT(0x00),
+        SMART_DAT(0x05),
+        SMART_DELAY(1),
+
+        /* P-ON Init sequence */
+        SMART_CMD(0x00), /* OSC ON */
+        SMART_CMD(0x00),
+        SMART_DAT(0x00),
+        SMART_DAT(0x01),
+        SMART_CMD(0x00),
+        SMART_CMD(0x01), /* SOURCE DRIVER SHIFT DIRECTION and display RAM setting */
+        SMART_DAT(0x01),
+        SMART_DAT(0x27),
+        SMART_CMD(0x00),
+        SMART_CMD(0x02), /* LINE INV */
+        SMART_DAT(0x02),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),
+        SMART_CMD(0x03), /* IF mode(1) */
+        SMART_DAT(0x01), /* 8bit smart mode(8-8),high speed write mode */
+        SMART_DAT(0x30),
+        SMART_CMD(0x07),
+        SMART_CMD(0x00), /* RAM Write Mode */
+        SMART_DAT(0x00),
+        SMART_DAT(0x03),
+        SMART_CMD(0x00),
+
+        /* DISPLAY Setting,  262K, fixed(NO scroll), no split screen */
+        SMART_CMD(0x07),
+        SMART_DAT(0x40), /* 16/18/19 BPP */
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),
+        SMART_CMD(0x08), /* BP, FP Seting, BP=2H, FP=3H */
+        SMART_DAT(0x03),
+        SMART_DAT(0x02),
+        SMART_CMD(0x00),
+        SMART_CMD(0x0C), /* IF mode(2), using internal clock & MPU */
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),
+        SMART_CMD(0x0D), /* Frame setting, 1Min. Frequence, 16CLK */
+        SMART_DAT(0x00),
+        SMART_DAT(0x10),
+        SMART_CMD(0x00),
+        SMART_CMD(0x12), /* Timing(1),ASW W=4CLK, ASW ST=1CLK */
+        SMART_DAT(0x03),
+        SMART_DAT(0x02),
+        SMART_CMD(0x00),
+        SMART_CMD(0x13), /* Timing(2),OEV ST=0.5CLK, OEV ED=1CLK */
+        SMART_DAT(0x01),
+        SMART_DAT(0x02),
+        SMART_CMD(0x00),
+        SMART_CMD(0x14), /* Timing(3), ASW HOLD=0.5CLK */
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),
+        SMART_CMD(0x15), /* Timing(4), CKV ST=0CLK, CKV ED=1CLK */
+        SMART_DAT(0x20),
+        SMART_DAT(0x00),
+        SMART_CMD(0x00),
+        SMART_CMD(0x1C),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x03),
+        SMART_CMD(0x00),
+        SMART_DAT(0x04),
+        SMART_DAT(0x03),
+        SMART_CMD(0x03),
+        SMART_CMD(0x01),
+        SMART_DAT(0x03),
+        SMART_DAT(0x04),
+        SMART_CMD(0x03),
+        SMART_CMD(0x02),
+        SMART_DAT(0x04),
+        SMART_DAT(0x03),
+        SMART_CMD(0x03),
+        SMART_CMD(0x03),
+        SMART_DAT(0x03),
+        SMART_DAT(0x03),
+        SMART_CMD(0x03),
+        SMART_CMD(0x04),
+        SMART_DAT(0x01),
+        SMART_DAT(0x01),
+        SMART_CMD(0x03),
+        SMART_CMD(0x05),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x04),
+        SMART_CMD(0x02),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x04),
+        SMART_CMD(0x03),
+        SMART_DAT(0x01),
+        SMART_DAT(0x3F),
+        SMART_DELAY(0),
+
+        /* DISP RAM setting: 240*320 */
+        SMART_CMD(0x04), /* HADDR, START 0 */
+        SMART_CMD(0x06),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00), /* x1,3 */
+        SMART_CMD(0x04), /* HADDR,  END   4 */
+        SMART_CMD(0x07),
+        SMART_DAT(0x00),
+        SMART_DAT(0xEF), /* x2, 7 */
+        SMART_CMD(0x04), /* VADDR, START 8 */
+        SMART_CMD(0x08),
+        SMART_DAT(0x00), /* y1, 10 */
+        SMART_DAT(0x00), /* y1, 11 */
+        SMART_CMD(0x04), /* VADDR, END 12 */
+        SMART_CMD(0x09),
+        SMART_DAT(0x01), /* y2, 14 */
+        SMART_DAT(0x3F), /* y2, 15 */
+        SMART_CMD(0x02), /* RAM ADDR SETTING 16 */
+        SMART_CMD(0x00),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00), /* x1, 19 */
+        SMART_CMD(0x02), /* RAM ADDR SETTING 20 */
+        SMART_CMD(0x01),
+        SMART_DAT(0x00), /* y1, 22 */
+        SMART_DAT(0x00), /* y1, 23 */
+};
+
+static uint16_t panel_on[] = {
+        /* Power-IC ON */
+        SMART_CMD(0x01),
+        SMART_CMD(0x02),
+        SMART_DAT(0x07),
+        SMART_DAT(0x7D),
+        SMART_CMD(0x01),
+        SMART_CMD(0x03),
+        SMART_DAT(0x00),
+        SMART_DAT(0x05),
+        SMART_CMD(0x01),
+        SMART_CMD(0x04),
+        SMART_DAT(0x00),
+        SMART_DAT(0x00),
+        SMART_CMD(0x01),
+        SMART_CMD(0x05),
+        SMART_DAT(0x00),
+        SMART_DAT(0x15),
+        SMART_CMD(0x01),
+        SMART_CMD(0x00),
+        SMART_DAT(0xC0),
+        SMART_DAT(0x10),
+        SMART_DELAY(30),
+
+        /* DISP ON */
+        SMART_CMD(0x01),
+        SMART_CMD(0x01),
+        SMART_DAT(0x00),
+        SMART_DAT(0x01),
+        SMART_CMD(0x01),
+        SMART_CMD(0x00),
+        SMART_DAT(0xFF),
+        SMART_DAT(0xFE),
+        SMART_DELAY(150),
+};
+
+static uint16_t panel_off[] = {
+        SMART_CMD(0x00),
+        SMART_CMD(0x1E),
+        SMART_DAT(0x00),
+        SMART_DAT(0x0A),
+        SMART_CMD(0x01),
+        SMART_CMD(0x00),
+        SMART_DAT(0xFF),
+        SMART_DAT(0xEE),
+        SMART_CMD(0x01),
+        SMART_CMD(0x00),
+        SMART_DAT(0xF8),
+        SMART_DAT(0x12),
+        SMART_CMD(0x01),
+        SMART_CMD(0x00),
+        SMART_DAT(0xE8),
+        SMART_DAT(0x11),
+        SMART_CMD(0x01),
+        SMART_CMD(0x00),
+        SMART_DAT(0xC0),
+        SMART_DAT(0x11),
+        SMART_CMD(0x01),
+        SMART_CMD(0x00),
+        SMART_DAT(0x40),
+        SMART_DAT(0x11),
+        SMART_CMD(0x01),
+        SMART_CMD(0x00),
+        SMART_DAT(0x00),
+        SMART_DAT(0x10),
+};
+
+static uint16_t update_framedata[] = {
+        /* write ram */
+        SMART_CMD(0x02),
+        SMART_CMD(0x02),
+
+        /* write frame data */
+        SMART_CMD_WRITE_FRAME,
+};
+
+static void ltm020d550_lcd_power(int on, struct fb_var_screeninfo *var)
+{
+        struct fb_info *info = container_of(var, struct fb_info, var);
+
+        if (on) {
+                pxafb_smart_queue(info, ARRAY_AND_SIZE(panel_init));
+                pxafb_smart_queue(info, ARRAY_AND_SIZE(panel_on));
+        } else {
+                pxafb_smart_queue(info, ARRAY_AND_SIZE(panel_off));
+        }
+
+        if (pxafb_smart_flush(info))
+                pr_err("%s: timed out\n", __func__);
+}
+
+static void ltm020d550_update(struct fb_info *info)
+{
+        pxafb_smart_queue(info, ARRAY_AND_SIZE(update_framedata));
+        pxafb_smart_flush(info);
+}
+
+static struct pxafb_mode_info toshiba_ltm020d550_modes[] = {
+        [0] = {
+                .xres                   = 240,
+                .yres                   = 320,
+                .bpp                    = 16,
+                .a0csrd_set_hld         = 30,
+                .a0cswr_set_hld         = 30,
+                .wr_pulse_width         = 30,
+                .rd_pulse_width         = 170,
+                .op_hold_time           = 30,
+                .cmd_inh_time           = 60,
+
+                /* L_LCLK_A0 and L_LCLK_RD active low */
+                .sync                   = FB_SYNC_HOR_HIGH_ACT |
+                                          FB_SYNC_VERT_HIGH_ACT,
+        },
+};
+
+static struct pxafb_mach_info tavorevb_lcd_info = {
+        .modes                  = toshiba_ltm020d550_modes,
+        .num_modes              = 1,
+        .lcd_conn               = LCD_SMART_PANEL_8BPP | LCD_PCLK_EDGE_FALL,
+        .pxafb_lcd_power        = ltm020d550_lcd_power,
+        .smart_update           = ltm020d550_update,
+};
+
+static void __init tavorevb_init_lcd(void)
+{
+        platform_device_register(&tavorevb_backlight_devices[0]);
+        platform_device_register(&tavorevb_backlight_devices[1]);
+        set_pxa_fb_info(&tavorevb_lcd_info);
+}
+#else
+static inline void tavorevb_init_lcd(void) {}
+#endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */
+
 static void __init tavorevb_init(void)
 {
         /* initialize MFP configurations */
         pxa3xx_mfp_config(ARRAY_AND_SIZE(tavorevb_mfp_cfg));
 
         platform_device_register(&smc91x_device);
+
+        tavorevb_init_lcd();
+        tavorevb_init_keypad();
 }
 
 MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)")
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index ef4ddf9d5040..001624158519 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -24,7 +24,6 @@
 #include <asm/mach/time.h>
 #include <mach/hardware.h>
 #include <mach/pxa-regs.h>
-#include <asm/mach-types.h>
 
 /*
  * This is PXA's sched_clock implementation. This has a resolution
@@ -151,18 +150,11 @@ static struct irqaction pxa_ost0_irq = {
 
 static void __init pxa_timer_init(void)
 {
-        unsigned long clock_tick_rate;
+        unsigned long clock_tick_rate = get_clock_tick_rate();
 
         OIER = 0;
         OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
 
-        if (cpu_is_pxa25x())
-                clock_tick_rate = 3686400;
-        else if (machine_is_mainstone())
-                clock_tick_rate = 3249600;
-        else
-                clock_tick_rate = 3250000;
-
         set_oscr2ns_scale(clock_tick_rate);
 
         ckevt_pxa_osmr0.mult =
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
index b70846c096aa..60711822b125 100644
--- a/arch/arm/mach-sa1100/include/mach/hardware.h
+++ b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -59,6 +59,10 @@
 # define __REG(x)       (*((volatile unsigned long *)io_p2v(x)))
 # define __PREG(x)      (io_v2p((unsigned long)&(x)))
 
+static inline unsigned long get_clock_tick_rate(void)
+{
+        return 3686400;
+}
 #else
 
 # define __REG(x)       io_p2v(x)