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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-06-14 06:01:05 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-06-14 06:01:05 -0400
commit06099961002a813324d057a91695af7c72939da6 (patch)
treed55ee7a8833c95ee2afb6914bb8a2977cbb9fa31 /arch/arm
parent4c31791c3d9d38ac052dd5e2981df713d8f3dcc4 (diff)
parentc11c22177ae2929598051a39e4655be4a42cb805 (diff)
Merge branch 'stmp' into devel
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig15
-rw-r--r--arch/arm/Makefile3
-rw-r--r--arch/arm/configs/stmp378x_defconfig1141
-rw-r--r--arch/arm/configs/stmp37xx_defconfig1002
-rw-r--r--arch/arm/mach-stmp378x/Makefile2
-rw-r--r--arch/arm/mach-stmp378x/Makefile.boot3
-rw-r--r--arch/arm/mach-stmp378x/include/mach/entry-macro.S35
-rw-r--r--arch/arm/mach-stmp378x/include/mach/irqs.h95
-rw-r--r--arch/arm/mach-stmp378x/include/mach/pins.h151
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-apbh.h101
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-apbx.h119
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-audioin.h63
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-audioout.h104
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-bch.h56
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h88
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-dcp.h87
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-digctl.h38
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-dram.h27
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-dri.h45
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-ecc8.h39
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-emi.h25
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-gpmi.h78
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-i2c.h55
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-icoll.h45
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-ir.h23
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-lcdif.h195
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-lradc.h99
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-ocotp.h40
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h90
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-power.h63
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-pwm.h53
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-pxp.h140
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-rtc.h59
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-saif.h21
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-spdif.h49
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-ssp.h102
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-sydma.h23
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-timrot.h68
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-tvenc.h67
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-uartapp.h87
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h268
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h40
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-usbphy.h37
-rw-r--r--arch/arm/mach-stmp378x/stmp378x.c299
-rw-r--r--arch/arm/mach-stmp378x/stmp378x.h25
-rw-r--r--arch/arm/mach-stmp378x/stmp378x_devb.c334
-rw-r--r--arch/arm/mach-stmp37xx/Makefile2
-rw-r--r--arch/arm/mach-stmp37xx/Makefile.boot3
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/entry-macro.S37
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/irqs.h99
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/pins.h147
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-apbh.h97
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-apbx.h113
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-audioin.h61
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-audioout.h111
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h72
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-digctl.h24
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h37
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h63
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-i2c.h55
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-icoll.h43
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h89
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-lradc.h97
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h88
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-power.h56
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-pwm.h51
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-rtc.h57
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-ssp.h101
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-timrot.h49
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h85
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h268
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h22
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h22
-rw-r--r--arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h37
-rw-r--r--arch/arm/mach-stmp37xx/stmp37xx.c219
-rw-r--r--arch/arm/mach-stmp37xx/stmp37xx.h24
-rw-r--r--arch/arm/mach-stmp37xx/stmp37xx_devb.c101
-rw-r--r--arch/arm/plat-stmp3xxx/Kconfig37
-rw-r--r--arch/arm/plat-stmp3xxx/Makefile5
-rw-r--r--arch/arm/plat-stmp3xxx/clock.c1135
-rw-r--r--arch/arm/plat-stmp3xxx/clock.h61
-rw-r--r--arch/arm/plat-stmp3xxx/core.c128
-rw-r--r--arch/arm/plat-stmp3xxx/devices.c389
-rw-r--r--arch/arm/plat-stmp3xxx/dma.c463
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/clkdev.h18
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/cputype.h33
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/debug-macro.S42
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/dma.h153
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/gpio.h28
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/gpmi.h12
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/hardware.h32
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/io.h25
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/memory.h22
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/mmc.h14
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/pinmux.h157
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/pins.h30
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/platform.h68
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h54
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/system.h49
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/timex.h20
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/uncompress.h53
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/vmalloc.h12
-rw-r--r--arch/arm/plat-stmp3xxx/irq.c51
-rw-r--r--arch/arm/plat-stmp3xxx/pinmux.c552
-rw-r--r--arch/arm/plat-stmp3xxx/timer.c189
105 files changed, 11761 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3473f8b8ede6..fee7c64ca723 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -298,6 +298,19 @@ config ARCH_MXC
298 help 298 help
299 Support for Freescale MXC/iMX-based family of processors 299 Support for Freescale MXC/iMX-based family of processors
300 300
301config ARCH_STMP3XXX
302 bool "Freescale STMP3xxx"
303 select CPU_ARM926T
304 select HAVE_CLK
305 select COMMON_CLKDEV
306 select ARCH_REQUIRE_GPIOLIB
307 select GENERIC_TIME
308 select GENERIC_CLOCKEVENTS
309 select GENERIC_GPIO
310 select USB_ARCH_HAS_EHCI
311 help
312 Support for systems based on the Freescale 3xxx CPUs.
313
301config ARCH_NETX 314config ARCH_NETX
302 bool "Hilscher NetX based" 315 bool "Hilscher NetX based"
303 select CPU_ARM926T 316 select CPU_ARM926T
@@ -673,6 +686,8 @@ source "arch/arm/mach-s3c6400/Kconfig"
673source "arch/arm/mach-s3c6410/Kconfig" 686source "arch/arm/mach-s3c6410/Kconfig"
674endif 687endif
675 688
689source "arch/arm/plat-stmp3xxx/Kconfig"
690
676source "arch/arm/mach-lh7a40x/Kconfig" 691source "arch/arm/mach-lh7a40x/Kconfig"
677 692
678source "arch/arm/mach-h720x/Kconfig" 693source "arch/arm/mach-h720x/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 0c25f2cb73a1..2f3cac809e31 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -152,6 +152,8 @@ machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
152machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 152machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410
153machine-$(CONFIG_ARCH_SA1100) := sa1100 153machine-$(CONFIG_ARCH_SA1100) := sa1100
154machine-$(CONFIG_ARCH_SHARK) := shark 154machine-$(CONFIG_ARCH_SHARK) := shark
155machine-$(CONFIG_ARCH_STMP378X) := stmp378x
156machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx
155machine-$(CONFIG_ARCH_VERSATILE) := versatile 157machine-$(CONFIG_ARCH_VERSATILE) := versatile
156machine-$(CONFIG_ARCH_W90X900) := w90x900 158machine-$(CONFIG_ARCH_W90X900) := w90x900
157machine-$(CONFIG_FOOTBRIDGE) := footbridge 159machine-$(CONFIG_FOOTBRIDGE) := footbridge
@@ -165,6 +167,7 @@ plat-$(CONFIG_PLAT_ORION) := orion
165plat-$(CONFIG_PLAT_PXA) := pxa 167plat-$(CONFIG_PLAT_PXA) := pxa
166plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c 168plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c
167plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c 169plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c
170plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx
168 171
169ifeq ($(CONFIG_ARCH_EBSA110),y) 172ifeq ($(CONFIG_ARCH_EBSA110),y)
170# This is what happens if you forget the IOCS16 line. 173# This is what happens if you forget the IOCS16 line.
diff --git a/arch/arm/configs/stmp378x_defconfig b/arch/arm/configs/stmp378x_defconfig
new file mode 100644
index 000000000000..44461f197a17
--- /dev/null
+++ b/arch/arm/configs/stmp378x_defconfig
@@ -0,0 +1,1141 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.30-rc2
4# Thu Apr 23 02:44:13 2009
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_HAVE_LATENCYTOP_SUPPORT=y
16CONFIG_LOCKDEP_SUPPORT=y
17CONFIG_TRACE_IRQFLAGS_SUPPORT=y
18CONFIG_HARDIRQS_SW_RESEND=y
19CONFIG_GENERIC_IRQ_PROBE=y
20CONFIG_RWSEM_GENERIC_SPINLOCK=y
21# CONFIG_ARCH_HAS_ILOG2_U32 is not set
22# CONFIG_ARCH_HAS_ILOG2_U64 is not set
23CONFIG_GENERIC_HWEIGHT=y
24CONFIG_GENERIC_CALIBRATE_DELAY=y
25CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
26CONFIG_VECTORS_BASE=0xffff0000
27CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
28
29#
30# General setup
31#
32CONFIG_EXPERIMENTAL=y
33CONFIG_BROKEN_ON_SMP=y
34CONFIG_LOCK_KERNEL=y
35CONFIG_INIT_ENV_ARG_LIMIT=32
36CONFIG_LOCALVERSION="-default"
37CONFIG_LOCALVERSION_AUTO=y
38CONFIG_SWAP=y
39CONFIG_SYSVIPC=y
40CONFIG_SYSVIPC_SYSCTL=y
41CONFIG_POSIX_MQUEUE=y
42CONFIG_POSIX_MQUEUE_SYSCTL=y
43CONFIG_BSD_PROCESS_ACCT=y
44# CONFIG_BSD_PROCESS_ACCT_V3 is not set
45# CONFIG_TASKSTATS is not set
46# CONFIG_AUDIT is not set
47
48#
49# RCU Subsystem
50#
51CONFIG_CLASSIC_RCU=y
52# CONFIG_TREE_RCU is not set
53# CONFIG_PREEMPT_RCU is not set
54# CONFIG_TREE_RCU_TRACE is not set
55# CONFIG_PREEMPT_RCU_TRACE is not set
56# CONFIG_IKCONFIG is not set
57CONFIG_LOG_BUF_SHIFT=17
58# CONFIG_GROUP_SCHED is not set
59# CONFIG_CGROUPS is not set
60CONFIG_SYSFS_DEPRECATED=y
61CONFIG_SYSFS_DEPRECATED_V2=y
62CONFIG_RELAY=y
63# CONFIG_NAMESPACES is not set
64CONFIG_BLK_DEV_INITRD=y
65CONFIG_INITRAMFS_SOURCE=""
66CONFIG_INITRAMFS_ROOT_UID=0
67CONFIG_INITRAMFS_ROOT_GID=0
68CONFIG_RD_GZIP=y
69# CONFIG_RD_BZIP2 is not set
70# CONFIG_RD_LZMA is not set
71# CONFIG_INITRAMFS_COMPRESSION_NONE is not set
72CONFIG_INITRAMFS_COMPRESSION_GZIP=y
73# CONFIG_INITRAMFS_COMPRESSION_BZIP2 is not set
74# CONFIG_INITRAMFS_COMPRESSION_LZMA is not set
75CONFIG_CC_OPTIMIZE_FOR_SIZE=y
76CONFIG_SYSCTL=y
77CONFIG_ANON_INODES=y
78CONFIG_EMBEDDED=y
79CONFIG_UID16=y
80CONFIG_SYSCTL_SYSCALL=y
81CONFIG_KALLSYMS=y
82CONFIG_KALLSYMS_ALL=y
83# CONFIG_KALLSYMS_EXTRA_PASS is not set
84CONFIG_STRIP_ASM_SYMS=y
85CONFIG_HOTPLUG=y
86CONFIG_PRINTK=y
87CONFIG_BUG=y
88CONFIG_ELF_CORE=y
89CONFIG_BASE_FULL=y
90CONFIG_FUTEX=y
91CONFIG_EPOLL=y
92CONFIG_SIGNALFD=y
93CONFIG_TIMERFD=y
94CONFIG_EVENTFD=y
95CONFIG_SHMEM=y
96CONFIG_AIO=y
97CONFIG_VM_EVENT_COUNTERS=y
98CONFIG_COMPAT_BRK=y
99CONFIG_SLAB=y
100# CONFIG_SLUB is not set
101# CONFIG_SLOB is not set
102# CONFIG_PROFILING is not set
103CONFIG_TRACEPOINTS=y
104CONFIG_MARKERS=y
105CONFIG_HAVE_OPROFILE=y
106# CONFIG_KPROBES is not set
107CONFIG_HAVE_KPROBES=y
108CONFIG_HAVE_KRETPROBES=y
109CONFIG_HAVE_CLK=y
110# CONFIG_SLOW_WORK is not set
111CONFIG_HAVE_GENERIC_DMA_COHERENT=y
112CONFIG_SLABINFO=y
113CONFIG_RT_MUTEXES=y
114CONFIG_BASE_SMALL=0
115CONFIG_MODULES=y
116# CONFIG_MODULE_FORCE_LOAD is not set
117CONFIG_MODULE_UNLOAD=y
118CONFIG_MODULE_FORCE_UNLOAD=y
119CONFIG_MODVERSIONS=y
120CONFIG_MODULE_SRCVERSION_ALL=y
121CONFIG_BLOCK=y
122CONFIG_LBD=y
123# CONFIG_BLK_DEV_BSG is not set
124# CONFIG_BLK_DEV_INTEGRITY is not set
125
126#
127# IO Schedulers
128#
129CONFIG_IOSCHED_NOOP=y
130CONFIG_IOSCHED_AS=y
131CONFIG_IOSCHED_DEADLINE=y
132CONFIG_IOSCHED_CFQ=y
133# CONFIG_DEFAULT_AS is not set
134# CONFIG_DEFAULT_DEADLINE is not set
135CONFIG_DEFAULT_CFQ=y
136# CONFIG_DEFAULT_NOOP is not set
137CONFIG_DEFAULT_IOSCHED="cfq"
138# CONFIG_FREEZER is not set
139
140#
141# System Type
142#
143# CONFIG_ARCH_AAEC2000 is not set
144# CONFIG_ARCH_INTEGRATOR is not set
145# CONFIG_ARCH_REALVIEW is not set
146# CONFIG_ARCH_VERSATILE is not set
147# CONFIG_ARCH_AT91 is not set
148# CONFIG_ARCH_CLPS711X is not set
149# CONFIG_ARCH_EBSA110 is not set
150# CONFIG_ARCH_EP93XX is not set
151# CONFIG_ARCH_GEMINI is not set
152# CONFIG_ARCH_FOOTBRIDGE is not set
153# CONFIG_ARCH_NETX is not set
154# CONFIG_ARCH_H720X is not set
155# CONFIG_ARCH_IMX is not set
156# CONFIG_ARCH_IOP13XX is not set
157# CONFIG_ARCH_IOP32X is not set
158# CONFIG_ARCH_IOP33X is not set
159# CONFIG_ARCH_IXP23XX is not set
160# CONFIG_ARCH_IXP2000 is not set
161# CONFIG_ARCH_IXP4XX is not set
162# CONFIG_ARCH_L7200 is not set
163# CONFIG_ARCH_KIRKWOOD is not set
164# CONFIG_ARCH_KS8695 is not set
165# CONFIG_ARCH_NS9XXX is not set
166# CONFIG_ARCH_LOKI is not set
167# CONFIG_ARCH_MV78XX0 is not set
168# CONFIG_ARCH_MXC is not set
169# CONFIG_ARCH_ORION5X is not set
170# CONFIG_ARCH_PNX4008 is not set
171# CONFIG_ARCH_PXA is not set
172# CONFIG_ARCH_MMP is not set
173# CONFIG_ARCH_RPC is not set
174# CONFIG_ARCH_SA1100 is not set
175# CONFIG_ARCH_S3C2410 is not set
176# CONFIG_ARCH_S3C64XX is not set
177# CONFIG_ARCH_SHARK is not set
178# CONFIG_ARCH_LH7A40X is not set
179# CONFIG_ARCH_DAVINCI is not set
180# CONFIG_ARCH_OMAP is not set
181# CONFIG_ARCH_MSM is not set
182# CONFIG_ARCH_W90X900 is not set
183CONFIG_ARCH_STMP3XXX=y
184
185#
186# Freescale STMP3xxx implementations
187#
188# CONFIG_ARCH_STMP37XX is not set
189CONFIG_ARCH_STMP378X=y
190# CONFIG_MACH_STMP37XX is not set
191CONFIG_MACH_STMP378X=y
192
193#
194# Processor Type
195#
196CONFIG_CPU_32=y
197CONFIG_CPU_ARM926T=y
198CONFIG_CPU_32v5=y
199CONFIG_CPU_ABRT_EV5TJ=y
200CONFIG_CPU_PABRT_NOIFAR=y
201CONFIG_CPU_CACHE_VIVT=y
202CONFIG_CPU_COPY_V4WB=y
203CONFIG_CPU_TLB_V4WBI=y
204CONFIG_CPU_CP15=y
205CONFIG_CPU_CP15_MMU=y
206
207#
208# Processor Features
209#
210CONFIG_ARM_THUMB=y
211# CONFIG_CPU_ICACHE_DISABLE is not set
212# CONFIG_CPU_DCACHE_DISABLE is not set
213# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
214# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
215# CONFIG_OUTER_CACHE is not set
216CONFIG_COMMON_CLKDEV=y
217
218#
219# Bus support
220#
221# CONFIG_PCI_SYSCALL is not set
222# CONFIG_ARCH_SUPPORTS_MSI is not set
223# CONFIG_PCCARD is not set
224
225#
226# Kernel Features
227#
228CONFIG_TICK_ONESHOT=y
229CONFIG_NO_HZ=y
230CONFIG_HIGH_RES_TIMERS=y
231CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
232CONFIG_VMSPLIT_3G=y
233# CONFIG_VMSPLIT_2G is not set
234# CONFIG_VMSPLIT_1G is not set
235CONFIG_PAGE_OFFSET=0xC0000000
236CONFIG_PREEMPT=y
237CONFIG_HZ=100
238CONFIG_AEABI=y
239CONFIG_OABI_COMPAT=y
240CONFIG_ARCH_FLATMEM_HAS_HOLES=y
241# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
242# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
243CONFIG_HIGHMEM=y
244CONFIG_SELECT_MEMORY_MODEL=y
245CONFIG_FLATMEM_MANUAL=y
246# CONFIG_DISCONTIGMEM_MANUAL is not set
247# CONFIG_SPARSEMEM_MANUAL is not set
248CONFIG_FLATMEM=y
249CONFIG_FLAT_NODE_MEM_MAP=y
250CONFIG_PAGEFLAGS_EXTENDED=y
251CONFIG_SPLIT_PTLOCK_CPUS=4096
252# CONFIG_PHYS_ADDR_T_64BIT is not set
253CONFIG_ZONE_DMA_FLAG=0
254CONFIG_BOUNCE=y
255CONFIG_VIRT_TO_BUS=y
256CONFIG_UNEVICTABLE_LRU=y
257CONFIG_HAVE_MLOCK=y
258CONFIG_HAVE_MLOCKED_PAGE_BIT=y
259CONFIG_ALIGNMENT_TRAP=y
260
261#
262# Boot options
263#
264CONFIG_ZBOOT_ROM_TEXT=0x0
265CONFIG_ZBOOT_ROM_BSS=0x0
266CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M"
267# CONFIG_XIP_KERNEL is not set
268# CONFIG_KEXEC is not set
269
270#
271# CPU Power Management
272#
273# CONFIG_CPU_IDLE is not set
274
275#
276# Floating point emulation
277#
278
279#
280# At least one emulation must be selected
281#
282# CONFIG_FPE_NWFPE is not set
283# CONFIG_FPE_FASTFPE is not set
284# CONFIG_VFP is not set
285
286#
287# Userspace binary formats
288#
289CONFIG_BINFMT_ELF=y
290# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
291CONFIG_HAVE_AOUT=y
292# CONFIG_BINFMT_AOUT is not set
293# CONFIG_BINFMT_MISC is not set
294
295#
296# Power management options
297#
298# CONFIG_PM is not set
299CONFIG_ARCH_SUSPEND_POSSIBLE=y
300CONFIG_NET=y
301
302#
303# Networking options
304#
305CONFIG_PACKET=y
306CONFIG_PACKET_MMAP=y
307CONFIG_UNIX=y
308CONFIG_XFRM=y
309# CONFIG_XFRM_USER is not set
310# CONFIG_XFRM_SUB_POLICY is not set
311# CONFIG_XFRM_MIGRATE is not set
312# CONFIG_XFRM_STATISTICS is not set
313# CONFIG_NET_KEY is not set
314CONFIG_INET=y
315CONFIG_IP_MULTICAST=y
316CONFIG_IP_ADVANCED_ROUTER=y
317CONFIG_ASK_IP_FIB_HASH=y
318# CONFIG_IP_FIB_TRIE is not set
319CONFIG_IP_FIB_HASH=y
320CONFIG_IP_MULTIPLE_TABLES=y
321CONFIG_IP_ROUTE_MULTIPATH=y
322CONFIG_IP_ROUTE_VERBOSE=y
323CONFIG_IP_PNP=y
324CONFIG_IP_PNP_DHCP=y
325CONFIG_IP_PNP_BOOTP=y
326# CONFIG_IP_PNP_RARP is not set
327# CONFIG_NET_IPIP is not set
328# CONFIG_NET_IPGRE is not set
329CONFIG_IP_MROUTE=y
330CONFIG_IP_PIMSM_V1=y
331CONFIG_IP_PIMSM_V2=y
332# CONFIG_ARPD is not set
333CONFIG_SYN_COOKIES=y
334# CONFIG_INET_AH is not set
335# CONFIG_INET_ESP is not set
336# CONFIG_INET_IPCOMP is not set
337# CONFIG_INET_XFRM_TUNNEL is not set
338# CONFIG_INET_TUNNEL is not set
339CONFIG_INET_XFRM_MODE_TRANSPORT=y
340CONFIG_INET_XFRM_MODE_TUNNEL=y
341CONFIG_INET_XFRM_MODE_BEET=y
342# CONFIG_INET_LRO is not set
343CONFIG_INET_DIAG=y
344CONFIG_INET_TCP_DIAG=y
345# CONFIG_TCP_CONG_ADVANCED is not set
346CONFIG_TCP_CONG_CUBIC=y
347CONFIG_DEFAULT_TCP_CONG="cubic"
348# CONFIG_TCP_MD5SIG is not set
349# CONFIG_IPV6 is not set
350# CONFIG_NETLABEL is not set
351# CONFIG_NETWORK_SECMARK is not set
352# CONFIG_NETFILTER is not set
353# CONFIG_IP_DCCP is not set
354# CONFIG_IP_SCTP is not set
355# CONFIG_TIPC is not set
356# CONFIG_ATM is not set
357# CONFIG_BRIDGE is not set
358# CONFIG_NET_DSA is not set
359# CONFIG_VLAN_8021Q is not set
360# CONFIG_DECNET is not set
361# CONFIG_LLC2 is not set
362# CONFIG_IPX is not set
363# CONFIG_ATALK is not set
364# CONFIG_X25 is not set
365# CONFIG_LAPB is not set
366# CONFIG_ECONET is not set
367# CONFIG_WAN_ROUTER is not set
368# CONFIG_PHONET is not set
369CONFIG_NET_SCHED=y
370
371#
372# Queueing/Scheduling
373#
374# CONFIG_NET_SCH_CBQ is not set
375# CONFIG_NET_SCH_HTB is not set
376# CONFIG_NET_SCH_HFSC is not set
377# CONFIG_NET_SCH_PRIO is not set
378# CONFIG_NET_SCH_MULTIQ is not set
379# CONFIG_NET_SCH_RED is not set
380# CONFIG_NET_SCH_SFQ is not set
381# CONFIG_NET_SCH_TEQL is not set
382# CONFIG_NET_SCH_TBF is not set
383# CONFIG_NET_SCH_GRED is not set
384# CONFIG_NET_SCH_DSMARK is not set
385# CONFIG_NET_SCH_NETEM is not set
386# CONFIG_NET_SCH_DRR is not set
387
388#
389# Classification
390#
391# CONFIG_NET_CLS_BASIC is not set
392# CONFIG_NET_CLS_TCINDEX is not set
393# CONFIG_NET_CLS_ROUTE4 is not set
394# CONFIG_NET_CLS_FW is not set
395# CONFIG_NET_CLS_U32 is not set
396# CONFIG_NET_CLS_RSVP is not set
397# CONFIG_NET_CLS_RSVP6 is not set
398# CONFIG_NET_CLS_FLOW is not set
399# CONFIG_NET_EMATCH is not set
400# CONFIG_NET_CLS_ACT is not set
401CONFIG_NET_SCH_FIFO=y
402# CONFIG_DCB is not set
403
404#
405# Network testing
406#
407# CONFIG_NET_PKTGEN is not set
408# CONFIG_NET_DROP_MONITOR is not set
409# CONFIG_HAMRADIO is not set
410# CONFIG_CAN is not set
411# CONFIG_IRDA is not set
412# CONFIG_BT is not set
413# CONFIG_AF_RXRPC is not set
414CONFIG_FIB_RULES=y
415# CONFIG_WIRELESS is not set
416# CONFIG_WIMAX is not set
417# CONFIG_RFKILL is not set
418# CONFIG_NET_9P is not set
419
420#
421# Device Drivers
422#
423
424#
425# Generic Driver Options
426#
427CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
428# CONFIG_STANDALONE is not set
429CONFIG_PREVENT_FIRMWARE_BUILD=y
430CONFIG_FW_LOADER=y
431CONFIG_FIRMWARE_IN_KERNEL=y
432CONFIG_EXTRA_FIRMWARE=""
433# CONFIG_DEBUG_DRIVER is not set
434# CONFIG_DEBUG_DEVRES is not set
435# CONFIG_SYS_HYPERVISOR is not set
436# CONFIG_CONNECTOR is not set
437CONFIG_MTD=y
438# CONFIG_MTD_DEBUG is not set
439# CONFIG_MTD_CONCAT is not set
440# CONFIG_MTD_PARTITIONS is not set
441# CONFIG_MTD_TESTS is not set
442
443#
444# User Modules And Translation Layers
445#
446CONFIG_MTD_CHAR=y
447# CONFIG_MTD_BLKDEVS is not set
448# CONFIG_MTD_BLOCK is not set
449# CONFIG_MTD_BLOCK_RO is not set
450# CONFIG_FTL is not set
451# CONFIG_NFTL is not set
452# CONFIG_INFTL is not set
453# CONFIG_RFD_FTL is not set
454# CONFIG_SSFDC is not set
455# CONFIG_MTD_OOPS is not set
456
457#
458# RAM/ROM/Flash chip drivers
459#
460# CONFIG_MTD_CFI is not set
461# CONFIG_MTD_JEDECPROBE is not set
462CONFIG_MTD_MAP_BANK_WIDTH_1=y
463CONFIG_MTD_MAP_BANK_WIDTH_2=y
464CONFIG_MTD_MAP_BANK_WIDTH_4=y
465# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
466# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
467# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
468CONFIG_MTD_CFI_I1=y
469CONFIG_MTD_CFI_I2=y
470# CONFIG_MTD_CFI_I4 is not set
471# CONFIG_MTD_CFI_I8 is not set
472# CONFIG_MTD_RAM is not set
473# CONFIG_MTD_ROM is not set
474# CONFIG_MTD_ABSENT is not set
475
476#
477# Mapping drivers for chip access
478#
479# CONFIG_MTD_COMPLEX_MAPPINGS is not set
480# CONFIG_MTD_PLATRAM is not set
481
482#
483# Self-contained MTD device drivers
484#
485# CONFIG_MTD_SLRAM is not set
486# CONFIG_MTD_PHRAM is not set
487# CONFIG_MTD_MTDRAM is not set
488# CONFIG_MTD_BLOCK2MTD is not set
489
490#
491# Disk-On-Chip Device Drivers
492#
493# CONFIG_MTD_DOC2000 is not set
494# CONFIG_MTD_DOC2001 is not set
495# CONFIG_MTD_DOC2001PLUS is not set
496CONFIG_MTD_NAND=y
497# CONFIG_MTD_NAND_VERIFY_WRITE is not set
498# CONFIG_MTD_NAND_ECC_SMC is not set
499# CONFIG_MTD_NAND_MUSEUM_IDS is not set
500# CONFIG_MTD_NAND_GPIO is not set
501CONFIG_MTD_NAND_IDS=y
502# CONFIG_MTD_NAND_DISKONCHIP is not set
503# CONFIG_MTD_NAND_PLATFORM is not set
504# CONFIG_MTD_ONENAND is not set
505
506#
507# LPDDR flash memory drivers
508#
509# CONFIG_MTD_LPDDR is not set
510
511#
512# UBI - Unsorted block images
513#
514CONFIG_MTD_UBI=y
515CONFIG_MTD_UBI_WL_THRESHOLD=4096
516CONFIG_MTD_UBI_BEB_RESERVE=1
517CONFIG_MTD_UBI_GLUEBI=y
518
519#
520# UBI debugging options
521#
522# CONFIG_MTD_UBI_DEBUG is not set
523# CONFIG_PARPORT is not set
524CONFIG_BLK_DEV=y
525# CONFIG_BLK_DEV_COW_COMMON is not set
526CONFIG_BLK_DEV_LOOP=y
527CONFIG_BLK_DEV_CRYPTOLOOP=y
528# CONFIG_BLK_DEV_NBD is not set
529CONFIG_BLK_DEV_RAM=y
530CONFIG_BLK_DEV_RAM_COUNT=4
531CONFIG_BLK_DEV_RAM_SIZE=6144
532# CONFIG_BLK_DEV_XIP is not set
533# CONFIG_CDROM_PKTCDVD is not set
534# CONFIG_ATA_OVER_ETH is not set
535# CONFIG_MISC_DEVICES is not set
536CONFIG_HAVE_IDE=y
537# CONFIG_IDE is not set
538
539#
540# SCSI device support
541#
542# CONFIG_RAID_ATTRS is not set
543CONFIG_SCSI=y
544CONFIG_SCSI_DMA=y
545# CONFIG_SCSI_TGT is not set
546# CONFIG_SCSI_NETLINK is not set
547CONFIG_SCSI_PROC_FS=y
548
549#
550# SCSI support type (disk, tape, CD-ROM)
551#
552CONFIG_BLK_DEV_SD=y
553# CONFIG_CHR_DEV_ST is not set
554# CONFIG_CHR_DEV_OSST is not set
555# CONFIG_BLK_DEV_SR is not set
556CONFIG_CHR_DEV_SG=y
557# CONFIG_CHR_DEV_SCH is not set
558
559#
560# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
561#
562# CONFIG_SCSI_MULTI_LUN is not set
563# CONFIG_SCSI_CONSTANTS is not set
564# CONFIG_SCSI_LOGGING is not set
565# CONFIG_SCSI_SCAN_ASYNC is not set
566CONFIG_SCSI_WAIT_SCAN=m
567
568#
569# SCSI Transports
570#
571# CONFIG_SCSI_SPI_ATTRS is not set
572# CONFIG_SCSI_FC_ATTRS is not set
573# CONFIG_SCSI_ISCSI_ATTRS is not set
574# CONFIG_SCSI_SAS_LIBSAS is not set
575# CONFIG_SCSI_SRP_ATTRS is not set
576# CONFIG_SCSI_LOWLEVEL is not set
577# CONFIG_SCSI_DH is not set
578# CONFIG_SCSI_OSD_INITIATOR is not set
579# CONFIG_ATA is not set
580# CONFIG_MD is not set
581# CONFIG_NETDEVICES is not set
582# CONFIG_ISDN is not set
583
584#
585# Input device support
586#
587CONFIG_INPUT=y
588# CONFIG_INPUT_FF_MEMLESS is not set
589CONFIG_INPUT_POLLDEV=y
590
591#
592# Userland interfaces
593#
594CONFIG_INPUT_MOUSEDEV=y
595CONFIG_INPUT_MOUSEDEV_PSAUX=y
596CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
597CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
598# CONFIG_INPUT_JOYDEV is not set
599CONFIG_INPUT_EVDEV=y
600# CONFIG_INPUT_EVBUG is not set
601
602#
603# Input Device Drivers
604#
605CONFIG_INPUT_KEYBOARD=y
606# CONFIG_KEYBOARD_ATKBD is not set
607# CONFIG_KEYBOARD_SUNKBD is not set
608# CONFIG_KEYBOARD_LKKBD is not set
609# CONFIG_KEYBOARD_XTKBD is not set
610# CONFIG_KEYBOARD_NEWTON is not set
611# CONFIG_KEYBOARD_STOWAWAY is not set
612# CONFIG_KEYBOARD_GPIO is not set
613# CONFIG_INPUT_MOUSE is not set
614# CONFIG_INPUT_JOYSTICK is not set
615# CONFIG_INPUT_TABLET is not set
616CONFIG_INPUT_TOUCHSCREEN=y
617# CONFIG_TOUCHSCREEN_AD7879 is not set
618# CONFIG_TOUCHSCREEN_FUJITSU is not set
619# CONFIG_TOUCHSCREEN_GUNZE is not set
620# CONFIG_TOUCHSCREEN_ELO is not set
621# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
622# CONFIG_TOUCHSCREEN_MTOUCH is not set
623# CONFIG_TOUCHSCREEN_INEXIO is not set
624# CONFIG_TOUCHSCREEN_MK712 is not set
625# CONFIG_TOUCHSCREEN_PENMOUNT is not set
626# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
627# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
628# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
629CONFIG_INPUT_MISC=y
630# CONFIG_INPUT_UINPUT is not set
631# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
632
633#
634# Hardware I/O ports
635#
636CONFIG_SERIO=y
637# CONFIG_SERIO_SERPORT is not set
638# CONFIG_SERIO_LIBPS2 is not set
639# CONFIG_SERIO_RAW is not set
640# CONFIG_GAMEPORT is not set
641
642#
643# Character devices
644#
645CONFIG_VT=y
646CONFIG_CONSOLE_TRANSLATIONS=y
647CONFIG_VT_CONSOLE=y
648CONFIG_HW_CONSOLE=y
649CONFIG_VT_HW_CONSOLE_BINDING=y
650CONFIG_DEVKMEM=y
651# CONFIG_SERIAL_NONSTANDARD is not set
652
653#
654# Serial drivers
655#
656# CONFIG_SERIAL_8250 is not set
657
658#
659# Non-8250 serial port support
660#
661CONFIG_UNIX98_PTYS=y
662# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
663# CONFIG_LEGACY_PTYS is not set
664# CONFIG_IPMI_HANDLER is not set
665CONFIG_HW_RANDOM=y
666# CONFIG_HW_RANDOM_TIMERIOMEM is not set
667# CONFIG_R3964 is not set
668# CONFIG_RAW_DRIVER is not set
669# CONFIG_TCG_TPM is not set
670# CONFIG_I2C is not set
671# CONFIG_SPI is not set
672CONFIG_ARCH_REQUIRE_GPIOLIB=y
673CONFIG_GPIOLIB=y
674CONFIG_DEBUG_GPIO=y
675CONFIG_GPIO_SYSFS=y
676
677#
678# Memory mapped GPIO expanders:
679#
680
681#
682# I2C GPIO expanders:
683#
684
685#
686# PCI GPIO expanders:
687#
688
689#
690# SPI GPIO expanders:
691#
692# CONFIG_W1 is not set
693# CONFIG_POWER_SUPPLY is not set
694# CONFIG_HWMON is not set
695# CONFIG_THERMAL is not set
696# CONFIG_THERMAL_HWMON is not set
697# CONFIG_WATCHDOG is not set
698CONFIG_SSB_POSSIBLE=y
699
700#
701# Sonics Silicon Backplane
702#
703# CONFIG_SSB is not set
704
705#
706# Multifunction device drivers
707#
708# CONFIG_MFD_CORE is not set
709# CONFIG_MFD_SM501 is not set
710# CONFIG_MFD_ASIC3 is not set
711# CONFIG_HTC_EGPIO is not set
712# CONFIG_HTC_PASIC3 is not set
713# CONFIG_MFD_TMIO is not set
714# CONFIG_MFD_T7L66XB is not set
715# CONFIG_MFD_TC6387XB is not set
716# CONFIG_MFD_TC6393XB is not set
717
718#
719# Multimedia devices
720#
721
722#
723# Multimedia core support
724#
725CONFIG_VIDEO_DEV=y
726CONFIG_VIDEO_V4L2_COMMON=y
727# CONFIG_VIDEO_ALLOW_V4L1 is not set
728# CONFIG_VIDEO_V4L1_COMPAT is not set
729# CONFIG_DVB_CORE is not set
730CONFIG_VIDEO_MEDIA=y
731
732#
733# Multimedia drivers
734#
735# CONFIG_MEDIA_ATTACH is not set
736CONFIG_VIDEO_V4L2=y
737CONFIG_VIDEO_CAPTURE_DRIVERS=y
738# CONFIG_VIDEO_ADV_DEBUG is not set
739# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
740# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
741
742#
743# Encoders/decoders and other helper chips
744#
745
746#
747# Audio decoders
748#
749
750#
751# RDS decoders
752#
753
754#
755# Video decoders
756#
757
758#
759# Video and audio decoders
760#
761
762#
763# MPEG video encoders
764#
765# CONFIG_VIDEO_CX2341X is not set
766
767#
768# Video encoders
769#
770
771#
772# Video improvement chips
773#
774# CONFIG_VIDEO_VIVI is not set
775# CONFIG_SOC_CAMERA is not set
776# CONFIG_RADIO_ADAPTERS is not set
777# CONFIG_DAB is not set
778
779#
780# Graphics support
781#
782# CONFIG_VGASTATE is not set
783# CONFIG_VIDEO_OUTPUT_CONTROL is not set
784CONFIG_FB=y
785# CONFIG_FIRMWARE_EDID is not set
786# CONFIG_FB_DDC is not set
787# CONFIG_FB_BOOT_VESA_SUPPORT is not set
788# CONFIG_FB_CFB_FILLRECT is not set
789# CONFIG_FB_CFB_COPYAREA is not set
790# CONFIG_FB_CFB_IMAGEBLIT is not set
791# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
792# CONFIG_FB_SYS_FILLRECT is not set
793# CONFIG_FB_SYS_COPYAREA is not set
794# CONFIG_FB_SYS_IMAGEBLIT is not set
795# CONFIG_FB_FOREIGN_ENDIAN is not set
796# CONFIG_FB_SYS_FOPS is not set
797# CONFIG_FB_SVGALIB is not set
798# CONFIG_FB_MACMODES is not set
799# CONFIG_FB_BACKLIGHT is not set
800# CONFIG_FB_MODE_HELPERS is not set
801# CONFIG_FB_TILEBLITTING is not set
802
803#
804# Frame buffer hardware drivers
805#
806# CONFIG_FB_S1D13XXX is not set
807# CONFIG_FB_VIRTUAL is not set
808# CONFIG_FB_METRONOME is not set
809# CONFIG_FB_MB862XX is not set
810# CONFIG_FB_BROADSHEET is not set
811CONFIG_BACKLIGHT_LCD_SUPPORT=y
812CONFIG_LCD_CLASS_DEVICE=y
813# CONFIG_LCD_ILI9320 is not set
814# CONFIG_LCD_PLATFORM is not set
815CONFIG_BACKLIGHT_CLASS_DEVICE=y
816CONFIG_BACKLIGHT_GENERIC=y
817
818#
819# Display device support
820#
821# CONFIG_DISPLAY_SUPPORT is not set
822
823#
824# Console display driver support
825#
826# CONFIG_VGA_CONSOLE is not set
827CONFIG_DUMMY_CONSOLE=y
828CONFIG_FRAMEBUFFER_CONSOLE=y
829# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
830# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
831# CONFIG_FONTS is not set
832CONFIG_FONT_8x8=y
833CONFIG_FONT_8x16=y
834CONFIG_LOGO=y
835CONFIG_LOGO_LINUX_MONO=y
836CONFIG_LOGO_LINUX_VGA16=y
837CONFIG_LOGO_LINUX_CLUT224=y
838# CONFIG_SOUND is not set
839# CONFIG_HID_SUPPORT is not set
840# CONFIG_USB_SUPPORT is not set
841CONFIG_USB_ARCH_HAS_EHCI=y
842# CONFIG_MMC is not set
843# CONFIG_MEMSTICK is not set
844# CONFIG_ACCESSIBILITY is not set
845# CONFIG_NEW_LEDS is not set
846CONFIG_RTC_LIB=y
847# CONFIG_RTC_CLASS is not set
848# CONFIG_DMADEVICES is not set
849# CONFIG_AUXDISPLAY is not set
850# CONFIG_REGULATOR is not set
851# CONFIG_UIO is not set
852# CONFIG_STAGING is not set
853
854#
855# File systems
856#
857# CONFIG_EXT2_FS is not set
858# CONFIG_EXT3_FS is not set
859# CONFIG_EXT4_FS is not set
860# CONFIG_REISERFS_FS is not set
861# CONFIG_JFS_FS is not set
862# CONFIG_FS_POSIX_ACL is not set
863CONFIG_FILE_LOCKING=y
864# CONFIG_XFS_FS is not set
865# CONFIG_GFS2_FS is not set
866# CONFIG_OCFS2_FS is not set
867# CONFIG_BTRFS_FS is not set
868# CONFIG_DNOTIFY is not set
869# CONFIG_INOTIFY is not set
870# CONFIG_QUOTA is not set
871# CONFIG_AUTOFS_FS is not set
872# CONFIG_AUTOFS4_FS is not set
873# CONFIG_FUSE_FS is not set
874
875#
876# Caches
877#
878# CONFIG_FSCACHE is not set
879
880#
881# CD-ROM/DVD Filesystems
882#
883# CONFIG_ISO9660_FS is not set
884# CONFIG_UDF_FS is not set
885
886#
887# DOS/FAT/NT Filesystems
888#
889# CONFIG_MSDOS_FS is not set
890# CONFIG_VFAT_FS is not set
891# CONFIG_NTFS_FS is not set
892
893#
894# Pseudo filesystems
895#
896CONFIG_PROC_FS=y
897CONFIG_PROC_SYSCTL=y
898CONFIG_PROC_PAGE_MONITOR=y
899CONFIG_SYSFS=y
900CONFIG_TMPFS=y
901# CONFIG_TMPFS_POSIX_ACL is not set
902# CONFIG_HUGETLB_PAGE is not set
903CONFIG_CONFIGFS_FS=m
904# CONFIG_MISC_FILESYSTEMS is not set
905# CONFIG_NETWORK_FILESYSTEMS is not set
906
907#
908# Partition Types
909#
910# CONFIG_PARTITION_ADVANCED is not set
911CONFIG_MSDOS_PARTITION=y
912# CONFIG_NLS is not set
913# CONFIG_DLM is not set
914
915#
916# Kernel hacking
917#
918# CONFIG_PRINTK_TIME is not set
919CONFIG_ENABLE_WARN_DEPRECATED=y
920# CONFIG_ENABLE_MUST_CHECK is not set
921CONFIG_FRAME_WARN=1024
922# CONFIG_MAGIC_SYSRQ is not set
923# CONFIG_UNUSED_SYMBOLS is not set
924CONFIG_DEBUG_FS=y
925# CONFIG_HEADERS_CHECK is not set
926CONFIG_DEBUG_KERNEL=y
927CONFIG_DEBUG_SHIRQ=y
928CONFIG_DETECT_SOFTLOCKUP=y
929# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
930CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
931CONFIG_DETECT_HUNG_TASK=y
932# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
933CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
934# CONFIG_SCHED_DEBUG is not set
935# CONFIG_SCHEDSTATS is not set
936# CONFIG_TIMER_STATS is not set
937CONFIG_DEBUG_OBJECTS=y
938CONFIG_DEBUG_OBJECTS_SELFTEST=y
939CONFIG_DEBUG_OBJECTS_FREE=y
940CONFIG_DEBUG_OBJECTS_TIMERS=y
941CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1
942CONFIG_DEBUG_SLAB=y
943CONFIG_DEBUG_SLAB_LEAK=y
944CONFIG_DEBUG_PREEMPT=y
945CONFIG_DEBUG_RT_MUTEXES=y
946CONFIG_DEBUG_PI_LIST=y
947# CONFIG_RT_MUTEX_TESTER is not set
948CONFIG_DEBUG_SPINLOCK=y
949CONFIG_DEBUG_MUTEXES=y
950CONFIG_DEBUG_LOCK_ALLOC=y
951CONFIG_PROVE_LOCKING=y
952CONFIG_LOCKDEP=y
953# CONFIG_LOCK_STAT is not set
954# CONFIG_DEBUG_LOCKDEP is not set
955CONFIG_TRACE_IRQFLAGS=y
956CONFIG_DEBUG_SPINLOCK_SLEEP=y
957# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
958CONFIG_STACKTRACE=y
959CONFIG_DEBUG_KOBJECT=y
960# CONFIG_DEBUG_HIGHMEM is not set
961# CONFIG_DEBUG_BUGVERBOSE is not set
962CONFIG_DEBUG_INFO=y
963# CONFIG_DEBUG_VM is not set
964# CONFIG_DEBUG_WRITECOUNT is not set
965# CONFIG_DEBUG_MEMORY_INIT is not set
966# CONFIG_DEBUG_LIST is not set
967# CONFIG_DEBUG_SG is not set
968# CONFIG_DEBUG_NOTIFIERS is not set
969CONFIG_FRAME_POINTER=y
970# CONFIG_BOOT_PRINTK_DELAY is not set
971# CONFIG_RCU_TORTURE_TEST is not set
972# CONFIG_RCU_CPU_STALL_DETECTOR is not set
973# CONFIG_BACKTRACE_SELF_TEST is not set
974# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
975# CONFIG_FAULT_INJECTION is not set
976# CONFIG_LATENCYTOP is not set
977CONFIG_SYSCTL_SYSCALL_CHECK=y
978# CONFIG_PAGE_POISONING is not set
979CONFIG_NOP_TRACER=y
980CONFIG_HAVE_FUNCTION_TRACER=y
981CONFIG_RING_BUFFER=y
982CONFIG_TRACING=y
983CONFIG_TRACING_SUPPORT=y
984
985#
986# Tracers
987#
988CONFIG_FUNCTION_TRACER=y
989# CONFIG_IRQSOFF_TRACER is not set
990# CONFIG_PREEMPT_TRACER is not set
991# CONFIG_SCHED_TRACER is not set
992CONFIG_CONTEXT_SWITCH_TRACER=y
993# CONFIG_EVENT_TRACER is not set
994CONFIG_BOOT_TRACER=y
995# CONFIG_TRACE_BRANCH_PROFILING is not set
996CONFIG_STACK_TRACER=y
997# CONFIG_KMEMTRACE is not set
998# CONFIG_WORKQUEUE_TRACER is not set
999CONFIG_BLK_DEV_IO_TRACE=y
1000# CONFIG_FTRACE_STARTUP_TEST is not set
1001# CONFIG_DYNAMIC_DEBUG is not set
1002# CONFIG_SAMPLES is not set
1003CONFIG_HAVE_ARCH_KGDB=y
1004# CONFIG_KGDB is not set
1005CONFIG_ARM_UNWIND=y
1006# CONFIG_DEBUG_USER is not set
1007# CONFIG_DEBUG_ERRORS is not set
1008# CONFIG_DEBUG_STACK_USAGE is not set
1009# CONFIG_DEBUG_LL is not set
1010
1011#
1012# Security options
1013#
1014CONFIG_KEYS=y
1015CONFIG_KEYS_DEBUG_PROC_KEYS=y
1016CONFIG_SECURITY=y
1017# CONFIG_SECURITYFS is not set
1018# CONFIG_SECURITY_NETWORK is not set
1019# CONFIG_SECURITY_PATH is not set
1020# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1021CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
1022# CONFIG_SECURITY_TOMOYO is not set
1023CONFIG_CRYPTO=y
1024
1025#
1026# Crypto core or helper
1027#
1028# CONFIG_CRYPTO_FIPS is not set
1029CONFIG_CRYPTO_ALGAPI=y
1030CONFIG_CRYPTO_ALGAPI2=y
1031CONFIG_CRYPTO_AEAD2=y
1032CONFIG_CRYPTO_BLKCIPHER=y
1033CONFIG_CRYPTO_BLKCIPHER2=y
1034CONFIG_CRYPTO_HASH=y
1035CONFIG_CRYPTO_HASH2=y
1036CONFIG_CRYPTO_RNG2=y
1037CONFIG_CRYPTO_PCOMP=y
1038CONFIG_CRYPTO_MANAGER=y
1039CONFIG_CRYPTO_MANAGER2=y
1040# CONFIG_CRYPTO_GF128MUL is not set
1041# CONFIG_CRYPTO_NULL is not set
1042CONFIG_CRYPTO_WORKQUEUE=y
1043# CONFIG_CRYPTO_CRYPTD is not set
1044# CONFIG_CRYPTO_AUTHENC is not set
1045CONFIG_CRYPTO_TEST=m
1046
1047#
1048# Authenticated Encryption with Associated Data
1049#
1050# CONFIG_CRYPTO_CCM is not set
1051# CONFIG_CRYPTO_GCM is not set
1052# CONFIG_CRYPTO_SEQIV is not set
1053
1054#
1055# Block modes
1056#
1057CONFIG_CRYPTO_CBC=y
1058# CONFIG_CRYPTO_CTR is not set
1059# CONFIG_CRYPTO_CTS is not set
1060CONFIG_CRYPTO_ECB=y
1061# CONFIG_CRYPTO_LRW is not set
1062# CONFIG_CRYPTO_PCBC is not set
1063# CONFIG_CRYPTO_XTS is not set
1064
1065#
1066# Hash modes
1067#
1068CONFIG_CRYPTO_HMAC=y
1069# CONFIG_CRYPTO_XCBC is not set
1070
1071#
1072# Digest
1073#
1074# CONFIG_CRYPTO_CRC32C is not set
1075# CONFIG_CRYPTO_MD4 is not set
1076CONFIG_CRYPTO_MD5=y
1077# CONFIG_CRYPTO_MICHAEL_MIC is not set
1078# CONFIG_CRYPTO_RMD128 is not set
1079# CONFIG_CRYPTO_RMD160 is not set
1080# CONFIG_CRYPTO_RMD256 is not set
1081# CONFIG_CRYPTO_RMD320 is not set
1082CONFIG_CRYPTO_SHA1=m
1083# CONFIG_CRYPTO_SHA256 is not set
1084# CONFIG_CRYPTO_SHA512 is not set
1085# CONFIG_CRYPTO_TGR192 is not set
1086# CONFIG_CRYPTO_WP512 is not set
1087
1088#
1089# Ciphers
1090#
1091CONFIG_CRYPTO_AES=m
1092# CONFIG_CRYPTO_ANUBIS is not set
1093# CONFIG_CRYPTO_ARC4 is not set
1094# CONFIG_CRYPTO_BLOWFISH is not set
1095# CONFIG_CRYPTO_CAMELLIA is not set
1096# CONFIG_CRYPTO_CAST5 is not set
1097# CONFIG_CRYPTO_CAST6 is not set
1098CONFIG_CRYPTO_DES=y
1099# CONFIG_CRYPTO_FCRYPT is not set
1100# CONFIG_CRYPTO_KHAZAD is not set
1101# CONFIG_CRYPTO_SALSA20 is not set
1102# CONFIG_CRYPTO_SEED is not set
1103# CONFIG_CRYPTO_SERPENT is not set
1104# CONFIG_CRYPTO_TEA is not set
1105# CONFIG_CRYPTO_TWOFISH is not set
1106
1107#
1108# Compression
1109#
1110CONFIG_CRYPTO_DEFLATE=y
1111# CONFIG_CRYPTO_ZLIB is not set
1112CONFIG_CRYPTO_LZO=y
1113
1114#
1115# Random Number Generation
1116#
1117# CONFIG_CRYPTO_ANSI_CPRNG is not set
1118CONFIG_CRYPTO_HW=y
1119CONFIG_BINARY_PRINTF=y
1120
1121#
1122# Library routines
1123#
1124CONFIG_BITREVERSE=y
1125CONFIG_GENERIC_FIND_LAST_BIT=y
1126CONFIG_CRC_CCITT=m
1127CONFIG_CRC16=y
1128# CONFIG_CRC_T10DIF is not set
1129# CONFIG_CRC_ITU_T is not set
1130CONFIG_CRC32=y
1131# CONFIG_CRC7 is not set
1132# CONFIG_LIBCRC32C is not set
1133CONFIG_ZLIB_INFLATE=y
1134CONFIG_ZLIB_DEFLATE=y
1135CONFIG_LZO_COMPRESS=y
1136CONFIG_LZO_DECOMPRESS=y
1137CONFIG_DECOMPRESS_GZIP=y
1138CONFIG_HAS_IOMEM=y
1139CONFIG_HAS_IOPORT=y
1140CONFIG_HAS_DMA=y
1141CONFIG_NLATTR=y
diff --git a/arch/arm/configs/stmp37xx_defconfig b/arch/arm/configs/stmp37xx_defconfig
new file mode 100644
index 000000000000..401279d531d5
--- /dev/null
+++ b/arch/arm/configs/stmp37xx_defconfig
@@ -0,0 +1,1002 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29.1
4# Mon Apr 20 04:41:26 2009
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_HAVE_LATENCYTOP_SUPPORT=y
16CONFIG_LOCKDEP_SUPPORT=y
17CONFIG_TRACE_IRQFLAGS_SUPPORT=y
18CONFIG_HARDIRQS_SW_RESEND=y
19CONFIG_GENERIC_IRQ_PROBE=y
20CONFIG_RWSEM_GENERIC_SPINLOCK=y
21# CONFIG_ARCH_HAS_ILOG2_U32 is not set
22# CONFIG_ARCH_HAS_ILOG2_U64 is not set
23CONFIG_GENERIC_HWEIGHT=y
24CONFIG_GENERIC_CALIBRATE_DELAY=y
25CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
26CONFIG_VECTORS_BASE=0xffff0000
27CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
28
29#
30# General setup
31#
32CONFIG_EXPERIMENTAL=y
33CONFIG_BROKEN_ON_SMP=y
34CONFIG_LOCK_KERNEL=y
35CONFIG_INIT_ENV_ARG_LIMIT=32
36CONFIG_LOCALVERSION="-default"
37CONFIG_LOCALVERSION_AUTO=y
38CONFIG_SWAP=y
39CONFIG_SYSVIPC=y
40CONFIG_SYSVIPC_SYSCTL=y
41CONFIG_POSIX_MQUEUE=y
42CONFIG_BSD_PROCESS_ACCT=y
43# CONFIG_BSD_PROCESS_ACCT_V3 is not set
44# CONFIG_TASKSTATS is not set
45# CONFIG_AUDIT is not set
46
47#
48# RCU Subsystem
49#
50CONFIG_CLASSIC_RCU=y
51# CONFIG_TREE_RCU is not set
52# CONFIG_PREEMPT_RCU is not set
53# CONFIG_TREE_RCU_TRACE is not set
54# CONFIG_PREEMPT_RCU_TRACE is not set
55# CONFIG_IKCONFIG is not set
56CONFIG_LOG_BUF_SHIFT=17
57# CONFIG_GROUP_SCHED is not set
58# CONFIG_CGROUPS is not set
59CONFIG_SYSFS_DEPRECATED=y
60CONFIG_SYSFS_DEPRECATED_V2=y
61CONFIG_RELAY=y
62# CONFIG_NAMESPACES is not set
63CONFIG_BLK_DEV_INITRD=y
64CONFIG_INITRAMFS_SOURCE=""
65CONFIG_INITRAMFS_ROOT_UID=0
66CONFIG_INITRAMFS_ROOT_GID=0
67CONFIG_CC_OPTIMIZE_FOR_SIZE=y
68CONFIG_SYSCTL=y
69CONFIG_ANON_INODES=y
70CONFIG_EMBEDDED=y
71CONFIG_UID16=y
72CONFIG_SYSCTL_SYSCALL=y
73CONFIG_KALLSYMS=y
74# CONFIG_KALLSYMS_ALL is not set
75# CONFIG_KALLSYMS_EXTRA_PASS is not set
76CONFIG_HOTPLUG=y
77CONFIG_PRINTK=y
78CONFIG_BUG=y
79CONFIG_ELF_CORE=y
80CONFIG_BASE_FULL=y
81CONFIG_FUTEX=y
82CONFIG_EPOLL=y
83CONFIG_SIGNALFD=y
84CONFIG_TIMERFD=y
85CONFIG_EVENTFD=y
86CONFIG_SHMEM=y
87CONFIG_AIO=y
88CONFIG_VM_EVENT_COUNTERS=y
89CONFIG_COMPAT_BRK=y
90CONFIG_SLAB=y
91# CONFIG_SLUB is not set
92# CONFIG_SLOB is not set
93# CONFIG_PROFILING is not set
94CONFIG_TRACEPOINTS=y
95CONFIG_MARKERS=y
96CONFIG_HAVE_OPROFILE=y
97# CONFIG_KPROBES is not set
98CONFIG_HAVE_KPROBES=y
99CONFIG_HAVE_KRETPROBES=y
100CONFIG_HAVE_CLK=y
101CONFIG_HAVE_GENERIC_DMA_COHERENT=y
102CONFIG_SLABINFO=y
103CONFIG_RT_MUTEXES=y
104CONFIG_BASE_SMALL=0
105CONFIG_MODULES=y
106# CONFIG_MODULE_FORCE_LOAD is not set
107CONFIG_MODULE_UNLOAD=y
108CONFIG_MODULE_FORCE_UNLOAD=y
109CONFIG_MODVERSIONS=y
110CONFIG_MODULE_SRCVERSION_ALL=y
111CONFIG_BLOCK=y
112CONFIG_LBD=y
113CONFIG_BLK_DEV_IO_TRACE=y
114# CONFIG_BLK_DEV_BSG is not set
115# CONFIG_BLK_DEV_INTEGRITY is not set
116
117#
118# IO Schedulers
119#
120CONFIG_IOSCHED_NOOP=y
121CONFIG_IOSCHED_AS=y
122CONFIG_IOSCHED_DEADLINE=y
123CONFIG_IOSCHED_CFQ=y
124# CONFIG_DEFAULT_AS is not set
125# CONFIG_DEFAULT_DEADLINE is not set
126CONFIG_DEFAULT_CFQ=y
127# CONFIG_DEFAULT_NOOP is not set
128CONFIG_DEFAULT_IOSCHED="cfq"
129# CONFIG_FREEZER is not set
130
131#
132# System Type
133#
134# CONFIG_ARCH_AAEC2000 is not set
135# CONFIG_ARCH_INTEGRATOR is not set
136# CONFIG_ARCH_REALVIEW is not set
137# CONFIG_ARCH_VERSATILE is not set
138# CONFIG_ARCH_AT91 is not set
139# CONFIG_ARCH_CLPS711X is not set
140# CONFIG_ARCH_EBSA110 is not set
141# CONFIG_ARCH_EP93XX is not set
142# CONFIG_ARCH_FOOTBRIDGE is not set
143# CONFIG_ARCH_NETX is not set
144# CONFIG_ARCH_H720X is not set
145# CONFIG_ARCH_IMX is not set
146# CONFIG_ARCH_IOP13XX is not set
147# CONFIG_ARCH_IOP32X is not set
148# CONFIG_ARCH_IOP33X is not set
149# CONFIG_ARCH_IXP23XX is not set
150# CONFIG_ARCH_IXP2000 is not set
151# CONFIG_ARCH_IXP4XX is not set
152# CONFIG_ARCH_L7200 is not set
153# CONFIG_ARCH_KIRKWOOD is not set
154# CONFIG_ARCH_KS8695 is not set
155# CONFIG_ARCH_NS9XXX is not set
156# CONFIG_ARCH_LOKI is not set
157# CONFIG_ARCH_MV78XX0 is not set
158# CONFIG_ARCH_MXC is not set
159# CONFIG_ARCH_ORION5X is not set
160# CONFIG_ARCH_PNX4008 is not set
161# CONFIG_ARCH_PXA is not set
162# CONFIG_ARCH_RPC is not set
163# CONFIG_ARCH_SA1100 is not set
164# CONFIG_ARCH_S3C2410 is not set
165# CONFIG_ARCH_S3C64XX is not set
166# CONFIG_ARCH_SHARK is not set
167# CONFIG_ARCH_LH7A40X is not set
168# CONFIG_ARCH_DAVINCI is not set
169# CONFIG_ARCH_OMAP is not set
170# CONFIG_ARCH_MSM is not set
171# CONFIG_ARCH_W90X900 is not set
172CONFIG_ARCH_STMP3XXX=y
173
174#
175# Freescale STMP3xxx implementations
176#
177CONFIG_ARCH_STMP37XX=y
178# CONFIG_ARCH_STMP378X is not set
179CONFIG_MACH_STMP37XX=y
180# CONFIG_MACH_STMP378X is not set
181
182#
183# Processor Type
184#
185CONFIG_CPU_32=y
186CONFIG_CPU_ARM926T=y
187CONFIG_CPU_32v5=y
188CONFIG_CPU_ABRT_EV5TJ=y
189CONFIG_CPU_PABRT_NOIFAR=y
190CONFIG_CPU_CACHE_VIVT=y
191CONFIG_CPU_COPY_V4WB=y
192CONFIG_CPU_TLB_V4WBI=y
193CONFIG_CPU_CP15=y
194CONFIG_CPU_CP15_MMU=y
195
196#
197# Processor Features
198#
199CONFIG_ARM_THUMB=y
200# CONFIG_CPU_ICACHE_DISABLE is not set
201# CONFIG_CPU_DCACHE_DISABLE is not set
202# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
203# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
204# CONFIG_OUTER_CACHE is not set
205CONFIG_COMMON_CLKDEV=y
206
207#
208# Bus support
209#
210# CONFIG_PCI_SYSCALL is not set
211# CONFIG_ARCH_SUPPORTS_MSI is not set
212# CONFIG_PCCARD is not set
213
214#
215# Kernel Features
216#
217CONFIG_TICK_ONESHOT=y
218CONFIG_NO_HZ=y
219CONFIG_HIGH_RES_TIMERS=y
220CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
221CONFIG_VMSPLIT_3G=y
222# CONFIG_VMSPLIT_2G is not set
223# CONFIG_VMSPLIT_1G is not set
224CONFIG_PAGE_OFFSET=0xC0000000
225CONFIG_PREEMPT=y
226CONFIG_HZ=100
227CONFIG_AEABI=y
228CONFIG_OABI_COMPAT=y
229CONFIG_ARCH_FLATMEM_HAS_HOLES=y
230# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
231# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
232CONFIG_SELECT_MEMORY_MODEL=y
233CONFIG_FLATMEM_MANUAL=y
234# CONFIG_DISCONTIGMEM_MANUAL is not set
235# CONFIG_SPARSEMEM_MANUAL is not set
236CONFIG_FLATMEM=y
237CONFIG_FLAT_NODE_MEM_MAP=y
238CONFIG_PAGEFLAGS_EXTENDED=y
239CONFIG_SPLIT_PTLOCK_CPUS=4096
240# CONFIG_PHYS_ADDR_T_64BIT is not set
241CONFIG_ZONE_DMA_FLAG=0
242CONFIG_VIRT_TO_BUS=y
243CONFIG_UNEVICTABLE_LRU=y
244CONFIG_ALIGNMENT_TRAP=y
245
246#
247# Boot options
248#
249CONFIG_ZBOOT_ROM_TEXT=0x0
250CONFIG_ZBOOT_ROM_BSS=0x0
251CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M lcd_panel=lms350 rdinit=/bin/sh ignore_loglevel"
252# CONFIG_XIP_KERNEL is not set
253# CONFIG_KEXEC is not set
254
255#
256# CPU Power Management
257#
258# CONFIG_CPU_IDLE is not set
259
260#
261# Floating point emulation
262#
263
264#
265# At least one emulation must be selected
266#
267# CONFIG_FPE_NWFPE is not set
268# CONFIG_FPE_FASTFPE is not set
269# CONFIG_VFP is not set
270
271#
272# Userspace binary formats
273#
274CONFIG_BINFMT_ELF=y
275# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
276CONFIG_HAVE_AOUT=y
277# CONFIG_BINFMT_AOUT is not set
278# CONFIG_BINFMT_MISC is not set
279
280#
281# Power management options
282#
283# CONFIG_PM is not set
284CONFIG_ARCH_SUSPEND_POSSIBLE=y
285CONFIG_NET=y
286
287#
288# Networking options
289#
290CONFIG_COMPAT_NET_DEV_OPS=y
291CONFIG_PACKET=y
292CONFIG_PACKET_MMAP=y
293CONFIG_UNIX=y
294CONFIG_XFRM=y
295# CONFIG_XFRM_USER is not set
296# CONFIG_XFRM_SUB_POLICY is not set
297# CONFIG_XFRM_MIGRATE is not set
298# CONFIG_XFRM_STATISTICS is not set
299# CONFIG_NET_KEY is not set
300CONFIG_INET=y
301CONFIG_IP_MULTICAST=y
302CONFIG_IP_ADVANCED_ROUTER=y
303CONFIG_ASK_IP_FIB_HASH=y
304# CONFIG_IP_FIB_TRIE is not set
305CONFIG_IP_FIB_HASH=y
306CONFIG_IP_MULTIPLE_TABLES=y
307CONFIG_IP_ROUTE_MULTIPATH=y
308CONFIG_IP_ROUTE_VERBOSE=y
309CONFIG_IP_PNP=y
310CONFIG_IP_PNP_DHCP=y
311CONFIG_IP_PNP_BOOTP=y
312# CONFIG_IP_PNP_RARP is not set
313# CONFIG_NET_IPIP is not set
314# CONFIG_NET_IPGRE is not set
315CONFIG_IP_MROUTE=y
316CONFIG_IP_PIMSM_V1=y
317CONFIG_IP_PIMSM_V2=y
318# CONFIG_ARPD is not set
319CONFIG_SYN_COOKIES=y
320# CONFIG_INET_AH is not set
321# CONFIG_INET_ESP is not set
322# CONFIG_INET_IPCOMP is not set
323# CONFIG_INET_XFRM_TUNNEL is not set
324# CONFIG_INET_TUNNEL is not set
325CONFIG_INET_XFRM_MODE_TRANSPORT=y
326CONFIG_INET_XFRM_MODE_TUNNEL=y
327CONFIG_INET_XFRM_MODE_BEET=y
328# CONFIG_INET_LRO is not set
329CONFIG_INET_DIAG=y
330CONFIG_INET_TCP_DIAG=y
331# CONFIG_TCP_CONG_ADVANCED is not set
332CONFIG_TCP_CONG_CUBIC=y
333CONFIG_DEFAULT_TCP_CONG="cubic"
334# CONFIG_TCP_MD5SIG is not set
335# CONFIG_IPV6 is not set
336# CONFIG_NETLABEL is not set
337# CONFIG_NETWORK_SECMARK is not set
338# CONFIG_NETFILTER is not set
339# CONFIG_IP_DCCP is not set
340# CONFIG_IP_SCTP is not set
341# CONFIG_TIPC is not set
342# CONFIG_ATM is not set
343# CONFIG_BRIDGE is not set
344# CONFIG_NET_DSA is not set
345# CONFIG_VLAN_8021Q is not set
346# CONFIG_DECNET is not set
347# CONFIG_LLC2 is not set
348# CONFIG_IPX is not set
349# CONFIG_ATALK is not set
350# CONFIG_X25 is not set
351# CONFIG_LAPB is not set
352# CONFIG_ECONET is not set
353# CONFIG_WAN_ROUTER is not set
354CONFIG_NET_SCHED=y
355
356#
357# Queueing/Scheduling
358#
359# CONFIG_NET_SCH_CBQ is not set
360# CONFIG_NET_SCH_HTB is not set
361# CONFIG_NET_SCH_HFSC is not set
362# CONFIG_NET_SCH_PRIO is not set
363# CONFIG_NET_SCH_MULTIQ is not set
364# CONFIG_NET_SCH_RED is not set
365# CONFIG_NET_SCH_SFQ is not set
366# CONFIG_NET_SCH_TEQL is not set
367# CONFIG_NET_SCH_TBF is not set
368# CONFIG_NET_SCH_GRED is not set
369# CONFIG_NET_SCH_DSMARK is not set
370# CONFIG_NET_SCH_NETEM is not set
371# CONFIG_NET_SCH_DRR is not set
372
373#
374# Classification
375#
376# CONFIG_NET_CLS_BASIC is not set
377# CONFIG_NET_CLS_TCINDEX is not set
378# CONFIG_NET_CLS_ROUTE4 is not set
379# CONFIG_NET_CLS_FW is not set
380# CONFIG_NET_CLS_U32 is not set
381# CONFIG_NET_CLS_RSVP is not set
382# CONFIG_NET_CLS_RSVP6 is not set
383# CONFIG_NET_CLS_FLOW is not set
384# CONFIG_NET_EMATCH is not set
385# CONFIG_NET_CLS_ACT is not set
386CONFIG_NET_SCH_FIFO=y
387# CONFIG_DCB is not set
388
389#
390# Network testing
391#
392# CONFIG_NET_PKTGEN is not set
393# CONFIG_HAMRADIO is not set
394# CONFIG_CAN is not set
395# CONFIG_IRDA is not set
396# CONFIG_BT is not set
397# CONFIG_AF_RXRPC is not set
398# CONFIG_PHONET is not set
399CONFIG_FIB_RULES=y
400# CONFIG_WIRELESS is not set
401# CONFIG_WIMAX is not set
402# CONFIG_RFKILL is not set
403# CONFIG_NET_9P is not set
404
405#
406# Device Drivers
407#
408
409#
410# Generic Driver Options
411#
412CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
413# CONFIG_STANDALONE is not set
414CONFIG_PREVENT_FIRMWARE_BUILD=y
415CONFIG_FW_LOADER=y
416CONFIG_FIRMWARE_IN_KERNEL=y
417CONFIG_EXTRA_FIRMWARE=""
418# CONFIG_DEBUG_DRIVER is not set
419# CONFIG_DEBUG_DEVRES is not set
420# CONFIG_SYS_HYPERVISOR is not set
421# CONFIG_CONNECTOR is not set
422# CONFIG_MTD is not set
423# CONFIG_PARPORT is not set
424CONFIG_BLK_DEV=y
425# CONFIG_BLK_DEV_COW_COMMON is not set
426CONFIG_BLK_DEV_LOOP=y
427CONFIG_BLK_DEV_CRYPTOLOOP=y
428# CONFIG_BLK_DEV_NBD is not set
429CONFIG_BLK_DEV_RAM=y
430CONFIG_BLK_DEV_RAM_COUNT=4
431CONFIG_BLK_DEV_RAM_SIZE=6144
432# CONFIG_BLK_DEV_XIP is not set
433# CONFIG_CDROM_PKTCDVD is not set
434# CONFIG_ATA_OVER_ETH is not set
435# CONFIG_MISC_DEVICES is not set
436CONFIG_HAVE_IDE=y
437# CONFIG_IDE is not set
438
439#
440# SCSI device support
441#
442# CONFIG_RAID_ATTRS is not set
443CONFIG_SCSI=y
444CONFIG_SCSI_DMA=y
445# CONFIG_SCSI_TGT is not set
446# CONFIG_SCSI_NETLINK is not set
447CONFIG_SCSI_PROC_FS=y
448
449#
450# SCSI support type (disk, tape, CD-ROM)
451#
452CONFIG_BLK_DEV_SD=y
453# CONFIG_CHR_DEV_ST is not set
454# CONFIG_CHR_DEV_OSST is not set
455# CONFIG_BLK_DEV_SR is not set
456CONFIG_CHR_DEV_SG=y
457# CONFIG_CHR_DEV_SCH is not set
458
459#
460# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
461#
462# CONFIG_SCSI_MULTI_LUN is not set
463# CONFIG_SCSI_CONSTANTS is not set
464# CONFIG_SCSI_LOGGING is not set
465# CONFIG_SCSI_SCAN_ASYNC is not set
466CONFIG_SCSI_WAIT_SCAN=m
467
468#
469# SCSI Transports
470#
471# CONFIG_SCSI_SPI_ATTRS is not set
472# CONFIG_SCSI_FC_ATTRS is not set
473# CONFIG_SCSI_ISCSI_ATTRS is not set
474# CONFIG_SCSI_SAS_LIBSAS is not set
475# CONFIG_SCSI_SRP_ATTRS is not set
476# CONFIG_SCSI_LOWLEVEL is not set
477# CONFIG_SCSI_DH is not set
478# CONFIG_ATA is not set
479# CONFIG_MD is not set
480# CONFIG_NETDEVICES is not set
481# CONFIG_ISDN is not set
482
483#
484# Input device support
485#
486CONFIG_INPUT=y
487# CONFIG_INPUT_FF_MEMLESS is not set
488CONFIG_INPUT_POLLDEV=y
489
490#
491# Userland interfaces
492#
493CONFIG_INPUT_MOUSEDEV=y
494CONFIG_INPUT_MOUSEDEV_PSAUX=y
495CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
496CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
497# CONFIG_INPUT_JOYDEV is not set
498CONFIG_INPUT_EVDEV=y
499# CONFIG_INPUT_EVBUG is not set
500
501#
502# Input Device Drivers
503#
504CONFIG_INPUT_KEYBOARD=y
505# CONFIG_KEYBOARD_ATKBD is not set
506# CONFIG_KEYBOARD_SUNKBD is not set
507# CONFIG_KEYBOARD_LKKBD is not set
508# CONFIG_KEYBOARD_XTKBD is not set
509# CONFIG_KEYBOARD_NEWTON is not set
510# CONFIG_KEYBOARD_STOWAWAY is not set
511# CONFIG_KEYBOARD_GPIO is not set
512# CONFIG_INPUT_MOUSE is not set
513# CONFIG_INPUT_JOYSTICK is not set
514# CONFIG_INPUT_TABLET is not set
515CONFIG_INPUT_TOUCHSCREEN=y
516# CONFIG_TOUCHSCREEN_FUJITSU is not set
517# CONFIG_TOUCHSCREEN_GUNZE is not set
518# CONFIG_TOUCHSCREEN_ELO is not set
519# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
520# CONFIG_TOUCHSCREEN_MTOUCH is not set
521# CONFIG_TOUCHSCREEN_INEXIO is not set
522# CONFIG_TOUCHSCREEN_MK712 is not set
523# CONFIG_TOUCHSCREEN_PENMOUNT is not set
524# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
525# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
526# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
527CONFIG_INPUT_MISC=y
528# CONFIG_INPUT_UINPUT is not set
529
530#
531# Hardware I/O ports
532#
533CONFIG_SERIO=y
534# CONFIG_SERIO_SERPORT is not set
535# CONFIG_SERIO_LIBPS2 is not set
536# CONFIG_SERIO_RAW is not set
537# CONFIG_GAMEPORT is not set
538
539#
540# Character devices
541#
542CONFIG_VT=y
543CONFIG_CONSOLE_TRANSLATIONS=y
544CONFIG_VT_CONSOLE=y
545CONFIG_HW_CONSOLE=y
546CONFIG_VT_HW_CONSOLE_BINDING=y
547CONFIG_DEVKMEM=y
548# CONFIG_SERIAL_NONSTANDARD is not set
549
550#
551# Serial drivers
552#
553# CONFIG_SERIAL_8250 is not set
554
555#
556# Non-8250 serial port support
557#
558# CONFIG_SERIAL_STMP_DBG is not set
559CONFIG_UNIX98_PTYS=y
560# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
561# CONFIG_LEGACY_PTYS is not set
562# CONFIG_IPMI_HANDLER is not set
563CONFIG_HW_RANDOM=y
564# CONFIG_R3964 is not set
565# CONFIG_RAW_DRIVER is not set
566# CONFIG_TCG_TPM is not set
567# CONFIG_I2C is not set
568# CONFIG_SPI is not set
569CONFIG_ARCH_REQUIRE_GPIOLIB=y
570CONFIG_GPIOLIB=y
571CONFIG_DEBUG_GPIO=y
572CONFIG_GPIO_SYSFS=y
573
574#
575# Memory mapped GPIO expanders:
576#
577
578#
579# I2C GPIO expanders:
580#
581
582#
583# PCI GPIO expanders:
584#
585
586#
587# SPI GPIO expanders:
588#
589# CONFIG_W1 is not set
590# CONFIG_POWER_SUPPLY is not set
591# CONFIG_HWMON is not set
592# CONFIG_THERMAL is not set
593# CONFIG_THERMAL_HWMON is not set
594# CONFIG_WATCHDOG is not set
595CONFIG_SSB_POSSIBLE=y
596
597#
598# Sonics Silicon Backplane
599#
600# CONFIG_SSB is not set
601
602#
603# Multifunction device drivers
604#
605# CONFIG_MFD_CORE is not set
606# CONFIG_MFD_SM501 is not set
607# CONFIG_MFD_ASIC3 is not set
608# CONFIG_HTC_EGPIO is not set
609# CONFIG_HTC_PASIC3 is not set
610# CONFIG_MFD_TMIO is not set
611# CONFIG_MFD_T7L66XB is not set
612# CONFIG_MFD_TC6387XB is not set
613# CONFIG_MFD_TC6393XB is not set
614
615#
616# Multimedia devices
617#
618
619#
620# Multimedia core support
621#
622CONFIG_VIDEO_DEV=y
623CONFIG_VIDEO_V4L2_COMMON=y
624# CONFIG_VIDEO_ALLOW_V4L1 is not set
625# CONFIG_VIDEO_V4L1_COMPAT is not set
626# CONFIG_DVB_CORE is not set
627CONFIG_VIDEO_MEDIA=y
628
629#
630# Multimedia drivers
631#
632# CONFIG_MEDIA_ATTACH is not set
633CONFIG_VIDEO_V4L2=y
634CONFIG_VIDEO_CAPTURE_DRIVERS=y
635# CONFIG_VIDEO_ADV_DEBUG is not set
636# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
637# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
638
639#
640# Encoders/decoders and other helper chips
641#
642
643#
644# Audio decoders
645#
646
647#
648# Video decoders
649#
650
651#
652# Video and audio decoders
653#
654
655#
656# MPEG video encoders
657#
658# CONFIG_VIDEO_CX2341X is not set
659
660#
661# Video encoders
662#
663
664#
665# Video improvement chips
666#
667# CONFIG_VIDEO_VIVI is not set
668# CONFIG_SOC_CAMERA is not set
669# CONFIG_RADIO_ADAPTERS is not set
670# CONFIG_DAB is not set
671
672#
673# Graphics support
674#
675# CONFIG_VGASTATE is not set
676# CONFIG_VIDEO_OUTPUT_CONTROL is not set
677CONFIG_FB=y
678# CONFIG_FIRMWARE_EDID is not set
679# CONFIG_FB_DDC is not set
680# CONFIG_FB_BOOT_VESA_SUPPORT is not set
681# CONFIG_FB_CFB_FILLRECT is not set
682# CONFIG_FB_CFB_COPYAREA is not set
683# CONFIG_FB_CFB_IMAGEBLIT is not set
684# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
685# CONFIG_FB_SYS_FILLRECT is not set
686# CONFIG_FB_SYS_COPYAREA is not set
687# CONFIG_FB_SYS_IMAGEBLIT is not set
688# CONFIG_FB_FOREIGN_ENDIAN is not set
689# CONFIG_FB_SYS_FOPS is not set
690# CONFIG_FB_SVGALIB is not set
691# CONFIG_FB_MACMODES is not set
692# CONFIG_FB_BACKLIGHT is not set
693# CONFIG_FB_MODE_HELPERS is not set
694# CONFIG_FB_TILEBLITTING is not set
695
696#
697# Frame buffer hardware drivers
698#
699# CONFIG_FB_S1D13XXX is not set
700# CONFIG_FB_VIRTUAL is not set
701# CONFIG_FB_METRONOME is not set
702# CONFIG_FB_MB862XX is not set
703CONFIG_BACKLIGHT_LCD_SUPPORT=y
704CONFIG_LCD_CLASS_DEVICE=y
705# CONFIG_LCD_ILI9320 is not set
706# CONFIG_LCD_PLATFORM is not set
707CONFIG_BACKLIGHT_CLASS_DEVICE=y
708CONFIG_BACKLIGHT_GENERIC=y
709
710#
711# Display device support
712#
713# CONFIG_DISPLAY_SUPPORT is not set
714
715#
716# Console display driver support
717#
718# CONFIG_VGA_CONSOLE is not set
719CONFIG_DUMMY_CONSOLE=y
720CONFIG_FRAMEBUFFER_CONSOLE=y
721# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
722# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
723# CONFIG_FONTS is not set
724CONFIG_FONT_8x8=y
725CONFIG_FONT_8x16=y
726CONFIG_LOGO=y
727CONFIG_LOGO_LINUX_MONO=y
728CONFIG_LOGO_LINUX_VGA16=y
729CONFIG_LOGO_LINUX_CLUT224=y
730# CONFIG_SOUND is not set
731# CONFIG_HID_SUPPORT is not set
732# CONFIG_USB_SUPPORT is not set
733CONFIG_USB_ARCH_HAS_EHCI=y
734# CONFIG_MMC is not set
735# CONFIG_MEMSTICK is not set
736# CONFIG_ACCESSIBILITY is not set
737# CONFIG_NEW_LEDS is not set
738CONFIG_RTC_LIB=y
739# CONFIG_RTC_CLASS is not set
740# CONFIG_DMADEVICES is not set
741# CONFIG_REGULATOR is not set
742# CONFIG_UIO is not set
743# CONFIG_STAGING is not set
744
745#
746# File systems
747#
748# CONFIG_EXT2_FS is not set
749# CONFIG_EXT3_FS is not set
750# CONFIG_EXT4_FS is not set
751# CONFIG_REISERFS_FS is not set
752# CONFIG_JFS_FS is not set
753# CONFIG_FS_POSIX_ACL is not set
754CONFIG_FILE_LOCKING=y
755# CONFIG_XFS_FS is not set
756# CONFIG_GFS2_FS is not set
757# CONFIG_OCFS2_FS is not set
758# CONFIG_BTRFS_FS is not set
759# CONFIG_DNOTIFY is not set
760# CONFIG_INOTIFY is not set
761# CONFIG_QUOTA is not set
762# CONFIG_AUTOFS_FS is not set
763# CONFIG_AUTOFS4_FS is not set
764# CONFIG_FUSE_FS is not set
765
766#
767# CD-ROM/DVD Filesystems
768#
769# CONFIG_ISO9660_FS is not set
770# CONFIG_UDF_FS is not set
771
772#
773# DOS/FAT/NT Filesystems
774#
775# CONFIG_MSDOS_FS is not set
776# CONFIG_VFAT_FS is not set
777# CONFIG_NTFS_FS is not set
778
779#
780# Pseudo filesystems
781#
782CONFIG_PROC_FS=y
783CONFIG_PROC_SYSCTL=y
784CONFIG_PROC_PAGE_MONITOR=y
785CONFIG_SYSFS=y
786CONFIG_TMPFS=y
787# CONFIG_TMPFS_POSIX_ACL is not set
788# CONFIG_HUGETLB_PAGE is not set
789CONFIG_CONFIGFS_FS=m
790# CONFIG_MISC_FILESYSTEMS is not set
791# CONFIG_NETWORK_FILESYSTEMS is not set
792
793#
794# Partition Types
795#
796# CONFIG_PARTITION_ADVANCED is not set
797CONFIG_MSDOS_PARTITION=y
798# CONFIG_NLS is not set
799# CONFIG_DLM is not set
800
801#
802# Kernel hacking
803#
804# CONFIG_PRINTK_TIME is not set
805CONFIG_ENABLE_WARN_DEPRECATED=y
806# CONFIG_ENABLE_MUST_CHECK is not set
807CONFIG_FRAME_WARN=1024
808# CONFIG_MAGIC_SYSRQ is not set
809# CONFIG_UNUSED_SYMBOLS is not set
810CONFIG_DEBUG_FS=y
811# CONFIG_HEADERS_CHECK is not set
812CONFIG_DEBUG_SECTION_MISMATCH=y
813CONFIG_DEBUG_KERNEL=y
814# CONFIG_DEBUG_SHIRQ is not set
815CONFIG_DETECT_SOFTLOCKUP=y
816# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
817CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
818CONFIG_SCHED_DEBUG=y
819# CONFIG_SCHEDSTATS is not set
820# CONFIG_TIMER_STATS is not set
821# CONFIG_DEBUG_OBJECTS is not set
822# CONFIG_DEBUG_SLAB is not set
823CONFIG_DEBUG_PREEMPT=y
824# CONFIG_DEBUG_RT_MUTEXES is not set
825# CONFIG_RT_MUTEX_TESTER is not set
826# CONFIG_DEBUG_SPINLOCK is not set
827# CONFIG_DEBUG_MUTEXES is not set
828# CONFIG_DEBUG_LOCK_ALLOC is not set
829# CONFIG_PROVE_LOCKING is not set
830# CONFIG_LOCK_STAT is not set
831# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
832# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
833CONFIG_STACKTRACE=y
834# CONFIG_DEBUG_KOBJECT is not set
835# CONFIG_DEBUG_BUGVERBOSE is not set
836# CONFIG_DEBUG_INFO is not set
837# CONFIG_DEBUG_VM is not set
838# CONFIG_DEBUG_WRITECOUNT is not set
839# CONFIG_DEBUG_MEMORY_INIT is not set
840# CONFIG_DEBUG_LIST is not set
841# CONFIG_DEBUG_SG is not set
842# CONFIG_DEBUG_NOTIFIERS is not set
843CONFIG_FRAME_POINTER=y
844# CONFIG_BOOT_PRINTK_DELAY is not set
845# CONFIG_RCU_TORTURE_TEST is not set
846# CONFIG_RCU_CPU_STALL_DETECTOR is not set
847# CONFIG_BACKTRACE_SELF_TEST is not set
848# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
849# CONFIG_FAULT_INJECTION is not set
850# CONFIG_LATENCYTOP is not set
851CONFIG_SYSCTL_SYSCALL_CHECK=y
852CONFIG_NOP_TRACER=y
853CONFIG_HAVE_FUNCTION_TRACER=y
854CONFIG_RING_BUFFER=y
855CONFIG_TRACING=y
856
857#
858# Tracers
859#
860CONFIG_FUNCTION_TRACER=y
861# CONFIG_IRQSOFF_TRACER is not set
862# CONFIG_PREEMPT_TRACER is not set
863# CONFIG_SCHED_TRACER is not set
864CONFIG_CONTEXT_SWITCH_TRACER=y
865CONFIG_BOOT_TRACER=y
866# CONFIG_TRACE_BRANCH_PROFILING is not set
867CONFIG_STACK_TRACER=y
868# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
869# CONFIG_SAMPLES is not set
870CONFIG_HAVE_ARCH_KGDB=y
871# CONFIG_KGDB is not set
872# CONFIG_DEBUG_USER is not set
873# CONFIG_DEBUG_ERRORS is not set
874# CONFIG_DEBUG_STACK_USAGE is not set
875CONFIG_DEBUG_LL=y
876# CONFIG_DEBUG_ICEDCC is not set
877
878#
879# Security options
880#
881CONFIG_KEYS=y
882CONFIG_KEYS_DEBUG_PROC_KEYS=y
883CONFIG_SECURITY=y
884# CONFIG_SECURITYFS is not set
885# CONFIG_SECURITY_NETWORK is not set
886# CONFIG_SECURITY_PATH is not set
887# CONFIG_SECURITY_FILE_CAPABILITIES is not set
888CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
889CONFIG_CRYPTO=y
890
891#
892# Crypto core or helper
893#
894# CONFIG_CRYPTO_FIPS is not set
895CONFIG_CRYPTO_ALGAPI=y
896CONFIG_CRYPTO_ALGAPI2=y
897CONFIG_CRYPTO_AEAD2=y
898CONFIG_CRYPTO_BLKCIPHER=y
899CONFIG_CRYPTO_BLKCIPHER2=y
900CONFIG_CRYPTO_HASH=y
901CONFIG_CRYPTO_HASH2=y
902CONFIG_CRYPTO_RNG2=y
903CONFIG_CRYPTO_MANAGER=y
904CONFIG_CRYPTO_MANAGER2=y
905# CONFIG_CRYPTO_GF128MUL is not set
906# CONFIG_CRYPTO_NULL is not set
907# CONFIG_CRYPTO_CRYPTD is not set
908# CONFIG_CRYPTO_AUTHENC is not set
909CONFIG_CRYPTO_TEST=m
910
911#
912# Authenticated Encryption with Associated Data
913#
914# CONFIG_CRYPTO_CCM is not set
915# CONFIG_CRYPTO_GCM is not set
916# CONFIG_CRYPTO_SEQIV is not set
917
918#
919# Block modes
920#
921CONFIG_CRYPTO_CBC=y
922# CONFIG_CRYPTO_CTR is not set
923# CONFIG_CRYPTO_CTS is not set
924CONFIG_CRYPTO_ECB=y
925# CONFIG_CRYPTO_LRW is not set
926# CONFIG_CRYPTO_PCBC is not set
927# CONFIG_CRYPTO_XTS is not set
928
929#
930# Hash modes
931#
932CONFIG_CRYPTO_HMAC=y
933# CONFIG_CRYPTO_XCBC is not set
934
935#
936# Digest
937#
938# CONFIG_CRYPTO_CRC32C is not set
939# CONFIG_CRYPTO_MD4 is not set
940CONFIG_CRYPTO_MD5=y
941# CONFIG_CRYPTO_MICHAEL_MIC is not set
942# CONFIG_CRYPTO_RMD128 is not set
943# CONFIG_CRYPTO_RMD160 is not set
944# CONFIG_CRYPTO_RMD256 is not set
945# CONFIG_CRYPTO_RMD320 is not set
946CONFIG_CRYPTO_SHA1=m
947# CONFIG_CRYPTO_SHA256 is not set
948# CONFIG_CRYPTO_SHA512 is not set
949# CONFIG_CRYPTO_TGR192 is not set
950# CONFIG_CRYPTO_WP512 is not set
951
952#
953# Ciphers
954#
955CONFIG_CRYPTO_AES=m
956# CONFIG_CRYPTO_ANUBIS is not set
957# CONFIG_CRYPTO_ARC4 is not set
958# CONFIG_CRYPTO_BLOWFISH is not set
959# CONFIG_CRYPTO_CAMELLIA is not set
960# CONFIG_CRYPTO_CAST5 is not set
961# CONFIG_CRYPTO_CAST6 is not set
962CONFIG_CRYPTO_DES=y
963# CONFIG_CRYPTO_FCRYPT is not set
964# CONFIG_CRYPTO_KHAZAD is not set
965# CONFIG_CRYPTO_SALSA20 is not set
966# CONFIG_CRYPTO_SEED is not set
967# CONFIG_CRYPTO_SERPENT is not set
968# CONFIG_CRYPTO_TEA is not set
969# CONFIG_CRYPTO_TWOFISH is not set
970
971#
972# Compression
973#
974CONFIG_CRYPTO_DEFLATE=y
975CONFIG_CRYPTO_LZO=y
976
977#
978# Random Number Generation
979#
980# CONFIG_CRYPTO_ANSI_CPRNG is not set
981CONFIG_CRYPTO_HW=y
982
983#
984# Library routines
985#
986CONFIG_BITREVERSE=y
987CONFIG_GENERIC_FIND_LAST_BIT=y
988CONFIG_CRC_CCITT=m
989CONFIG_CRC16=y
990# CONFIG_CRC_T10DIF is not set
991# CONFIG_CRC_ITU_T is not set
992CONFIG_CRC32=y
993# CONFIG_CRC7 is not set
994# CONFIG_LIBCRC32C is not set
995CONFIG_ZLIB_INFLATE=y
996CONFIG_ZLIB_DEFLATE=y
997CONFIG_LZO_COMPRESS=y
998CONFIG_LZO_DECOMPRESS=y
999CONFIG_PLIST=y
1000CONFIG_HAS_IOMEM=y
1001CONFIG_HAS_IOPORT=y
1002CONFIG_HAS_DMA=y
diff --git a/arch/arm/mach-stmp378x/Makefile b/arch/arm/mach-stmp378x/Makefile
new file mode 100644
index 000000000000..d156f76b379f
--- /dev/null
+++ b/arch/arm/mach-stmp378x/Makefile
@@ -0,0 +1,2 @@
1obj-$(CONFIG_ARCH_STMP378X) += stmp378x.o
2obj-$(CONFIG_MACH_STMP378X) += stmp378x_devb.o
diff --git a/arch/arm/mach-stmp378x/Makefile.boot b/arch/arm/mach-stmp378x/Makefile.boot
new file mode 100644
index 000000000000..1568ad404d59
--- /dev/null
+++ b/arch/arm/mach-stmp378x/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x40008000
2params_phys-y := 0x40000100
3initrd_phys-y := 0x40800000
diff --git a/arch/arm/mach-stmp378x/include/mach/entry-macro.S b/arch/arm/mach-stmp378x/include/mach/entry-macro.S
new file mode 100644
index 000000000000..731a92286da2
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/entry-macro.S
@@ -0,0 +1,35 @@
1/*
2 * Low-level IRQ helper macros for Freescale STMP378X
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18
19 .macro disable_fiq
20 .endm
21
22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
23
24 mov \base, #0xf0000000 @ vm address of IRQ controller
25 ldr \irqnr, [\base, #0x70] @ HW_ICOLL_STAT
26 cmp \irqnr, #0x7f
27 moveqs \irqnr, #0 @ Zero flag set for no IRQ
28
29 .endm
30
31 .macro get_irqnr_preamble, base, tmp
32 .endm
33
34 .macro arch_ret_to_user, tmp1, tmp2
35 .endm
diff --git a/arch/arm/mach-stmp378x/include/mach/irqs.h b/arch/arm/mach-stmp378x/include/mach/irqs.h
new file mode 100644
index 000000000000..cc59673becdd
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/irqs.h
@@ -0,0 +1,95 @@
1/*
2 * Freescale STMP378X interrupts
3 *
4 * Copyright (C) 2005 Sigmatel Inc
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18
19#define IRQ_DEBUG_UART 0
20#define IRQ_COMMS_RX 1
21#define IRQ_COMMS_TX 1
22#define IRQ_SSP2_ERROR 2
23#define IRQ_VDD5V 3
24#define IRQ_HEADPHONE_SHORT 4
25#define IRQ_DAC_DMA 5
26#define IRQ_DAC_ERROR 6
27#define IRQ_ADC_DMA 7
28#define IRQ_ADC_ERROR 8
29#define IRQ_SPDIF_DMA 9
30#define IRQ_SAIF2_DMA 9
31#define IRQ_SPDIF_ERROR 10
32#define IRQ_SAIF1_IRQ 10
33#define IRQ_SAIF2_IRQ 10
34#define IRQ_USB_CTRL 11
35#define IRQ_USB_WAKEUP 12
36#define IRQ_GPMI_DMA 13
37#define IRQ_SSP1_DMA 14
38#define IRQ_SSP_ERROR 15
39#define IRQ_GPIO0 16
40#define IRQ_GPIO1 17
41#define IRQ_GPIO2 18
42#define IRQ_SAIF1_DMA 19
43#define IRQ_SSP2_DMA 20
44#define IRQ_ECC8_IRQ 21
45#define IRQ_RTC_ALARM 22
46#define IRQ_UARTAPP_TX_DMA 23
47#define IRQ_UARTAPP_INTERNAL 24
48#define IRQ_UARTAPP_RX_DMA 25
49#define IRQ_I2C_DMA 26
50#define IRQ_I2C_ERROR 27
51#define IRQ_TIMER0 28
52#define IRQ_TIMER1 29
53#define IRQ_TIMER2 30
54#define IRQ_TIMER3 31
55#define IRQ_BATT_BRNOUT 32
56#define IRQ_VDDD_BRNOUT 33
57#define IRQ_VDDIO_BRNOUT 34
58#define IRQ_VDD18_BRNOUT 35
59#define IRQ_TOUCH_DETECT 36
60#define IRQ_LRADC_CH0 37
61#define IRQ_LRADC_CH1 38
62#define IRQ_LRADC_CH2 39
63#define IRQ_LRADC_CH3 40
64#define IRQ_LRADC_CH4 41
65#define IRQ_LRADC_CH5 42
66#define IRQ_LRADC_CH6 43
67#define IRQ_LRADC_CH7 44
68#define IRQ_LCDIF_DMA 45
69#define IRQ_LCDIF_ERROR 46
70#define IRQ_DIGCTL_DEBUG_TRAP 47
71#define IRQ_RTC_1MSEC 48
72#define IRQ_DRI_DMA 49
73#define IRQ_DRI_ATTENTION 50
74#define IRQ_GPMI_ATTENTION 51
75#define IRQ_IR 52
76#define IRQ_DCP_VMI 53
77#define IRQ_DCP 54
78#define IRQ_BCH 56
79#define IRQ_PXP 57
80#define IRQ_UARTAPP2_TX_DMA 58
81#define IRQ_UARTAPP2_INTERNAL 59
82#define IRQ_UARTAPP2_RX_DMA 60
83#define IRQ_VDAC_DETECT 61
84#define IRQ_VDD5V_DROOP 64
85#define IRQ_DCDC4P2_BO 65
86
87
88#define NR_REAL_IRQS 128
89#define NR_IRQS (NR_REAL_IRQS + 32 * 3)
90
91/* All interrupts are FIQ capable */
92#define FIQ_START IRQ_DEBUG_UART
93
94/* Hard disk IRQ is a GPMI attention IRQ */
95#define IRQ_HARDDISK IRQ_GPMI_ATTENTION
diff --git a/arch/arm/mach-stmp378x/include/mach/pins.h b/arch/arm/mach-stmp378x/include/mach/pins.h
new file mode 100644
index 000000000000..93f952d35969
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/pins.h
@@ -0,0 +1,151 @@
1/*
2 * Freescale STMP378X SoC pin multiplexing
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_ARCH_PINS_H
19#define __ASM_ARCH_PINS_H
20
21/*
22 * Define all STMP378x pins, a pin name corresponds to a STMP378x hardware
23 * interface this pin belongs to.
24 */
25
26/* Bank 0 */
27#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0)
28#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1)
29#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2)
30#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3)
31#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4)
32#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5)
33#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6)
34#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7)
35#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8)
36#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9)
37#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10)
38#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11)
39#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12)
40#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13)
41#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14)
42#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15)
43#define PINID_GPMI_CLE STMP3XXX_PINID(0, 16)
44#define PINID_GPMI_ALE STMP3XXX_PINID(0, 17)
45#define PINID_GMPI_CE2N STMP3XXX_PINID(0, 18)
46#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19)
47#define PINID_GPMI_RDY1 STMP3XXX_PINID(0, 20)
48#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 21)
49#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 22)
50#define PINID_GPMI_WPN STMP3XXX_PINID(0, 23)
51#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24)
52#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25)
53#define PINID_AUART1_CTS STMP3XXX_PINID(0, 26)
54#define PINID_AUART1_RTS STMP3XXX_PINID(0, 27)
55#define PINID_AUART1_RX STMP3XXX_PINID(0, 28)
56#define PINID_AUART1_TX STMP3XXX_PINID(0, 29)
57#define PINID_I2C_SCL STMP3XXX_PINID(0, 30)
58#define PINID_I2C_SDA STMP3XXX_PINID(0, 31)
59
60/* Bank 1 */
61#define PINID_LCD_D00 STMP3XXX_PINID(1, 0)
62#define PINID_LCD_D01 STMP3XXX_PINID(1, 1)
63#define PINID_LCD_D02 STMP3XXX_PINID(1, 2)
64#define PINID_LCD_D03 STMP3XXX_PINID(1, 3)
65#define PINID_LCD_D04 STMP3XXX_PINID(1, 4)
66#define PINID_LCD_D05 STMP3XXX_PINID(1, 5)
67#define PINID_LCD_D06 STMP3XXX_PINID(1, 6)
68#define PINID_LCD_D07 STMP3XXX_PINID(1, 7)
69#define PINID_LCD_D08 STMP3XXX_PINID(1, 8)
70#define PINID_LCD_D09 STMP3XXX_PINID(1, 9)
71#define PINID_LCD_D10 STMP3XXX_PINID(1, 10)
72#define PINID_LCD_D11 STMP3XXX_PINID(1, 11)
73#define PINID_LCD_D12 STMP3XXX_PINID(1, 12)
74#define PINID_LCD_D13 STMP3XXX_PINID(1, 13)
75#define PINID_LCD_D14 STMP3XXX_PINID(1, 14)
76#define PINID_LCD_D15 STMP3XXX_PINID(1, 15)
77#define PINID_LCD_D16 STMP3XXX_PINID(1, 16)
78#define PINID_LCD_D17 STMP3XXX_PINID(1, 17)
79#define PINID_LCD_RESET STMP3XXX_PINID(1, 18)
80#define PINID_LCD_RS STMP3XXX_PINID(1, 19)
81#define PINID_LCD_WR STMP3XXX_PINID(1, 20)
82#define PINID_LCD_CS STMP3XXX_PINID(1, 21)
83#define PINID_LCD_DOTCK STMP3XXX_PINID(1, 22)
84#define PINID_LCD_ENABLE STMP3XXX_PINID(1, 23)
85#define PINID_LCD_HSYNC STMP3XXX_PINID(1, 24)
86#define PINID_LCD_VSYNC STMP3XXX_PINID(1, 25)
87#define PINID_PWM0 STMP3XXX_PINID(1, 26)
88#define PINID_PWM1 STMP3XXX_PINID(1, 27)
89#define PINID_PWM2 STMP3XXX_PINID(1, 28)
90#define PINID_PWM3 STMP3XXX_PINID(1, 29)
91#define PINID_PWM4 STMP3XXX_PINID(1, 30)
92
93/* Bank 2 */
94#define PINID_SSP1_CMD STMP3XXX_PINID(2, 0)
95#define PINID_SSP1_DETECT STMP3XXX_PINID(2, 1)
96#define PINID_SSP1_DATA0 STMP3XXX_PINID(2, 2)
97#define PINID_SSP1_DATA1 STMP3XXX_PINID(2, 3)
98#define PINID_SSP1_DATA2 STMP3XXX_PINID(2, 4)
99#define PINID_SSP1_DATA3 STMP3XXX_PINID(2, 5)
100#define PINID_SSP1_SCK STMP3XXX_PINID(2, 6)
101#define PINID_ROTARYA STMP3XXX_PINID(2, 7)
102#define PINID_ROTARYB STMP3XXX_PINID(2, 8)
103#define PINID_EMI_A00 STMP3XXX_PINID(2, 9)
104#define PINID_EMI_A01 STMP3XXX_PINID(2, 10)
105#define PINID_EMI_A02 STMP3XXX_PINID(2, 11)
106#define PINID_EMI_A03 STMP3XXX_PINID(2, 12)
107#define PINID_EMI_A04 STMP3XXX_PINID(2, 13)
108#define PINID_EMI_A05 STMP3XXX_PINID(2, 14)
109#define PINID_EMI_A06 STMP3XXX_PINID(2, 15)
110#define PINID_EMI_A07 STMP3XXX_PINID(2, 16)
111#define PINID_EMI_A08 STMP3XXX_PINID(2, 17)
112#define PINID_EMI_A09 STMP3XXX_PINID(2, 18)
113#define PINID_EMI_A10 STMP3XXX_PINID(2, 19)
114#define PINID_EMI_A11 STMP3XXX_PINID(2, 20)
115#define PINID_EMI_A12 STMP3XXX_PINID(2, 21)
116#define PINID_EMI_BA0 STMP3XXX_PINID(2, 22)
117#define PINID_EMI_BA1 STMP3XXX_PINID(2, 23)
118#define PINID_EMI_CASN STMP3XXX_PINID(2, 24)
119#define PINID_EMI_CE0N STMP3XXX_PINID(2, 25)
120#define PINID_EMI_CE1N STMP3XXX_PINID(2, 26)
121#define PINID_GPMI_CE1N STMP3XXX_PINID(2, 27)
122#define PINID_GPMI_CE0N STMP3XXX_PINID(2, 28)
123#define PINID_EMI_CKE STMP3XXX_PINID(2, 29)
124#define PINID_EMI_RASN STMP3XXX_PINID(2, 30)
125#define PINID_EMI_WEN STMP3XXX_PINID(2, 31)
126
127/* Bank 3 */
128#define PINID_EMI_D00 STMP3XXX_PINID(3, 0)
129#define PINID_EMI_D01 STMP3XXX_PINID(3, 1)
130#define PINID_EMI_D02 STMP3XXX_PINID(3, 2)
131#define PINID_EMI_D03 STMP3XXX_PINID(3, 3)
132#define PINID_EMI_D04 STMP3XXX_PINID(3, 4)
133#define PINID_EMI_D05 STMP3XXX_PINID(3, 5)
134#define PINID_EMI_D06 STMP3XXX_PINID(3, 6)
135#define PINID_EMI_D07 STMP3XXX_PINID(3, 7)
136#define PINID_EMI_D08 STMP3XXX_PINID(3, 8)
137#define PINID_EMI_D09 STMP3XXX_PINID(3, 9)
138#define PINID_EMI_D10 STMP3XXX_PINID(3, 10)
139#define PINID_EMI_D11 STMP3XXX_PINID(3, 11)
140#define PINID_EMI_D12 STMP3XXX_PINID(3, 12)
141#define PINID_EMI_D13 STMP3XXX_PINID(3, 13)
142#define PINID_EMI_D14 STMP3XXX_PINID(3, 14)
143#define PINID_EMI_D15 STMP3XXX_PINID(3, 15)
144#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 16)
145#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 17)
146#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 18)
147#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 19)
148#define PINID_EMI_CLK STMP3XXX_PINID(3, 20)
149#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21)
150
151#endif /* __ASM_ARCH_PINS_H */
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h
new file mode 100644
index 000000000000..dbcf85b6ac2a
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h
@@ -0,0 +1,101 @@
1/*
2 * stmp378x: APBH register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_APBH
22#define _MACH_REGS_APBH
23
24#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000)
25#define REGS_APBH_PHYS 0x80004000
26#define REGS_APBH_SIZE 0x2000
27
28#define HW_APBH_CTRL0 0x0
29#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
30#define BP_APBH_CTRL0_RESET_CHANNEL 16
31#define BM_APBH_CTRL0_CLKGATE 0x40000000
32#define BM_APBH_CTRL0_SFTRST 0x80000000
33
34#define HW_APBH_CTRL1 0x10
35#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
36#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
37
38#define HW_APBH_CTRL2 0x20
39
40#define HW_APBH_DEVSEL 0x30
41
42#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70)
43#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70)
44#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70)
45#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70)
46#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70)
47#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70)
48#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70)
49#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70)
50#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70)
51#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70)
52#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70)
53#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70)
54#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70)
55#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70)
56#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70)
57#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70)
58
59#define HW_APBH_CHn_NXTCMDAR 0x50
60
61#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0
62#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 1
63#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 2
64#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 3
65#define BM_APBH_CHn_CMD_COMMAND 0x00000003
66#define BP_APBH_CHn_CMD_COMMAND 0
67#define BM_APBH_CHn_CMD_CHAIN 0x00000004
68#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
69#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
70#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
71#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
72#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
73#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
74#define BP_APBH_CHn_CMD_CMDWORDS 12
75#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
76#define BP_APBH_CHn_CMD_XFER_COUNT 16
77
78#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70)
79#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70)
80#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70)
81#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70)
82#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70)
83#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70)
84#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70)
85#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70)
86#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70)
87#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70)
88#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70)
89#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70)
90#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70)
91#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70)
92#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70)
93#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70)
94
95#define HW_APBH_CHn_SEMA 0x80
96#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
97#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
98#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
99#define BP_APBH_CHn_SEMA_PHORE 16
100
101#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h
new file mode 100644
index 000000000000..3b934a4d27f0
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h
@@ -0,0 +1,119 @@
1/*
2 * stmp378x: APBX register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_APBX
22#define _MACH_REGS_APBX
23
24#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000)
25#define REGS_APBX_PHYS 0x80024000
26#define REGS_APBX_SIZE 0x2000
27
28#define HW_APBX_CTRL0 0x0
29#define BM_APBX_CTRL0_CLKGATE 0x40000000
30#define BM_APBX_CTRL0_SFTRST 0x80000000
31
32#define HW_APBX_CTRL1 0x10
33
34#define HW_APBX_CTRL2 0x20
35
36#define HW_APBX_CHANNEL_CTRL 0x30
37#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000
38#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16
39
40#define HW_APBX_DEVSEL 0x40
41
42#define HW_APBX_CH0_NXTCMDAR (0x110 + 0 * 0x70)
43#define HW_APBX_CH1_NXTCMDAR (0x110 + 1 * 0x70)
44#define HW_APBX_CH2_NXTCMDAR (0x110 + 2 * 0x70)
45#define HW_APBX_CH3_NXTCMDAR (0x110 + 3 * 0x70)
46#define HW_APBX_CH4_NXTCMDAR (0x110 + 4 * 0x70)
47#define HW_APBX_CH5_NXTCMDAR (0x110 + 5 * 0x70)
48#define HW_APBX_CH6_NXTCMDAR (0x110 + 6 * 0x70)
49#define HW_APBX_CH7_NXTCMDAR (0x110 + 7 * 0x70)
50#define HW_APBX_CH8_NXTCMDAR (0x110 + 8 * 0x70)
51#define HW_APBX_CH9_NXTCMDAR (0x110 + 9 * 0x70)
52#define HW_APBX_CH10_NXTCMDAR (0x110 + 10 * 0x70)
53#define HW_APBX_CH11_NXTCMDAR (0x110 + 11 * 0x70)
54#define HW_APBX_CH12_NXTCMDAR (0x110 + 12 * 0x70)
55#define HW_APBX_CH13_NXTCMDAR (0x110 + 13 * 0x70)
56#define HW_APBX_CH14_NXTCMDAR (0x110 + 14 * 0x70)
57#define HW_APBX_CH15_NXTCMDAR (0x110 + 15 * 0x70)
58
59#define HW_APBX_CHn_NXTCMDAR 0x110
60#define BM_APBX_CHn_CMD_COMMAND 0x00000003
61#define BP_APBX_CHn_CMD_COMMAND 0
62#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0
63#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 1
64#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 2
65#define BV_APBX_CHn_CMD_COMMAND__DMA_SENSE 3
66#define BM_APBX_CHn_CMD_CHAIN 0x00000004
67#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
68#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
69#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
70#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100
71#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
72#define BP_APBX_CHn_CMD_CMDWORDS 12
73#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
74#define BP_APBX_CHn_CMD_XFER_COUNT 16
75
76#define HW_APBX_CH0_BAR (0x130 + 0 * 0x70)
77#define HW_APBX_CH1_BAR (0x130 + 1 * 0x70)
78#define HW_APBX_CH2_BAR (0x130 + 2 * 0x70)
79#define HW_APBX_CH3_BAR (0x130 + 3 * 0x70)
80#define HW_APBX_CH4_BAR (0x130 + 4 * 0x70)
81#define HW_APBX_CH5_BAR (0x130 + 5 * 0x70)
82#define HW_APBX_CH6_BAR (0x130 + 6 * 0x70)
83#define HW_APBX_CH7_BAR (0x130 + 7 * 0x70)
84#define HW_APBX_CH8_BAR (0x130 + 8 * 0x70)
85#define HW_APBX_CH9_BAR (0x130 + 9 * 0x70)
86#define HW_APBX_CH10_BAR (0x130 + 10 * 0x70)
87#define HW_APBX_CH11_BAR (0x130 + 11 * 0x70)
88#define HW_APBX_CH12_BAR (0x130 + 12 * 0x70)
89#define HW_APBX_CH13_BAR (0x130 + 13 * 0x70)
90#define HW_APBX_CH14_BAR (0x130 + 14 * 0x70)
91#define HW_APBX_CH15_BAR (0x130 + 15 * 0x70)
92
93#define HW_APBX_CHn_BAR 0x130
94
95#define HW_APBX_CH0_SEMA (0x140 + 0 * 0x70)
96#define HW_APBX_CH1_SEMA (0x140 + 1 * 0x70)
97#define HW_APBX_CH2_SEMA (0x140 + 2 * 0x70)
98#define HW_APBX_CH3_SEMA (0x140 + 3 * 0x70)
99#define HW_APBX_CH4_SEMA (0x140 + 4 * 0x70)
100#define HW_APBX_CH5_SEMA (0x140 + 5 * 0x70)
101#define HW_APBX_CH6_SEMA (0x140 + 6 * 0x70)
102#define HW_APBX_CH7_SEMA (0x140 + 7 * 0x70)
103#define HW_APBX_CH8_SEMA (0x140 + 8 * 0x70)
104#define HW_APBX_CH9_SEMA (0x140 + 9 * 0x70)
105#define HW_APBX_CH10_SEMA (0x140 + 10 * 0x70)
106#define HW_APBX_CH11_SEMA (0x140 + 11 * 0x70)
107#define HW_APBX_CH12_SEMA (0x140 + 12 * 0x70)
108#define HW_APBX_CH13_SEMA (0x140 + 13 * 0x70)
109#define HW_APBX_CH14_SEMA (0x140 + 14 * 0x70)
110#define HW_APBX_CH15_SEMA (0x140 + 15 * 0x70)
111
112#define HW_APBX_CHn_SEMA 0x140
113#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
114#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
115#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
116#define BP_APBX_CHn_SEMA_PHORE 16
117
118#endif
119
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h b/arch/arm/mach-stmp378x/include/mach/regs-audioin.h
new file mode 100644
index 000000000000..641ac6126f83
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-audioin.h
@@ -0,0 +1,63 @@
1/*
2 * stmp378x: AUDIOIN register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000)
22#define REGS_AUDIOIN_PHYS 0x8004C000
23#define REGS_AUDIOIN_SIZE 0x2000
24
25#define HW_AUDIOIN_CTRL 0x0
26#define BM_AUDIOIN_CTRL_RUN 0x00000001
27#define BP_AUDIOIN_CTRL_RUN 0
28#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
29#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
30#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
31#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020
32#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
33#define BM_AUDIOIN_CTRL_SFTRST 0x80000000
34
35#define HW_AUDIOIN_STAT 0x10
36
37#define HW_AUDIOIN_ADCSRR 0x20
38
39#define HW_AUDIOIN_ADCVOLUME 0x30
40#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF
41#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0
42#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000
43#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16
44
45#define HW_AUDIOIN_ADCDEBUG 0x40
46
47#define HW_AUDIOIN_ADCVOL 0x50
48#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F
49#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0
50#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030
51#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4
52#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00
53#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8
54#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000
55#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12
56#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000
57
58#define HW_AUDIOIN_MICLINE 0x60
59
60#define HW_AUDIOIN_ANACLKCTRL 0x70
61#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000
62
63#define HW_AUDIOIN_DATA 0x80
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h b/arch/arm/mach-stmp378x/include/mach/regs-audioout.h
new file mode 100644
index 000000000000..f533e23694a0
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-audioout.h
@@ -0,0 +1,104 @@
1/*
2 * stmp378x: AUDIOOUT register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000)
22#define REGS_AUDIOOUT_PHYS 0x80048000
23#define REGS_AUDIOOUT_SIZE 0x2000
24
25#define HW_AUDIOOUT_CTRL 0x0
26#define BM_AUDIOOUT_CTRL_RUN 0x00000001
27#define BP_AUDIOOUT_CTRL_RUN 0
28#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
29#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
30#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
31#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040
32#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000
33#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
34
35#define HW_AUDIOOUT_STAT 0x10
36
37#define HW_AUDIOOUT_DACSRR 0x20
38#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF
39#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0
40#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000
41#define BP_AUDIOOUT_DACSRR_SRC_INT 16
42#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000
43#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24
44#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000
45#define BP_AUDIOOUT_DACSRR_BASEMULT 28
46
47#define HW_AUDIOOUT_DACVOLUME 0x30
48#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100
49#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
50#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000
51
52#define HW_AUDIOOUT_DACDEBUG 0x40
53
54#define HW_AUDIOOUT_HPVOL 0x50
55#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000
56#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000
57
58#define HW_AUDIOOUT_PWRDN 0x70
59#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001
60#define BP_AUDIOOUT_PWRDN_HEADPHONE 0
61#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010
62#define BM_AUDIOOUT_PWRDN_ADC 0x00000100
63#define BM_AUDIOOUT_PWRDN_DAC 0x00001000
64#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000
65#define BM_AUDIOOUT_PWRDN_SPEAKER 0x01000000
66
67#define HW_AUDIOOUT_REFCTRL 0x80
68#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0
69#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4
70#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00
71#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8
72#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000
73#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000
74#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000
75#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16
76#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000
77#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000
78#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20
79#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000
80#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000
81
82#define HW_AUDIOOUT_ANACTRL 0x90
83#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010
84#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
85
86#define HW_AUDIOOUT_TEST 0xA0
87#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000
88#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22
89
90#define HW_AUDIOOUT_BISTCTRL 0xB0
91
92#define HW_AUDIOOUT_BISTSTAT0 0xC0
93
94#define HW_AUDIOOUT_BISTSTAT1 0xD0
95
96#define HW_AUDIOOUT_ANACLKCTRL 0xE0
97#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000
98
99#define HW_AUDIOOUT_DATA 0xF0
100
101#define HW_AUDIOOUT_SPEAKERCTRL 0x100
102#define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x01000000
103
104#define HW_AUDIOOUT_VERSION 0x200
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-bch.h b/arch/arm/mach-stmp378x/include/mach/regs-bch.h
new file mode 100644
index 000000000000..532d24650717
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-bch.h
@@ -0,0 +1,56 @@
1/*
2 * stmp378x: BCH register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_BCH_BASE (STMP3XXX_REGS_BASE + 0xA000)
22#define REGS_BCH_PHYS 0x8000A000
23#define REGS_BCH_SIZE 0x2000
24
25#define HW_BCH_CTRL 0x0
26#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001
27#define BP_BCH_CTRL_COMPLETE_IRQ 0
28#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100
29
30#define HW_BCH_STATUS0 0x10
31#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004
32#define BM_BCH_STATUS0_CORRECTED 0x00000008
33#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00
34#define BP_BCH_STATUS0_STATUS_BLK0 8
35#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000
36#define BP_BCH_STATUS0_COMPLETED_CE 16
37
38#define HW_BCH_LAYOUTSELECT 0x70
39
40#define HW_BCH_FLASH0LAYOUT0 0x80
41#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF
42#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0
43#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000
44#define BP_BCH_FLASH0LAYOUT0_ECC0 12
45#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000
46#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16
47#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000
48#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24
49#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF
50#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0
51#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000
52#define BP_BCH_FLASH0LAYOUT1_ECCN 12
53#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000
54#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16
55
56#define HW_BCH_BLOCKNAME 0x150
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h
new file mode 100644
index 000000000000..7c546afd57a3
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h
@@ -0,0 +1,88 @@
1/*
2 * stmp378x: CLKCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_CLKCTRL
22#define _MACH_REGS_CLKCTRL
23
24#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000)
25#define REGS_CLKCTRL_PHYS 0x80040000
26#define REGS_CLKCTRL_SIZE 0x2000
27
28#define HW_CLKCTRL_PLLCTRL0 0x0
29#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
30
31#define HW_CLKCTRL_CPU 0x20
32#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
33#define BP_CLKCTRL_CPU_DIV_CPU 0
34
35#define HW_CLKCTRL_HBUS 0x30
36#define BM_CLKCTRL_HBUS_DIV 0x0000001F
37#define BP_CLKCTRL_HBUS_DIV 0
38#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
39
40#define HW_CLKCTRL_XBUS 0x40
41
42#define HW_CLKCTRL_XTAL 0x50
43#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
44
45#define HW_CLKCTRL_PIX 0x60
46#define BM_CLKCTRL_PIX_DIV 0x00000FFF
47#define BP_CLKCTRL_PIX_DIV 0
48#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
49
50#define HW_CLKCTRL_SSP 0x70
51
52#define HW_CLKCTRL_GPMI 0x80
53
54#define HW_CLKCTRL_SPDIF 0x90
55
56#define HW_CLKCTRL_EMI 0xA0
57#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
58#define BP_CLKCTRL_EMI_DIV_EMI 0
59#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
60#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
61#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
62#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
63
64#define HW_CLKCTRL_IR 0xB0
65
66#define HW_CLKCTRL_SAIF 0xC0
67
68#define HW_CLKCTRL_TV 0xD0
69
70#define HW_CLKCTRL_ETM 0xE0
71
72#define HW_CLKCTRL_FRAC 0xF0
73#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
74#define BP_CLKCTRL_FRAC_EMIFRAC 8
75#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
76#define BP_CLKCTRL_FRAC_PIXFRAC 16
77#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
78
79#define HW_CLKCTRL_FRAC1 0x100
80
81#define HW_CLKCTRL_CLKSEQ 0x110
82#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
83
84#define HW_CLKCTRL_RESET 0x120
85#define BM_CLKCTRL_RESET_DIG 0x00000001
86#define BP_CLKCTRL_RESET_DIG 0
87
88#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h b/arch/arm/mach-stmp378x/include/mach/regs-dcp.h
new file mode 100644
index 000000000000..fdedd00c0e28
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-dcp.h
@@ -0,0 +1,87 @@
1/*
2 * stmp378x: DCP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DCP_BASE (STMP3XXX_REGS_BASE + 0x28000)
22#define REGS_DCP_PHYS 0x80028000
23#define REGS_DCP_SIZE 0x2000
24
25#define HW_DCP_CTRL 0x0
26#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0x000000FF
27#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0
28#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x00400000
29#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x00800000
30#define BM_DCP_CTRL_CLKGATE 0x40000000
31#define BM_DCP_CTRL_SFTRST 0x80000000
32
33#define HW_DCP_STAT 0x10
34#define BM_DCP_STAT_IRQ 0x0000000F
35#define BP_DCP_STAT_IRQ 0
36
37#define HW_DCP_CHANNELCTRL 0x20
38#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0x000000FF
39#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0
40
41#define HW_DCP_CONTEXT 0x50
42#define BM_DCP_PACKET1_INTERRUPT 0x00000001
43#define BP_DCP_PACKET1_INTERRUPT 0
44#define BM_DCP_PACKET1_DECR_SEMAPHORE 0x00000002
45#define BM_DCP_PACKET1_CHAIN 0x00000004
46#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x00000008
47#define BM_DCP_PACKET1_ENABLE_CIPHER 0x00000020
48#define BM_DCP_PACKET1_ENABLE_HASH 0x00000040
49#define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x00000100
50#define BM_DCP_PACKET1_CIPHER_INIT 0x00000200
51#define BM_DCP_PACKET1_OTP_KEY 0x00000400
52#define BM_DCP_PACKET1_PAYLOAD_KEY 0x00000800
53#define BM_DCP_PACKET1_HASH_INIT 0x00001000
54#define BM_DCP_PACKET1_HASH_TERM 0x00002000
55#define BM_DCP_PACKET2_CIPHER_SELECT 0x0000000F
56#define BP_DCP_PACKET2_CIPHER_SELECT 0
57#define BM_DCP_PACKET2_CIPHER_MODE 0x000000F0
58#define BP_DCP_PACKET2_CIPHER_MODE 4
59#define BM_DCP_PACKET2_KEY_SELECT 0x0000FF00
60#define BP_DCP_PACKET2_KEY_SELECT 8
61#define BM_DCP_PACKET2_HASH_SELECT 0x000F0000
62#define BP_DCP_PACKET2_HASH_SELECT 16
63#define BM_DCP_PACKET2_CIPHER_CFG 0xFF000000
64#define BP_DCP_PACKET2_CIPHER_CFG 24
65
66#define HW_DCP_CH0CMDPTR (0x100 + 0 * 0x40)
67#define HW_DCP_CH1CMDPTR (0x100 + 1 * 0x40)
68#define HW_DCP_CH2CMDPTR (0x100 + 2 * 0x40)
69#define HW_DCP_CH3CMDPTR (0x100 + 3 * 0x40)
70
71#define HW_DCP_CHnCMDPTR 0x100
72
73#define HW_DCP_CH0SEMA (0x110 + 0 * 0x40)
74#define HW_DCP_CH1SEMA (0x110 + 1 * 0x40)
75#define HW_DCP_CH2SEMA (0x110 + 2 * 0x40)
76#define HW_DCP_CH3SEMA (0x110 + 3 * 0x40)
77
78#define HW_DCP_CHnSEMA 0x110
79#define BM_DCP_CHnSEMA_INCREMENT 0x000000FF
80#define BP_DCP_CHnSEMA_INCREMENT 0
81
82#define HW_DCP_CH0STAT (0x120 + 0 * 0x40)
83#define HW_DCP_CH1STAT (0x120 + 1 * 0x40)
84#define HW_DCP_CH2STAT (0x120 + 2 * 0x40)
85#define HW_DCP_CH3STAT (0x120 + 3 * 0x40)
86
87#define HW_DCP_CHnSTAT 0x120
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h b/arch/arm/mach-stmp378x/include/mach/regs-digctl.h
new file mode 100644
index 000000000000..5293005523b3
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-digctl.h
@@ -0,0 +1,38 @@
1/*
2 * stmp378x: DIGCTL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000)
22#define REGS_DIGCTL_PHYS 0x8001C000
23#define REGS_DIGCTL_SIZE 0x2000
24
25#define HW_DIGCTL_CTRL 0x0
26#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004
27
28#define HW_DIGCTL_ARMCACHE 0x2B0
29#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x00000003
30#define BP_DIGCTL_ARMCACHE_ITAG_SS 0
31#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x00000030
32#define BP_DIGCTL_ARMCACHE_DTAG_SS 4
33#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x00000300
34#define BP_DIGCTL_ARMCACHE_CACHE_SS 8
35#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x00003000
36#define BP_DIGCTL_ARMCACHE_DRTY_SS 12
37#define BM_DIGCTL_ARMCACHE_VALID_SS 0x00030000
38#define BP_DIGCTL_ARMCACHE_VALID_SS 16
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dram.h b/arch/arm/mach-stmp378x/include/mach/regs-dram.h
new file mode 100644
index 000000000000..02851431677c
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-dram.h
@@ -0,0 +1,27 @@
1/*
2 * stmp378x: DRAM register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DRAM_BASE (STMP3XXX_REGS_BASE + 0xE0000)
22#define REGS_DRAM_PHYS 0x800E0000
23#define REGS_DRAM_SIZE 0x2000
24
25#define HW_DRAM_CTL06 0x18
26
27#define HW_DRAM_CTL08 0x20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dri.h b/arch/arm/mach-stmp378x/include/mach/regs-dri.h
new file mode 100644
index 000000000000..da25f7e397e5
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-dri.h
@@ -0,0 +1,45 @@
1/*
2 * stmp378x: DRI register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DRI_BASE (STMP3XXX_REGS_BASE + 0x74000)
22#define REGS_DRI_PHYS 0x80074000
23#define REGS_DRI_SIZE 0x2000
24
25#define HW_DRI_CTRL 0x0
26#define BM_DRI_CTRL_RUN 0x00000001
27#define BP_DRI_CTRL_RUN 0
28#define BM_DRI_CTRL_ATTENTION_IRQ 0x00000002
29#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x00000004
30#define BM_DRI_CTRL_OVERFLOW_IRQ 0x00000008
31#define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x00000200
32#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x00000400
33#define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x00000800
34#define BM_DRI_CTRL_REACQUIRE_PHASE 0x00008000
35#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x02000000
36#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x04000000
37#define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000
38#define BM_DRI_CTRL_CLKGATE 0x40000000
39#define BM_DRI_CTRL_SFTRST 0x80000000
40
41#define HW_DRI_TIMING 0x10
42#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0x000000FF
43#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0
44#define BM_DRI_TIMING_PILOT_REP_RATE 0x000F0000
45#define BP_DRI_TIMING_PILOT_REP_RATE 16
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h b/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h
new file mode 100644
index 000000000000..cc353bec331b
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h
@@ -0,0 +1,39 @@
1/*
2 * stmp378x: ECC8 register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000)
22#define REGS_ECC8_PHYS 0x80008000
23#define REGS_ECC8_SIZE 0x2000
24
25#define HW_ECC8_CTRL 0x0
26#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001
27#define BP_ECC8_CTRL_COMPLETE_IRQ 0
28#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100
29#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000
30
31#define HW_ECC8_STATUS0 0x10
32#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004
33#define BM_ECC8_STATUS0_CORRECTED 0x00000008
34#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00
35#define BP_ECC8_STATUS0_STATUS_AUX 8
36#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000
37#define BP_ECC8_STATUS0_COMPLETED_CE 16
38
39#define HW_ECC8_STATUS1 0x20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-emi.h b/arch/arm/mach-stmp378x/include/mach/regs-emi.h
new file mode 100644
index 000000000000..98773fc33d7b
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-emi.h
@@ -0,0 +1,25 @@
1/*
2 * stmp378x: EMI register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_EMI_BASE (STMP3XXX_REGS_BASE + 0x20000)
22#define REGS_EMI_PHYS 0x80020000
23#define REGS_EMI_SIZE 0x2000
24
25#define HW_EMI_STAT 0x10
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h b/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h
new file mode 100644
index 000000000000..2cc8bbe91687
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h
@@ -0,0 +1,78 @@
1/*
2 * stmp378x: GPMI register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000)
22#define REGS_GPMI_PHYS 0x8000C000
23#define REGS_GPMI_SIZE 0x2000
24
25#define HW_GPMI_CTRL0 0x0
26#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_GPMI_CTRL0_XFER_COUNT 0
28#define BM_GPMI_CTRL0_CS 0x00300000
29#define BP_GPMI_CTRL0_CS 20
30#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
31#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
32#define BM_GPMI_CTRL0_ADDRESS 0x000E0000
33#define BP_GPMI_CTRL0_ADDRESS 17
34#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
35#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
36#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
37#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000
38#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
39#define BP_GPMI_CTRL0_COMMAND_MODE 24
40#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
41#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
42#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
43#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
44#define BM_GPMI_CTRL0_RUN 0x20000000
45#define BM_GPMI_CTRL0_CLKGATE 0x40000000
46#define BM_GPMI_CTRL0_SFTRST 0x80000000
47#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF
48#define BP_GPMI_ECCCTRL_BUFFER_MASK 0
49#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
50#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
51#define BP_GPMI_ECCCTRL_ECC_CMD 13
52#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0
53#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 1
54#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 2
55#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 3
56
57#define HW_GPMI_CTRL1 0x60
58#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
59#define BP_GPMI_CTRL1_GPMI_MODE 0
60#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
61#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
62#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
63#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
64#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
65#define BP_GPMI_CTRL1_RDN_DELAY 12
66#define BM_GPMI_CTRL1_BCH_MODE 0x00040000
67
68#define HW_GPMI_TIMING0 0x70
69#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
70#define BP_GPMI_TIMING0_DATA_SETUP 0
71#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
72#define BP_GPMI_TIMING0_DATA_HOLD 8
73#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000
74#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
75
76#define HW_GPMI_TIMING1 0x80
77#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
78#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h b/arch/arm/mach-stmp378x/include/mach/regs-i2c.h
new file mode 100644
index 000000000000..13a234c99433
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-i2c.h
@@ -0,0 +1,55 @@
1/*
2 * stmp378x: I2C register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000)
22#define REGS_I2C_PHYS 0x80058000
23#define REGS_I2C_SIZE 0x2000
24
25#define HW_I2C_CTRL0 0x0
26#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_I2C_CTRL0_XFER_COUNT 0
28#define BM_I2C_CTRL0_DIRECTION 0x00010000
29#define BM_I2C_CTRL0_MASTER_MODE 0x00020000
30#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000
31#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000
32#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000
33#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
34#define BM_I2C_CTRL0_CLKGATE 0x40000000
35#define BM_I2C_CTRL0_SFTRST 0x80000000
36
37#define HW_I2C_TIMING0 0x10
38
39#define HW_I2C_TIMING1 0x20
40
41#define HW_I2C_TIMING2 0x30
42
43#define HW_I2C_CTRL1 0x40
44#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001
45#define BP_I2C_CTRL1_SLAVE_IRQ 0
46#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002
47#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004
48#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008
49#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010
50#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020
51#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040
52#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080
53#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
54
55#define HW_I2C_VERSION 0x90
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h b/arch/arm/mach-stmp378x/include/mach/regs-icoll.h
new file mode 100644
index 000000000000..f996e80f40e7
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-icoll.h
@@ -0,0 +1,45 @@
1/*
2 * stmp378x: ICOLL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_ICOLL
22#define _MACH_REGS_ICOLL
23
24#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0)
25#define REGS_ICOLL_PHYS 0x80000000
26#define REGS_ICOLL_SIZE 0x2000
27
28#define HW_ICOLL_VECTOR 0x0
29
30#define HW_ICOLL_LEVELACK 0x10
31#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F
32#define BP_ICOLL_LEVELACK_IRQLEVELACK 0
33
34#define HW_ICOLL_CTRL 0x20
35#define BM_ICOLL_CTRL_CLKGATE 0x40000000
36#define BM_ICOLL_CTRL_SFTRST 0x80000000
37
38#define HW_ICOLL_STAT 0x70
39
40#define HW_ICOLL_INTERRUPTn 0x120
41
42#define HW_ICOLL_INTERRUPTn 0x120
43#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004
44
45#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ir.h b/arch/arm/mach-stmp378x/include/mach/regs-ir.h
new file mode 100644
index 000000000000..a5b4ef10fab8
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-ir.h
@@ -0,0 +1,23 @@
1/*
2 * stmp378x: IR register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_IR_BASE (STMP3XXX_REGS_BASE + 0x78000)
22#define REGS_IR_PHYS 0x80078000
23#define REGS_IR_SIZE 0x2000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h b/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h
new file mode 100644
index 000000000000..9cdbef4badc3
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h
@@ -0,0 +1,195 @@
1/*
2 * stmp378x: LCDIF register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000)
22#define REGS_LCDIF_PHYS 0x80030000
23#define REGS_LCDIF_SIZE 0x2000
24
25#define HW_LCDIF_CTRL 0x0
26#define BM_LCDIF_CTRL_RUN 0x00000001
27#define BP_LCDIF_CTRL_RUN 0
28#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020
29#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080
30#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300
31#define BP_LCDIF_CTRL_WORD_LENGTH 8
32#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00
33#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10
34#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000
35#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14
36#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000
37#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000
38#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000
39#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000
40#define BM_LCDIF_CTRL_DVI_MODE 0x00100000
41#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000
42#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21
43#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000
44#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000
45#define BM_LCDIF_CTRL_CLKGATE 0x40000000
46#define BM_LCDIF_CTRL_SFTRST 0x80000000
47
48#define HW_LCDIF_CTRL1 0x10
49#define BM_LCDIF_CTRL1_RESET 0x00000001
50#define BP_LCDIF_CTRL1_RESET 0
51#define BM_LCDIF_CTRL1_MODE86 0x00000002
52#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004
53#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100
54#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200
55#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400
56#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800
57#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000
58#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000
59#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16
60#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000
61#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000
62
63#define HW_LCDIF_TRANSFER_COUNT 0x20
64#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF
65#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0
66#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000
67#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16
68
69#define HW_LCDIF_CUR_BUF 0x30
70
71#define HW_LCDIF_NEXT_BUF 0x40
72
73#define HW_LCDIF_TIMING 0x60
74
75#define HW_LCDIF_VDCTRL0 0x70
76#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF
77#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0
78#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
79#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000
80#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000
81#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000
82#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000
83#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000
84#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
85#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000
86
87#define HW_LCDIF_VDCTRL1 0x80
88#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF
89#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0
90
91#define HW_LCDIF_VDCTRL2 0x90
92#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF
93#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0
94#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF000000
95#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 24
96
97#define HW_LCDIF_VDCTRL3 0xA0
98#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF
99#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0
100#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000
101#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16
102
103#define HW_LCDIF_VDCTRL4 0xB0
104#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF
105#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0
106#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000
107
108#define HW_LCDIF_DVICTRL0 0xC0
109#define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x000003FF
110#define BP_LCDIF_DVICTRL0_V_LINES_CNT 0
111#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x000FFC00
112#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10
113#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7FF00000
114#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20
115
116#define HW_LCDIF_DVICTRL1 0xD0
117#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF
118#define BP_LCDIF_DVICTRL1_F2_START_LINE 0
119#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00
120#define BP_LCDIF_DVICTRL1_F1_END_LINE 10
121#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000
122#define BP_LCDIF_DVICTRL1_F1_START_LINE 20
123
124#define HW_LCDIF_DVICTRL2 0xE0
125#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF
126#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0
127#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00
128#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10
129#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000
130#define BP_LCDIF_DVICTRL2_F2_END_LINE 20
131
132#define HW_LCDIF_DVICTRL3 0xF0
133#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000003FF
134#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0
135#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x03FF0000
136#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16
137
138#define HW_LCDIF_DVICTRL4 0x100
139#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF
140#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0
141#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00
142#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8
143#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000
144#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16
145#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000
146#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24
147
148#define HW_LCDIF_CSC_COEFF0 0x110
149#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003
150#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0
151#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000
152#define BP_LCDIF_CSC_COEFF0_C0 16
153
154#define HW_LCDIF_CSC_COEFF1 0x120
155#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF
156#define BP_LCDIF_CSC_COEFF1_C1 0
157#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000
158#define BP_LCDIF_CSC_COEFF1_C2 16
159
160#define HW_LCDIF_CSC_COEFF2 0x130
161#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF
162#define BP_LCDIF_CSC_COEFF2_C3 0
163#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000
164#define BP_LCDIF_CSC_COEFF2_C4 16
165
166#define HW_LCDIF_CSC_COEFF3 0x140
167#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF
168#define BP_LCDIF_CSC_COEFF3_C5 0
169#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000
170#define BP_LCDIF_CSC_COEFF3_C6 16
171
172#define HW_LCDIF_CSC_COEFF4 0x150
173#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF
174#define BP_LCDIF_CSC_COEFF4_C7 0
175#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000
176#define BP_LCDIF_CSC_COEFF4_C8 16
177
178#define HW_LCDIF_CSC_OFFSET 0x160
179#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF
180#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0
181#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000
182#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16
183
184#define HW_LCDIF_CSC_LIMIT 0x170
185#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF
186#define BP_LCDIF_CSC_LIMIT_Y_MAX 0
187#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00
188#define BP_LCDIF_CSC_LIMIT_Y_MIN 8
189#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000
190#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16
191#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000
192#define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24
193
194#define HW_LCDIF_STAT 0x1D0
195#define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h b/arch/arm/mach-stmp378x/include/mach/regs-lradc.h
new file mode 100644
index 000000000000..cb8cb06f8277
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-lradc.h
@@ -0,0 +1,99 @@
1/*
2 * stmp378x: LRADC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000)
22#define REGS_LRADC_PHYS 0x80050000
23#define REGS_LRADC_SIZE 0x2000
24
25#define HW_LRADC_CTRL0 0x0
26#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF
27#define BP_LRADC_CTRL0_SCHEDULE 0
28#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000
29#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000
30#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000
31#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000
32#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000
33#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000
34#define BM_LRADC_CTRL0_CLKGATE 0x40000000
35#define BM_LRADC_CTRL0_SFTRST 0x80000000
36
37#define HW_LRADC_CTRL1 0x10
38#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001
39#define BP_LRADC_CTRL1_LRADC0_IRQ 0
40#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020
41#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040
42#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100
43#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000
44#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000
45#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000
46
47#define HW_LRADC_CTRL2 0x20
48#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000
49#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16
50#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000
51#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000
52#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000
53#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24
54
55#define HW_LRADC_CTRL3 0x30
56#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300
57#define BP_LRADC_CTRL3_CYCLE_TIME 8
58
59#define HW_LRADC_STATUS 0x40
60#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001
61#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0
62
63#define HW_LRADC_CH0 (0x50 + 0 * 0x10)
64#define HW_LRADC_CH1 (0x50 + 1 * 0x10)
65#define HW_LRADC_CH2 (0x50 + 2 * 0x10)
66#define HW_LRADC_CH3 (0x50 + 3 * 0x10)
67#define HW_LRADC_CH4 (0x50 + 4 * 0x10)
68#define HW_LRADC_CH5 (0x50 + 5 * 0x10)
69#define HW_LRADC_CH6 (0x50 + 6 * 0x10)
70#define HW_LRADC_CH7 (0x50 + 7 * 0x10)
71
72#define HW_LRADC_CHn 0x50
73#define BM_LRADC_CHn_VALUE 0x0003FFFF
74#define BP_LRADC_CHn_VALUE 0
75#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000
76#define BP_LRADC_CHn_NUM_SAMPLES 24
77#define BM_LRADC_CHn_ACCUMULATE 0x20000000
78
79#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10)
80#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10)
81#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10)
82#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10)
83
84#define HW_LRADC_DELAYn 0xD0
85#define BM_LRADC_DELAYn_DELAY 0x000007FF
86#define BP_LRADC_DELAYn_DELAY 0
87#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800
88#define BP_LRADC_DELAYn_LOOP_COUNT 11
89#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000
90#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16
91#define BM_LRADC_DELAYn_KICK 0x00100000
92#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000
93#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24
94
95#define HW_LRADC_CTRL4 0x140
96#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000
97#define BP_LRADC_CTRL4_LRADC6SELECT 24
98#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000
99#define BP_LRADC_CTRL4_LRADC7SELECT 28
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h b/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h
new file mode 100644
index 000000000000..f0af64d9937e
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h
@@ -0,0 +1,40 @@
1/*
2 * stmp378x: OCOTP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_OCOTP_BASE (STMP3XXX_REGS_BASE + 0x2C000)
22#define REGS_OCOTP_PHYS 0x8002C000
23#define REGS_OCOTP_SIZE 0x2000
24
25#define HW_OCOTP_CTRL 0x0
26#define BM_OCOTP_CTRL_BUSY 0x00000100
27#define BM_OCOTP_CTRL_ERROR 0x00000200
28#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000
29#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000
30#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000
31#define BP_OCOTP_CTRL_WR_UNLOCK 16
32
33#define HW_OCOTP_DATA 0x10
34
35#define HW_OCOTP_CUST0 (0x20 + 0 * 0x10)
36#define HW_OCOTP_CUST1 (0x20 + 1 * 0x10)
37#define HW_OCOTP_CUST2 (0x20 + 2 * 0x10)
38#define HW_OCOTP_CUST3 (0x20 + 3 * 0x10)
39
40#define HW_OCOTP_CUSTn 0x20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h
new file mode 100644
index 000000000000..50d90ea1b136
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h
@@ -0,0 +1,90 @@
1/*
2 * stmp378x: PINCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_PINCTRL
22#define _MACH_REGS_PINCTRL
23
24#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000)
25#define REGS_PINCTRL_PHYS 0x80018000
26#define REGS_PINCTRL_SIZE 0x2000
27
28#define HW_PINCTRL_MUXSEL0 0x100
29#define HW_PINCTRL_MUXSEL1 0x110
30#define HW_PINCTRL_MUXSEL2 0x120
31#define HW_PINCTRL_MUXSEL3 0x130
32#define HW_PINCTRL_MUXSEL4 0x140
33#define HW_PINCTRL_MUXSEL5 0x150
34#define HW_PINCTRL_MUXSEL6 0x160
35#define HW_PINCTRL_MUXSEL7 0x170
36
37#define HW_PINCTRL_DRIVE0 0x200
38#define HW_PINCTRL_DRIVE1 0x210
39#define HW_PINCTRL_DRIVE2 0x220
40#define HW_PINCTRL_DRIVE3 0x230
41#define HW_PINCTRL_DRIVE4 0x240
42#define HW_PINCTRL_DRIVE5 0x250
43#define HW_PINCTRL_DRIVE6 0x260
44#define HW_PINCTRL_DRIVE7 0x270
45#define HW_PINCTRL_DRIVE8 0x280
46#define HW_PINCTRL_DRIVE9 0x290
47#define HW_PINCTRL_DRIVE10 0x2A0
48#define HW_PINCTRL_DRIVE11 0x2B0
49#define HW_PINCTRL_DRIVE12 0x2C0
50#define HW_PINCTRL_DRIVE13 0x2D0
51#define HW_PINCTRL_DRIVE14 0x2E0
52
53#define HW_PINCTRL_PULL0 0x400
54#define HW_PINCTRL_PULL1 0x410
55#define HW_PINCTRL_PULL2 0x420
56#define HW_PINCTRL_PULL3 0x430
57
58#define HW_PINCTRL_DOUT0 0x500
59#define HW_PINCTRL_DOUT1 0x510
60#define HW_PINCTRL_DOUT2 0x520
61
62#define HW_PINCTRL_DIN0 0x600
63#define HW_PINCTRL_DIN1 0x610
64#define HW_PINCTRL_DIN2 0x620
65
66#define HW_PINCTRL_DOE0 0x700
67#define HW_PINCTRL_DOE1 0x710
68#define HW_PINCTRL_DOE2 0x720
69
70#define HW_PINCTRL_PIN2IRQ0 0x800
71#define HW_PINCTRL_PIN2IRQ1 0x810
72#define HW_PINCTRL_PIN2IRQ2 0x820
73
74#define HW_PINCTRL_IRQEN0 0x900
75#define HW_PINCTRL_IRQEN1 0x910
76#define HW_PINCTRL_IRQEN2 0x920
77
78#define HW_PINCTRL_IRQLEVEL0 0xA00
79#define HW_PINCTRL_IRQLEVEL1 0xA10
80#define HW_PINCTRL_IRQLEVEL2 0xA20
81
82#define HW_PINCTRL_IRQPOL0 0xB00
83#define HW_PINCTRL_IRQPOL1 0xB10
84#define HW_PINCTRL_IRQPOL2 0xB20
85
86#define HW_PINCTRL_IRQSTAT0 0xC00
87#define HW_PINCTRL_IRQSTAT1 0xC10
88#define HW_PINCTRL_IRQSTAT2 0xC20
89
90#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-power.h b/arch/arm/mach-stmp378x/include/mach/regs-power.h
new file mode 100644
index 000000000000..e454c830f076
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-power.h
@@ -0,0 +1,63 @@
1/*
2 * stmp378x: POWER register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_POWER
22#define _MACH_REGS_POWER
23
24#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000)
25#define REGS_POWER_PHYS 0x80044000
26#define REGS_POWER_SIZE 0x2000
27
28#define HW_POWER_CTRL 0x0
29#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001
30#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0
31#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000
32#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000
33#define BM_POWER_CTRL_CLKGATE 0x40000000
34
35#define HW_POWER_5VCTRL 0x10
36#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040
37
38#define HW_POWER_MINPWR 0x20
39
40#define HW_POWER_CHARGE 0x30
41
42#define HW_POWER_VDDDCTRL 0x40
43
44#define HW_POWER_VDDACTRL 0x50
45
46#define HW_POWER_VDDIOCTRL 0x60
47#define BM_POWER_VDDIOCTRL_TRG 0x0000001F
48#define BP_POWER_VDDIOCTRL_TRG 0
49
50#define HW_POWER_STS 0xC0
51#define BM_POWER_STS_VBUSVALID 0x00000002
52#define BM_POWER_STS_BVALID 0x00000004
53#define BM_POWER_STS_AVALID 0x00000008
54#define BM_POWER_STS_DC_OK 0x00000200
55
56#define HW_POWER_RESET 0x100
57
58#define HW_POWER_DEBUG 0x110
59#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002
60#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004
61#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
62
63#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h b/arch/arm/mach-stmp378x/include/mach/regs-pwm.h
new file mode 100644
index 000000000000..0d0f9e56ec77
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-pwm.h
@@ -0,0 +1,53 @@
1/*
2 * stmp378x: PWM register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000)
22#define REGS_PWM_PHYS 0x80064000
23#define REGS_PWM_SIZE 0x2000
24
25#define HW_PWM_CTRL 0x0
26#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
27#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020
28
29#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20)
30#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20)
31#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20)
32#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20)
33
34#define HW_PWM_ACTIVEn 0x10
35#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF
36#define BP_PWM_ACTIVEn_ACTIVE 0
37#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
38#define BP_PWM_ACTIVEn_INACTIVE 16
39
40#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20)
41#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20)
42#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20)
43#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20)
44
45#define HW_PWM_PERIODn 0x20
46#define BM_PWM_PERIODn_PERIOD 0x0000FFFF
47#define BP_PWM_PERIODn_PERIOD 0
48#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000
49#define BP_PWM_PERIODn_ACTIVE_STATE 16
50#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000
51#define BP_PWM_PERIODn_INACTIVE_STATE 18
52#define BM_PWM_PERIODn_CDIV 0x00700000
53#define BP_PWM_PERIODn_CDIV 20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h b/arch/arm/mach-stmp378x/include/mach/regs-pxp.h
new file mode 100644
index 000000000000..54d297896de8
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-pxp.h
@@ -0,0 +1,140 @@
1/*
2 * stmp378x: PXP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_PXP_BASE (STMP3XXX_REGS_BASE + 0x2A000)
22#define REGS_PXP_PHYS 0x8002A000
23#define REGS_PXP_SIZE 0x2000
24
25#define HW_PXP_CTRL 0x0
26#define BM_PXP_CTRL_ENABLE 0x00000001
27#define BP_PXP_CTRL_ENABLE 0
28#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002
29#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT 0x000000F0
30#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT 4
31#define BM_PXP_CTRL_ROTATE 0x00000300
32#define BP_PXP_CTRL_ROTATE 8
33#define BM_PXP_CTRL_HFLIP 0x00000400
34#define BM_PXP_CTRL_VFLIP 0x00000800
35#define BM_PXP_CTRL_S0_FORMAT 0x0000F000
36#define BP_PXP_CTRL_S0_FORMAT 12
37#define BM_PXP_CTRL_SCALE 0x00040000
38#define BM_PXP_CTRL_CROP 0x00080000
39
40#define HW_PXP_STAT 0x10
41#define BM_PXP_STAT_IRQ 0x00000001
42#define BP_PXP_STAT_IRQ 0
43
44#define HW_PXP_RGBBUF 0x20
45
46#define HW_PXP_RGBSIZE 0x40
47#define BM_PXP_RGBSIZE_HEIGHT 0x00000FFF
48#define BP_PXP_RGBSIZE_HEIGHT 0
49#define BM_PXP_RGBSIZE_WIDTH 0x00FFF000
50#define BP_PXP_RGBSIZE_WIDTH 12
51
52#define HW_PXP_S0BUF 0x50
53
54#define HW_PXP_S0UBUF 0x60
55
56#define HW_PXP_S0VBUF 0x70
57
58#define HW_PXP_S0PARAM 0x80
59#define BM_PXP_S0PARAM_HEIGHT 0x000000FF
60#define BP_PXP_S0PARAM_HEIGHT 0
61#define BM_PXP_S0PARAM_WIDTH 0x0000FF00
62#define BP_PXP_S0PARAM_WIDTH 8
63#define BM_PXP_S0PARAM_YBASE 0x00FF0000
64#define BP_PXP_S0PARAM_YBASE 16
65#define BM_PXP_S0PARAM_XBASE 0xFF000000
66#define BP_PXP_S0PARAM_XBASE 24
67
68#define HW_PXP_S0BACKGROUND 0x90
69
70#define HW_PXP_S0CROP 0xA0
71#define BM_PXP_S0CROP_HEIGHT 0x000000FF
72#define BP_PXP_S0CROP_HEIGHT 0
73#define BM_PXP_S0CROP_WIDTH 0x0000FF00
74#define BP_PXP_S0CROP_WIDTH 8
75#define BM_PXP_S0CROP_YBASE 0x00FF0000
76#define BP_PXP_S0CROP_YBASE 16
77#define BM_PXP_S0CROP_XBASE 0xFF000000
78#define BP_PXP_S0CROP_XBASE 24
79
80#define HW_PXP_S0SCALE 0xB0
81#define BM_PXP_S0SCALE_XSCALE 0x00003FFF
82#define BP_PXP_S0SCALE_XSCALE 0
83#define BM_PXP_S0SCALE_YSCALE 0x3FFF0000
84#define BP_PXP_S0SCALE_YSCALE 16
85
86#define HW_PXP_CSCCOEFF0 0xD0
87
88#define HW_PXP_CSCCOEFF1 0xE0
89
90#define HW_PXP_CSCCOEFF2 0xF0
91
92#define HW_PXP_S0COLORKEYLOW 0x180
93
94#define HW_PXP_S0COLORKEYHIGH 0x190
95
96#define HW_PXP_OL0 (0x200 + 0 * 0x40)
97#define HW_PXP_OL1 (0x200 + 1 * 0x40)
98#define HW_PXP_OL2 (0x200 + 2 * 0x40)
99#define HW_PXP_OL3 (0x200 + 3 * 0x40)
100#define HW_PXP_OL4 (0x200 + 4 * 0x40)
101#define HW_PXP_OL5 (0x200 + 5 * 0x40)
102#define HW_PXP_OL6 (0x200 + 6 * 0x40)
103#define HW_PXP_OL7 (0x200 + 7 * 0x40)
104
105#define HW_PXP_OLn 0x200
106
107#define HW_PXP_OL0SIZE (0x210 + 0 * 0x40)
108#define HW_PXP_OL1SIZE (0x210 + 1 * 0x40)
109#define HW_PXP_OL2SIZE (0x210 + 2 * 0x40)
110#define HW_PXP_OL3SIZE (0x210 + 3 * 0x40)
111#define HW_PXP_OL4SIZE (0x210 + 4 * 0x40)
112#define HW_PXP_OL5SIZE (0x210 + 5 * 0x40)
113#define HW_PXP_OL6SIZE (0x210 + 6 * 0x40)
114#define HW_PXP_OL7SIZE (0x210 + 7 * 0x40)
115
116#define HW_PXP_OLnSIZE 0x210
117#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF
118#define BP_PXP_OLnSIZE_HEIGHT 0
119#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00
120#define BP_PXP_OLnSIZE_WIDTH 8
121
122#define HW_PXP_OL0PARAM (0x220 + 0 * 0x40)
123#define HW_PXP_OL1PARAM (0x220 + 1 * 0x40)
124#define HW_PXP_OL2PARAM (0x220 + 2 * 0x40)
125#define HW_PXP_OL3PARAM (0x220 + 3 * 0x40)
126#define HW_PXP_OL4PARAM (0x220 + 4 * 0x40)
127#define HW_PXP_OL5PARAM (0x220 + 5 * 0x40)
128#define HW_PXP_OL6PARAM (0x220 + 6 * 0x40)
129#define HW_PXP_OL7PARAM (0x220 + 7 * 0x40)
130
131#define HW_PXP_OLnPARAM 0x220
132#define BM_PXP_OLnPARAM_ENABLE 0x00000001
133#define BP_PXP_OLnPARAM_ENABLE 0
134#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006
135#define BP_PXP_OLnPARAM_ALPHA_CNTL 1
136#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008
137#define BM_PXP_OLnPARAM_FORMAT 0x000000F0
138#define BP_PXP_OLnPARAM_FORMAT 4
139#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00
140#define BP_PXP_OLnPARAM_ALPHA 8
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h b/arch/arm/mach-stmp378x/include/mach/regs-rtc.h
new file mode 100644
index 000000000000..b8dbd6742d98
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-rtc.h
@@ -0,0 +1,59 @@
1/*
2 * stmp378x: RTC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000)
22#define REGS_RTC_PHYS 0x8005C000
23#define REGS_RTC_SIZE 0x2000
24
25#define HW_RTC_CTRL 0x0
26#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001
27#define BP_RTC_CTRL_ALARM_IRQ_EN 0
28#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
29#define BM_RTC_CTRL_ALARM_IRQ 0x00000004
30#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008
31#define BM_RTC_CTRL_WATCHDOGEN 0x00000010
32
33#define HW_RTC_STAT 0x10
34#define BM_RTC_STAT_NEW_REGS 0x0000FF00
35#define BP_RTC_STAT_NEW_REGS 8
36#define BM_RTC_STAT_STALE_REGS 0x00FF0000
37#define BP_RTC_STAT_STALE_REGS 16
38#define BM_RTC_STAT_RTC_PRESENT 0x80000000
39
40#define HW_RTC_SECONDS 0x30
41
42#define HW_RTC_ALARM 0x40
43
44#define HW_RTC_WATCHDOG 0x50
45
46#define HW_RTC_PERSISTENT0 0x60
47#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002
48#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004
49#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010
50#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020
51#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080
52#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
53#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
54
55#define HW_RTC_PERSISTENT1 0x70
56#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF
57#define BP_RTC_PERSISTENT1_GENERAL 0
58
59#define HW_RTC_VERSION 0xD0
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-saif.h b/arch/arm/mach-stmp378x/include/mach/regs-saif.h
new file mode 100644
index 000000000000..6df41762c2a3
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-saif.h
@@ -0,0 +1,21 @@
1/*
2 * stmp378x: SAIF register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SAIF_SIZE 0x2000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h b/arch/arm/mach-stmp378x/include/mach/regs-spdif.h
new file mode 100644
index 000000000000..801539848c28
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-spdif.h
@@ -0,0 +1,49 @@
1/*
2 * stmp378x: SPDIF register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SPDIF_BASE (STMP3XXX_REGS_BASE + 0x54000)
22#define REGS_SPDIF_PHYS 0x80054000
23#define REGS_SPDIF_SIZE 0x2000
24
25#define HW_SPDIF_CTRL 0x0
26#define BM_SPDIF_CTRL_RUN 0x00000001
27#define BP_SPDIF_CTRL_RUN 0
28#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
29#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
30#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
31#define BM_SPDIF_CTRL_WORD_LENGTH 0x00000010
32#define BM_SPDIF_CTRL_CLKGATE 0x40000000
33#define BM_SPDIF_CTRL_SFTRST 0x80000000
34
35#define HW_SPDIF_STAT 0x10
36
37#define HW_SPDIF_FRAMECTRL 0x20
38
39#define HW_SPDIF_SRR 0x30
40#define BM_SPDIF_SRR_RATE 0x000FFFFF
41#define BP_SPDIF_SRR_RATE 0
42#define BM_SPDIF_SRR_BASEMULT 0x70000000
43#define BP_SPDIF_SRR_BASEMULT 28
44
45#define HW_SPDIF_DEBUG 0x40
46
47#define HW_SPDIF_DATA 0x50
48
49#define HW_SPDIF_VERSION 0x60
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h b/arch/arm/mach-stmp378x/include/mach/regs-ssp.h
new file mode 100644
index 000000000000..28aacf0f58ed
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-ssp.h
@@ -0,0 +1,102 @@
1/*
2 * stmp378x: SSP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SSP1_BASE (STMP3XXX_REGS_BASE + 0x10000)
22#define REGS_SSP1_PHYS 0x80010000
23#define REGS_SSP2_BASE (STMP3XXX_REGS_BASE + 0x34000)
24#define REGS_SSP2_PHYS 0x80034000
25#define REGS_SSP_SIZE 0x2000
26
27#define HW_SSP_CTRL0 0x0
28#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
29#define BP_SSP_CTRL0_XFER_COUNT 0
30#define BM_SSP_CTRL0_ENABLE 0x00010000
31#define BM_SSP_CTRL0_GET_RESP 0x00020000
32#define BM_SSP_CTRL0_LONG_RESP 0x00080000
33#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000
34#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000
35#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000
36#define BP_SSP_CTRL0_BUS_WIDTH 22
37#define BM_SSP_CTRL0_DATA_XFER 0x01000000
38#define BM_SSP_CTRL0_READ 0x02000000
39#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
40#define BM_SSP_CTRL0_LOCK_CS 0x08000000
41#define BM_SSP_CTRL0_RUN 0x20000000
42#define BM_SSP_CTRL0_CLKGATE 0x40000000
43#define BM_SSP_CTRL0_SFTRST 0x80000000
44
45#define HW_SSP_CMD0 0x10
46#define BM_SSP_CMD0_CMD 0x000000FF
47#define BP_SSP_CMD0_CMD 0
48#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
49#define BP_SSP_CMD0_BLOCK_COUNT 8
50#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000
51#define BP_SSP_CMD0_BLOCK_SIZE 16
52#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
53#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF
54#define BP_SSP_CMD1_CMD_ARG 0
55
56#define HW_SSP_TIMING 0x50
57#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF
58#define BP_SSP_TIMING_CLOCK_RATE 0
59#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00
60#define BP_SSP_TIMING_CLOCK_DIVIDE 8
61#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000
62#define BP_SSP_TIMING_TIMEOUT 16
63
64#define HW_SSP_CTRL1 0x60
65#define BM_SSP_CTRL1_SSP_MODE 0x0000000F
66#define BP_SSP_CTRL1_SSP_MODE 0
67#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0
68#define BP_SSP_CTRL1_WORD_LENGTH 4
69#define BM_SSP_CTRL1_POLARITY 0x00000200
70#define BM_SSP_CTRL1_PHASE 0x00000400
71#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
72#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000
73#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000
74#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000
75#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000
76#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000
77#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000
78#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000
79#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000
80#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000
81#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000
82#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
83#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
84#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
85
86#define HW_SSP_DATA 0x70
87
88#define HW_SSP_SDRESP0 0x80
89
90#define HW_SSP_SDRESP1 0x90
91
92#define HW_SSP_SDRESP2 0xA0
93
94#define HW_SSP_SDRESP3 0xB0
95
96#define HW_SSP_STATUS 0xC0
97#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020
98#define BM_SSP_STATUS_TIMEOUT 0x00001000
99#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000
100#define BM_SSP_STATUS_RESP_ERR 0x00008000
101#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000
102#define BM_SSP_STATUS_CARD_DETECT 0x10000000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h b/arch/arm/mach-stmp378x/include/mach/regs-sydma.h
new file mode 100644
index 000000000000..08343a8b5566
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-sydma.h
@@ -0,0 +1,23 @@
1/*
2 * stmp378x: SYDMA register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SYDMA_BASE (STMP3XXX_REGS_BASE + 0x26000)
22#define REGS_SYDMA_PHYS 0x80026000
23#define REGS_SYDMA_SIZE 0x2000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h b/arch/arm/mach-stmp378x/include/mach/regs-timrot.h
new file mode 100644
index 000000000000..b5527957c67f
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-timrot.h
@@ -0,0 +1,68 @@
1/*
2 * stmp378x: TIMROT register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_TIMROT
22#define _MACH_REGS_TIMROT
23
24#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000)
25#define REGS_TIMROT_PHYS 0x80068000
26#define REGS_TIMROT_SIZE 0x2000
27
28#define HW_TIMROT_ROTCTRL 0x0
29#define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007
30#define BP_TIMROT_ROTCTRL_SELECT_A 0
31#define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070
32#define BP_TIMROT_ROTCTRL_SELECT_B 4
33#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100
34#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200
35#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00
36#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10
37#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000
38#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000
39#define BP_TIMROT_ROTCTRL_DIVIDER 16
40#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000
41#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
42#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
43
44#define HW_TIMROT_ROTCOUNT 0x10
45#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF
46#define BP_TIMROT_ROTCOUNT_UPDOWN 0
47
48#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20)
49#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20)
50#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20)
51
52#define HW_TIMROT_TIMCTRLn 0x20
53#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
54#define BP_TIMROT_TIMCTRLn_SELECT 0
55#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
56#define BP_TIMROT_TIMCTRLn_PRESCALE 4
57#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
58#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
59#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
60#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
61
62#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20)
63#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20)
64#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20)
65
66#define HW_TIMROT_TIMCOUNTn 0x30
67
68#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h b/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h
new file mode 100644
index 000000000000..7f895cb34350
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h
@@ -0,0 +1,67 @@
1/*
2 * stmp378x: TVENC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_TVENC_BASE (STMP3XXX_REGS_BASE + 0x38000)
22#define REGS_TVENC_PHYS 0x80038000
23#define REGS_TVENC_SIZE 0x2000
24
25#define HW_TVENC_CTRL 0x0
26#define BM_TVENC_CTRL_CLKGATE 0x40000000
27#define BM_TVENC_CTRL_SFTRST 0x80000000
28
29#define HW_TVENC_CONFIG 0x10
30#define BM_TVENC_CONFIG_ENCD_MODE 0x00000007
31#define BP_TVENC_CONFIG_ENCD_MODE 0
32#define BM_TVENC_CONFIG_SYNC_MODE 0x00000070
33#define BP_TVENC_CONFIG_SYNC_MODE 4
34#define BM_TVENC_CONFIG_FSYNC_PHS 0x00000200
35#define BM_TVENC_CONFIG_CGAIN 0x0000C000
36#define BP_TVENC_CONFIG_CGAIN 14
37#define BM_TVENC_CONFIG_YGAIN_SEL 0x00030000
38#define BP_TVENC_CONFIG_YGAIN_SEL 16
39#define BM_TVENC_CONFIG_PAL_SHAPE 0x00100000
40
41#define HW_TVENC_SYNCOFFSET 0x30
42
43#define HW_TVENC_COLORSUB0 0xC0
44
45#define HW_TVENC_COLORBURST 0x140
46#define BM_TVENC_COLORBURST_PBA 0x00FF0000
47#define BP_TVENC_COLORBURST_PBA 16
48#define BM_TVENC_COLORBURST_NBA 0xFF000000
49#define BP_TVENC_COLORBURST_NBA 24
50
51#define HW_TVENC_MACROVISION0 0x150
52
53#define HW_TVENC_MACROVISION1 0x160
54
55#define HW_TVENC_MACROVISION2 0x170
56
57#define HW_TVENC_MACROVISION3 0x180
58
59#define HW_TVENC_MACROVISION4 0x190
60
61#define HW_TVENC_DACCTRL 0x1A0
62#define BM_TVENC_DACCTRL_RVAL 0x00000070
63#define BP_TVENC_DACCTRL_RVAL 4
64#define BM_TVENC_DACCTRL_DUMP_TOVDD1 0x00000100
65#define BM_TVENC_DACCTRL_PWRUP1 0x00001000
66#define BM_TVENC_DACCTRL_GAINUP 0x00040000
67#define BM_TVENC_DACCTRL_GAINDN 0x00080000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h b/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h
new file mode 100644
index 000000000000..a251e68bb3a1
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h
@@ -0,0 +1,87 @@
1/*
2 * stmp378x: UARTAPP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_UARTAPP1_BASE (STMP3XXX_REGS_BASE + 0x6C000)
22#define REGS_UARTAPP1_PHYS 0x8006C000
23#define REGS_UARTAPP2_BASE (STMP3XXX_REGS_BASE + 0x6E000)
24#define REGS_UARTAPP2_PHYS 0x8006E000
25#define REGS_UARTAPP_SIZE 0x2000
26
27#define HW_UARTAPP_CTRL0 0x0
28#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF
29#define BP_UARTAPP_CTRL0_XFER_COUNT 0
30#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000
31#define BP_UARTAPP_CTRL0_RXTIMEOUT 16
32#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000
33#define BM_UARTAPP_CTRL0_RUN 0x20000000
34#define BM_UARTAPP_CTRL0_SFTRST 0x80000000
35#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF
36#define BP_UARTAPP_CTRL1_XFER_COUNT 0
37#define BM_UARTAPP_CTRL1_RUN 0x10000000
38
39#define HW_UARTAPP_CTRL2 0x20
40#define BM_UARTAPP_CTRL2_UARTEN 0x00000001
41#define BP_UARTAPP_CTRL2_UARTEN 0
42#define BM_UARTAPP_CTRL2_TXE 0x00000100
43#define BM_UARTAPP_CTRL2_RXE 0x00000200
44#define BM_UARTAPP_CTRL2_RTS 0x00000800
45#define BM_UARTAPP_CTRL2_RTSEN 0x00004000
46#define BM_UARTAPP_CTRL2_CTSEN 0x00008000
47#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000
48#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000
49#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000
50
51#define HW_UARTAPP_LINECTRL 0x30
52#define BM_UARTAPP_LINECTRL_BRK 0x00000001
53#define BP_UARTAPP_LINECTRL_BRK 0
54#define BM_UARTAPP_LINECTRL_PEN 0x00000002
55#define BM_UARTAPP_LINECTRL_EPS 0x00000004
56#define BM_UARTAPP_LINECTRL_STP2 0x00000008
57#define BM_UARTAPP_LINECTRL_FEN 0x00000010
58#define BM_UARTAPP_LINECTRL_WLEN 0x00000060
59#define BP_UARTAPP_LINECTRL_WLEN 5
60#define BM_UARTAPP_LINECTRL_SPS 0x00000080
61#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00
62#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8
63#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000
64#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16
65
66#define HW_UARTAPP_INTR 0x50
67#define BM_UARTAPP_INTR_CTSMIS 0x00000002
68#define BM_UARTAPP_INTR_RTIS 0x00000040
69#define BM_UARTAPP_INTR_CTSMIEN 0x00020000
70#define BM_UARTAPP_INTR_RXIEN 0x00100000
71#define BM_UARTAPP_INTR_RTIEN 0x00400000
72
73#define HW_UARTAPP_DATA 0x60
74
75#define HW_UARTAPP_STAT 0x70
76#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF
77#define BP_UARTAPP_STAT_RXCOUNT 0
78#define BM_UARTAPP_STAT_FERR 0x00010000
79#define BM_UARTAPP_STAT_PERR 0x00020000
80#define BM_UARTAPP_STAT_BERR 0x00040000
81#define BM_UARTAPP_STAT_OERR 0x00080000
82#define BM_UARTAPP_STAT_RXFE 0x01000000
83#define BM_UARTAPP_STAT_TXFF 0x02000000
84#define BM_UARTAPP_STAT_TXFE 0x08000000
85#define BM_UARTAPP_STAT_CTS 0x10000000
86
87#define HW_UARTAPP_VERSION 0x90
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h
new file mode 100644
index 000000000000..b810deb552a9
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h
@@ -0,0 +1,268 @@
1/*
2 * stmp378x: UARTDBG register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000)
22#define REGS_UARTDBG_PHYS 0x80070000
23#define REGS_UARTDBG_SIZE 0x2000
24
25#define HW_UARTDBGDR 0x00000000
26#define BP_UARTDBGDR_UNAVAILABLE 16
27#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
28#define BF_UARTDBGDR_UNAVAILABLE(v) \
29 (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
30#define BP_UARTDBGDR_RESERVED 12
31#define BM_UARTDBGDR_RESERVED 0x0000F000
32#define BF_UARTDBGDR_RESERVED(v) \
33 (((v) << 12) & BM_UARTDBGDR_RESERVED)
34#define BM_UARTDBGDR_OE 0x00000800
35#define BM_UARTDBGDR_BE 0x00000400
36#define BM_UARTDBGDR_PE 0x00000200
37#define BM_UARTDBGDR_FE 0x00000100
38#define BP_UARTDBGDR_DATA 0
39#define BM_UARTDBGDR_DATA 0x000000FF
40#define BF_UARTDBGDR_DATA(v) \
41 (((v) << 0) & BM_UARTDBGDR_DATA)
42#define HW_UARTDBGRSR_ECR 0x00000004
43#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
44#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
45#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
46 (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
47#define BP_UARTDBGRSR_ECR_EC 4
48#define BM_UARTDBGRSR_ECR_EC 0x000000F0
49#define BF_UARTDBGRSR_ECR_EC(v) \
50 (((v) << 4) & BM_UARTDBGRSR_ECR_EC)
51#define BM_UARTDBGRSR_ECR_OE 0x00000008
52#define BM_UARTDBGRSR_ECR_BE 0x00000004
53#define BM_UARTDBGRSR_ECR_PE 0x00000002
54#define BM_UARTDBGRSR_ECR_FE 0x00000001
55#define HW_UARTDBGFR 0x00000018
56#define BP_UARTDBGFR_UNAVAILABLE 16
57#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
58#define BF_UARTDBGFR_UNAVAILABLE(v) \
59 (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
60#define BP_UARTDBGFR_RESERVED 9
61#define BM_UARTDBGFR_RESERVED 0x0000FE00
62#define BF_UARTDBGFR_RESERVED(v) \
63 (((v) << 9) & BM_UARTDBGFR_RESERVED)
64#define BM_UARTDBGFR_RI 0x00000100
65#define BM_UARTDBGFR_TXFE 0x00000080
66#define BM_UARTDBGFR_RXFF 0x00000040
67#define BM_UARTDBGFR_TXFF 0x00000020
68#define BM_UARTDBGFR_RXFE 0x00000010
69#define BM_UARTDBGFR_BUSY 0x00000008
70#define BM_UARTDBGFR_DCD 0x00000004
71#define BM_UARTDBGFR_DSR 0x00000002
72#define BM_UARTDBGFR_CTS 0x00000001
73#define HW_UARTDBGILPR 0x00000020
74#define BP_UARTDBGILPR_UNAVAILABLE 8
75#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
76#define BF_UARTDBGILPR_UNAVAILABLE(v) \
77 (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
78#define BP_UARTDBGILPR_ILPDVSR 0
79#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
80#define BF_UARTDBGILPR_ILPDVSR(v) \
81 (((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
82#define HW_UARTDBGIBRD 0x00000024
83#define BP_UARTDBGIBRD_UNAVAILABLE 16
84#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
85#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
86 (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
87#define BP_UARTDBGIBRD_BAUD_DIVINT 0
88#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
89#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
90 (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
91#define HW_UARTDBGFBRD 0x00000028
92#define BP_UARTDBGFBRD_UNAVAILABLE 8
93#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
94#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
95 (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
96#define BP_UARTDBGFBRD_RESERVED 6
97#define BM_UARTDBGFBRD_RESERVED 0x000000C0
98#define BF_UARTDBGFBRD_RESERVED(v) \
99 (((v) << 6) & BM_UARTDBGFBRD_RESERVED)
100#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
101#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
102#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
103 (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
104#define HW_UARTDBGLCR_H 0x0000002c
105#define BP_UARTDBGLCR_H_UNAVAILABLE 16
106#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
107#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
108 (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
109#define BP_UARTDBGLCR_H_RESERVED 8
110#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
111#define BF_UARTDBGLCR_H_RESERVED(v) \
112 (((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
113#define BM_UARTDBGLCR_H_SPS 0x00000080
114#define BP_UARTDBGLCR_H_WLEN 5
115#define BM_UARTDBGLCR_H_WLEN 0x00000060
116#define BF_UARTDBGLCR_H_WLEN(v) \
117 (((v) << 5) & BM_UARTDBGLCR_H_WLEN)
118#define BM_UARTDBGLCR_H_FEN 0x00000010
119#define BM_UARTDBGLCR_H_STP2 0x00000008
120#define BM_UARTDBGLCR_H_EPS 0x00000004
121#define BM_UARTDBGLCR_H_PEN 0x00000002
122#define BM_UARTDBGLCR_H_BRK 0x00000001
123#define HW_UARTDBGCR 0x00000030
124#define BP_UARTDBGCR_UNAVAILABLE 16
125#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
126#define BF_UARTDBGCR_UNAVAILABLE(v) \
127 (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
128#define BM_UARTDBGCR_CTSEN 0x00008000
129#define BM_UARTDBGCR_RTSEN 0x00004000
130#define BM_UARTDBGCR_OUT2 0x00002000
131#define BM_UARTDBGCR_OUT1 0x00001000
132#define BM_UARTDBGCR_RTS 0x00000800
133#define BM_UARTDBGCR_DTR 0x00000400
134#define BM_UARTDBGCR_RXE 0x00000200
135#define BM_UARTDBGCR_TXE 0x00000100
136#define BM_UARTDBGCR_LBE 0x00000080
137#define BP_UARTDBGCR_RESERVED 3
138#define BM_UARTDBGCR_RESERVED 0x00000078
139#define BF_UARTDBGCR_RESERVED(v) \
140 (((v) << 3) & BM_UARTDBGCR_RESERVED)
141#define BM_UARTDBGCR_SIRLP 0x00000004
142#define BM_UARTDBGCR_SIREN 0x00000002
143#define BM_UARTDBGCR_UARTEN 0x00000001
144#define HW_UARTDBGIFLS 0x00000034
145#define BP_UARTDBGIFLS_UNAVAILABLE 16
146#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
147#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
148 (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
149#define BP_UARTDBGIFLS_RESERVED 6
150#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
151#define BF_UARTDBGIFLS_RESERVED(v) \
152 (((v) << 6) & BM_UARTDBGIFLS_RESERVED)
153#define BP_UARTDBGIFLS_RXIFLSEL 3
154#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
155#define BF_UARTDBGIFLS_RXIFLSEL(v) \
156 (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
157#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0
158#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
159#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
160#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
161#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
162#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
163#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
164#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
165#define BP_UARTDBGIFLS_TXIFLSEL 0
166#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
167#define BF_UARTDBGIFLS_TXIFLSEL(v) \
168 (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
169#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0
170#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
171#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
172#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
173#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
174#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
175#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
176#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
177#define HW_UARTDBGIMSC 0x00000038
178#define BP_UARTDBGIMSC_UNAVAILABLE 16
179#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
180#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
181 (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
182#define BP_UARTDBGIMSC_RESERVED 11
183#define BM_UARTDBGIMSC_RESERVED 0x0000F800
184#define BF_UARTDBGIMSC_RESERVED(v) \
185 (((v) << 11) & BM_UARTDBGIMSC_RESERVED)
186#define BM_UARTDBGIMSC_OEIM 0x00000400
187#define BM_UARTDBGIMSC_BEIM 0x00000200
188#define BM_UARTDBGIMSC_PEIM 0x00000100
189#define BM_UARTDBGIMSC_FEIM 0x00000080
190#define BM_UARTDBGIMSC_RTIM 0x00000040
191#define BM_UARTDBGIMSC_TXIM 0x00000020
192#define BM_UARTDBGIMSC_RXIM 0x00000010
193#define BM_UARTDBGIMSC_DSRMIM 0x00000008
194#define BM_UARTDBGIMSC_DCDMIM 0x00000004
195#define BM_UARTDBGIMSC_CTSMIM 0x00000002
196#define BM_UARTDBGIMSC_RIMIM 0x00000001
197#define HW_UARTDBGRIS 0x0000003c
198#define BP_UARTDBGRIS_UNAVAILABLE 16
199#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
200#define BF_UARTDBGRIS_UNAVAILABLE(v) \
201 (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
202#define BP_UARTDBGRIS_RESERVED 11
203#define BM_UARTDBGRIS_RESERVED 0x0000F800
204#define BF_UARTDBGRIS_RESERVED(v) \
205 (((v) << 11) & BM_UARTDBGRIS_RESERVED)
206#define BM_UARTDBGRIS_OERIS 0x00000400
207#define BM_UARTDBGRIS_BERIS 0x00000200
208#define BM_UARTDBGRIS_PERIS 0x00000100
209#define BM_UARTDBGRIS_FERIS 0x00000080
210#define BM_UARTDBGRIS_RTRIS 0x00000040
211#define BM_UARTDBGRIS_TXRIS 0x00000020
212#define BM_UARTDBGRIS_RXRIS 0x00000010
213#define BM_UARTDBGRIS_DSRRMIS 0x00000008
214#define BM_UARTDBGRIS_DCDRMIS 0x00000004
215#define BM_UARTDBGRIS_CTSRMIS 0x00000002
216#define BM_UARTDBGRIS_RIRMIS 0x00000001
217#define HW_UARTDBGMIS 0x00000040
218#define BP_UARTDBGMIS_UNAVAILABLE 16
219#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
220#define BF_UARTDBGMIS_UNAVAILABLE(v) \
221 (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
222#define BP_UARTDBGMIS_RESERVED 11
223#define BM_UARTDBGMIS_RESERVED 0x0000F800
224#define BF_UARTDBGMIS_RESERVED(v) \
225 (((v) << 11) & BM_UARTDBGMIS_RESERVED)
226#define BM_UARTDBGMIS_OEMIS 0x00000400
227#define BM_UARTDBGMIS_BEMIS 0x00000200
228#define BM_UARTDBGMIS_PEMIS 0x00000100
229#define BM_UARTDBGMIS_FEMIS 0x00000080
230#define BM_UARTDBGMIS_RTMIS 0x00000040
231#define BM_UARTDBGMIS_TXMIS 0x00000020
232#define BM_UARTDBGMIS_RXMIS 0x00000010
233#define BM_UARTDBGMIS_DSRMMIS 0x00000008
234#define BM_UARTDBGMIS_DCDMMIS 0x00000004
235#define BM_UARTDBGMIS_CTSMMIS 0x00000002
236#define BM_UARTDBGMIS_RIMMIS 0x00000001
237#define HW_UARTDBGICR 0x00000044
238#define BP_UARTDBGICR_UNAVAILABLE 16
239#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
240#define BF_UARTDBGICR_UNAVAILABLE(v) \
241 (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
242#define BP_UARTDBGICR_RESERVED 11
243#define BM_UARTDBGICR_RESERVED 0x0000F800
244#define BF_UARTDBGICR_RESERVED(v) \
245 (((v) << 11) & BM_UARTDBGICR_RESERVED)
246#define BM_UARTDBGICR_OEIC 0x00000400
247#define BM_UARTDBGICR_BEIC 0x00000200
248#define BM_UARTDBGICR_PEIC 0x00000100
249#define BM_UARTDBGICR_FEIC 0x00000080
250#define BM_UARTDBGICR_RTIC 0x00000040
251#define BM_UARTDBGICR_TXIC 0x00000020
252#define BM_UARTDBGICR_RXIC 0x00000010
253#define BM_UARTDBGICR_DSRMIC 0x00000008
254#define BM_UARTDBGICR_DCDMIC 0x00000004
255#define BM_UARTDBGICR_CTSMIC 0x00000002
256#define BM_UARTDBGICR_RIMIC 0x00000001
257#define HW_UARTDBGDMACR 0x00000048
258#define BP_UARTDBGDMACR_UNAVAILABLE 16
259#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
260#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
261 (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
262#define BP_UARTDBGDMACR_RESERVED 3
263#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
264#define BF_UARTDBGDMACR_RESERVED(v) \
265 (((v) << 3) & BM_UARTDBGDMACR_RESERVED)
266#define BM_UARTDBGDMACR_DMAONERR 0x00000004
267#define BM_UARTDBGDMACR_TXDMAE 0x00000002
268#define BM_UARTDBGDMACR_RXDMAE 0x00000001
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h
new file mode 100644
index 000000000000..25112c1aa608
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h
@@ -0,0 +1,40 @@
1/*
2 * stmp378x: USBCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000)
22#define REGS_USBCTRL_PHYS 0x80080000
23#define REGS_USBCTRL_SIZE 0x2000
24
25#define HW_USBCTRL_USBCMD 0x140
26#define BM_USBCTRL_USBCMD_RS 0x00000001
27#define BP_USBCTRL_USBCMD_RS 0
28#define BM_USBCTRL_USBCMD_RST 0x00000002
29
30#define HW_USBCTRL_USBINTR 0x148
31#define BM_USBCTRL_USBINTR_UE 0x00000001
32#define BP_USBCTRL_USBINTR_UE 0
33
34#define HW_USBCTRL_PORTSC1 0x184
35#define BM_USBCTRL_PORTSC1_PHCD 0x00800000
36
37#define HW_USBCTRL_OTGSC 0x1A4
38#define BM_USBCTRL_OTGSC_ID 0x00000100
39#define BM_USBCTRL_OTGSC_IDIS 0x00010000
40#define BM_USBCTRL_OTGSC_IDIE 0x01000000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h b/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h
new file mode 100644
index 000000000000..11f3b732dc92
--- /dev/null
+++ b/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h
@@ -0,0 +1,37 @@
1/*
2 * stmp378x: USBPHY register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000)
22#define REGS_USBPHY_PHYS 0x8007C000
23#define REGS_USBPHY_SIZE 0x2000
24
25#define HW_USBPHY_PWD 0x0
26
27#define HW_USBPHY_CTRL 0x30
28#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002
29#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010
30#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080
31#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800
32#define BM_USBPHY_CTRL_CLKGATE 0x40000000
33#define BM_USBPHY_CTRL_SFTRST 0x80000000
34
35#define HW_USBPHY_STATUS 0x40
36#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040
37#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100
diff --git a/arch/arm/mach-stmp378x/stmp378x.c b/arch/arm/mach-stmp378x/stmp378x.c
new file mode 100644
index 000000000000..ddd49a760fd4
--- /dev/null
+++ b/arch/arm/mach-stmp378x/stmp378x.c
@@ -0,0 +1,299 @@
1/*
2 * Freescale STMP378X platform support
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/platform_device.h>
21#include <linux/irq.h>
22#include <linux/dma-mapping.h>
23
24#include <asm/dma.h>
25#include <asm/setup.h>
26#include <asm/mach-types.h>
27
28#include <asm/mach/arch.h>
29#include <asm/mach/irq.h>
30#include <asm/mach/map.h>
31#include <asm/mach/time.h>
32
33#include <mach/pins.h>
34#include <mach/pinmux.h>
35#include <mach/dma.h>
36#include <mach/hardware.h>
37#include <mach/system.h>
38#include <mach/platform.h>
39#include <mach/stmp3xxx.h>
40#include <mach/regs-icoll.h>
41#include <mach/regs-apbh.h>
42#include <mach/regs-apbx.h>
43#include <mach/regs-pxp.h>
44#include <mach/regs-i2c.h>
45
46#include "stmp378x.h"
47/*
48 * IRQ handling
49 */
50static void stmp378x_ack_irq(unsigned int irq)
51{
52 /* Tell ICOLL to release IRQ line */
53 __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
54
55 /* ACK current interrupt */
56 __raw_writel(0x01 /* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 */,
57 REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
58
59 /* Barrier */
60 (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
61}
62
63static void stmp378x_mask_irq(unsigned int irq)
64{
65 /* IRQ disable */
66 stmp3xxx_clearl(BM_ICOLL_INTERRUPTn_ENABLE,
67 REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10);
68}
69
70static void stmp378x_unmask_irq(unsigned int irq)
71{
72 /* IRQ enable */
73 stmp3xxx_setl(BM_ICOLL_INTERRUPTn_ENABLE,
74 REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + irq * 0x10);
75}
76
77static struct irq_chip stmp378x_chip = {
78 .ack = stmp378x_ack_irq,
79 .mask = stmp378x_mask_irq,
80 .unmask = stmp378x_unmask_irq,
81};
82
83void __init stmp378x_init_irq(void)
84{
85 stmp3xxx_init_irq(&stmp378x_chip);
86}
87
88/*
89 * DMA interrupt handling
90 */
91void stmp3xxx_arch_dma_enable_interrupt(int channel)
92{
93 void __iomem *c1, *c2;
94
95 switch (STMP3XXX_DMA_BUS(channel)) {
96 case STMP3XXX_BUS_APBH:
97 c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
98 c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
99 break;
100
101 case STMP3XXX_BUS_APBX:
102 c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
103 c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
104 break;
105
106 default:
107 return;
108 }
109 stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c1);
110 stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c2);
111}
112EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
113
114void stmp3xxx_arch_dma_clear_interrupt(int channel)
115{
116 void __iomem *c1, *c2;
117
118 switch (STMP3XXX_DMA_BUS(channel)) {
119 case STMP3XXX_BUS_APBH:
120 c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
121 c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
122 break;
123
124 case STMP3XXX_BUS_APBX:
125 c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
126 c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
127 break;
128
129 default:
130 return;
131 }
132 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c1);
133 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c2);
134}
135EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
136
137int stmp3xxx_arch_dma_is_interrupt(int channel)
138{
139 int r = 0;
140
141 switch (STMP3XXX_DMA_BUS(channel)) {
142 case STMP3XXX_BUS_APBH:
143 r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
144 (1 << STMP3XXX_DMA_CHANNEL(channel));
145 break;
146
147 case STMP3XXX_BUS_APBX:
148 r = __raw_readl(REGS_APBX_BASE + HW_APBX_CTRL1) &
149 (1 << STMP3XXX_DMA_CHANNEL(channel));
150 break;
151 }
152 return r;
153}
154EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
155
156void stmp3xxx_arch_dma_reset_channel(int channel)
157{
158 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
159 void __iomem *c0;
160 u32 mask;
161
162 switch (STMP3XXX_DMA_BUS(channel)) {
163 case STMP3XXX_BUS_APBH:
164 c0 = REGS_APBH_BASE + HW_APBH_CTRL0;
165 mask = chbit << BP_APBH_CTRL0_RESET_CHANNEL;
166 break;
167 case STMP3XXX_BUS_APBX:
168 c0 = REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL;
169 mask = chbit << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL;
170 break;
171 default:
172 return;
173 }
174
175 /* Reset channel and wait for it to complete */
176 stmp3xxx_setl(mask, c0);
177 while (__raw_readl(c0) & mask)
178 cpu_relax();
179}
180EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
181
182void stmp3xxx_arch_dma_freeze(int channel)
183{
184 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
185 u32 mask = 1 << chbit;
186
187 switch (STMP3XXX_DMA_BUS(channel)) {
188 case STMP3XXX_BUS_APBH:
189 stmp3xxx_setl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
190 break;
191 case STMP3XXX_BUS_APBX:
192 stmp3xxx_setl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
193 break;
194 }
195}
196EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
197
198void stmp3xxx_arch_dma_unfreeze(int channel)
199{
200 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
201 u32 mask = 1 << chbit;
202
203 switch (STMP3XXX_DMA_BUS(channel)) {
204 case STMP3XXX_BUS_APBH:
205 stmp3xxx_clearl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
206 break;
207 case STMP3XXX_BUS_APBX:
208 stmp3xxx_clearl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
209 break;
210 }
211}
212EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
213
214/*
215 * The registers are all very closely mapped, so we might as well map them all
216 * with a single mapping
217 *
218 * Logical Physical
219 * f0000000 80000000 On-chip registers
220 * f1000000 00000000 32k on-chip SRAM
221 */
222
223static struct map_desc stmp378x_io_desc[] __initdata = {
224 {
225 .virtual = (u32)STMP3XXX_REGS_BASE,
226 .pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE),
227 .length = STMP3XXX_REGS_SIZE,
228 .type = MT_DEVICE,
229 },
230 {
231 .virtual = (u32)STMP3XXX_OCRAM_BASE,
232 .pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE),
233 .length = STMP3XXX_OCRAM_SIZE,
234 .type = MT_DEVICE,
235 },
236};
237
238
239static u64 common_dmamask = DMA_BIT_MASK(32);
240
241/*
242 * devices that are present only on stmp378x, not on all 3xxx boards:
243 * PxP
244 * I2C
245 */
246static struct resource pxp_resource[] = {
247 {
248 .flags = IORESOURCE_MEM,
249 .start = REGS_PXP_PHYS,
250 .end = REGS_PXP_PHYS + REGS_PXP_SIZE,
251 }, {
252 .flags = IORESOURCE_IRQ,
253 .start = IRQ_PXP,
254 .end = IRQ_PXP,
255 },
256};
257
258struct platform_device stmp378x_pxp = {
259 .name = "stmp3xxx-pxp",
260 .id = -1,
261 .dev = {
262 .dma_mask = &common_dmamask,
263 .coherent_dma_mask = DMA_BIT_MASK(32),
264 },
265 .num_resources = ARRAY_SIZE(pxp_resource),
266 .resource = pxp_resource,
267};
268
269static struct resource i2c_resources[] = {
270 {
271 .flags = IORESOURCE_IRQ,
272 .start = IRQ_I2C_ERROR,
273 .end = IRQ_I2C_ERROR,
274 }, {
275 .flags = IORESOURCE_MEM,
276 .start = REGS_I2C_PHYS,
277 .end = REGS_I2C_PHYS + REGS_I2C_SIZE,
278 }, {
279 .flags = IORESOURCE_DMA,
280 .start = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX),
281 .end = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX),
282 },
283};
284
285struct platform_device stmp378x_i2c = {
286 .name = "i2c_stmp3xxx",
287 .id = 0,
288 .dev = {
289 .dma_mask = &common_dmamask,
290 .coherent_dma_mask = DMA_BIT_MASK(32),
291 },
292 .resource = i2c_resources,
293 .num_resources = ARRAY_SIZE(i2c_resources),
294};
295
296void __init stmp378x_map_io(void)
297{
298 iotable_init(stmp378x_io_desc, ARRAY_SIZE(stmp378x_io_desc));
299}
diff --git a/arch/arm/mach-stmp378x/stmp378x.h b/arch/arm/mach-stmp378x/stmp378x.h
new file mode 100644
index 000000000000..0dc15b3c891f
--- /dev/null
+++ b/arch/arm/mach-stmp378x/stmp378x.h
@@ -0,0 +1,25 @@
1/*
2 * Freescale STMP37XX/STMP378X internal functions and data declarations
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __MACH_STMP378X_H
19#define __MACH_STMP378X_H
20
21void stmp378x_map_io(void);
22void stmp378x_init_irq(void);
23
24extern struct platform_device stmp378x_pxp, stmp378x_i2c;
25#endif /* __MACH_STMP378X_COMMON_H */
diff --git a/arch/arm/mach-stmp378x/stmp378x_devb.c b/arch/arm/mach-stmp378x/stmp378x_devb.c
new file mode 100644
index 000000000000..90d8fe6f10fe
--- /dev/null
+++ b/arch/arm/mach-stmp378x/stmp378x_devb.c
@@ -0,0 +1,334 @@
1/*
2 * Freescale STMP378X development board support
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/platform_device.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/err.h>
25#include <linux/spi/spi.h>
26
27#include <asm/setup.h>
28#include <asm/mach-types.h>
29#include <asm/mach/arch.h>
30
31#include <mach/pins.h>
32#include <mach/pinmux.h>
33#include <mach/platform.h>
34#include <mach/stmp3xxx.h>
35#include <mach/mmc.h>
36#include <mach/gpmi.h>
37
38#include "stmp378x.h"
39
40static struct platform_device *devices[] = {
41 &stmp3xxx_dbguart,
42 &stmp3xxx_appuart,
43 &stmp3xxx_watchdog,
44 &stmp3xxx_touchscreen,
45 &stmp3xxx_rtc,
46 &stmp3xxx_keyboard,
47 &stmp3xxx_framebuffer,
48 &stmp3xxx_backlight,
49 &stmp3xxx_rotdec,
50 &stmp3xxx_persistent,
51 &stmp3xxx_dcp_bootstream,
52 &stmp3xxx_dcp,
53 &stmp3xxx_battery,
54 &stmp378x_pxp,
55 &stmp378x_i2c,
56};
57
58static struct pin_desc i2c_pins_desc[] = {
59 { PINID_I2C_SCL, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
60 { PINID_I2C_SDA, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
61};
62
63static struct pin_group i2c_pins = {
64 .pins = i2c_pins_desc,
65 .nr_pins = ARRAY_SIZE(i2c_pins_desc),
66};
67
68static struct pin_desc dbguart_pins_0[] = {
69 { PINID_PWM0, PIN_FUN3, },
70 { PINID_PWM1, PIN_FUN3, },
71};
72
73static struct pin_group dbguart_pins[] = {
74 [0] = {
75 .pins = dbguart_pins_0,
76 .nr_pins = ARRAY_SIZE(dbguart_pins_0),
77 },
78};
79
80static int dbguart_pins_control(int id, int request)
81{
82 int r = 0;
83
84 if (request)
85 r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart");
86 else
87 stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart");
88 return r;
89}
90
91static struct pin_desc appuart_pins_0[] = {
92 { PINID_AUART1_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
93 { PINID_AUART1_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
94 { PINID_AUART1_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
95 { PINID_AUART1_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
96};
97
98static struct pin_desc appuart_pins_1[] = {
99#if 0 /* enable these when second appuart will be connected */
100 { PINID_AUART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
101 { PINID_AUART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
102 { PINID_AUART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
103 { PINID_AUART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
104#endif
105};
106
107static struct pin_desc mmc_pins_desc[] = {
108 { PINID_SSP1_DATA0, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
109 { PINID_SSP1_DATA1, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
110 { PINID_SSP1_DATA2, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
111 { PINID_SSP1_DATA3, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
112 { PINID_SSP1_CMD, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
113 { PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 },
114 { PINID_SSP1_DETECT, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 },
115};
116
117static struct pin_group mmc_pins = {
118 .pins = mmc_pins_desc,
119 .nr_pins = ARRAY_SIZE(mmc_pins_desc),
120};
121
122static int stmp3xxxmmc_get_wp(void)
123{
124 return gpio_get_value(PINID_PWM4);
125}
126
127static int stmp3xxxmmc_hw_init_ssp1(void)
128{
129 int ret;
130
131 ret = stmp3xxx_request_pin_group(&mmc_pins, "mmc");
132 if (ret)
133 goto out;
134
135 /* Configure write protect GPIO pin */
136 ret = gpio_request(PINID_PWM4, "mmc wp");
137 if (ret)
138 goto out_wp;
139
140 gpio_direction_input(PINID_PWM4);
141
142 /* Configure POWER pin as gpio to drive power to MMC slot */
143 ret = gpio_request(PINID_PWM3, "mmc power");
144 if (ret)
145 goto out_power;
146
147 gpio_direction_output(PINID_PWM3, 0);
148 mdelay(100);
149
150 return 0;
151
152out_power:
153 gpio_free(PINID_PWM4);
154out_wp:
155 stmp3xxx_release_pin_group(&mmc_pins, "mmc");
156out:
157 return ret;
158}
159
160static void stmp3xxxmmc_hw_release_ssp1(void)
161{
162 gpio_free(PINID_PWM3);
163 gpio_free(PINID_PWM4);
164 stmp3xxx_release_pin_group(&mmc_pins, "mmc");
165}
166
167static void stmp3xxxmmc_cmd_pullup_ssp1(int enable)
168{
169 stmp3xxx_pin_pullup(PINID_SSP1_CMD, enable, "mmc");
170}
171
172static unsigned long
173stmp3xxxmmc_setclock_ssp1(void __iomem *base, unsigned long hz)
174{
175 struct clk *ssp, *parent;
176 char *p;
177 long r;
178
179 ssp = clk_get(NULL, "ssp");
180
181 /* using SSP1, no timeout, clock rate 1 */
182 writel(BF(2, SSP_TIMING_CLOCK_DIVIDE) |
183 BF(0xFFFF, SSP_TIMING_TIMEOUT),
184 base + HW_SSP_TIMING);
185
186 p = (hz > 1000000) ? "io" : "osc_24M";
187 parent = clk_get(NULL, p);
188 clk_set_parent(ssp, parent);
189 r = clk_set_rate(ssp, 2 * hz / 1000);
190 clk_put(parent);
191 clk_put(ssp);
192
193 return hz;
194}
195
196static struct stmp3xxxmmc_platform_data mmc_data = {
197 .hw_init = stmp3xxxmmc_hw_init_ssp1,
198 .hw_release = stmp3xxxmmc_hw_release_ssp1,
199 .get_wp = stmp3xxxmmc_get_wp,
200 .cmd_pullup = stmp3xxxmmc_cmd_pullup_ssp1,
201 .setclock = stmp3xxxmmc_setclock_ssp1,
202};
203
204
205static struct pin_group appuart_pins[] = {
206 [0] = {
207 .pins = appuart_pins_0,
208 .nr_pins = ARRAY_SIZE(appuart_pins_0),
209 },
210 [1] = {
211 .pins = appuart_pins_1,
212 .nr_pins = ARRAY_SIZE(appuart_pins_1),
213 },
214};
215
216static struct pin_desc ssp1_pins_desc[] = {
217 { PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0, },
218 { PINID_SSP1_CMD, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
219 { PINID_SSP1_DATA0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
220 { PINID_SSP1_DATA3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
221};
222
223static struct pin_desc ssp2_pins_desc[] = {
224 { PINID_GPMI_WRN, PIN_FUN3, PIN_8MA, PIN_3_3V, 0, },
225 { PINID_GPMI_RDY1, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
226 { PINID_GPMI_D00, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
227 { PINID_GPMI_D03, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
228};
229
230static struct pin_group ssp1_pins = {
231 .pins = ssp1_pins_desc,
232 .nr_pins = ARRAY_SIZE(ssp1_pins_desc),
233};
234
235static struct pin_group ssp2_pins = {
236 .pins = ssp1_pins_desc,
237 .nr_pins = ARRAY_SIZE(ssp2_pins_desc),
238};
239
240static struct pin_desc gpmi_pins_desc[] = {
241 { PINID_GPMI_CE0N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
242 { PINID_GPMI_CE1N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
243 { PINID_GMPI_CE2N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
244 { PINID_GPMI_CLE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
245 { PINID_GPMI_ALE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
246 { PINID_GPMI_WPN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
247 { PINID_GPMI_RDY1, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
248 { PINID_GPMI_D00, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
249 { PINID_GPMI_D01, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
250 { PINID_GPMI_D02, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
251 { PINID_GPMI_D03, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
252 { PINID_GPMI_D04, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
253 { PINID_GPMI_D05, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
254 { PINID_GPMI_D06, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
255 { PINID_GPMI_D07, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
256 { PINID_GPMI_RDY0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
257 { PINID_GPMI_RDY2, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
258 { PINID_GPMI_RDY3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
259 { PINID_GPMI_WRN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
260 { PINID_GPMI_RDN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
261};
262
263static struct pin_group gpmi_pins = {
264 .pins = gpmi_pins_desc,
265 .nr_pins = ARRAY_SIZE(gpmi_pins_desc),
266};
267
268static struct mtd_partition gpmi_partitions[] = {
269 [0] = {
270 .name = "boot",
271 .size = 10 * SZ_1M,
272 .offset = 0,
273 },
274 [1] = {
275 .name = "data",
276 .size = MTDPART_SIZ_FULL,
277 .offset = MTDPART_OFS_APPEND,
278 },
279};
280
281static struct gpmi_platform_data gpmi_data = {
282 .pins = &gpmi_pins,
283 .nr_parts = ARRAY_SIZE(gpmi_partitions),
284 .parts = gpmi_partitions,
285 .part_types = { "cmdline", NULL },
286};
287
288static struct spi_board_info spi_board_info[] __initdata = {
289#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
290 {
291 .modalias = "enc28j60",
292 .max_speed_hz = 6 * 1000 * 1000,
293 .bus_num = 1,
294 .chip_select = 0,
295 .platform_data = NULL,
296 },
297#endif
298};
299
300static void __init stmp378x_devb_init(void)
301{
302 stmp3xxx_pinmux_init(NR_REAL_IRQS);
303
304 /* init stmp3xxx platform */
305 stmp3xxx_init();
306
307 stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control;
308 stmp3xxx_appuart.dev.platform_data = appuart_pins;
309 stmp3xxx_mmc.dev.platform_data = &mmc_data;
310 stmp3xxx_gpmi.dev.platform_data = &gpmi_data;
311 stmp3xxx_spi1.dev.platform_data = &ssp1_pins;
312 stmp3xxx_spi2.dev.platform_data = &ssp2_pins;
313 stmp378x_i2c.dev.platform_data = &i2c_pins;
314
315 /* register spi devices */
316 spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
317
318 /* add board's devices */
319 platform_add_devices(devices, ARRAY_SIZE(devices));
320
321 /* add devices selected by command line ssp1= and ssp2= options */
322 stmp3xxx_ssp1_device_register();
323 stmp3xxx_ssp2_device_register();
324}
325
326MACHINE_START(STMP378X, "STMP378X")
327 .phys_io = 0x80000000,
328 .io_pg_offst = ((0xf0000000) >> 18) & 0xfffc,
329 .boot_params = 0x40000100,
330 .map_io = stmp378x_map_io,
331 .init_irq = stmp378x_init_irq,
332 .timer = &stmp3xxx_timer,
333 .init_machine = stmp378x_devb_init,
334MACHINE_END
diff --git a/arch/arm/mach-stmp37xx/Makefile b/arch/arm/mach-stmp37xx/Makefile
new file mode 100644
index 000000000000..57deffd09fbf
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/Makefile
@@ -0,0 +1,2 @@
1obj-$(CONFIG_ARCH_STMP37XX) += stmp37xx.o
2obj-$(CONFIG_MACH_STMP37XX) += stmp37xx_devb.o
diff --git a/arch/arm/mach-stmp37xx/Makefile.boot b/arch/arm/mach-stmp37xx/Makefile.boot
new file mode 100644
index 000000000000..1568ad404d59
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x40008000
2params_phys-y := 0x40000100
3initrd_phys-y := 0x40800000
diff --git a/arch/arm/mach-stmp37xx/include/mach/entry-macro.S b/arch/arm/mach-stmp37xx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..fed2787b6c34
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/entry-macro.S
@@ -0,0 +1,37 @@
1/*
2 * Low-level IRQ helper macros for Freescale STMP37XX
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18
19 .macro disable_fiq
20 .endm
21
22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
23
24 mov \base, #0xf0000000 @ vm address of IRQ controller
25 ldr \irqnr, [\base, #0x30] @ HW_ICOLL_STAT
26 cmp \irqnr, #0x3f
27 movne \irqstat, #0 @ Ack this IRQ
28 strne \irqstat, [\base, #0x00]@ HW_ICOLL_VECTOR
29 moveqs \irqnr, #0 @ Zero flag set for no IRQ
30
31 .endm
32
33 .macro get_irqnr_preamble, base, tmp
34 .endm
35
36 .macro arch_ret_to_user, tmp1, tmp2
37 .endm
diff --git a/arch/arm/mach-stmp37xx/include/mach/irqs.h b/arch/arm/mach-stmp37xx/include/mach/irqs.h
new file mode 100644
index 000000000000..98f12938550d
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/irqs.h
@@ -0,0 +1,99 @@
1/*
2 * Freescale STMP37XX interrupts
3 *
4 * Copyright (C) 2005 Sigmatel Inc
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef _ASM_ARCH_IRQS_H
19#define _ASM_ARCH_IRQS_H
20
21#define IRQ_DEBUG_UART 0
22#define IRQ_COMMS_RX 1
23#define IRQ_COMMS_TX 1
24#define IRQ_SSP2_ERROR 2
25#define IRQ_VDD5V 3
26#define IRQ_HEADPHONE_SHORT 4
27#define IRQ_DAC_DMA 5
28#define IRQ_DAC_ERROR 6
29#define IRQ_ADC_DMA 7
30#define IRQ_ADC_ERROR 8
31#define IRQ_SPDIF_DMA 9
32#define IRQ_SAIF2_DMA 9
33#define IRQ_SPDIF_ERROR 10
34#define IRQ_SAIF1_IRQ 10
35#define IRQ_SAIF2_IRQ 10
36#define IRQ_USB_CTRL 11
37#define IRQ_USB_WAKEUP 12
38#define IRQ_GPMI_DMA 13
39#define IRQ_SSP1_DMA 14
40#define IRQ_SSP_ERROR 15
41#define IRQ_GPIO0 16
42#define IRQ_GPIO1 17
43#define IRQ_GPIO2 18
44#define IRQ_SAIF1_DMA 19
45#define IRQ_SSP2_DMA 20
46#define IRQ_ECC8_IRQ 21
47#define IRQ_RTC_ALARM 22
48#define IRQ_UARTAPP_TX_DMA 23
49#define IRQ_UARTAPP_INTERNAL 24
50#define IRQ_UARTAPP_RX_DMA 25
51#define IRQ_I2C_DMA 26
52#define IRQ_I2C_ERROR 27
53#define IRQ_TIMER0 28
54#define IRQ_TIMER1 29
55#define IRQ_TIMER2 30
56#define IRQ_TIMER3 31
57#define IRQ_BATT_BRNOUT 32
58#define IRQ_VDDD_BRNOUT 33
59#define IRQ_VDDIO_BRNOUT 34
60#define IRQ_VDD18_BRNOUT 35
61#define IRQ_TOUCH_DETECT 36
62#define IRQ_LRADC_CH0 37
63#define IRQ_LRADC_CH1 38
64#define IRQ_LRADC_CH2 39
65#define IRQ_LRADC_CH3 40
66#define IRQ_LRADC_CH4 41
67#define IRQ_LRADC_CH5 42
68#define IRQ_LRADC_CH6 43
69#define IRQ_LRADC_CH7 44
70#define IRQ_LCDIF_DMA 45
71#define IRQ_LCDIF_ERROR 46
72#define IRQ_DIGCTL_DEBUG_TRAP 47
73#define IRQ_RTC_1MSEC 48
74#define IRQ_DRI_DMA 49
75#define IRQ_DRI_ATTENTION 50
76#define IRQ_GPMI_ATTENTION 51
77#define IRQ_IR 52
78#define IRQ_DCP_VMI 53
79#define IRQ_DCP 54
80#define IRQ_RESERVED_55 55
81#define IRQ_RESERVED_56 56
82#define IRQ_RESERVED_57 57
83#define IRQ_RESERVED_58 58
84#define IRQ_RESERVED_59 59
85#define SW_IRQ_60 60
86#define SW_IRQ_61 61
87#define SW_IRQ_62 62
88#define SW_IRQ_63 63
89
90#define NR_REAL_IRQS 64
91#define NR_IRQS (NR_REAL_IRQS + 32 * 3)
92
93/* TIMER and BRNOUT are FIQ capable */
94#define FIQ_START IRQ_TIMER0
95
96/* Hard disk IRQ is a GPMI attention IRQ */
97#define IRQ_HARDDISK IRQ_GPMI_ATTENTION
98
99#endif /* _ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-stmp37xx/include/mach/pins.h b/arch/arm/mach-stmp37xx/include/mach/pins.h
new file mode 100644
index 000000000000..d56de0c471d8
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/pins.h
@@ -0,0 +1,147 @@
1/*
2 * Freescale STMP37XX SoC pin multiplexing
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_ARCH_PINS_H
19#define __ASM_ARCH_PINS_H
20
21/*
22 * Define all STMP37XX pins, a pin name corresponds to a STMP37xx hardware
23 * interface this pin belongs to.
24 */
25
26/* Bank 0 */
27#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0)
28#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1)
29#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2)
30#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3)
31#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4)
32#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5)
33#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6)
34#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7)
35#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8)
36#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9)
37#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10)
38#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11)
39#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12)
40#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13)
41#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14)
42#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15)
43#define PINID_GPMI_A0 STMP3XXX_PINID(0, 16)
44#define PINID_GPMI_A1 STMP3XXX_PINID(0, 17)
45#define PINID_GPMI_A2 STMP3XXX_PINID(0, 18)
46#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19)
47#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 20)
48#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 21)
49#define PINID_GPMI_RESETN STMP3XXX_PINID(0, 22)
50#define PINID_GPMI_IRQ STMP3XXX_PINID(0, 23)
51#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24)
52#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25)
53#define PINID_UART2_CTS STMP3XXX_PINID(0, 26)
54#define PINID_UART2_RTS STMP3XXX_PINID(0, 27)
55#define PINID_UART2_RX STMP3XXX_PINID(0, 28)
56#define PINID_UART2_TX STMP3XXX_PINID(0, 29)
57
58/* Bank 1 */
59#define PINID_LCD_D00 STMP3XXX_PINID(1, 0)
60#define PINID_LCD_D01 STMP3XXX_PINID(1, 1)
61#define PINID_LCD_D02 STMP3XXX_PINID(1, 2)
62#define PINID_LCD_D03 STMP3XXX_PINID(1, 3)
63#define PINID_LCD_D04 STMP3XXX_PINID(1, 4)
64#define PINID_LCD_D05 STMP3XXX_PINID(1, 5)
65#define PINID_LCD_D06 STMP3XXX_PINID(1, 6)
66#define PINID_LCD_D07 STMP3XXX_PINID(1, 7)
67#define PINID_LCD_D08 STMP3XXX_PINID(1, 8)
68#define PINID_LCD_D09 STMP3XXX_PINID(1, 9)
69#define PINID_LCD_D10 STMP3XXX_PINID(1, 10)
70#define PINID_LCD_D11 STMP3XXX_PINID(1, 11)
71#define PINID_LCD_D12 STMP3XXX_PINID(1, 12)
72#define PINID_LCD_D13 STMP3XXX_PINID(1, 13)
73#define PINID_LCD_D14 STMP3XXX_PINID(1, 14)
74#define PINID_LCD_D15 STMP3XXX_PINID(1, 15)
75#define PINID_LCD_RESET STMP3XXX_PINID(1, 16)
76#define PINID_LCD_RS STMP3XXX_PINID(1, 17)
77#define PINID_LCD_WR_RWN STMP3XXX_PINID(1, 18)
78#define PINID_LCD_RD_E STMP3XXX_PINID(1, 19)
79#define PINID_LCD_CS STMP3XXX_PINID(1, 20)
80#define PINID_LCD_BUSY STMP3XXX_PINID(1, 21)
81#define PINID_SSP1_CMD STMP3XXX_PINID(1, 22)
82#define PINID_SSP1_SCK STMP3XXX_PINID(1, 23)
83#define PINID_SSP1_DATA0 STMP3XXX_PINID(1, 24)
84#define PINID_SSP1_DATA1 STMP3XXX_PINID(1, 25)
85#define PINID_SSP1_DATA2 STMP3XXX_PINID(1, 26)
86#define PINID_SSP1_DATA3 STMP3XXX_PINID(1, 27)
87#define PINID_SSP1_DETECT STMP3XXX_PINID(1, 28)
88
89/* Bank 2 */
90#define PINID_PWM0 STMP3XXX_PINID(2, 0)
91#define PINID_PWM1 STMP3XXX_PINID(2, 1)
92#define PINID_PWM2 STMP3XXX_PINID(2, 2)
93#define PINID_PWM3 STMP3XXX_PINID(2, 3)
94#define PINID_PWM4 STMP3XXX_PINID(2, 4)
95#define PINID_I2C_SCL STMP3XXX_PINID(2, 5)
96#define PINID_I2C_SDA STMP3XXX_PINID(2, 6)
97#define PINID_ROTTARYA STMP3XXX_PINID(2, 7)
98#define PINID_ROTTARYB STMP3XXX_PINID(2, 8)
99#define PINID_EMI_CKE STMP3XXX_PINID(2, 9)
100#define PINID_EMI_RASN STMP3XXX_PINID(2, 10)
101#define PINID_EMI_CASN STMP3XXX_PINID(2, 11)
102#define PINID_EMI_CE0N STMP3XXX_PINID(2, 12)
103#define PINID_EMI_CE1N STMP3XXX_PINID(2, 13)
104#define PINID_EMI_CE2N STMP3XXX_PINID(2, 14)
105#define PINID_EMI_CE3N STMP3XXX_PINID(2, 15)
106#define PINID_EMI_A00 STMP3XXX_PINID(2, 16)
107#define PINID_EMI_A01 STMP3XXX_PINID(2, 17)
108#define PINID_EMI_A02 STMP3XXX_PINID(2, 18)
109#define PINID_EMI_A03 STMP3XXX_PINID(2, 19)
110#define PINID_EMI_A04 STMP3XXX_PINID(2, 20)
111#define PINID_EMI_A05 STMP3XXX_PINID(2, 21)
112#define PINID_EMI_A06 STMP3XXX_PINID(2, 22)
113#define PINID_EMI_A07 STMP3XXX_PINID(2, 23)
114#define PINID_EMI_A08 STMP3XXX_PINID(2, 24)
115#define PINID_EMI_A09 STMP3XXX_PINID(2, 25)
116#define PINID_EMI_A10 STMP3XXX_PINID(2, 26)
117#define PINID_EMI_A11 STMP3XXX_PINID(2, 27)
118#define PINID_EMI_A12 STMP3XXX_PINID(2, 28)
119#define PINID_EMI_A13 STMP3XXX_PINID(2, 29)
120#define PINID_EMI_A14 STMP3XXX_PINID(2, 30)
121#define PINID_EMI_WEN STMP3XXX_PINID(2, 31)
122
123/* Bank 3 */
124#define PINID_EMI_D00 STMP3XXX_PINID(3, 0)
125#define PINID_EMI_D01 STMP3XXX_PINID(3, 1)
126#define PINID_EMI_D02 STMP3XXX_PINID(3, 2)
127#define PINID_EMI_D03 STMP3XXX_PINID(3, 3)
128#define PINID_EMI_D04 STMP3XXX_PINID(3, 4)
129#define PINID_EMI_D05 STMP3XXX_PINID(3, 5)
130#define PINID_EMI_D06 STMP3XXX_PINID(3, 6)
131#define PINID_EMI_D07 STMP3XXX_PINID(3, 7)
132#define PINID_EMI_D08 STMP3XXX_PINID(3, 8)
133#define PINID_EMI_D09 STMP3XXX_PINID(3, 9)
134#define PINID_EMI_D10 STMP3XXX_PINID(3, 10)
135#define PINID_EMI_D11 STMP3XXX_PINID(3, 11)
136#define PINID_EMI_D12 STMP3XXX_PINID(3, 12)
137#define PINID_EMI_D13 STMP3XXX_PINID(3, 13)
138#define PINID_EMI_D14 STMP3XXX_PINID(3, 14)
139#define PINID_EMI_D15 STMP3XXX_PINID(3, 15)
140#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 16)
141#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 17)
142#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 18)
143#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 19)
144#define PINID_EMI_CLK STMP3XXX_PINID(3, 20)
145#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21)
146
147#endif /* __ASM_ARCH_PINS_H */
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h
new file mode 100644
index 000000000000..a323aa9a21f2
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h
@@ -0,0 +1,97 @@
1/*
2 * stmp37xx: APBH register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_APBH
22#define _MACH_REGS_APBH
23
24#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000)
25
26#define HW_APBH_CTRL0 0x0
27#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
28#define BP_APBH_CTRL0_RESET_CHANNEL 16
29#define BM_APBH_CTRL0_CLKGATE 0x40000000
30#define BM_APBH_CTRL0_SFTRST 0x80000000
31
32#define HW_APBH_CTRL1 0x10
33#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
34#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
35
36#define HW_APBH_DEVSEL 0x20
37
38#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70)
39#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70)
40#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70)
41#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70)
42#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70)
43#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70)
44#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70)
45#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70)
46#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70)
47#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70)
48#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70)
49#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70)
50#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70)
51#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70)
52#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70)
53#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70)
54
55#define HW_APBH_CHn_NXTCMDAR 0x50
56
57#define BM_APBH_CHn_CMD_MODE 0x00000003
58#define BP_APBH_CHn_CMD_MODE 0x00000001
59#define BV_APBH_CHn_CMD_MODE_NOOP 0
60#define BV_APBH_CHn_CMD_MODE_WRITE 1
61#define BV_APBH_CHn_CMD_MODE_READ 2
62#define BV_APBH_CHn_CMD_MODE_SENSE 3
63#define BM_APBH_CHn_CMD_CHAIN 0x00000004
64#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
65#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
66#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
67#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
68#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
69#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
70#define BP_APBH_CHn_CMD_CMDWORDS 12
71#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
72#define BP_APBH_CHn_CMD_XFER_COUNT 16
73
74#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70)
75#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70)
76#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70)
77#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70)
78#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70)
79#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70)
80#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70)
81#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70)
82#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70)
83#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70)
84#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70)
85#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70)
86#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70)
87#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70)
88#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70)
89#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70)
90
91#define HW_APBH_CHn_SEMA 0x80
92#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
93#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
94#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
95#define BP_APBH_CHn_SEMA_PHORE 16
96
97#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h
new file mode 100644
index 000000000000..6d080cd5b702
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h
@@ -0,0 +1,113 @@
1/*
2 * stmp37xx: APBX register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_APBX
22#define _MACH_REGS_APBX
23
24#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000)
25
26#define HW_APBX_CTRL0 0x0
27#define BM_APBX_CTRL0_RESET_CHANNEL 0x00FF0000
28#define BP_APBX_CTRL0_RESET_CHANNEL 16
29#define BM_APBX_CTRL0_CLKGATE 0x40000000
30#define BM_APBX_CTRL0_SFTRST 0x80000000
31
32#define HW_APBX_CTRL1 0x10
33
34#define HW_APBX_DEVSEL 0x20
35
36#define HW_APBX_CH0_NXTCMDAR (0x50 + 0 * 0x70)
37#define HW_APBX_CH1_NXTCMDAR (0x50 + 1 * 0x70)
38#define HW_APBX_CH2_NXTCMDAR (0x50 + 2 * 0x70)
39#define HW_APBX_CH3_NXTCMDAR (0x50 + 3 * 0x70)
40#define HW_APBX_CH4_NXTCMDAR (0x50 + 4 * 0x70)
41#define HW_APBX_CH5_NXTCMDAR (0x50 + 5 * 0x70)
42#define HW_APBX_CH6_NXTCMDAR (0x50 + 6 * 0x70)
43#define HW_APBX_CH7_NXTCMDAR (0x50 + 7 * 0x70)
44#define HW_APBX_CH8_NXTCMDAR (0x50 + 8 * 0x70)
45#define HW_APBX_CH9_NXTCMDAR (0x50 + 9 * 0x70)
46#define HW_APBX_CH10_NXTCMDAR (0x50 + 10 * 0x70)
47#define HW_APBX_CH11_NXTCMDAR (0x50 + 11 * 0x70)
48#define HW_APBX_CH12_NXTCMDAR (0x50 + 12 * 0x70)
49#define HW_APBX_CH13_NXTCMDAR (0x50 + 13 * 0x70)
50#define HW_APBX_CH14_NXTCMDAR (0x50 + 14 * 0x70)
51#define HW_APBX_CH15_NXTCMDAR (0x50 + 15 * 0x70)
52
53#define HW_APBX_CHn_NXTCMDAR 0x50
54#define BM_APBX_CHn_CMD_MODE 0x00000003
55#define BP_APBX_CHn_CMD_MODE 0x00000001
56#define BV_APBX_CHn_CMD_MODE_NOOP 0
57#define BV_APBX_CHn_CMD_MODE_WRITE 1
58#define BV_APBX_CHn_CMD_MODE_READ 2
59#define BV_APBX_CHn_CMD_MODE_SENSE 3
60#define BM_APBX_CHn_CMD_COMMAND 0x00000003
61#define BP_APBX_CHn_CMD_COMMAND 0
62#define BM_APBX_CHn_CMD_CHAIN 0x00000004
63#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
64#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
65#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
66#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
67#define BP_APBX_CHn_CMD_CMDWORDS 12
68#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
69#define BP_APBX_CHn_CMD_XFER_COUNT 16
70
71#define HW_APBX_CH0_BAR (0x70 + 0 * 0x70)
72#define HW_APBX_CH1_BAR (0x70 + 1 * 0x70)
73#define HW_APBX_CH2_BAR (0x70 + 2 * 0x70)
74#define HW_APBX_CH3_BAR (0x70 + 3 * 0x70)
75#define HW_APBX_CH4_BAR (0x70 + 4 * 0x70)
76#define HW_APBX_CH5_BAR (0x70 + 5 * 0x70)
77#define HW_APBX_CH6_BAR (0x70 + 6 * 0x70)
78#define HW_APBX_CH7_BAR (0x70 + 7 * 0x70)
79#define HW_APBX_CH8_BAR (0x70 + 8 * 0x70)
80#define HW_APBX_CH9_BAR (0x70 + 9 * 0x70)
81#define HW_APBX_CH10_BAR (0x70 + 10 * 0x70)
82#define HW_APBX_CH11_BAR (0x70 + 11 * 0x70)
83#define HW_APBX_CH12_BAR (0x70 + 12 * 0x70)
84#define HW_APBX_CH13_BAR (0x70 + 13 * 0x70)
85#define HW_APBX_CH14_BAR (0x70 + 14 * 0x70)
86#define HW_APBX_CH15_BAR (0x70 + 15 * 0x70)
87
88#define HW_APBX_CHn_BAR 0x70
89
90#define HW_APBX_CH0_SEMA (0x80 + 0 * 0x70)
91#define HW_APBX_CH1_SEMA (0x80 + 1 * 0x70)
92#define HW_APBX_CH2_SEMA (0x80 + 2 * 0x70)
93#define HW_APBX_CH3_SEMA (0x80 + 3 * 0x70)
94#define HW_APBX_CH4_SEMA (0x80 + 4 * 0x70)
95#define HW_APBX_CH5_SEMA (0x80 + 5 * 0x70)
96#define HW_APBX_CH6_SEMA (0x80 + 6 * 0x70)
97#define HW_APBX_CH7_SEMA (0x80 + 7 * 0x70)
98#define HW_APBX_CH8_SEMA (0x80 + 8 * 0x70)
99#define HW_APBX_CH9_SEMA (0x80 + 9 * 0x70)
100#define HW_APBX_CH10_SEMA (0x80 + 10 * 0x70)
101#define HW_APBX_CH11_SEMA (0x80 + 11 * 0x70)
102#define HW_APBX_CH12_SEMA (0x80 + 12 * 0x70)
103#define HW_APBX_CH13_SEMA (0x80 + 13 * 0x70)
104#define HW_APBX_CH14_SEMA (0x80 + 14 * 0x70)
105#define HW_APBX_CH15_SEMA (0x80 + 15 * 0x70)
106
107#define HW_APBX_CHn_SEMA 0x80
108#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
109#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
110#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
111#define BP_APBX_CHn_SEMA_PHORE 16
112
113#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h b/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h
new file mode 100644
index 000000000000..3b511f947a53
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h
@@ -0,0 +1,61 @@
1/*
2 * stmp37xx: AUDIOIN register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000)
22
23#define HW_AUDIOIN_CTRL 0x0
24#define BM_AUDIOIN_CTRL_RUN 0x00000001
25#define BP_AUDIOIN_CTRL_RUN 0
26#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
27#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
28#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
29#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020
30#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
31#define BM_AUDIOIN_CTRL_SFTRST 0x80000000
32
33#define HW_AUDIOIN_STAT 0x10
34
35#define HW_AUDIOIN_ADCSRR 0x20
36
37#define HW_AUDIOIN_ADCVOLUME 0x30
38#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF
39#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0
40#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000
41#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16
42
43#define HW_AUDIOIN_ADCDEBUG 0x40
44
45#define HW_AUDIOIN_ADCVOL 0x50
46#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F
47#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0
48#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030
49#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4
50#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00
51#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8
52#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000
53#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12
54#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000
55
56#define HW_AUDIOIN_MICLINE 0x60
57
58#define HW_AUDIOIN_ANACLKCTRL 0x70
59#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000
60
61#define HW_AUDIOIN_DATA 0x80
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h b/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h
new file mode 100644
index 000000000000..ca1942b8a3e9
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h
@@ -0,0 +1,111 @@
1/*
2 * stmp37xx: AUDIOOUT register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000)
22
23#define HW_AUDIOOUT_CTRL 0x0
24#define BM_AUDIOOUT_CTRL_RUN 0x00000001
25#define BP_AUDIOOUT_CTRL_RUN 0
26#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
27#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
28#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
29#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040
30#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000
31#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
32
33#define HW_AUDIOOUT_STAT 0x10
34
35#define HW_AUDIOOUT_DACSRR 0x20
36#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF
37#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0
38#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000
39#define BP_AUDIOOUT_DACSRR_SRC_INT 16
40#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000
41#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24
42#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000
43#define BP_AUDIOOUT_DACSRR_BASEMULT 28
44
45#define HW_AUDIOOUT_DACVOLUME 0x30
46#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100
47#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
48#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000
49
50#define HW_AUDIOOUT_DACDEBUG 0x40
51
52#define HW_AUDIOOUT_HPVOL 0x50
53#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000
54#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000
55
56#define HW_AUDIOOUT_PWRDN 0x70
57#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001
58#define BP_AUDIOOUT_PWRDN_HEADPHONE 0
59#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010
60#define BM_AUDIOOUT_PWRDN_ADC 0x00000100
61#define BM_AUDIOOUT_PWRDN_DAC 0x00001000
62#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000
63#define BM_AUDIOOUT_PWRDN_LINEOUT 0x01000000
64
65#define HW_AUDIOOUT_REFCTRL 0x80
66#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0
67#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4
68#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00
69#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8
70#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000
71#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000
72#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000
73#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16
74#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000
75#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000
76#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20
77#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000
78#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000
79
80#define HW_AUDIOOUT_ANACTRL 0x90
81#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010
82#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
83
84#define HW_AUDIOOUT_TEST 0xA0
85#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000
86#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22
87
88#define HW_AUDIOOUT_BISTCTRL 0xB0
89
90#define HW_AUDIOOUT_BISTSTAT0 0xC0
91
92#define HW_AUDIOOUT_BISTSTAT1 0xD0
93
94#define HW_AUDIOOUT_ANACLKCTRL 0xE0
95#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000
96
97#define HW_AUDIOOUT_DATA 0xF0
98
99#define HW_AUDIOOUT_LINEOUTCTRL 0x100
100#define BM_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0x0000001F
101#define BP_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0
102#define BM_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 0x00001F00
103#define BP_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 8
104#define BM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 0x00007000
105#define BP_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 12
106#define BM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 0x00F00000
107#define BP_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 20
108#define BM_AUDIOOUT_LINEOUTCTRL_MUTE 0x01000000
109#define BM_AUDIOOUT_LINEOUTCTRL_EN_ZCD 0x02000000
110
111#define HW_AUDIOOUT_VERSION 0x200
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h
new file mode 100644
index 000000000000..47f5c92fdaf6
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h
@@ -0,0 +1,72 @@
1/*
2 * stmp37xx: CLKCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_CLKCTRL
22#define _MACH_REGS_CLKCTRL
23
24#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000)
25
26#define HW_CLKCTRL_PLLCTRL0 0x0
27#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
28
29#define HW_CLKCTRL_CPU 0x20
30#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
31#define BP_CLKCTRL_CPU_DIV_CPU 0
32
33#define HW_CLKCTRL_HBUS 0x30
34#define BM_CLKCTRL_HBUS_DIV 0x0000001F
35#define BP_CLKCTRL_HBUS_DIV 0
36
37#define HW_CLKCTRL_XBUS 0x40
38
39#define HW_CLKCTRL_XTAL 0x50
40
41#define HW_CLKCTRL_PIX 0x60
42#define BM_CLKCTRL_PIX_DIV 0x00007FFF
43#define BP_CLKCTRL_PIX_DIV 0
44#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
45
46#define HW_CLKCTRL_SSP 0x70
47
48#define HW_CLKCTRL_GPMI 0x80
49
50#define HW_CLKCTRL_SPDIF 0x90
51
52#define HW_CLKCTRL_EMI 0xA0
53
54#define HW_CLKCTRL_IR 0xB0
55
56#define HW_CLKCTRL_SAIF 0xC0
57
58#define HW_CLKCTRL_FRAC 0xD0
59#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
60#define BP_CLKCTRL_FRAC_EMIFRAC 8
61#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
62#define BP_CLKCTRL_FRAC_PIXFRAC 16
63#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
64
65#define HW_CLKCTRL_CLKSEQ 0xE0
66#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
67
68#define HW_CLKCTRL_RESET 0xF0
69#define BM_CLKCTRL_RESET_DIG 0x00000001
70#define BP_CLKCTRL_RESET_DIG 0
71
72#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h b/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h
new file mode 100644
index 000000000000..ba1bbe265c20
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h
@@ -0,0 +1,24 @@
1/*
2 * stmp37xx: DIGCTL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000)
22
23#define HW_DIGCTL_CTRL 0x0
24#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h b/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h
new file mode 100644
index 000000000000..3b6d990a3af5
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h
@@ -0,0 +1,37 @@
1/*
2 * stmp37xx: ECC8 register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000)
22
23#define HW_ECC8_CTRL 0x0
24#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001
25#define BP_ECC8_CTRL_COMPLETE_IRQ 0
26#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100
27#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000
28
29#define HW_ECC8_STATUS0 0x10
30#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004
31#define BM_ECC8_STATUS0_CORRECTED 0x00000008
32#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00
33#define BP_ECC8_STATUS0_STATUS_AUX 8
34#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000
35#define BP_ECC8_STATUS0_COMPLETED_CE 16
36
37#define HW_ECC8_STATUS1 0x20
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h b/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h
new file mode 100644
index 000000000000..f2b304f54490
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h
@@ -0,0 +1,63 @@
1/*
2 * stmp37xx: GPMI register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000)
22#define REGS_GPMI_PHYS 0x8000C000
23#define REGS_GPMI_SIZE 0x2000
24
25#define HW_GPMI_CTRL0 0x0
26#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_GPMI_CTRL0_XFER_COUNT 0
28#define BM_GPMI_CTRL0_CS 0x00300000
29#define BP_GPMI_CTRL0_CS 20
30#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
31#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
32#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
33#define BP_GPMI_CTRL0_COMMAND_MODE 24
34#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
35#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
36#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
37#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
38#define BM_GPMI_CTRL0_RUN 0x20000000
39#define BM_GPMI_CTRL0_CLKGATE 0x40000000
40#define BM_GPMI_CTRL0_SFTRST 0x80000000
41#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
42#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
43#define BP_GPMI_ECCCTRL_ECC_CMD 13
44
45#define HW_GPMI_CTRL1 0x60
46#define BM_GPMI_CTRL1_GPMI_MODE 0x00000003
47#define BP_GPMI_CTRL1_GPMI_MODE 0
48#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
49#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
50#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
51#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
52#define BM_GPMI_CTRL1_DSAMPLE_TIME 0x00007000
53#define BP_GPMI_CTRL1_DSAMPLE_TIME 12
54
55#define HW_GPMI_TIMING0 0x70
56#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
57#define BP_GPMI_TIMING0_DATA_SETUP 0
58#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
59#define BP_GPMI_TIMING0_DATA_HOLD 8
60
61#define HW_GPMI_TIMING1 0x80
62#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
63#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h b/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h
new file mode 100644
index 000000000000..35882a9b8bc5
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h
@@ -0,0 +1,55 @@
1/*
2 * stmp37xx: I2C register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000)
22#define REGS_I2C_PHYS 0x80058000
23#define REGS_I2C_SIZE 0x2000
24
25#define HW_I2C_CTRL0 0x0
26#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_I2C_CTRL0_XFER_COUNT 0
28#define BM_I2C_CTRL0_DIRECTION 0x00010000
29#define BM_I2C_CTRL0_MASTER_MODE 0x00020000
30#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000
31#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000
32#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000
33#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
34#define BM_I2C_CTRL0_CLKGATE 0x40000000
35#define BM_I2C_CTRL0_SFTRST 0x80000000
36
37#define HW_I2C_TIMING0 0x10
38
39#define HW_I2C_TIMING1 0x20
40
41#define HW_I2C_TIMING2 0x30
42
43#define HW_I2C_CTRL1 0x40
44#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001
45#define BP_I2C_CTRL1_SLAVE_IRQ 0
46#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002
47#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004
48#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008
49#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010
50#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020
51#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040
52#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080
53#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
54
55#define HW_I2C_VERSION 0x90
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h b/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h
new file mode 100644
index 000000000000..3b7c92239e20
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h
@@ -0,0 +1,43 @@
1/*
2 * stmp37xx: ICOLL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_ICOLL
22#define _MACH_REGS_ICOLL
23
24#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0)
25
26#define HW_ICOLL_VECTOR 0x0
27
28#define HW_ICOLL_LEVELACK 0x10
29
30#define HW_ICOLL_CTRL 0x20
31#define BM_ICOLL_CTRL_CLKGATE 0x40000000
32#define BM_ICOLL_CTRL_SFTRST 0x80000000
33
34#define HW_ICOLL_STAT 0x30
35
36#define HW_ICOLL_PRIORITY0 (0x60 + 0 * 0x10)
37#define HW_ICOLL_PRIORITY1 (0x60 + 1 * 0x10)
38#define HW_ICOLL_PRIORITY2 (0x60 + 2 * 0x10)
39#define HW_ICOLL_PRIORITY3 (0x60 + 3 * 0x10)
40
41#define HW_ICOLL_PRIORITYn 0x60
42
43#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h b/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h
new file mode 100644
index 000000000000..72514e8b0737
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h
@@ -0,0 +1,89 @@
1/*
2 * stmp37xx: LCDIF register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000)
22#define REGS_LCDIF_PHYS 0x80030000
23#define REGS_LCDIF_SIZE 0x2000
24
25#define HW_LCDIF_CTRL 0x0
26#define BM_LCDIF_CTRL_COUNT 0x0000FFFF
27#define BP_LCDIF_CTRL_COUNT 0
28#define BM_LCDIF_CTRL_RUN 0x00010000
29#define BM_LCDIF_CTRL_WORD_LENGTH 0x00020000
30#define BM_LCDIF_CTRL_DATA_SELECT 0x00040000
31#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00080000
32#define BM_LCDIF_CTRL_VSYNC_MODE 0x00100000
33#define BM_LCDIF_CTRL_DATA_SWIZZLE 0x00600000
34#define BP_LCDIF_CTRL_DATA_SWIZZLE 21
35#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00800000
36#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x06000000
37#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 25
38#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x08000000
39#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x10000000
40#define BM_LCDIF_CTRL_CLKGATE 0x40000000
41#define BM_LCDIF_CTRL_SFTRST 0x80000000
42
43#define HW_LCDIF_CTRL1 0x10
44#define BM_LCDIF_CTRL1_RESET 0x00000001
45#define BP_LCDIF_CTRL1_RESET 0
46#define BM_LCDIF_CTRL1_MODE86 0x00000002
47#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004
48#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100
49#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200
50#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400
51#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800
52#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000
53#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000
54#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16
55
56#define HW_LCDIF_TIMING 0x20
57
58#define HW_LCDIF_VDCTRL0 0x30
59#define BM_LCDIF_VDCTRL0_VALID_DATA_CNT 0x000003FF
60#define BP_LCDIF_VDCTRL0_VALID_DATA_CNT 0
61#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
62#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000
63#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000
64#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000
65#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000
66#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000
67#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
68#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000
69
70#define HW_LCDIF_VDCTRL1 0x40
71#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0x000FFFFF
72#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0
73#define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 0xFFF00000
74#define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 20
75
76#define HW_LCDIF_VDCTRL2 0x50
77#define BM_LCDIF_VDCTRL2_VALID_DATA_CNT 0x000007FF
78#define BP_LCDIF_VDCTRL2_VALID_DATA_CNT 0
79#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x007FF800
80#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 11
81#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF800000
82#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 23
83
84#define HW_LCDIF_VDCTRL3 0x60
85#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x000001FF
86#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0
87#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x00FFF000
88#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 12
89#define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON 0x01000000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h b/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h
new file mode 100644
index 000000000000..cc7b4702d1cd
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h
@@ -0,0 +1,97 @@
1/*
2 * stmp37xx: LRADC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000)
22
23#define HW_LRADC_CTRL0 0x0
24#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF
25#define BP_LRADC_CTRL0_SCHEDULE 0
26#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000
27#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000
28#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000
29#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000
30#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000
31#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000
32#define BM_LRADC_CTRL0_CLKGATE 0x40000000
33#define BM_LRADC_CTRL0_SFTRST 0x80000000
34
35#define HW_LRADC_CTRL1 0x10
36#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001
37#define BP_LRADC_CTRL1_LRADC0_IRQ 0
38#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020
39#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040
40#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100
41#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000
42#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000
43#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000
44
45#define HW_LRADC_CTRL2 0x20
46#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000
47#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16
48#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000
49#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000
50#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000
51#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24
52
53#define HW_LRADC_CTRL3 0x30
54#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300
55#define BP_LRADC_CTRL3_CYCLE_TIME 8
56
57#define HW_LRADC_STATUS 0x40
58#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001
59#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0
60
61#define HW_LRADC_CH0 (0x50 + 0 * 0x10)
62#define HW_LRADC_CH1 (0x50 + 1 * 0x10)
63#define HW_LRADC_CH2 (0x50 + 2 * 0x10)
64#define HW_LRADC_CH3 (0x50 + 3 * 0x10)
65#define HW_LRADC_CH4 (0x50 + 4 * 0x10)
66#define HW_LRADC_CH5 (0x50 + 5 * 0x10)
67#define HW_LRADC_CH6 (0x50 + 6 * 0x10)
68#define HW_LRADC_CH7 (0x50 + 7 * 0x10)
69
70#define HW_LRADC_CHn 0x50
71#define BM_LRADC_CHn_VALUE 0x0003FFFF
72#define BP_LRADC_CHn_VALUE 0
73#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000
74#define BP_LRADC_CHn_NUM_SAMPLES 24
75#define BM_LRADC_CHn_ACCUMULATE 0x20000000
76
77#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10)
78#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10)
79#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10)
80#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10)
81
82#define HW_LRADC_DELAYn 0xD0
83#define BM_LRADC_DELAYn_DELAY 0x000007FF
84#define BP_LRADC_DELAYn_DELAY 0
85#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800
86#define BP_LRADC_DELAYn_LOOP_COUNT 11
87#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000
88#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16
89#define BM_LRADC_DELAYn_KICK 0x00100000
90#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000
91#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24
92
93#define HW_LRADC_CTRL4 0x140
94#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000
95#define BP_LRADC_CTRL4_LRADC6SELECT 24
96#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000
97#define BP_LRADC_CTRL4_LRADC7SELECT 28
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h
new file mode 100644
index 000000000000..d5efce2388c7
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h
@@ -0,0 +1,88 @@
1/*
2 * stmp37xx: PINCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_PINCTRL
22#define _MACH_REGS_PINCTRL
23
24#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000)
25
26#define HW_PINCTRL_MUXSEL0 0x100
27#define HW_PINCTRL_MUXSEL1 0x110
28#define HW_PINCTRL_MUXSEL2 0x120
29#define HW_PINCTRL_MUXSEL3 0x130
30#define HW_PINCTRL_MUXSEL4 0x140
31#define HW_PINCTRL_MUXSEL5 0x150
32#define HW_PINCTRL_MUXSEL6 0x160
33#define HW_PINCTRL_MUXSEL7 0x170
34
35#define HW_PINCTRL_DRIVE0 0x200
36#define HW_PINCTRL_DRIVE1 0x210
37#define HW_PINCTRL_DRIVE2 0x220
38#define HW_PINCTRL_DRIVE3 0x230
39#define HW_PINCTRL_DRIVE4 0x240
40#define HW_PINCTRL_DRIVE5 0x250
41#define HW_PINCTRL_DRIVE6 0x260
42#define HW_PINCTRL_DRIVE7 0x270
43#define HW_PINCTRL_DRIVE8 0x280
44#define HW_PINCTRL_DRIVE9 0x290
45#define HW_PINCTRL_DRIVE10 0x2A0
46#define HW_PINCTRL_DRIVE11 0x2B0
47#define HW_PINCTRL_DRIVE12 0x2C0
48#define HW_PINCTRL_DRIVE13 0x2D0
49#define HW_PINCTRL_DRIVE14 0x2E0
50
51#define HW_PINCTRL_PULL0 0x300
52#define HW_PINCTRL_PULL1 0x310
53#define HW_PINCTRL_PULL2 0x320
54#define HW_PINCTRL_PULL3 0x330
55
56#define HW_PINCTRL_DOUT0 0x400
57#define HW_PINCTRL_DOUT1 0x410
58#define HW_PINCTRL_DOUT2 0x420
59
60#define HW_PINCTRL_DIN0 0x500
61#define HW_PINCTRL_DIN1 0x510
62#define HW_PINCTRL_DIN2 0x520
63
64#define HW_PINCTRL_DOE0 0x600
65#define HW_PINCTRL_DOE1 0x610
66#define HW_PINCTRL_DOE2 0x620
67
68#define HW_PINCTRL_PIN2IRQ0 0x700
69#define HW_PINCTRL_PIN2IRQ1 0x710
70#define HW_PINCTRL_PIN2IRQ2 0x720
71
72#define HW_PINCTRL_IRQEN0 0x800
73#define HW_PINCTRL_IRQEN1 0x810
74#define HW_PINCTRL_IRQEN2 0x820
75
76#define HW_PINCTRL_IRQLEVEL0 0x900
77#define HW_PINCTRL_IRQLEVEL1 0x910
78#define HW_PINCTRL_IRQLEVEL2 0x920
79
80#define HW_PINCTRL_IRQPOL0 0xA00
81#define HW_PINCTRL_IRQPOL1 0xA10
82#define HW_PINCTRL_IRQPOL2 0xA20
83
84#define HW_PINCTRL_IRQSTAT0 0xB00
85#define HW_PINCTRL_IRQSTAT1 0xB10
86#define HW_PINCTRL_IRQSTAT2 0xB20
87
88#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-power.h b/arch/arm/mach-stmp37xx/include/mach/regs-power.h
new file mode 100644
index 000000000000..0e733d74a229
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-power.h
@@ -0,0 +1,56 @@
1/*
2 * stmp37xx: POWER register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_POWER
22#define _MACH_REGS_POWER
23
24#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000)
25
26#define HW_POWER_CTRL 0x0
27#define BM_POWER_CTRL_CLKGATE 0x40000000
28
29#define HW_POWER_5VCTRL 0x10
30
31#define HW_POWER_MINPWR 0x20
32
33#define HW_POWER_CHARGE 0x30
34
35#define HW_POWER_VDDDCTRL 0x40
36
37#define HW_POWER_VDDACTRL 0x50
38
39#define HW_POWER_VDDIOCTRL 0x60
40#define BM_POWER_VDDIOCTRL_TRG 0x0000001F
41#define BP_POWER_VDDIOCTRL_TRG 0
42
43#define HW_POWER_STS 0xB0
44#define BM_POWER_STS_VBUSVALID 0x00000002
45#define BM_POWER_STS_BVALID 0x00000004
46#define BM_POWER_STS_AVALID 0x00000008
47#define BM_POWER_STS_DC_OK 0x00000100
48
49#define HW_POWER_RESET 0xE0
50
51#define HW_POWER_DEBUG 0xF0
52#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002
53#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004
54#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
55
56#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h b/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h
new file mode 100644
index 000000000000..15966a1b62e0
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h
@@ -0,0 +1,51 @@
1/*
2 * stmp37xx: PWM register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000)
22
23#define HW_PWM_CTRL 0x0
24#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
25#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020
26
27#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20)
28#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20)
29#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20)
30#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20)
31
32#define HW_PWM_ACTIVEn 0x10
33#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF
34#define BP_PWM_ACTIVEn_ACTIVE 0
35#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
36#define BP_PWM_ACTIVEn_INACTIVE 16
37
38#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20)
39#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20)
40#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20)
41#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20)
42
43#define HW_PWM_PERIODn 0x20
44#define BM_PWM_PERIODn_PERIOD 0x0000FFFF
45#define BP_PWM_PERIODn_PERIOD 0
46#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000
47#define BP_PWM_PERIODn_ACTIVE_STATE 16
48#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000
49#define BP_PWM_PERIODn_INACTIVE_STATE 18
50#define BM_PWM_PERIODn_CDIV 0x00700000
51#define BP_PWM_PERIODn_CDIV 20
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h b/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h
new file mode 100644
index 000000000000..fac40edc38a1
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h
@@ -0,0 +1,57 @@
1/*
2 * stmp37xx: RTC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000)
22#define REGS_RTC_PHYS 0x8005C000
23#define REGS_RTC_SIZE 0x2000
24
25#define HW_RTC_CTRL 0x0
26#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001
27#define BP_RTC_CTRL_ALARM_IRQ_EN 0
28#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
29#define BM_RTC_CTRL_ALARM_IRQ 0x00000004
30#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008
31#define BM_RTC_CTRL_WATCHDOGEN 0x00000010
32
33#define HW_RTC_STAT 0x10
34#define BM_RTC_STAT_NEW_REGS 0x0000FF00
35#define BP_RTC_STAT_NEW_REGS 8
36#define BM_RTC_STAT_STALE_REGS 0x00FF0000
37#define BP_RTC_STAT_STALE_REGS 16
38#define BM_RTC_STAT_RTC_PRESENT 0x80000000
39
40#define HW_RTC_SECONDS 0x30
41
42#define HW_RTC_ALARM 0x40
43
44#define HW_RTC_WATCHDOG 0x50
45
46#define HW_RTC_PERSISTENT0 0x60
47#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002
48#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004
49#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010
50#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020
51#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080
52#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
53#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
54
55#define HW_RTC_PERSISTENT1 0x70
56
57#define HW_RTC_VERSION 0xD0
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h b/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h
new file mode 100644
index 000000000000..cbde891a06c2
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h
@@ -0,0 +1,101 @@
1/*
2 * stmp37xx: SSP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SSP_BASE (STMP3XXX_REGS_BASE + 0x10000)
22#define REGS_SSP1_PHYS 0x80010000
23#define REGS_SSP2_PHYS 0x80034000
24#define REGS_SSP_SIZE 0x2000
25
26#define HW_SSP_CTRL0 0x0
27#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
28#define BP_SSP_CTRL0_XFER_COUNT 0
29#define BM_SSP_CTRL0_ENABLE 0x00010000
30#define BM_SSP_CTRL0_GET_RESP 0x00020000
31#define BM_SSP_CTRL0_LONG_RESP 0x00080000
32#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000
33#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000
34#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000
35#define BP_SSP_CTRL0_BUS_WIDTH 22
36#define BM_SSP_CTRL0_DATA_XFER 0x01000000
37#define BM_SSP_CTRL0_READ 0x02000000
38#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
39#define BM_SSP_CTRL0_LOCK_CS 0x08000000
40#define BM_SSP_CTRL0_RUN 0x20000000
41#define BM_SSP_CTRL0_CLKGATE 0x40000000
42#define BM_SSP_CTRL0_SFTRST 0x80000000
43
44#define HW_SSP_CMD0 0x10
45#define BM_SSP_CMD0_CMD 0x000000FF
46#define BP_SSP_CMD0_CMD 0
47#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
48#define BP_SSP_CMD0_BLOCK_COUNT 8
49#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000
50#define BP_SSP_CMD0_BLOCK_SIZE 16
51#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
52#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF
53#define BP_SSP_CMD1_CMD_ARG 0
54
55#define HW_SSP_TIMING 0x50
56#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF
57#define BP_SSP_TIMING_CLOCK_RATE 0
58#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00
59#define BP_SSP_TIMING_CLOCK_DIVIDE 8
60#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000
61#define BP_SSP_TIMING_TIMEOUT 16
62
63#define HW_SSP_CTRL1 0x60
64#define BM_SSP_CTRL1_SSP_MODE 0x0000000F
65#define BP_SSP_CTRL1_SSP_MODE 0
66#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0
67#define BP_SSP_CTRL1_WORD_LENGTH 4
68#define BM_SSP_CTRL1_POLARITY 0x00000200
69#define BM_SSP_CTRL1_PHASE 0x00000400
70#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
71#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000
72#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000
73#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000
74#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000
75#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000
76#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000
77#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000
78#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000
79#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000
80#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000
81#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
82#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
83#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
84
85#define HW_SSP_DATA 0x70
86
87#define HW_SSP_SDRESP0 0x80
88
89#define HW_SSP_SDRESP1 0x90
90
91#define HW_SSP_SDRESP2 0xA0
92
93#define HW_SSP_SDRESP3 0xB0
94
95#define HW_SSP_STATUS 0xC0
96#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020
97#define BM_SSP_STATUS_TIMEOUT 0x00001000
98#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000
99#define BM_SSP_STATUS_RESP_ERR 0x00008000
100#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000
101#define BM_SSP_STATUS_CARD_DETECT 0x10000000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h b/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h
new file mode 100644
index 000000000000..4af0f6edfa78
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h
@@ -0,0 +1,49 @@
1/*
2 * stmp37xx: TIMROT register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_TIMROT
22#define _MACH_REGS_TIMROT
23
24#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000)
25
26#define HW_TIMROT_ROTCTRL 0x0
27#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
28#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
29
30#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20)
31#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20)
32#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20)
33
34#define HW_TIMROT_TIMCTRLn 0x20
35#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
36#define BP_TIMROT_TIMCTRLn_SELECT 0
37#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
38#define BP_TIMROT_TIMCTRLn_PRESCALE 4
39#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
40#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
41#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
42#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
43
44#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20)
45#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20)
46#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20)
47
48#define HW_TIMROT_TIMCOUNTn 0x30
49#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h b/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h
new file mode 100644
index 000000000000..0594275d860c
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h
@@ -0,0 +1,85 @@
1/*
2 * stmp37xx: UARTAPP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_UARTAPP_BASE (STMP3XXX_REGS_BASE + 0x6C000)
22#define REGS_UARTAPP1_PHYS 0x8006C000
23#define REGS_UARTAPP_SIZE 0x2000
24
25#define HW_UARTAPP_CTRL0 0x0
26#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_UARTAPP_CTRL0_XFER_COUNT 0
28#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000
29#define BP_UARTAPP_CTRL0_RXTIMEOUT 16
30#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000
31#define BM_UARTAPP_CTRL0_RUN 0x20000000
32#define BM_UARTAPP_CTRL0_SFTRST 0x80000000
33#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF
34#define BP_UARTAPP_CTRL1_XFER_COUNT 0
35#define BM_UARTAPP_CTRL1_RUN 0x10000000
36
37#define HW_UARTAPP_CTRL2 0x20
38#define BM_UARTAPP_CTRL2_UARTEN 0x00000001
39#define BP_UARTAPP_CTRL2_UARTEN 0
40#define BM_UARTAPP_CTRL2_TXE 0x00000100
41#define BM_UARTAPP_CTRL2_RXE 0x00000200
42#define BM_UARTAPP_CTRL2_RTS 0x00000800
43#define BM_UARTAPP_CTRL2_RTSEN 0x00004000
44#define BM_UARTAPP_CTRL2_CTSEN 0x00008000
45#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000
46#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000
47#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000
48
49#define HW_UARTAPP_LINECTRL 0x30
50#define BM_UARTAPP_LINECTRL_BRK 0x00000001
51#define BP_UARTAPP_LINECTRL_BRK 0
52#define BM_UARTAPP_LINECTRL_PEN 0x00000002
53#define BM_UARTAPP_LINECTRL_EPS 0x00000004
54#define BM_UARTAPP_LINECTRL_STP2 0x00000008
55#define BM_UARTAPP_LINECTRL_FEN 0x00000010
56#define BM_UARTAPP_LINECTRL_WLEN 0x00000060
57#define BP_UARTAPP_LINECTRL_WLEN 5
58#define BM_UARTAPP_LINECTRL_SPS 0x00000080
59#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00
60#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8
61#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000
62#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16
63
64#define HW_UARTAPP_INTR 0x50
65#define BM_UARTAPP_INTR_CTSMIS 0x00000002
66#define BM_UARTAPP_INTR_RTIS 0x00000040
67#define BM_UARTAPP_INTR_CTSMIEN 0x00020000
68#define BM_UARTAPP_INTR_RXIEN 0x00100000
69#define BM_UARTAPP_INTR_RTIEN 0x00400000
70
71#define HW_UARTAPP_DATA 0x60
72
73#define HW_UARTAPP_STAT 0x70
74#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF
75#define BP_UARTAPP_STAT_RXCOUNT 0
76#define BM_UARTAPP_STAT_FERR 0x00010000
77#define BM_UARTAPP_STAT_PERR 0x00020000
78#define BM_UARTAPP_STAT_BERR 0x00040000
79#define BM_UARTAPP_STAT_OERR 0x00080000
80#define BM_UARTAPP_STAT_RXFE 0x01000000
81#define BM_UARTAPP_STAT_TXFF 0x02000000
82#define BM_UARTAPP_STAT_TXFE 0x08000000
83#define BM_UARTAPP_STAT_CTS 0x10000000
84
85#define HW_UARTAPP_VERSION 0x90
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h
new file mode 100644
index 000000000000..b810deb552a9
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h
@@ -0,0 +1,268 @@
1/*
2 * stmp378x: UARTDBG register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000)
22#define REGS_UARTDBG_PHYS 0x80070000
23#define REGS_UARTDBG_SIZE 0x2000
24
25#define HW_UARTDBGDR 0x00000000
26#define BP_UARTDBGDR_UNAVAILABLE 16
27#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
28#define BF_UARTDBGDR_UNAVAILABLE(v) \
29 (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
30#define BP_UARTDBGDR_RESERVED 12
31#define BM_UARTDBGDR_RESERVED 0x0000F000
32#define BF_UARTDBGDR_RESERVED(v) \
33 (((v) << 12) & BM_UARTDBGDR_RESERVED)
34#define BM_UARTDBGDR_OE 0x00000800
35#define BM_UARTDBGDR_BE 0x00000400
36#define BM_UARTDBGDR_PE 0x00000200
37#define BM_UARTDBGDR_FE 0x00000100
38#define BP_UARTDBGDR_DATA 0
39#define BM_UARTDBGDR_DATA 0x000000FF
40#define BF_UARTDBGDR_DATA(v) \
41 (((v) << 0) & BM_UARTDBGDR_DATA)
42#define HW_UARTDBGRSR_ECR 0x00000004
43#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
44#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
45#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
46 (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
47#define BP_UARTDBGRSR_ECR_EC 4
48#define BM_UARTDBGRSR_ECR_EC 0x000000F0
49#define BF_UARTDBGRSR_ECR_EC(v) \
50 (((v) << 4) & BM_UARTDBGRSR_ECR_EC)
51#define BM_UARTDBGRSR_ECR_OE 0x00000008
52#define BM_UARTDBGRSR_ECR_BE 0x00000004
53#define BM_UARTDBGRSR_ECR_PE 0x00000002
54#define BM_UARTDBGRSR_ECR_FE 0x00000001
55#define HW_UARTDBGFR 0x00000018
56#define BP_UARTDBGFR_UNAVAILABLE 16
57#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
58#define BF_UARTDBGFR_UNAVAILABLE(v) \
59 (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
60#define BP_UARTDBGFR_RESERVED 9
61#define BM_UARTDBGFR_RESERVED 0x0000FE00
62#define BF_UARTDBGFR_RESERVED(v) \
63 (((v) << 9) & BM_UARTDBGFR_RESERVED)
64#define BM_UARTDBGFR_RI 0x00000100
65#define BM_UARTDBGFR_TXFE 0x00000080
66#define BM_UARTDBGFR_RXFF 0x00000040
67#define BM_UARTDBGFR_TXFF 0x00000020
68#define BM_UARTDBGFR_RXFE 0x00000010
69#define BM_UARTDBGFR_BUSY 0x00000008
70#define BM_UARTDBGFR_DCD 0x00000004
71#define BM_UARTDBGFR_DSR 0x00000002
72#define BM_UARTDBGFR_CTS 0x00000001
73#define HW_UARTDBGILPR 0x00000020
74#define BP_UARTDBGILPR_UNAVAILABLE 8
75#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
76#define BF_UARTDBGILPR_UNAVAILABLE(v) \
77 (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
78#define BP_UARTDBGILPR_ILPDVSR 0
79#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
80#define BF_UARTDBGILPR_ILPDVSR(v) \
81 (((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
82#define HW_UARTDBGIBRD 0x00000024
83#define BP_UARTDBGIBRD_UNAVAILABLE 16
84#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
85#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
86 (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
87#define BP_UARTDBGIBRD_BAUD_DIVINT 0
88#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
89#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
90 (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
91#define HW_UARTDBGFBRD 0x00000028
92#define BP_UARTDBGFBRD_UNAVAILABLE 8
93#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
94#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
95 (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
96#define BP_UARTDBGFBRD_RESERVED 6
97#define BM_UARTDBGFBRD_RESERVED 0x000000C0
98#define BF_UARTDBGFBRD_RESERVED(v) \
99 (((v) << 6) & BM_UARTDBGFBRD_RESERVED)
100#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
101#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
102#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
103 (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
104#define HW_UARTDBGLCR_H 0x0000002c
105#define BP_UARTDBGLCR_H_UNAVAILABLE 16
106#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
107#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
108 (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
109#define BP_UARTDBGLCR_H_RESERVED 8
110#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
111#define BF_UARTDBGLCR_H_RESERVED(v) \
112 (((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
113#define BM_UARTDBGLCR_H_SPS 0x00000080
114#define BP_UARTDBGLCR_H_WLEN 5
115#define BM_UARTDBGLCR_H_WLEN 0x00000060
116#define BF_UARTDBGLCR_H_WLEN(v) \
117 (((v) << 5) & BM_UARTDBGLCR_H_WLEN)
118#define BM_UARTDBGLCR_H_FEN 0x00000010
119#define BM_UARTDBGLCR_H_STP2 0x00000008
120#define BM_UARTDBGLCR_H_EPS 0x00000004
121#define BM_UARTDBGLCR_H_PEN 0x00000002
122#define BM_UARTDBGLCR_H_BRK 0x00000001
123#define HW_UARTDBGCR 0x00000030
124#define BP_UARTDBGCR_UNAVAILABLE 16
125#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
126#define BF_UARTDBGCR_UNAVAILABLE(v) \
127 (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
128#define BM_UARTDBGCR_CTSEN 0x00008000
129#define BM_UARTDBGCR_RTSEN 0x00004000
130#define BM_UARTDBGCR_OUT2 0x00002000
131#define BM_UARTDBGCR_OUT1 0x00001000
132#define BM_UARTDBGCR_RTS 0x00000800
133#define BM_UARTDBGCR_DTR 0x00000400
134#define BM_UARTDBGCR_RXE 0x00000200
135#define BM_UARTDBGCR_TXE 0x00000100
136#define BM_UARTDBGCR_LBE 0x00000080
137#define BP_UARTDBGCR_RESERVED 3
138#define BM_UARTDBGCR_RESERVED 0x00000078
139#define BF_UARTDBGCR_RESERVED(v) \
140 (((v) << 3) & BM_UARTDBGCR_RESERVED)
141#define BM_UARTDBGCR_SIRLP 0x00000004
142#define BM_UARTDBGCR_SIREN 0x00000002
143#define BM_UARTDBGCR_UARTEN 0x00000001
144#define HW_UARTDBGIFLS 0x00000034
145#define BP_UARTDBGIFLS_UNAVAILABLE 16
146#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
147#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
148 (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
149#define BP_UARTDBGIFLS_RESERVED 6
150#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
151#define BF_UARTDBGIFLS_RESERVED(v) \
152 (((v) << 6) & BM_UARTDBGIFLS_RESERVED)
153#define BP_UARTDBGIFLS_RXIFLSEL 3
154#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
155#define BF_UARTDBGIFLS_RXIFLSEL(v) \
156 (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
157#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0
158#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
159#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
160#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
161#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
162#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
163#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
164#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
165#define BP_UARTDBGIFLS_TXIFLSEL 0
166#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
167#define BF_UARTDBGIFLS_TXIFLSEL(v) \
168 (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
169#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0
170#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
171#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
172#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
173#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
174#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
175#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
176#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
177#define HW_UARTDBGIMSC 0x00000038
178#define BP_UARTDBGIMSC_UNAVAILABLE 16
179#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
180#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
181 (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
182#define BP_UARTDBGIMSC_RESERVED 11
183#define BM_UARTDBGIMSC_RESERVED 0x0000F800
184#define BF_UARTDBGIMSC_RESERVED(v) \
185 (((v) << 11) & BM_UARTDBGIMSC_RESERVED)
186#define BM_UARTDBGIMSC_OEIM 0x00000400
187#define BM_UARTDBGIMSC_BEIM 0x00000200
188#define BM_UARTDBGIMSC_PEIM 0x00000100
189#define BM_UARTDBGIMSC_FEIM 0x00000080
190#define BM_UARTDBGIMSC_RTIM 0x00000040
191#define BM_UARTDBGIMSC_TXIM 0x00000020
192#define BM_UARTDBGIMSC_RXIM 0x00000010
193#define BM_UARTDBGIMSC_DSRMIM 0x00000008
194#define BM_UARTDBGIMSC_DCDMIM 0x00000004
195#define BM_UARTDBGIMSC_CTSMIM 0x00000002
196#define BM_UARTDBGIMSC_RIMIM 0x00000001
197#define HW_UARTDBGRIS 0x0000003c
198#define BP_UARTDBGRIS_UNAVAILABLE 16
199#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
200#define BF_UARTDBGRIS_UNAVAILABLE(v) \
201 (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
202#define BP_UARTDBGRIS_RESERVED 11
203#define BM_UARTDBGRIS_RESERVED 0x0000F800
204#define BF_UARTDBGRIS_RESERVED(v) \
205 (((v) << 11) & BM_UARTDBGRIS_RESERVED)
206#define BM_UARTDBGRIS_OERIS 0x00000400
207#define BM_UARTDBGRIS_BERIS 0x00000200
208#define BM_UARTDBGRIS_PERIS 0x00000100
209#define BM_UARTDBGRIS_FERIS 0x00000080
210#define BM_UARTDBGRIS_RTRIS 0x00000040
211#define BM_UARTDBGRIS_TXRIS 0x00000020
212#define BM_UARTDBGRIS_RXRIS 0x00000010
213#define BM_UARTDBGRIS_DSRRMIS 0x00000008
214#define BM_UARTDBGRIS_DCDRMIS 0x00000004
215#define BM_UARTDBGRIS_CTSRMIS 0x00000002
216#define BM_UARTDBGRIS_RIRMIS 0x00000001
217#define HW_UARTDBGMIS 0x00000040
218#define BP_UARTDBGMIS_UNAVAILABLE 16
219#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
220#define BF_UARTDBGMIS_UNAVAILABLE(v) \
221 (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
222#define BP_UARTDBGMIS_RESERVED 11
223#define BM_UARTDBGMIS_RESERVED 0x0000F800
224#define BF_UARTDBGMIS_RESERVED(v) \
225 (((v) << 11) & BM_UARTDBGMIS_RESERVED)
226#define BM_UARTDBGMIS_OEMIS 0x00000400
227#define BM_UARTDBGMIS_BEMIS 0x00000200
228#define BM_UARTDBGMIS_PEMIS 0x00000100
229#define BM_UARTDBGMIS_FEMIS 0x00000080
230#define BM_UARTDBGMIS_RTMIS 0x00000040
231#define BM_UARTDBGMIS_TXMIS 0x00000020
232#define BM_UARTDBGMIS_RXMIS 0x00000010
233#define BM_UARTDBGMIS_DSRMMIS 0x00000008
234#define BM_UARTDBGMIS_DCDMMIS 0x00000004
235#define BM_UARTDBGMIS_CTSMMIS 0x00000002
236#define BM_UARTDBGMIS_RIMMIS 0x00000001
237#define HW_UARTDBGICR 0x00000044
238#define BP_UARTDBGICR_UNAVAILABLE 16
239#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
240#define BF_UARTDBGICR_UNAVAILABLE(v) \
241 (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
242#define BP_UARTDBGICR_RESERVED 11
243#define BM_UARTDBGICR_RESERVED 0x0000F800
244#define BF_UARTDBGICR_RESERVED(v) \
245 (((v) << 11) & BM_UARTDBGICR_RESERVED)
246#define BM_UARTDBGICR_OEIC 0x00000400
247#define BM_UARTDBGICR_BEIC 0x00000200
248#define BM_UARTDBGICR_PEIC 0x00000100
249#define BM_UARTDBGICR_FEIC 0x00000080
250#define BM_UARTDBGICR_RTIC 0x00000040
251#define BM_UARTDBGICR_TXIC 0x00000020
252#define BM_UARTDBGICR_RXIC 0x00000010
253#define BM_UARTDBGICR_DSRMIC 0x00000008
254#define BM_UARTDBGICR_DCDMIC 0x00000004
255#define BM_UARTDBGICR_CTSMIC 0x00000002
256#define BM_UARTDBGICR_RIMIC 0x00000001
257#define HW_UARTDBGDMACR 0x00000048
258#define BP_UARTDBGDMACR_UNAVAILABLE 16
259#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
260#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
261 (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
262#define BP_UARTDBGDMACR_RESERVED 3
263#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
264#define BF_UARTDBGDMACR_RESERVED(v) \
265 (((v) << 3) & BM_UARTDBGDMACR_RESERVED)
266#define BM_UARTDBGDMACR_DMAONERR 0x00000004
267#define BM_UARTDBGDMACR_TXDMAE 0x00000002
268#define BM_UARTDBGDMACR_RXDMAE 0x00000001
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h
new file mode 100644
index 000000000000..9145e22df32c
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h
@@ -0,0 +1,22 @@
1/*
2 * stmp37xx: USBCTL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBCTL_BASE (STMP3XXX_REGS_BASE + 0x80000)
22#define REGS_USBCTL_PHYS 0x80000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h
new file mode 100644
index 000000000000..1a2ae9cbdfed
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h
@@ -0,0 +1,22 @@
1/*
2 * stmp37xx: USBCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000)
22#define REGS_USBCTRL_PHYS 0x80080000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h
new file mode 100644
index 000000000000..b7fce0fbc560
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h
@@ -0,0 +1,37 @@
1/*
2 * stmp37xx: USBPHY register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000)
22
23#define HW_USBPHY_PWD 0x0
24
25#define HW_USBPHY_CTRL 0x30
26#define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT 0x00000001
27#define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT 0
28#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002
29#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010
30#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080
31#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800
32#define BM_USBPHY_CTRL_CLKGATE 0x40000000
33#define BM_USBPHY_CTRL_SFTRST 0x80000000
34
35#define HW_USBPHY_STATUS 0x40
36#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040
37#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100
diff --git a/arch/arm/mach-stmp37xx/stmp37xx.c b/arch/arm/mach-stmp37xx/stmp37xx.c
new file mode 100644
index 000000000000..8c7d6fb191a3
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/stmp37xx.c
@@ -0,0 +1,219 @@
1/*
2 * Freescale STMP37XX platform support
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/device.h>
22#include <linux/platform_device.h>
23#include <linux/irq.h>
24#include <linux/io.h>
25
26#include <asm/setup.h>
27#include <asm/mach-types.h>
28
29#include <asm/mach/arch.h>
30#include <asm/mach/irq.h>
31#include <asm/mach/map.h>
32#include <asm/mach/time.h>
33
34#include <mach/stmp3xxx.h>
35#include <mach/dma.h>
36
37#include <mach/platform.h>
38#include <mach/regs-icoll.h>
39#include <mach/regs-apbh.h>
40#include <mach/regs-apbx.h>
41#include "stmp37xx.h"
42
43/*
44 * IRQ handling
45 */
46static void stmp37xx_ack_irq(unsigned int irq)
47{
48 /* Disable IRQ */
49 stmp3xxx_clearl(0x04 << ((irq % 4) * 8),
50 REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
51
52 /* ACK current interrupt */
53 __raw_writel(1, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
54
55 /* Barrier */
56 (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
57}
58
59static void stmp37xx_mask_irq(unsigned int irq)
60{
61 /* IRQ disable */
62 stmp3xxx_clearl(0x04 << ((irq % 4) * 8),
63 REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
64}
65
66static void stmp37xx_unmask_irq(unsigned int irq)
67{
68 /* IRQ enable */
69 stmp3xxx_setl(0x04 << ((irq % 4) * 8),
70 REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + irq / 4 * 0x10);
71}
72
73static struct irq_chip stmp37xx_chip = {
74 .ack = stmp37xx_ack_irq,
75 .mask = stmp37xx_mask_irq,
76 .unmask = stmp37xx_unmask_irq,
77};
78
79void __init stmp37xx_init_irq(void)
80{
81 stmp3xxx_init_irq(&stmp37xx_chip);
82}
83
84/*
85 * DMA interrupt handling
86 */
87void stmp3xxx_arch_dma_enable_interrupt(int channel)
88{
89 switch (STMP3XXX_DMA_BUS(channel)) {
90 case STMP3XXX_BUS_APBH:
91 stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
92 REGS_APBH_BASE + HW_APBH_CTRL1);
93 break;
94
95 case STMP3XXX_BUS_APBX:
96 stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
97 REGS_APBX_BASE + HW_APBX_CTRL1);
98 break;
99 }
100}
101EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
102
103void stmp3xxx_arch_dma_clear_interrupt(int channel)
104{
105 switch (STMP3XXX_DMA_BUS(channel)) {
106 case STMP3XXX_BUS_APBH:
107 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
108 REGS_APBH_BASE + HW_APBH_CTRL1);
109 break;
110
111 case STMP3XXX_BUS_APBX:
112 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
113 REGS_APBX_BASE + HW_APBX_CTRL1);
114 break;
115 }
116}
117EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
118
119int stmp3xxx_arch_dma_is_interrupt(int channel)
120{
121 int r = 0;
122
123 switch (STMP3XXX_DMA_BUS(channel)) {
124 case STMP3XXX_BUS_APBH:
125 r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
126 (1 << STMP3XXX_DMA_CHANNEL(channel));
127 break;
128
129 case STMP3XXX_BUS_APBX:
130 r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
131 (1 << STMP3XXX_DMA_CHANNEL(channel));
132 break;
133 }
134 return r;
135}
136EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
137
138void stmp3xxx_arch_dma_reset_channel(int channel)
139{
140 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
141
142 switch (STMP3XXX_DMA_BUS(channel)) {
143 case STMP3XXX_BUS_APBH:
144 /* Reset channel and wait for it to complete */
145 stmp3xxx_setl(chbit << BP_APBH_CTRL0_RESET_CHANNEL,
146 REGS_APBH_BASE + HW_APBH_CTRL0);
147 while (__raw_readl(REGS_APBH_BASE + HW_APBH_CTRL0) &
148 (chbit << BP_APBH_CTRL0_RESET_CHANNEL))
149 cpu_relax();
150 break;
151
152 case STMP3XXX_BUS_APBX:
153 stmp3xxx_setl(chbit << BP_APBX_CTRL0_RESET_CHANNEL,
154 REGS_APBX_BASE + HW_APBX_CTRL0);
155 while (__raw_readl(REGS_APBX_BASE + HW_APBX_CTRL0) &
156 (chbit << BP_APBX_CTRL0_RESET_CHANNEL))
157 cpu_relax();
158 break;
159 }
160}
161EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
162
163void stmp3xxx_arch_dma_freeze(int channel)
164{
165 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
166
167 switch (STMP3XXX_DMA_BUS(channel)) {
168 case STMP3XXX_BUS_APBH:
169 stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
170 break;
171 case STMP3XXX_BUS_APBX:
172 stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
173 break;
174 }
175}
176EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
177
178void stmp3xxx_arch_dma_unfreeze(int channel)
179{
180 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
181
182 switch (STMP3XXX_DMA_BUS(channel)) {
183 case STMP3XXX_BUS_APBH:
184 stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
185 break;
186 case STMP3XXX_BUS_APBX:
187 stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
188 break;
189 }
190}
191EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
192
193/*
194 * The registers are all very closely mapped, so we might as well map them all
195 * with a single mapping
196 *
197 * Logical Physical
198 * f0000000 80000000 On-chip registers
199 * f1000000 00000000 32k on-chip SRAM
200 */
201static struct map_desc stmp37xx_io_desc[] __initdata = {
202 {
203 .virtual = (u32)STMP3XXX_REGS_BASE,
204 .pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE),
205 .length = SZ_1M,
206 .type = MT_DEVICE
207 },
208 {
209 .virtual = (u32)STMP3XXX_OCRAM_BASE,
210 .pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE),
211 .length = STMP3XXX_OCRAM_SIZE,
212 .type = MT_DEVICE,
213 },
214};
215
216void __init stmp37xx_map_io(void)
217{
218 iotable_init(stmp37xx_io_desc, ARRAY_SIZE(stmp37xx_io_desc));
219}
diff --git a/arch/arm/mach-stmp37xx/stmp37xx.h b/arch/arm/mach-stmp37xx/stmp37xx.h
new file mode 100644
index 000000000000..0b75fb796a64
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/stmp37xx.h
@@ -0,0 +1,24 @@
1/*
2 * Freescale STMP37XX/STMP378X internal functions and data declarations
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __MACH_STMP37XX_H
19#define __MACH_STMP37XX_H
20
21void stmp37xx_map_io(void);
22void stmp37xx_init_irq(void);
23
24#endif /* __MACH_STMP37XX_H */
diff --git a/arch/arm/mach-stmp37xx/stmp37xx_devb.c b/arch/arm/mach-stmp37xx/stmp37xx_devb.c
new file mode 100644
index 000000000000..394f21ab59e6
--- /dev/null
+++ b/arch/arm/mach-stmp37xx/stmp37xx_devb.c
@@ -0,0 +1,101 @@
1/*
2 * Freescale STMP37XX development board support
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/device.h>
21#include <linux/platform_device.h>
22#include <asm/setup.h>
23#include <asm/mach-types.h>
24#include <asm/mach/arch.h>
25
26#include <mach/stmp3xxx.h>
27#include <mach/pins.h>
28#include <mach/pinmux.h>
29#include "stmp37xx.h"
30
31/*
32 * List of STMP37xx development board specific devices
33 */
34static struct platform_device *stmp37xx_devb_devices[] = {
35 &stmp3xxx_dbguart,
36 &stmp3xxx_appuart,
37};
38
39static struct pin_desc dbguart_pins_0[] = {
40 { PINID_PWM0, PIN_FUN3, },
41 { PINID_PWM1, PIN_FUN3, },
42};
43
44struct pin_desc appuart_pins_0[] = {
45 { PINID_UART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
46 { PINID_UART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
47 { PINID_UART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
48 { PINID_UART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
49};
50
51static struct pin_group appuart_pins[] = {
52 [0] = {
53 .pins = appuart_pins_0,
54 .nr_pins = ARRAY_SIZE(appuart_pins_0),
55 },
56 /* 37xx has the only app uart */
57};
58
59static struct pin_group dbguart_pins[] = {
60 [0] = {
61 .pins = dbguart_pins_0,
62 .nr_pins = ARRAY_SIZE(dbguart_pins_0),
63 },
64};
65
66static int dbguart_pins_control(int id, int request)
67{
68 int r = 0;
69
70 if (request)
71 r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart");
72 else
73 stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart");
74 return r;
75}
76
77
78static void __init stmp37xx_devb_init(void)
79{
80 stmp3xxx_pinmux_init(NR_REAL_IRQS);
81
82 /* Init STMP3xxx platform */
83 stmp3xxx_init();
84
85 stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control;
86 stmp3xxx_appuart.dev.platform_data = appuart_pins;
87
88 /* Add STMP37xx development board devices */
89 platform_add_devices(stmp37xx_devb_devices,
90 ARRAY_SIZE(stmp37xx_devb_devices));
91}
92
93MACHINE_START(STMP37XX, "STMP37XX")
94 .phys_io = 0x80000000,
95 .io_pg_offst = ((0xf0000000) >> 18) & 0xfffc,
96 .boot_params = 0x40000100,
97 .map_io = stmp37xx_map_io,
98 .init_irq = stmp37xx_init_irq,
99 .timer = &stmp3xxx_timer,
100 .init_machine = stmp37xx_devb_init,
101MACHINE_END
diff --git a/arch/arm/plat-stmp3xxx/Kconfig b/arch/arm/plat-stmp3xxx/Kconfig
new file mode 100644
index 000000000000..2cf37c35951b
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/Kconfig
@@ -0,0 +1,37 @@
1if ARCH_STMP3XXX
2
3menu "Freescale STMP3xxx implementations"
4
5choice
6 prompt "Select STMP3xxx chip family"
7
8config ARCH_STMP37XX
9 bool "Freescale SMTP37xx"
10 select CPU_ARM926T
11 ---help---
12 STMP37xx refers to 3700 through 3769 chips
13
14config ARCH_STMP378X
15 bool "Freescale STMP378x"
16 select CPU_ARM926T
17 ---help---
18 STMP378x refers to 3780 through 3789 chips
19
20endchoice
21
22choice
23 prompt "Select STMP3xxx board type"
24
25config MACH_STMP37XX
26 depends on ARCH_STMP37XX
27 bool "Freescale STMP37xx development board"
28
29config MACH_STMP378X
30 depends on ARCH_STMP378X
31 bool "Freescale STMP378x development board"
32
33endchoice
34
35endmenu
36
37endif
diff --git a/arch/arm/plat-stmp3xxx/Makefile b/arch/arm/plat-stmp3xxx/Makefile
new file mode 100644
index 000000000000..31dd518f37a5
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the linux kernel.
3#
4# Object file lists.
5obj-y += core.o timer.o irq.o dma.o clock.o pinmux.o devices.o
diff --git a/arch/arm/plat-stmp3xxx/clock.c b/arch/arm/plat-stmp3xxx/clock.c
new file mode 100644
index 000000000000..5d2f19a09e44
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/clock.c
@@ -0,0 +1,1135 @@
1/*
2 * Clock manipulation routines for Freescale STMP37XX/STMP378X
3 *
4 * Author: Vitaly Wool <vital@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#define DEBUG
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/clk.h>
23#include <linux/spinlock.h>
24#include <linux/errno.h>
25#include <linux/err.h>
26#include <linux/delay.h>
27#include <linux/io.h>
28
29#include <asm/mach-types.h>
30#include <asm/clkdev.h>
31#include <mach/platform.h>
32#include <mach/regs-clkctrl.h>
33
34#include "clock.h"
35
36static DEFINE_SPINLOCK(clocks_lock);
37
38static struct clk osc_24M;
39static struct clk pll_clk;
40static struct clk cpu_clk;
41static struct clk hclk;
42
43static int propagate_rate(struct clk *);
44
45static inline int clk_is_busy(struct clk *clk)
46{
47 return __raw_readl(clk->busy_reg) & (1 << clk->busy_bit);
48}
49
50static inline int clk_good(struct clk *clk)
51{
52 return clk && !IS_ERR(clk) && clk->ops;
53}
54
55static int std_clk_enable(struct clk *clk)
56{
57 if (clk->enable_reg) {
58 u32 clk_reg = __raw_readl(clk->enable_reg);
59 if (clk->enable_negate)
60 clk_reg &= ~(1 << clk->enable_shift);
61 else
62 clk_reg |= (1 << clk->enable_shift);
63 __raw_writel(clk_reg, clk->enable_reg);
64 if (clk->enable_wait)
65 udelay(clk->enable_wait);
66 return 0;
67 } else
68 return -EINVAL;
69}
70
71static int std_clk_disable(struct clk *clk)
72{
73 if (clk->enable_reg) {
74 u32 clk_reg = __raw_readl(clk->enable_reg);
75 if (clk->enable_negate)
76 clk_reg |= (1 << clk->enable_shift);
77 else
78 clk_reg &= ~(1 << clk->enable_shift);
79 __raw_writel(clk_reg, clk->enable_reg);
80 return 0;
81 } else
82 return -EINVAL;
83}
84
85static int io_set_rate(struct clk *clk, u32 rate)
86{
87 u32 reg_frac, clkctrl_frac;
88 int i, ret = 0, mask = 0x1f;
89
90 clkctrl_frac = (clk->parent->rate * 18 + rate - 1) / rate;
91
92 if (clkctrl_frac < 18 || clkctrl_frac > 35) {
93 ret = -EINVAL;
94 goto out;
95 }
96
97 reg_frac = __raw_readl(clk->scale_reg);
98 reg_frac &= ~(mask << clk->scale_shift);
99 __raw_writel(reg_frac | (clkctrl_frac << clk->scale_shift),
100 clk->scale_reg);
101 if (clk->busy_reg) {
102 for (i = 10000; i; i--)
103 if (!clk_is_busy(clk))
104 break;
105 if (!i)
106 ret = -ETIMEDOUT;
107 else
108 ret = 0;
109 }
110out:
111 return ret;
112}
113
114static long io_get_rate(struct clk *clk)
115{
116 long rate = clk->parent->rate * 18;
117 int mask = 0x1f;
118
119 rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
120 clk->rate = rate;
121
122 return rate;
123}
124
125static long per_get_rate(struct clk *clk)
126{
127 long rate = clk->parent->rate;
128 long div;
129 const int mask = 0xff;
130
131 if (clk->enable_reg &&
132 !(__raw_readl(clk->enable_reg) & clk->enable_shift))
133 clk->rate = 0;
134 else {
135 div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
136 if (div)
137 rate /= div;
138 clk->rate = rate;
139 }
140
141 return clk->rate;
142}
143
144static int per_set_rate(struct clk *clk, u32 rate)
145{
146 int ret = -EINVAL;
147 int div = (clk->parent->rate + rate - 1) / rate;
148 u32 reg_frac;
149 const int mask = 0xff;
150 int try = 10;
151 int i = -1;
152
153 if (div == 0 || div > mask)
154 goto out;
155
156 reg_frac = __raw_readl(clk->scale_reg);
157 reg_frac &= ~(mask << clk->scale_shift);
158
159 while (try--) {
160 __raw_writel(reg_frac | (div << clk->scale_shift),
161 clk->scale_reg);
162
163 if (clk->busy_reg) {
164 for (i = 10000; i; i--)
165 if (!clk_is_busy(clk))
166 break;
167 }
168 if (i)
169 break;
170 }
171
172 if (!i)
173 ret = -ETIMEDOUT;
174 else
175 ret = 0;
176
177out:
178 if (ret != 0)
179 printk(KERN_ERR "%s: error %d\n", __func__, ret);
180 return ret;
181}
182
183static long lcdif_get_rate(struct clk *clk)
184{
185 long rate = clk->parent->rate;
186 long div;
187 const int mask = 0xff;
188
189 div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
190 if (div) {
191 rate /= div;
192 div = (__raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC) &
193 BM_CLKCTRL_FRAC_PIXFRAC) >> BP_CLKCTRL_FRAC_PIXFRAC;
194 rate /= div;
195 }
196 clk->rate = rate;
197
198 return rate;
199}
200
201static int lcdif_set_rate(struct clk *clk, u32 rate)
202{
203 int ret = 0;
204 /*
205 * On 3700, we can get most timings exact by modifying ref_pix
206 * and the divider, but keeping the phase timings at 1 (2
207 * phases per cycle).
208 *
209 * ref_pix can be between 480e6*18/35=246.9MHz and 480e6*18/18=480MHz,
210 * which is between 18/(18*480e6)=2.084ns and 35/(18*480e6)=4.050ns.
211 *
212 * ns_cycle >= 2*18e3/(18*480) = 25/6
213 * ns_cycle <= 2*35e3/(18*480) = 875/108
214 *
215 * Multiply the ns_cycle by 'div' to lengthen it until it fits the
216 * bounds. This is the divider we'll use after ref_pix.
217 *
218 * 6 * ns_cycle >= 25 * div
219 * 108 * ns_cycle <= 875 * div
220 */
221 u32 ns_cycle = 1000000 / rate;
222 u32 div, reg_val;
223 u32 lowest_result = (u32) -1;
224 u32 lowest_div = 0, lowest_fracdiv = 0;
225
226 for (div = 1; div < 256; ++div) {
227 u32 fracdiv;
228 u32 ps_result;
229 int lower_bound = 6 * ns_cycle >= 25 * div;
230 int upper_bound = 108 * ns_cycle <= 875 * div;
231 if (!lower_bound)
232 break;
233 if (!upper_bound)
234 continue;
235 /*
236 * Found a matching div. Calculate fractional divider needed,
237 * rounded up.
238 */
239 fracdiv = ((clk->parent->rate / 1000 * 18 / 2) *
240 ns_cycle + 1000 * div - 1) /
241 (1000 * div);
242 if (fracdiv < 18 || fracdiv > 35) {
243 ret = -EINVAL;
244 goto out;
245 }
246 /* Calculate the actual cycle time this results in */
247 ps_result = 6250 * div * fracdiv / 27;
248
249 /* Use the fastest result that doesn't break ns_cycle */
250 if (ps_result <= lowest_result) {
251 lowest_result = ps_result;
252 lowest_div = div;
253 lowest_fracdiv = fracdiv;
254 }
255 }
256
257 if (div >= 256 || lowest_result == (u32) -1) {
258 ret = -EINVAL;
259 goto out;
260 }
261 pr_debug("Programming PFD=%u,DIV=%u ref_pix=%uMHz "
262 "PIXCLK=%uMHz cycle=%u.%03uns\n",
263 lowest_fracdiv, lowest_div,
264 480*18/lowest_fracdiv, 480*18/lowest_fracdiv/lowest_div,
265 lowest_result / 1000, lowest_result % 1000);
266
267 /* Program ref_pix phase fractional divider */
268 reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
269 reg_val &= ~BM_CLKCTRL_FRAC_PIXFRAC;
270 reg_val |= BF(lowest_fracdiv, CLKCTRL_FRAC_PIXFRAC);
271 __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
272
273 /* Ungate PFD */
274 stmp3xxx_clearl(BM_CLKCTRL_FRAC_CLKGATEPIX,
275 REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
276
277 /* Program pix divider */
278 reg_val = __raw_readl(clk->scale_reg);
279 reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE);
280 reg_val |= BF(lowest_div, CLKCTRL_PIX_DIV);
281 __raw_writel(reg_val, clk->scale_reg);
282
283 /* Wait for divider update */
284 if (clk->busy_reg) {
285 int i;
286 for (i = 10000; i; i--)
287 if (!clk_is_busy(clk))
288 break;
289 if (!i) {
290 ret = -ETIMEDOUT;
291 goto out;
292 }
293 }
294
295 /* Switch to ref_pix source */
296 reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
297 reg_val &= ~BM_CLKCTRL_CLKSEQ_BYPASS_PIX;
298 __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
299
300out:
301 return ret;
302}
303
304
305static int cpu_set_rate(struct clk *clk, u32 rate)
306{
307 u32 reg_val;
308
309 if (rate < 24000)
310 return -EINVAL;
311 else if (rate == 24000) {
312 /* switch to the 24M source */
313 clk_set_parent(clk, &osc_24M);
314 } else {
315 int i;
316 u32 clkctrl_cpu = 1;
317 u32 c = clkctrl_cpu;
318 u32 clkctrl_frac = 1;
319 u32 val;
320 for ( ; c < 0x40; c++) {
321 u32 f = (pll_clk.rate*18/c + rate/2) / rate;
322 int s1, s2;
323
324 if (f < 18 || f > 35)
325 continue;
326 s1 = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu - rate;
327 s2 = pll_clk.rate*18/c/f - rate;
328 pr_debug("%s: s1 %d, s2 %d\n", __func__, s1, s2);
329 if (abs(s1) > abs(s2)) {
330 clkctrl_cpu = c;
331 clkctrl_frac = f;
332 }
333 if (s2 == 0)
334 break;
335 };
336 pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__,
337 clkctrl_cpu, clkctrl_frac);
338 if (c == 0x40) {
339 int d = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu -
340 rate;
341 if (abs(d) > 100 ||
342 clkctrl_frac < 18 || clkctrl_frac > 35)
343 return -EINVAL;
344 }
345
346 /* 4.6.2 */
347 val = __raw_readl(clk->scale_reg);
348 val &= ~(0x3f << clk->scale_shift);
349 val |= clkctrl_frac;
350 clk_set_parent(clk, &osc_24M);
351 udelay(10);
352 __raw_writel(val, clk->scale_reg);
353 /* ungate */
354 __raw_writel(1<<7, clk->scale_reg + 8);
355 /* write clkctrl_cpu */
356 clk->saved_div = clkctrl_cpu;
357
358 reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
359 reg_val &= ~0x3F;
360 reg_val |= clkctrl_cpu;
361 __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
362
363 for (i = 10000; i; i--)
364 if (!clk_is_busy(clk))
365 break;
366 if (!i) {
367 printk(KERN_ERR "couldn't set up CPU divisor\n");
368 return -ETIMEDOUT;
369 }
370 clk_set_parent(clk, &pll_clk);
371 clk->saved_div = 0;
372 udelay(10);
373 }
374 return 0;
375}
376
377static long cpu_get_rate(struct clk *clk)
378{
379 long rate = clk->parent->rate * 18;
380
381 rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
382 rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU) & 0x3f;
383 rate = ((rate + 9) / 10) * 10;
384 clk->rate = rate;
385
386 return rate;
387}
388
389static long cpu_round_rate(struct clk *clk, u32 rate)
390{
391 unsigned long r = 0;
392
393 if (rate <= 24000)
394 r = 24000;
395 else {
396 u32 clkctrl_cpu = 1;
397 u32 clkctrl_frac;
398 do {
399 clkctrl_frac =
400 (pll_clk.rate*18 / clkctrl_cpu + rate/2) / rate;
401 if (clkctrl_frac > 35)
402 continue;
403 if (pll_clk.rate*18 / clkctrl_frac / clkctrl_cpu/10 ==
404 rate / 10)
405 break;
406 } while (pll_clk.rate / 2 >= clkctrl_cpu++ * rate);
407 if (pll_clk.rate / 2 < (clkctrl_cpu - 1) * rate)
408 clkctrl_cpu--;
409 pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__,
410 clkctrl_cpu, clkctrl_frac);
411 if (clkctrl_frac < 18)
412 clkctrl_frac = 18;
413 if (clkctrl_frac > 35)
414 clkctrl_frac = 35;
415
416 r = pll_clk.rate * 18;
417 r /= clkctrl_frac;
418 r /= clkctrl_cpu;
419 r = 10 * ((r + 9) / 10);
420 }
421 return r;
422}
423
424static long emi_get_rate(struct clk *clk)
425{
426 long rate = clk->parent->rate * 18;
427
428 rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
429 rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI) & 0x3f;
430 clk->rate = rate;
431
432 return rate;
433}
434
435static int clkseq_set_parent(struct clk *clk, struct clk *parent)
436{
437 int ret = -EINVAL;
438 int shift = 8;
439
440 /* bypass? */
441 if (parent == &osc_24M)
442 shift = 4;
443
444 if (clk->bypass_reg) {
445#ifdef CONFIG_ARCH_STMP378X
446 u32 hbus_val, cpu_val;
447
448 if (clk == &cpu_clk && shift == 4) {
449 hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
450 HW_CLKCTRL_HBUS);
451 cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
452 HW_CLKCTRL_CPU);
453
454 hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
455 BM_CLKCTRL_HBUS_DIV);
456 clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU;
457 cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
458 cpu_val |= 1;
459
460 if (machine_is_stmp378x()) {
461 __raw_writel(hbus_val,
462 REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
463 __raw_writel(cpu_val,
464 REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
465 hclk.rate = 0;
466 }
467 } else if (clk == &cpu_clk && shift == 8) {
468 hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
469 HW_CLKCTRL_HBUS);
470 cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
471 HW_CLKCTRL_CPU);
472 hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
473 BM_CLKCTRL_HBUS_DIV);
474 hbus_val |= 2;
475 cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
476 if (clk->saved_div)
477 cpu_val |= clk->saved_div;
478 else
479 cpu_val |= 2;
480
481 if (machine_is_stmp378x()) {
482 __raw_writel(hbus_val,
483 REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
484 __raw_writel(cpu_val,
485 REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
486 hclk.rate = 0;
487 }
488 }
489#endif
490 __raw_writel(1 << clk->bypass_shift, clk->bypass_reg + shift);
491
492 ret = 0;
493 }
494
495 return ret;
496}
497
498static int hbus_set_rate(struct clk *clk, u32 rate)
499{
500 u8 div = 0;
501 int is_frac = 0;
502 u32 clkctrl_hbus;
503 struct clk *parent = clk->parent;
504
505 pr_debug("%s: rate %d, parent rate %d\n", __func__, rate,
506 parent->rate);
507
508 if (rate > parent->rate)
509 return -EINVAL;
510
511 if (((parent->rate + rate/2) / rate) * rate != parent->rate &&
512 parent->rate / rate < 32) {
513 pr_debug("%s: switching to fractional mode\n", __func__);
514 is_frac = 1;
515 }
516
517 if (is_frac)
518 div = (32 * rate + parent->rate / 2) / parent->rate;
519 else
520 div = (parent->rate + rate - 1) / rate;
521 pr_debug("%s: div calculated is %d\n", __func__, div);
522 if (!div || div > 0x1f)
523 return -EINVAL;
524
525 clk_set_parent(&cpu_clk, &osc_24M);
526 udelay(10);
527 clkctrl_hbus = __raw_readl(clk->scale_reg);
528 clkctrl_hbus &= ~0x3f;
529 clkctrl_hbus |= div;
530 clkctrl_hbus |= (is_frac << 5);
531
532 __raw_writel(clkctrl_hbus, clk->scale_reg);
533 if (clk->busy_reg) {
534 int i;
535 for (i = 10000; i; i--)
536 if (!clk_is_busy(clk))
537 break;
538 if (!i) {
539 printk(KERN_ERR "couldn't set up CPU divisor\n");
540 return -ETIMEDOUT;
541 }
542 }
543 clk_set_parent(&cpu_clk, &pll_clk);
544 __raw_writel(clkctrl_hbus, clk->scale_reg);
545 udelay(10);
546 return 0;
547}
548
549static long hbus_get_rate(struct clk *clk)
550{
551 long rate = clk->parent->rate;
552
553 if (__raw_readl(clk->scale_reg) & 0x20) {
554 rate *= __raw_readl(clk->scale_reg) & 0x1f;
555 rate /= 32;
556 } else
557 rate /= __raw_readl(clk->scale_reg) & 0x1f;
558 clk->rate = rate;
559
560 return rate;
561}
562
563static int xbus_set_rate(struct clk *clk, u32 rate)
564{
565 u16 div = 0;
566 u32 clkctrl_xbus;
567
568 pr_debug("%s: rate %d, parent rate %d\n", __func__, rate,
569 clk->parent->rate);
570
571 div = (clk->parent->rate + rate - 1) / rate;
572 pr_debug("%s: div calculated is %d\n", __func__, div);
573 if (!div || div > 0x3ff)
574 return -EINVAL;
575
576 clkctrl_xbus = __raw_readl(clk->scale_reg);
577 clkctrl_xbus &= ~0x3ff;
578 clkctrl_xbus |= div;
579 __raw_writel(clkctrl_xbus, clk->scale_reg);
580 if (clk->busy_reg) {
581 int i;
582 for (i = 10000; i; i--)
583 if (!clk_is_busy(clk))
584 break;
585 if (!i) {
586 printk(KERN_ERR "couldn't set up xbus divisor\n");
587 return -ETIMEDOUT;
588 }
589 }
590 return 0;
591}
592
593static long xbus_get_rate(struct clk *clk)
594{
595 long rate = clk->parent->rate;
596
597 rate /= __raw_readl(clk->scale_reg) & 0x3ff;
598 clk->rate = rate;
599
600 return rate;
601}
602
603
604/* Clock ops */
605
606static struct clk_ops std_ops = {
607 .enable = std_clk_enable,
608 .disable = std_clk_disable,
609 .get_rate = per_get_rate,
610 .set_rate = per_set_rate,
611 .set_parent = clkseq_set_parent,
612};
613
614static struct clk_ops min_ops = {
615 .enable = std_clk_enable,
616 .disable = std_clk_disable,
617};
618
619static struct clk_ops cpu_ops = {
620 .enable = std_clk_enable,
621 .disable = std_clk_disable,
622 .get_rate = cpu_get_rate,
623 .set_rate = cpu_set_rate,
624 .round_rate = cpu_round_rate,
625 .set_parent = clkseq_set_parent,
626};
627
628static struct clk_ops io_ops = {
629 .enable = std_clk_enable,
630 .disable = std_clk_disable,
631 .get_rate = io_get_rate,
632 .set_rate = io_set_rate,
633};
634
635static struct clk_ops hbus_ops = {
636 .get_rate = hbus_get_rate,
637 .set_rate = hbus_set_rate,
638};
639
640static struct clk_ops xbus_ops = {
641 .get_rate = xbus_get_rate,
642 .set_rate = xbus_set_rate,
643};
644
645static struct clk_ops lcdif_ops = {
646 .enable = std_clk_enable,
647 .disable = std_clk_disable,
648 .get_rate = lcdif_get_rate,
649 .set_rate = lcdif_set_rate,
650 .set_parent = clkseq_set_parent,
651};
652
653static struct clk_ops emi_ops = {
654 .get_rate = emi_get_rate,
655};
656
657/* List of on-chip clocks */
658
659static struct clk osc_24M = {
660 .flags = FIXED_RATE | ENABLED,
661 .rate = 24000,
662};
663
664static struct clk pll_clk = {
665 .parent = &osc_24M,
666 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
667 .enable_shift = 16,
668 .enable_wait = 10,
669 .flags = FIXED_RATE | ENABLED,
670 .rate = 480000,
671 .ops = &min_ops,
672};
673
674static struct clk cpu_clk = {
675 .parent = &pll_clk,
676 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
677 .scale_shift = 0,
678 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
679 .bypass_shift = 7,
680 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU,
681 .busy_bit = 28,
682 .flags = RATE_PROPAGATES | ENABLED,
683 .ops = &cpu_ops,
684};
685
686static struct clk io_clk = {
687 .parent = &pll_clk,
688 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
689 .enable_shift = 31,
690 .enable_negate = 1,
691 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
692 .scale_shift = 24,
693 .flags = RATE_PROPAGATES | ENABLED,
694 .ops = &io_ops,
695};
696
697static struct clk hclk = {
698 .parent = &cpu_clk,
699 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
700 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
701 .bypass_shift = 7,
702 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
703 .busy_bit = 29,
704 .flags = RATE_PROPAGATES | ENABLED,
705 .ops = &hbus_ops,
706};
707
708static struct clk xclk = {
709 .parent = &osc_24M,
710 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
711 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
712 .busy_bit = 31,
713 .flags = RATE_PROPAGATES | ENABLED,
714 .ops = &xbus_ops,
715};
716
717static struct clk uart_clk = {
718 .parent = &xclk,
719 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
720 .enable_shift = 31,
721 .enable_negate = 1,
722 .flags = ENABLED,
723 .ops = &min_ops,
724};
725
726static struct clk audio_clk = {
727 .parent = &xclk,
728 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
729 .enable_shift = 30,
730 .enable_negate = 1,
731 .ops = &min_ops,
732};
733
734static struct clk pwm_clk = {
735 .parent = &xclk,
736 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
737 .enable_shift = 29,
738 .enable_negate = 1,
739 .ops = &min_ops,
740};
741
742static struct clk dri_clk = {
743 .parent = &xclk,
744 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
745 .enable_shift = 28,
746 .enable_negate = 1,
747 .ops = &min_ops,
748};
749
750static struct clk digctl_clk = {
751 .parent = &xclk,
752 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
753 .enable_shift = 27,
754 .enable_negate = 1,
755 .ops = &min_ops,
756};
757
758static struct clk timer_clk = {
759 .parent = &xclk,
760 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
761 .enable_shift = 26,
762 .enable_negate = 1,
763 .flags = ENABLED,
764 .ops = &min_ops,
765};
766
767static struct clk lcdif_clk = {
768 .parent = &pll_clk,
769 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
770 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
771 .busy_bit = 29,
772 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
773 .enable_shift = 31,
774 .enable_negate = 1,
775 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
776 .bypass_shift = 1,
777 .flags = NEEDS_SET_PARENT,
778 .ops = &lcdif_ops,
779};
780
781static struct clk ssp_clk = {
782 .parent = &io_clk,
783 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
784 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
785 .busy_bit = 29,
786 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
787 .enable_shift = 31,
788 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
789 .bypass_shift = 5,
790 .enable_negate = 1,
791 .flags = NEEDS_SET_PARENT,
792 .ops = &std_ops,
793};
794
795static struct clk gpmi_clk = {
796 .parent = &io_clk,
797 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
798 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
799 .busy_bit = 29,
800 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
801 .enable_shift = 31,
802 .enable_negate = 1,
803 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
804 .bypass_shift = 4,
805 .flags = NEEDS_SET_PARENT,
806 .ops = &std_ops,
807};
808
809static struct clk spdif_clk = {
810 .parent = &pll_clk,
811 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SPDIF,
812 .enable_shift = 31,
813 .enable_negate = 1,
814 .ops = &min_ops,
815};
816
817static struct clk emi_clk = {
818 .parent = &pll_clk,
819 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
820 .enable_shift = 31,
821 .enable_negate = 1,
822 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
823 .scale_shift = 8,
824 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
825 .busy_bit = 28,
826 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
827 .bypass_shift = 6,
828 .flags = ENABLED,
829 .ops = &emi_ops,
830};
831
832static struct clk ir_clk = {
833 .parent = &io_clk,
834 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_IR,
835 .enable_shift = 31,
836 .enable_negate = 1,
837 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
838 .bypass_shift = 3,
839 .ops = &min_ops,
840};
841
842static struct clk saif_clk = {
843 .parent = &pll_clk,
844 .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
845 .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
846 .busy_bit = 29,
847 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
848 .enable_shift = 31,
849 .enable_negate = 1,
850 .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
851 .bypass_shift = 0,
852 .ops = &std_ops,
853};
854
855static struct clk usb_clk = {
856 .parent = &pll_clk,
857 .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
858 .enable_shift = 18,
859 .enable_negate = 1,
860 .ops = &min_ops,
861};
862
863/* list of all the clocks */
864static struct clk_lookup onchip_clks[] = {
865 {
866 .con_id = "osc_24M",
867 .clk = &osc_24M,
868 }, {
869 .con_id = "pll",
870 .clk = &pll_clk,
871 }, {
872 .con_id = "cpu",
873 .clk = &cpu_clk,
874 }, {
875 .con_id = "hclk",
876 .clk = &hclk,
877 }, {
878 .con_id = "xclk",
879 .clk = &xclk,
880 }, {
881 .con_id = "io",
882 .clk = &io_clk,
883 }, {
884 .con_id = "uart",
885 .clk = &uart_clk,
886 }, {
887 .con_id = "audio",
888 .clk = &audio_clk,
889 }, {
890 .con_id = "pwm",
891 .clk = &pwm_clk,
892 }, {
893 .con_id = "dri",
894 .clk = &dri_clk,
895 }, {
896 .con_id = "digctl",
897 .clk = &digctl_clk,
898 }, {
899 .con_id = "timer",
900 .clk = &timer_clk,
901 }, {
902 .con_id = "lcdif",
903 .clk = &lcdif_clk,
904 }, {
905 .con_id = "ssp",
906 .clk = &ssp_clk,
907 }, {
908 .con_id = "gpmi",
909 .clk = &gpmi_clk,
910 }, {
911 .con_id = "spdif",
912 .clk = &spdif_clk,
913 }, {
914 .con_id = "emi",
915 .clk = &emi_clk,
916 }, {
917 .con_id = "ir",
918 .clk = &ir_clk,
919 }, {
920 .con_id = "saif",
921 .clk = &saif_clk,
922 }, {
923 .con_id = "usb",
924 .clk = &usb_clk,
925 },
926};
927
928static int __init propagate_rate(struct clk *clk)
929{
930 struct clk_lookup *cl;
931
932 for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks);
933 cl++) {
934 if (unlikely(!clk_good(cl->clk)))
935 continue;
936 if (cl->clk->parent == clk && cl->clk->ops->get_rate) {
937 cl->clk->ops->get_rate(cl->clk);
938 if (cl->clk->flags & RATE_PROPAGATES)
939 propagate_rate(cl->clk);
940 }
941 }
942
943 return 0;
944}
945
946/* Exported API */
947unsigned long clk_get_rate(struct clk *clk)
948{
949 if (unlikely(!clk_good(clk)))
950 return 0;
951
952 if (clk->rate != 0)
953 return clk->rate;
954
955 if (clk->ops->get_rate != NULL)
956 return clk->ops->get_rate(clk);
957
958 return clk_get_rate(clk->parent);
959}
960EXPORT_SYMBOL(clk_get_rate);
961
962long clk_round_rate(struct clk *clk, unsigned long rate)
963{
964 if (unlikely(!clk_good(clk)))
965 return 0;
966
967 if (clk->ops->round_rate)
968 return clk->ops->round_rate(clk, rate);
969
970 return 0;
971}
972EXPORT_SYMBOL(clk_round_rate);
973
974static inline int close_enough(long rate1, long rate2)
975{
976 return rate1 && !((rate2 - rate1) * 1000 / rate1);
977}
978
979int clk_set_rate(struct clk *clk, unsigned long rate)
980{
981 int ret = -EINVAL;
982
983 if (unlikely(!clk_good(clk)))
984 goto out;
985
986 if (clk->flags & FIXED_RATE || !clk->ops->set_rate)
987 goto out;
988
989 else if (!close_enough(clk->rate, rate)) {
990 ret = clk->ops->set_rate(clk, rate);
991 if (ret < 0)
992 goto out;
993 clk->rate = rate;
994 if (clk->flags & RATE_PROPAGATES)
995 propagate_rate(clk);
996 } else
997 ret = 0;
998
999out:
1000 return ret;
1001}
1002EXPORT_SYMBOL(clk_set_rate);
1003
1004int clk_enable(struct clk *clk)
1005{
1006 unsigned long clocks_flags;
1007
1008 if (unlikely(!clk_good(clk)))
1009 return -EINVAL;
1010
1011 if (clk->parent)
1012 clk_enable(clk->parent);
1013
1014 spin_lock_irqsave(&clocks_lock, clocks_flags);
1015
1016 clk->usage++;
1017 if (clk->ops && clk->ops->enable)
1018 clk->ops->enable(clk);
1019
1020 spin_unlock_irqrestore(&clocks_lock, clocks_flags);
1021 return 0;
1022}
1023EXPORT_SYMBOL(clk_enable);
1024
1025static void local_clk_disable(struct clk *clk)
1026{
1027 if (unlikely(!clk_good(clk)))
1028 return;
1029
1030 if (clk->usage == 0 && clk->ops->disable)
1031 clk->ops->disable(clk);
1032
1033 if (clk->parent)
1034 local_clk_disable(clk->parent);
1035}
1036
1037void clk_disable(struct clk *clk)
1038{
1039 unsigned long clocks_flags;
1040
1041 if (unlikely(!clk_good(clk)))
1042 return;
1043
1044 spin_lock_irqsave(&clocks_lock, clocks_flags);
1045
1046 if ((--clk->usage) == 0 && clk->ops->disable)
1047 clk->ops->disable(clk);
1048
1049 spin_unlock_irqrestore(&clocks_lock, clocks_flags);
1050 if (clk->parent)
1051 clk_disable(clk->parent);
1052}
1053EXPORT_SYMBOL(clk_disable);
1054
1055/* Some additional API */
1056int clk_set_parent(struct clk *clk, struct clk *parent)
1057{
1058 int ret = -ENODEV;
1059 unsigned long clocks_flags;
1060
1061 if (unlikely(!clk_good(clk)))
1062 goto out;
1063
1064 if (!clk->ops->set_parent)
1065 goto out;
1066
1067 spin_lock_irqsave(&clocks_lock, clocks_flags);
1068
1069 ret = clk->ops->set_parent(clk, parent);
1070 if (!ret) {
1071 /* disable if usage count is 0 */
1072 local_clk_disable(parent);
1073
1074 parent->usage += clk->usage;
1075 clk->parent->usage -= clk->usage;
1076
1077 /* disable if new usage count is 0 */
1078 local_clk_disable(clk->parent);
1079
1080 clk->parent = parent;
1081 }
1082 spin_unlock_irqrestore(&clocks_lock, clocks_flags);
1083
1084out:
1085 return ret;
1086}
1087EXPORT_SYMBOL(clk_set_parent);
1088
1089struct clk *clk_get_parent(struct clk *clk)
1090{
1091 if (unlikely(!clk_good(clk)))
1092 return NULL;
1093 return clk->parent;
1094}
1095EXPORT_SYMBOL(clk_get_parent);
1096
1097static int __init clk_init(void)
1098{
1099 struct clk_lookup *cl;
1100 struct clk_ops *ops;
1101
1102 spin_lock_init(&clocks_lock);
1103
1104 for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks);
1105 cl++) {
1106 if (cl->clk->flags & ENABLED)
1107 clk_enable(cl->clk);
1108 else
1109 local_clk_disable(cl->clk);
1110
1111 ops = cl->clk->ops;
1112
1113 if ((cl->clk->flags & NEEDS_INITIALIZATION) &&
1114 ops && ops->set_rate)
1115 ops->set_rate(cl->clk, cl->clk->rate);
1116
1117 if (cl->clk->flags & FIXED_RATE) {
1118 if (cl->clk->flags & RATE_PROPAGATES)
1119 propagate_rate(cl->clk);
1120 } else {
1121 if (ops && ops->get_rate)
1122 ops->get_rate(cl->clk);
1123 }
1124
1125 if (cl->clk->flags & NEEDS_SET_PARENT) {
1126 if (ops && ops->set_parent)
1127 ops->set_parent(cl->clk, cl->clk->parent);
1128 }
1129
1130 clkdev_add(cl);
1131 }
1132 return 0;
1133}
1134
1135arch_initcall(clk_init);
diff --git a/arch/arm/plat-stmp3xxx/clock.h b/arch/arm/plat-stmp3xxx/clock.h
new file mode 100644
index 000000000000..a6611e1a3510
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/clock.h
@@ -0,0 +1,61 @@
1/*
2 * Clock control driver for Freescale STMP37XX/STMP378X - internal header file
3 *
4 * Author: Vitaly Wool <vital@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ARCH_ARM_STMX3XXX_CLOCK_H__
19#define __ARCH_ARM_STMX3XXX_CLOCK_H__
20
21#ifndef __ASSEMBLER__
22
23struct clk_ops {
24 int (*enable) (struct clk *);
25 int (*disable) (struct clk *);
26 long (*get_rate) (struct clk *);
27 long (*round_rate) (struct clk *, u32);
28 int (*set_rate) (struct clk *, u32);
29 int (*set_parent) (struct clk *, struct clk *);
30};
31
32struct clk {
33 struct clk *parent;
34 u32 rate;
35 u32 flags;
36 u8 scale_shift;
37 u8 enable_shift;
38 u8 bypass_shift;
39 u8 busy_bit;
40 s8 usage;
41 int enable_wait;
42 int enable_negate;
43 u32 saved_div;
44 void __iomem *enable_reg;
45 void __iomem *scale_reg;
46 void __iomem *bypass_reg;
47 void __iomem *busy_reg;
48 struct clk_ops *ops;
49};
50
51#endif /* __ASSEMBLER__ */
52
53/* Flags */
54#define RATE_PROPAGATES (1<<0)
55#define NEEDS_INITIALIZATION (1<<1)
56#define PARENT_SET_RATE (1<<2)
57#define FIXED_RATE (1<<3)
58#define ENABLED (1<<4)
59#define NEEDS_SET_PARENT (1<<5)
60
61#endif
diff --git a/arch/arm/plat-stmp3xxx/core.c b/arch/arm/plat-stmp3xxx/core.c
new file mode 100644
index 000000000000..37b8a09148a4
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/core.c
@@ -0,0 +1,128 @@
1/*
2 * Freescale STMP37XX/STMP378X core routines
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/io.h>
21
22#include <mach/stmp3xxx.h>
23#include <mach/platform.h>
24#include <mach/dma.h>
25#include <mach/regs-clkctrl.h>
26
27static int __stmp3xxx_reset_block(void __iomem *hwreg, int just_enable)
28{
29 u32 c;
30 int timeout;
31
32 /* the process of software reset of IP block is done
33 in several steps:
34
35 - clear SFTRST and wait for block is enabled;
36 - clear clock gating (CLKGATE bit);
37 - set the SFTRST again and wait for block is in reset;
38 - clear SFTRST and wait for reset completion.
39 */
40 c = __raw_readl(hwreg);
41 c &= ~(1<<31); /* clear SFTRST */
42 __raw_writel(c, hwreg);
43 for (timeout = 1000000; timeout > 0; timeout--)
44 /* still in SFTRST state ? */
45 if ((__raw_readl(hwreg) & (1<<31)) == 0)
46 break;
47 if (timeout <= 0) {
48 printk(KERN_ERR"%s(%p): timeout when enabling\n",
49 __func__, hwreg);
50 return -ETIME;
51 }
52
53 c = __raw_readl(hwreg);
54 c &= ~(1<<30); /* clear CLKGATE */
55 __raw_writel(c, hwreg);
56
57 if (!just_enable) {
58 c = __raw_readl(hwreg);
59 c |= (1<<31); /* now again set SFTRST */
60 __raw_writel(c, hwreg);
61 for (timeout = 1000000; timeout > 0; timeout--)
62 /* poll until CLKGATE set */
63 if (__raw_readl(hwreg) & (1<<30))
64 break;
65 if (timeout <= 0) {
66 printk(KERN_ERR"%s(%p): timeout when resetting\n",
67 __func__, hwreg);
68 return -ETIME;
69 }
70
71 c = __raw_readl(hwreg);
72 c &= ~(1<<31); /* clear SFTRST */
73 __raw_writel(c, hwreg);
74 for (timeout = 1000000; timeout > 0; timeout--)
75 /* still in SFTRST state ? */
76 if ((__raw_readl(hwreg) & (1<<31)) == 0)
77 break;
78 if (timeout <= 0) {
79 printk(KERN_ERR"%s(%p): timeout when enabling "
80 "after reset\n", __func__, hwreg);
81 return -ETIME;
82 }
83
84 c = __raw_readl(hwreg);
85 c &= ~(1<<30); /* clear CLKGATE */
86 __raw_writel(c, hwreg);
87 }
88 for (timeout = 1000000; timeout > 0; timeout--)
89 /* still in SFTRST state ? */
90 if ((__raw_readl(hwreg) & (1<<30)) == 0)
91 break;
92
93 if (timeout <= 0) {
94 printk(KERN_ERR"%s(%p): timeout when unclockgating\n",
95 __func__, hwreg);
96 return -ETIME;
97 }
98
99 return 0;
100}
101
102int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable)
103{
104 int try = 10;
105 int r;
106
107 while (try--) {
108 r = __stmp3xxx_reset_block(hwreg, just_enable);
109 if (!r)
110 break;
111 pr_debug("%s: try %d failed\n", __func__, 10 - try);
112 }
113 return r;
114}
115EXPORT_SYMBOL(stmp3xxx_reset_block);
116
117struct platform_device stmp3xxx_dbguart = {
118 .name = "stmp3xxx-dbguart",
119 .id = -1,
120};
121
122void __init stmp3xxx_init(void)
123{
124 /* Turn off auto-slow and other tricks */
125 stmp3xxx_clearl(0x7f00000, REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
126
127 stmp3xxx_dma_init();
128}
diff --git a/arch/arm/plat-stmp3xxx/devices.c b/arch/arm/plat-stmp3xxx/devices.c
new file mode 100644
index 000000000000..68fed4b8746a
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/devices.c
@@ -0,0 +1,389 @@
1/*
2* Freescale STMP37XX/STMP378X platform devices
3*
4* Embedded Alley Solutions, Inc <source@embeddedalley.com>
5*
6* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8*/
9
10/*
11* The code contained herein is licensed under the GNU General Public
12* License. You may obtain a copy of the GNU General Public License
13* Version 2 or later at the following locations:
14*
15* http://www.opensource.org/licenses/gpl-license.html
16* http://www.gnu.org/copyleft/gpl.html
17*/
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/device.h>
21#include <linux/platform_device.h>
22#include <linux/dma-mapping.h>
23
24#include <mach/dma.h>
25#include <mach/platform.h>
26#include <mach/stmp3xxx.h>
27#include <mach/regs-lcdif.h>
28#include <mach/regs-uartapp.h>
29#include <mach/regs-gpmi.h>
30#include <mach/regs-usbctrl.h>
31#include <mach/regs-ssp.h>
32#include <mach/regs-rtc.h>
33
34static u64 common_dmamask = DMA_BIT_MASK(32);
35
36static struct resource appuart_resources[] = {
37 {
38 .start = IRQ_UARTAPP_INTERNAL,
39 .end = IRQ_UARTAPP_INTERNAL,
40 .flags = IORESOURCE_IRQ,
41 }, {
42 .start = IRQ_UARTAPP_RX_DMA,
43 .end = IRQ_UARTAPP_RX_DMA,
44 .flags = IORESOURCE_IRQ,
45 }, {
46 .start = IRQ_UARTAPP_TX_DMA,
47 .end = IRQ_UARTAPP_TX_DMA,
48 .flags = IORESOURCE_IRQ,
49 }, {
50 .start = REGS_UARTAPP1_PHYS,
51 .end = REGS_UARTAPP1_PHYS + REGS_UARTAPP_SIZE,
52 .flags = IORESOURCE_MEM,
53 }, {
54 /* Rx DMA channel */
55 .start = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX),
56 .end = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX),
57 .flags = IORESOURCE_DMA,
58 }, {
59 /* Tx DMA channel */
60 .start = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX),
61 .end = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX),
62 .flags = IORESOURCE_DMA,
63 },
64};
65
66struct platform_device stmp3xxx_appuart = {
67 .name = "stmp3xxx-appuart",
68 .id = 0,
69 .resource = appuart_resources,
70 .num_resources = ARRAY_SIZE(appuart_resources),
71 .dev = {
72 .dma_mask = &common_dmamask,
73 .coherent_dma_mask = DMA_BIT_MASK(32),
74 },
75};
76
77struct platform_device stmp3xxx_watchdog = {
78 .name = "stmp3xxx_wdt",
79 .id = -1,
80};
81
82static struct resource ts_resource[] = {
83 {
84 .flags = IORESOURCE_IRQ,
85 .start = IRQ_TOUCH_DETECT,
86 .end = IRQ_TOUCH_DETECT,
87 }, {
88 .flags = IORESOURCE_IRQ,
89 .start = IRQ_LRADC_CH5,
90 .end = IRQ_LRADC_CH5,
91 },
92};
93
94struct platform_device stmp3xxx_touchscreen = {
95 .name = "stmp3xxx_ts",
96 .id = -1,
97 .resource = ts_resource,
98 .num_resources = ARRAY_SIZE(ts_resource),
99};
100
101/*
102* Keypad device
103*/
104struct platform_device stmp3xxx_keyboard = {
105 .name = "stmp3xxx-keyboard",
106 .id = -1,
107};
108
109static struct resource gpmi_resources[] = {
110 {
111 .flags = IORESOURCE_MEM,
112 .start = REGS_GPMI_PHYS,
113 .end = REGS_GPMI_PHYS + REGS_GPMI_SIZE,
114 }, {
115 .flags = IORESOURCE_IRQ,
116 .start = IRQ_GPMI_DMA,
117 .end = IRQ_GPMI_DMA,
118 }, {
119 .flags = IORESOURCE_DMA,
120 .start = STMP3XXX_DMA(4, STMP3XXX_BUS_APBH),
121 .end = STMP3XXX_DMA(8, STMP3XXX_BUS_APBH),
122 },
123};
124
125struct platform_device stmp3xxx_gpmi = {
126 .name = "gpmi",
127 .id = -1,
128 .dev = {
129 .dma_mask = &common_dmamask,
130 .coherent_dma_mask = DMA_BIT_MASK(32),
131 },
132 .resource = gpmi_resources,
133 .num_resources = ARRAY_SIZE(gpmi_resources),
134};
135
136static struct resource mmc1_resource[] = {
137 {
138 .flags = IORESOURCE_MEM,
139 .start = REGS_SSP1_PHYS,
140 .end = REGS_SSP1_PHYS + REGS_SSP_SIZE,
141 }, {
142 .flags = IORESOURCE_DMA,
143 .start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
144 .end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
145 }, {
146 .flags = IORESOURCE_IRQ,
147 .start = IRQ_SSP1_DMA,
148 .end = IRQ_SSP1_DMA,
149 }, {
150 .flags = IORESOURCE_IRQ,
151 .start = IRQ_SSP_ERROR,
152 .end = IRQ_SSP_ERROR,
153 },
154};
155
156struct platform_device stmp3xxx_mmc = {
157 .name = "stmp3xxx-mmc",
158 .id = 1,
159 .dev = {
160 .dma_mask = &common_dmamask,
161 .coherent_dma_mask = DMA_BIT_MASK(32),
162 },
163 .resource = mmc1_resource,
164 .num_resources = ARRAY_SIZE(mmc1_resource),
165};
166
167static struct resource usb_resources[] = {
168 {
169 .start = REGS_USBCTRL_PHYS,
170 .end = REGS_USBCTRL_PHYS + SZ_4K,
171 .flags = IORESOURCE_MEM,
172 }, {
173 .start = IRQ_USB_CTRL,
174 .end = IRQ_USB_CTRL,
175 .flags = IORESOURCE_IRQ,
176 },
177};
178
179struct platform_device stmp3xxx_udc = {
180 .name = "fsl-usb2-udc",
181 .id = -1,
182 .dev = {
183 .dma_mask = &common_dmamask,
184 .coherent_dma_mask = DMA_BIT_MASK(32),
185 },
186 .resource = usb_resources,
187 .num_resources = ARRAY_SIZE(usb_resources),
188};
189
190struct platform_device stmp3xxx_ehci = {
191 .name = "fsl-ehci",
192 .id = -1,
193 .dev = {
194 .dma_mask = &common_dmamask,
195 .coherent_dma_mask = DMA_BIT_MASK(32),
196 },
197 .resource = usb_resources,
198 .num_resources = ARRAY_SIZE(usb_resources),
199};
200
201static struct resource rtc_resources[] = {
202 {
203 .start = REGS_RTC_PHYS,
204 .end = REGS_RTC_PHYS + REGS_RTC_SIZE,
205 .flags = IORESOURCE_MEM,
206 }, {
207 .start = IRQ_RTC_ALARM,
208 .end = IRQ_RTC_ALARM,
209 .flags = IORESOURCE_IRQ,
210 }, {
211 .start = IRQ_RTC_1MSEC,
212 .end = IRQ_RTC_1MSEC,
213 .flags = IORESOURCE_IRQ,
214 },
215};
216
217struct platform_device stmp3xxx_rtc = {
218 .name = "stmp3xxx-rtc",
219 .id = -1,
220 .resource = rtc_resources,
221 .num_resources = ARRAY_SIZE(rtc_resources),
222};
223
224static struct resource ssp1_resources[] = {
225 {
226 .start = REGS_SSP1_PHYS,
227 .end = REGS_SSP1_PHYS + REGS_SSP_SIZE,
228 .flags = IORESOURCE_MEM,
229 }, {
230 .start = IRQ_SSP1_DMA,
231 .end = IRQ_SSP1_DMA,
232 .flags = IORESOURCE_IRQ,
233 }, {
234 .start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
235 .end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
236 .flags = IORESOURCE_DMA,
237 },
238};
239
240static struct resource ssp2_resources[] = {
241 {
242 .start = REGS_SSP2_PHYS,
243 .end = REGS_SSP2_PHYS + REGS_SSP_SIZE,
244 .flags = IORESOURCE_MEM,
245 }, {
246 .start = IRQ_SSP2_DMA,
247 .end = IRQ_SSP2_DMA,
248 .flags = IORESOURCE_IRQ,
249 }, {
250 .start = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH),
251 .end = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH),
252 .flags = IORESOURCE_DMA,
253 },
254};
255
256struct platform_device stmp3xxx_spi1 = {
257 .name = "stmp3xxx_ssp",
258 .id = 1,
259 .dev = {
260 .dma_mask = &common_dmamask,
261 .coherent_dma_mask = DMA_BIT_MASK(32),
262 },
263 .resource = ssp1_resources,
264 .num_resources = ARRAY_SIZE(ssp1_resources),
265};
266
267struct platform_device stmp3xxx_spi2 = {
268 .name = "stmp3xxx_ssp",
269 .id = 2,
270 .dev = {
271 .dma_mask = &common_dmamask,
272 .coherent_dma_mask = DMA_BIT_MASK(32),
273 },
274 .resource = ssp2_resources,
275 .num_resources = ARRAY_SIZE(ssp2_resources),
276};
277
278static struct resource fb_resource[] = {
279 {
280 .flags = IORESOURCE_IRQ,
281 .start = IRQ_LCDIF_DMA,
282 .end = IRQ_LCDIF_DMA,
283 }, {
284 .flags = IORESOURCE_IRQ,
285 .start = IRQ_LCDIF_ERROR,
286 .end = IRQ_LCDIF_ERROR,
287 }, {
288 .flags = IORESOURCE_MEM,
289 .start = REGS_LCDIF_PHYS,
290 .end = REGS_LCDIF_PHYS + REGS_LCDIF_SIZE,
291 },
292};
293
294struct platform_device stmp3xxx_framebuffer = {
295 .name = "stmp3xxx-fb",
296 .id = -1,
297 .dev = {
298 .dma_mask = &common_dmamask,
299 .coherent_dma_mask = DMA_BIT_MASK(32),
300 },
301 .num_resources = ARRAY_SIZE(fb_resource),
302 .resource = fb_resource,
303};
304
305#define CMDLINE_DEVICE_CHOOSE(name, dev1, dev2) \
306 static char *cmdline_device_##name; \
307 static int cmdline_device_##name##_setup(char *dev) \
308 { \
309 cmdline_device_##name = dev + 1; \
310 return 0; \
311 } \
312 __setup(#name, cmdline_device_##name##_setup); \
313 int stmp3xxx_##name##_device_register(void) \
314 { \
315 struct platform_device *d = NULL; \
316 if (!cmdline_device_##name || \
317 !strcmp(cmdline_device_##name, #dev1)) \
318 d = &stmp3xxx_##dev1; \
319 else if (!strcmp(cmdline_device_##name, #dev2)) \
320 d = &stmp3xxx_##dev2; \
321 else \
322 printk(KERN_ERR"Unknown %s assignment '%s'.\n", \
323 #name, cmdline_device_##name); \
324 return d ? platform_device_register(d) : -ENOENT; \
325 }
326
327CMDLINE_DEVICE_CHOOSE(ssp1, mmc, spi1)
328CMDLINE_DEVICE_CHOOSE(ssp2, gpmi, spi2)
329
330struct platform_device stmp3xxx_backlight = {
331 .name = "stmp3xxx-bl",
332 .id = -1,
333};
334
335struct platform_device stmp3xxx_rotdec = {
336 .name = "stmp3xxx-rotdec",
337 .id = -1,
338};
339
340struct platform_device stmp3xxx_persistent = {
341 .name = "stmp3xxx-persistent",
342 .id = -1,
343};
344
345struct platform_device stmp3xxx_dcp_bootstream = {
346 .name = "stmp3xxx-dcpboot",
347 .id = -1,
348 .dev = {
349 .dma_mask = &common_dmamask,
350 .coherent_dma_mask = DMA_BIT_MASK(32),
351 },
352};
353
354static struct resource dcp_resources[] = {
355 {
356 .start = IRQ_DCP_VMI,
357 .end = IRQ_DCP_VMI,
358 .flags = IORESOURCE_IRQ,
359 }, {
360 .start = IRQ_DCP,
361 .end = IRQ_DCP,
362 .flags = IORESOURCE_IRQ,
363 },
364};
365
366struct platform_device stmp3xxx_dcp = {
367 .name = "stmp3xxx-dcp",
368 .id = -1,
369 .resource = dcp_resources,
370 .num_resources = ARRAY_SIZE(dcp_resources),
371 .dev = {
372 .dma_mask = &common_dmamask,
373 .coherent_dma_mask = DMA_BIT_MASK(32),
374 },
375};
376
377static struct resource battery_resource[] = {
378 {
379 .flags = IORESOURCE_IRQ,
380 .start = IRQ_VDD5V,
381 .end = IRQ_VDD5V,
382 },
383};
384
385struct platform_device stmp3xxx_battery = {
386 .name = "stmp3xxx-battery",
387 .resource = battery_resource,
388 .num_resources = ARRAY_SIZE(battery_resource),
389};
diff --git a/arch/arm/plat-stmp3xxx/dma.c b/arch/arm/plat-stmp3xxx/dma.c
new file mode 100644
index 000000000000..d2f497764dce
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/dma.c
@@ -0,0 +1,463 @@
1/*
2 * DMA helper routines for Freescale STMP37XX/STMP378X
3 *
4 * Author: dmitry pervushin <dpervushin@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/device.h>
20#include <linux/dmapool.h>
21#include <linux/sysdev.h>
22#include <linux/cpufreq.h>
23
24#include <asm/page.h>
25
26#include <mach/platform.h>
27#include <mach/dma.h>
28#include <mach/regs-apbx.h>
29#include <mach/regs-apbh.h>
30
31static const size_t pool_item_size = sizeof(struct stmp3xxx_dma_command);
32static const size_t pool_alignment = 8;
33static struct stmp3xxx_dma_user {
34 void *pool;
35 int inuse;
36 const char *name;
37} channels[MAX_DMA_CHANNELS];
38
39#define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS)
40#define IS_USED(ch) (channels[ch].inuse)
41
42int stmp3xxx_dma_request(int ch, struct device *dev, const char *name)
43{
44 struct stmp3xxx_dma_user *user;
45 int err = 0;
46
47 user = channels + ch;
48 if (!IS_VALID_CHANNEL(ch)) {
49 err = -ENODEV;
50 goto out;
51 }
52 if (IS_USED(ch)) {
53 err = -EBUSY;
54 goto out;
55 }
56 /* Create a pool to allocate dma commands from */
57 user->pool = dma_pool_create(name, dev, pool_item_size,
58 pool_alignment, PAGE_SIZE);
59 if (user->pool == NULL) {
60 err = -ENOMEM;
61 goto out;
62 }
63 user->name = name;
64 user->inuse++;
65out:
66 return err;
67}
68EXPORT_SYMBOL(stmp3xxx_dma_request);
69
70int stmp3xxx_dma_release(int ch)
71{
72 struct stmp3xxx_dma_user *user = channels + ch;
73 int err = 0;
74
75 if (!IS_VALID_CHANNEL(ch)) {
76 err = -ENODEV;
77 goto out;
78 }
79 if (!IS_USED(ch)) {
80 err = -EBUSY;
81 goto out;
82 }
83 BUG_ON(user->pool == NULL);
84 dma_pool_destroy(user->pool);
85 user->inuse--;
86out:
87 return err;
88}
89EXPORT_SYMBOL(stmp3xxx_dma_release);
90
91int stmp3xxx_dma_read_semaphore(int channel)
92{
93 int sem = -1;
94
95 switch (STMP3XXX_DMA_BUS(channel)) {
96 case STMP3XXX_BUS_APBH:
97 sem = __raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
98 STMP3XXX_DMA_CHANNEL(channel) * 0x70);
99 sem &= BM_APBH_CHn_SEMA_PHORE;
100 sem >>= BP_APBH_CHn_SEMA_PHORE;
101 break;
102
103 case STMP3XXX_BUS_APBX:
104 sem = __raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
105 STMP3XXX_DMA_CHANNEL(channel) * 0x70);
106 sem &= BM_APBX_CHn_SEMA_PHORE;
107 sem >>= BP_APBX_CHn_SEMA_PHORE;
108 break;
109 default:
110 BUG();
111 }
112 return sem;
113}
114EXPORT_SYMBOL(stmp3xxx_dma_read_semaphore);
115
116int stmp3xxx_dma_allocate_command(int channel,
117 struct stmp3xxx_dma_descriptor *descriptor)
118{
119 struct stmp3xxx_dma_user *user = channels + channel;
120 int err = 0;
121
122 if (!IS_VALID_CHANNEL(channel)) {
123 err = -ENODEV;
124 goto out;
125 }
126 if (!IS_USED(channel)) {
127 err = -EBUSY;
128 goto out;
129 }
130 if (descriptor == NULL) {
131 err = -EINVAL;
132 goto out;
133 }
134
135 /* Allocate memory for a command from the buffer */
136 descriptor->command =
137 dma_pool_alloc(user->pool, GFP_KERNEL, &descriptor->handle);
138
139 /* Check it worked */
140 if (!descriptor->command) {
141 err = -ENOMEM;
142 goto out;
143 }
144
145 memset(descriptor->command, 0, pool_item_size);
146out:
147 WARN_ON(err);
148 return err;
149}
150EXPORT_SYMBOL(stmp3xxx_dma_allocate_command);
151
152int stmp3xxx_dma_free_command(int channel,
153 struct stmp3xxx_dma_descriptor *descriptor)
154{
155 int err = 0;
156
157 if (!IS_VALID_CHANNEL(channel)) {
158 err = -ENODEV;
159 goto out;
160 }
161 if (!IS_USED(channel)) {
162 err = -EBUSY;
163 goto out;
164 }
165
166 /* Return the command memory to the pool */
167 dma_pool_free(channels[channel].pool, descriptor->command,
168 descriptor->handle);
169
170 /* Initialise descriptor so we're not tempted to use it */
171 descriptor->command = NULL;
172 descriptor->handle = 0;
173 descriptor->virtual_buf_ptr = NULL;
174 descriptor->next_descr = NULL;
175
176 WARN_ON(err);
177out:
178 return err;
179}
180EXPORT_SYMBOL(stmp3xxx_dma_free_command);
181
182void stmp3xxx_dma_go(int channel,
183 struct stmp3xxx_dma_descriptor *head, u32 semaphore)
184{
185 int ch = STMP3XXX_DMA_CHANNEL(channel);
186 void __iomem *c, *s;
187
188 switch (STMP3XXX_DMA_BUS(channel)) {
189 case STMP3XXX_BUS_APBH:
190 c = REGS_APBH_BASE + HW_APBH_CHn_NXTCMDAR + 0x70 * ch;
191 s = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * ch;
192 break;
193
194 case STMP3XXX_BUS_APBX:
195 c = REGS_APBX_BASE + HW_APBX_CHn_NXTCMDAR + 0x70 * ch;
196 s = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * ch;
197 break;
198
199 default:
200 return;
201 }
202
203 /* Set next command */
204 __raw_writel(head->handle, c);
205 /* Set counting semaphore (kicks off transfer). Assumes
206 peripheral has been set up correctly */
207 __raw_writel(semaphore, s);
208}
209EXPORT_SYMBOL(stmp3xxx_dma_go);
210
211int stmp3xxx_dma_running(int channel)
212{
213 switch (STMP3XXX_DMA_BUS(channel)) {
214 case STMP3XXX_BUS_APBH:
215 return (__raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
216 0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
217 BM_APBH_CHn_SEMA_PHORE;
218
219 case STMP3XXX_BUS_APBX:
220 return (__raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
221 0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
222 BM_APBX_CHn_SEMA_PHORE;
223 default:
224 BUG();
225 return 0;
226 }
227}
228EXPORT_SYMBOL(stmp3xxx_dma_running);
229
230/*
231 * Circular dma chain management
232 */
233void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain)
234{
235 int i;
236
237 for (i = 0; i < chain->total_count; i++)
238 stmp3xxx_dma_free_command(
239 STMP3XXX_DMA(chain->channel, chain->bus),
240 &chain->chain[i]);
241}
242EXPORT_SYMBOL(stmp3xxx_dma_free_chain);
243
244int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
245 struct stmp3xxx_dma_descriptor descriptors[],
246 unsigned items)
247{
248 int i;
249 int err = 0;
250
251 if (items == 0)
252 return err;
253
254 for (i = 0; i < items; i++) {
255 err = stmp3xxx_dma_allocate_command(ch, &descriptors[i]);
256 if (err) {
257 WARN_ON(err);
258 /*
259 * Couldn't allocate the whole chain.
260 * deallocate what has been allocated
261 */
262 if (i) {
263 do {
264 stmp3xxx_dma_free_command(ch,
265 &descriptors
266 [i]);
267 } while (i-- >= 0);
268 }
269 return err;
270 }
271
272 /* link them! */
273 if (i > 0) {
274 descriptors[i - 1].next_descr = &descriptors[i];
275 descriptors[i - 1].command->next =
276 descriptors[i].handle;
277 }
278 }
279
280 /* make list circular */
281 descriptors[items - 1].next_descr = &descriptors[0];
282 descriptors[items - 1].command->next = descriptors[0].handle;
283
284 chain->total_count = items;
285 chain->chain = descriptors;
286 chain->free_index = 0;
287 chain->active_index = 0;
288 chain->cooked_index = 0;
289 chain->free_count = items;
290 chain->active_count = 0;
291 chain->cooked_count = 0;
292 chain->bus = STMP3XXX_DMA_BUS(ch);
293 chain->channel = STMP3XXX_DMA_CHANNEL(ch);
294 return err;
295}
296EXPORT_SYMBOL(stmp3xxx_dma_make_chain);
297
298void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain)
299{
300 BUG_ON(stmp3xxx_dma_running(STMP3XXX_DMA(chain->channel, chain->bus)));
301 chain->free_index = 0;
302 chain->active_index = 0;
303 chain->cooked_index = 0;
304 chain->free_count = chain->total_count;
305 chain->active_count = 0;
306 chain->cooked_count = 0;
307}
308EXPORT_SYMBOL(stmp37xx_circ_clear_chain);
309
310void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain,
311 unsigned count)
312{
313 BUG_ON(chain->cooked_count < count);
314
315 chain->cooked_count -= count;
316 chain->cooked_index += count;
317 chain->cooked_index %= chain->total_count;
318 chain->free_count += count;
319}
320EXPORT_SYMBOL(stmp37xx_circ_advance_free);
321
322void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
323 unsigned count)
324{
325 void __iomem *c;
326 u32 mask_clr, mask;
327 BUG_ON(chain->free_count < count);
328
329 chain->free_count -= count;
330 chain->free_index += count;
331 chain->free_index %= chain->total_count;
332 chain->active_count += count;
333
334 switch (chain->bus) {
335 case STMP3XXX_BUS_APBH:
336 c = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * chain->channel;
337 mask_clr = BM_APBH_CHn_SEMA_INCREMENT_SEMA;
338 mask = BF(count, APBH_CHn_SEMA_INCREMENT_SEMA);
339 break;
340 case STMP3XXX_BUS_APBX:
341 c = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * chain->channel;
342 mask_clr = BM_APBX_CHn_SEMA_INCREMENT_SEMA;
343 mask = BF(count, APBX_CHn_SEMA_INCREMENT_SEMA);
344 break;
345 default:
346 BUG();
347 return;
348 }
349
350 /* Set counting semaphore (kicks off transfer). Assumes
351 peripheral has been set up correctly */
352 stmp3xxx_clearl(mask_clr, c);
353 stmp3xxx_setl(mask, c);
354}
355EXPORT_SYMBOL(stmp37xx_circ_advance_active);
356
357unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain)
358{
359 unsigned cooked;
360
361 cooked = chain->active_count -
362 stmp3xxx_dma_read_semaphore(STMP3XXX_DMA(chain->channel, chain->bus));
363
364 chain->active_count -= cooked;
365 chain->active_index += cooked;
366 chain->active_index %= chain->total_count;
367
368 chain->cooked_count += cooked;
369
370 return cooked;
371}
372EXPORT_SYMBOL(stmp37xx_circ_advance_cooked);
373
374void stmp3xxx_dma_set_alt_target(int channel, int function)
375{
376#if defined(CONFIG_ARCH_STMP37XX)
377 unsigned bits = 4;
378#elif defined(CONFIG_ARCH_STMP378X)
379 unsigned bits = 2;
380#else
381#error wrong arch
382#endif
383 int shift = STMP3XXX_DMA_CHANNEL(channel) * bits;
384 unsigned mask = (1<<bits) - 1;
385 void __iomem *c;
386
387 BUG_ON(function < 0 || function >= (1<<bits));
388 pr_debug("%s: channel = %d, using mask %x, "
389 "shift = %d\n", __func__, channel, mask, shift);
390
391 switch (STMP3XXX_DMA_BUS(channel)) {
392 case STMP3XXX_BUS_APBH:
393 c = REGS_APBH_BASE + HW_APBH_DEVSEL;
394 break;
395 case STMP3XXX_BUS_APBX:
396 c = REGS_APBX_BASE + HW_APBX_DEVSEL;
397 break;
398 default:
399 BUG();
400 }
401 stmp3xxx_clearl(mask << shift, c);
402 stmp3xxx_setl(mask << shift, c);
403}
404EXPORT_SYMBOL(stmp3xxx_dma_set_alt_target);
405
406void stmp3xxx_dma_suspend(void)
407{
408 stmp3xxx_setl(BM_APBH_CTRL0_CLKGATE, REGS_APBH_BASE + HW_APBH_CTRL0);
409 stmp3xxx_setl(BM_APBX_CTRL0_CLKGATE, REGS_APBX_BASE + HW_APBX_CTRL0);
410}
411
412void stmp3xxx_dma_resume(void)
413{
414 stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
415 REGS_APBH_BASE + HW_APBH_CTRL0);
416 stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
417 REGS_APBX_BASE + HW_APBX_CTRL0);
418}
419
420#ifdef CONFIG_CPU_FREQ
421
422struct dma_notifier_block {
423 struct notifier_block nb;
424 void *data;
425};
426
427static int dma_cpufreq_notifier(struct notifier_block *self,
428 unsigned long phase, void *p)
429{
430 switch (phase) {
431 case CPUFREQ_POSTCHANGE:
432 stmp3xxx_dma_resume();
433 break;
434
435 case CPUFREQ_PRECHANGE:
436 stmp3xxx_dma_suspend();
437 break;
438
439 default:
440 break;
441 }
442
443 return NOTIFY_DONE;
444}
445
446static struct dma_notifier_block dma_cpufreq_nb = {
447 .nb = {
448 .notifier_call = dma_cpufreq_notifier,
449 },
450};
451#endif /* CONFIG_CPU_FREQ */
452
453void __init stmp3xxx_dma_init(void)
454{
455 stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
456 REGS_APBH_BASE + HW_APBH_CTRL0);
457 stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
458 REGS_APBX_BASE + HW_APBX_CTRL0);
459#ifdef CONFIG_CPU_FREQ
460 cpufreq_register_notifier(&dma_cpufreq_nb.nb,
461 CPUFREQ_TRANSITION_NOTIFIER);
462#endif /* CONFIG_CPU_FREQ */
463}
diff --git a/arch/arm/plat-stmp3xxx/include/mach/clkdev.h b/arch/arm/plat-stmp3xxx/include/mach/clkdev.h
new file mode 100644
index 000000000000..f9c39772d7c5
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/clkdev.h
@@ -0,0 +1,18 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12#ifndef __ASM_MACH_CLKDEV_H
13#define __ASM_MACH_CLKDEV_H
14
15#define __clk_get(clk) ({ 1; })
16#define __clk_put(clk) do { } while (0)
17
18#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/cputype.h b/arch/arm/plat-stmp3xxx/include/mach/cputype.h
new file mode 100644
index 000000000000..b4e205b95f2c
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/cputype.h
@@ -0,0 +1,33 @@
1/*
2 * Freescale STMP37XX/STMP378X CPU type detection
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_CPU_H
19#define __ASM_PLAT_CPU_H
20
21#ifdef CONFIG_ARCH_STMP37XX
22#define cpu_is_stmp37xx() (1)
23#else
24#define cpu_is_stmp37xx() (0)
25#endif
26
27#ifdef CONFIG_ARCH_STMP378X
28#define cpu_is_stmp378x() (1)
29#else
30#define cpu_is_stmp378x() (0)
31#endif
32
33#endif /* __ASM_PLAT_CPU_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
new file mode 100644
index 000000000000..fb3b969bf0a2
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
@@ -0,0 +1,42 @@
1/*
2 * Debugging macro include header
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18
19 .macro addruart,rx
20 mrc p15, 0, \rx, c1, c0
21 tst \rx, #1 @ MMU enabled?
22 moveq \rx, #0x80000000 @ physical base address
23 addeq \rx, \rx, #0x00070000
24 movne \rx, #0xf0000000 @ virtual base
25 addne \rx, \rx, #0x00070000
26 .endm
27
28 .macro senduart,rd,rx
29 strb \rd, [\rx, #0] @ data register at 0
30 .endm
31
32 .macro waituart,rd,rx
331001: ldr \rd, [\rx, #0x18] @ UARTFLG
34 tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
35 bne 1001b
36 .endm
37
38 .macro busyuart,rd,rx
391001: ldr \rd, [\rx, #0x18] @ UARTFLG
40 tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
41 bne 1001b
42 .endm
diff --git a/arch/arm/plat-stmp3xxx/include/mach/dma.h b/arch/arm/plat-stmp3xxx/include/mach/dma.h
new file mode 100644
index 000000000000..7c58557c6766
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/dma.h
@@ -0,0 +1,153 @@
1/*
2 * Freescale STMP37XX/STMP378X DMA helper interface
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_STMP3XXX_DMA_H
19#define __ASM_PLAT_STMP3XXX_DMA_H
20
21#include <linux/platform_device.h>
22#include <linux/dmapool.h>
23
24#if !defined(MAX_PIO_WORDS)
25#define MAX_PIO_WORDS (15)
26#endif
27
28#define STMP3XXX_BUS_APBH 0
29#define STMP3XXX_BUS_APBX 1
30#define STMP3XXX_DMA_MAX_CHANNEL 16
31#define STMP3XXX_DMA_BUS(dma) ((dma) / 16)
32#define STMP3XXX_DMA_CHANNEL(dma) ((dma) % 16)
33#define STMP3XXX_DMA(channel, bus) ((bus) * 16 + (channel))
34#define MAX_DMA_ADDRESS 0xffffffff
35#define MAX_DMA_CHANNELS 32
36
37struct stmp3xxx_dma_command {
38 u32 next;
39 u32 cmd;
40 union {
41 u32 buf_ptr;
42 u32 alternate;
43 };
44 u32 pio_words[MAX_PIO_WORDS];
45};
46
47struct stmp3xxx_dma_descriptor {
48 struct stmp3xxx_dma_command *command;
49 dma_addr_t handle;
50
51 /* The virtual address of the buffer pointer */
52 void *virtual_buf_ptr;
53 /* The next descriptor in a the DMA chain (optional) */
54 struct stmp3xxx_dma_descriptor *next_descr;
55};
56
57struct stmp37xx_circ_dma_chain {
58 unsigned total_count;
59 struct stmp3xxx_dma_descriptor *chain;
60
61 unsigned free_index;
62 unsigned free_count;
63 unsigned active_index;
64 unsigned active_count;
65 unsigned cooked_index;
66 unsigned cooked_count;
67
68 int bus;
69 unsigned channel;
70};
71
72static inline struct stmp3xxx_dma_descriptor
73 *stmp3xxx_dma_circ_get_free_head(struct stmp37xx_circ_dma_chain *chain)
74{
75 return &(chain->chain[chain->free_index]);
76}
77
78static inline struct stmp3xxx_dma_descriptor
79 *stmp3xxx_dma_circ_get_cooked_head(struct stmp37xx_circ_dma_chain *chain)
80{
81 return &(chain->chain[chain->cooked_index]);
82}
83
84int stmp3xxx_dma_request(int ch, struct device *dev, const char *name);
85int stmp3xxx_dma_release(int ch);
86int stmp3xxx_dma_allocate_command(int ch,
87 struct stmp3xxx_dma_descriptor *descriptor);
88int stmp3xxx_dma_free_command(int ch,
89 struct stmp3xxx_dma_descriptor *descriptor);
90void stmp3xxx_dma_continue(int channel, u32 semaphore);
91void stmp3xxx_dma_go(int ch, struct stmp3xxx_dma_descriptor *head,
92 u32 semaphore);
93int stmp3xxx_dma_running(int ch);
94int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
95 struct stmp3xxx_dma_descriptor descriptors[],
96 unsigned items);
97void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain);
98void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain);
99void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain,
100 unsigned count);
101void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
102 unsigned count);
103unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain);
104int stmp3xxx_dma_read_semaphore(int ch);
105void stmp3xxx_dma_init(void);
106void stmp3xxx_dma_set_alt_target(int ch, int target);
107void stmp3xxx_dma_suspend(void);
108void stmp3xxx_dma_resume(void);
109
110/*
111 * STMP37xx and STMP378x have different DMA control
112 * registers layout
113 */
114
115void stmp3xxx_arch_dma_freeze(int ch);
116void stmp3xxx_arch_dma_unfreeze(int ch);
117void stmp3xxx_arch_dma_reset_channel(int ch);
118void stmp3xxx_arch_dma_enable_interrupt(int ch);
119void stmp3xxx_arch_dma_clear_interrupt(int ch);
120int stmp3xxx_arch_dma_is_interrupt(int ch);
121
122static inline void stmp3xxx_dma_reset_channel(int ch)
123{
124 stmp3xxx_arch_dma_reset_channel(ch);
125}
126
127
128static inline void stmp3xxx_dma_freeze(int ch)
129{
130 stmp3xxx_arch_dma_freeze(ch);
131}
132
133static inline void stmp3xxx_dma_unfreeze(int ch)
134{
135 stmp3xxx_arch_dma_unfreeze(ch);
136}
137
138static inline void stmp3xxx_dma_enable_interrupt(int ch)
139{
140 stmp3xxx_arch_dma_enable_interrupt(ch);
141}
142
143static inline void stmp3xxx_dma_clear_interrupt(int ch)
144{
145 stmp3xxx_arch_dma_clear_interrupt(ch);
146}
147
148static inline int stmp3xxx_dma_is_interrupt(int ch)
149{
150 return stmp3xxx_arch_dma_is_interrupt(ch);
151}
152
153#endif /* __ASM_PLAT_STMP3XXX_DMA_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpio.h b/arch/arm/plat-stmp3xxx/include/mach/gpio.h
new file mode 100644
index 000000000000..a8b579256170
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/gpio.h
@@ -0,0 +1,28 @@
1/*
2 * Freescale STMP37XX/STMP378X GPIO interface
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_GPIO_H
19#define __ASM_PLAT_GPIO_H
20
21#define ARCH_NR_GPIOS (32 * 3)
22#define gpio_to_irq(gpio) __gpio_to_irq(gpio)
23#define gpio_get_value(gpio) __gpio_get_value(gpio)
24#define gpio_set_value(gpio, value) __gpio_set_value(gpio, value)
25
26#include <asm-generic/gpio.h>
27
28#endif /* __ASM_PLAT_GPIO_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpmi.h b/arch/arm/plat-stmp3xxx/include/mach/gpmi.h
new file mode 100644
index 000000000000..e166432910ad
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/gpmi.h
@@ -0,0 +1,12 @@
1#ifndef __MACH_GPMI_H
2
3#include <linux/mtd/partitions.h>
4#include <mach/regs-gpmi.h>
5
6struct gpmi_platform_data {
7 void *pins;
8 int nr_parts;
9 struct mtd_partition *parts;
10 const char *part_types[];
11};
12#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/hardware.h b/arch/arm/plat-stmp3xxx/include/mach/hardware.h
new file mode 100644
index 000000000000..47b8978405bc
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/hardware.h
@@ -0,0 +1,32 @@
1/*
2 * This file contains the hardware definitions of the Freescale STMP3XXX
3 *
4 * Copyright (C) 2005 Sigmatel Inc
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_ARCH_HARDWARE_H
19#define __ASM_ARCH_HARDWARE_H
20
21/*
22 * Where in virtual memory the IO devices (timers, system controllers
23 * and so on)
24 */
25#define IO_BASE 0xF0000000 /* VA of IO */
26#define IO_SIZE 0x00100000 /* How much? */
27#define IO_START 0x80000000 /* PA of IO */
28
29/* macro to get at IO space when running virtually */
30#define IO_ADDRESS(x) (((x) & 0x000fffff) | IO_BASE)
31
32#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/io.h b/arch/arm/plat-stmp3xxx/include/mach/io.h
new file mode 100644
index 000000000000..d08b1b7f3d1c
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/io.h
@@ -0,0 +1,25 @@
1/*
2 * Copyright (C) 2005 Sigmatel Inc
3 *
4 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 */
7
8/*
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16#ifndef __ASM_ARM_ARCH_IO_H
17#define __ASM_ARM_ARCH_IO_H
18
19#define IO_SPACE_LIMIT 0xffffffff
20
21#define __io(a) __typesafe_io(a)
22#define __mem_pci(a) (a)
23#define __mem_isa(a) (a)
24
25#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/memory.h b/arch/arm/plat-stmp3xxx/include/mach/memory.h
new file mode 100644
index 000000000000..7b875a07a1a7
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/memory.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 */
5
6/*
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14#ifndef __ASM_ARCH_MEMORY_H
15#define __ASM_ARCH_MEMORY_H
16
17/*
18 * Physical DRAM offset.
19 */
20#define PHYS_OFFSET UL(0x40000000)
21
22#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/mmc.h b/arch/arm/plat-stmp3xxx/include/mach/mmc.h
new file mode 100644
index 000000000000..ba81e1543761
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/mmc.h
@@ -0,0 +1,14 @@
1#ifndef _MACH_MMC_H
2#define _MACH_MMC_H
3
4#include <mach/regs-ssp.h>
5
6struct stmp3xxxmmc_platform_data {
7 int (*get_wp)(void);
8 unsigned long (*setclock)(void __iomem *base, unsigned long);
9 void (*cmd_pullup)(int);
10 int (*hw_init)(void);
11 void (*hw_release)(void);
12};
13
14#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h b/arch/arm/plat-stmp3xxx/include/mach/pinmux.h
new file mode 100644
index 000000000000..cc5af82279ad
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/pinmux.h
@@ -0,0 +1,157 @@
1/*
2 * Freescale STMP37XX/STMP378X Pin Multiplexing
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __PINMUX_H
19#define __PINMUX_H
20
21#include <linux/spinlock.h>
22#include <linux/types.h>
23#include <linux/gpio.h>
24#include <asm-generic/gpio.h>
25
26/* Pin definitions */
27#include "pins.h"
28#include <mach/pins.h>
29
30/*
31 * Each pin may be routed up to four different HW interfaces
32 * including GPIO
33 */
34enum pin_fun {
35 PIN_FUN1 = 0,
36 PIN_FUN2,
37 PIN_FUN3,
38 PIN_GPIO,
39};
40
41/*
42 * Each pin may have different output drive strength in range from
43 * 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths.
44 */
45enum pin_strength {
46 PIN_4MA = 0,
47 PIN_8MA,
48 PIN_12MA,
49 PIN_16MA,
50 PIN_20MA,
51};
52
53/*
54 * Each pin can be programmed for 1.8V or 3.3V
55 */
56enum pin_voltage {
57 PIN_1_8V = 0,
58 PIN_3_3V,
59};
60
61/*
62 * Structure to define a group of pins and their parameters
63 */
64struct pin_desc {
65 unsigned id;
66 enum pin_fun fun;
67 enum pin_strength strength;
68 enum pin_voltage voltage;
69 unsigned pullup:1;
70};
71
72struct pin_group {
73 struct pin_desc *pins;
74 int nr_pins;
75};
76
77/* Set pin drive strength */
78void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
79 const char *label);
80
81/* Set pin voltage */
82void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
83 const char *label);
84
85/* Enable pull-up resistor for a pin */
86void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label);
87
88/*
89 * Request a pin ownership, only one module (identified by @label)
90 * may own a pin.
91 */
92int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label);
93
94/* Release pin */
95void stmp3xxx_release_pin(unsigned id, const char *label);
96
97void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun);
98
99/*
100 * Each bank is associated with a number of registers to control
101 * pin function, drive strength, voltage and pull-up reigster. The
102 * number of registers of a given type depends on the number of bits
103 * describin particular pin.
104 */
105#define HW_MUXSEL_NUM 2 /* registers per bank */
106#define HW_MUXSEL_PIN_LEN 2 /* bits per pin */
107#define HW_MUXSEL_PIN_NUM 16 /* pins per register */
108#define HW_MUXSEL_PINFUN_MASK 0x3 /* pin function mask */
109#define HW_MUXSEL_PINFUN_NUM 4 /* four options for a pin */
110
111#define HW_DRIVE_NUM 4 /* registers per bank */
112#define HW_DRIVE_PIN_LEN 4 /* bits per pin */
113#define HW_DRIVE_PIN_NUM 8 /* pins per register */
114#define HW_DRIVE_PINDRV_MASK 0x3 /* pin strength mask - 2 bits */
115#define HW_DRIVE_PINDRV_NUM 5 /* five possible strength values */
116#define HW_DRIVE_PINV_MASK 0x4 /* pin voltage mask - 1 bit */
117
118
119struct stmp3xxx_pinmux_bank {
120 struct gpio_chip chip;
121
122 /* Pins allocation map */
123 unsigned long pin_map;
124
125 /* Pin owner names */
126 const char *pin_labels[32];
127
128 /* Bank registers */
129 void __iomem *hw_muxsel[HW_MUXSEL_NUM];
130 void __iomem *hw_drive[HW_DRIVE_NUM];
131 void __iomem *hw_pull;
132
133 void __iomem *pin2irq,
134 *irqlevel,
135 *irqpolarity,
136 *irqen,
137 *irqstat;
138
139 /* HW MUXSEL register function bit values */
140 u8 functions[HW_MUXSEL_PINFUN_NUM];
141
142 /*
143 * HW DRIVE register strength bit values:
144 * 0xff - requested strength is not supported for this bank
145 */
146 u8 strengths[HW_DRIVE_PINDRV_NUM];
147
148 /* GPIO things */
149 void __iomem *hw_gpio_in,
150 *hw_gpio_out,
151 *hw_gpio_doe;
152 int irq, virq;
153};
154
155int __init stmp3xxx_pinmux_init(int virtual_irq_start);
156
157#endif /* __PINMUX_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/pins.h b/arch/arm/plat-stmp3xxx/include/mach/pins.h
new file mode 100644
index 000000000000..c573318e1caa
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/pins.h
@@ -0,0 +1,30 @@
1/*
2 * Freescale STMP37XX/STMP378X Pin multiplexing interface definitions
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_PINS_H
19#define __ASM_PLAT_PINS_H
20
21#define STMP3XXX_PINID(bank, pin) (bank * 32 + pin)
22#define STMP3XXX_PINID_TO_BANK(pinid) (pinid / 32)
23#define STMP3XXX_PINID_TO_PINNUM(pinid) (pinid % 32)
24
25/*
26 * Special invalid pin identificator to show a pin doesn't exist
27 */
28#define PINID_NO_PIN STMP3XXX_PINID(0xFF, 0xFF)
29
30#endif /* __ASM_PLAT_PINS_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/platform.h b/arch/arm/plat-stmp3xxx/include/mach/platform.h
new file mode 100644
index 000000000000..7007ddaa91eb
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/platform.h
@@ -0,0 +1,68 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 */
5
6/*
7 * The code contained herein is licensed under the GNU General Public
8 * License. You may obtain a copy of the GNU General Public License
9 * Version 2 or later at the following locations:
10 *
11 * http://www.opensource.org/licenses/gpl-license.html
12 * http://www.gnu.org/copyleft/gpl.html
13 */
14#ifndef __ASM_PLAT_PLATFORM_H
15#define __ASM_PLAT_PLATFORM_H
16
17#ifndef __ASSEMBLER__
18#include <linux/io.h>
19#endif
20#include <asm/sizes.h>
21
22/* Virtual address where registers are mapped */
23#define STMP3XXX_REGS_PHBASE 0x80000000
24#ifdef __ASSEMBLER__
25#define STMP3XXX_REGS_BASE 0xF0000000
26#else
27#define STMP3XXX_REGS_BASE (void __iomem *)0xF0000000
28#endif
29#define STMP3XXX_REGS_SIZE SZ_1M
30
31/* Virtual address where OCRAM is mapped */
32#define STMP3XXX_OCRAM_PHBASE 0x00000000
33#ifdef __ASSEMBLER__
34#define STMP3XXX_OCRAM_BASE 0xf1000000
35#else
36#define STMP3XXX_OCRAM_BASE (void __iomem *)0xf1000000
37#endif
38#define STMP3XXX_OCRAM_SIZE (32 * SZ_1K)
39
40#ifdef CONFIG_ARCH_STMP37XX
41#define IRQ_PRIORITY_REG_RD HW_ICOLL_PRIORITYn_RD
42#define IRQ_PRIORITY_REG_WR HW_ICOLL_PRIORITYn_WR
43#endif
44
45#ifdef CONFIG_ARCH_STMP378X
46#define IRQ_PRIORITY_REG_RD HW_ICOLL_INTERRUPTn_RD
47#define IRQ_PRIORITY_REG_WR HW_ICOLL_INTERRUPTn_WR
48#endif
49
50#define HW_STMP3XXX_SET 0x04
51#define HW_STMP3XXX_CLR 0x08
52#define HW_STMP3XXX_TOG 0x0c
53
54#ifndef __ASSEMBLER__
55static inline void stmp3xxx_clearl(u32 v, void __iomem *r)
56{
57 __raw_writel(v, r + HW_STMP3XXX_CLR);
58}
59
60static inline void stmp3xxx_setl(u32 v, void __iomem *r)
61{
62 __raw_writel(v, r + HW_STMP3XXX_SET);
63}
64#endif
65
66#define BF(value, field) (((value) << BP_##field) & BM_##field)
67
68#endif /* __ASM_ARCH_PLATFORM_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h
new file mode 100644
index 000000000000..2e300feaa4cf
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h
@@ -0,0 +1,54 @@
1/*
2 * Freescale STMP37XX/STMP378X core structure and function declarations
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_PLAT_STMP3XXX_H
19#define __ASM_PLAT_STMP3XXX_H
20
21#include <linux/irq.h>
22
23extern struct sys_timer stmp3xxx_timer;
24
25void stmp3xxx_init_irq(struct irq_chip *chip);
26void stmp3xxx_init(void);
27int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable);
28extern struct platform_device stmp3xxx_dbguart,
29 stmp3xxx_appuart,
30 stmp3xxx_watchdog,
31 stmp3xxx_touchscreen,
32 stmp3xxx_keyboard,
33 stmp3xxx_gpmi,
34 stmp3xxx_mmc,
35 stmp3xxx_udc,
36 stmp3xxx_ehci,
37 stmp3xxx_rtc,
38 stmp3xxx_spi1,
39 stmp3xxx_spi2,
40 stmp3xxx_backlight,
41 stmp3xxx_rotdec,
42 stmp3xxx_dcp,
43 stmp3xxx_dcp_bootstream,
44 stmp3xxx_persistent,
45 stmp3xxx_framebuffer,
46 stmp3xxx_battery;
47int stmp3xxx_ssp1_device_register(void);
48int stmp3xxx_ssp2_device_register(void);
49
50struct pin_group;
51void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label);
52int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label);
53
54#endif /* __ASM_PLAT_STMP3XXX_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/system.h b/arch/arm/plat-stmp3xxx/include/mach/system.h
new file mode 100644
index 000000000000..28a988889319
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/system.h
@@ -0,0 +1,49 @@
1/*
2 * Copyright (C) 2005 Sigmatel Inc
3 *
4 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 */
7
8/*
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16#ifndef __ASM_ARCH_SYSTEM_H
17#define __ASM_ARCH_SYSTEM_H
18
19#include <asm/proc-fns.h>
20#include <mach/platform.h>
21#include <mach/regs-clkctrl.h>
22#include <mach/regs-power.h>
23
24static inline void arch_idle(void)
25{
26 /*
27 * This should do all the clock switching
28 * and wait for interrupt tricks
29 */
30
31 cpu_do_idle();
32}
33
34static inline void arch_reset(char mode, const char *cmd)
35{
36 /* Set BATTCHRG to default value */
37 __raw_writel(0x00010000, REGS_POWER_BASE + HW_POWER_CHARGE);
38
39 /* Set MINPWR to default value */
40 __raw_writel(0, REGS_POWER_BASE + HW_POWER_MINPWR);
41
42 /* Reset digital side of chip (but not power or RTC) */
43 __raw_writel(BM_CLKCTRL_RESET_DIG,
44 REGS_CLKCTRL_BASE + HW_CLKCTRL_RESET);
45
46 /* Should not return */
47}
48
49#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/timex.h b/arch/arm/plat-stmp3xxx/include/mach/timex.h
new file mode 100644
index 000000000000..3373985d7a8e
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/timex.h
@@ -0,0 +1,20 @@
1/*
2 * Copyright (C) 1999 ARM Limited
3 *
4 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 */
7
8/*
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17/*
18 * System time clock is sourced from the 32k clock
19 */
20#define CLOCK_TICK_RATE (32768)
diff --git a/arch/arm/plat-stmp3xxx/include/mach/uncompress.h b/arch/arm/plat-stmp3xxx/include/mach/uncompress.h
new file mode 100644
index 000000000000..f79f5ee56cd4
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/uncompress.h
@@ -0,0 +1,53 @@
1/*
2 *
3 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
5 */
6
7/*
8 * The code contained herein is licensed under the GNU General Public
9 * License. You may obtain a copy of the GNU General Public License
10 * Version 2 or later at the following locations:
11 *
12 * http://www.opensource.org/licenses/gpl-license.html
13 * http://www.gnu.org/copyleft/gpl.html
14 */
15#ifndef __ASM_PLAT_UNCOMPRESS_H
16#define __ASM_PLAT_UNCOMPRESS_H
17
18/*
19 * Register includes are for when the MMU enabled; we need to define our
20 * own stuff here for pre-MMU use
21 */
22#define UARTDBG_BASE 0x80070000
23#define UART(c) (((volatile unsigned *)UARTDBG_BASE)[c])
24
25/*
26 * This does not append a newline
27 */
28static void putc(char c)
29{
30 /* Wait for TX fifo empty */
31 while ((UART(6) & (1<<7)) == 0)
32 continue;
33
34 /* Write byte */
35 UART(0) = c;
36
37 /* Wait for last bit to exit the UART */
38 while (UART(6) & (1<<3))
39 continue;
40}
41
42static void flush(void)
43{
44}
45
46/*
47 * nothing to do
48 */
49#define arch_decomp_setup()
50
51#define arch_decomp_wdog()
52
53#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..541b880c1863
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
@@ -0,0 +1,12 @@
1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12#define VMALLOC_END (0xF0000000)
diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c
new file mode 100644
index 000000000000..20de4e0401ef
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/irq.c
@@ -0,0 +1,51 @@
1/*
2 * Freescale STMP37XX/STMP378X common interrupt handling code
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/delay.h>
21#include <linux/irq.h>
22#include <linux/sysdev.h>
23
24#include <mach/stmp3xxx.h>
25#include <mach/platform.h>
26#include <mach/regs-icoll.h>
27
28void __init stmp3xxx_init_irq(struct irq_chip *chip)
29{
30 unsigned int i, lv;
31
32 /* Reset the interrupt controller */
33 stmp3xxx_reset_block(REGS_ICOLL_BASE + HW_ICOLL_CTRL, true);
34
35 /* Disable all interrupts initially */
36 for (i = 0; i < NR_REAL_IRQS; i++) {
37 chip->mask(i);
38 set_irq_chip(i, chip);
39 set_irq_handler(i, handle_level_irq);
40 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
41 }
42
43 /* Ensure vector is cleared */
44 for (lv = 0; lv < 4; lv++)
45 __raw_writel(1 << lv, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
46 __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
47
48 /* Barrier */
49 (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
50}
51
diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c
new file mode 100644
index 000000000000..d41200382208
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/pinmux.c
@@ -0,0 +1,552 @@
1/*
2 * Freescale STMP378X/STMP378X Pin Multiplexing
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#define DEBUG
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/errno.h>
22#include <linux/sysdev.h>
23#include <linux/string.h>
24#include <linux/bitops.h>
25#include <linux/sysdev.h>
26#include <linux/irq.h>
27
28#include <mach/hardware.h>
29#include <mach/platform.h>
30#include <mach/regs-pinctrl.h>
31#include <mach/pins.h>
32#include <mach/pinmux.h>
33
34#define NR_BANKS ARRAY_SIZE(pinmux_banks)
35static struct stmp3xxx_pinmux_bank pinmux_banks[] = {
36 [0] = {
37 .hw_muxsel = {
38 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0,
39 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1,
40 },
41 .hw_drive = {
42 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0,
43 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1,
44 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2,
45 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3,
46 },
47 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL0,
48 .functions = { 0x0, 0x1, 0x2, 0x3 },
49 .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
50
51 .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN0,
52 .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0,
53 .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE0,
54 .irq = IRQ_GPIO0,
55
56 .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0,
57 .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0,
58 .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0,
59 .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0,
60 .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0,
61 },
62 [1] = {
63 .hw_muxsel = {
64 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2,
65 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3,
66 },
67 .hw_drive = {
68 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4,
69 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5,
70 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6,
71 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7,
72 },
73 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL1,
74 .functions = { 0x0, 0x1, 0x2, 0x3 },
75 .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
76
77 .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN1,
78 .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1,
79 .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE1,
80 .irq = IRQ_GPIO1,
81
82 .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1,
83 .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1,
84 .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1,
85 .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1,
86 .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1,
87 },
88 [2] = {
89 .hw_muxsel = {
90 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4,
91 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5,
92 },
93 .hw_drive = {
94 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8,
95 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9,
96 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10,
97 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11,
98 },
99 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL2,
100 .functions = { 0x0, 0x1, 0x2, 0x3 },
101 .strengths = { 0x0, 0x1, 0x2, 0x1, 0x2 },
102
103 .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN2,
104 .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2,
105 .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE2,
106 .irq = IRQ_GPIO2,
107
108 .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2,
109 .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2,
110 .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2,
111 .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2,
112 .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2,
113 },
114 [3] = {
115 .hw_muxsel = {
116 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6,
117 REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7,
118 },
119 .hw_drive = {
120 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12,
121 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13,
122 REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14,
123 NULL,
124 },
125 .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL3,
126 .functions = {0x0, 0x1, 0x2, 0x3},
127 .strengths = {0x0, 0x1, 0x2, 0x3, 0xff},
128 },
129};
130
131static inline struct stmp3xxx_pinmux_bank *
132stmp3xxx_pinmux_bank(unsigned id, unsigned *bank, unsigned *pin)
133{
134 unsigned b, p;
135
136 b = STMP3XXX_PINID_TO_BANK(id);
137 p = STMP3XXX_PINID_TO_PINNUM(id);
138 BUG_ON(b >= NR_BANKS);
139 if (bank)
140 *bank = b;
141 if (pin)
142 *pin = p;
143 return &pinmux_banks[b];
144}
145
146/* Check if requested pin is owned by caller */
147static int stmp3xxx_check_pin(unsigned id, const char *label)
148{
149 unsigned pin;
150 struct stmp3xxx_pinmux_bank *pm = stmp3xxx_pinmux_bank(id, NULL, &pin);
151
152 if (!test_bit(pin, &pm->pin_map)) {
153 printk(KERN_WARNING
154 "%s: Accessing free pin %x, caller %s\n",
155 __func__, id, label);
156
157 return -EINVAL;
158 }
159
160 if (label && pm->pin_labels[pin] &&
161 strcmp(label, pm->pin_labels[pin])) {
162 printk(KERN_WARNING
163 "%s: Wrong pin owner %x, caller %s owner %s\n",
164 __func__, id, label, pm->pin_labels[pin]);
165
166 return -EINVAL;
167 }
168 return 0;
169}
170
171void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
172 const char *label)
173{
174 struct stmp3xxx_pinmux_bank *pbank;
175 void __iomem *hwdrive;
176 u32 shift, val;
177 u32 bank, pin;
178
179 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
180 pr_debug("%s: label %s bank %d pin %d strength %d\n", __func__, label,
181 bank, pin, strength);
182
183 hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM];
184 shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN;
185 val = pbank->strengths[strength];
186 if (val == 0xff) {
187 printk(KERN_WARNING
188 "%s: strength is not supported for bank %d, caller %s",
189 __func__, bank, label);
190 return;
191 }
192
193 if (stmp3xxx_check_pin(id, label))
194 return;
195
196 pr_debug("%s: writing 0x%x to 0x%p register\n", __func__,
197 val << shift, hwdrive);
198 stmp3xxx_clearl(HW_DRIVE_PINDRV_MASK << shift, hwdrive);
199 stmp3xxx_setl(val << shift, hwdrive);
200}
201
202void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
203 const char *label)
204{
205 struct stmp3xxx_pinmux_bank *pbank;
206 void __iomem *hwdrive;
207 u32 shift;
208 u32 bank, pin;
209
210 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
211 pr_debug("%s: label %s bank %d pin %d voltage %d\n", __func__, label,
212 bank, pin, voltage);
213
214 hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM];
215 shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN;
216
217 if (stmp3xxx_check_pin(id, label))
218 return;
219
220 pr_debug("%s: changing 0x%x bit in 0x%p register\n",
221 __func__, HW_DRIVE_PINV_MASK << shift, hwdrive);
222 if (voltage == PIN_1_8V)
223 stmp3xxx_clearl(HW_DRIVE_PINV_MASK << shift, hwdrive);
224 else
225 stmp3xxx_setl(HW_DRIVE_PINV_MASK << shift, hwdrive);
226}
227
228void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label)
229{
230 struct stmp3xxx_pinmux_bank *pbank;
231 void __iomem *hwpull;
232 u32 bank, pin;
233
234 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
235 pr_debug("%s: label %s bank %d pin %d enable %d\n", __func__, label,
236 bank, pin, enable);
237
238 hwpull = pbank->hw_pull;
239
240 if (stmp3xxx_check_pin(id, label))
241 return;
242
243 pr_debug("%s: changing 0x%x bit in 0x%p register\n",
244 __func__, 1 << pin, hwpull);
245 if (enable)
246 stmp3xxx_setl(1 << pin, hwpull);
247 else
248 stmp3xxx_clearl(1 << pin, hwpull);
249}
250
251int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label)
252{
253 struct stmp3xxx_pinmux_bank *pbank;
254 u32 bank, pin;
255 int ret = 0;
256
257 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
258 pr_debug("%s: label %s bank %d pin %d fun %d\n", __func__, label,
259 bank, pin, fun);
260
261 if (test_bit(pin, &pbank->pin_map)) {
262 printk(KERN_WARNING
263 "%s: CONFLICT DETECTED pin %d:%d caller %s owner %s\n",
264 __func__, bank, pin, label, pbank->pin_labels[pin]);
265 return -EBUSY;
266 }
267
268 set_bit(pin, &pbank->pin_map);
269 pbank->pin_labels[pin] = label;
270
271 stmp3xxx_set_pin_type(id, fun);
272
273 return ret;
274}
275
276void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun)
277{
278 struct stmp3xxx_pinmux_bank *pbank;
279 void __iomem *hwmux;
280 u32 shift, val;
281 u32 bank, pin;
282
283 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
284
285 hwmux = pbank->hw_muxsel[pin / HW_MUXSEL_PIN_NUM];
286 shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
287
288 val = pbank->functions[fun];
289 shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
290 pr_debug("%s: writing 0x%x to 0x%p register\n",
291 __func__, val << shift, hwmux);
292 stmp3xxx_clearl(HW_MUXSEL_PINFUN_MASK << shift, hwmux);
293 stmp3xxx_setl(val << shift, hwmux);
294}
295
296void stmp3xxx_release_pin(unsigned id, const char *label)
297{
298 struct stmp3xxx_pinmux_bank *pbank;
299 u32 bank, pin;
300
301 pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
302 pr_debug("%s: label %s bank %d pin %d\n", __func__, label, bank, pin);
303
304 if (stmp3xxx_check_pin(id, label))
305 return;
306
307 clear_bit(pin, &pbank->pin_map);
308 pbank->pin_labels[pin] = NULL;
309}
310
311int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label)
312{
313 struct pin_desc *pin;
314 int p;
315 int err = 0;
316
317 /* Allocate and configure pins */
318 for (p = 0; p < pin_group->nr_pins; p++) {
319 pr_debug("%s: #%d\n", __func__, p);
320 pin = &pin_group->pins[p];
321
322 err = stmp3xxx_request_pin(pin->id, pin->fun, label);
323 if (err)
324 goto out_err;
325
326 stmp3xxx_pin_strength(pin->id, pin->strength, label);
327 stmp3xxx_pin_voltage(pin->id, pin->voltage, label);
328 stmp3xxx_pin_pullup(pin->id, pin->pullup, label);
329 }
330
331 return 0;
332
333out_err:
334 /* Release allocated pins in case of error */
335 while (--p >= 0) {
336 pr_debug("%s: releasing #%d\n", __func__, p);
337 stmp3xxx_release_pin(pin_group->pins[p].id, label);
338 }
339 return err;
340}
341EXPORT_SYMBOL(stmp3xxx_request_pin_group);
342
343void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label)
344{
345 struct pin_desc *pin;
346 int p;
347
348 for (p = 0; p < pin_group->nr_pins; p++) {
349 pin = &pin_group->pins[p];
350 stmp3xxx_release_pin(pin->id, label);
351 }
352}
353EXPORT_SYMBOL(stmp3xxx_release_pin_group);
354
355static int stmp3xxx_irq_to_gpio(int irq,
356 struct stmp3xxx_pinmux_bank **bank, unsigned *gpio)
357{
358 struct stmp3xxx_pinmux_bank *pm;
359
360 for (pm = pinmux_banks; pm < pinmux_banks + NR_BANKS; pm++)
361 if (pm->virq <= irq && irq < pm->virq + 32) {
362 *bank = pm;
363 *gpio = irq - pm->virq;
364 return 0;
365 }
366 return -ENOENT;
367}
368
369static int stmp3xxx_set_irqtype(unsigned irq, unsigned type)
370{
371 struct stmp3xxx_pinmux_bank *pm;
372 unsigned gpio;
373 int l, p;
374
375 stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
376 switch (type) {
377 case IRQ_TYPE_EDGE_RISING:
378 l = 0; p = 1; break;
379 case IRQ_TYPE_EDGE_FALLING:
380 l = 0; p = 0; break;
381 case IRQ_TYPE_LEVEL_HIGH:
382 l = 1; p = 1; break;
383 case IRQ_TYPE_LEVEL_LOW:
384 l = 1; p = 0; break;
385 default:
386 pr_debug("%s: Incorrect GPIO interrupt type 0x%x\n",
387 __func__, type);
388 return -ENXIO;
389 }
390
391 if (l)
392 stmp3xxx_setl(1 << gpio, pm->irqlevel);
393 else
394 stmp3xxx_clearl(1 << gpio, pm->irqlevel);
395 if (p)
396 stmp3xxx_setl(1 << gpio, pm->irqpolarity);
397 else
398 stmp3xxx_clearl(1 << gpio, pm->irqpolarity);
399 return 0;
400}
401
402static void stmp3xxx_pin_ack_irq(unsigned irq)
403{
404 u32 stat;
405 struct stmp3xxx_pinmux_bank *pm;
406 unsigned gpio;
407
408 stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
409 stat = __raw_readl(pm->irqstat) & (1 << gpio);
410 stmp3xxx_clearl(stat, pm->irqstat);
411}
412
413static void stmp3xxx_pin_mask_irq(unsigned irq)
414{
415 struct stmp3xxx_pinmux_bank *pm;
416 unsigned gpio;
417
418 stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
419 stmp3xxx_clearl(1 << gpio, pm->irqen);
420 stmp3xxx_clearl(1 << gpio, pm->pin2irq);
421}
422
423static void stmp3xxx_pin_unmask_irq(unsigned irq)
424{
425 struct stmp3xxx_pinmux_bank *pm;
426 unsigned gpio;
427
428 stmp3xxx_irq_to_gpio(irq, &pm, &gpio);
429 stmp3xxx_setl(1 << gpio, pm->irqen);
430 stmp3xxx_setl(1 << gpio, pm->pin2irq);
431}
432
433static inline
434struct stmp3xxx_pinmux_bank *to_pinmux_bank(struct gpio_chip *chip)
435{
436 return container_of(chip, struct stmp3xxx_pinmux_bank, chip);
437}
438
439static int stmp3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
440{
441 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
442 return pm->virq + offset;
443}
444
445static int stmp3xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
446{
447 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
448 unsigned v;
449
450 v = __raw_readl(pm->hw_gpio_in) & (1 << offset);
451 return v ? 1 : 0;
452}
453
454static void stmp3xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int v)
455{
456 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
457
458 if (v)
459 stmp3xxx_setl(1 << offset, pm->hw_gpio_out);
460 else
461 stmp3xxx_clearl(1 << offset, pm->hw_gpio_out);
462}
463
464static int stmp3xxx_gpio_output(struct gpio_chip *chip, unsigned offset, int v)
465{
466 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
467
468 stmp3xxx_setl(1 << offset, pm->hw_gpio_doe);
469 stmp3xxx_gpio_set(chip, offset, v);
470 return 0;
471}
472
473static int stmp3xxx_gpio_input(struct gpio_chip *chip, unsigned offset)
474{
475 struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
476
477 stmp3xxx_clearl(1 << offset, pm->hw_gpio_doe);
478 return 0;
479}
480
481static int stmp3xxx_gpio_request(struct gpio_chip *chip, unsigned offset)
482{
483 return stmp3xxx_request_pin(chip->base + offset, PIN_GPIO, "gpio");
484}
485
486static void stmp3xxx_gpio_free(struct gpio_chip *chip, unsigned offset)
487{
488 stmp3xxx_release_pin(chip->base + offset, "gpio");
489}
490
491static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc)
492{
493 struct stmp3xxx_pinmux_bank *pm = get_irq_data(irq);
494 int gpio_irq = pm->virq;
495 u32 stat = __raw_readl(pm->irqstat);
496
497 while (stat) {
498 if (stat & 1)
499 irq_desc[gpio_irq].handle_irq(gpio_irq,
500 &irq_desc[gpio_irq]);
501 gpio_irq++;
502 stat >>= 1;
503 }
504}
505
506static struct irq_chip gpio_irq_chip = {
507 .ack = stmp3xxx_pin_ack_irq,
508 .mask = stmp3xxx_pin_mask_irq,
509 .unmask = stmp3xxx_pin_unmask_irq,
510 .set_type = stmp3xxx_set_irqtype,
511};
512
513int __init stmp3xxx_pinmux_init(int virtual_irq_start)
514{
515 int b, r = 0;
516 struct stmp3xxx_pinmux_bank *pm;
517 int virq;
518
519 for (b = 0; b < 3; b++) {
520 /* only banks 0,1,2 are allowed to GPIO */
521 pm = pinmux_banks + b;
522 pm->chip.base = 32 * b;
523 pm->chip.ngpio = 32;
524 pm->chip.owner = THIS_MODULE;
525 pm->chip.can_sleep = 1;
526 pm->chip.exported = 1;
527 pm->chip.to_irq = stmp3xxx_gpio_to_irq;
528 pm->chip.direction_input = stmp3xxx_gpio_input;
529 pm->chip.direction_output = stmp3xxx_gpio_output;
530 pm->chip.get = stmp3xxx_gpio_get;
531 pm->chip.set = stmp3xxx_gpio_set;
532 pm->chip.request = stmp3xxx_gpio_request;
533 pm->chip.free = stmp3xxx_gpio_free;
534 pm->virq = virtual_irq_start + b * 32;
535
536 for (virq = pm->virq; virq < pm->virq; virq++) {
537 gpio_irq_chip.mask(virq);
538 set_irq_chip(virq, &gpio_irq_chip);
539 set_irq_handler(virq, handle_level_irq);
540 set_irq_flags(virq, IRQF_VALID);
541 }
542 r = gpiochip_add(&pm->chip);
543 if (r < 0)
544 break;
545 set_irq_chained_handler(pm->irq, stmp3xxx_gpio_irq);
546 set_irq_data(pm->irq, pm);
547 }
548 return r;
549}
550
551MODULE_AUTHOR("Vladislav Buzov");
552MODULE_LICENSE("GPL");
diff --git a/arch/arm/plat-stmp3xxx/timer.c b/arch/arm/plat-stmp3xxx/timer.c
new file mode 100644
index 000000000000..063c7bc0e740
--- /dev/null
+++ b/arch/arm/plat-stmp3xxx/timer.c
@@ -0,0 +1,189 @@
1/*
2 * System timer for Freescale STMP37XX/STMP378X
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/spinlock.h>
21#include <linux/clocksource.h>
22#include <linux/clockchips.h>
23#include <linux/io.h>
24#include <linux/irq.h>
25#include <linux/interrupt.h>
26
27#include <asm/mach/time.h>
28#include <mach/stmp3xxx.h>
29#include <mach/platform.h>
30#include <mach/regs-timrot.h>
31
32static irqreturn_t
33stmp3xxx_timer_interrupt(int irq, void *dev_id)
34{
35 struct clock_event_device *c = dev_id;
36
37 /* timer 0 */
38 if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0) &
39 BM_TIMROT_TIMCTRLn_IRQ) {
40 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
41 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
42 c->event_handler(c);
43 }
44
45 /* timer 1 */
46 else if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1)
47 & BM_TIMROT_TIMCTRLn_IRQ) {
48 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
49 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
50 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN,
51 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
52 __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
53 }
54
55 return IRQ_HANDLED;
56}
57
58static cycle_t stmp3xxx_clock_read(struct clocksource *cs)
59{
60 return ~((__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1)
61 & 0xFFFF0000) >> 16);
62}
63
64static int
65stmp3xxx_timrot_set_next_event(unsigned long delta,
66 struct clock_event_device *dev)
67{
68 /* reload the timer */
69 __raw_writel(delta, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
70 return 0;
71}
72
73static void
74stmp3xxx_timrot_set_mode(enum clock_event_mode mode,
75 struct clock_event_device *dev)
76{
77}
78
79static struct clock_event_device ckevt_timrot = {
80 .name = "timrot",
81 .features = CLOCK_EVT_FEAT_ONESHOT,
82 .shift = 32,
83 .set_next_event = stmp3xxx_timrot_set_next_event,
84 .set_mode = stmp3xxx_timrot_set_mode,
85};
86
87static struct clocksource cksrc_stmp3xxx = {
88 .name = "cksrc_stmp3xxx",
89 .rating = 250,
90 .read = stmp3xxx_clock_read,
91 .mask = CLOCKSOURCE_MASK(16),
92 .shift = 10,
93 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
94};
95
96static struct irqaction stmp3xxx_timer_irq = {
97 .name = "stmp3xxx_timer",
98 .flags = IRQF_DISABLED | IRQF_TIMER,
99 .handler = stmp3xxx_timer_interrupt,
100 .dev_id = &ckevt_timrot,
101};
102
103
104/*
105 * Set up timer interrupt, and return the current time in seconds.
106 */
107static void __init stmp3xxx_init_timer(void)
108{
109 cksrc_stmp3xxx.mult = clocksource_hz2mult(CLOCK_TICK_RATE,
110 cksrc_stmp3xxx.shift);
111 ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
112 ckevt_timrot.shift);
113 ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot);
114 ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot);
115 ckevt_timrot.cpumask = cpumask_of(0);
116
117 stmp3xxx_reset_block(REGS_TIMROT_BASE, false);
118
119 /* clear two timers */
120 __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
121 __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
122
123 /* configure them */
124 __raw_writel(
125 (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */
126 BM_TIMROT_TIMCTRLn_RELOAD |
127 BM_TIMROT_TIMCTRLn_UPDATE |
128 BM_TIMROT_TIMCTRLn_IRQ_EN,
129 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
130 __raw_writel(
131 (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */
132 BM_TIMROT_TIMCTRLn_RELOAD |
133 BM_TIMROT_TIMCTRLn_UPDATE |
134 BM_TIMROT_TIMCTRLn_IRQ_EN,
135 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
136
137 __raw_writel(CLOCK_TICK_RATE / HZ - 1,
138 REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
139 __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
140
141 setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq);
142
143 clocksource_register(&cksrc_stmp3xxx);
144 clockevents_register_device(&ckevt_timrot);
145}
146
147#ifdef CONFIG_PM
148
149void stmp3xxx_suspend_timer(void)
150{
151 stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN | BM_TIMROT_TIMCTRLn_IRQ,
152 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
153 stmp3xxx_setl(BM_TIMROT_ROTCTRL_CLKGATE,
154 REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
155}
156
157void stmp3xxx_resume_timer(void)
158{
159 stmp3xxx_clearl(BM_TIMROT_ROTCTRL_SFTRST | BM_TIMROT_ROTCTRL_CLKGATE,
160 REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
161 __raw_writel(
162 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */
163 BM_TIMROT_TIMCTRLn_RELOAD |
164 BM_TIMROT_TIMCTRLn_UPDATE |
165 BM_TIMROT_TIMCTRLn_IRQ_EN,
166 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
167 __raw_writel(
168 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */
169 BM_TIMROT_TIMCTRLn_RELOAD |
170 BM_TIMROT_TIMCTRLn_UPDATE |
171 BM_TIMROT_TIMCTRLn_IRQ_EN,
172 REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
173 __raw_writel(CLOCK_TICK_RATE / HZ - 1,
174 REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
175 __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
176}
177
178#else
179
180#define stmp3xxx_suspend_timer NULL
181#define stmp3xxx_resume_timer NULL
182
183#endif /* CONFIG_PM */
184
185struct sys_timer stmp3xxx_timer = {
186 .init = stmp3xxx_init_timer,
187 .suspend = stmp3xxx_suspend_timer,
188 .resume = stmp3xxx_resume_timer,
189};