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authorJosh Cartwright <josh.cartwright@ni.com>2012-10-21 22:15:37 -0400
committerMichal Simek <michal.simek@xilinx.com>2012-10-29 03:54:56 -0400
commitf58007762f537ba13674a3138b3f4c20fff1cba9 (patch)
treea88498fd3c86be7ca74ce90d9a0bf6f8e7febeab /arch/arm
parentf7977939e956bdf6558ae6f4b743653db9f5c291 (diff)
zynq: move static peripheral mappings
Shifting them up into the vmalloc region prevents the following warning, when booting a zynq qemu target with more than 512mb of RAM: BUG: mapping for 0xe0000000 at 0xe0000000 out of vmalloc space In addition, it allows for reuse of these mappings when the proper drivers issue requests via ioremap(). There are currently unknown issues with the early uart mapping. For now, the uart will be mapped to a known working address. Signed-off-by: Josh Cartwright <josh.cartwright@ni.com> Cc: John Linn <john.linn@xilinx.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Tested-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-zynq/common.c6
-rw-r--r--arch/arm/mach-zynq/include/mach/zynq_soc.h25
2 files changed, 18 insertions, 13 deletions
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index ba48f067d8f2..ba8d14f78d4d 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -73,12 +73,12 @@ static struct map_desc io_desc[] __initdata = {
73 { 73 {
74 .virtual = TTC0_VIRT, 74 .virtual = TTC0_VIRT,
75 .pfn = __phys_to_pfn(TTC0_PHYS), 75 .pfn = __phys_to_pfn(TTC0_PHYS),
76 .length = SZ_4K, 76 .length = TTC0_SIZE,
77 .type = MT_DEVICE, 77 .type = MT_DEVICE,
78 }, { 78 }, {
79 .virtual = SCU_PERIPH_VIRT, 79 .virtual = SCU_PERIPH_VIRT,
80 .pfn = __phys_to_pfn(SCU_PERIPH_PHYS), 80 .pfn = __phys_to_pfn(SCU_PERIPH_PHYS),
81 .length = SZ_8K, 81 .length = SCU_PERIPH_SIZE,
82 .type = MT_DEVICE, 82 .type = MT_DEVICE,
83 }, 83 },
84 84
@@ -86,7 +86,7 @@ static struct map_desc io_desc[] __initdata = {
86 { 86 {
87 .virtual = UART0_VIRT, 87 .virtual = UART0_VIRT,
88 .pfn = __phys_to_pfn(UART0_PHYS), 88 .pfn = __phys_to_pfn(UART0_PHYS),
89 .length = SZ_4K, 89 .length = UART0_SIZE,
90 .type = MT_DEVICE, 90 .type = MT_DEVICE,
91 }, 91 },
92#endif 92#endif
diff --git a/arch/arm/mach-zynq/include/mach/zynq_soc.h b/arch/arm/mach-zynq/include/mach/zynq_soc.h
index 218283a94247..1b8bf0ecbcb0 100644
--- a/arch/arm/mach-zynq/include/mach/zynq_soc.h
+++ b/arch/arm/mach-zynq/include/mach/zynq_soc.h
@@ -15,27 +15,32 @@
15#ifndef __MACH_XILINX_SOC_H__ 15#ifndef __MACH_XILINX_SOC_H__
16#define __MACH_XILINX_SOC_H__ 16#define __MACH_XILINX_SOC_H__
17 17
18#include <asm/pgtable.h>
19
18#define PERIPHERAL_CLOCK_RATE 2500000 20#define PERIPHERAL_CLOCK_RATE 2500000
19 21
20/* For now, all mappings are flat (physical = virtual) 22/* Static peripheral mappings are mapped at the top of the vmalloc region. The
23 * early uart mapping causes intermediate problems/failure at certain
24 * addresses, including the very top of the vmalloc region. Map it at an
25 * address that is known to work.
21 */ 26 */
22#define UART0_PHYS 0xE0000000 27#define UART0_PHYS 0xE0000000
23#define UART0_VIRT UART0_PHYS 28#define UART0_SIZE SZ_4K
29#define UART0_VIRT 0xF0001000
24 30
25#define TTC0_PHYS 0xF8001000 31#define TTC0_PHYS 0xF8001000
26#define TTC0_VIRT TTC0_PHYS 32#define TTC0_SIZE SZ_4K
33#define TTC0_VIRT (VMALLOC_END - TTC0_SIZE)
27 34
28#define SCU_PERIPH_PHYS 0xF8F00000 35#define SCU_PERIPH_PHYS 0xF8F00000
29#define SCU_PERIPH_VIRT SCU_PERIPH_PHYS 36#define SCU_PERIPH_SIZE SZ_8K
37#define SCU_PERIPH_VIRT (TTC0_VIRT - SCU_PERIPH_SIZE)
30 38
31/* The following are intended for the devices that are mapped early */ 39/* The following are intended for the devices that are mapped early */
32 40
33#define TTC0_BASE IOMEM(TTC0_VIRT) 41#define TTC0_BASE IOMEM(TTC0_VIRT)
34#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT) 42#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT)
35 43
36/*
37 * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical
38 */
39#define LL_UART_PADDR UART0_PHYS 44#define LL_UART_PADDR UART0_PHYS
40#define LL_UART_VADDR UART0_VIRT 45#define LL_UART_VADDR UART0_VIRT
41 46