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authorTuomas Tynkkynen <ttynkkynen@nvidia.com>2013-08-01 11:00:17 -0400
committerStephen Warren <swarren@nvidia.com>2013-08-13 14:40:47 -0400
commitcc34c9f79c1dae776ebec069bb49376462221595 (patch)
tree0d99b21d7412a280178fa93473b18d543a1f8842 /arch/arm
parentd7283c11f7e87e40c44bbffc4397309ef8bc5c7b (diff)
ARM: tegra: add USB DT entries for Tegra30
Add device tree entries for the 3 USB controllers and PHYs and enable the third controller on Cardhu and Beaver boards. Fix VBUS regulator entries on Beaver. The GPIO pins were wrong. Also, internal pullups need to be enabled on those pins. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/tegra30-beaver.dts22
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi9
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi86
3 files changed, 115 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 51a0ee7b0c85..4f1f01cbe135 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -110,6 +110,11 @@
110 nvidia,pull = <0>; 110 nvidia,pull = <0>;
111 nvidia,tristate = <0>; 111 nvidia,tristate = <0>;
112 }; 112 };
113 pex_l1_prsnt_n_pdd4 {
114 nvidia,pins = "pex_l1_prsnt_n_pdd4",
115 "pex_l1_clkreq_n_pdd6";
116 nvidia,pull = <2>;
117 };
113 sdio3 { 118 sdio3 {
114 nvidia,pins = "drive_sdio3"; 119 nvidia,pins = "drive_sdio3";
115 nvidia,high-speed-mode = <0>; 120 nvidia,high-speed-mode = <0>;
@@ -119,6 +124,10 @@
119 nvidia,slew-rate-rising = <1>; 124 nvidia,slew-rate-rising = <1>;
120 nvidia,slew-rate-falling = <1>; 125 nvidia,slew-rate-falling = <1>;
121 }; 126 };
127 gpv {
128 nvidia,pins = "drive_gpv";
129 nvidia,pull-up-strength = <16>;
130 };
122 }; 131 };
123 }; 132 };
124 133
@@ -319,6 +328,15 @@
319 non-removable; 328 non-removable;
320 }; 329 };
321 330
331 usb@7d008000 {
332 status = "okay";
333 };
334
335 usb-phy@7d008000 {
336 vbus-supply = <&usb3_vbus_reg>;
337 status = "okay";
338 };
339
322 clocks { 340 clocks {
323 compatible = "simple-bus"; 341 compatible = "simple-bus";
324 #address-cells = <1>; 342 #address-cells = <1>;
@@ -391,7 +409,7 @@
391 regulator-min-microvolt = <5000000>; 409 regulator-min-microvolt = <5000000>;
392 regulator-max-microvolt = <5000000>; 410 regulator-max-microvolt = <5000000>;
393 enable-active-high; 411 enable-active-high;
394 gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; 412 gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
395 gpio-open-drain; 413 gpio-open-drain;
396 vin-supply = <&vdd_5v_in_reg>; 414 vin-supply = <&vdd_5v_in_reg>;
397 }; 415 };
@@ -403,7 +421,7 @@
403 regulator-min-microvolt = <5000000>; 421 regulator-min-microvolt = <5000000>;
404 regulator-max-microvolt = <5000000>; 422 regulator-max-microvolt = <5000000>;
405 enable-active-high; 423 enable-active-high;
406 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; 424 gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
407 gpio-open-drain; 425 gpio-open-drain;
408 vin-supply = <&vdd_5v_in_reg>; 426 vin-supply = <&vdd_5v_in_reg>;
409 }; 427 };
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 1ecd470e0c77..e19dbf238e5c 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -357,6 +357,15 @@
357 non-removable; 357 non-removable;
358 }; 358 };
359 359
360 usb@7d008000 {
361 status = "okay";
362 };
363
364 usb-phy@7d008000 {
365 vbus-supply = <&usb3_vbus_reg>;
366 status = "okay";
367 };
368
360 clocks { 369 clocks {
361 compatible = "simple-bus"; 370 compatible = "simple-bus";
362 #address-cells = <1>; 371 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index d81c52e5b358..0022c127e1d9 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -631,6 +631,92 @@
631 status = "disabled"; 631 status = "disabled";
632 }; 632 };
633 633
634 usb@7d000000 {
635 compatible = "nvidia,tegra30-ehci", "usb-ehci";
636 reg = <0x7d000000 0x4000>;
637 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
638 phy_type = "utmi";
639 clocks = <&tegra_car TEGRA30_CLK_USBD>;
640 nvidia,needs-double-reset;
641 nvidia,phy = <&phy1>;
642 status = "disabled";
643 };
644
645 phy1: usb-phy@7d000000 {
646 compatible = "nvidia,tegra30-usb-phy";
647 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
648 phy_type = "utmi";
649 clocks = <&tegra_car TEGRA30_CLK_USBD>,
650 <&tegra_car TEGRA30_CLK_PLL_U>,
651 <&tegra_car TEGRA30_CLK_USBD>;
652 clock-names = "reg", "pll_u", "utmi-pads";
653 nvidia,hssync-start-delay = <9>;
654 nvidia,idle-wait-delay = <17>;
655 nvidia,elastic-limit = <16>;
656 nvidia,term-range-adj = <6>;
657 nvidia,xcvr-setup = <51>;
658 nvidia.xcvr-setup-use-fuses;
659 nvidia,xcvr-lsfslew = <1>;
660 nvidia,xcvr-lsrslew = <1>;
661 nvidia,xcvr-hsslew = <32>;
662 nvidia,hssquelch-level = <2>;
663 nvidia,hsdiscon-level = <5>;
664 status = "disabled";
665 };
666
667 usb@7d004000 {
668 compatible = "nvidia,tegra30-ehci", "usb-ehci";
669 reg = <0x7d004000 0x4000>;
670 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
671 phy_type = "ulpi";
672 clocks = <&tegra_car TEGRA30_CLK_USB2>;
673 nvidia,phy = <&phy2>;
674 status = "disabled";
675 };
676
677 phy2: usb-phy@7d004000 {
678 compatible = "nvidia,tegra30-usb-phy";
679 reg = <0x7d004000 0x4000>;
680 phy_type = "ulpi";
681 clocks = <&tegra_car TEGRA30_CLK_USB2>,
682 <&tegra_car TEGRA30_CLK_PLL_U>,
683 <&tegra_car TEGRA30_CLK_CDEV2>;
684 clock-names = "reg", "pll_u", "ulpi-link";
685 status = "disabled";
686 };
687
688 usb@7d008000 {
689 compatible = "nvidia,tegra30-ehci", "usb-ehci";
690 reg = <0x7d008000 0x4000>;
691 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
692 phy_type = "utmi";
693 clocks = <&tegra_car TEGRA30_CLK_USB3>;
694 nvidia,phy = <&phy3>;
695 status = "disabled";
696 };
697
698 phy3: usb-phy@7d008000 {
699 compatible = "nvidia,tegra30-usb-phy";
700 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
701 phy_type = "utmi";
702 clocks = <&tegra_car TEGRA30_CLK_USB3>,
703 <&tegra_car TEGRA30_CLK_PLL_U>,
704 <&tegra_car TEGRA30_CLK_USBD>;
705 clock-names = "reg", "pll_u", "utmi-pads";
706 nvidia,hssync-start-delay = <0>;
707 nvidia,idle-wait-delay = <17>;
708 nvidia,elastic-limit = <16>;
709 nvidia,term-range-adj = <6>;
710 nvidia,xcvr-setup = <51>;
711 nvidia.xcvr-setup-use-fuses;
712 nvidia,xcvr-lsfslew = <2>;
713 nvidia,xcvr-lsrslew = <2>;
714 nvidia,xcvr-hsslew = <32>;
715 nvidia,hssquelch-level = <2>;
716 nvidia,hsdiscon-level = <5>;
717 status = "disabled";
718 };
719
634 cpus { 720 cpus {
635 #address-cells = <1>; 721 #address-cells = <1>;
636 #size-cells = <0>; 722 #size-cells = <0>;