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authorWill Deacon <will.deacon@arm.com>2010-09-14 04:53:02 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-09-17 05:16:52 -0400
commita672e99b129e286df2e2697a1b603d82321117f3 (patch)
tree3307cdb68df62a67d78309ecdf6c35cab7321892 /arch/arm
parent9f05027c7cb3cfe56a31892bd83391138d41a667 (diff)
ARM: 6389/1: errata: incorrect hazard handling in the SCU may lead to data corruption
On the r2p0, r2p1 and r2p2 versions of the Cortex-A9, data corruption can occur if a shared cache line is replaced on one CPU as another CPU is accessing it. This workaround sets two bits in the diagnostic register of the Cortex-A9, reducing the linefill issuing capabilities of the processor and avoiding the erroneous behaviour. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig14
-rw-r--r--arch/arm/mm/proc-v7.S9
2 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ab14c0a5d21e..0f89335b84c2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1063,6 +1063,20 @@ config ARM_ERRATA_742230
1063 instruction to behave as a DSB, ensuring the correct behaviour of 1063 instruction to behave as a DSB, ensuring the correct behaviour of
1064 the two writes. 1064 the two writes.
1065 1065
1066config ARM_ERRATA_742231
1067 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1068 depends on CPU_V7 && SMP
1069 help
1070 This option enables the workaround for the 742231 Cortex-A9
1071 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1072 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1073 accessing some data located in the same cache line, may get corrupted
1074 data due to bad handling of the address hazard when the line gets
1075 replaced from one of the CPUs at the same time as another CPU is
1076 accessing it. This workaround sets specific bits in the diagnostic
1077 register of the Cortex-A9 which reduces the linefill issuing
1078 capabilities of the processor.
1079
1066config PL310_ERRATA_588369 1080config PL310_ERRATA_588369
1067 bool "Clean & Invalidate maintenance operations do not invalidate clean lines" 1081 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1068 depends on CACHE_L2X0 && ARCH_OMAP4 1082 depends on CACHE_L2X0 && ARCH_OMAP4
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 945f36341fa6..080129263eef 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -243,6 +243,15 @@ __v7_setup:
243 orrle r10, r10, #1 << 4 @ set bit #4 243 orrle r10, r10, #1 << 4 @ set bit #4
244 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register 244 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
245#endif 245#endif
246#ifdef CONFIG_ARM_ERRATA_742231
247 teq r6, #0x20 @ present in r2p0
248 teqne r6, #0x21 @ present in r2p1
249 teqne r6, #0x22 @ present in r2p2
250 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
251 orreq r10, r10, #1 << 12 @ set bit #12
252 orreq r10, r10, #1 << 22 @ set bit #22
253 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
254#endif
246 255
2473: mov r10, #0 2563: mov r10, #0
248#ifdef HARVARD_CACHE 257#ifdef HARVARD_CACHE