diff options
| author | Lee Jones <lee.jones@linaro.org> | 2013-05-15 05:51:32 -0400 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2013-05-23 15:13:37 -0400 |
| commit | 9c3c95147cdd30756a08c511c3c80e8fdf05a36a (patch) | |
| tree | fb8beae66ef1a3dc2531e100955291727eff7dfd /arch/arm | |
| parent | 01c935c4ecbf6e67d8b7b8258c5eb3be84c248aa (diff) | |
ARM: ux500: Remove DMA address look-up table
DMA addresses are now passed as part of the dmaengine API by invoking
dmaengine_slave_config(). So there's no requirement for the DMA40
driver to look them up in a table provided by platform data. This
method does not fit in well using Device Tree either.
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-ux500/devices-db8500.c | 80 |
1 files changed, 0 insertions, 80 deletions
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index bed25a39e68b..e21ffd8c1412 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c | |||
| @@ -42,87 +42,7 @@ static struct resource dma40_resources[] = { | |||
| 42 | } | 42 | } |
| 43 | }; | 43 | }; |
| 44 | 44 | ||
| 45 | /* | ||
| 46 | * Mapping between destination event lines and physical device address. | ||
| 47 | * The event line is tied to a device and therefore the address is constant. | ||
| 48 | * When the address comes from a primecell it will be configured in runtime | ||
| 49 | * and we set the address to -1 as a placeholder. | ||
| 50 | */ | ||
| 51 | static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = { | ||
| 52 | /* MUSB - these will be runtime-reconfigured */ | ||
| 53 | [DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8] = -1, | ||
| 54 | [DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15] = -1, | ||
| 55 | [DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14] = -1, | ||
| 56 | [DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13] = -1, | ||
| 57 | [DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12] = -1, | ||
| 58 | [DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11] = -1, | ||
| 59 | [DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10] = -1, | ||
| 60 | [DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9] = -1, | ||
| 61 | /* PrimeCells - run-time configured */ | ||
| 62 | [DB8500_DMA_DEV0_SPI0] = -1, | ||
| 63 | [DB8500_DMA_DEV1_SD_MMC0] = -1, | ||
| 64 | [DB8500_DMA_DEV2_SD_MMC1] = -1, | ||
| 65 | [DB8500_DMA_DEV3_SD_MMC2] = -1, | ||
| 66 | [DB8500_DMA_DEV8_SSP0] = -1, | ||
| 67 | [DB8500_DMA_DEV9_SSP1] = -1, | ||
| 68 | [DB8500_DMA_DEV11_UART2] = -1, | ||
| 69 | [DB8500_DMA_DEV12_UART1] = -1, | ||
| 70 | [DB8500_DMA_DEV13_UART0] = -1, | ||
| 71 | [DB8500_DMA_DEV28_SD_MM2] = -1, | ||
| 72 | [DB8500_DMA_DEV29_SD_MM0] = -1, | ||
| 73 | [DB8500_DMA_DEV32_SD_MM1] = -1, | ||
| 74 | [DB8500_DMA_DEV33_SPI2] = -1, | ||
| 75 | [DB8500_DMA_DEV35_SPI1] = -1, | ||
| 76 | [DB8500_DMA_DEV40_SPI3] = -1, | ||
| 77 | [DB8500_DMA_DEV41_SD_MM3] = -1, | ||
| 78 | [DB8500_DMA_DEV42_SD_MM4] = -1, | ||
| 79 | [DB8500_DMA_DEV43_SD_MM5] = -1, | ||
| 80 | [DB8500_DMA_DEV14_MSP2] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET, | ||
| 81 | [DB8500_DMA_DEV30_MSP1] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET, | ||
| 82 | [DB8500_DMA_DEV31_MSP0_SLIM0_CH0] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET, | ||
| 83 | [DB8500_DMA_DEV48_CAC1] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET, | ||
| 84 | [DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET, | ||
| 85 | }; | ||
| 86 | |||
| 87 | /* Mapping between source event lines and physical device address */ | ||
| 88 | static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = { | ||
| 89 | /* MUSB - these will be runtime-reconfigured */ | ||
| 90 | [DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8] = -1, | ||
| 91 | [DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15] = -1, | ||
| 92 | [DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14] = -1, | ||
| 93 | [DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13] = -1, | ||
| 94 | [DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12] = -1, | ||
| 95 | [DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11] = -1, | ||
| 96 | [DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10] = -1, | ||
| 97 | [DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9] = -1, | ||
| 98 | /* PrimeCells */ | ||
| 99 | [DB8500_DMA_DEV0_SPI0] = -1, | ||
| 100 | [DB8500_DMA_DEV1_SD_MMC0] = -1, | ||
| 101 | [DB8500_DMA_DEV2_SD_MMC1] = -1, | ||
| 102 | [DB8500_DMA_DEV3_SD_MMC2] = -1, | ||
| 103 | [DB8500_DMA_DEV8_SSP0] = -1, | ||
| 104 | [DB8500_DMA_DEV9_SSP1] = -1, | ||
| 105 | [DB8500_DMA_DEV11_UART2] = -1, | ||
| 106 | [DB8500_DMA_DEV12_UART1] = -1, | ||
| 107 | [DB8500_DMA_DEV13_UART0] = -1, | ||
| 108 | [DB8500_DMA_DEV28_SD_MM2] = -1, | ||
| 109 | [DB8500_DMA_DEV29_SD_MM0] = -1, | ||
| 110 | [DB8500_DMA_DEV32_SD_MM1] = -1, | ||
| 111 | [DB8500_DMA_DEV33_SPI2] = -1, | ||
| 112 | [DB8500_DMA_DEV35_SPI1] = -1, | ||
| 113 | [DB8500_DMA_DEV40_SPI3] = -1, | ||
| 114 | [DB8500_DMA_DEV41_SD_MM3] = -1, | ||
| 115 | [DB8500_DMA_DEV42_SD_MM4] = -1, | ||
| 116 | [DB8500_DMA_DEV43_SD_MM5] = -1, | ||
| 117 | [DB8500_DMA_DEV14_MSP2] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET, | ||
| 118 | [DB8500_DMA_DEV30_MSP3] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET, | ||
| 119 | [DB8500_DMA_DEV31_MSP0_SLIM0_CH0] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET, | ||
| 120 | [DB8500_DMA_DEV48_CAC1] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET, | ||
| 121 | }; | ||
| 122 | |||
| 123 | struct stedma40_platform_data dma40_plat_data = { | 45 | struct stedma40_platform_data dma40_plat_data = { |
| 124 | .dev_rx = dma40_rx_map, | ||
| 125 | .dev_tx = dma40_tx_map, | ||
| 126 | .disabled_channels = {-1}, | 46 | .disabled_channels = {-1}, |
| 127 | }; | 47 | }; |
| 128 | 48 | ||