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authorLinus Torvalds <torvalds@linux-foundation.org>2011-11-01 23:58:25 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-11-01 23:58:25 -0400
commit81a3c10ce8a7fd5bf9a06bfc38bd417512911831 (patch)
tree12ceac10fae8c4b2dc17b362672a5db305a8d960 /arch/arm
parent6585dea1f99cc2265582ff2e4cc1727062136e92 (diff)
parentdf80442d1ee2902c2e39f90f18160f2e08d14c06 (diff)
Merge branch 'next/cleanup2' of git://git.linaro.org/people/arnd/arm-soc
* 'next/cleanup2' of git://git.linaro.org/people/arnd/arm-soc: (31 commits) ARM: OMAP: Warn if omap_ioremap is called before SoC detection ARM: OMAP: Move set_globals initialization to happen in init_early ARM: OMAP: Map SRAM later on with ioremap_exec() ARM: OMAP: Remove calls to SRAM allocations for framebuffer ARM: OMAP: Avoid cpu_is_omapxxxx usage until map_io is done ARM: OMAP1: Use generic map_io, init_early and init_irq arm/dts: OMAP3+: Add mpu, dsp and iva nodes arm/dts: OMAP4: Add a main ocp entry bound to l3-noc driver ARM: OMAP2+: l3-noc: Add support for device-tree ARM: OMAP2+: board-generic: Add i2c static init ARM: OMAP2+: board-generic: Add DT support to generic board arm/dts: Add support for OMAP3 Beagle board arm/dts: Add initial device tree support for OMAP3 SoC arm/dts: Add support for OMAP4 SDP board arm/dts: Add support for OMAP4 PandaBoard arm/dts: Add initial device tree support for OMAP4 SoC ARM: OMAP: omap_device: Add a method to build an omap_device from a DT node ARM: OMAP: omap_device: Add omap_device_[alloc|delete] for DT integration of: Add helpers to get one string in multiple strings property ARM: OMAP2+: devices: Remove all omap_device_pm_latency structures ... Fix up trivial header file conflicts in arch/arm/mach-omap2/board-generic.c
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/omap3-beagle.dts29
-rw-r--r--arch/arm/boot/dts/omap3.dtsi63
-rw-r--r--arch/arm/boot/dts/omap4-panda.dts29
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts29
-rw-r--r--arch/arm/boot/dts/omap4.dtsi103
-rw-r--r--arch/arm/mach-omap1/board-ams-delta.c16
-rw-r--r--arch/arm/mach-omap1/board-fsample.c76
-rw-r--r--arch/arm/mach-omap1/board-generic.c16
-rw-r--r--arch/arm/mach-omap1/board-h2.c16
-rw-r--r--arch/arm/mach-omap1/board-h3.c16
-rw-r--r--arch/arm/mach-omap1/board-htcherald.c12
-rw-r--r--arch/arm/mach-omap1/board-innovator.c36
-rw-r--r--arch/arm/mach-omap1/board-nokia770.c34
-rw-r--r--arch/arm/mach-omap1/board-osk.c16
-rw-r--r--arch/arm/mach-omap1/board-palmte.c16
-rw-r--r--arch/arm/mach-omap1/board-palmtt.c16
-rw-r--r--arch/arm/mach-omap1/board-palmz71.c18
-rw-r--r--arch/arm/mach-omap1/board-perseus2.c75
-rw-r--r--arch/arm/mach-omap1/board-sx1.c17
-rw-r--r--arch/arm/mach-omap1/board-voiceblue.c16
-rw-r--r--arch/arm/mach-omap1/devices.c3
-rw-r--r--arch/arm/mach-omap1/io.c59
-rw-r--r--arch/arm/mach-omap2/Kconfig8
-rw-r--r--arch/arm/mach-omap2/board-generic.c159
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c11
-rw-r--r--arch/arm/mach-omap2/board-ti8168evm.c1
-rw-r--r--arch/arm/mach-omap2/common.c50
-rw-r--r--arch/arm/mach-omap2/control.c14
-rw-r--r--arch/arm/mach-omap2/devices.c51
-rw-r--r--arch/arm/mach-omap2/display.c11
-rw-r--r--arch/arm/mach-omap2/dma.c11
-rw-r--r--arch/arm/mach-omap2/gpio.c12
-rw-r--r--arch/arm/mach-omap2/hsmmc.c18
-rw-r--r--arch/arm/mach-omap2/hwspinlock.c12
-rw-r--r--arch/arm/mach-omap2/io.c129
-rw-r--r--arch/arm/mach-omap2/io.h7
-rw-r--r--arch/arm/mach-omap2/mcbsp.c11
-rw-r--r--arch/arm/mach-omap2/omap-smp.c7
-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.c147
-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.h224
-rw-r--r--arch/arm/mach-omap2/omap_l3_smx.c91
-rw-r--r--arch/arm/mach-omap2/omap_l3_smx.h164
-rw-r--r--arch/arm/mach-omap2/pm.c72
-rw-r--r--arch/arm/mach-omap2/prcm.c19
-rw-r--r--arch/arm/mach-omap2/sdrc.c13
-rw-r--r--arch/arm/mach-omap2/serial.c25
-rw-r--r--arch/arm/mach-omap2/sr_device.c11
-rw-r--r--arch/arm/mach-omap2/timer.c6
-rw-r--r--arch/arm/mach-omap2/usb-musb.c26
-rw-r--r--arch/arm/plat-omap/i2c.c10
-rw-r--r--arch/arm/plat-omap/include/plat/common.h17
-rw-r--r--arch/arm/plat-omap/include/plat/io.h33
-rw-r--r--arch/arm/plat-omap/include/plat/omap_device.h1
-rw-r--r--arch/arm/plat-omap/io.c10
-rw-r--r--arch/arm/plat-omap/omap_device.c313
-rw-r--r--arch/arm/plat-omap/sram.c85
56 files changed, 1372 insertions, 1118 deletions
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
new file mode 100644
index 000000000000..9486be62bcdd
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap3.dtsi"
11
12/ {
13 model = "TI OMAP3 BeagleBoard";
14 compatible = "ti,omap3-beagle", "ti,omap3";
15
16 /*
17 * Since the initial device tree board file does not create any
18 * devices (MMC, network...), the only way to boot is to provide a
19 * ramdisk.
20 */
21 chosen {
22 bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug earlyprintk";
23 };
24
25 memory {
26 device_type = "memory";
27 reg = <0x80000000 0x20000000>; /* 512 MB */
28 };
29};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
new file mode 100644
index 000000000000..d202bb5ec7ef
--- /dev/null
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -0,0 +1,63 @@
1/*
2 * Device Tree Source for OMAP3 SoC
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "ti,omap3430", "ti,omap3";
15
16 cpus {
17 cpu@0 {
18 compatible = "arm,cortex-a8";
19 };
20 };
21
22 /*
23 * The soc node represents the soc top level view. It is uses for IPs
24 * that are not memory mapped in the MPU view or for the MPU itself.
25 */
26 soc {
27 compatible = "ti,omap-infra";
28 mpu {
29 compatible = "ti,omap3-mpu";
30 ti,hwmods = "mpu";
31 };
32
33 iva {
34 compatible = "ti,iva2.2";
35 ti,hwmods = "iva";
36
37 dsp {
38 compatible = "ti,omap3-c64";
39 };
40 };
41 };
42
43 /*
44 * XXX: Use a flat representation of the OMAP3 interconnect.
45 * The real OMAP interconnect network is quite complex.
46 * Since that will not bring real advantage to represent that in DT for
47 * the moment, just use a fake OCP bus entry to represent the whole bus
48 * hierarchy.
49 */
50 ocp {
51 compatible = "simple-bus";
52 #address-cells = <1>;
53 #size-cells = <1>;
54 ranges;
55 ti,hwmods = "l3_main";
56
57 intc: interrupt-controller@1 {
58 compatible = "ti,omap3-intc";
59 interrupt-controller;
60 #interrupt-cells = <1>;
61 };
62 };
63};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
new file mode 100644
index 000000000000..c7026578ce7d
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap4.dtsi"
11
12/ {
13 model = "TI OMAP4 PandaBoard";
14 compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
15
16 /*
17 * Since the initial device tree board file does not create any
18 * devices (MMC, network...), the only way to boot is to provide a
19 * ramdisk.
20 */
21 chosen {
22 bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
23 };
24
25 memory {
26 device_type = "memory";
27 reg = <0x80000000 0x40000000>; /* 1 GB */
28 };
29};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
new file mode 100644
index 000000000000..066e28c90328
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap4.dtsi"
11
12/ {
13 model = "TI OMAP4 SDP board";
14 compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4";
15
16 /*
17 * Since the initial device tree board file does not create any
18 * devices (MMC, network...), the only way to boot is to provide a
19 * ramdisk.
20 */
21 chosen {
22 bootargs = "root=/dev/ram0 rw console=ttyO2,115200n8 initrd=0x81600000,20M ramdisk_size=20480 no_console_suspend debug";
23 };
24
25 memory {
26 device_type = "memory";
27 reg = <0x80000000 0x40000000>; /* 1 GB */
28 };
29};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
new file mode 100644
index 000000000000..4c61c829043a
--- /dev/null
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -0,0 +1,103 @@
1/*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Carveout for multimedia usecases
11 * It should be the last 48MB of the first 512MB memory part
12 * In theory, it should not even exist. That zone should be reserved
13 * dynamically during the .reserve callback.
14 */
15/memreserve/ 0x9d000000 0x03000000;
16
17/include/ "skeleton.dtsi"
18
19/ {
20 compatible = "ti,omap4430", "ti,omap4";
21 interrupt-parent = <&gic>;
22
23 aliases {
24 };
25
26 cpus {
27 cpu@0 {
28 compatible = "arm,cortex-a9";
29 };
30 cpu@1 {
31 compatible = "arm,cortex-a9";
32 };
33 };
34
35 /*
36 * The soc node represents the soc top level view. It is uses for IPs
37 * that are not memory mapped in the MPU view or for the MPU itself.
38 */
39 soc {
40 compatible = "ti,omap-infra";
41 mpu {
42 compatible = "ti,omap4-mpu";
43 ti,hwmods = "mpu";
44 };
45
46 dsp {
47 compatible = "ti,omap3-c64";
48 ti,hwmods = "dsp";
49 };
50
51 iva {
52 compatible = "ti,ivahd";
53 ti,hwmods = "iva";
54 };
55 };
56
57 /*
58 * XXX: Use a flat representation of the OMAP4 interconnect.
59 * The real OMAP interconnect network is quite complex.
60 *
61 * MPU -+-- MPU_PRIVATE - GIC, L2
62 * |
63 * +----------------+----------+
64 * | | |
65 * + +- EMIF - DDR |
66 * | | |
67 * | + +--------+
68 * | | |
69 * | +- L4_ABE - AESS, MCBSP, TIMERs...
70 * | |
71 * +- L3_MAIN --+- L4_CORE - IPs...
72 * |
73 * +- L4_PER - IPs...
74 * |
75 * +- L4_CFG -+- L4_WKUP - IPs...
76 * | |
77 * | +- IPs...
78 * +- IPU ----+
79 * | |
80 * +- DSP ----+
81 * | |
82 * +- DSS ----+
83 *
84 * Since that will not bring real advantage to represent that in DT for
85 * the moment, just use a fake OCP bus entry to represent the whole bus
86 * hierarchy.
87 */
88 ocp {
89 compatible = "ti,omap4-l3-noc", "simple-bus";
90 #address-cells = <1>;
91 #size-cells = <1>;
92 ranges;
93 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
94
95 gic: interrupt-controller@48241000 {
96 compatible = "arm,cortex-a9-gic";
97 interrupt-controller;
98 #interrupt-cells = <1>;
99 reg = <0x48241000 0x1000>,
100 <0x48240100 0x0100>;
101 };
102 };
103};
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 4ea60e2038ea..1f1db76d704a 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -134,12 +134,6 @@ void ams_delta_latch2_write(u16 mask, u16 value)
134 *(volatile __u16 *) AMS_DELTA_LATCH2_VIRT = ams_delta_latch2_reg; 134 *(volatile __u16 *) AMS_DELTA_LATCH2_VIRT = ams_delta_latch2_reg;
135} 135}
136 136
137static void __init ams_delta_init_irq(void)
138{
139 omap1_init_common_hw();
140 omap1_init_irq();
141}
142
143static struct map_desc ams_delta_io_desc[] __initdata = { 137static struct map_desc ams_delta_io_desc[] __initdata = {
144 /* AMS_DELTA_LATCH1 */ 138 /* AMS_DELTA_LATCH1 */
145 { 139 {
@@ -378,17 +372,13 @@ static int __init ams_delta_modem_init(void)
378} 372}
379arch_initcall(ams_delta_modem_init); 373arch_initcall(ams_delta_modem_init);
380 374
381static void __init ams_delta_map_io(void)
382{
383 omap1_map_common_io();
384}
385
386MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)") 375MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
387 /* Maintainer: Jonathan McDowell <noodles@earth.li> */ 376 /* Maintainer: Jonathan McDowell <noodles@earth.li> */
388 .atag_offset = 0x100, 377 .atag_offset = 0x100,
389 .map_io = ams_delta_map_io, 378 .map_io = omap15xx_map_io,
379 .init_early = omap1_init_early,
390 .reserve = omap_reserve, 380 .reserve = omap_reserve,
391 .init_irq = ams_delta_init_irq, 381 .init_irq = omap1_init_irq,
392 .init_machine = ams_delta_init, 382 .init_machine = ams_delta_init,
393 .timer = &omap1_timer, 383 .timer = &omap1_timer,
394MACHINE_END 384MACHINE_END
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 31e089b6f03f..23178275f96b 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -296,6 +296,39 @@ static struct omap_board_config_kernel fsample_config[] __initdata = {
296 296
297static void __init omap_fsample_init(void) 297static void __init omap_fsample_init(void)
298{ 298{
299 /* Early, board-dependent init */
300
301 /*
302 * Hold GSM Reset until needed
303 */
304 omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
305
306 /*
307 * UARTs -> done automagically by 8250 driver
308 */
309
310 /*
311 * CSx timings, GPIO Mux ... setup
312 */
313
314 /* Flash: CS0 timings setup */
315 omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
316 omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
317
318 /*
319 * Ethernet support through the debug board
320 * CS1 timings setup
321 */
322 omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
323 omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
324
325 /*
326 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
327 * It is used as the Ethernet controller interrupt
328 */
329 omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF,
330 OMAP7XX_IO_CONF_9);
331
299 fsample_init_smc91x(); 332 fsample_init_smc91x();
300 333
301 if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0) 334 if (gpio_request(FSAMPLE_NAND_RB_GPIO_PIN, "NAND ready") < 0)
@@ -325,12 +358,6 @@ static void __init omap_fsample_init(void)
325 omap_register_i2c_bus(1, 100, NULL, 0); 358 omap_register_i2c_bus(1, 100, NULL, 0);
326} 359}
327 360
328static void __init omap_fsample_init_irq(void)
329{
330 omap1_init_common_hw();
331 omap1_init_irq();
332}
333
334/* Only FPGA needs to be mapped here. All others are done with ioremap */ 361/* Only FPGA needs to be mapped here. All others are done with ioremap */
335static struct map_desc omap_fsample_io_desc[] __initdata = { 362static struct map_desc omap_fsample_io_desc[] __initdata = {
336 { 363 {
@@ -349,49 +376,18 @@ static struct map_desc omap_fsample_io_desc[] __initdata = {
349 376
350static void __init omap_fsample_map_io(void) 377static void __init omap_fsample_map_io(void)
351{ 378{
352 omap1_map_common_io(); 379 omap15xx_map_io();
353 iotable_init(omap_fsample_io_desc, 380 iotable_init(omap_fsample_io_desc,
354 ARRAY_SIZE(omap_fsample_io_desc)); 381 ARRAY_SIZE(omap_fsample_io_desc));
355
356 /* Early, board-dependent init */
357
358 /*
359 * Hold GSM Reset until needed
360 */
361 omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
362
363 /*
364 * UARTs -> done automagically by 8250 driver
365 */
366
367 /*
368 * CSx timings, GPIO Mux ... setup
369 */
370
371 /* Flash: CS0 timings setup */
372 omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
373 omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
374
375 /*
376 * Ethernet support through the debug board
377 * CS1 timings setup
378 */
379 omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
380 omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
381
382 /*
383 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
384 * It is used as the Ethernet controller interrupt
385 */
386 omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9);
387} 382}
388 383
389MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample") 384MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
390/* Maintainer: Brian Swetland <swetland@google.com> */ 385/* Maintainer: Brian Swetland <swetland@google.com> */
391 .atag_offset = 0x100, 386 .atag_offset = 0x100,
392 .map_io = omap_fsample_map_io, 387 .map_io = omap_fsample_map_io,
388 .init_early = omap1_init_early,
393 .reserve = omap_reserve, 389 .reserve = omap_reserve,
394 .init_irq = omap_fsample_init_irq, 390 .init_irq = omap1_init_irq,
395 .init_machine = omap_fsample_init, 391 .init_machine = omap_fsample_init,
396 .timer = &omap1_timer, 392 .timer = &omap1_timer,
397MACHINE_END 393MACHINE_END
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index 05c6e9d858f3..dc5b75de531c 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -27,12 +27,6 @@
27#include <plat/board.h> 27#include <plat/board.h>
28#include <plat/common.h> 28#include <plat/common.h>
29 29
30static void __init omap_generic_init_irq(void)
31{
32 omap1_init_common_hw();
33 omap1_init_irq();
34}
35
36/* assume no Mini-AB port */ 30/* assume no Mini-AB port */
37 31
38#ifdef CONFIG_ARCH_OMAP15XX 32#ifdef CONFIG_ARCH_OMAP15XX
@@ -86,17 +80,13 @@ static void __init omap_generic_init(void)
86 omap_register_i2c_bus(1, 100, NULL, 0); 80 omap_register_i2c_bus(1, 100, NULL, 0);
87} 81}
88 82
89static void __init omap_generic_map_io(void)
90{
91 omap1_map_common_io();
92}
93
94MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710") 83MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
95 /* Maintainer: Tony Lindgren <tony@atomide.com> */ 84 /* Maintainer: Tony Lindgren <tony@atomide.com> */
96 .atag_offset = 0x100, 85 .atag_offset = 0x100,
97 .map_io = omap_generic_map_io, 86 .map_io = omap16xx_map_io,
87 .init_early = omap1_init_early,
98 .reserve = omap_reserve, 88 .reserve = omap_reserve,
99 .init_irq = omap_generic_init_irq, 89 .init_irq = omap1_init_irq,
100 .init_machine = omap_generic_init, 90 .init_machine = omap_generic_init,
101 .timer = &omap1_timer, 91 .timer = &omap1_timer,
102MACHINE_END 92MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index c2e279173d42..b334b1481678 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -372,12 +372,6 @@ static struct i2c_board_info __initdata h2_i2c_board_info[] = {
372 }, 372 },
373}; 373};
374 374
375static void __init h2_init_irq(void)
376{
377 omap1_init_common_hw();
378 omap1_init_irq();
379}
380
381static struct omap_usb_config h2_usb_config __initdata = { 375static struct omap_usb_config h2_usb_config __initdata = {
382 /* usb1 has a Mini-AB port and external isp1301 transceiver */ 376 /* usb1 has a Mini-AB port and external isp1301 transceiver */
383 .otg = 2, 377 .otg = 2,
@@ -453,17 +447,13 @@ static void __init h2_init(void)
453 h2_mmc_init(); 447 h2_mmc_init();
454} 448}
455 449
456static void __init h2_map_io(void)
457{
458 omap1_map_common_io();
459}
460
461MACHINE_START(OMAP_H2, "TI-H2") 450MACHINE_START(OMAP_H2, "TI-H2")
462 /* Maintainer: Imre Deak <imre.deak@nokia.com> */ 451 /* Maintainer: Imre Deak <imre.deak@nokia.com> */
463 .atag_offset = 0x100, 452 .atag_offset = 0x100,
464 .map_io = h2_map_io, 453 .map_io = omap16xx_map_io,
454 .init_early = omap1_init_early,
465 .reserve = omap_reserve, 455 .reserve = omap_reserve,
466 .init_irq = h2_init_irq, 456 .init_irq = omap1_init_irq,
467 .init_machine = h2_init, 457 .init_machine = h2_init,
468 .timer = &omap1_timer, 458 .timer = &omap1_timer,
469MACHINE_END 459MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 8f5b6af7ed59..74ebe72c9848 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -435,23 +435,13 @@ static void __init h3_init(void)
435 h3_mmc_init(); 435 h3_mmc_init();
436} 436}
437 437
438static void __init h3_init_irq(void)
439{
440 omap1_init_common_hw();
441 omap1_init_irq();
442}
443
444static void __init h3_map_io(void)
445{
446 omap1_map_common_io();
447}
448
449MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board") 438MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
450 /* Maintainer: Texas Instruments, Inc. */ 439 /* Maintainer: Texas Instruments, Inc. */
451 .atag_offset = 0x100, 440 .atag_offset = 0x100,
452 .map_io = h3_map_io, 441 .map_io = omap16xx_map_io,
442 .init_early = omap1_init_early,
453 .reserve = omap_reserve, 443 .reserve = omap_reserve,
454 .init_irq = h3_init_irq, 444 .init_irq = omap1_init_irq,
455 .init_machine = h3_init, 445 .init_machine = h3_init,
456 .timer = &omap1_timer, 446 .timer = &omap1_timer,
457MACHINE_END 447MACHINE_END
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index fcd1a3c31896..3e91baab1a89 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -499,7 +499,7 @@ static void __init htcherald_lcd_init(void)
499 499
500static void __init htcherald_map_io(void) 500static void __init htcherald_map_io(void)
501{ 501{
502 omap1_map_common_io(); 502 omap7xx_map_io();
503 503
504 /* 504 /*
505 * The LCD panel must be disabled and DMA turned off here, as doing 505 * The LCD panel must be disabled and DMA turned off here, as doing
@@ -600,20 +600,14 @@ static void __init htcherald_init(void)
600#endif 600#endif
601} 601}
602 602
603static void __init htcherald_init_irq(void)
604{
605 printk(KERN_INFO "htcherald_init_irq.\n");
606 omap1_init_common_hw();
607 omap1_init_irq();
608}
609
610MACHINE_START(HERALD, "HTC Herald") 603MACHINE_START(HERALD, "HTC Herald")
611 /* Maintainer: Cory Maccarrone <darkstar6262@gmail.com> */ 604 /* Maintainer: Cory Maccarrone <darkstar6262@gmail.com> */
612 /* Maintainer: wing-linux.sourceforge.net */ 605 /* Maintainer: wing-linux.sourceforge.net */
613 .atag_offset = 0x100, 606 .atag_offset = 0x100,
614 .map_io = htcherald_map_io, 607 .map_io = htcherald_map_io,
608 .init_early = omap1_init_early,
615 .reserve = omap_reserve, 609 .reserve = omap_reserve,
616 .init_irq = htcherald_init_irq, 610 .init_irq = omap1_init_irq,
617 .init_machine = htcherald_init, 611 .init_machine = htcherald_init,
618 .timer = &omap1_timer, 612 .timer = &omap1_timer,
619MACHINE_END 613MACHINE_END
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index c2234caf8a7a..273153dba15b 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -288,12 +288,6 @@ static void __init innovator_init_smc91x(void)
288 } 288 }
289} 289}
290 290
291static void __init innovator_init_irq(void)
292{
293 omap1_init_common_hw();
294 omap1_init_irq();
295}
296
297#ifdef CONFIG_ARCH_OMAP15XX 291#ifdef CONFIG_ARCH_OMAP15XX
298static struct omap_usb_config innovator1510_usb_config __initdata = { 292static struct omap_usb_config innovator1510_usb_config __initdata = {
299 /* for bundled non-standard host and peripheral cables */ 293 /* for bundled non-standard host and peripheral cables */
@@ -438,30 +432,32 @@ static void __init innovator_init(void)
438 innovator_mmc_init(); 432 innovator_mmc_init();
439} 433}
440 434
435/*
436 * REVISIT: Assume 15xx for now, we don't want to do revision check
437 * until later on. The right way to fix this is to set up a different
438 * machine_id for 16xx Innovator, or use device tree.
439 */
441static void __init innovator_map_io(void) 440static void __init innovator_map_io(void)
442{ 441{
443 omap1_map_common_io(); 442 omap15xx_map_io();
444 443
445#ifdef CONFIG_ARCH_OMAP15XX 444 iotable_init(innovator1510_io_desc, ARRAY_SIZE(innovator1510_io_desc));
446 if (cpu_is_omap1510()) { 445 udelay(10); /* Delay needed for FPGA */
447 iotable_init(innovator1510_io_desc, ARRAY_SIZE(innovator1510_io_desc)); 446
448 udelay(10); /* Delay needed for FPGA */ 447 /* Dump the Innovator FPGA rev early - useful info for support. */
449 448 pr_debug("Innovator FPGA Rev %d.%d Board Rev %d\n",
450 /* Dump the Innovator FPGA rev early - useful info for support. */ 449 fpga_read(OMAP1510_FPGA_REV_HIGH),
451 printk("Innovator FPGA Rev %d.%d Board Rev %d\n", 450 fpga_read(OMAP1510_FPGA_REV_LOW),
452 fpga_read(OMAP1510_FPGA_REV_HIGH), 451 fpga_read(OMAP1510_FPGA_BOARD_REV));
453 fpga_read(OMAP1510_FPGA_REV_LOW),
454 fpga_read(OMAP1510_FPGA_BOARD_REV));
455 }
456#endif
457} 452}
458 453
459MACHINE_START(OMAP_INNOVATOR, "TI-Innovator") 454MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
460 /* Maintainer: MontaVista Software, Inc. */ 455 /* Maintainer: MontaVista Software, Inc. */
461 .atag_offset = 0x100, 456 .atag_offset = 0x100,
462 .map_io = innovator_map_io, 457 .map_io = innovator_map_io,
458 .init_early = omap1_init_early,
463 .reserve = omap_reserve, 459 .reserve = omap_reserve,
464 .init_irq = innovator_init_irq, 460 .init_irq = omap1_init_irq,
465 .init_machine = innovator_init, 461 .init_machine = innovator_init,
466 .timer = &omap1_timer, 462 .timer = &omap1_timer,
467MACHINE_END 463MACHINE_END
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 02789c5d3703..6798b8488315 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -38,21 +38,6 @@
38 38
39#define ADS7846_PENDOWN_GPIO 15 39#define ADS7846_PENDOWN_GPIO 15
40 40
41static void __init omap_nokia770_init_irq(void)
42{
43 /* On Nokia 770, the SleepX signal is masked with an
44 * MPUIO line by default. It has to be unmasked for it
45 * to become functional */
46
47 /* SleepX mask direction */
48 omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008);
49 /* Unmask SleepX signal */
50 omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
51
52 omap1_init_common_hw();
53 omap1_init_irq();
54}
55
56static const unsigned int nokia770_keymap[] = { 41static const unsigned int nokia770_keymap[] = {
57 KEY(1, 0, GROUP_0 | KEY_UP), 42 KEY(1, 0, GROUP_0 | KEY_UP),
58 KEY(2, 0, GROUP_1 | KEY_F5), 43 KEY(2, 0, GROUP_1 | KEY_F5),
@@ -245,6 +230,15 @@ static inline void nokia770_mmc_init(void)
245 230
246static void __init omap_nokia770_init(void) 231static void __init omap_nokia770_init(void)
247{ 232{
233 /* On Nokia 770, the SleepX signal is masked with an
234 * MPUIO line by default. It has to be unmasked for it
235 * to become functional */
236
237 /* SleepX mask direction */
238 omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008);
239 /* Unmask SleepX signal */
240 omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
241
248 platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices)); 242 platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices));
249 spi_register_board_info(nokia770_spi_board_info, 243 spi_register_board_info(nokia770_spi_board_info,
250 ARRAY_SIZE(nokia770_spi_board_info)); 244 ARRAY_SIZE(nokia770_spi_board_info));
@@ -257,16 +251,12 @@ static void __init omap_nokia770_init(void)
257 nokia770_mmc_init(); 251 nokia770_mmc_init();
258} 252}
259 253
260static void __init omap_nokia770_map_io(void)
261{
262 omap1_map_common_io();
263}
264
265MACHINE_START(NOKIA770, "Nokia 770") 254MACHINE_START(NOKIA770, "Nokia 770")
266 .atag_offset = 0x100, 255 .atag_offset = 0x100,
267 .map_io = omap_nokia770_map_io, 256 .map_io = omap16xx_map_io,
257 .init_early = omap1_init_early,
268 .reserve = omap_reserve, 258 .reserve = omap_reserve,
269 .init_irq = omap_nokia770_init_irq, 259 .init_irq = omap1_init_irq,
270 .init_machine = omap_nokia770_init, 260 .init_machine = omap_nokia770_init,
271 .timer = &omap1_timer, 261 .timer = &omap1_timer,
272MACHINE_END 262MACHINE_END
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index e4dca1deebb4..c3859278d257 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -278,12 +278,6 @@ static void __init osk_init_cf(void)
278 irq_set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING); 278 irq_set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING);
279} 279}
280 280
281static void __init osk_init_irq(void)
282{
283 omap1_init_common_hw();
284 omap1_init_irq();
285}
286
287static struct omap_usb_config osk_usb_config __initdata = { 281static struct omap_usb_config osk_usb_config __initdata = {
288 /* has usb host connector (A) ... for development it can also 282 /* has usb host connector (A) ... for development it can also
289 * be used, with a NONSTANDARD gender-bending cable/dongle, as 283 * be used, with a NONSTANDARD gender-bending cable/dongle, as
@@ -575,17 +569,13 @@ static void __init osk_init(void)
575 osk_mistral_init(); 569 osk_mistral_init();
576} 570}
577 571
578static void __init osk_map_io(void)
579{
580 omap1_map_common_io();
581}
582
583MACHINE_START(OMAP_OSK, "TI-OSK") 572MACHINE_START(OMAP_OSK, "TI-OSK")
584 /* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */ 573 /* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */
585 .atag_offset = 0x100, 574 .atag_offset = 0x100,
586 .map_io = osk_map_io, 575 .map_io = omap16xx_map_io,
576 .init_early = omap1_init_early,
587 .reserve = omap_reserve, 577 .reserve = omap_reserve,
588 .init_irq = osk_init_irq, 578 .init_irq = omap1_init_irq,
589 .init_machine = osk_init, 579 .init_machine = osk_init,
590 .timer = &omap1_timer, 580 .timer = &omap1_timer,
591MACHINE_END 581MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 50c4e398bcc8..f9c44cb15b47 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -58,12 +58,6 @@
58#define PALMTE_MMC2_GPIO OMAP_MPUIO(7) 58#define PALMTE_MMC2_GPIO OMAP_MPUIO(7)
59#define PALMTE_MMC3_GPIO OMAP_MPUIO(11) 59#define PALMTE_MMC3_GPIO OMAP_MPUIO(11)
60 60
61static void __init omap_palmte_init_irq(void)
62{
63 omap1_init_common_hw();
64 omap1_init_irq();
65}
66
67static const unsigned int palmte_keymap[] = { 61static const unsigned int palmte_keymap[] = {
68 KEY(0, 0, KEY_F1), /* Calendar */ 62 KEY(0, 0, KEY_F1), /* Calendar */
69 KEY(1, 0, KEY_F2), /* Contacts */ 63 KEY(1, 0, KEY_F2), /* Contacts */
@@ -268,16 +262,12 @@ static void __init omap_palmte_init(void)
268 omap_register_i2c_bus(1, 100, NULL, 0); 262 omap_register_i2c_bus(1, 100, NULL, 0);
269} 263}
270 264
271static void __init omap_palmte_map_io(void)
272{
273 omap1_map_common_io();
274}
275
276MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E") 265MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
277 .atag_offset = 0x100, 266 .atag_offset = 0x100,
278 .map_io = omap_palmte_map_io, 267 .map_io = omap15xx_map_io,
268 .init_early = omap1_init_early,
279 .reserve = omap_reserve, 269 .reserve = omap_reserve,
280 .init_irq = omap_palmte_init_irq, 270 .init_irq = omap1_init_irq,
281 .init_machine = omap_palmte_init, 271 .init_machine = omap_palmte_init,
282 .timer = &omap1_timer, 272 .timer = &omap1_timer,
283MACHINE_END 273MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 273771cb1b61..11a98539f7bb 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -263,12 +263,6 @@ static struct spi_board_info __initdata palmtt_boardinfo[] = {
263 } 263 }
264}; 264};
265 265
266static void __init omap_palmtt_init_irq(void)
267{
268 omap1_init_common_hw();
269 omap1_init_irq();
270}
271
272static struct omap_usb_config palmtt_usb_config __initdata = { 266static struct omap_usb_config palmtt_usb_config __initdata = {
273 .register_dev = 1, 267 .register_dev = 1,
274 .hmc_mode = 0, 268 .hmc_mode = 0,
@@ -315,16 +309,12 @@ static void __init omap_palmtt_init(void)
315 omap_register_i2c_bus(1, 100, NULL, 0); 309 omap_register_i2c_bus(1, 100, NULL, 0);
316} 310}
317 311
318static void __init omap_palmtt_map_io(void)
319{
320 omap1_map_common_io();
321}
322
323MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T") 312MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
324 .atag_offset = 0x100, 313 .atag_offset = 0x100,
325 .map_io = omap_palmtt_map_io, 314 .map_io = omap15xx_map_io,
315 .init_early = omap1_init_early,
326 .reserve = omap_reserve, 316 .reserve = omap_reserve,
327 .init_irq = omap_palmtt_init_irq, 317 .init_irq = omap1_init_irq,
328 .init_machine = omap_palmtt_init, 318 .init_machine = omap_palmtt_init,
329 .timer = &omap1_timer, 319 .timer = &omap1_timer,
330MACHINE_END 320MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index de36ade38ef7..c6fe61dfe856 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -57,13 +57,6 @@
57#define PALMZ71_SLIDER_GPIO OMAP_MPUIO(3) 57#define PALMZ71_SLIDER_GPIO OMAP_MPUIO(3)
58#define PALMZ71_MMC_IN_GPIO OMAP_MPUIO(4) 58#define PALMZ71_MMC_IN_GPIO OMAP_MPUIO(4)
59 59
60static void __init
61omap_palmz71_init_irq(void)
62{
63 omap1_init_common_hw();
64 omap1_init_irq();
65}
66
67static const unsigned int palmz71_keymap[] = { 60static const unsigned int palmz71_keymap[] = {
68 KEY(0, 0, KEY_F1), 61 KEY(0, 0, KEY_F1),
69 KEY(1, 0, KEY_F2), 62 KEY(1, 0, KEY_F2),
@@ -334,17 +327,12 @@ omap_palmz71_init(void)
334 palmz71_gpio_setup(0); 327 palmz71_gpio_setup(0);
335} 328}
336 329
337static void __init
338omap_palmz71_map_io(void)
339{
340 omap1_map_common_io();
341}
342
343MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71") 330MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
344 .atag_offset = 0x100, 331 .atag_offset = 0x100,
345 .map_io = omap_palmz71_map_io, 332 .map_io = omap15xx_map_io,
333 .init_early = omap1_init_early,
346 .reserve = omap_reserve, 334 .reserve = omap_reserve,
347 .init_irq = omap_palmz71_init_irq, 335 .init_irq = omap1_init_irq,
348 .init_machine = omap_palmz71_init, 336 .init_machine = omap_palmz71_init,
349 .timer = &omap1_timer, 337 .timer = &omap1_timer,
350MACHINE_END 338MACHINE_END
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 04b1befaced6..203ae07550db 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -264,6 +264,39 @@ static void __init perseus2_init_smc91x(void)
264 264
265static void __init omap_perseus2_init(void) 265static void __init omap_perseus2_init(void)
266{ 266{
267 /* Early, board-dependent init */
268
269 /*
270 * Hold GSM Reset until needed
271 */
272 omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
273
274 /*
275 * UARTs -> done automagically by 8250 driver
276 */
277
278 /*
279 * CSx timings, GPIO Mux ... setup
280 */
281
282 /* Flash: CS0 timings setup */
283 omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
284 omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
285
286 /*
287 * Ethernet support through the debug board
288 * CS1 timings setup
289 */
290 omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
291 omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
292
293 /*
294 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
295 * It is used as the Ethernet controller interrupt
296 */
297 omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF,
298 OMAP7XX_IO_CONF_9);
299
267 perseus2_init_smc91x(); 300 perseus2_init_smc91x();
268 301
269 if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0) 302 if (gpio_request(P2_NAND_RB_GPIO_PIN, "NAND ready") < 0)
@@ -293,11 +326,6 @@ static void __init omap_perseus2_init(void)
293 omap_register_i2c_bus(1, 100, NULL, 0); 326 omap_register_i2c_bus(1, 100, NULL, 0);
294} 327}
295 328
296static void __init omap_perseus2_init_irq(void)
297{
298 omap1_init_common_hw();
299 omap1_init_irq();
300}
301/* Only FPGA needs to be mapped here. All others are done with ioremap */ 329/* Only FPGA needs to be mapped here. All others are done with ioremap */
302static struct map_desc omap_perseus2_io_desc[] __initdata = { 330static struct map_desc omap_perseus2_io_desc[] __initdata = {
303 { 331 {
@@ -310,49 +338,18 @@ static struct map_desc omap_perseus2_io_desc[] __initdata = {
310 338
311static void __init omap_perseus2_map_io(void) 339static void __init omap_perseus2_map_io(void)
312{ 340{
313 omap1_map_common_io(); 341 omap7xx_map_io();
314 iotable_init(omap_perseus2_io_desc, 342 iotable_init(omap_perseus2_io_desc,
315 ARRAY_SIZE(omap_perseus2_io_desc)); 343 ARRAY_SIZE(omap_perseus2_io_desc));
316
317 /* Early, board-dependent init */
318
319 /*
320 * Hold GSM Reset until needed
321 */
322 omap_writew(omap_readw(OMAP7XX_DSP_M_CTL) & ~1, OMAP7XX_DSP_M_CTL);
323
324 /*
325 * UARTs -> done automagically by 8250 driver
326 */
327
328 /*
329 * CSx timings, GPIO Mux ... setup
330 */
331
332 /* Flash: CS0 timings setup */
333 omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_0);
334 omap_writel(0x00000088, OMAP7XX_FLASH_ACFG_0);
335
336 /*
337 * Ethernet support through the debug board
338 * CS1 timings setup
339 */
340 omap_writel(0x0000fff3, OMAP7XX_FLASH_CFG_1);
341 omap_writel(0x00000000, OMAP7XX_FLASH_ACFG_1);
342
343 /*
344 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
345 * It is used as the Ethernet controller interrupt
346 */
347 omap_writel(omap_readl(OMAP7XX_IO_CONF_9) & 0x1FFFFFFF, OMAP7XX_IO_CONF_9);
348} 344}
349 345
350MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2") 346MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
351 /* Maintainer: Kevin Hilman <kjh@hilman.org> */ 347 /* Maintainer: Kevin Hilman <kjh@hilman.org> */
352 .atag_offset = 0x100, 348 .atag_offset = 0x100,
353 .map_io = omap_perseus2_map_io, 349 .map_io = omap_perseus2_map_io,
350 .init_early = omap1_init_early,
354 .reserve = omap_reserve, 351 .reserve = omap_reserve,
355 .init_irq = omap_perseus2_init_irq, 352 .init_irq = omap1_init_irq,
356 .init_machine = omap_perseus2_init, 353 .init_machine = omap_perseus2_init,
357 .timer = &omap1_timer, 354 .timer = &omap1_timer,
358MACHINE_END 355MACHINE_END
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 2bea941741d5..667a7cbdb11c 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -406,24 +406,13 @@ static void __init omap_sx1_init(void)
406 gpio_direction_output(11, 0); /*A_SWITCH = 0 */ 406 gpio_direction_output(11, 0); /*A_SWITCH = 0 */
407 gpio_direction_output(15, 0); /*A_USB_ON = 0 */ 407 gpio_direction_output(15, 0); /*A_USB_ON = 0 */
408} 408}
409/*----------------------------------------*/
410static void __init omap_sx1_init_irq(void)
411{
412 omap1_init_common_hw();
413 omap1_init_irq();
414}
415/*----------------------------------------*/
416
417static void __init omap_sx1_map_io(void)
418{
419 omap1_map_common_io();
420}
421 409
422MACHINE_START(SX1, "OMAP310 based Siemens SX1") 410MACHINE_START(SX1, "OMAP310 based Siemens SX1")
423 .atag_offset = 0x100, 411 .atag_offset = 0x100,
424 .map_io = omap_sx1_map_io, 412 .map_io = omap15xx_map_io,
413 .init_early = omap1_init_early,
425 .reserve = omap_reserve, 414 .reserve = omap_reserve,
426 .init_irq = omap_sx1_init_irq, 415 .init_irq = omap1_init_irq,
427 .init_machine = omap_sx1_init, 416 .init_machine = omap_sx1_init,
428 .timer = &omap1_timer, 417 .timer = &omap1_timer,
429MACHINE_END 418MACHINE_END
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 940faed82be2..2a6545ba61c4 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -159,17 +159,6 @@ static struct omap_usb_config voiceblue_usb_config __initdata = {
159static struct omap_board_config_kernel voiceblue_config[] = { 159static struct omap_board_config_kernel voiceblue_config[] = {
160}; 160};
161 161
162static void __init voiceblue_init_irq(void)
163{
164 omap1_init_common_hw();
165 omap1_init_irq();
166}
167
168static void __init voiceblue_map_io(void)
169{
170 omap1_map_common_io();
171}
172
173#define MACHINE_PANICED 1 162#define MACHINE_PANICED 1
174#define MACHINE_REBOOTING 2 163#define MACHINE_REBOOTING 2
175#define MACHINE_REBOOT 4 164#define MACHINE_REBOOT 4
@@ -302,9 +291,10 @@ static void __init voiceblue_init(void)
302MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910") 291MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
303 /* Maintainer: Ladislav Michl <michl@2n.cz> */ 292 /* Maintainer: Ladislav Michl <michl@2n.cz> */
304 .atag_offset = 0x100, 293 .atag_offset = 0x100,
305 .map_io = voiceblue_map_io, 294 .map_io = omap15xx_map_io,
295 .init_early = omap1_init_early,
306 .reserve = omap_reserve, 296 .reserve = omap_reserve,
307 .init_irq = voiceblue_init_irq, 297 .init_irq = omap1_init_irq,
308 .init_machine = voiceblue_init, 298 .init_machine = voiceblue_init,
309 .timer = &omap1_timer, 299 .timer = &omap1_timer,
310MACHINE_END 300MACHINE_END
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 7c50ecf68123..48ef9888e820 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -22,6 +22,7 @@
22#include <mach/hardware.h> 22#include <mach/hardware.h>
23#include <asm/mach/map.h> 23#include <asm/mach/map.h>
24 24
25#include <plat/common.h>
25#include <plat/tc.h> 26#include <plat/tc.h>
26#include <plat/board.h> 27#include <plat/board.h>
27#include <plat/mux.h> 28#include <plat/mux.h>
@@ -291,6 +292,8 @@ static int __init omap1_init_devices(void)
291 if (!cpu_class_is_omap1()) 292 if (!cpu_class_is_omap1())
292 return -ENODEV; 293 return -ENODEV;
293 294
295 omap_sram_init();
296
294 /* please keep these calls, and their implementations above, 297 /* please keep these calls, and their implementations above,
295 * in alphabetical order so they're easier to sort through. 298 * in alphabetical order so they're easier to sort through.
296 */ 299 */
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 1cfa1b6bb62b..7969cfda4454 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -21,7 +21,6 @@
21#include "clock.h" 21#include "clock.h"
22 22
23extern void omap_check_revision(void); 23extern void omap_check_revision(void);
24extern void omap_sram_init(void);
25 24
26/* 25/*
27 * The machine specific code may provide the extra mapping besides the 26 * The machine specific code may provide the extra mapping besides the
@@ -85,51 +84,45 @@ static struct map_desc omap16xx_io_desc[] __initdata = {
85#endif 84#endif
86 85
87/* 86/*
88 * Maps common IO regions for omap1. This should only get called from 87 * Maps common IO regions for omap1
89 * board specific init.
90 */ 88 */
91void __init omap1_map_common_io(void) 89static void __init omap1_map_common_io(void)
92{ 90{
93 iotable_init(omap_io_desc, ARRAY_SIZE(omap_io_desc)); 91 iotable_init(omap_io_desc, ARRAY_SIZE(omap_io_desc));
94 92}
95 /* Normally devicemaps_init() would flush caches and tlb after
96 * mdesc->map_io(), but we must also do it here because of the CPU
97 * revision check below.
98 */
99 local_flush_tlb_all();
100 flush_cache_all();
101
102 /* We want to check CPU revision early for cpu_is_omapxxxx() macros.
103 * IO space mapping must be initialized before we can do that.
104 */
105 omap_check_revision();
106 93
107#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850) 94#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
108 if (cpu_is_omap7xx()) { 95void __init omap7xx_map_io(void)
109 iotable_init(omap7xx_io_desc, ARRAY_SIZE(omap7xx_io_desc)); 96{
110 } 97 omap1_map_common_io();
98 iotable_init(omap7xx_io_desc, ARRAY_SIZE(omap7xx_io_desc));
99}
111#endif 100#endif
101
112#ifdef CONFIG_ARCH_OMAP15XX 102#ifdef CONFIG_ARCH_OMAP15XX
113 if (cpu_is_omap15xx()) { 103void __init omap15xx_map_io(void)
114 iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc)); 104{
115 } 105 omap1_map_common_io();
116#endif 106 iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc));
117#if defined(CONFIG_ARCH_OMAP16XX) 107}
118 if (cpu_is_omap16xx()) {
119 iotable_init(omap16xx_io_desc, ARRAY_SIZE(omap16xx_io_desc));
120 }
121#endif 108#endif
122 109
123 omap_sram_init(); 110#if defined(CONFIG_ARCH_OMAP16XX)
124 omap_init_consistent_dma_size(); 111void __init omap16xx_map_io(void)
112{
113 omap1_map_common_io();
114 iotable_init(omap16xx_io_desc, ARRAY_SIZE(omap16xx_io_desc));
125} 115}
116#endif
126 117
127/* 118/*
128 * Common low-level hardware init for omap1. This should only get called from 119 * Common low-level hardware init for omap1.
129 * board specific init.
130 */ 120 */
131void __init omap1_init_common_hw(void) 121void omap1_init_early(void)
132{ 122{
123 omap_check_revision();
124 omap_ioremap_init();
125
133 /* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort 126 /* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort
134 * on a Posted Write in the TIPB Bridge". 127 * on a Posted Write in the TIPB Bridge".
135 */ 128 */
@@ -139,8 +132,8 @@ void __init omap1_init_common_hw(void)
139 /* Must init clocks early to assure that timer interrupt works 132 /* Must init clocks early to assure that timer interrupt works
140 */ 133 */
141 omap1_clk_init(); 134 omap1_clk_init();
142
143 omap1_mux_init(); 135 omap1_mux_init();
136 omap_init_consistent_dma_size();
144} 137}
145 138
146/* 139/*
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 89bfb49389f2..497e9dc27958 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -108,9 +108,13 @@ comment "OMAP Board Type"
108 depends on ARCH_OMAP2PLUS 108 depends on ARCH_OMAP2PLUS
109 109
110config MACH_OMAP_GENERIC 110config MACH_OMAP_GENERIC
111 bool "Generic OMAP board" 111 bool "Generic OMAP2+ board"
112 depends on ARCH_OMAP2 112 depends on ARCH_OMAP2PLUS
113 select USE_OF
113 default y 114 default y
115 help
116 Support for generic TI OMAP2+ boards using Flattened Device Tree.
117 More information at Documentation/devicetree
114 118
115config MACH_OMAP2_TUSB6010 119config MACH_OMAP2_TUSB6010
116 bool 120 bool
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 7ac546219e5d..0c427976d62f 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -1,75 +1,158 @@
1/* 1/*
2 * linux/arch/arm/mach-omap2/board-generic.c
3 *
4 * Copyright (C) 2005 Nokia Corporation 2 * Copyright (C) 2005 Nokia Corporation
5 * Author: Paul Mundt <paul.mundt@nokia.com> 3 * Author: Paul Mundt <paul.mundt@nokia.com>
6 * 4 *
7 * Modified from mach-omap/omap1/board-generic.c 5 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
8 * 6 *
9 * Code for generic OMAP2 board. Should work on many OMAP2 systems where 7 * Modified from the original mach-omap/omap2/board-generic.c did by Paul
10 * the bootloader passes the board-specific data to the kernel. 8 * to support the OMAP2+ device tree boards with an unique board file.
11 * Do not put any board specific code to this file; create a new machine
12 * type if you need custom low-level initializations.
13 * 9 *
14 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
17 */ 13 */
18#include <linux/gpio.h> 14
19#include <linux/kernel.h> 15#include <linux/io.h>
20#include <linux/init.h> 16#include <linux/of_platform.h>
21#include <linux/device.h> 17#include <linux/irqdomain.h>
18#include <linux/i2c/twl.h>
22 19
23#include <mach/hardware.h> 20#include <mach/hardware.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27 22
28#include <plat/usb.h>
29#include <plat/board.h> 23#include <plat/board.h>
30#include <plat/common.h> 24#include <plat/common.h>
25#include <mach/omap4-common.h>
26#include "common-board-devices.h"
31 27
32static struct omap_board_config_kernel generic_config[] = { 28/*
29 * XXX: Still needed to boot until the i2c & twl driver is adapted to
30 * device-tree
31 */
32static struct twl4030_platform_data sdp4430_twldata = {
33 .irq_base = TWL6030_IRQ_BASE,
34 .irq_end = TWL6030_IRQ_END,
33}; 35};
34 36
35static void __init omap_generic_init_early(void) 37static void __init omap4_i2c_init(void)
36{ 38{
37 omap2_init_common_infrastructure(); 39 omap4_pmic_init("twl6030", &sdp4430_twldata);
38} 40}
39 41
42static struct twl4030_platform_data beagle_twldata = {
43 .irq_base = TWL4030_IRQ_BASE,
44 .irq_end = TWL4030_IRQ_END,
45};
46
47static void __init omap3_i2c_init(void)
48{
49 omap3_pmic_init("twl4030", &beagle_twldata);
50}
51
52static struct of_device_id omap_dt_match_table[] __initdata = {
53 { .compatible = "simple-bus", },
54 { .compatible = "ti,omap-infra", },
55 { }
56};
57
58static struct of_device_id intc_match[] __initdata = {
59 { .compatible = "ti,omap3-intc", },
60 { .compatible = "arm,cortex-a9-gic", },
61 { }
62};
63
40static void __init omap_generic_init(void) 64static void __init omap_generic_init(void)
41{ 65{
66 struct device_node *node = of_find_matching_node(NULL, intc_match);
67 if (node)
68 irq_domain_add_simple(node, 0);
69
42 omap_serial_init(); 70 omap_serial_init();
43 omap_sdrc_init(NULL, NULL); 71 omap_sdrc_init(NULL, NULL);
44 omap_board_config = generic_config; 72
45 omap_board_config_size = ARRAY_SIZE(generic_config); 73 of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
74}
75
76static void __init omap4_init(void)
77{
78 omap4_i2c_init();
79 omap_generic_init();
46} 80}
47 81
48static void __init omap_generic_map_io(void) 82static void __init omap3_init(void)
49{ 83{
50 if (cpu_is_omap242x()) { 84 omap3_i2c_init();
51 omap2_set_globals_242x(); 85 omap_generic_init();
52 omap242x_map_common_io();
53 } else if (cpu_is_omap243x()) {
54 omap2_set_globals_243x();
55 omap243x_map_common_io();
56 } else if (cpu_is_omap34xx()) {
57 omap2_set_globals_3xxx();
58 omap34xx_map_common_io();
59 } else if (cpu_is_omap44xx()) {
60 omap2_set_globals_443x();
61 omap44xx_map_common_io();
62 }
63} 86}
64 87
65/* XXX This machine entry name should be updated */ 88#if defined(CONFIG_SOC_OMAP2420)
66MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx") 89static const char *omap242x_boards_compat[] __initdata = {
67 /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */ 90 "ti,omap2420",
91 NULL,
92};
93
94DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
68 .atag_offset = 0x100, 95 .atag_offset = 0x100,
69 .reserve = omap_reserve, 96 .reserve = omap_reserve,
70 .map_io = omap_generic_map_io, 97 .map_io = omap242x_map_io,
71 .init_early = omap_generic_init_early, 98 .init_early = omap2420_init_early,
72 .init_irq = omap2_init_irq, 99 .init_irq = omap2_init_irq,
73 .init_machine = omap_generic_init, 100 .init_machine = omap_generic_init,
74 .timer = &omap2_timer, 101 .timer = &omap2_timer,
102 .dt_compat = omap242x_boards_compat,
103MACHINE_END
104#endif
105
106#if defined(CONFIG_SOC_OMAP2430)
107static const char *omap243x_boards_compat[] __initdata = {
108 "ti,omap2430",
109 NULL,
110};
111
112DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
113 .atag_offset = 0x100,
114 .reserve = omap_reserve,
115 .map_io = omap243x_map_io,
116 .init_early = omap2430_init_early,
117 .init_irq = omap2_init_irq,
118 .init_machine = omap_generic_init,
119 .timer = &omap2_timer,
120 .dt_compat = omap243x_boards_compat,
121MACHINE_END
122#endif
123
124#if defined(CONFIG_ARCH_OMAP3)
125static const char *omap3_boards_compat[] __initdata = {
126 "ti,omap3",
127 NULL,
128};
129
130DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
131 .atag_offset = 0x100,
132 .reserve = omap_reserve,
133 .map_io = omap3_map_io,
134 .init_early = omap3430_init_early,
135 .init_irq = omap3_init_irq,
136 .init_machine = omap3_init,
137 .timer = &omap3_timer,
138 .dt_compat = omap3_boards_compat,
139MACHINE_END
140#endif
141
142#if defined(CONFIG_ARCH_OMAP4)
143static const char *omap4_boards_compat[] __initdata = {
144 "ti,omap4",
145 NULL,
146};
147
148DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
149 .atag_offset = 0x100,
150 .reserve = omap_reserve,
151 .map_io = omap4_map_io,
152 .init_early = omap4430_init_early,
153 .init_irq = gic_init_irq,
154 .init_machine = omap4_init,
155 .timer = &omap4_timer,
156 .dt_compat = omap4_boards_compat,
75MACHINE_END 157MACHINE_END
158#endif
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 474a7e2cb638..70261bcda3f9 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -444,11 +444,6 @@ static struct platform_device keys_gpio = {
444 }, 444 },
445}; 445};
446 446
447static void __init omap3_beagle_init_early(void)
448{
449 omap2_init_common_infrastructure();
450}
451
452static struct platform_device *omap3_beagle_devices[] __initdata = { 447static struct platform_device *omap3_beagle_devices[] __initdata = {
453 &leds_gpio, 448 &leds_gpio,
454 &keys_gpio, 449 &keys_gpio,
@@ -486,8 +481,8 @@ static void __init beagle_opp_init(void)
486 if (cpu_is_omap3630()) { 481 if (cpu_is_omap3630()) {
487 struct device *mpu_dev, *iva_dev; 482 struct device *mpu_dev, *iva_dev;
488 483
489 mpu_dev = omap2_get_mpuss_device(); 484 mpu_dev = omap_device_get_by_hwmod_name("mpu");
490 iva_dev = omap2_get_iva_device(); 485 iva_dev = omap_device_get_by_hwmod_name("iva");
491 486
492 if (!mpu_dev || !iva_dev) { 487 if (!mpu_dev || !iva_dev) {
493 pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n", 488 pr_err("%s: Aiee.. no mpu/dsp devices? %p %p\n",
@@ -555,7 +550,7 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
555 .atag_offset = 0x100, 550 .atag_offset = 0x100,
556 .reserve = omap_reserve, 551 .reserve = omap_reserve,
557 .map_io = omap3_map_io, 552 .map_io = omap3_map_io,
558 .init_early = omap3_beagle_init_early, 553 .init_early = omap3_init_early,
559 .init_irq = omap3_init_irq, 554 .init_irq = omap3_init_irq,
560 .init_machine = omap3_beagle_init, 555 .init_machine = omap3_beagle_init,
561 .timer = &omap3_secure_timer, 556 .timer = &omap3_secure_timer,
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index e26c79cb6ce9..e6ee8842285c 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -37,7 +37,6 @@ static void __init ti8168_evm_init(void)
37 37
38static void __init ti8168_evm_map_io(void) 38static void __init ti8168_evm_map_io(void)
39{ 39{
40 omap2_set_globals_ti816x();
41 omapti816x_map_common_io(); 40 omapti816x_map_common_io();
42} 41}
43 42
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index de61f15c48e2..110e5b9db145 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -45,11 +45,11 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
45static struct omap_globals omap242x_globals = { 45static struct omap_globals omap242x_globals = {
46 .class = OMAP242X_CLASS, 46 .class = OMAP242X_CLASS,
47 .tap = OMAP2_L4_IO_ADDRESS(0x48014000), 47 .tap = OMAP2_L4_IO_ADDRESS(0x48014000),
48 .sdrc = OMAP2420_SDRC_BASE, 48 .sdrc = OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
49 .sms = OMAP2420_SMS_BASE, 49 .sms = OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE),
50 .ctrl = OMAP242X_CTRL_BASE, 50 .ctrl = OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
51 .prm = OMAP2420_PRM_BASE, 51 .prm = OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE),
52 .cm = OMAP2420_CM_BASE, 52 .cm = OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE),
53}; 53};
54 54
55void __init omap2_set_globals_242x(void) 55void __init omap2_set_globals_242x(void)
@@ -59,7 +59,6 @@ void __init omap2_set_globals_242x(void)
59 59
60void __init omap242x_map_io(void) 60void __init omap242x_map_io(void)
61{ 61{
62 omap2_set_globals_242x();
63 omap242x_map_common_io(); 62 omap242x_map_common_io();
64} 63}
65#endif 64#endif
@@ -69,11 +68,11 @@ void __init omap242x_map_io(void)
69static struct omap_globals omap243x_globals = { 68static struct omap_globals omap243x_globals = {
70 .class = OMAP243X_CLASS, 69 .class = OMAP243X_CLASS,
71 .tap = OMAP2_L4_IO_ADDRESS(0x4900a000), 70 .tap = OMAP2_L4_IO_ADDRESS(0x4900a000),
72 .sdrc = OMAP243X_SDRC_BASE, 71 .sdrc = OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
73 .sms = OMAP243X_SMS_BASE, 72 .sms = OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE),
74 .ctrl = OMAP243X_CTRL_BASE, 73 .ctrl = OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
75 .prm = OMAP2430_PRM_BASE, 74 .prm = OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE),
76 .cm = OMAP2430_CM_BASE, 75 .cm = OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE),
77}; 76};
78 77
79void __init omap2_set_globals_243x(void) 78void __init omap2_set_globals_243x(void)
@@ -83,7 +82,6 @@ void __init omap2_set_globals_243x(void)
83 82
84void __init omap243x_map_io(void) 83void __init omap243x_map_io(void)
85{ 84{
86 omap2_set_globals_243x();
87 omap243x_map_common_io(); 85 omap243x_map_common_io();
88} 86}
89#endif 87#endif
@@ -93,11 +91,11 @@ void __init omap243x_map_io(void)
93static struct omap_globals omap3_globals = { 91static struct omap_globals omap3_globals = {
94 .class = OMAP343X_CLASS, 92 .class = OMAP343X_CLASS,
95 .tap = OMAP2_L4_IO_ADDRESS(0x4830A000), 93 .tap = OMAP2_L4_IO_ADDRESS(0x4830A000),
96 .sdrc = OMAP343X_SDRC_BASE, 94 .sdrc = OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
97 .sms = OMAP343X_SMS_BASE, 95 .sms = OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE),
98 .ctrl = OMAP343X_CTRL_BASE, 96 .ctrl = OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
99 .prm = OMAP3430_PRM_BASE, 97 .prm = OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE),
100 .cm = OMAP3430_CM_BASE, 98 .cm = OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
101}; 99};
102 100
103void __init omap2_set_globals_3xxx(void) 101void __init omap2_set_globals_3xxx(void)
@@ -107,7 +105,6 @@ void __init omap2_set_globals_3xxx(void)
107 105
108void __init omap3_map_io(void) 106void __init omap3_map_io(void)
109{ 107{
110 omap2_set_globals_3xxx();
111 omap34xx_map_common_io(); 108 omap34xx_map_common_io();
112} 109}
113 110
@@ -122,9 +119,9 @@ void __init omap3_map_io(void)
122static struct omap_globals ti816x_globals = { 119static struct omap_globals ti816x_globals = {
123 .class = OMAP343X_CLASS, 120 .class = OMAP343X_CLASS,
124 .tap = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE), 121 .tap = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE),
125 .ctrl = TI816X_CTRL_BASE, 122 .ctrl = OMAP2_L4_IO_ADDRESS(TI816X_CTRL_BASE),
126 .prm = TI816X_PRCM_BASE, 123 .prm = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
127 .cm = TI816X_PRCM_BASE, 124 .cm = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
128}; 125};
129 126
130void __init omap2_set_globals_ti816x(void) 127void __init omap2_set_globals_ti816x(void)
@@ -137,11 +134,11 @@ void __init omap2_set_globals_ti816x(void)
137static struct omap_globals omap4_globals = { 134static struct omap_globals omap4_globals = {
138 .class = OMAP443X_CLASS, 135 .class = OMAP443X_CLASS,
139 .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), 136 .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
140 .ctrl = OMAP443X_SCM_BASE, 137 .ctrl = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
141 .ctrl_pad = OMAP443X_CTRL_BASE, 138 .ctrl_pad = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE),
142 .prm = OMAP4430_PRM_BASE, 139 .prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE),
143 .cm = OMAP4430_CM_BASE, 140 .cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
144 .cm2 = OMAP4430_CM2_BASE, 141 .cm2 = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE),
145}; 142};
146 143
147void __init omap2_set_globals_443x(void) 144void __init omap2_set_globals_443x(void)
@@ -153,7 +150,6 @@ void __init omap2_set_globals_443x(void)
153 150
154void __init omap4_map_io(void) 151void __init omap4_map_io(void)
155{ 152{
156 omap2_set_globals_443x();
157 omap44xx_map_common_io(); 153 omap44xx_map_common_io();
158} 154}
159#endif 155#endif
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index aab884fecc55..e34d27f8c49c 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -149,17 +149,11 @@ static struct omap3_control_regs control_context;
149 149
150void __init omap2_set_globals_control(struct omap_globals *omap2_globals) 150void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
151{ 151{
152 /* Static mapping, never released */ 152 if (omap2_globals->ctrl)
153 if (omap2_globals->ctrl) { 153 omap2_ctrl_base = omap2_globals->ctrl;
154 omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
155 WARN_ON(!omap2_ctrl_base);
156 }
157 154
158 /* Static mapping, never released */ 155 if (omap2_globals->ctrl_pad)
159 if (omap2_globals->ctrl_pad) { 156 omap4_ctrl_pad_base = omap2_globals->ctrl_pad;
160 omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K);
161 WARN_ON(!omap4_ctrl_pad_base);
162 }
163} 157}
164 158
165void __iomem *omap_ctrl_base_get(void) 159void __iomem *omap_ctrl_base_get(void)
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 406b56cfedbc..68ec03152d5f 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -16,6 +16,7 @@
16#include <linux/clk.h> 16#include <linux/clk.h>
17#include <linux/err.h> 17#include <linux/err.h>
18#include <linux/slab.h> 18#include <linux/slab.h>
19#include <linux/of.h>
19 20
20#include <mach/hardware.h> 21#include <mach/hardware.h>
21#include <mach/irqs.h> 22#include <mach/irqs.h>
@@ -76,6 +77,10 @@ static int __init omap4_l3_init(void)
76 struct platform_device *pdev; 77 struct platform_device *pdev;
77 char oh_name[L3_MODULES_MAX_LEN]; 78 char oh_name[L3_MODULES_MAX_LEN];
78 79
80 /* If dtb is there, the devices will be created dynamically */
81 if (of_have_populated_dt())
82 return -ENODEV;
83
79 /* 84 /*
80 * To avoid code running on other OMAPs in 85 * To avoid code running on other OMAPs in
81 * multi-omap builds 86 * multi-omap builds
@@ -220,14 +225,6 @@ static inline void omap_init_camera(void)
220#endif 225#endif
221} 226}
222 227
223struct omap_device_pm_latency omap_keyboard_latency[] = {
224 {
225 .deactivate_func = omap_device_idle_hwmods,
226 .activate_func = omap_device_enable_hwmods,
227 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
228 },
229};
230
231int __init omap4_keyboard_init(struct omap4_keypad_platform_data 228int __init omap4_keyboard_init(struct omap4_keypad_platform_data
232 *sdp4430_keypad_data, struct omap_board_data *bdata) 229 *sdp4430_keypad_data, struct omap_board_data *bdata)
233{ 230{
@@ -247,9 +244,7 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
247 keypad_data = sdp4430_keypad_data; 244 keypad_data = sdp4430_keypad_data;
248 245
249 pdev = omap_device_build(name, id, oh, keypad_data, 246 pdev = omap_device_build(name, id, oh, keypad_data,
250 sizeof(struct omap4_keypad_platform_data), 247 sizeof(struct omap4_keypad_platform_data), NULL, 0, 0);
251 omap_keyboard_latency,
252 ARRAY_SIZE(omap_keyboard_latency), 0);
253 248
254 if (IS_ERR(pdev)) { 249 if (IS_ERR(pdev)) {
255 WARN(1, "Can't build omap_device for %s:%s.\n", 250 WARN(1, "Can't build omap_device for %s:%s.\n",
@@ -262,14 +257,6 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
262} 257}
263 258
264#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) 259#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
265static struct omap_device_pm_latency mbox_latencies[] = {
266 [0] = {
267 .activate_func = omap_device_enable_hwmods,
268 .deactivate_func = omap_device_idle_hwmods,
269 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
270 },
271};
272
273static inline void omap_init_mbox(void) 260static inline void omap_init_mbox(void)
274{ 261{
275 struct omap_hwmod *oh; 262 struct omap_hwmod *oh;
@@ -281,8 +268,7 @@ static inline void omap_init_mbox(void)
281 return; 268 return;
282 } 269 }
283 270
284 pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, 271 pdev = omap_device_build("omap-mailbox", -1, oh, NULL, 0, NULL, 0, 0);
285 mbox_latencies, ARRAY_SIZE(mbox_latencies), 0);
286 WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n", 272 WARN(IS_ERR(pdev), "%s: could not build device, err %ld\n",
287 __func__, PTR_ERR(pdev)); 273 __func__, PTR_ERR(pdev));
288} 274}
@@ -365,14 +351,6 @@ static inline void omap_init_mcpdm(void) {}
365 351
366#include <plat/mcspi.h> 352#include <plat/mcspi.h>
367 353
368struct omap_device_pm_latency omap_mcspi_latency[] = {
369 [0] = {
370 .deactivate_func = omap_device_idle_hwmods,
371 .activate_func = omap_device_enable_hwmods,
372 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
373 },
374};
375
376static int omap_mcspi_init(struct omap_hwmod *oh, void *unused) 354static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
377{ 355{
378 struct platform_device *pdev; 356 struct platform_device *pdev;
@@ -403,8 +381,7 @@ static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
403 381
404 spi_num++; 382 spi_num++;
405 pdev = omap_device_build(name, spi_num, oh, pdata, 383 pdev = omap_device_build(name, spi_num, oh, pdata,
406 sizeof(*pdata), omap_mcspi_latency, 384 sizeof(*pdata), NULL, 0, 0);
407 ARRAY_SIZE(omap_mcspi_latency), 0);
408 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n", 385 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s\n",
409 name, oh->name); 386 name, oh->name);
410 kfree(pdata); 387 kfree(pdata);
@@ -730,14 +707,6 @@ static int __init omap2_init_devices(void)
730arch_initcall(omap2_init_devices); 707arch_initcall(omap2_init_devices);
731 708
732#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE) 709#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
733static struct omap_device_pm_latency omap_wdt_latency[] = {
734 [0] = {
735 .deactivate_func = omap_device_idle_hwmods,
736 .activate_func = omap_device_enable_hwmods,
737 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
738 },
739};
740
741static int __init omap_init_wdt(void) 710static int __init omap_init_wdt(void)
742{ 711{
743 int id = -1; 712 int id = -1;
@@ -755,9 +724,7 @@ static int __init omap_init_wdt(void)
755 return -EINVAL; 724 return -EINVAL;
756 } 725 }
757 726
758 pdev = omap_device_build(dev_name, id, oh, NULL, 0, 727 pdev = omap_device_build(dev_name, id, oh, NULL, 0, NULL, 0, 0);
759 omap_wdt_latency,
760 ARRAY_SIZE(omap_wdt_latency), 0);
761 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n", 728 WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
762 dev_name, oh->name); 729 dev_name, oh->name);
763 return 0; 730 return 0;
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 836f0f7d8c00..4036821a01f3 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -37,14 +37,6 @@ static struct platform_device omap_display_device = {
37 }, 37 },
38}; 38};
39 39
40static struct omap_device_pm_latency omap_dss_latency[] = {
41 [0] = {
42 .deactivate_func = omap_device_idle_hwmods,
43 .activate_func = omap_device_enable_hwmods,
44 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
45 },
46};
47
48struct omap_dss_hwmod_data { 40struct omap_dss_hwmod_data {
49 const char *oh_name; 41 const char *oh_name;
50 const char *dev_name; 42 const char *dev_name;
@@ -165,8 +157,7 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
165 pdev = omap_device_build(curr_dss_hwmod[i].dev_name, 157 pdev = omap_device_build(curr_dss_hwmod[i].dev_name,
166 curr_dss_hwmod[i].id, oh, &pdata, 158 curr_dss_hwmod[i].id, oh, &pdata,
167 sizeof(struct omap_display_platform_data), 159 sizeof(struct omap_display_platform_data),
168 omap_dss_latency, 160 NULL, 0, 0);
169 ARRAY_SIZE(omap_dss_latency), 0);
170 161
171 if (WARN((IS_ERR(pdev)), "Could not build omap_device for %s\n", 162 if (WARN((IS_ERR(pdev)), "Could not build omap_device for %s\n",
172 curr_dss_hwmod[i].oh_name)) 163 curr_dss_hwmod[i].oh_name))
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index ae8cb3fb1830..a59a45a0096e 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -87,14 +87,6 @@ static u16 reg_map[] = {
87 [CCDN] = 0xd8, 87 [CCDN] = 0xd8,
88}; 88};
89 89
90static struct omap_device_pm_latency omap2_dma_latency[] = {
91 {
92 .deactivate_func = omap_device_idle_hwmods,
93 .activate_func = omap_device_enable_hwmods,
94 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
95 },
96};
97
98static void __iomem *dma_base; 90static void __iomem *dma_base;
99static inline void dma_write(u32 val, int reg, int lch) 91static inline void dma_write(u32 val, int reg, int lch)
100{ 92{
@@ -258,8 +250,7 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
258 250
259 p->errata = configure_dma_errata(); 251 p->errata = configure_dma_errata();
260 252
261 pdev = omap_device_build(name, 0, oh, p, sizeof(*p), 253 pdev = omap_device_build(name, 0, oh, p, sizeof(*p), NULL, 0, 0);
262 omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0);
263 kfree(p); 254 kfree(p);
264 if (IS_ERR(pdev)) { 255 if (IS_ERR(pdev)) {
265 pr_err("%s: Can't build omap_device for %s:%s.\n", 256 pr_err("%s: Can't build omap_device for %s:%s.\n",
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 652ccc574196..8cbfbc2918ce 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -24,14 +24,6 @@
24#include <plat/omap_hwmod.h> 24#include <plat/omap_hwmod.h>
25#include <plat/omap_device.h> 25#include <plat/omap_device.h>
26 26
27static struct omap_device_pm_latency omap_gpio_latency[] = {
28 [0] = {
29 .deactivate_func = omap_device_idle_hwmods,
30 .activate_func = omap_device_enable_hwmods,
31 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
32 },
33};
34
35static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) 27static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
36{ 28{
37 struct platform_device *pdev; 29 struct platform_device *pdev;
@@ -108,9 +100,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused)
108 } 100 }
109 101
110 pdev = omap_device_build(name, id - 1, oh, pdata, 102 pdev = omap_device_build(name, id - 1, oh, pdata,
111 sizeof(*pdata), omap_gpio_latency, 103 sizeof(*pdata), NULL, 0, false);
112 ARRAY_SIZE(omap_gpio_latency),
113 false);
114 kfree(pdata); 104 kfree(pdata);
115 105
116 if (IS_ERR(pdev)) { 106 if (IS_ERR(pdev)) {
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 2dc002a388b3..77085847e4e7 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -409,31 +409,17 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
409 return 0; 409 return 0;
410} 410}
411 411
412static struct omap_device_pm_latency omap_hsmmc_latency[] = {
413 [0] = {
414 .deactivate_func = omap_device_idle_hwmods,
415 .activate_func = omap_device_enable_hwmods,
416 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
417 },
418 /*
419 * XXX There should also be an entry here to power off/on the
420 * MMC regulators/PBIAS cells, etc.
421 */
422};
423
424#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16 412#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
425 413
426void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr) 414void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
427{ 415{
428 struct omap_hwmod *oh; 416 struct omap_hwmod *oh;
429 struct platform_device *pdev; 417 struct platform_device *pdev;
430 struct omap_device_pm_latency *ohl;
431 char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN]; 418 char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
432 struct omap_mmc_platform_data *mmc_data; 419 struct omap_mmc_platform_data *mmc_data;
433 struct omap_mmc_dev_attr *mmc_dev_attr; 420 struct omap_mmc_dev_attr *mmc_dev_attr;
434 char *name; 421 char *name;
435 int l; 422 int l;
436 int ohl_cnt = 0;
437 423
438 mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL); 424 mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
439 if (!mmc_data) { 425 if (!mmc_data) {
@@ -448,8 +434,6 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
448 omap_hsmmc_mux(mmc_data, (ctrl_nr - 1)); 434 omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
449 435
450 name = "omap_hsmmc"; 436 name = "omap_hsmmc";
451 ohl = omap_hsmmc_latency;
452 ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency);
453 437
454 l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN, 438 l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
455 "mmc%d", ctrl_nr); 439 "mmc%d", ctrl_nr);
@@ -468,7 +452,7 @@ void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
468 } 452 }
469 453
470 pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data, 454 pdev = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
471 sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false); 455 sizeof(struct omap_mmc_platform_data), NULL, 0, false);
472 if (IS_ERR(pdev)) { 456 if (IS_ERR(pdev)) {
473 WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name); 457 WARN(1, "Can't build omap_device for %s:%s.\n", name, oh->name);
474 kfree(mmc_data->slots[0].name); 458 kfree(mmc_data->slots[0].name);
diff --git a/arch/arm/mach-omap2/hwspinlock.c b/arch/arm/mach-omap2/hwspinlock.c
index 0b3ae9d9c3b3..36e21091b06a 100644
--- a/arch/arm/mach-omap2/hwspinlock.c
+++ b/arch/arm/mach-omap2/hwspinlock.c
@@ -23,14 +23,6 @@
23#include <plat/omap_hwmod.h> 23#include <plat/omap_hwmod.h>
24#include <plat/omap_device.h> 24#include <plat/omap_device.h>
25 25
26struct omap_device_pm_latency omap_spinlock_latency[] = {
27 {
28 .deactivate_func = omap_device_idle_hwmods,
29 .activate_func = omap_device_enable_hwmods,
30 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
31 }
32};
33
34int __init hwspinlocks_init(void) 26int __init hwspinlocks_init(void)
35{ 27{
36 int retval = 0; 28 int retval = 0;
@@ -48,9 +40,7 @@ int __init hwspinlocks_init(void)
48 if (oh == NULL) 40 if (oh == NULL)
49 return -EINVAL; 41 return -EINVAL;
50 42
51 pdev = omap_device_build(dev_name, 0, oh, NULL, 0, 43 pdev = omap_device_build(dev_name, 0, oh, NULL, 0, NULL, 0, false);
52 omap_spinlock_latency,
53 ARRAY_SIZE(omap_spinlock_latency), false);
54 if (IS_ERR(pdev)) { 44 if (IS_ERR(pdev)) {
55 pr_err("Can't build omap_device for %s:%s\n", dev_name, 45 pr_err("Can't build omap_device for %s:%s\n", dev_name,
56 oh_name); 46 oh_name);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index f01273006e4d..a5d8dce2a70b 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -34,8 +34,8 @@
34#include "clock2xxx.h" 34#include "clock2xxx.h"
35#include "clock3xxx.h" 35#include "clock3xxx.h"
36#include "clock44xx.h" 36#include "clock44xx.h"
37#include "io.h"
38 37
38#include <plat/common.h>
39#include <plat/omap-pm.h> 39#include <plat/omap-pm.h>
40#include "voltage.h" 40#include "voltage.h"
41#include "powerdomain.h" 41#include "powerdomain.h"
@@ -43,6 +43,7 @@
43#include "clockdomain.h" 43#include "clockdomain.h"
44#include <plat/omap_hwmod.h> 44#include <plat/omap_hwmod.h>
45#include <plat/multi.h> 45#include <plat/multi.h>
46#include <plat/common.h>
46 47
47/* 48/*
48 * The machine specific code may provide the extra mapping besides the 49 * The machine specific code may provide the extra mapping besides the
@@ -239,26 +240,11 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
239}; 240};
240#endif 241#endif
241 242
242static void __init _omap2_map_common_io(void)
243{
244 /* Normally devicemaps_init() would flush caches and tlb after
245 * mdesc->map_io(), but we must also do it here because of the CPU
246 * revision check below.
247 */
248 local_flush_tlb_all();
249 flush_cache_all();
250
251 omap2_check_revision();
252 omap_sram_init();
253 omap_init_consistent_dma_size();
254}
255
256#ifdef CONFIG_SOC_OMAP2420 243#ifdef CONFIG_SOC_OMAP2420
257void __init omap242x_map_common_io(void) 244void __init omap242x_map_common_io(void)
258{ 245{
259 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 246 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
260 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc)); 247 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
261 _omap2_map_common_io();
262} 248}
263#endif 249#endif
264 250
@@ -267,7 +253,6 @@ void __init omap243x_map_common_io(void)
267{ 253{
268 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc)); 254 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
269 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc)); 255 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
270 _omap2_map_common_io();
271} 256}
272#endif 257#endif
273 258
@@ -275,7 +260,6 @@ void __init omap243x_map_common_io(void)
275void __init omap34xx_map_common_io(void) 260void __init omap34xx_map_common_io(void)
276{ 261{
277 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc)); 262 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
278 _omap2_map_common_io();
279} 263}
280#endif 264#endif
281 265
@@ -283,7 +267,6 @@ void __init omap34xx_map_common_io(void)
283void __init omapti816x_map_common_io(void) 267void __init omapti816x_map_common_io(void)
284{ 268{
285 iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc)); 269 iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
286 _omap2_map_common_io();
287} 270}
288#endif 271#endif
289 272
@@ -291,7 +274,6 @@ void __init omapti816x_map_common_io(void)
291void __init omap44xx_map_common_io(void) 274void __init omap44xx_map_common_io(void)
292{ 275{
293 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc)); 276 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
294 _omap2_map_common_io();
295} 277}
296#endif 278#endif
297 279
@@ -337,33 +319,16 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
337/* See irq.c, omap4-common.c and entry-macro.S */ 319/* See irq.c, omap4-common.c and entry-macro.S */
338void __iomem *omap_irq_base; 320void __iomem *omap_irq_base;
339 321
340void __init omap2_init_common_infrastructure(void) 322static void __init omap_common_init_early(void)
341{ 323{
342 u8 postsetup_state; 324 omap2_check_revision();
325 omap_ioremap_init();
326 omap_init_consistent_dma_size();
327}
343 328
344 if (cpu_is_omap242x()) { 329static void __init omap_hwmod_init_postsetup(void)
345 omap2xxx_voltagedomains_init(); 330{
346 omap242x_powerdomains_init(); 331 u8 postsetup_state;
347 omap242x_clockdomains_init();
348 omap2420_hwmod_init();
349 } else if (cpu_is_omap243x()) {
350 omap2xxx_voltagedomains_init();
351 omap243x_powerdomains_init();
352 omap243x_clockdomains_init();
353 omap2430_hwmod_init();
354 } else if (cpu_is_omap34xx()) {
355 omap3xxx_voltagedomains_init();
356 omap3xxx_powerdomains_init();
357 omap3xxx_clockdomains_init();
358 omap3xxx_hwmod_init();
359 } else if (cpu_is_omap44xx()) {
360 omap44xx_voltagedomains_init();
361 omap44xx_powerdomains_init();
362 omap44xx_clockdomains_init();
363 omap44xx_hwmod_init();
364 } else {
365 pr_err("Could not init hwmod data - unknown SoC\n");
366 }
367 332
368 /* Set the default postsetup state for all hwmods */ 333 /* Set the default postsetup state for all hwmods */
369#ifdef CONFIG_PM_RUNTIME 334#ifdef CONFIG_PM_RUNTIME
@@ -392,67 +357,101 @@ void __init omap2_init_common_infrastructure(void)
392 &postsetup_state); 357 &postsetup_state);
393 358
394 omap_pm_if_early_init(); 359 omap_pm_if_early_init();
395
396 if (cpu_is_omap2420())
397 omap2420_clk_init();
398 else if (cpu_is_omap2430())
399 omap2430_clk_init();
400 else if (cpu_is_omap34xx())
401 omap3xxx_clk_init();
402 else if (cpu_is_omap44xx())
403 omap4xxx_clk_init();
404 else
405 pr_err("Could not init clock framework - unknown SoC\n");
406} 360}
407 361
408void __init omap2420_init_early(void) 362void __init omap2420_init_early(void)
409{ 363{
410 omap2_init_common_infrastructure(); 364 omap2_set_globals_242x();
365 omap_common_init_early();
366 omap2xxx_voltagedomains_init();
367 omap242x_powerdomains_init();
368 omap242x_clockdomains_init();
369 omap2420_hwmod_init();
370 omap_hwmod_init_postsetup();
371 omap2420_clk_init();
411} 372}
412 373
413void __init omap2430_init_early(void) 374void __init omap2430_init_early(void)
414{ 375{
415 omap2_init_common_infrastructure(); 376 omap2_set_globals_243x();
377 omap_common_init_early();
378 omap2xxx_voltagedomains_init();
379 omap243x_powerdomains_init();
380 omap243x_clockdomains_init();
381 omap2430_hwmod_init();
382 omap_hwmod_init_postsetup();
383 omap2430_clk_init();
384}
385
386/*
387 * Currently only board-omap3beagle.c should call this because of the
388 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
389 */
390void __init omap3_init_early(void)
391{
392 omap2_set_globals_3xxx();
393 omap_common_init_early();
394 omap3xxx_voltagedomains_init();
395 omap3xxx_powerdomains_init();
396 omap3xxx_clockdomains_init();
397 omap3xxx_hwmod_init();
398 omap_hwmod_init_postsetup();
399 omap3xxx_clk_init();
416} 400}
417 401
418void __init omap3430_init_early(void) 402void __init omap3430_init_early(void)
419{ 403{
420 omap2_init_common_infrastructure(); 404 omap3_init_early();
421} 405}
422 406
423void __init omap35xx_init_early(void) 407void __init omap35xx_init_early(void)
424{ 408{
425 omap2_init_common_infrastructure(); 409 omap3_init_early();
426} 410}
427 411
428void __init omap3630_init_early(void) 412void __init omap3630_init_early(void)
429{ 413{
430 omap2_init_common_infrastructure(); 414 omap3_init_early();
431} 415}
432 416
433void __init am35xx_init_early(void) 417void __init am35xx_init_early(void)
434{ 418{
435 omap2_init_common_infrastructure(); 419 omap3_init_early();
436} 420}
437 421
438void __init ti816x_init_early(void) 422void __init ti816x_init_early(void)
439{ 423{
440 omap2_init_common_infrastructure(); 424 omap2_set_globals_ti816x();
425 omap_common_init_early();
426 omap3xxx_voltagedomains_init();
427 omap3xxx_powerdomains_init();
428 omap3xxx_clockdomains_init();
429 omap3xxx_hwmod_init();
430 omap_hwmod_init_postsetup();
431 omap3xxx_clk_init();
441} 432}
442 433
443void __init omap4430_init_early(void) 434void __init omap4430_init_early(void)
444{ 435{
445 omap2_init_common_infrastructure(); 436 omap2_set_globals_443x();
437 omap_common_init_early();
438 omap44xx_voltagedomains_init();
439 omap44xx_powerdomains_init();
440 omap44xx_clockdomains_init();
441 omap44xx_hwmod_init();
442 omap_hwmod_init_postsetup();
443 omap4xxx_clk_init();
446} 444}
447 445
448void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 446void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
449 struct omap_sdrc_params *sdrc_cs1) 447 struct omap_sdrc_params *sdrc_cs1)
450{ 448{
449 omap_sram_init();
450
451 if (cpu_is_omap24xx() || omap3_has_sdrc()) { 451 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
452 omap2_sdrc_init(sdrc_cs0, sdrc_cs1); 452 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
453 _omap2_init_reprogram_sdrc(); 453 _omap2_init_reprogram_sdrc();
454 } 454 }
455
456} 455}
457 456
458/* 457/*
diff --git a/arch/arm/mach-omap2/io.h b/arch/arm/mach-omap2/io.h
index fd230c6cded5..e69de29bb2d1 100644
--- a/arch/arm/mach-omap2/io.h
+++ b/arch/arm/mach-omap2/io.h
@@ -1,7 +0,0 @@
1
2#ifndef __MACH_OMAP2_IO_H__
3#define __MACH_OMAP2_IO_H__
4
5extern int __init omap_sram_init(void);
6
7#endif /* __MACH_OMAP2_IO_H__ */
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 5063f253c4b9..292eee3be15f 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -122,14 +122,6 @@ static int omap3_enable_st_clock(unsigned int id, bool enable)
122 return 0; 122 return 0;
123} 123}
124 124
125struct omap_device_pm_latency omap2_mcbsp_latency[] = {
126 {
127 .deactivate_func = omap_device_idle_hwmods,
128 .activate_func = omap_device_enable_hwmods,
129 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
130 },
131};
132
133static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused) 125static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
134{ 126{
135 int id, count = 1; 127 int id, count = 1;
@@ -175,8 +167,7 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
175 count++; 167 count++;
176 } 168 }
177 pdev = omap_device_build_ss(name, id, oh_device, count, pdata, 169 pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
178 sizeof(*pdata), omap2_mcbsp_latency, 170 sizeof(*pdata), NULL, 0, false);
179 ARRAY_SIZE(omap2_mcbsp_latency), false);
180 kfree(pdata); 171 kfree(pdata);
181 if (IS_ERR(pdev)) { 172 if (IS_ERR(pdev)) {
182 pr_err("%s: Can't build omap_device for %s:%s.\n", __func__, 173 pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 889464dc7b2d..4412ddb7b3f6 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -102,8 +102,11 @@ void __init smp_init_cpus(void)
102{ 102{
103 unsigned int i, ncores; 103 unsigned int i, ncores;
104 104
105 /* Never released */ 105 /*
106 scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256); 106 * Currently we can't call ioremap here because
107 * SoC detection won't work until after init_early.
108 */
109 scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
107 BUG_ON(!scu_base); 110 BUG_ON(!scu_base);
108 111
109 ncores = scu_get_core_count(scu_base); 112 ncores = scu_get_core_count(scu_base);
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
index 7b9f1909ddb2..c8b1bef92e5a 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.c
+++ b/arch/arm/mach-omap2/omap_l3_noc.c
@@ -1,25 +1,25 @@
1/* 1/*
2 * OMAP4XXX L3 Interconnect error handling driver 2 * OMAP4XXX L3 Interconnect error handling driver
3 * 3 *
4 * Copyright (C) 2011 Texas Corporation 4 * Copyright (C) 2011 Texas Corporation
5 * Santosh Shilimkar <santosh.shilimkar@ti.com> 5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * Sricharan <r.sricharan@ti.com> 6 * Sricharan <r.sricharan@ti.com>
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or 10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version. 11 * (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21 * USA 21 * USA
22 */ 22 */
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
@@ -55,12 +55,12 @@
55static irqreturn_t l3_interrupt_handler(int irq, void *_l3) 55static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
56{ 56{
57 57
58 struct omap4_l3 *l3 = _l3; 58 struct omap4_l3 *l3 = _l3;
59 int inttype, i, j; 59 int inttype, i, k;
60 int err_src = 0; 60 int err_src = 0;
61 u32 std_err_main_addr, std_err_main, err_reg; 61 u32 std_err_main, err_reg, clear, masterid;
62 u32 base, slave_addr, clear; 62 void __iomem *base, *l3_targ_base;
63 char *source_name; 63 char *target_name, *master_name = "UN IDENTIFIED";
64 64
65 /* Get the Type of interrupt */ 65 /* Get the Type of interrupt */
66 inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; 66 inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
@@ -70,43 +70,50 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
70 * Read the regerr register of the clock domain 70 * Read the regerr register of the clock domain
71 * to determine the source 71 * to determine the source
72 */ 72 */
73 base = (u32)l3->l3_base[i]; 73 base = l3->l3_base[i];
74 err_reg = readl(base + l3_flagmux[i] + (inttype << 3)); 74 err_reg = __raw_readl(base + l3_flagmux[i] +
75 + L3_FLAGMUX_REGERR0 + (inttype << 3));
75 76
76 /* Get the corresponding error and analyse */ 77 /* Get the corresponding error and analyse */
77 if (err_reg) { 78 if (err_reg) {
78 /* Identify the source from control status register */ 79 /* Identify the source from control status register */
79 for (j = 0; !(err_reg & (1 << j)); j++) 80 err_src = __ffs(err_reg);
80 ;
81 81
82 err_src = j;
83 /* Read the stderrlog_main_source from clk domain */ 82 /* Read the stderrlog_main_source from clk domain */
84 std_err_main_addr = base + *(l3_targ[i] + err_src); 83 l3_targ_base = base + *(l3_targ[i] + err_src);
85 std_err_main = readl(std_err_main_addr); 84 std_err_main = __raw_readl(l3_targ_base +
85 L3_TARG_STDERRLOG_MAIN);
86 masterid = __raw_readl(l3_targ_base +
87 L3_TARG_STDERRLOG_MSTADDR);
86 88
87 switch (std_err_main & CUSTOM_ERROR) { 89 switch (std_err_main & CUSTOM_ERROR) {
88 case STANDARD_ERROR: 90 case STANDARD_ERROR:
89 source_name = 91 target_name =
90 l3_targ_stderrlog_main_name[i][err_src]; 92 l3_targ_inst_name[i][err_src];
91 93 WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n",
92 slave_addr = std_err_main_addr + 94 target_name,
93 L3_SLAVE_ADDRESS_OFFSET; 95 __raw_readl(l3_targ_base +
94 WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n", 96 L3_TARG_STDERRLOG_SLVOFSLSB));
95 source_name, readl(slave_addr));
96 /* clear the std error log*/ 97 /* clear the std error log*/
97 clear = std_err_main | CLEAR_STDERR_LOG; 98 clear = std_err_main | CLEAR_STDERR_LOG;
98 writel(clear, std_err_main_addr); 99 writel(clear, l3_targ_base +
100 L3_TARG_STDERRLOG_MAIN);
99 break; 101 break;
100 102
101 case CUSTOM_ERROR: 103 case CUSTOM_ERROR:
102 source_name = 104 target_name =
103 l3_targ_stderrlog_main_name[i][err_src]; 105 l3_targ_inst_name[i][err_src];
104 106 for (k = 0; k < NUM_OF_L3_MASTERS; k++) {
105 WARN(true, "CUSTOM SRESP error with SOURCE:%s\n", 107 if (masterid == l3_masters[k].id)
106 source_name); 108 master_name =
109 l3_masters[k].name;
110 }
111 WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n",
112 master_name, target_name);
107 /* clear the std error log*/ 113 /* clear the std error log*/
108 clear = std_err_main | CLEAR_STDERR_LOG; 114 clear = std_err_main | CLEAR_STDERR_LOG;
109 writel(clear, std_err_main_addr); 115 writel(clear, l3_targ_base +
116 L3_TARG_STDERRLOG_MAIN);
110 break; 117 break;
111 118
112 default: 119 default:
@@ -120,12 +127,11 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
120 return IRQ_HANDLED; 127 return IRQ_HANDLED;
121} 128}
122 129
123static int __init omap4_l3_probe(struct platform_device *pdev) 130static int __devinit omap4_l3_probe(struct platform_device *pdev)
124{ 131{
125 static struct omap4_l3 *l3; 132 static struct omap4_l3 *l3;
126 struct resource *res; 133 struct resource *res;
127 int ret; 134 int ret;
128 int irq;
129 135
130 l3 = kzalloc(sizeof(*l3), GFP_KERNEL); 136 l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
131 if (!l3) 137 if (!l3)
@@ -177,27 +183,25 @@ static int __init omap4_l3_probe(struct platform_device *pdev)
177 /* 183 /*
178 * Setup interrupt Handlers 184 * Setup interrupt Handlers
179 */ 185 */
180 irq = platform_get_irq(pdev, 0); 186 l3->debug_irq = platform_get_irq(pdev, 0);
181 ret = request_irq(irq, 187 ret = request_irq(l3->debug_irq,
182 l3_interrupt_handler, 188 l3_interrupt_handler,
183 IRQF_DISABLED, "l3-dbg-irq", l3); 189 IRQF_DISABLED, "l3-dbg-irq", l3);
184 if (ret) { 190 if (ret) {
185 pr_crit("L3: request_irq failed to register for 0x%x\n", 191 pr_crit("L3: request_irq failed to register for 0x%x\n",
186 OMAP44XX_IRQ_L3_DBG); 192 OMAP44XX_IRQ_L3_DBG);
187 goto err3; 193 goto err3;
188 } 194 }
189 l3->debug_irq = irq;
190 195
191 irq = platform_get_irq(pdev, 1); 196 l3->app_irq = platform_get_irq(pdev, 1);
192 ret = request_irq(irq, 197 ret = request_irq(l3->app_irq,
193 l3_interrupt_handler, 198 l3_interrupt_handler,
194 IRQF_DISABLED, "l3-app-irq", l3); 199 IRQF_DISABLED, "l3-app-irq", l3);
195 if (ret) { 200 if (ret) {
196 pr_crit("L3: request_irq failed to register for 0x%x\n", 201 pr_crit("L3: request_irq failed to register for 0x%x\n",
197 OMAP44XX_IRQ_L3_APP); 202 OMAP44XX_IRQ_L3_APP);
198 goto err4; 203 goto err4;
199 } 204 }
200 l3->app_irq = irq;
201 205
202 return 0; 206 return 0;
203 207
@@ -214,9 +218,9 @@ err0:
214 return ret; 218 return ret;
215} 219}
216 220
217static int __exit omap4_l3_remove(struct platform_device *pdev) 221static int __devexit omap4_l3_remove(struct platform_device *pdev)
218{ 222{
219 struct omap4_l3 *l3 = platform_get_drvdata(pdev); 223 struct omap4_l3 *l3 = platform_get_drvdata(pdev);
220 224
221 free_irq(l3->app_irq, l3); 225 free_irq(l3->app_irq, l3);
222 free_irq(l3->debug_irq, l3); 226 free_irq(l3->debug_irq, l3);
@@ -228,16 +232,29 @@ static int __exit omap4_l3_remove(struct platform_device *pdev)
228 return 0; 232 return 0;
229} 233}
230 234
235#if defined(CONFIG_OF)
236static const struct of_device_id l3_noc_match[] = {
237 {.compatible = "ti,omap4-l3-noc", },
238 {},
239}
240MODULE_DEVICE_TABLE(of, l3_noc_match);
241#else
242#define l3_noc_match NULL
243#endif
244
231static struct platform_driver omap4_l3_driver = { 245static struct platform_driver omap4_l3_driver = {
232 .remove = __exit_p(omap4_l3_remove), 246 .probe = omap4_l3_probe,
247 .remove = __devexit_p(omap4_l3_remove),
233 .driver = { 248 .driver = {
234 .name = "omap_l3_noc", 249 .name = "omap_l3_noc",
250 .owner = THIS_MODULE,
251 .of_match_table = l3_noc_match,
235 }, 252 },
236}; 253};
237 254
238static int __init omap4_l3_init(void) 255static int __init omap4_l3_init(void)
239{ 256{
240 return platform_driver_probe(&omap4_l3_driver, omap4_l3_probe); 257 return platform_driver_register(&omap4_l3_driver);
241} 258}
242postcore_initcall_sync(omap4_l3_init); 259postcore_initcall_sync(omap4_l3_init);
243 260
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
index 359b83348aed..90b50984cd2e 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.h
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -1,132 +1,162 @@
1 /* 1/*
2 * OMAP4XXX L3 Interconnect error handling driver header 2 * OMAP4XXX L3 Interconnect error handling driver header
3 * 3 *
4 * Copyright (C) 2011 Texas Corporation 4 * Copyright (C) 2011 Texas Corporation
5 * Santosh Shilimkar <santosh.shilimkar@ti.com> 5 * Santosh Shilimkar <santosh.shilimkar@ti.com>
6 * sricharan <r.sricharan@ti.com> 6 * sricharan <r.sricharan@ti.com>
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or 10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version. 11 * (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
21 * USA 21 * USA
22 */ 22 */
23#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 23#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
24#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 24#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25 25
26/*
27 * L3 register offsets
28 */
29#define L3_MODULES 3 26#define L3_MODULES 3
30#define CLEAR_STDERR_LOG (1 << 31) 27#define CLEAR_STDERR_LOG (1 << 31)
31#define CUSTOM_ERROR 0x2 28#define CUSTOM_ERROR 0x2
32#define STANDARD_ERROR 0x0 29#define STANDARD_ERROR 0x0
33#define INBAND_ERROR 0x0 30#define INBAND_ERROR 0x0
34#define EMIF_KERRLOG_OFFSET 0x10
35#define L3_SLAVE_ADDRESS_OFFSET 0x14
36#define LOGICAL_ADDR_ERRORLOG 0x4
37#define L3_APPLICATION_ERROR 0x0 31#define L3_APPLICATION_ERROR 0x0
38#define L3_DEBUG_ERROR 0x1 32#define L3_DEBUG_ERROR 0x1
39 33
40u32 l3_flagmux[L3_MODULES] = { 34/* L3 TARG register offsets */
41 0x50C, 35#define L3_TARG_STDERRLOG_MAIN 0x48
42 0x100C, 36#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
43 0X020C 37#define L3_TARG_STDERRLOG_MSTADDR 0x68
38#define L3_FLAGMUX_REGERR0 0xc
39
40#define NUM_OF_L3_MASTERS (sizeof(l3_masters)/sizeof(l3_masters[0]))
41
42static u32 l3_flagmux[L3_MODULES] = {
43 0x500,
44 0x1000,
45 0X0200
44}; 46};
45 47
46/* 48/* L3 Target standard Error register offsets */
47 * L3 Target standard Error register offsets 49static u32 l3_targ_inst_clk1[] = {
48 */ 50 0x100, /* DMM1 */
49u32 l3_targ_stderrlog_main_clk1[] = { 51 0x200, /* DMM2 */
50 0x148, /* DMM1 */ 52 0x300, /* ABE */
51 0x248, /* DMM2 */ 53 0x400, /* L4CFG */
52 0x348, /* ABE */ 54 0x600 /* CLK2 PWR DISC */
53 0x448, /* L4CFG */
54 0x648 /* CLK2 PWR DISC */
55}; 55};
56 56
57u32 l3_targ_stderrlog_main_clk2[] = { 57static u32 l3_targ_inst_clk2[] = {
58 0x548, /* CORTEX M3 */ 58 0x500, /* CORTEX M3 */
59 0x348, /* DSS */ 59 0x300, /* DSS */
60 0x148, /* GPMC */ 60 0x100, /* GPMC */
61 0x448, /* ISS */ 61 0x400, /* ISS */
62 0x748, /* IVAHD */ 62 0x700, /* IVAHD */
63 0xD48, /* missing in TRM corresponds to AES1*/ 63 0xD00, /* missing in TRM corresponds to AES1*/
64 0x948, /* L4 PER0*/ 64 0x900, /* L4 PER0*/
65 0x248, /* OCMRAM */ 65 0x200, /* OCMRAM */
66 0x148, /* missing in TRM corresponds to GPMC sERROR*/ 66 0x100, /* missing in TRM corresponds to GPMC sERROR*/
67 0x648, /* SGX */ 67 0x600, /* SGX */
68 0x848, /* SL2 */ 68 0x800, /* SL2 */
69 0x1648, /* C2C */ 69 0x1600, /* C2C */
70 0x1148, /* missing in TRM corresponds PWR DISC CLK1*/ 70 0x1100, /* missing in TRM corresponds PWR DISC CLK1*/
71 0xF48, /* missing in TRM corrsponds to SHA1*/ 71 0xF00, /* missing in TRM corrsponds to SHA1*/
72 0xE48, /* missing in TRM corresponds to AES2*/ 72 0xE00, /* missing in TRM corresponds to AES2*/
73 0xC48, /* L4 PER3 */ 73 0xC00, /* L4 PER3 */
74 0xA48, /* L4 PER1*/ 74 0xA00, /* L4 PER1*/
75 0xB48 /* L4 PER2*/ 75 0xB00 /* L4 PER2*/
76}; 76};
77 77
78u32 l3_targ_stderrlog_main_clk3[] = { 78static u32 l3_targ_inst_clk3[] = {
79 0x0148 /* EMUSS */ 79 0x0100 /* EMUSS */
80}; 80};
81 81
82char *l3_targ_stderrlog_main_name[L3_MODULES][18] = { 82static struct l3_masters_data {
83 u32 id;
84 char name[10];
85} l3_masters[] = {
86 { 0x0 , "MPU"},
87 { 0x10, "CS_ADP"},
88 { 0x14, "xxx"},
89 { 0x20, "DSP"},
90 { 0x30, "IVAHD"},
91 { 0x40, "ISS"},
92 { 0x44, "DucatiM3"},
93 { 0x48, "FaceDetect"},
94 { 0x50, "SDMA_Rd"},
95 { 0x54, "SDMA_Wr"},
96 { 0x58, "xxx"},
97 { 0x5C, "xxx"},
98 { 0x60, "SGX"},
99 { 0x70, "DSS"},
100 { 0x80, "C2C"},
101 { 0x88, "xxx"},
102 { 0x8C, "xxx"},
103 { 0x90, "HSI"},
104 { 0xA0, "MMC1"},
105 { 0xA4, "MMC2"},
106 { 0xA8, "MMC6"},
107 { 0xB0, "UNIPRO1"},
108 { 0xC0, "USBHOSTHS"},
109 { 0xC4, "USBOTGHS"},
110 { 0xC8, "USBHOSTFS"}
111};
112
113static char *l3_targ_inst_name[L3_MODULES][18] = {
83 { 114 {
84 "DMM1", 115 "DMM1",
85 "DMM2", 116 "DMM2",
86 "ABE", 117 "ABE",
87 "L4CFG", 118 "L4CFG",
88 "CLK2 PWR DISC", 119 "CLK2 PWR DISC",
89 }, 120 },
90 { 121 {
91 "CORTEX M3" , 122 "CORTEX M3" ,
92 "DSS ", 123 "DSS ",
93 "GPMC ", 124 "GPMC ",
94 "ISS ", 125 "ISS ",
95 "IVAHD ", 126 "IVAHD ",
96 "AES1", 127 "AES1",
97 "L4 PER0", 128 "L4 PER0",
98 "OCMRAM ", 129 "OCMRAM ",
99 "GPMC sERROR", 130 "GPMC sERROR",
100 "SGX ", 131 "SGX ",
101 "SL2 ", 132 "SL2 ",
102 "C2C ", 133 "C2C ",
103 "PWR DISC CLK1", 134 "PWR DISC CLK1",
104 "SHA1", 135 "SHA1",
105 "AES2", 136 "AES2",
106 "L4 PER3", 137 "L4 PER3",
107 "L4 PER1", 138 "L4 PER1",
108 "L4 PER2", 139 "L4 PER2",
109 }, 140 },
110 { 141 {
111 "EMUSS", 142 "EMUSS",
112 }, 143 },
113}; 144};
114 145
115u32 *l3_targ[L3_MODULES] = { 146static u32 *l3_targ[L3_MODULES] = {
116 l3_targ_stderrlog_main_clk1, 147 l3_targ_inst_clk1,
117 l3_targ_stderrlog_main_clk2, 148 l3_targ_inst_clk2,
118 l3_targ_stderrlog_main_clk3, 149 l3_targ_inst_clk3,
119}; 150};
120 151
121struct omap4_l3 { 152struct omap4_l3 {
122 struct device *dev; 153 struct device *dev;
123 struct clk *ick; 154 struct clk *ick;
124 155
125 /* memory base */ 156 /* memory base */
126 void __iomem *l3_base[4]; 157 void __iomem *l3_base[L3_MODULES];
127 158
128 int debug_irq; 159 int debug_irq;
129 int app_irq; 160 int app_irq;
130}; 161};
131
132#endif 162#endif
diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
index 873c0e33b512..a05a62f9ee5b 100644
--- a/arch/arm/mach-omap2/omap_l3_smx.c
+++ b/arch/arm/mach-omap2/omap_l3_smx.c
@@ -1,26 +1,26 @@
1 /* 1/*
2 * OMAP3XXX L3 Interconnect Driver 2 * OMAP3XXX L3 Interconnect Driver
3 * 3 *
4 * Copyright (C) 2011 Texas Corporation 4 * Copyright (C) 2011 Texas Corporation
5 * Felipe Balbi <balbi@ti.com> 5 * Felipe Balbi <balbi@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com> 6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * Sricharan <r.sricharan@ti.com> 7 * Sricharan <r.sricharan@ti.com>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or 11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version. 12 * (at your option) any later version.
13 * 13 *
14 * This program is distributed in the hope that it will be useful, 14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA 22 * USA
23 */ 23 */
24 24
25#include <linux/kernel.h> 25#include <linux/kernel.h>
26#include <linux/slab.h> 26#include <linux/slab.h>
@@ -135,7 +135,7 @@ static char *omap3_l3_initiator_string(u8 initid)
135 } 135 }
136} 136}
137 137
138/** 138/*
139 * omap3_l3_block_irq - handles a register block's irq 139 * omap3_l3_block_irq - handles a register block's irq
140 * @l3: struct omap3_l3 * 140 * @l3: struct omap3_l3 *
141 * @base: register block base address 141 * @base: register block base address
@@ -150,30 +150,29 @@ static char *omap3_l3_initiator_string(u8 initid)
150static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3, 150static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
151 u64 error, int error_addr) 151 u64 error, int error_addr)
152{ 152{
153 u8 code = omap3_l3_decode_error_code(error); 153 u8 code = omap3_l3_decode_error_code(error);
154 u8 initid = omap3_l3_decode_initid(error); 154 u8 initid = omap3_l3_decode_initid(error);
155 u8 multi = error & L3_ERROR_LOG_MULTI; 155 u8 multi = error & L3_ERROR_LOG_MULTI;
156 u32 address = omap3_l3_decode_addr(error_addr); 156 u32 address = omap3_l3_decode_addr(error_addr);
157 157
158 WARN(true, "%s seen by %s %s at address %x\n", 158 WARN(true, "%s seen by %s %s at address %x\n",
159 omap3_l3_code_string(code), 159 omap3_l3_code_string(code),
160 omap3_l3_initiator_string(initid), 160 omap3_l3_initiator_string(initid),
161 multi ? "Multiple Errors" : "", 161 multi ? "Multiple Errors" : "", address);
162 address);
163 162
164 return IRQ_HANDLED; 163 return IRQ_HANDLED;
165} 164}
166 165
167static irqreturn_t omap3_l3_app_irq(int irq, void *_l3) 166static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
168{ 167{
169 struct omap3_l3 *l3 = _l3; 168 struct omap3_l3 *l3 = _l3;
170 u64 status, clear; 169 u64 status, clear;
171 u64 error; 170 u64 error;
172 u64 error_addr; 171 u64 error_addr;
173 u64 err_source = 0; 172 u64 err_source = 0;
174 void __iomem *base; 173 void __iomem *base;
175 int int_type; 174 int int_type;
176 irqreturn_t ret = IRQ_NONE; 175 irqreturn_t ret = IRQ_NONE;
177 176
178 int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; 177 int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
179 if (!int_type) { 178 if (!int_type) {
@@ -191,14 +190,12 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
191 } 190 }
192 191
193 /* identify the error source */ 192 /* identify the error source */
194 for (err_source = 0; !(status & (1 << err_source)); err_source++) 193 err_source = __ffs(status);
195 ;
196 194
197 base = l3->rt + *(omap3_l3_bases[int_type] + err_source); 195 base = l3->rt + omap3_l3_bases[int_type][err_source];
198 error = omap3_l3_readll(base, L3_ERROR_LOG); 196 error = omap3_l3_readll(base, L3_ERROR_LOG);
199 if (error) { 197 if (error) {
200 error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR); 198 error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
201
202 ret |= omap3_l3_block_irq(l3, error, error_addr); 199 ret |= omap3_l3_block_irq(l3, error, error_addr);
203 } 200 }
204 201
@@ -215,9 +212,9 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
215 212
216static int __init omap3_l3_probe(struct platform_device *pdev) 213static int __init omap3_l3_probe(struct platform_device *pdev)
217{ 214{
218 struct omap3_l3 *l3; 215 struct omap3_l3 *l3;
219 struct resource *res; 216 struct resource *res;
220 int ret; 217 int ret;
221 218
222 l3 = kzalloc(sizeof(*l3), GFP_KERNEL); 219 l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
223 if (!l3) 220 if (!l3)
diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h
index ba2ed9a850cc..4f3cebca4179 100644
--- a/arch/arm/mach-omap2/omap_l3_smx.h
+++ b/arch/arm/mach-omap2/omap_l3_smx.h
@@ -1,26 +1,26 @@
1 /* 1/*
2 * OMAP3XXX L3 Interconnect Driver header 2 * OMAP3XXX L3 Interconnect Driver header
3 * 3 *
4 * Copyright (C) 2011 Texas Corporation 4 * Copyright (C) 2011 Texas Corporation
5 * Felipe Balbi <balbi@ti.com> 5 * Felipe Balbi <balbi@ti.com>
6 * Santosh Shilimkar <santosh.shilimkar@ti.com> 6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * sricharan <r.sricharan@ti.com> 7 * sricharan <r.sricharan@ti.com>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or 11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version. 12 * (at your option) any later version.
13 * 13 *
14 * This program is distributed in the hope that it will be useful, 14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
22 * USA 22 * USA
23 */ 23 */
24#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 24#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 25#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
26 26
@@ -40,7 +40,7 @@
40#define L3_SI_CONTROL 0x020 40#define L3_SI_CONTROL 0x020
41#define L3_SI_FLAG_STATUS_0 0x510 41#define L3_SI_FLAG_STATUS_0 0x510
42 42
43const u64 shift = 1; 43static const u64 shift = 1;
44 44
45#define L3_STATUS_0_MPUIA_BRST (shift << 0) 45#define L3_STATUS_0_MPUIA_BRST (shift << 0)
46#define L3_STATUS_0_MPUIA_RSP (shift << 1) 46#define L3_STATUS_0_MPUIA_RSP (shift << 1)
@@ -78,32 +78,32 @@ const u64 shift = 1;
78#define L3_STATUS_0_L4EMUTA_REQ (shift << 60) 78#define L3_STATUS_0_L4EMUTA_REQ (shift << 60)
79#define L3_STATUS_0_MAD2DTA_REQ (shift << 61) 79#define L3_STATUS_0_MAD2DTA_REQ (shift << 61)
80 80
81#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \ 81#define L3_STATUS_0_TIMEOUT_MASK (L3_STATUS_0_MPUIA_BRST \
82 | L3_STATUS_0_MPUIA_RSP \ 82 | L3_STATUS_0_MPUIA_RSP \
83 | L3_STATUS_0_IVAIA_BRST \ 83 | L3_STATUS_0_IVAIA_BRST \
84 | L3_STATUS_0_IVAIA_RSP \ 84 | L3_STATUS_0_IVAIA_RSP \
85 | L3_STATUS_0_SGXIA_BRST \ 85 | L3_STATUS_0_SGXIA_BRST \
86 | L3_STATUS_0_SGXIA_RSP \ 86 | L3_STATUS_0_SGXIA_RSP \
87 | L3_STATUS_0_CAMIA_BRST \ 87 | L3_STATUS_0_CAMIA_BRST \
88 | L3_STATUS_0_CAMIA_RSP \ 88 | L3_STATUS_0_CAMIA_RSP \
89 | L3_STATUS_0_DISPIA_BRST \ 89 | L3_STATUS_0_DISPIA_BRST \
90 | L3_STATUS_0_DISPIA_RSP \ 90 | L3_STATUS_0_DISPIA_RSP \
91 | L3_STATUS_0_DMARDIA_BRST \ 91 | L3_STATUS_0_DMARDIA_BRST \
92 | L3_STATUS_0_DMARDIA_RSP \ 92 | L3_STATUS_0_DMARDIA_RSP \
93 | L3_STATUS_0_DMAWRIA_BRST \ 93 | L3_STATUS_0_DMAWRIA_BRST \
94 | L3_STATUS_0_DMAWRIA_RSP \ 94 | L3_STATUS_0_DMAWRIA_RSP \
95 | L3_STATUS_0_USBOTGIA_BRST \ 95 | L3_STATUS_0_USBOTGIA_BRST \
96 | L3_STATUS_0_USBOTGIA_RSP \ 96 | L3_STATUS_0_USBOTGIA_RSP \
97 | L3_STATUS_0_USBHOSTIA_BRST \ 97 | L3_STATUS_0_USBHOSTIA_BRST \
98 | L3_STATUS_0_SMSTA_REQ \ 98 | L3_STATUS_0_SMSTA_REQ \
99 | L3_STATUS_0_GPMCTA_REQ \ 99 | L3_STATUS_0_GPMCTA_REQ \
100 | L3_STATUS_0_OCMRAMTA_REQ \ 100 | L3_STATUS_0_OCMRAMTA_REQ \
101 | L3_STATUS_0_OCMROMTA_REQ \ 101 | L3_STATUS_0_OCMROMTA_REQ \
102 | L3_STATUS_0_IVATA_REQ \ 102 | L3_STATUS_0_IVATA_REQ \
103 | L3_STATUS_0_SGXTA_REQ \ 103 | L3_STATUS_0_SGXTA_REQ \
104 | L3_STATUS_0_L4CORETA_REQ \ 104 | L3_STATUS_0_L4CORETA_REQ \
105 | L3_STATUS_0_L4PERTA_REQ \ 105 | L3_STATUS_0_L4PERTA_REQ \
106 | L3_STATUS_0_L4EMUTA_REQ \ 106 | L3_STATUS_0_L4EMUTA_REQ \
107 | L3_STATUS_0_MAD2DTA_REQ) 107 | L3_STATUS_0_MAD2DTA_REQ)
108 108
109#define L3_SI_FLAG_STATUS_1 0x530 109#define L3_SI_FLAG_STATUS_1 0x530
@@ -137,19 +137,19 @@ const u64 shift = 1;
137 137
138enum omap3_l3_initiator_id { 138enum omap3_l3_initiator_id {
139 /* LCD has 1 ID */ 139 /* LCD has 1 ID */
140 OMAP_L3_LCD = 29, 140 OMAP_L3_LCD = 29,
141 /* SAD2D has 1 ID */ 141 /* SAD2D has 1 ID */
142 OMAP_L3_SAD2D = 28, 142 OMAP_L3_SAD2D = 28,
143 /* MPU has 5 IDs */ 143 /* MPU has 5 IDs */
144 OMAP_L3_IA_MPU_SS_1 = 27, 144 OMAP_L3_IA_MPU_SS_1 = 27,
145 OMAP_L3_IA_MPU_SS_2 = 26, 145 OMAP_L3_IA_MPU_SS_2 = 26,
146 OMAP_L3_IA_MPU_SS_3 = 25, 146 OMAP_L3_IA_MPU_SS_3 = 25,
147 OMAP_L3_IA_MPU_SS_4 = 24, 147 OMAP_L3_IA_MPU_SS_4 = 24,
148 OMAP_L3_IA_MPU_SS_5 = 23, 148 OMAP_L3_IA_MPU_SS_5 = 23,
149 /* IVA2.2 SS has 3 IDs*/ 149 /* IVA2.2 SS has 3 IDs*/
150 OMAP_L3_IA_IVA_SS_1 = 22, 150 OMAP_L3_IA_IVA_SS_1 = 22,
151 OMAP_L3_IA_IVA_SS_2 = 21, 151 OMAP_L3_IA_IVA_SS_2 = 21,
152 OMAP_L3_IA_IVA_SS_3 = 20, 152 OMAP_L3_IA_IVA_SS_3 = 20,
153 /* IVA 2.2 SS DMA has 6 IDS */ 153 /* IVA 2.2 SS DMA has 6 IDS */
154 OMAP_L3_IA_IVA_SS_DMA_1 = 19, 154 OMAP_L3_IA_IVA_SS_DMA_1 = 19,
155 OMAP_L3_IA_IVA_SS_DMA_2 = 18, 155 OMAP_L3_IA_IVA_SS_DMA_2 = 18,
@@ -158,25 +158,25 @@ enum omap3_l3_initiator_id {
158 OMAP_L3_IA_IVA_SS_DMA_5 = 15, 158 OMAP_L3_IA_IVA_SS_DMA_5 = 15,
159 OMAP_L3_IA_IVA_SS_DMA_6 = 14, 159 OMAP_L3_IA_IVA_SS_DMA_6 = 14,
160 /* SGX has 1 ID */ 160 /* SGX has 1 ID */
161 OMAP_L3_IA_SGX = 13, 161 OMAP_L3_IA_SGX = 13,
162 /* CAM has 3 ID */ 162 /* CAM has 3 ID */
163 OMAP_L3_IA_CAM_1 = 12, 163 OMAP_L3_IA_CAM_1 = 12,
164 OMAP_L3_IA_CAM_2 = 11, 164 OMAP_L3_IA_CAM_2 = 11,
165 OMAP_L3_IA_CAM_3 = 10, 165 OMAP_L3_IA_CAM_3 = 10,
166 /* DAP has 1 ID */ 166 /* DAP has 1 ID */
167 OMAP_L3_IA_DAP = 9, 167 OMAP_L3_IA_DAP = 9,
168 /* SDMA WR has 2 IDs */ 168 /* SDMA WR has 2 IDs */
169 OMAP_L3_SDMA_WR_1 = 8, 169 OMAP_L3_SDMA_WR_1 = 8,
170 OMAP_L3_SDMA_WR_2 = 7, 170 OMAP_L3_SDMA_WR_2 = 7,
171 /* SDMA RD has 4 IDs */ 171 /* SDMA RD has 4 IDs */
172 OMAP_L3_SDMA_RD_1 = 6, 172 OMAP_L3_SDMA_RD_1 = 6,
173 OMAP_L3_SDMA_RD_2 = 5, 173 OMAP_L3_SDMA_RD_2 = 5,
174 OMAP_L3_SDMA_RD_3 = 4, 174 OMAP_L3_SDMA_RD_3 = 4,
175 OMAP_L3_SDMA_RD_4 = 3, 175 OMAP_L3_SDMA_RD_4 = 3,
176 /* HSUSB OTG has 1 ID */ 176 /* HSUSB OTG has 1 ID */
177 OMAP_L3_USBOTG = 2, 177 OMAP_L3_USBOTG = 2,
178 /* HSUSB HOST has 1 ID */ 178 /* HSUSB HOST has 1 ID */
179 OMAP_L3_USBHOST = 1, 179 OMAP_L3_USBHOST = 1,
180}; 180};
181 181
182enum omap3_l3_code { 182enum omap3_l3_code {
@@ -192,21 +192,21 @@ enum omap3_l3_code {
192}; 192};
193 193
194struct omap3_l3 { 194struct omap3_l3 {
195 struct device *dev; 195 struct device *dev;
196 struct clk *ick; 196 struct clk *ick;
197 197
198 /* memory base*/ 198 /* memory base*/
199 void __iomem *rt; 199 void __iomem *rt;
200 200
201 int debug_irq; 201 int debug_irq;
202 int app_irq; 202 int app_irq;
203 203
204 /* true when and inband functional error occurs */ 204 /* true when and inband functional error occurs */
205 unsigned inband:1; 205 unsigned inband:1;
206}; 206};
207 207
208/* offsets for l3 agents in order with the Flag status register */ 208/* offsets for l3 agents in order with the Flag status register */
209unsigned int __iomem omap3_l3_app_bases[] = { 209static unsigned int omap3_l3_app_bases[] = {
210 /* MPU IA */ 210 /* MPU IA */
211 0x1400, 211 0x1400,
212 0x1400, 212 0x1400,
@@ -305,7 +305,7 @@ unsigned int __iomem omap3_l3_app_bases[] = {
305 0, 305 0,
306}; 306};
307 307
308unsigned int __iomem omap3_l3_debug_bases[] = { 308static unsigned int omap3_l3_debug_bases[] = {
309 /* MPU DATA IA */ 309 /* MPU DATA IA */
310 0x1400, 310 0x1400,
311 /* RESERVED */ 311 /* RESERVED */
@@ -321,7 +321,7 @@ unsigned int __iomem omap3_l3_debug_bases[] = {
321 /* REST RESERVED */ 321 /* REST RESERVED */
322}; 322};
323 323
324u32 *omap3_l3_bases[] = { 324static u32 *omap3_l3_bases[] = {
325 omap3_l3_app_bases, 325 omap3_l3_app_bases,
326 omap3_l3_debug_bases, 326 omap3_l3_debug_bases,
327}; 327};
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 0844e2ecfb4a..2ab7a9e17fe2 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -26,38 +26,7 @@
26 26
27static struct omap_device_pm_latency *pm_lats; 27static struct omap_device_pm_latency *pm_lats;
28 28
29static struct device *mpu_dev; 29static int _init_omap_device(char *name)
30static struct device *iva_dev;
31static struct device *l3_dev;
32static struct device *dsp_dev;
33
34struct device *omap2_get_mpuss_device(void)
35{
36 WARN_ON_ONCE(!mpu_dev);
37 return mpu_dev;
38}
39
40struct device *omap2_get_iva_device(void)
41{
42 WARN_ON_ONCE(!iva_dev);
43 return iva_dev;
44}
45
46struct device *omap2_get_l3_device(void)
47{
48 WARN_ON_ONCE(!l3_dev);
49 return l3_dev;
50}
51
52struct device *omap4_get_dsp_device(void)
53{
54 WARN_ON_ONCE(!dsp_dev);
55 return dsp_dev;
56}
57EXPORT_SYMBOL(omap4_get_dsp_device);
58
59/* static int _init_omap_device(struct omap_hwmod *oh, void *user) */
60static int _init_omap_device(char *name, struct device **new_dev)
61{ 30{
62 struct omap_hwmod *oh; 31 struct omap_hwmod *oh;
63 struct platform_device *pdev; 32 struct platform_device *pdev;
@@ -72,8 +41,6 @@ static int _init_omap_device(char *name, struct device **new_dev)
72 __func__, name)) 41 __func__, name))
73 return -ENODEV; 42 return -ENODEV;
74 43
75 *new_dev = &pdev->dev;
76
77 return 0; 44 return 0;
78} 45}
79 46
@@ -82,16 +49,16 @@ static int _init_omap_device(char *name, struct device **new_dev)
82 */ 49 */
83static void omap2_init_processor_devices(void) 50static void omap2_init_processor_devices(void)
84{ 51{
85 _init_omap_device("mpu", &mpu_dev); 52 _init_omap_device("mpu");
86 if (omap3_has_iva()) 53 if (omap3_has_iva())
87 _init_omap_device("iva", &iva_dev); 54 _init_omap_device("iva");
88 55
89 if (cpu_is_omap44xx()) { 56 if (cpu_is_omap44xx()) {
90 _init_omap_device("l3_main_1", &l3_dev); 57 _init_omap_device("l3_main_1");
91 _init_omap_device("dsp", &dsp_dev); 58 _init_omap_device("dsp");
92 _init_omap_device("iva", &iva_dev); 59 _init_omap_device("iva");
93 } else { 60 } else {
94 _init_omap_device("l3_main", &l3_dev); 61 _init_omap_device("l3_main");
95 } 62 }
96} 63}
97 64
@@ -169,18 +136,26 @@ err:
169 * in the opp entry 136 * in the opp entry
170 */ 137 */
171static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name, 138static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
172 struct device *dev) 139 const char *oh_name)
173{ 140{
174 struct voltagedomain *voltdm; 141 struct voltagedomain *voltdm;
175 struct clk *clk; 142 struct clk *clk;
176 struct opp *opp; 143 struct opp *opp;
177 unsigned long freq, bootup_volt; 144 unsigned long freq, bootup_volt;
145 struct device *dev;
178 146
179 if (!vdd_name || !clk_name || !dev) { 147 if (!vdd_name || !clk_name || !oh_name) {
180 pr_err("%s: invalid parameters\n", __func__); 148 pr_err("%s: invalid parameters\n", __func__);
181 goto exit; 149 goto exit;
182 } 150 }
183 151
152 dev = omap_device_get_by_hwmod_name(oh_name);
153 if (IS_ERR(dev)) {
154 pr_err("%s: Unable to get dev pointer for hwmod %s\n",
155 __func__, oh_name);
156 goto exit;
157 }
158
184 voltdm = voltdm_lookup(vdd_name); 159 voltdm = voltdm_lookup(vdd_name);
185 if (IS_ERR(voltdm)) { 160 if (IS_ERR(voltdm)) {
186 pr_err("%s: unable to get vdd pointer for vdd_%s\n", 161 pr_err("%s: unable to get vdd pointer for vdd_%s\n",
@@ -224,8 +199,8 @@ static void __init omap3_init_voltages(void)
224 if (!cpu_is_omap34xx()) 199 if (!cpu_is_omap34xx())
225 return; 200 return;
226 201
227 omap2_set_init_voltage("mpu_iva", "dpll1_ck", mpu_dev); 202 omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu");
228 omap2_set_init_voltage("core", "l3_ick", l3_dev); 203 omap2_set_init_voltage("core", "l3_ick", "l3_main");
229} 204}
230 205
231static void __init omap4_init_voltages(void) 206static void __init omap4_init_voltages(void)
@@ -233,14 +208,15 @@ static void __init omap4_init_voltages(void)
233 if (!cpu_is_omap44xx()) 208 if (!cpu_is_omap44xx())
234 return; 209 return;
235 210
236 omap2_set_init_voltage("mpu", "dpll_mpu_ck", mpu_dev); 211 omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu");
237 omap2_set_init_voltage("core", "l3_div_ck", l3_dev); 212 omap2_set_init_voltage("core", "l3_div_ck", "l3_main_1");
238 omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", iva_dev); 213 omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva");
239} 214}
240 215
241static int __init omap2_common_pm_init(void) 216static int __init omap2_common_pm_init(void)
242{ 217{
243 omap2_init_processor_devices(); 218 if (!of_have_populated_dt())
219 omap2_init_processor_devices();
244 omap_pm_if_init(); 220 omap_pm_if_init();
245 221
246 return 0; 222 return 0;
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 2e40a5cf0163..8db5f035eb0a 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -151,17 +151,10 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
151 151
152void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals) 152void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
153{ 153{
154 /* Static mapping, never released */ 154 if (omap2_globals->prm)
155 if (omap2_globals->prm) { 155 prm_base = omap2_globals->prm;
156 prm_base = ioremap(omap2_globals->prm, SZ_8K); 156 if (omap2_globals->cm)
157 WARN_ON(!prm_base); 157 cm_base = omap2_globals->cm;
158 } 158 if (omap2_globals->cm2)
159 if (omap2_globals->cm) { 159 cm2_base = omap2_globals->cm2;
160 cm_base = ioremap(omap2_globals->cm, SZ_8K);
161 WARN_ON(!cm_base);
162 }
163 if (omap2_globals->cm2) {
164 cm2_base = ioremap(omap2_globals->cm2, SZ_8K);
165 WARN_ON(!cm2_base);
166 }
167} 160}
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index da6f3a63b5d5..8f2782874771 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -117,15 +117,10 @@ int omap2_sdrc_get_params(unsigned long r,
117 117
118void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals) 118void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
119{ 119{
120 /* Static mapping, never released */ 120 if (omap2_globals->sdrc)
121 if (omap2_globals->sdrc) { 121 omap2_sdrc_base = omap2_globals->sdrc;
122 omap2_sdrc_base = ioremap(omap2_globals->sdrc, SZ_64K); 122 if (omap2_globals->sms)
123 WARN_ON(!omap2_sdrc_base); 123 omap2_sms_base = omap2_globals->sms;
124 }
125 if (omap2_globals->sms) {
126 omap2_sms_base = ioremap(omap2_globals->sms, SZ_64K);
127 WARN_ON(!omap2_sms_base);
128 }
129} 124}
130 125
131/** 126/**
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 3d1c1d393f8f..9992dbfdfdb3 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -107,28 +107,6 @@ struct omap_uart_state {
107static LIST_HEAD(uart_list); 107static LIST_HEAD(uart_list);
108static u8 num_uarts; 108static u8 num_uarts;
109 109
110static int uart_idle_hwmod(struct omap_device *od)
111{
112 omap_hwmod_idle(od->hwmods[0]);
113
114 return 0;
115}
116
117static int uart_enable_hwmod(struct omap_device *od)
118{
119 omap_hwmod_enable(od->hwmods[0]);
120
121 return 0;
122}
123
124static struct omap_device_pm_latency omap_uart_latency[] = {
125 {
126 .deactivate_func = uart_idle_hwmod,
127 .activate_func = uart_enable_hwmod,
128 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
129 },
130};
131
132static inline unsigned int __serial_read_reg(struct uart_port *up, 110static inline unsigned int __serial_read_reg(struct uart_port *up,
133 int offset) 111 int offset)
134{ 112{
@@ -800,8 +778,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
800 return; 778 return;
801 779
802 pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size, 780 pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
803 omap_uart_latency, 781 NULL, 0, false);
804 ARRAY_SIZE(omap_uart_latency), false);
805 WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n", 782 WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
806 name, oh->name); 783 name, oh->name);
807 784
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index eba9f9a8ab65..9f43fcc05d3e 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -31,14 +31,6 @@
31 31
32static bool sr_enable_on_init; 32static bool sr_enable_on_init;
33 33
34static struct omap_device_pm_latency omap_sr_latency[] = {
35 {
36 .deactivate_func = omap_device_idle_hwmods,
37 .activate_func = omap_device_enable_hwmods,
38 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST
39 },
40};
41
42/* Read EFUSE values from control registers for OMAP3430 */ 34/* Read EFUSE values from control registers for OMAP3430 */
43static void __init sr_set_nvalues(struct omap_volt_data *volt_data, 35static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
44 struct omap_sr_data *sr_data) 36 struct omap_sr_data *sr_data)
@@ -121,8 +113,7 @@ static int sr_dev_init(struct omap_hwmod *oh, void *user)
121 sr_data->enable_on_init = sr_enable_on_init; 113 sr_data->enable_on_init = sr_enable_on_init;
122 114
123 pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data), 115 pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data),
124 omap_sr_latency, 116 NULL, 0, 0);
125 ARRAY_SIZE(omap_sr_latency), 0);
126 if (IS_ERR(pdev)) 117 if (IS_ERR(pdev))
127 pr_warning("%s: Could not build omap_device for %s: %s.\n\n", 118 pr_warning("%s: Could not build omap_device for %s: %s.\n\n",
128 __func__, name, oh->name); 119 __func__, name, oh->name);
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 1140e98c9773..e49fc7be2229 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -434,7 +434,7 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
434 int ret = 0; 434 int ret = 0;
435 char *name = "omap_timer"; 435 char *name = "omap_timer";
436 struct dmtimer_platform_data *pdata; 436 struct dmtimer_platform_data *pdata;
437 struct omap_device *od; 437 struct platform_device *pdev;
438 struct omap_timer_capability_dev_attr *timer_dev_attr; 438 struct omap_timer_capability_dev_attr *timer_dev_attr;
439 struct powerdomain *pwrdm; 439 struct powerdomain *pwrdm;
440 440
@@ -476,12 +476,12 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
476#ifdef CONFIG_PM 476#ifdef CONFIG_PM
477 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; 477 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
478#endif 478#endif
479 od = omap_device_build(name, id, oh, pdata, sizeof(*pdata), 479 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
480 omap2_dmtimer_latency, 480 omap2_dmtimer_latency,
481 ARRAY_SIZE(omap2_dmtimer_latency), 481 ARRAY_SIZE(omap2_dmtimer_latency),
482 0); 482 0);
483 483
484 if (IS_ERR(od)) { 484 if (IS_ERR(pdev)) {
485 pr_err("%s: Can't build omap_device for %s: %s.\n", 485 pr_err("%s: Can't build omap_device for %s: %s.\n",
486 __func__, name, oh->name); 486 __func__, name, oh->name);
487 ret = -EINVAL; 487 ret = -EINVAL;
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 19e4dac62a8c..47fb5d607630 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -60,14 +60,6 @@ static struct musb_hdrc_platform_data musb_plat = {
60 60
61static u64 musb_dmamask = DMA_BIT_MASK(32); 61static u64 musb_dmamask = DMA_BIT_MASK(32);
62 62
63static struct omap_device_pm_latency omap_musb_latency[] = {
64 {
65 .deactivate_func = omap_device_idle_hwmods,
66 .activate_func = omap_device_enable_hwmods,
67 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
68 },
69};
70
71static void usb_musb_mux_init(struct omap_musb_board_data *board_data) 63static void usb_musb_mux_init(struct omap_musb_board_data *board_data)
72{ 64{
73 switch (board_data->interface_type) { 65 switch (board_data->interface_type) {
@@ -115,7 +107,6 @@ static struct omap_musb_board_data musb_default_board_data = {
115void __init usb_musb_init(struct omap_musb_board_data *musb_board_data) 107void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
116{ 108{
117 struct omap_hwmod *oh; 109 struct omap_hwmod *oh;
118 struct omap_device *od;
119 struct platform_device *pdev; 110 struct platform_device *pdev;
120 struct device *dev; 111 struct device *dev;
121 int bus_id = -1; 112 int bus_id = -1;
@@ -145,22 +136,19 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
145 name = "musb-omap2430"; 136 name = "musb-omap2430";
146 } 137 }
147 138
148 oh = omap_hwmod_lookup(oh_name); 139 oh = omap_hwmod_lookup(oh_name);
149 if (!oh) { 140 if (WARN(!oh, "%s: could not find omap_hwmod for %s\n",
150 pr_err("Could not look up %s\n", oh_name); 141 __func__, oh_name))
151 return; 142 return;
152 }
153 143
154 od = omap_device_build(name, bus_id, oh, &musb_plat, 144 pdev = omap_device_build(name, bus_id, oh, &musb_plat,
155 sizeof(musb_plat), omap_musb_latency, 145 sizeof(musb_plat), NULL, 0, false);
156 ARRAY_SIZE(omap_musb_latency), false); 146 if (IS_ERR(pdev)) {
157 if (IS_ERR(od)) {
158 pr_err("Could not build omap_device for %s %s\n", 147 pr_err("Could not build omap_device for %s %s\n",
159 name, oh_name); 148 name, oh_name);
160 return; 149 return;
161 } 150 }
162 151
163 pdev = &od->pdev;
164 dev = &pdev->dev; 152 dev = &pdev->dev;
165 get_device(dev); 153 get_device(dev);
166 dev->dma_mask = &musb_dmamask; 154 dev->dma_mask = &musb_dmamask;
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index a162b2c2ae15..679cbd49c019 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -139,14 +139,6 @@ static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
139 omap_pm_set_max_mpu_wakeup_lat(dev, t); 139 omap_pm_set_max_mpu_wakeup_lat(dev, t);
140} 140}
141 141
142static struct omap_device_pm_latency omap_i2c_latency[] = {
143 [0] = {
144 .deactivate_func = omap_device_idle_hwmods,
145 .activate_func = omap_device_enable_hwmods,
146 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
147 },
148};
149
150static inline int omap2_i2c_add_bus(int bus_id) 142static inline int omap2_i2c_add_bus(int bus_id)
151{ 143{
152 int l; 144 int l;
@@ -189,7 +181,7 @@ static inline int omap2_i2c_add_bus(int bus_id)
189 pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat; 181 pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
190 pdev = omap_device_build(name, bus_id, oh, pdata, 182 pdev = omap_device_build(name, bus_id, oh, pdata,
191 sizeof(struct omap_i2c_bus_platform_data), 183 sizeof(struct omap_i2c_bus_platform_data),
192 omap_i2c_latency, ARRAY_SIZE(omap_i2c_latency), 0); 184 NULL, 0, 0);
193 WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name); 185 WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name);
194 186
195 return PTR_ERR(pdev); 187 return PTR_ERR(pdev);
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index abda2c7e499b..c50df4814f6f 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -50,10 +50,13 @@ void omap2430_init_early(void);
50void omap3430_init_early(void); 50void omap3430_init_early(void);
51void omap35xx_init_early(void); 51void omap35xx_init_early(void);
52void omap3630_init_early(void); 52void omap3630_init_early(void);
53void omap3_init_early(void); /* Do not use this one */
53void am35xx_init_early(void); 54void am35xx_init_early(void);
54void ti816x_init_early(void); 55void ti816x_init_early(void);
55void omap4430_init_early(void); 56void omap4430_init_early(void);
56 57
58void omap_sram_init(void);
59
57/* 60/*
58 * IO bases for various OMAP processors 61 * IO bases for various OMAP processors
59 * Except the tap base, rest all the io bases 62 * Except the tap base, rest all the io bases
@@ -62,13 +65,13 @@ void omap4430_init_early(void);
62struct omap_globals { 65struct omap_globals {
63 u32 class; /* OMAP class to detect */ 66 u32 class; /* OMAP class to detect */
64 void __iomem *tap; /* Control module ID code */ 67 void __iomem *tap; /* Control module ID code */
65 unsigned long sdrc; /* SDRAM Controller */ 68 void __iomem *sdrc; /* SDRAM Controller */
66 unsigned long sms; /* SDRAM Memory Scheduler */ 69 void __iomem *sms; /* SDRAM Memory Scheduler */
67 unsigned long ctrl; /* System Control Module */ 70 void __iomem *ctrl; /* System Control Module */
68 unsigned long ctrl_pad; /* PAD Control Module */ 71 void __iomem *ctrl_pad; /* PAD Control Module */
69 unsigned long prm; /* Power and Reset Management */ 72 void __iomem *prm; /* Power and Reset Management */
70 unsigned long cm; /* Clock Management */ 73 void __iomem *cm; /* Clock Management */
71 unsigned long cm2; 74 void __iomem *cm2;
72}; 75};
73 76
74void omap2_set_globals_242x(void); 77void omap2_set_globals_242x(void);
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index a93a00db93da..7f2969eadb85 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -228,13 +228,13 @@
228 228
229#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE 229#define OMAP44XX_EMIF2_PHYS OMAP44XX_EMIF2_BASE
230 /* 0x4d000000 --> 0xfd200000 */ 230 /* 0x4d000000 --> 0xfd200000 */
231#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF2_PHYS + OMAP4_L3_PER_IO_OFFSET)
232#define OMAP44XX_EMIF2_SIZE SZ_1M 231#define OMAP44XX_EMIF2_SIZE SZ_1M
232#define OMAP44XX_EMIF2_VIRT (OMAP44XX_EMIF1_VIRT + OMAP44XX_EMIF1_SIZE)
233 233
234#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE 234#define OMAP44XX_DMM_PHYS OMAP44XX_DMM_BASE
235 /* 0x4e000000 --> 0xfd300000 */ 235 /* 0x4e000000 --> 0xfd300000 */
236#define OMAP44XX_DMM_VIRT (OMAP44XX_DMM_PHYS + OMAP4_L3_PER_IO_OFFSET)
237#define OMAP44XX_DMM_SIZE SZ_1M 236#define OMAP44XX_DMM_SIZE SZ_1M
237#define OMAP44XX_DMM_VIRT (OMAP44XX_EMIF2_VIRT + OMAP44XX_EMIF2_SIZE)
238/* 238/*
239 * ---------------------------------------------------------------------------- 239 * ----------------------------------------------------------------------------
240 * Omap specific register access 240 * Omap specific register access
@@ -247,6 +247,8 @@
247 * NOTE: Please use ioremap + __raw_read/write where possible instead of these 247 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
248 */ 248 */
249 249
250void omap_ioremap_init(void);
251
250extern u8 omap_readb(u32 pa); 252extern u8 omap_readb(u32 pa);
251extern u16 omap_readw(u32 pa); 253extern u16 omap_readw(u32 pa);
252extern u32 omap_readl(u32 pa); 254extern u32 omap_readl(u32 pa);
@@ -256,8 +258,31 @@ extern void omap_writel(u32 v, u32 pa);
256 258
257struct omap_sdrc_params; 259struct omap_sdrc_params;
258 260
259extern void omap1_map_common_io(void); 261#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
260extern void omap1_init_common_hw(void); 262void omap7xx_map_io(void);
263#else
264static inline void omap_map_io(void)
265{
266}
267#endif
268
269#ifdef CONFIG_ARCH_OMAP15XX
270void omap15xx_map_io(void);
271#else
272static inline void omap15xx_map_io(void)
273{
274}
275#endif
276
277#ifdef CONFIG_ARCH_OMAP16XX
278void omap16xx_map_io(void);
279#else
280static inline void omap16xx_map_io(void)
281{
282}
283#endif
284
285void omap1_init_early(void);
261 286
262#ifdef CONFIG_SOC_OMAP2420 287#ifdef CONFIG_SOC_OMAP2420
263extern void omap242x_map_common_io(void); 288extern void omap242x_map_common_io(void);
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index d4d9b96f961e..12c5b0c345bf 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -101,6 +101,7 @@ struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
101 int pm_lats_cnt, int is_early_device); 101 int pm_lats_cnt, int is_early_device);
102 102
103void __iomem *omap_device_get_rt_va(struct omap_device *od); 103void __iomem *omap_device_get_rt_va(struct omap_device *od);
104struct device *omap_device_get_by_hwmod_name(const char *oh_name);
104 105
105/* OMAP PM interface */ 106/* OMAP PM interface */
106int omap_device_align_pm_lat(struct platform_device *pdev, 107int omap_device_align_pm_lat(struct platform_device *pdev,
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index e9b0e23edd0a..333871f59995 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -24,11 +24,16 @@
24#define BETWEEN(p,st,sz) ((p) >= (st) && (p) < ((st) + (sz))) 24#define BETWEEN(p,st,sz) ((p) >= (st) && (p) < ((st) + (sz)))
25#define XLATE(p,pst,vst) ((void __iomem *)((p) - (pst) + (vst))) 25#define XLATE(p,pst,vst) ((void __iomem *)((p) - (pst) + (vst)))
26 26
27static int initialized;
28
27/* 29/*
28 * Intercept ioremap() requests for addresses in our fixed mapping regions. 30 * Intercept ioremap() requests for addresses in our fixed mapping regions.
29 */ 31 */
30void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type) 32void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
31{ 33{
34
35 WARN(!initialized, "Do not use ioremap before init_early\n");
36
32#ifdef CONFIG_ARCH_OMAP1 37#ifdef CONFIG_ARCH_OMAP1
33 if (cpu_class_is_omap1()) { 38 if (cpu_class_is_omap1()) {
34 if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE)) 39 if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE))
@@ -147,3 +152,8 @@ void __init omap_init_consistent_dma_size(void)
147 init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20); 152 init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20);
148#endif 153#endif
149} 154}
155
156void __init omap_ioremap_init(void)
157{
158 initialized++;
159}
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 26aee5cc1fc1..cd90bedd9306 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -85,6 +85,8 @@
85#include <linux/clk.h> 85#include <linux/clk.h>
86#include <linux/clkdev.h> 86#include <linux/clkdev.h>
87#include <linux/pm_runtime.h> 87#include <linux/pm_runtime.h>
88#include <linux/of.h>
89#include <linux/notifier.h>
88 90
89#include <plat/omap_device.h> 91#include <plat/omap_device.h>
90#include <plat/omap_hwmod.h> 92#include <plat/omap_hwmod.h>
@@ -96,6 +98,20 @@
96 98
97static int omap_device_register(struct platform_device *pdev); 99static int omap_device_register(struct platform_device *pdev);
98static int omap_early_device_register(struct platform_device *pdev); 100static int omap_early_device_register(struct platform_device *pdev);
101static struct omap_device *omap_device_alloc(struct platform_device *pdev,
102 struct omap_hwmod **ohs, int oh_cnt,
103 struct omap_device_pm_latency *pm_lats,
104 int pm_lats_cnt);
105static void omap_device_delete(struct omap_device *od);
106
107
108static struct omap_device_pm_latency omap_default_latency[] = {
109 {
110 .deactivate_func = omap_device_idle_hwmods,
111 .activate_func = omap_device_enable_hwmods,
112 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
113 }
114};
99 115
100/* Private functions */ 116/* Private functions */
101 117
@@ -303,6 +319,96 @@ static void _add_hwmod_clocks_clkdev(struct omap_device *od,
303} 319}
304 320
305 321
322static struct dev_pm_domain omap_device_pm_domain;
323
324/**
325 * omap_device_build_from_dt - build an omap_device with multiple hwmods
326 * @pdev_name: name of the platform_device driver to use
327 * @pdev_id: this platform_device's connection ID
328 * @oh: ptr to the single omap_hwmod that backs this omap_device
329 * @pdata: platform_data ptr to associate with the platform_device
330 * @pdata_len: amount of memory pointed to by @pdata
331 * @pm_lats: pointer to a omap_device_pm_latency array for this device
332 * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
333 * @is_early_device: should the device be registered as an early device or not
334 *
335 * Function for building an omap_device already registered from device-tree
336 *
337 * Returns 0 or PTR_ERR() on error.
338 */
339static int omap_device_build_from_dt(struct platform_device *pdev)
340{
341 struct omap_hwmod **hwmods;
342 struct omap_device *od;
343 struct omap_hwmod *oh;
344 struct device_node *node = pdev->dev.of_node;
345 const char *oh_name;
346 int oh_cnt, i, ret = 0;
347
348 oh_cnt = of_property_count_strings(node, "ti,hwmods");
349 if (!oh_cnt || IS_ERR_VALUE(oh_cnt)) {
350 dev_warn(&pdev->dev, "No 'hwmods' to build omap_device\n");
351 return -ENODEV;
352 }
353
354 hwmods = kzalloc(sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL);
355 if (!hwmods) {
356 ret = -ENOMEM;
357 goto odbfd_exit;
358 }
359
360 for (i = 0; i < oh_cnt; i++) {
361 of_property_read_string_index(node, "ti,hwmods", i, &oh_name);
362 oh = omap_hwmod_lookup(oh_name);
363 if (!oh) {
364 dev_err(&pdev->dev, "Cannot lookup hwmod '%s'\n",
365 oh_name);
366 ret = -EINVAL;
367 goto odbfd_exit1;
368 }
369 hwmods[i] = oh;
370 }
371
372 od = omap_device_alloc(pdev, hwmods, oh_cnt, NULL, 0);
373 if (!od) {
374 dev_err(&pdev->dev, "Cannot allocate omap_device for :%s\n",
375 oh_name);
376 ret = PTR_ERR(od);
377 goto odbfd_exit1;
378 }
379
380 if (of_get_property(node, "ti,no_idle_on_suspend", NULL))
381 omap_device_disable_idle_on_suspend(pdev);
382
383 pdev->dev.pm_domain = &omap_device_pm_domain;
384
385odbfd_exit1:
386 kfree(hwmods);
387odbfd_exit:
388 return ret;
389}
390
391static int _omap_device_notifier_call(struct notifier_block *nb,
392 unsigned long event, void *dev)
393{
394 struct platform_device *pdev = to_platform_device(dev);
395
396 switch (event) {
397 case BUS_NOTIFY_ADD_DEVICE:
398 if (pdev->dev.of_node)
399 omap_device_build_from_dt(pdev);
400 break;
401
402 case BUS_NOTIFY_DEL_DEVICE:
403 if (pdev->archdata.od)
404 omap_device_delete(pdev->archdata.od);
405 break;
406 }
407
408 return NOTIFY_DONE;
409}
410
411
306/* Public functions for use by core code */ 412/* Public functions for use by core code */
307 413
308/** 414/**
@@ -389,6 +495,113 @@ static int omap_device_fill_resources(struct omap_device *od,
389} 495}
390 496
391/** 497/**
498 * omap_device_alloc - allocate an omap_device
499 * @pdev: platform_device that will be included in this omap_device
500 * @oh: ptr to the single omap_hwmod that backs this omap_device
501 * @pdata: platform_data ptr to associate with the platform_device
502 * @pdata_len: amount of memory pointed to by @pdata
503 * @pm_lats: pointer to a omap_device_pm_latency array for this device
504 * @pm_lats_cnt: ARRAY_SIZE() of @pm_lats
505 *
506 * Convenience function for allocating an omap_device structure and filling
507 * hwmods, resources and pm_latency attributes.
508 *
509 * Returns an struct omap_device pointer or ERR_PTR() on error;
510 */
511static struct omap_device *omap_device_alloc(struct platform_device *pdev,
512 struct omap_hwmod **ohs, int oh_cnt,
513 struct omap_device_pm_latency *pm_lats,
514 int pm_lats_cnt)
515{
516 int ret = -ENOMEM;
517 struct omap_device *od;
518 struct resource *res = NULL;
519 int i, res_count;
520 struct omap_hwmod **hwmods;
521
522 od = kzalloc(sizeof(struct omap_device), GFP_KERNEL);
523 if (!od) {
524 ret = -ENOMEM;
525 goto oda_exit1;
526 }
527 od->hwmods_cnt = oh_cnt;
528
529 hwmods = kmemdup(ohs, sizeof(struct omap_hwmod *) * oh_cnt, GFP_KERNEL);
530 if (!hwmods)
531 goto oda_exit2;
532
533 od->hwmods = hwmods;
534 od->pdev = pdev;
535
536 /*
537 * HACK: Ideally the resources from DT should match, and hwmod
538 * should just add the missing ones. Since the name is not
539 * properly populated by DT, stick to hwmod resources only.
540 */
541 if (pdev->num_resources && pdev->resource)
542 dev_warn(&pdev->dev, "%s(): resources already allocated %d\n",
543 __func__, pdev->num_resources);
544
545 res_count = omap_device_count_resources(od);
546 if (res_count > 0) {
547 dev_dbg(&pdev->dev, "%s(): resources allocated from hwmod %d\n",
548 __func__, res_count);
549 res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
550 if (!res)
551 goto oda_exit3;
552
553 omap_device_fill_resources(od, res);
554
555 ret = platform_device_add_resources(pdev, res, res_count);
556 kfree(res);
557
558 if (ret)
559 goto oda_exit3;
560 }
561
562 if (!pm_lats) {
563 pm_lats = omap_default_latency;
564 pm_lats_cnt = ARRAY_SIZE(omap_default_latency);
565 }
566
567 od->pm_lats_cnt = pm_lats_cnt;
568 od->pm_lats = kmemdup(pm_lats,
569 sizeof(struct omap_device_pm_latency) * pm_lats_cnt,
570 GFP_KERNEL);
571 if (!od->pm_lats)
572 goto oda_exit3;
573
574 pdev->archdata.od = od;
575
576 for (i = 0; i < oh_cnt; i++) {
577 hwmods[i]->od = od;
578 _add_hwmod_clocks_clkdev(od, hwmods[i]);
579 }
580
581 return od;
582
583oda_exit3:
584 kfree(hwmods);
585oda_exit2:
586 kfree(od);
587oda_exit1:
588 dev_err(&pdev->dev, "omap_device: build failed (%d)\n", ret);
589
590 return ERR_PTR(ret);
591}
592
593static void omap_device_delete(struct omap_device *od)
594{
595 if (!od)
596 return;
597
598 od->pdev->archdata.od = NULL;
599 kfree(od->pm_lats);
600 kfree(od->hwmods);
601 kfree(od);
602}
603
604/**
392 * omap_device_build - build and register an omap_device with one omap_hwmod 605 * omap_device_build - build and register an omap_device with one omap_hwmod
393 * @pdev_name: name of the platform_device driver to use 606 * @pdev_name: name of the platform_device driver to use
394 * @pdev_id: this platform_device's connection ID 607 * @pdev_id: this platform_device's connection ID
@@ -447,9 +660,6 @@ struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
447 int ret = -ENOMEM; 660 int ret = -ENOMEM;
448 struct platform_device *pdev; 661 struct platform_device *pdev;
449 struct omap_device *od; 662 struct omap_device *od;
450 struct resource *res = NULL;
451 int i, res_count;
452 struct omap_hwmod **hwmods;
453 663
454 if (!ohs || oh_cnt == 0 || !pdev_name) 664 if (!ohs || oh_cnt == 0 || !pdev_name)
455 return ERR_PTR(-EINVAL); 665 return ERR_PTR(-EINVAL);
@@ -463,67 +673,31 @@ struct platform_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
463 goto odbs_exit; 673 goto odbs_exit;
464 } 674 }
465 675
466 pr_debug("omap_device: %s: building with %d hwmods\n", pdev_name, 676 /* Set the dev_name early to allow dev_xxx in omap_device_alloc */
467 oh_cnt); 677 if (pdev->id != -1)
678 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
679 else
680 dev_set_name(&pdev->dev, "%s", pdev->name);
468 681
469 od = kzalloc(sizeof(struct omap_device), GFP_KERNEL); 682 od = omap_device_alloc(pdev, ohs, oh_cnt, pm_lats, pm_lats_cnt);
470 if (!od) { 683 if (!od)
471 ret = -ENOMEM;
472 goto odbs_exit1; 684 goto odbs_exit1;
473 }
474 od->hwmods_cnt = oh_cnt;
475
476 hwmods = kzalloc(sizeof(struct omap_hwmod *) * oh_cnt,
477 GFP_KERNEL);
478 if (!hwmods)
479 goto odbs_exit2;
480
481 memcpy(hwmods, ohs, sizeof(struct omap_hwmod *) * oh_cnt);
482 od->hwmods = hwmods;
483 od->pdev = pdev;
484
485 res_count = omap_device_count_resources(od);
486 if (res_count > 0) {
487 res = kzalloc(sizeof(struct resource) * res_count, GFP_KERNEL);
488 if (!res)
489 goto odbs_exit3;
490
491 omap_device_fill_resources(od, res);
492
493 ret = platform_device_add_resources(pdev, res, res_count);
494 kfree(res);
495
496 if (ret)
497 goto odbs_exit3;
498 }
499 685
500 ret = platform_device_add_data(pdev, pdata, pdata_len); 686 ret = platform_device_add_data(pdev, pdata, pdata_len);
501 if (ret) 687 if (ret)
502 goto odbs_exit3; 688 goto odbs_exit2;
503
504 pdev->archdata.od = od;
505 689
506 if (is_early_device) 690 if (is_early_device)
507 ret = omap_early_device_register(pdev); 691 ret = omap_early_device_register(pdev);
508 else 692 else
509 ret = omap_device_register(pdev); 693 ret = omap_device_register(pdev);
510 if (ret) 694 if (ret)
511 goto odbs_exit3; 695 goto odbs_exit2;
512
513 od->pm_lats = pm_lats;
514 od->pm_lats_cnt = pm_lats_cnt;
515
516 for (i = 0; i < oh_cnt; i++) {
517 hwmods[i]->od = od;
518 _add_hwmod_clocks_clkdev(od, hwmods[i]);
519 }
520 696
521 return pdev; 697 return pdev;
522 698
523odbs_exit3:
524 kfree(hwmods);
525odbs_exit2: 699odbs_exit2:
526 kfree(od); 700 omap_device_delete(od);
527odbs_exit1: 701odbs_exit1:
528 platform_device_put(pdev); 702 platform_device_put(pdev);
529odbs_exit: 703odbs_exit:
@@ -844,6 +1018,42 @@ void __iomem *omap_device_get_rt_va(struct omap_device *od)
844 return omap_hwmod_get_mpu_rt_va(od->hwmods[0]); 1018 return omap_hwmod_get_mpu_rt_va(od->hwmods[0]);
845} 1019}
846 1020
1021/**
1022 * omap_device_get_by_hwmod_name() - convert a hwmod name to
1023 * device pointer.
1024 * @oh_name: name of the hwmod device
1025 *
1026 * Returns back a struct device * pointer associated with a hwmod
1027 * device represented by a hwmod_name
1028 */
1029struct device *omap_device_get_by_hwmod_name(const char *oh_name)
1030{
1031 struct omap_hwmod *oh;
1032
1033 if (!oh_name) {
1034 WARN(1, "%s: no hwmod name!\n", __func__);
1035 return ERR_PTR(-EINVAL);
1036 }
1037
1038 oh = omap_hwmod_lookup(oh_name);
1039 if (IS_ERR_OR_NULL(oh)) {
1040 WARN(1, "%s: no hwmod for %s\n", __func__,
1041 oh_name);
1042 return ERR_PTR(oh ? PTR_ERR(oh) : -ENODEV);
1043 }
1044 if (IS_ERR_OR_NULL(oh->od)) {
1045 WARN(1, "%s: no omap_device for %s\n", __func__,
1046 oh_name);
1047 return ERR_PTR(oh->od ? PTR_ERR(oh->od) : -ENODEV);
1048 }
1049
1050 if (IS_ERR_OR_NULL(oh->od->pdev))
1051 return ERR_PTR(oh->od->pdev ? PTR_ERR(oh->od->pdev) : -ENODEV);
1052
1053 return &oh->od->pdev->dev;
1054}
1055EXPORT_SYMBOL(omap_device_get_by_hwmod_name);
1056
847/* 1057/*
848 * Public functions intended for use in omap_device_pm_latency 1058 * Public functions intended for use in omap_device_pm_latency
849 * .activate_func and .deactivate_func function pointers 1059 * .activate_func and .deactivate_func function pointers
@@ -924,8 +1134,13 @@ struct device omap_device_parent = {
924 .parent = &platform_bus, 1134 .parent = &platform_bus,
925}; 1135};
926 1136
1137static struct notifier_block platform_nb = {
1138 .notifier_call = _omap_device_notifier_call,
1139};
1140
927static int __init omap_device_init(void) 1141static int __init omap_device_init(void)
928{ 1142{
1143 bus_register_notifier(&platform_bus_type, &platform_nb);
929 return device_register(&omap_device_parent); 1144 return device_register(&omap_device_parent);
930} 1145}
931core_initcall(omap_device_init); 1146core_initcall(omap_device_init);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 363c91e44efb..8b28664d1c62 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -19,7 +19,6 @@
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/omapfb.h>
23 22
24#include <asm/tlb.h> 23#include <asm/tlb.h>
25#include <asm/cacheflush.h> 24#include <asm/cacheflush.h>
@@ -29,10 +28,8 @@
29#include <plat/sram.h> 28#include <plat/sram.h>
30#include <plat/board.h> 29#include <plat/board.h>
31#include <plat/cpu.h> 30#include <plat/cpu.h>
32#include <plat/vram.h>
33 31
34#include "sram.h" 32#include "sram.h"
35#include "fb.h"
36 33
37/* XXX These "sideways" includes are a sign that something is wrong */ 34/* XXX These "sideways" includes are a sign that something is wrong */
38#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 35#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
@@ -41,16 +38,9 @@
41#endif 38#endif
42 39
43#define OMAP1_SRAM_PA 0x20000000 40#define OMAP1_SRAM_PA 0x20000000
44#define OMAP1_SRAM_VA VMALLOC_END
45#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800) 41#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
46#define OMAP2_SRAM_VA 0xfe400000
47#define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800)
48#define OMAP3_SRAM_VA 0xfe400000
49#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000) 42#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
50#define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000)
51#define OMAP4_SRAM_VA 0xfe400000
52#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000) 43#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
53#define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000)
54 44
55#if defined(CONFIG_ARCH_OMAP2PLUS) 45#if defined(CONFIG_ARCH_OMAP2PLUS)
56#define SRAM_BOOTLOADER_SZ 0x00 46#define SRAM_BOOTLOADER_SZ 0x00
@@ -73,9 +63,9 @@
73#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) 63#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
74 64
75static unsigned long omap_sram_start; 65static unsigned long omap_sram_start;
76static unsigned long omap_sram_base; 66static void __iomem *omap_sram_base;
77static unsigned long omap_sram_size; 67static unsigned long omap_sram_size;
78static unsigned long omap_sram_ceil; 68static void __iomem *omap_sram_ceil;
79 69
80/* 70/*
81 * Depending on the target RAMFS firewall setup, the public usable amount of 71 * Depending on the target RAMFS firewall setup, the public usable amount of
@@ -112,12 +102,9 @@ static int is_sram_locked(void)
112 */ 102 */
113static void __init omap_detect_sram(void) 103static void __init omap_detect_sram(void)
114{ 104{
115 unsigned long reserved;
116
117 if (cpu_class_is_omap2()) { 105 if (cpu_class_is_omap2()) {
118 if (is_sram_locked()) { 106 if (is_sram_locked()) {
119 if (cpu_is_omap34xx()) { 107 if (cpu_is_omap34xx()) {
120 omap_sram_base = OMAP3_SRAM_PUB_VA;
121 omap_sram_start = OMAP3_SRAM_PUB_PA; 108 omap_sram_start = OMAP3_SRAM_PUB_PA;
122 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) || 109 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
123 (omap_type() == OMAP2_DEVICE_TYPE_SEC)) { 110 (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
@@ -126,25 +113,20 @@ static void __init omap_detect_sram(void)
126 omap_sram_size = 0x8000; /* 32K */ 113 omap_sram_size = 0x8000; /* 32K */
127 } 114 }
128 } else if (cpu_is_omap44xx()) { 115 } else if (cpu_is_omap44xx()) {
129 omap_sram_base = OMAP4_SRAM_PUB_VA;
130 omap_sram_start = OMAP4_SRAM_PUB_PA; 116 omap_sram_start = OMAP4_SRAM_PUB_PA;
131 omap_sram_size = 0xa000; /* 40K */ 117 omap_sram_size = 0xa000; /* 40K */
132 } else { 118 } else {
133 omap_sram_base = OMAP2_SRAM_PUB_VA;
134 omap_sram_start = OMAP2_SRAM_PUB_PA; 119 omap_sram_start = OMAP2_SRAM_PUB_PA;
135 omap_sram_size = 0x800; /* 2K */ 120 omap_sram_size = 0x800; /* 2K */
136 } 121 }
137 } else { 122 } else {
138 if (cpu_is_omap34xx()) { 123 if (cpu_is_omap34xx()) {
139 omap_sram_base = OMAP3_SRAM_VA;
140 omap_sram_start = OMAP3_SRAM_PA; 124 omap_sram_start = OMAP3_SRAM_PA;
141 omap_sram_size = 0x10000; /* 64K */ 125 omap_sram_size = 0x10000; /* 64K */
142 } else if (cpu_is_omap44xx()) { 126 } else if (cpu_is_omap44xx()) {
143 omap_sram_base = OMAP4_SRAM_VA;
144 omap_sram_start = OMAP4_SRAM_PA; 127 omap_sram_start = OMAP4_SRAM_PA;
145 omap_sram_size = 0xe000; /* 56K */ 128 omap_sram_size = 0xe000; /* 56K */
146 } else { 129 } else {
147 omap_sram_base = OMAP2_SRAM_VA;
148 omap_sram_start = OMAP2_SRAM_PA; 130 omap_sram_start = OMAP2_SRAM_PA;
149 if (cpu_is_omap242x()) 131 if (cpu_is_omap242x())
150 omap_sram_size = 0xa0000; /* 640K */ 132 omap_sram_size = 0xa0000; /* 640K */
@@ -153,7 +135,6 @@ static void __init omap_detect_sram(void)
153 } 135 }
154 } 136 }
155 } else { 137 } else {
156 omap_sram_base = OMAP1_SRAM_VA;
157 omap_sram_start = OMAP1_SRAM_PA; 138 omap_sram_start = OMAP1_SRAM_PA;
158 139
159 if (cpu_is_omap7xx()) 140 if (cpu_is_omap7xx())
@@ -170,35 +151,14 @@ static void __init omap_detect_sram(void)
170 omap_sram_size = 0x4000; 151 omap_sram_size = 0x4000;
171 } 152 }
172 } 153 }
173 reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
174 omap_sram_size,
175 omap_sram_start + SRAM_BOOTLOADER_SZ,
176 omap_sram_size - SRAM_BOOTLOADER_SZ);
177 omap_sram_size -= reserved;
178
179 reserved = omap_vram_reserve_sram(omap_sram_start, omap_sram_base,
180 omap_sram_size,
181 omap_sram_start + SRAM_BOOTLOADER_SZ,
182 omap_sram_size - SRAM_BOOTLOADER_SZ);
183 omap_sram_size -= reserved;
184
185 omap_sram_ceil = omap_sram_base + omap_sram_size;
186} 154}
187 155
188static struct map_desc omap_sram_io_desc[] __initdata = {
189 { /* .length gets filled in at runtime */
190 .virtual = OMAP1_SRAM_VA,
191 .pfn = __phys_to_pfn(OMAP1_SRAM_PA),
192 .type = MT_MEMORY
193 }
194};
195
196/* 156/*
197 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early. 157 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
198 */ 158 */
199static void __init omap_map_sram(void) 159static void __init omap_map_sram(void)
200{ 160{
201 unsigned long base; 161 int cached = 1;
202 162
203 if (omap_sram_size == 0) 163 if (omap_sram_size == 0)
204 return; 164 return;
@@ -211,28 +171,18 @@ static void __init omap_map_sram(void)
211 * the ARM may attempt to write cache lines back to SDRAM 171 * the ARM may attempt to write cache lines back to SDRAM
212 * which will cause the system to hang. 172 * which will cause the system to hang.
213 */ 173 */
214 omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED; 174 cached = 0;
215 } 175 }
216 176
217 omap_sram_io_desc[0].virtual = omap_sram_base; 177 omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
218 base = omap_sram_start; 178 omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
219 base = ROUND_DOWN(base, PAGE_SIZE); 179 cached);
220 omap_sram_io_desc[0].pfn = __phys_to_pfn(base); 180 if (!omap_sram_base) {
221 omap_sram_io_desc[0].length = ROUND_DOWN(omap_sram_size, PAGE_SIZE); 181 pr_err("SRAM: Could not map\n");
222 iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); 182 return;
223 183 }
224 pr_info("SRAM: Mapped pa 0x%08llx to va 0x%08lx size: 0x%lx\n",
225 (long long) __pfn_to_phys(omap_sram_io_desc[0].pfn),
226 omap_sram_io_desc[0].virtual,
227 omap_sram_io_desc[0].length);
228 184
229 /* 185 omap_sram_ceil = omap_sram_base + omap_sram_size;
230 * Normally devicemaps_init() would flush caches and tlb after
231 * mdesc->map_io(), but since we're called from map_io(), we
232 * must do it here.
233 */
234 local_flush_tlb_all();
235 flush_cache_all();
236 186
237 /* 187 /*
238 * Looks like we need to preserve some bootloader code at the 188 * Looks like we need to preserve some bootloader code at the
@@ -251,13 +201,18 @@ static void __init omap_map_sram(void)
251 */ 201 */
252void *omap_sram_push_address(unsigned long size) 202void *omap_sram_push_address(unsigned long size)
253{ 203{
254 if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) { 204 unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
205
206 available = omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ);
207
208 if (size > available) {
255 pr_err("Not enough space in SRAM\n"); 209 pr_err("Not enough space in SRAM\n");
256 return NULL; 210 return NULL;
257 } 211 }
258 212
259 omap_sram_ceil -= size; 213 new_ceil -= size;
260 omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, FNCPY_ALIGN); 214 new_ceil = ROUND_DOWN(new_ceil, FNCPY_ALIGN);
215 omap_sram_ceil = IOMEM(new_ceil);
261 216
262 return (void *)omap_sram_ceil; 217 return (void *)omap_sram_ceil;
263} 218}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-18 23:29:01 -0500