diff options
author | Paul Walmsley <paul@pwsan.com> | 2012-10-29 22:55:53 -0400 |
---|---|---|
committer | Paul Walmsley <paul@pwsan.com> | 2012-11-08 14:33:08 -0500 |
commit | 5f03937700e3991a0de801ade8374628f2c982d5 (patch) | |
tree | 06679db2cd46c3063a058ce9540e78294538d53b /arch/arm | |
parent | d08cce6a1d6952a7774e4b61066d469c16d47a11 (diff) |
ARM: OMAP2xxx: clock: remove global 'dclk' variable
Remove the global 'dclk' variable, instead replacing it with a
variable local to the dpllcore clock type C file. This removes some
of the special-case code surrounding the OMAP2xxx clock init.
This patch is a prerequisite for the removal of the
omap_prcm_restart() code from arch/arm/mach-omap2/prcm.c. It also
cleans up some special-case OMAP2xxx clock code in the process.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Tested-by: Vaibhav Hiremath <hvaibhav@ti.com>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 34 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock2420_data.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock2430_data.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock2xxx.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock2xxx.h | 5 |
6 files changed, 37 insertions, 14 deletions
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index 3432f913f743..08a896ba3f5d 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c | |||
@@ -36,9 +36,15 @@ | |||
36 | 36 | ||
37 | /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ | 37 | /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ |
38 | 38 | ||
39 | /* | ||
40 | * dpll_core_ck: pointer to the combined dpll_ck + core_ck on OMAP2xxx | ||
41 | * (currently defined as "dpll_ck" in the OMAP2xxx clock tree). Set | ||
42 | * during dpll_ck init and used later by omap2xxx_clk_get_core_rate(). | ||
43 | */ | ||
44 | static struct clk *dpll_core_ck; | ||
45 | |||
39 | /** | 46 | /** |
40 | * omap2xxx_clk_get_core_rate - return the CORE_CLK rate | 47 | * omap2xxx_clk_get_core_rate - return the CORE_CLK rate |
41 | * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck") | ||
42 | * | 48 | * |
43 | * Returns the CORE_CLK rate. CORE_CLK can have one of three rate | 49 | * Returns the CORE_CLK rate. CORE_CLK can have one of three rate |
44 | * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz | 50 | * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz |
@@ -46,12 +52,14 @@ | |||
46 | * struct clk *dpll_ck, which is a composite clock of dpll_ck and | 52 | * struct clk *dpll_ck, which is a composite clock of dpll_ck and |
47 | * core_ck. | 53 | * core_ck. |
48 | */ | 54 | */ |
49 | unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) | 55 | unsigned long omap2xxx_clk_get_core_rate(void) |
50 | { | 56 | { |
51 | long long core_clk; | 57 | long long core_clk; |
52 | u32 v; | 58 | u32 v; |
53 | 59 | ||
54 | core_clk = omap2_get_dpll_rate(clk); | 60 | WARN_ON(!dpll_core_ck); |
61 | |||
62 | core_clk = omap2_get_dpll_rate(dpll_core_ck); | ||
55 | 63 | ||
56 | v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | 64 | v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
57 | v &= OMAP24XX_CORE_CLK_SRC_MASK; | 65 | v &= OMAP24XX_CORE_CLK_SRC_MASK; |
@@ -99,7 +107,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) | |||
99 | 107 | ||
100 | unsigned long omap2_dpllcore_recalc(struct clk *clk) | 108 | unsigned long omap2_dpllcore_recalc(struct clk *clk) |
101 | { | 109 | { |
102 | return omap2xxx_clk_get_core_rate(clk); | 110 | return omap2xxx_clk_get_core_rate(); |
103 | } | 111 | } |
104 | 112 | ||
105 | int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | 113 | int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) |
@@ -109,7 +117,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | |||
109 | struct prcm_config tmpset; | 117 | struct prcm_config tmpset; |
110 | const struct dpll_data *dd; | 118 | const struct dpll_data *dd; |
111 | 119 | ||
112 | cur_rate = omap2xxx_clk_get_core_rate(dclk); | 120 | cur_rate = omap2xxx_clk_get_core_rate(); |
113 | mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | 121 | mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
114 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; | 122 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; |
115 | 123 | ||
@@ -170,3 +178,19 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | |||
170 | return 0; | 178 | return 0; |
171 | } | 179 | } |
172 | 180 | ||
181 | /** | ||
182 | * omap2xxx_clkt_dpllcore_init - clk init function for dpll_ck | ||
183 | * @clk: struct clk *dpll_ck | ||
184 | * | ||
185 | * Store a local copy of @clk in dpll_core_ck so other code can query | ||
186 | * the core rate without having to clk_get(), which can sleep. Must | ||
187 | * only be called once. No return value. XXX If the clock | ||
188 | * registration process is ever changed such that dpll_ck is no longer | ||
189 | * statically defined, this code may need to change to increment some | ||
190 | * kind of use count on dpll_ck. | ||
191 | */ | ||
192 | void omap2xxx_clkt_dpllcore_init(struct clk *clk) | ||
193 | { | ||
194 | WARN(dpll_core_ck, "dpll_core_ck already set - should never happen"); | ||
195 | dpll_core_ck = clk; | ||
196 | } | ||
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index c66276b2bf0a..311599405bfa 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | |||
@@ -118,7 +118,7 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate) | |||
118 | } | 118 | } |
119 | 119 | ||
120 | curr_prcm_set = prcm; | 120 | curr_prcm_set = prcm; |
121 | cur_rate = omap2xxx_clk_get_core_rate(dclk); | 121 | cur_rate = omap2xxx_clk_get_core_rate(); |
122 | 122 | ||
123 | if (prcm->dpll_speed == cur_rate / 2) { | 123 | if (prcm->dpll_speed == cur_rate / 2) { |
124 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); | 124 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); |
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index da1e388f22f7..d1034858b87a 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c | |||
@@ -124,6 +124,7 @@ static struct clk dpll_ck = { | |||
124 | .name = "dpll_ck", | 124 | .name = "dpll_ck", |
125 | .ops = &clkops_omap2xxx_dpll_ops, | 125 | .ops = &clkops_omap2xxx_dpll_ops, |
126 | .parent = &sys_ck, /* Can be func_32k also */ | 126 | .parent = &sys_ck, /* Can be func_32k also */ |
127 | .init = &omap2xxx_clkt_dpllcore_init, | ||
127 | .dpll_data = &dpll_dd, | 128 | .dpll_data = &dpll_dd, |
128 | .clkdm_name = "wkup_clkdm", | 129 | .clkdm_name = "wkup_clkdm", |
129 | .recalc = &omap2_dpllcore_recalc, | 130 | .recalc = &omap2_dpllcore_recalc, |
@@ -1953,7 +1954,7 @@ int __init omap2420_clk_init(void) | |||
1953 | omap_clk_disable_autoidle_all(); | 1954 | omap_clk_disable_autoidle_all(); |
1954 | 1955 | ||
1955 | /* Check the MPU rate set by bootloader */ | 1956 | /* Check the MPU rate set by bootloader */ |
1956 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); | 1957 | clkrate = omap2xxx_clk_get_core_rate(); |
1957 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | 1958 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { |
1958 | if (!(prcm->flags & cpu_mask)) | 1959 | if (!(prcm->flags & cpu_mask)) |
1959 | continue; | 1960 | continue; |
@@ -1979,7 +1980,6 @@ int __init omap2420_clk_init(void) | |||
1979 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ | 1980 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ |
1980 | vclk = clk_get(NULL, "virt_prcm_set"); | 1981 | vclk = clk_get(NULL, "virt_prcm_set"); |
1981 | sclk = clk_get(NULL, "sys_ck"); | 1982 | sclk = clk_get(NULL, "sys_ck"); |
1982 | dclk = clk_get(NULL, "dpll_ck"); | ||
1983 | 1983 | ||
1984 | return 0; | 1984 | return 0; |
1985 | } | 1985 | } |
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index c97dafef894d..3e16eab4691d 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c | |||
@@ -123,6 +123,7 @@ static struct clk dpll_ck = { | |||
123 | .name = "dpll_ck", | 123 | .name = "dpll_ck", |
124 | .ops = &clkops_omap2xxx_dpll_ops, | 124 | .ops = &clkops_omap2xxx_dpll_ops, |
125 | .parent = &sys_ck, /* Can be func_32k also */ | 125 | .parent = &sys_ck, /* Can be func_32k also */ |
126 | .init = &omap2xxx_clkt_dpllcore_init, | ||
126 | .dpll_data = &dpll_dd, | 127 | .dpll_data = &dpll_dd, |
127 | .clkdm_name = "wkup_clkdm", | 128 | .clkdm_name = "wkup_clkdm", |
128 | .recalc = &omap2_dpllcore_recalc, | 129 | .recalc = &omap2_dpllcore_recalc, |
@@ -2052,7 +2053,7 @@ int __init omap2430_clk_init(void) | |||
2052 | omap_clk_disable_autoidle_all(); | 2053 | omap_clk_disable_autoidle_all(); |
2053 | 2054 | ||
2054 | /* Check the MPU rate set by bootloader */ | 2055 | /* Check the MPU rate set by bootloader */ |
2055 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); | 2056 | clkrate = omap2xxx_clk_get_core_rate(); |
2056 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | 2057 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { |
2057 | if (!(prcm->flags & cpu_mask)) | 2058 | if (!(prcm->flags & cpu_mask)) |
2058 | continue; | 2059 | continue; |
@@ -2078,7 +2079,6 @@ int __init omap2430_clk_init(void) | |||
2078 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ | 2079 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ |
2079 | vclk = clk_get(NULL, "virt_prcm_set"); | 2080 | vclk = clk_get(NULL, "virt_prcm_set"); |
2080 | sclk = clk_get(NULL, "sys_ck"); | 2081 | sclk = clk_get(NULL, "sys_ck"); |
2081 | dclk = clk_get(NULL, "dpll_ck"); | ||
2082 | 2082 | ||
2083 | return 0; | 2083 | return 0; |
2084 | } | 2084 | } |
diff --git a/arch/arm/mach-omap2/clock2xxx.c b/arch/arm/mach-omap2/clock2xxx.c index 5feee16fee0e..8e0294e732f1 100644 --- a/arch/arm/mach-omap2/clock2xxx.c +++ b/arch/arm/mach-omap2/clock2xxx.c | |||
@@ -28,7 +28,7 @@ | |||
28 | #include "cm.h" | 28 | #include "cm.h" |
29 | #include "cm-regbits-24xx.h" | 29 | #include "cm-regbits-24xx.h" |
30 | 30 | ||
31 | struct clk *vclk, *sclk, *dclk; | 31 | struct clk *vclk, *sclk; |
32 | 32 | ||
33 | /* | 33 | /* |
34 | * Omap24xx specific clock functions | 34 | * Omap24xx specific clock functions |
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h index cb6df8ca9e4a..19dc065901c7 100644 --- a/arch/arm/mach-omap2/clock2xxx.h +++ b/arch/arm/mach-omap2/clock2xxx.h | |||
@@ -15,10 +15,11 @@ unsigned long omap2xxx_sys_clk_recalc(struct clk *clk); | |||
15 | unsigned long omap2_osc_clk_recalc(struct clk *clk); | 15 | unsigned long omap2_osc_clk_recalc(struct clk *clk); |
16 | unsigned long omap2_dpllcore_recalc(struct clk *clk); | 16 | unsigned long omap2_dpllcore_recalc(struct clk *clk); |
17 | int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); | 17 | int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); |
18 | unsigned long omap2xxx_clk_get_core_rate(struct clk *clk); | 18 | unsigned long omap2xxx_clk_get_core_rate(void); |
19 | u32 omap2xxx_get_apll_clkin(void); | 19 | u32 omap2xxx_get_apll_clkin(void); |
20 | u32 omap2xxx_get_sysclkdiv(void); | 20 | u32 omap2xxx_get_sysclkdiv(void); |
21 | void omap2xxx_clk_prepare_for_reboot(void); | 21 | void omap2xxx_clk_prepare_for_reboot(void); |
22 | void omap2xxx_clkt_dpllcore_init(struct clk *clk); | ||
22 | 23 | ||
23 | #ifdef CONFIG_SOC_OMAP2420 | 24 | #ifdef CONFIG_SOC_OMAP2420 |
24 | int omap2420_clk_init(void); | 25 | int omap2420_clk_init(void); |
@@ -34,8 +35,6 @@ int omap2430_clk_init(void); | |||
34 | 35 | ||
35 | extern void __iomem *prcm_clksrc_ctrl, *cm_idlest_pll; | 36 | extern void __iomem *prcm_clksrc_ctrl, *cm_idlest_pll; |
36 | 37 | ||
37 | extern struct clk *dclk; | ||
38 | |||
39 | extern const struct clkops clkops_omap2430_i2chs_wait; | 38 | extern const struct clkops clkops_omap2430_i2chs_wait; |
40 | extern const struct clkops clkops_oscck; | 39 | extern const struct clkops clkops_oscck; |
41 | extern const struct clkops clkops_apll96; | 40 | extern const struct clkops clkops_apll96; |