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authorJaecheol Lee <jc.lee@samsung.com>2010-10-11 20:19:34 -0400
committerKukjin Kim <kgene.kim@samsung.com>2010-10-25 03:04:04 -0400
commit3c5992160d42854bad4da215dda17a158dc94852 (patch)
treead9a01a9b21f99ec508886d277bbbd0657a8df9e /arch/arm
parent08f49d118e855f4d660ff29ecd2a4e736f26f9db (diff)
ARM: S5PV210: Add Register definition for CMU
This patch adds some CMU(Clock Management Unit) registers for supporting CPUFREQ and some drivers. Signed-off-by: Jaecheol Lee <jc.lee@samsung.com> Signed-off-by: Sangbeom Kim <sbkim73@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-s5pv210/include/mach/regs-clock.h31
1 files changed, 30 insertions, 1 deletions
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
index 929fd3a33f8a..61b55c8e438c 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
@@ -67,11 +67,28 @@
67#define S5P_CLKGATE_BUS1 S5P_CLKREG(0x488) 67#define S5P_CLKGATE_BUS1 S5P_CLKREG(0x488)
68#define S5P_CLK_OUT S5P_CLKREG(0x500) 68#define S5P_CLK_OUT S5P_CLKREG(0x500)
69 69
70/* DIV/MUX STATUS */
71#define S5P_CLKDIV_STAT0 S5P_CLKREG(0x1000)
72#define S5P_CLKDIV_STAT1 S5P_CLKREG(0x1004)
73#define S5P_CLKMUX_STAT0 S5P_CLKREG(0x1100)
74#define S5P_CLKMUX_STAT1 S5P_CLKREG(0x1104)
75
70/* CLKSRC0 */ 76/* CLKSRC0 */
71#define S5P_CLKSRC0_MUX200_MASK (0x1<<16) 77#define S5P_CLKSRC0_MUX200_SHIFT (16)
78#define S5P_CLKSRC0_MUX200_MASK (0x1 << S5P_CLKSRC0_MUX200_SHIFT)
72#define S5P_CLKSRC0_MUX166_MASK (0x1<<20) 79#define S5P_CLKSRC0_MUX166_MASK (0x1<<20)
73#define S5P_CLKSRC0_MUX133_MASK (0x1<<24) 80#define S5P_CLKSRC0_MUX133_MASK (0x1<<24)
74 81
82/* CLKSRC2 */
83#define S5P_CLKSRC2_G3D_SHIFT (0)
84#define S5P_CLKSRC2_G3D_MASK (0x3 << S5P_CLKSRC2_G3D_SHIFT)
85#define S5P_CLKSRC2_MFC_SHIFT (4)
86#define S5P_CLKSRC2_MFC_MASK (0x3 << S5P_CLKSRC2_MFC_SHIFT)
87
88/* CLKSRC6*/
89#define S5P_CLKSRC6_ONEDRAM_SHIFT (24)
90#define S5P_CLKSRC6_ONEDRAM_MASK (0x3 << S5P_CLKSRC6_ONEDRAM_SHIFT)
91
75/* CLKDIV0 */ 92/* CLKDIV0 */
76#define S5P_CLKDIV0_APLL_SHIFT (0) 93#define S5P_CLKDIV0_APLL_SHIFT (0)
77#define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT) 94#define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT)
@@ -90,8 +107,20 @@
90#define S5P_CLKDIV0_PCLK66_SHIFT (28) 107#define S5P_CLKDIV0_PCLK66_SHIFT (28)
91#define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT) 108#define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT)
92 109
110/* CLKDIV2 */
111#define S5P_CLKDIV2_G3D_SHIFT (0)
112#define S5P_CLKDIV2_G3D_MASK (0xF << S5P_CLKDIV2_G3D_SHIFT)
113#define S5P_CLKDIV2_MFC_SHIFT (4)
114#define S5P_CLKDIV2_MFC_MASK (0xF << S5P_CLKDIV2_MFC_SHIFT)
115
116/* CLKDIV6 */
117#define S5P_CLKDIV6_ONEDRAM_SHIFT (28)
118#define S5P_CLKDIV6_ONEDRAM_MASK (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT)
119
93#define S5P_SWRESET S5P_CLKREG(0x2000) 120#define S5P_SWRESET S5P_CLKREG(0x2000)
94 121
122#define S5P_ARM_MCS_CON S5P_CLKREG(0x6100)
123
95/* Registers related to power management */ 124/* Registers related to power management */
96#define S5P_PWR_CFG S5P_CLKREG(0xC000) 125#define S5P_PWR_CFG S5P_CLKREG(0xC000)
97#define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004) 126#define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004)