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authorTodd Poynor <toddpoynor@google.com>2011-08-24 09:41:39 -0400
committerSantosh Shilimkar <santosh.shilimkar@ti.com>2011-09-24 03:58:56 -0400
commit342fd144292a6b64ea869e4052eb250486c8f326 (patch)
tree31d565b230763b63eb35238899d2d24dd3b4fe87 /arch/arm
parentb6fd41e29dea9c6753b1843a77e50433e6123bcb (diff)
OMAP: Improve register access in L3 Error handler.
* Changed the way of accessing L3 target registers from standard base rather than relative to STDERRLOG_MAIN. * Use ffs() to find error source from the L3_FLAGMUX_REGERRn register. * Remove extra l3_base[] entry. * Modified L3 custom error message. Signed-off-by: Todd Poynor <toddpoynor@google.com> Signed-off-by: sricharan <r.sricharan@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.c43
-rw-r--r--arch/arm/mach-omap2/omap_l3_noc.h86
-rw-r--r--arch/arm/mach-omap2/omap_l3_smx.c5
-rw-r--r--arch/arm/mach-omap2/omap_l3_smx.h2
4 files changed, 65 insertions, 71 deletions
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
index 7b9f1909ddb2..d560c8894e1f 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.c
+++ b/arch/arm/mach-omap2/omap_l3_noc.c
@@ -56,10 +56,9 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
56{ 56{
57 57
58 struct omap4_l3 *l3 = _l3; 58 struct omap4_l3 *l3 = _l3;
59 int inttype, i, j; 59 int inttype, i;
60 int err_src = 0; 60 int err_src = 0;
61 u32 std_err_main_addr, std_err_main, err_reg; 61 u32 std_err_main, err_reg, clear, base, l3_targ_base;
62 u32 base, slave_addr, clear;
63 char *source_name; 62 char *source_name;
64 63
65 /* Get the Type of interrupt */ 64 /* Get the Type of interrupt */
@@ -71,42 +70,43 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
71 * to determine the source 70 * to determine the source
72 */ 71 */
73 base = (u32)l3->l3_base[i]; 72 base = (u32)l3->l3_base[i];
74 err_reg = readl(base + l3_flagmux[i] + (inttype << 3)); 73 err_reg = readl(base + l3_flagmux[i] +
74 + L3_FLAGMUX_REGERR0 + (inttype << 3));
75 75
76 /* Get the corresponding error and analyse */ 76 /* Get the corresponding error and analyse */
77 if (err_reg) { 77 if (err_reg) {
78 /* Identify the source from control status register */ 78 /* Identify the source from control status register */
79 for (j = 0; !(err_reg & (1 << j)); j++) 79 err_src = __ffs(err_reg);
80 ;
81 80
82 err_src = j;
83 /* Read the stderrlog_main_source from clk domain */ 81 /* Read the stderrlog_main_source from clk domain */
84 std_err_main_addr = base + *(l3_targ[i] + err_src); 82 l3_targ_base = base + *(l3_targ[i] + err_src);
85 std_err_main = readl(std_err_main_addr); 83 std_err_main = readl(l3_targ_base +
84 L3_TARG_STDERRLOG_MAIN);
86 85
87 switch (std_err_main & CUSTOM_ERROR) { 86 switch (std_err_main & CUSTOM_ERROR) {
88 case STANDARD_ERROR: 87 case STANDARD_ERROR:
89 source_name = 88 source_name =
90 l3_targ_stderrlog_main_name[i][err_src]; 89 l3_targ_inst_name[i][err_src];
91
92 slave_addr = std_err_main_addr +
93 L3_SLAVE_ADDRESS_OFFSET;
94 WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n", 90 WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n",
95 source_name, readl(slave_addr)); 91 source_name,
92 readl(l3_targ_base +
93 L3_TARG_STDERRLOG_SLVOFSLSB));
96 /* clear the std error log*/ 94 /* clear the std error log*/
97 clear = std_err_main | CLEAR_STDERR_LOG; 95 clear = std_err_main | CLEAR_STDERR_LOG;
98 writel(clear, std_err_main_addr); 96 writel(clear, l3_targ_base +
97 L3_TARG_STDERRLOG_MAIN);
99 break; 98 break;
100 99
101 case CUSTOM_ERROR: 100 case CUSTOM_ERROR:
102 source_name = 101 source_name =
103 l3_targ_stderrlog_main_name[i][err_src]; 102 l3_targ_inst_name[i][err_src];
104 103
105 WARN(true, "CUSTOM SRESP error with SOURCE:%s\n", 104 WARN(true, "L3 custom error: SOURCE:%s\n",
106 source_name); 105 source_name);
107 /* clear the std error log*/ 106 /* clear the std error log*/
108 clear = std_err_main | CLEAR_STDERR_LOG; 107 clear = std_err_main | CLEAR_STDERR_LOG;
109 writel(clear, std_err_main_addr); 108 writel(clear, l3_targ_base +
109 L3_TARG_STDERRLOG_MAIN);
110 break; 110 break;
111 111
112 default: 112 default:
@@ -123,9 +123,8 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
123static int __init omap4_l3_probe(struct platform_device *pdev) 123static int __init omap4_l3_probe(struct platform_device *pdev)
124{ 124{
125 static struct omap4_l3 *l3; 125 static struct omap4_l3 *l3;
126 struct resource *res; 126 struct resource *res;
127 int ret; 127 int ret, irq;
128 int irq;
129 128
130 l3 = kzalloc(sizeof(*l3), GFP_KERNEL); 129 l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
131 if (!l3) 130 if (!l3)
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
index 359b83348aed..22c0d57ee3d9 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.h
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -23,63 +23,60 @@
23#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 23#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
24#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H 24#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
25 25
26/*
27 * L3 register offsets
28 */
29#define L3_MODULES 3 26#define L3_MODULES 3
30#define CLEAR_STDERR_LOG (1 << 31) 27#define CLEAR_STDERR_LOG (1 << 31)
31#define CUSTOM_ERROR 0x2 28#define CUSTOM_ERROR 0x2
32#define STANDARD_ERROR 0x0 29#define STANDARD_ERROR 0x0
33#define INBAND_ERROR 0x0 30#define INBAND_ERROR 0x0
34#define EMIF_KERRLOG_OFFSET 0x10
35#define L3_SLAVE_ADDRESS_OFFSET 0x14
36#define LOGICAL_ADDR_ERRORLOG 0x4
37#define L3_APPLICATION_ERROR 0x0 31#define L3_APPLICATION_ERROR 0x0
38#define L3_DEBUG_ERROR 0x1 32#define L3_DEBUG_ERROR 0x1
39 33
34/* L3 TARG register offsets */
35#define L3_TARG_STDERRLOG_MAIN 0x48
36#define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
37#define L3_FLAGMUX_REGERR0 0xc
38
40u32 l3_flagmux[L3_MODULES] = { 39u32 l3_flagmux[L3_MODULES] = {
41 0x50C, 40 0x500,
42 0x100C, 41 0x1000,
43 0X020C 42 0X0200
44}; 43};
45 44
46/* 45/* L3 Target standard Error register offsets */
47 * L3 Target standard Error register offsets 46u32 l3_targ_inst_clk1[] = {
48 */ 47 0x100, /* DMM1 */
49u32 l3_targ_stderrlog_main_clk1[] = { 48 0x200, /* DMM2 */
50 0x148, /* DMM1 */ 49 0x300, /* ABE */
51 0x248, /* DMM2 */ 50 0x400, /* L4CFG */
52 0x348, /* ABE */ 51 0x600 /* CLK2 PWR DISC */
53 0x448, /* L4CFG */
54 0x648 /* CLK2 PWR DISC */
55}; 52};
56 53
57u32 l3_targ_stderrlog_main_clk2[] = { 54u32 l3_targ_inst_clk2[] = {
58 0x548, /* CORTEX M3 */ 55 0x500, /* CORTEX M3 */
59 0x348, /* DSS */ 56 0x300, /* DSS */
60 0x148, /* GPMC */ 57 0x100, /* GPMC */
61 0x448, /* ISS */ 58 0x400, /* ISS */
62 0x748, /* IVAHD */ 59 0x700, /* IVAHD */
63 0xD48, /* missing in TRM corresponds to AES1*/ 60 0xD00, /* missing in TRM corresponds to AES1*/
64 0x948, /* L4 PER0*/ 61 0x900, /* L4 PER0*/
65 0x248, /* OCMRAM */ 62 0x200, /* OCMRAM */
66 0x148, /* missing in TRM corresponds to GPMC sERROR*/ 63 0x100, /* missing in TRM corresponds to GPMC sERROR*/
67 0x648, /* SGX */ 64 0x600, /* SGX */
68 0x848, /* SL2 */ 65 0x800, /* SL2 */
69 0x1648, /* C2C */ 66 0x1600, /* C2C */
70 0x1148, /* missing in TRM corresponds PWR DISC CLK1*/ 67 0x1100, /* missing in TRM corresponds PWR DISC CLK1*/
71 0xF48, /* missing in TRM corrsponds to SHA1*/ 68 0xF00, /* missing in TRM corrsponds to SHA1*/
72 0xE48, /* missing in TRM corresponds to AES2*/ 69 0xE00, /* missing in TRM corresponds to AES2*/
73 0xC48, /* L4 PER3 */ 70 0xC00, /* L4 PER3 */
74 0xA48, /* L4 PER1*/ 71 0xA00, /* L4 PER1*/
75 0xB48 /* L4 PER2*/ 72 0xB00 /* L4 PER2*/
76}; 73};
77 74
78u32 l3_targ_stderrlog_main_clk3[] = { 75u32 l3_targ_inst_clk3[] = {
79 0x0148 /* EMUSS */ 76 0x0100 /* EMUSS */
80}; 77};
81 78
82char *l3_targ_stderrlog_main_name[L3_MODULES][18] = { 79char *l3_targ_inst_name[L3_MODULES][18] = {
83 { 80 {
84 "DMM1", 81 "DMM1",
85 "DMM2", 82 "DMM2",
@@ -113,9 +110,9 @@ char *l3_targ_stderrlog_main_name[L3_MODULES][18] = {
113}; 110};
114 111
115u32 *l3_targ[L3_MODULES] = { 112u32 *l3_targ[L3_MODULES] = {
116 l3_targ_stderrlog_main_clk1, 113 l3_targ_inst_clk1,
117 l3_targ_stderrlog_main_clk2, 114 l3_targ_inst_clk2,
118 l3_targ_stderrlog_main_clk3, 115 l3_targ_inst_clk3,
119}; 116};
120 117
121struct omap4_l3 { 118struct omap4_l3 {
@@ -123,10 +120,9 @@ struct omap4_l3 {
123 struct clk *ick; 120 struct clk *ick;
124 121
125 /* memory base */ 122 /* memory base */
126 void __iomem *l3_base[4]; 123 void __iomem *l3_base[L3_MODULES];
127 124
128 int debug_irq; 125 int debug_irq;
129 int app_irq; 126 int app_irq;
130}; 127};
131
132#endif 128#endif
diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
index 873c0e33b512..fa07edf938b2 100644
--- a/arch/arm/mach-omap2/omap_l3_smx.c
+++ b/arch/arm/mach-omap2/omap_l3_smx.c
@@ -191,10 +191,9 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
191 } 191 }
192 192
193 /* identify the error source */ 193 /* identify the error source */
194 for (err_source = 0; !(status & (1 << err_source)); err_source++) 194 err_source = __ffs(status);
195 ;
196 195
197 base = l3->rt + *(omap3_l3_bases[int_type] + err_source); 196 base = l3->rt + omap3_l3_bases[int_type][err_source];
198 error = omap3_l3_readll(base, L3_ERROR_LOG); 197 error = omap3_l3_readll(base, L3_ERROR_LOG);
199 if (error) { 198 if (error) {
200 error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR); 199 error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h
index ba2ed9a850cc..185d77ad4b2e 100644
--- a/arch/arm/mach-omap2/omap_l3_smx.h
+++ b/arch/arm/mach-omap2/omap_l3_smx.h
@@ -40,7 +40,7 @@
40#define L3_SI_CONTROL 0x020 40#define L3_SI_CONTROL 0x020
41#define L3_SI_FLAG_STATUS_0 0x510 41#define L3_SI_FLAG_STATUS_0 0x510
42 42
43const u64 shift = 1; 43static const u64 shift = 1;
44 44
45#define L3_STATUS_0_MPUIA_BRST (shift << 0) 45#define L3_STATUS_0_MPUIA_BRST (shift << 0)
46#define L3_STATUS_0_MPUIA_RSP (shift << 1) 46#define L3_STATUS_0_MPUIA_RSP (shift << 1)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 14:07:28 -0500