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authorShawn Guo <shawn.guo@linaro.org>2013-07-18 01:08:20 -0400
committerShawn Guo <shawn.guo@linaro.org>2013-08-22 11:20:37 -0400
commit1fa5007b3a71ebf8e9ebc9fd039da5339bd8c3f8 (patch)
tree446f13cd6c572af1a294f54a361657244020d3a8 /arch/arm
parent0a036388529477bcce01226a8ba901ef16333393 (diff)
ARM: imx6q: add spdif gate clock
It adds the missing spdif gate clock into imx6q clock driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index db9f8f5646f1..d739df196a15 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -239,7 +239,8 @@ enum mx6q_clks {
239 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, 239 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
240 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, 240 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
241 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, 241 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
242 usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, clk_max 242 usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
243 spdif, clk_max
243}; 244};
244 245
245static struct clk *clk[clk_max]; 246static struct clk *clk[clk_max];
@@ -521,6 +522,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
521 clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4); 522 clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
522 clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); 523 clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
523 clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); 524 clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
525 clk[spdif] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
524 clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18); 526 clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
525 clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20); 527 clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
526 clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22); 528 clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);