aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm
diff options
context:
space:
mode:
authorArnd Bergmann <arnd@arndb.de>2014-11-20 11:38:09 -0500
committerArnd Bergmann <arnd@arndb.de>2014-11-20 11:38:09 -0500
commit1eb953d0b4b8a34b5e6a8d797152cd41ad8903c3 (patch)
treea05406d70b42b03a61f50f825f77910ed4b147ff /arch/arm
parentec498f8e5178b5f1ff431464f4aa17e94fdbb5a0 (diff)
parent8fba96fac1c48b242ff2b202332572b6eeef95cc (diff)
Merge tag 'v3.19-meson-dts' of https://github.com/carlocaione/linux-meson into next/dt
Pull "ARM: meson: DTS related changes" from Carlo Caione: here is the pull request for the DT related changes for the 3.19. It's mainly the work done by Beniamino for the preliminary support of the Amlogic Meson8 SoC, the support for L2 cache and the I2C controller. Please note that the support for the Tronsmart S89 Elite TV box has not been included since the Meson8 development will be done now on a different dev board kindly provided by Amlogic. * tag 'v3.19-meson-dts' of https://github.com/carlocaione/linux-meson: ARM: dts: meson: add I2C controller nodes ARM: meson: DTS: enable L2 cache ARM: dts: add dtsi for Amlogic Meson8 SoCs DTS: meson: Add forgotten compatible in board DTS Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/meson.dtsi37
-rw-r--r--arch/arm/boot/dts/meson6-atv1200.dts2
-rw-r--r--arch/arm/boot/dts/meson6.dtsi2
-rw-r--r--arch/arm/boot/dts/meson8.dtsi92
4 files changed, 132 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index e6539ea5a711..03bcff87bd27 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -50,6 +50,13 @@
50/ { 50/ {
51 interrupt-parent = <&gic>; 51 interrupt-parent = <&gic>;
52 52
53 L2: l2-cache-controller@c4200000 {
54 compatible = "arm,pl310-cache";
55 reg = <0xc4200000 0x1000>;
56 cache-unified;
57 cache-level = <2>;
58 };
59
53 gic: interrupt-controller@c4301000 { 60 gic: interrupt-controller@c4301000 {
54 compatible = "arm,cortex-a9-gic"; 61 compatible = "arm,cortex-a9-gic";
55 reg = <0xc4301000 0x1000>, 62 reg = <0xc4301000 0x1000>,
@@ -106,5 +113,35 @@
106 clocks = <&clk81>; 113 clocks = <&clk81>;
107 status = "disabled"; 114 status = "disabled";
108 }; 115 };
116
117 i2c_AO: i2c@c8100500 {
118 compatible = "amlogic,meson6-i2c";
119 reg = <0xc8100500 0x20>;
120 interrupts = <0 92 1>;
121 clocks = <&clk81>;
122 #address-cells = <1>;
123 #size-cells = <0>;
124 status = "disabled";
125 };
126
127 i2c_A: i2c@c1108500 {
128 compatible = "amlogic,meson6-i2c";
129 reg = <0xc1108500 0x20>;
130 interrupts = <0 21 1>;
131 clocks = <&clk81>;
132 #address-cells = <1>;
133 #size-cells = <0>;
134 status = "disabled";
135 };
136
137 i2c_B: i2c@c11087c0 {
138 compatible = "amlogic,meson6-i2c";
139 reg = <0xc11087c0 0x20>;
140 interrupts = <0 128 1>;
141 clocks = <&clk81>;
142 #address-cells = <1>;
143 #size-cells = <0>;
144 status = "disabled";
145 };
109 }; 146 };
110}; /* end of / */ 147}; /* end of / */
diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts
index dc2541faf1ec..d7d351a68944 100644
--- a/arch/arm/boot/dts/meson6-atv1200.dts
+++ b/arch/arm/boot/dts/meson6-atv1200.dts
@@ -50,7 +50,7 @@
50 50
51/ { 51/ {
52 model = "Geniatech ATV1200"; 52 model = "Geniatech ATV1200";
53 compatible = "geniatech,atv1200"; 53 compatible = "geniatech,atv1200", "amlogic,meson6";
54 54
55 aliases { 55 aliases {
56 serial0 = &uart_AO; 56 serial0 = &uart_AO;
diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi
index 4ba49127779f..8b33be15af94 100644
--- a/arch/arm/boot/dts/meson6.dtsi
+++ b/arch/arm/boot/dts/meson6.dtsi
@@ -60,12 +60,14 @@
60 cpu@200 { 60 cpu@200 {
61 device_type = "cpu"; 61 device_type = "cpu";
62 compatible = "arm,cortex-a9"; 62 compatible = "arm,cortex-a9";
63 next-level-cache = <&L2>;
63 reg = <0x200>; 64 reg = <0x200>;
64 }; 65 };
65 66
66 cpu@201 { 67 cpu@201 {
67 device_type = "cpu"; 68 device_type = "cpu";
68 compatible = "arm,cortex-a9"; 69 compatible = "arm,cortex-a9";
70 next-level-cache = <&L2>;
69 reg = <0x201>; 71 reg = <0x201>;
70 }; 72 };
71 }; 73 };
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
new file mode 100644
index 000000000000..1f442a7fe03b
--- /dev/null
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -0,0 +1,92 @@
1/*
2 * Copyright 2014 Carlo Caione <carlo@caione.org>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46/include/ "meson.dtsi"
47
48/ {
49 model = "Amlogic Meson8 SoC";
50 compatible = "amlogic,meson8";
51
52 interrupt-parent = <&gic>;
53
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 cpu@200 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a9";
61 next-level-cache = <&L2>;
62 reg = <0x200>;
63 };
64
65 cpu@201 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a9";
68 next-level-cache = <&L2>;
69 reg = <0x201>;
70 };
71
72 cpu@202 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a9";
75 next-level-cache = <&L2>;
76 reg = <0x202>;
77 };
78
79 cpu@203 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a9";
82 next-level-cache = <&L2>;
83 reg = <0x203>;
84 };
85 };
86
87 clk81: clk@0 {
88 #clock-cells = <0>;
89 compatible = "fixed-clock";
90 clock-frequency = <141666666>;
91 };
92}; /* end of / */