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authorChanghwan Youn <chaos.youn@samsung.com>2011-07-15 21:49:53 -0400
committerKukjin Kim <kgene.kim@samsung.com>2011-07-20 10:33:43 -0400
commit069d4e743c4b0c56c5a5374e1636db3ffe24ca32 (patch)
tree864effe3ba5031657af0282ef2bba29c7d104c7e /arch/arm
parentaab74d3e753649defa52ea43cbec1e91ebb4cc8e (diff)
ARM: EXYNOS4: Remove clock event timers using ARM private timers
External GIC cannot support PPI (Private Peripheral Interrupt) for ARM private timers. Thus MCT should be selected as clock event timers by default. Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-exynos4/Kconfig3
-rw-r--r--arch/arm/mach-exynos4/Makefile7
-rw-r--r--arch/arm/mach-exynos4/cpu.c2
-rw-r--r--arch/arm/mach-exynos4/include/mach/entry-macro.S6
-rw-r--r--arch/arm/mach-exynos4/include/mach/irqs.h2
-rw-r--r--arch/arm/mach-exynos4/localtimer.c26
-rw-r--r--arch/arm/mach-exynos4/time.c301
7 files changed, 4 insertions, 343 deletions
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 5115b90d1a7c..a4fb109984f6 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -16,7 +16,8 @@ config CPU_EXYNOS4210
16 Enable EXYNOS4210 CPU support 16 Enable EXYNOS4210 CPU support
17 17
18config EXYNOS4_MCT 18config EXYNOS4_MCT
19 bool "Kernel timer support by MCT" 19 bool
20 default y
20 help 21 help
21 Use MCT (Multi Core Timer) as kernel timers 22 Use MCT (Multi Core Timer) as kernel timers
22 23
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 60fe5ecf3599..c3c70aba4972 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -20,12 +20,7 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o
20 20
21obj-$(CONFIG_SMP) += platsmp.o headsmp.o 21obj-$(CONFIG_SMP) += platsmp.o headsmp.o
22 22
23ifeq ($(CONFIG_EXYNOS4_MCT),y) 23obj-$(CONFIG_EXYNOS4_MCT) += mct.o
24obj-y += mct.o
25else
26obj-y += time.o
27obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
28endif
29 24
30obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 25obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
31 26
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 7dccf4ab11ff..910ade65e035 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -173,7 +173,7 @@ void __init exynos4_init_irq(void)
173{ 173{
174 int irq; 174 int irq;
175 175
176 gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); 176 gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
177 gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi; 177 gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
178 178
179 for (irq = 0; irq < MAX_COMBINER_NR; irq++) { 179 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index 4fad076baa43..d7a1e281ce7a 100644
--- a/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -80,10 +80,4 @@
80 /* As above, this assumes that irqstat and base are preserved.. */ 80 /* As above, this assumes that irqstat and base are preserved.. */
81 81
82 .macro test_for_ltirq, irqnr, irqstat, base, tmp 82 .macro test_for_ltirq, irqnr, irqstat, base, tmp
83 bic \irqnr, \irqstat, #0x1c00
84 mov \tmp, #0
85 cmp \irqnr, #29
86 moveq \tmp, #1
87 streq \irqstat, [\base, #GIC_CPU_EOI]
88 cmp \tmp, #0
89 .endm 83 .endm
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index e497ea223eba..250427f6dcc1 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -19,8 +19,6 @@
19 19
20#define IRQ_PPI(x) S5P_IRQ(x+16) 20#define IRQ_PPI(x) S5P_IRQ(x+16)
21 21
22#define IRQ_LOCALTIMER IRQ_PPI(13)
23
24/* SPI: Shared Peripheral Interrupt */ 22/* SPI: Shared Peripheral Interrupt */
25 23
26#define IRQ_SPI(x) S5P_IRQ(x+32) 24#define IRQ_SPI(x) S5P_IRQ(x+32)
diff --git a/arch/arm/mach-exynos4/localtimer.c b/arch/arm/mach-exynos4/localtimer.c
deleted file mode 100644
index 6bf3d0ab9627..000000000000
--- a/arch/arm/mach-exynos4/localtimer.c
+++ /dev/null
@@ -1,26 +0,0 @@
1/* linux/arch/arm/mach-exynos4/localtimer.c
2 *
3 * Cloned from linux/arch/arm/mach-realview/localtimer.c
4 *
5 * Copyright (C) 2002 ARM Ltd.
6 * All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/clockchips.h>
14
15#include <asm/irq.h>
16#include <asm/localtimer.h>
17
18/*
19 * Setup the local clock events for a CPU.
20 */
21int __cpuinit local_timer_setup(struct clock_event_device *evt)
22{
23 evt->irq = IRQ_LOCALTIMER;
24 twd_timer_setup(evt);
25 return 0;
26}
diff --git a/arch/arm/mach-exynos4/time.c b/arch/arm/mach-exynos4/time.c
deleted file mode 100644
index ebb8f38d5405..000000000000
--- a/arch/arm/mach-exynos4/time.c
+++ /dev/null
@@ -1,301 +0,0 @@
1/* linux/arch/arm/mach-exynos4/time.c
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 (and compatible) HRT support
7 * PWM 2/4 is used for this feature
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/sched.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/clockchips.h>
20#include <linux/platform_device.h>
21
22#include <asm/smp_twd.h>
23
24#include <mach/map.h>
25#include <plat/regs-timer.h>
26#include <asm/mach/time.h>
27
28static unsigned long clock_count_per_tick;
29
30static struct clk *tin2;
31static struct clk *tin4;
32static struct clk *tdiv2;
33static struct clk *tdiv4;
34static struct clk *timerclk;
35
36static void exynos4_pwm_stop(unsigned int pwm_id)
37{
38 unsigned long tcon;
39
40 tcon = __raw_readl(S3C2410_TCON);
41
42 switch (pwm_id) {
43 case 2:
44 tcon &= ~S3C2410_TCON_T2START;
45 break;
46 case 4:
47 tcon &= ~S3C2410_TCON_T4START;
48 break;
49 default:
50 break;
51 }
52 __raw_writel(tcon, S3C2410_TCON);
53}
54
55static void exynos4_pwm_init(unsigned int pwm_id, unsigned long tcnt)
56{
57 unsigned long tcon;
58
59 tcon = __raw_readl(S3C2410_TCON);
60
61 /* timers reload after counting zero, so reduce the count by 1 */
62 tcnt--;
63
64 /* ensure timer is stopped... */
65 switch (pwm_id) {
66 case 2:
67 tcon &= ~(0xf<<12);
68 tcon |= S3C2410_TCON_T2MANUALUPD;
69
70 __raw_writel(tcnt, S3C2410_TCNTB(2));
71 __raw_writel(tcnt, S3C2410_TCMPB(2));
72 __raw_writel(tcon, S3C2410_TCON);
73
74 break;
75 case 4:
76 tcon &= ~(7<<20);
77 tcon |= S3C2410_TCON_T4MANUALUPD;
78
79 __raw_writel(tcnt, S3C2410_TCNTB(4));
80 __raw_writel(tcnt, S3C2410_TCMPB(4));
81 __raw_writel(tcon, S3C2410_TCON);
82
83 break;
84 default:
85 break;
86 }
87}
88
89static inline void exynos4_pwm_start(unsigned int pwm_id, bool periodic)
90{
91 unsigned long tcon;
92
93 tcon = __raw_readl(S3C2410_TCON);
94
95 switch (pwm_id) {
96 case 2:
97 tcon |= S3C2410_TCON_T2START;
98 tcon &= ~S3C2410_TCON_T2MANUALUPD;
99
100 if (periodic)
101 tcon |= S3C2410_TCON_T2RELOAD;
102 else
103 tcon &= ~S3C2410_TCON_T2RELOAD;
104 break;
105 case 4:
106 tcon |= S3C2410_TCON_T4START;
107 tcon &= ~S3C2410_TCON_T4MANUALUPD;
108
109 if (periodic)
110 tcon |= S3C2410_TCON_T4RELOAD;
111 else
112 tcon &= ~S3C2410_TCON_T4RELOAD;
113 break;
114 default:
115 break;
116 }
117 __raw_writel(tcon, S3C2410_TCON);
118}
119
120static int exynos4_pwm_set_next_event(unsigned long cycles,
121 struct clock_event_device *evt)
122{
123 exynos4_pwm_init(2, cycles);
124 exynos4_pwm_start(2, 0);
125 return 0;
126}
127
128static void exynos4_pwm_set_mode(enum clock_event_mode mode,
129 struct clock_event_device *evt)
130{
131 exynos4_pwm_stop(2);
132
133 switch (mode) {
134 case CLOCK_EVT_MODE_PERIODIC:
135 exynos4_pwm_init(2, clock_count_per_tick);
136 exynos4_pwm_start(2, 1);
137 break;
138 case CLOCK_EVT_MODE_ONESHOT:
139 break;
140 case CLOCK_EVT_MODE_UNUSED:
141 case CLOCK_EVT_MODE_SHUTDOWN:
142 case CLOCK_EVT_MODE_RESUME:
143 break;
144 }
145}
146
147static struct clock_event_device pwm_event_device = {
148 .name = "pwm_timer2",
149 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
150 .rating = 200,
151 .shift = 32,
152 .set_next_event = exynos4_pwm_set_next_event,
153 .set_mode = exynos4_pwm_set_mode,
154};
155
156irqreturn_t exynos4_clock_event_isr(int irq, void *dev_id)
157{
158 struct clock_event_device *evt = &pwm_event_device;
159
160 evt->event_handler(evt);
161
162 return IRQ_HANDLED;
163}
164
165static struct irqaction exynos4_clock_event_irq = {
166 .name = "pwm_timer2_irq",
167 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
168 .handler = exynos4_clock_event_isr,
169};
170
171static void __init exynos4_clockevent_init(void)
172{
173 unsigned long pclk;
174 unsigned long clock_rate;
175 struct clk *tscaler;
176
177 pclk = clk_get_rate(timerclk);
178
179 /* configure clock tick */
180
181 tscaler = clk_get_parent(tdiv2);
182
183 clk_set_rate(tscaler, pclk / 2);
184 clk_set_rate(tdiv2, pclk / 2);
185 clk_set_parent(tin2, tdiv2);
186
187 clock_rate = clk_get_rate(tin2);
188
189 clock_count_per_tick = clock_rate / HZ;
190
191 pwm_event_device.mult =
192 div_sc(clock_rate, NSEC_PER_SEC, pwm_event_device.shift);
193 pwm_event_device.max_delta_ns =
194 clockevent_delta2ns(-1, &pwm_event_device);
195 pwm_event_device.min_delta_ns =
196 clockevent_delta2ns(1, &pwm_event_device);
197
198 pwm_event_device.cpumask = cpumask_of(0);
199 clockevents_register_device(&pwm_event_device);
200
201 setup_irq(IRQ_TIMER2, &exynos4_clock_event_irq);
202}
203
204static cycle_t exynos4_pwm4_read(struct clocksource *cs)
205{
206 return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40));
207}
208
209#ifdef CONFIG_PM
210static void exynos4_pwm4_resume(struct clocksource *cs)
211{
212 unsigned long pclk;
213
214 pclk = clk_get_rate(timerclk);
215
216 clk_set_rate(tdiv4, pclk / 2);
217 clk_set_parent(tin4, tdiv4);
218
219 exynos4_pwm_init(4, ~0);
220 exynos4_pwm_start(4, 1);
221}
222#endif
223
224struct clocksource pwm_clocksource = {
225 .name = "pwm_timer4",
226 .rating = 250,
227 .read = exynos4_pwm4_read,
228 .mask = CLOCKSOURCE_MASK(32),
229 .flags = CLOCK_SOURCE_IS_CONTINUOUS ,
230#ifdef CONFIG_PM
231 .resume = exynos4_pwm4_resume,
232#endif
233};
234
235static void __init exynos4_clocksource_init(void)
236{
237 unsigned long pclk;
238 unsigned long clock_rate;
239
240 pclk = clk_get_rate(timerclk);
241
242 clk_set_rate(tdiv4, pclk / 2);
243 clk_set_parent(tin4, tdiv4);
244
245 clock_rate = clk_get_rate(tin4);
246
247 exynos4_pwm_init(4, ~0);
248 exynos4_pwm_start(4, 1);
249
250 if (clocksource_register_hz(&pwm_clocksource, clock_rate))
251 panic("%s: can't register clocksource\n", pwm_clocksource.name);
252}
253
254static void __init exynos4_timer_resources(void)
255{
256 struct platform_device tmpdev;
257
258 tmpdev.dev.bus = &platform_bus_type;
259
260 timerclk = clk_get(NULL, "timers");
261 if (IS_ERR(timerclk))
262 panic("failed to get timers clock for system timer");
263
264 clk_enable(timerclk);
265
266 tmpdev.id = 2;
267 tin2 = clk_get(&tmpdev.dev, "pwm-tin");
268 if (IS_ERR(tin2))
269 panic("failed to get pwm-tin2 clock for system timer");
270
271 tdiv2 = clk_get(&tmpdev.dev, "pwm-tdiv");
272 if (IS_ERR(tdiv2))
273 panic("failed to get pwm-tdiv2 clock for system timer");
274 clk_enable(tin2);
275
276 tmpdev.id = 4;
277 tin4 = clk_get(&tmpdev.dev, "pwm-tin");
278 if (IS_ERR(tin4))
279 panic("failed to get pwm-tin4 clock for system timer");
280
281 tdiv4 = clk_get(&tmpdev.dev, "pwm-tdiv");
282 if (IS_ERR(tdiv4))
283 panic("failed to get pwm-tdiv4 clock for system timer");
284
285 clk_enable(tin4);
286}
287
288static void __init exynos4_timer_init(void)
289{
290#ifdef CONFIG_LOCAL_TIMERS
291 twd_base = S5P_VA_TWD;
292#endif
293
294 exynos4_timer_resources();
295 exynos4_clockevent_init();
296 exynos4_clocksource_init();
297}
298
299struct sys_timer exynos4_timer = {
300 .init = exynos4_timer_init,
301};