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authorSylwester Nawrocki <s.nawrocki@samsung.com>2012-05-12 02:31:53 -0400
committerKukjin Kim <kgene.kim@samsung.com>2012-05-12 02:32:00 -0400
commit06050e5580aaab667e5f25bc6cb0d554f8683bf0 (patch)
tree7232f487a35ca51d0a88a1bbd0e44115cda51023 /arch/arm
parentad28536a898fbdc8c57d64348e310e1bda776963 (diff)
ARM: EXYNOS: Add platform resource definitions for FIMC-LITE
Add the gate clocks and register region address definition for FIMC-LITE devices available in EXYNOS4X12 SoCs. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-exynos/clock-exynos4212.c10
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h3
2 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 98823120570e..da397d21bbcf 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -92,6 +92,16 @@ static struct clk init_clocks_off[] = {
92 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9), 92 .devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
93 .enable = exynos4212_clk_ip_isp1_ctrl, 93 .enable = exynos4212_clk_ip_isp1_ctrl,
94 .ctrlbit = (1 << 4), 94 .ctrlbit = (1 << 4),
95 }, {
96 .name = "flite",
97 .devname = "exynos-fimc-lite.0",
98 .enable = exynos4212_clk_ip_isp0_ctrl,
99 .ctrlbit = (1 << 4),
100 }, {
101 .name = "flite",
102 .devname = "exynos-fimc-lite.1",
103 .enable = exynos4212_clk_ip_isp0_ctrl,
104 .ctrlbit = (1 << 3),
95 } 105 }
96}; 106};
97 107
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 0e2292d04550..d30643ba2739 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -34,6 +34,9 @@
34 34
35#define EXYNOS4_PA_JPEG 0x11840000 35#define EXYNOS4_PA_JPEG 0x11840000
36 36
37/* x = 0...1 */
38#define EXYNOS4_PA_FIMC_LITE(x) (0x12390000 + ((x) * 0x10000))
39
37#define EXYNOS4_PA_G2D 0x12800000 40#define EXYNOS4_PA_G2D 0x12800000
38 41
39#define EXYNOS4_PA_I2S0 0x03830000 42#define EXYNOS4_PA_I2S0 0x03830000