diff options
| author | Nicolas Pitre <nico@cam.org> | 2008-10-22 23:34:08 -0400 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-10-23 07:53:32 -0400 |
| commit | 884afaab44c9f92eb618ce53b3d2b5316f174a39 (patch) | |
| tree | 4d2795bc6050916411092736e5fe37ba5640983d /arch/arm | |
| parent | f80a3bb252cbb0959259328b9ab02b019123ed05 (diff) | |
[ARM] 5320/1: fix assembly constraints in implementation of do_div()
Those inline assembly segments using the umlal instruction must have
the & modifier so to be sure that a purely input register won't alias
one of the registers used as input+output. In most cases, the inputs
are still used after the outputs are touched, and most binutil versions
insist on "rdhi, rdlo and rm must all be different" even for ARMv6+.
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/include/asm/div64.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/include/asm/div64.h b/arch/arm/include/asm/div64.h index 5001390be958..d3f0a9eee9f6 100644 --- a/arch/arm/include/asm/div64.h +++ b/arch/arm/include/asm/div64.h | |||
| @@ -165,7 +165,7 @@ | |||
| 165 | __res = __m; \ | 165 | __res = __m; \ |
| 166 | asm ( "umlal %Q0, %R0, %Q1, %Q2\n\t" \ | 166 | asm ( "umlal %Q0, %R0, %Q1, %Q2\n\t" \ |
| 167 | "mov %Q0, #0" \ | 167 | "mov %Q0, #0" \ |
| 168 | : "+r" (__res) \ | 168 | : "+&r" (__res) \ |
| 169 | : "r" (__m), "r" (__n) \ | 169 | : "r" (__m), "r" (__n) \ |
| 170 | : "cc" ); \ | 170 | : "cc" ); \ |
| 171 | } else { \ | 171 | } else { \ |
| @@ -182,7 +182,7 @@ | |||
| 182 | "umlal %R0, %Q0, %Q1, %R2\n\t" \ | 182 | "umlal %R0, %Q0, %Q1, %R2\n\t" \ |
| 183 | "mov %R0, #0\n\t" \ | 183 | "mov %R0, #0\n\t" \ |
| 184 | "umlal %Q0, %R0, %R1, %R2" \ | 184 | "umlal %Q0, %R0, %R1, %R2" \ |
| 185 | : "+r" (__res) \ | 185 | : "+&r" (__res) \ |
| 186 | : "r" (__m), "r" (__n) \ | 186 | : "r" (__m), "r" (__n) \ |
| 187 | : "cc" ); \ | 187 | : "cc" ); \ |
| 188 | } else { \ | 188 | } else { \ |
| @@ -192,7 +192,7 @@ | |||
| 192 | "adds %Q0, %1, %Q0\n\t" \ | 192 | "adds %Q0, %1, %Q0\n\t" \ |
| 193 | "adc %R0, %R0, #0\n\t" \ | 193 | "adc %R0, %R0, #0\n\t" \ |
| 194 | "umlal %Q0, %R0, %R2, %R3" \ | 194 | "umlal %Q0, %R0, %R2, %R3" \ |
| 195 | : "+r" (__res), "+r" (__z) \ | 195 | : "+&r" (__res), "+&r" (__z) \ |
| 196 | : "r" (__m), "r" (__n) \ | 196 | : "r" (__m), "r" (__n) \ |
| 197 | : "cc" ); \ | 197 | : "cc" ); \ |
| 198 | } \ | 198 | } \ |