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authorAl Viro <viro@ftp.linux.org.uk>2006-10-11 12:22:34 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-10-11 14:17:06 -0400
commit399ad77b9098ed2eb27cbfbeb6449c1caab3c18e (patch)
tree6282ac7b48efc4354b44eaae3aaac6bbfbe81f8b /arch/arm
parentfc048b5b0f2554bc953a8ada5b2e3b82bde2fcb0 (diff)
[PATCH] arm-versatile iomem annotations
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-versatile/core.c4
-rw-r--r--arch/arm/mach-versatile/pci.c32
2 files changed, 18 insertions, 18 deletions
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 2aa150b57ba1..3b8576111c16 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -188,12 +188,12 @@ static struct map_desc versatile_io_desc[] __initdata = {
188 .length = SZ_4K, 188 .length = SZ_4K,
189 .type = MT_DEVICE 189 .type = MT_DEVICE
190 }, { 190 }, {
191 .virtual = VERSATILE_PCI_VIRT_BASE, 191 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
192 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE), 192 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
193 .length = VERSATILE_PCI_BASE_SIZE, 193 .length = VERSATILE_PCI_BASE_SIZE,
194 .type = MT_DEVICE 194 .type = MT_DEVICE
195 }, { 195 }, {
196 .virtual = VERSATILE_PCI_CFG_VIRT_BASE, 196 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
197 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE), 197 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
198 .length = VERSATILE_PCI_CFG_BASE_SIZE, 198 .length = VERSATILE_PCI_CFG_BASE_SIZE,
199 .type = MT_DEVICE 199 .type = MT_DEVICE
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index 13bbd08ff841..5cd0b5d9e7eb 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -40,14 +40,15 @@
40 * Cfg 42000000 - 42FFFFFF PCI config 40 * Cfg 42000000 - 42FFFFFF PCI config
41 * 41 *
42 */ 42 */
43#define SYS_PCICTL IO_ADDRESS(VERSATILE_SYS_PCICTL) 43#define __IO_ADDRESS(n) ((void __iomem *)(unsigned long)IO_ADDRESS(n))
44#define PCI_IMAP0 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0) 44#define SYS_PCICTL __IO_ADDRESS(VERSATILE_SYS_PCICTL)
45#define PCI_IMAP1 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4) 45#define PCI_IMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
46#define PCI_IMAP2 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8) 46#define PCI_IMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
47#define PCI_SMAP0 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10) 47#define PCI_IMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
48#define PCI_SMAP1 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14) 48#define PCI_SMAP0 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10)
49#define PCI_SMAP2 IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18) 49#define PCI_SMAP1 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
50#define PCI_SELFID IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc) 50#define PCI_SMAP2 __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
51#define PCI_SELFID __IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)
51 52
52#define DEVICE_ID_OFFSET 0x00 53#define DEVICE_ID_OFFSET 0x00
53#define CSR_OFFSET 0x04 54#define CSR_OFFSET 0x04
@@ -76,7 +77,7 @@ static int __init versatile_pci_slot_ignore(char *str)
76__setup("pci_slot_ignore=", versatile_pci_slot_ignore); 77__setup("pci_slot_ignore=", versatile_pci_slot_ignore);
77 78
78 79
79static unsigned long __pci_addr(struct pci_bus *bus, 80static void __iomem *__pci_addr(struct pci_bus *bus,
80 unsigned int devfn, int offset) 81 unsigned int devfn, int offset)
81{ 82{
82 unsigned int busnr = bus->number; 83 unsigned int busnr = bus->number;
@@ -91,14 +92,14 @@ static unsigned long __pci_addr(struct pci_bus *bus,
91 if (devfn > 255) 92 if (devfn > 255)
92 BUG(); 93 BUG();
93 94
94 return (VERSATILE_PCI_CFG_VIRT_BASE | (busnr << 16) | 95 return VERSATILE_PCI_CFG_VIRT_BASE + ((busnr << 16) |
95 (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset); 96 (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | offset);
96} 97}
97 98
98static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where, 99static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int where,
99 int size, u32 *val) 100 int size, u32 *val)
100{ 101{
101 unsigned long addr = __pci_addr(bus, devfn, where); 102 void __iomem *addr = __pci_addr(bus, devfn, where & ~3);
102 u32 v; 103 u32 v;
103 int slot = PCI_SLOT(devfn); 104 int slot = PCI_SLOT(devfn);
104 105
@@ -121,13 +122,12 @@ static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int wh
121 break; 122 break;
122 123
123 case 2: 124 case 2:
124 v = __raw_readl(addr & ~3); 125 v = __raw_readl(addr);
125 if (addr & 2) v >>= 16; 126 if (where & 2) v >>= 16;
126 v &= 0xffff; 127 v &= 0xffff;
127 break; 128 break;
128 129
129 default: 130 default:
130 addr &= ~3;
131 v = __raw_readl(addr); 131 v = __raw_readl(addr);
132 break; 132 break;
133 } 133 }
@@ -140,7 +140,7 @@ static int versatile_read_config(struct pci_bus *bus, unsigned int devfn, int wh
140static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where, 140static int versatile_write_config(struct pci_bus *bus, unsigned int devfn, int where,
141 int size, u32 val) 141 int size, u32 val)
142{ 142{
143 unsigned long addr = __pci_addr(bus, devfn, where); 143 void __iomem *addr = __pci_addr(bus, devfn, where);
144 int slot = PCI_SLOT(devfn); 144 int slot = PCI_SLOT(devfn);
145 145
146 if (pci_slot_ignore & (1 << slot)) { 146 if (pci_slot_ignore & (1 << slot)) {
@@ -279,7 +279,7 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
279 printk("PCI core found (slot %d)\n",myslot); 279 printk("PCI core found (slot %d)\n",myslot);
280 280
281 __raw_writel(myslot, PCI_SELFID); 281 __raw_writel(myslot, PCI_SELFID);
282 local_pci_cfg_base = (void *) VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11); 282 local_pci_cfg_base = VERSATILE_PCI_CFG_VIRT_BASE + (myslot << 11);
283 283
284 val = __raw_readl(local_pci_cfg_base + CSR_OFFSET); 284 val = __raw_readl(local_pci_cfg_base + CSR_OFFSET);
285 val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE; 285 val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;