diff options
author | Ben Dooks <ben-linux@fluff.org> | 2006-09-28 15:45:29 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-09-28 15:49:32 -0400 |
commit | 625ac112d4253c7e5f7a6d59c99943e8eb0b46c9 (patch) | |
tree | e193d3557e66fa7ca31756306e16bce7b9a07f9e /arch/arm | |
parent | 38e0533ce87a58e25f959e6d0958478b6a137794 (diff) |
[ARM] 3872/1: S3C24XX: Apply consistant tabbing to irq_chips
Apply consistant tabbing to the IRQ chip
structures in arch/arm/mach-s3c2410/irq.c
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-s3c2410/irq.c | 60 |
1 files changed, 30 insertions, 30 deletions
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c index 0ecfef3c7514..edfeebd7362c 100644 --- a/arch/arm/mach-s3c2410/irq.c +++ b/arch/arm/mach-s3c2410/irq.c | |||
@@ -181,17 +181,17 @@ s3c_irq_unmask(unsigned int irqno) | |||
181 | } | 181 | } |
182 | 182 | ||
183 | struct irqchip s3c_irq_level_chip = { | 183 | struct irqchip s3c_irq_level_chip = { |
184 | .ack = s3c_irq_maskack, | 184 | .ack = s3c_irq_maskack, |
185 | .mask = s3c_irq_mask, | 185 | .mask = s3c_irq_mask, |
186 | .unmask = s3c_irq_unmask, | 186 | .unmask = s3c_irq_unmask, |
187 | .set_wake = s3c_irq_wake | 187 | .set_wake = s3c_irq_wake |
188 | }; | 188 | }; |
189 | 189 | ||
190 | static struct irqchip s3c_irq_chip = { | 190 | static struct irqchip s3c_irq_chip = { |
191 | .ack = s3c_irq_ack, | 191 | .ack = s3c_irq_ack, |
192 | .mask = s3c_irq_mask, | 192 | .mask = s3c_irq_mask, |
193 | .unmask = s3c_irq_unmask, | 193 | .unmask = s3c_irq_unmask, |
194 | .set_wake = s3c_irq_wake | 194 | .set_wake = s3c_irq_wake |
195 | }; | 195 | }; |
196 | 196 | ||
197 | static void | 197 | static void |
@@ -343,19 +343,19 @@ s3c_irqext_type(unsigned int irq, unsigned int type) | |||
343 | } | 343 | } |
344 | 344 | ||
345 | static struct irqchip s3c_irqext_chip = { | 345 | static struct irqchip s3c_irqext_chip = { |
346 | .mask = s3c_irqext_mask, | 346 | .mask = s3c_irqext_mask, |
347 | .unmask = s3c_irqext_unmask, | 347 | .unmask = s3c_irqext_unmask, |
348 | .ack = s3c_irqext_ack, | 348 | .ack = s3c_irqext_ack, |
349 | .set_type = s3c_irqext_type, | 349 | .set_type = s3c_irqext_type, |
350 | .set_wake = s3c_irqext_wake | 350 | .set_wake = s3c_irqext_wake |
351 | }; | 351 | }; |
352 | 352 | ||
353 | static struct irqchip s3c_irq_eint0t4 = { | 353 | static struct irqchip s3c_irq_eint0t4 = { |
354 | .ack = s3c_irq_ack, | 354 | .ack = s3c_irq_ack, |
355 | .mask = s3c_irq_mask, | 355 | .mask = s3c_irq_mask, |
356 | .unmask = s3c_irq_unmask, | 356 | .unmask = s3c_irq_unmask, |
357 | .set_wake = s3c_irq_wake, | 357 | .set_wake = s3c_irq_wake, |
358 | .set_type = s3c_irqext_type, | 358 | .set_type = s3c_irqext_type, |
359 | }; | 359 | }; |
360 | 360 | ||
361 | /* mask values for the parent registers for each of the interrupt types */ | 361 | /* mask values for the parent registers for each of the interrupt types */ |
@@ -387,9 +387,9 @@ s3c_irq_uart0_ack(unsigned int irqno) | |||
387 | } | 387 | } |
388 | 388 | ||
389 | static struct irqchip s3c_irq_uart0 = { | 389 | static struct irqchip s3c_irq_uart0 = { |
390 | .mask = s3c_irq_uart0_mask, | 390 | .mask = s3c_irq_uart0_mask, |
391 | .unmask = s3c_irq_uart0_unmask, | 391 | .unmask = s3c_irq_uart0_unmask, |
392 | .ack = s3c_irq_uart0_ack, | 392 | .ack = s3c_irq_uart0_ack, |
393 | }; | 393 | }; |
394 | 394 | ||
395 | /* UART1 */ | 395 | /* UART1 */ |
@@ -413,9 +413,9 @@ s3c_irq_uart1_ack(unsigned int irqno) | |||
413 | } | 413 | } |
414 | 414 | ||
415 | static struct irqchip s3c_irq_uart1 = { | 415 | static struct irqchip s3c_irq_uart1 = { |
416 | .mask = s3c_irq_uart1_mask, | 416 | .mask = s3c_irq_uart1_mask, |
417 | .unmask = s3c_irq_uart1_unmask, | 417 | .unmask = s3c_irq_uart1_unmask, |
418 | .ack = s3c_irq_uart1_ack, | 418 | .ack = s3c_irq_uart1_ack, |
419 | }; | 419 | }; |
420 | 420 | ||
421 | /* UART2 */ | 421 | /* UART2 */ |
@@ -439,9 +439,9 @@ s3c_irq_uart2_ack(unsigned int irqno) | |||
439 | } | 439 | } |
440 | 440 | ||
441 | static struct irqchip s3c_irq_uart2 = { | 441 | static struct irqchip s3c_irq_uart2 = { |
442 | .mask = s3c_irq_uart2_mask, | 442 | .mask = s3c_irq_uart2_mask, |
443 | .unmask = s3c_irq_uart2_unmask, | 443 | .unmask = s3c_irq_uart2_unmask, |
444 | .ack = s3c_irq_uart2_ack, | 444 | .ack = s3c_irq_uart2_ack, |
445 | }; | 445 | }; |
446 | 446 | ||
447 | /* ADC and Touchscreen */ | 447 | /* ADC and Touchscreen */ |
@@ -465,9 +465,9 @@ s3c_irq_adc_ack(unsigned int irqno) | |||
465 | } | 465 | } |
466 | 466 | ||
467 | static struct irqchip s3c_irq_adc = { | 467 | static struct irqchip s3c_irq_adc = { |
468 | .mask = s3c_irq_adc_mask, | 468 | .mask = s3c_irq_adc_mask, |
469 | .unmask = s3c_irq_adc_unmask, | 469 | .unmask = s3c_irq_adc_unmask, |
470 | .ack = s3c_irq_adc_ack, | 470 | .ack = s3c_irq_adc_ack, |
471 | }; | 471 | }; |
472 | 472 | ||
473 | /* irq demux for adc */ | 473 | /* irq demux for adc */ |