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authorBen Dooks <ben-linux@fluff.org>2006-01-09 16:16:18 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-01-09 16:16:18 -0500
commitfe38ea5623d262afc0b92ea47b8a7d8c988521d2 (patch)
treec08a8899b3281f4815d011d8b6f03909184875a1 /arch/arm
parent9d4ae7276ae26c5bfba6207cf05340af1931d8d4 (diff)
[ARM] 3246/1: S3C24XX - retab clock list in arch/arm/mach-s3c2410/clock.c
Patch from Ben Dooks Properly tabulate the clock table in arch/arm/mach-s3c2410/clock.c and put the requisite commas on the end of the structs. Fix the comment about clock enable and disable in the setup code Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-s3c2410/clock.c206
1 files changed, 103 insertions, 103 deletions
diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c
index 5830ae3ddd19..fc09ba92d66a 100644
--- a/arch/arm/mach-s3c2410/clock.c
+++ b/arch/arm/mach-s3c2410/clock.c
@@ -253,100 +253,101 @@ struct clk s3c24xx_uclk = {
253/* clock definitions */ 253/* clock definitions */
254 254
255static struct clk init_clocks[] = { 255static struct clk init_clocks[] = {
256 { .name = "nand", 256 {
257 .id = -1, 257 .name = "nand",
258 .parent = &clk_h, 258 .id = -1,
259 .enable = s3c24xx_clkcon_enable, 259 .parent = &clk_h,
260 .ctrlbit = S3C2410_CLKCON_NAND 260 .enable = s3c24xx_clkcon_enable,
261 }, 261 .ctrlbit = S3C2410_CLKCON_NAND,
262 { .name = "lcd", 262 }, {
263 .id = -1, 263 .name = "lcd",
264 .parent = &clk_h, 264 .id = -1,
265 .enable = s3c24xx_clkcon_enable, 265 .parent = &clk_h,
266 .ctrlbit = S3C2410_CLKCON_LCDC 266 .enable = s3c24xx_clkcon_enable,
267 }, 267 .ctrlbit = S3C2410_CLKCON_LCDC,
268 { .name = "usb-host", 268 }, {
269 .id = -1, 269 .name = "usb-host",
270 .parent = &clk_h, 270 .id = -1,
271 .enable = s3c24xx_clkcon_enable, 271 .parent = &clk_h,
272 .ctrlbit = S3C2410_CLKCON_USBH 272 .enable = s3c24xx_clkcon_enable,
273 }, 273 .ctrlbit = S3C2410_CLKCON_USBH,
274 { .name = "usb-device", 274 }, {
275 .id = -1, 275 .name = "usb-device",
276 .parent = &clk_h, 276 .id = -1,
277 .enable = s3c24xx_clkcon_enable, 277 .parent = &clk_h,
278 .ctrlbit = S3C2410_CLKCON_USBD 278 .enable = s3c24xx_clkcon_enable,
279 }, 279 .ctrlbit = S3C2410_CLKCON_USBD,
280 { .name = "timers", 280 }, {
281 .id = -1, 281 .name = "timers",
282 .parent = &clk_p, 282 .id = -1,
283 .enable = s3c24xx_clkcon_enable, 283 .parent = &clk_p,
284 .ctrlbit = S3C2410_CLKCON_PWMT 284 .enable = s3c24xx_clkcon_enable,
285 }, 285 .ctrlbit = S3C2410_CLKCON_PWMT,
286 { .name = "sdi", 286 }, {
287 .id = -1, 287 .name = "sdi",
288 .parent = &clk_p, 288 .id = -1,
289 .enable = s3c24xx_clkcon_enable, 289 .parent = &clk_p,
290 .ctrlbit = S3C2410_CLKCON_SDI 290 .enable = s3c24xx_clkcon_enable,
291 }, 291 .ctrlbit = S3C2410_CLKCON_SDI,
292 { .name = "uart", 292 }, {
293 .id = 0, 293 .name = "uart",
294 .parent = &clk_p, 294 .id = 0,
295 .enable = s3c24xx_clkcon_enable, 295 .parent = &clk_p,
296 .ctrlbit = S3C2410_CLKCON_UART0 296 .enable = s3c24xx_clkcon_enable,
297 }, 297 .ctrlbit = S3C2410_CLKCON_UART0,
298 { .name = "uart", 298 }, {
299 .id = 1, 299 .name = "uart",
300 .parent = &clk_p, 300 .id = 1,
301 .enable = s3c24xx_clkcon_enable, 301 .parent = &clk_p,
302 .ctrlbit = S3C2410_CLKCON_UART1 302 .enable = s3c24xx_clkcon_enable,
303 }, 303 .ctrlbit = S3C2410_CLKCON_UART1,
304 { .name = "uart", 304 }, {
305 .id = 2, 305 .name = "uart",
306 .parent = &clk_p, 306 .id = 2,
307 .enable = s3c24xx_clkcon_enable, 307 .parent = &clk_p,
308 .ctrlbit = S3C2410_CLKCON_UART2 308 .enable = s3c24xx_clkcon_enable,
309 }, 309 .ctrlbit = S3C2410_CLKCON_UART2,
310 { .name = "gpio", 310 }, {
311 .id = -1, 311 .name = "gpio",
312 .parent = &clk_p, 312 .id = -1,
313 .enable = s3c24xx_clkcon_enable, 313 .parent = &clk_p,
314 .ctrlbit = S3C2410_CLKCON_GPIO 314 .enable = s3c24xx_clkcon_enable,
315 }, 315 .ctrlbit = S3C2410_CLKCON_GPIO,
316 { .name = "rtc", 316 }, {
317 .id = -1, 317 .name = "rtc",
318 .parent = &clk_p, 318 .id = -1,
319 .enable = s3c24xx_clkcon_enable, 319 .parent = &clk_p,
320 .ctrlbit = S3C2410_CLKCON_RTC 320 .enable = s3c24xx_clkcon_enable,
321 }, 321 .ctrlbit = S3C2410_CLKCON_RTC,
322 { .name = "adc", 322 }, {
323 .id = -1, 323 .name = "adc",
324 .parent = &clk_p, 324 .id = -1,
325 .enable = s3c24xx_clkcon_enable, 325 .parent = &clk_p,
326 .ctrlbit = S3C2410_CLKCON_ADC 326 .enable = s3c24xx_clkcon_enable,
327 }, 327 .ctrlbit = S3C2410_CLKCON_ADC,
328 { .name = "i2c", 328 }, {
329 .id = -1, 329 .name = "i2c",
330 .parent = &clk_p, 330 .id = -1,
331 .enable = s3c24xx_clkcon_enable, 331 .parent = &clk_p,
332 .ctrlbit = S3C2410_CLKCON_IIC 332 .enable = s3c24xx_clkcon_enable,
333 }, 333 .ctrlbit = S3C2410_CLKCON_IIC,
334 { .name = "iis", 334 }, {
335 .id = -1, 335 .name = "iis",
336 .parent = &clk_p, 336 .id = -1,
337 .enable = s3c24xx_clkcon_enable, 337 .parent = &clk_p,
338 .ctrlbit = S3C2410_CLKCON_IIS 338 .enable = s3c24xx_clkcon_enable,
339 }, 339 .ctrlbit = S3C2410_CLKCON_IIS,
340 { .name = "spi", 340 }, {
341 .id = -1, 341 .name = "spi",
342 .parent = &clk_p, 342 .id = -1,
343 .enable = s3c24xx_clkcon_enable, 343 .parent = &clk_p,
344 .ctrlbit = S3C2410_CLKCON_SPI 344 .enable = s3c24xx_clkcon_enable,
345 }, 345 .ctrlbit = S3C2410_CLKCON_SPI,
346 { .name = "watchdog", 346 }, {
347 .id = -1, 347 .name = "watchdog",
348 .parent = &clk_p, 348 .id = -1,
349 .ctrlbit = 0 349 .parent = &clk_p,
350 .ctrlbit = 0,
350 } 351 }
351}; 352};
352 353
@@ -390,16 +391,15 @@ int __init s3c24xx_setup_clocks(unsigned long xtal,
390 clk_p.rate = pclk; 391 clk_p.rate = pclk;
391 clk_f.rate = fclk; 392 clk_f.rate = fclk;
392 393
393 /* it looks like just setting the register here is not good 394 /* We must be careful disabling the clocks we are not intending to
394 * enough, and causes the odd hang at initial boot time, so 395 * be using at boot time, as subsytems such as the LCD which do
395 * do all of them indivdually. 396 * their own DMA requests to the bus can cause the system to lockup
397 * if they where in the middle of requesting bus access.
396 * 398 *
397 * I think disabling the LCD clock if the LCD is active is 399 * Disabling the LCD clock if the LCD is active is very dangerous,
398 * very dangerous, and therefore the bootloader should be 400 * and therefore the bootloader should be careful to not enable
399 * careful to not enable the LCD clock if it is not needed. 401 * the LCD clock if it is not needed.
400 * 402 */
401 * and of course, this looks neater
402 */
403 403
404 s3c24xx_clk_enable(S3C2410_CLKCON_NAND, 0); 404 s3c24xx_clk_enable(S3C2410_CLKCON_NAND, 0);
405 s3c24xx_clk_enable(S3C2410_CLKCON_USBH, 0); 405 s3c24xx_clk_enable(S3C2410_CLKCON_USBH, 0);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 04:25:57 -0500