diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-12-18 17:15:30 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-12-18 17:15:30 -0500 |
commit | fdb0a1a67e131f07a308730c80d07e330211d2e0 (patch) | |
tree | 4fbf35055fc965737c1ffdbcfe98d7ea8335f940 /arch/arm | |
parent | fc0b7a20368193e1f7cf1376624eed419b9c33e6 (diff) | |
parent | 7bb56d01f111890414fbe35412698485b68ed468 (diff) |
Merge branch 'next-merged' of git://aeryn.fluff.org.uk/bjdooks/linux into devel
Diffstat (limited to 'arch/arm')
170 files changed, 10308 insertions, 1151 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d953ed95701e..f1a3b10cfa9e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -518,6 +518,13 @@ config ARCH_S3C2410 | |||
518 | BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or | 518 | BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or |
519 | the Samsung SMDK2410 development board (and derivatives). | 519 | the Samsung SMDK2410 development board (and derivatives). |
520 | 520 | ||
521 | config ARCH_S3C64XX | ||
522 | bool "Samsung S3C64XX" | ||
523 | select GENERIC_GPIO | ||
524 | select HAVE_CLK | ||
525 | help | ||
526 | Samsung S3C64XX series based systems | ||
527 | |||
521 | config ARCH_SHARK | 528 | config ARCH_SHARK |
522 | bool "Shark" | 529 | bool "Shark" |
523 | select CPU_SA110 | 530 | select CPU_SA110 |
@@ -621,6 +628,7 @@ source "arch/arm/mach-orion5x/Kconfig" | |||
621 | source "arch/arm/mach-kirkwood/Kconfig" | 628 | source "arch/arm/mach-kirkwood/Kconfig" |
622 | 629 | ||
623 | source "arch/arm/plat-s3c24xx/Kconfig" | 630 | source "arch/arm/plat-s3c24xx/Kconfig" |
631 | source "arch/arm/plat-s3c64xx/Kconfig" | ||
624 | source "arch/arm/plat-s3c/Kconfig" | 632 | source "arch/arm/plat-s3c/Kconfig" |
625 | 633 | ||
626 | if ARCH_S3C2410 | 634 | if ARCH_S3C2410 |
@@ -632,6 +640,11 @@ source "arch/arm/mach-s3c2442/Kconfig" | |||
632 | source "arch/arm/mach-s3c2443/Kconfig" | 640 | source "arch/arm/mach-s3c2443/Kconfig" |
633 | endif | 641 | endif |
634 | 642 | ||
643 | if ARCH_S3C64XX | ||
644 | source "arch/arm/mach-s3c6400/Kconfig" | ||
645 | source "arch/arm/mach-s3c6410/Kconfig" | ||
646 | endif | ||
647 | |||
635 | source "arch/arm/mach-lh7a40x/Kconfig" | 648 | source "arch/arm/mach-lh7a40x/Kconfig" |
636 | 649 | ||
637 | source "arch/arm/mach-imx/Kconfig" | 650 | source "arch/arm/mach-imx/Kconfig" |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index c8548a187413..24e0f0187697 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
@@ -121,7 +121,10 @@ endif | |||
121 | machine-$(CONFIG_ARCH_OMAP3) := omap2 | 121 | machine-$(CONFIG_ARCH_OMAP3) := omap2 |
122 | plat-$(CONFIG_ARCH_OMAP) := omap | 122 | plat-$(CONFIG_ARCH_OMAP) := omap |
123 | machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 | 123 | machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443 |
124 | machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 | ||
124 | plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c | 125 | plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx s3c |
126 | machine-$(CONFIG_ARCH_S3C64XX) := s3c6400 s3c6410 | ||
127 | plat-$(CONFIG_PLAT_S3C64XX) := s3c64xx s3c | ||
125 | machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x | 128 | machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x |
126 | machine-$(CONFIG_ARCH_VERSATILE) := versatile | 129 | machine-$(CONFIG_ARCH_VERSATILE) := versatile |
127 | machine-$(CONFIG_ARCH_IMX) := imx | 130 | machine-$(CONFIG_ARCH_IMX) := imx |
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index f1e4b8f60cab..ecf0bfbab107 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c | |||
@@ -69,12 +69,12 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, | |||
69 | /* | 69 | /* |
70 | * Make sure we clear all existing interrupts | 70 | * Make sure we clear all existing interrupts |
71 | */ | 71 | */ |
72 | writel(0, base + VIC_VECT_ADDR); | 72 | writel(0, base + VIC_PL190_VECT_ADDR); |
73 | for (i = 0; i < 19; i++) { | 73 | for (i = 0; i < 19; i++) { |
74 | unsigned int value; | 74 | unsigned int value; |
75 | 75 | ||
76 | value = readl(base + VIC_VECT_ADDR); | 76 | value = readl(base + VIC_PL190_VECT_ADDR); |
77 | writel(value, base + VIC_VECT_ADDR); | 77 | writel(value, base + VIC_PL190_VECT_ADDR); |
78 | } | 78 | } |
79 | 79 | ||
80 | for (i = 0; i < 16; i++) { | 80 | for (i = 0; i < 16; i++) { |
@@ -82,7 +82,7 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, | |||
82 | writel(VIC_VECT_CNTL_ENABLE | i, reg); | 82 | writel(VIC_VECT_CNTL_ENABLE | i, reg); |
83 | } | 83 | } |
84 | 84 | ||
85 | writel(32, base + VIC_DEF_VECT_ADDR); | 85 | writel(32, base + VIC_PL190_DEF_VECT_ADDR); |
86 | 86 | ||
87 | for (i = 0; i < 32; i++) { | 87 | for (i = 0; i < 32; i++) { |
88 | unsigned int irq = irq_start + i; | 88 | unsigned int irq = irq_start + i; |
diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig new file mode 100644 index 000000000000..cf3c1b5d7048 --- /dev/null +++ b/arch/arm/configs/s3c6400_defconfig | |||
@@ -0,0 +1,845 @@ | |||
1 | # | ||
2 | # Automatically generated make config: don't edit | ||
3 | # Linux kernel version: 2.6.28-rc3 | ||
4 | # Mon Nov 3 10:10:30 2008 | ||
5 | # | ||
6 | CONFIG_ARM=y | ||
7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
8 | CONFIG_GENERIC_GPIO=y | ||
9 | # CONFIG_GENERIC_TIME is not set | ||
10 | # CONFIG_GENERIC_CLOCKEVENTS is not set | ||
11 | CONFIG_MMU=y | ||
12 | CONFIG_NO_IOPORT=y | ||
13 | CONFIG_GENERIC_HARDIRQS=y | ||
14 | CONFIG_STACKTRACE_SUPPORT=y | ||
15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
16 | CONFIG_LOCKDEP_SUPPORT=y | ||
17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
23 | CONFIG_GENERIC_HWEIGHT=y | ||
24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
25 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
26 | CONFIG_VECTORS_BASE=0xffff0000 | ||
27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
28 | |||
29 | # | ||
30 | # General setup | ||
31 | # | ||
32 | CONFIG_EXPERIMENTAL=y | ||
33 | CONFIG_BROKEN_ON_SMP=y | ||
34 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
35 | CONFIG_LOCALVERSION="" | ||
36 | CONFIG_LOCALVERSION_AUTO=y | ||
37 | CONFIG_SWAP=y | ||
38 | # CONFIG_SYSVIPC is not set | ||
39 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
40 | # CONFIG_IKCONFIG is not set | ||
41 | CONFIG_LOG_BUF_SHIFT=17 | ||
42 | # CONFIG_CGROUPS is not set | ||
43 | # CONFIG_GROUP_SCHED is not set | ||
44 | CONFIG_SYSFS_DEPRECATED=y | ||
45 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
46 | # CONFIG_RELAY is not set | ||
47 | CONFIG_NAMESPACES=y | ||
48 | # CONFIG_UTS_NS is not set | ||
49 | # CONFIG_USER_NS is not set | ||
50 | # CONFIG_PID_NS is not set | ||
51 | CONFIG_BLK_DEV_INITRD=y | ||
52 | CONFIG_INITRAMFS_SOURCE="" | ||
53 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
54 | CONFIG_SYSCTL=y | ||
55 | # CONFIG_EMBEDDED is not set | ||
56 | CONFIG_UID16=y | ||
57 | CONFIG_SYSCTL_SYSCALL=y | ||
58 | CONFIG_KALLSYMS=y | ||
59 | CONFIG_KALLSYMS_ALL=y | ||
60 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
61 | CONFIG_HOTPLUG=y | ||
62 | CONFIG_PRINTK=y | ||
63 | CONFIG_BUG=y | ||
64 | CONFIG_ELF_CORE=y | ||
65 | CONFIG_COMPAT_BRK=y | ||
66 | CONFIG_BASE_FULL=y | ||
67 | CONFIG_FUTEX=y | ||
68 | CONFIG_ANON_INODES=y | ||
69 | CONFIG_EPOLL=y | ||
70 | CONFIG_SIGNALFD=y | ||
71 | CONFIG_TIMERFD=y | ||
72 | CONFIG_EVENTFD=y | ||
73 | CONFIG_SHMEM=y | ||
74 | CONFIG_AIO=y | ||
75 | CONFIG_VM_EVENT_COUNTERS=y | ||
76 | CONFIG_SLUB_DEBUG=y | ||
77 | # CONFIG_SLAB is not set | ||
78 | CONFIG_SLUB=y | ||
79 | # CONFIG_SLOB is not set | ||
80 | # CONFIG_PROFILING is not set | ||
81 | # CONFIG_MARKERS is not set | ||
82 | CONFIG_HAVE_OPROFILE=y | ||
83 | # CONFIG_KPROBES is not set | ||
84 | CONFIG_HAVE_KPROBES=y | ||
85 | CONFIG_HAVE_KRETPROBES=y | ||
86 | CONFIG_HAVE_CLK=y | ||
87 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
88 | CONFIG_SLABINFO=y | ||
89 | CONFIG_RT_MUTEXES=y | ||
90 | # CONFIG_TINY_SHMEM is not set | ||
91 | CONFIG_BASE_SMALL=0 | ||
92 | CONFIG_MODULES=y | ||
93 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
94 | CONFIG_MODULE_UNLOAD=y | ||
95 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
96 | # CONFIG_MODVERSIONS is not set | ||
97 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
98 | CONFIG_KMOD=y | ||
99 | CONFIG_BLOCK=y | ||
100 | CONFIG_LBD=y | ||
101 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
102 | CONFIG_LSF=y | ||
103 | # CONFIG_BLK_DEV_BSG is not set | ||
104 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
105 | |||
106 | # | ||
107 | # IO Schedulers | ||
108 | # | ||
109 | CONFIG_IOSCHED_NOOP=y | ||
110 | CONFIG_IOSCHED_AS=y | ||
111 | CONFIG_IOSCHED_DEADLINE=y | ||
112 | CONFIG_IOSCHED_CFQ=y | ||
113 | # CONFIG_DEFAULT_AS is not set | ||
114 | # CONFIG_DEFAULT_DEADLINE is not set | ||
115 | CONFIG_DEFAULT_CFQ=y | ||
116 | # CONFIG_DEFAULT_NOOP is not set | ||
117 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
118 | CONFIG_CLASSIC_RCU=y | ||
119 | # CONFIG_FREEZER is not set | ||
120 | |||
121 | # | ||
122 | # System Type | ||
123 | # | ||
124 | # CONFIG_ARCH_AAEC2000 is not set | ||
125 | # CONFIG_ARCH_INTEGRATOR is not set | ||
126 | # CONFIG_ARCH_REALVIEW is not set | ||
127 | # CONFIG_ARCH_VERSATILE is not set | ||
128 | # CONFIG_ARCH_AT91 is not set | ||
129 | # CONFIG_ARCH_CLPS7500 is not set | ||
130 | # CONFIG_ARCH_CLPS711X is not set | ||
131 | # CONFIG_ARCH_EBSA110 is not set | ||
132 | # CONFIG_ARCH_EP93XX is not set | ||
133 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
134 | # CONFIG_ARCH_NETX is not set | ||
135 | # CONFIG_ARCH_H720X is not set | ||
136 | # CONFIG_ARCH_IMX is not set | ||
137 | # CONFIG_ARCH_IOP13XX is not set | ||
138 | # CONFIG_ARCH_IOP32X is not set | ||
139 | # CONFIG_ARCH_IOP33X is not set | ||
140 | # CONFIG_ARCH_IXP23XX is not set | ||
141 | # CONFIG_ARCH_IXP2000 is not set | ||
142 | # CONFIG_ARCH_IXP4XX is not set | ||
143 | # CONFIG_ARCH_L7200 is not set | ||
144 | # CONFIG_ARCH_KIRKWOOD is not set | ||
145 | # CONFIG_ARCH_KS8695 is not set | ||
146 | # CONFIG_ARCH_NS9XXX is not set | ||
147 | # CONFIG_ARCH_LOKI is not set | ||
148 | # CONFIG_ARCH_MV78XX0 is not set | ||
149 | # CONFIG_ARCH_MXC is not set | ||
150 | # CONFIG_ARCH_ORION5X is not set | ||
151 | # CONFIG_ARCH_PNX4008 is not set | ||
152 | # CONFIG_ARCH_PXA is not set | ||
153 | # CONFIG_ARCH_RPC is not set | ||
154 | # CONFIG_ARCH_SA1100 is not set | ||
155 | # CONFIG_ARCH_S3C2410 is not set | ||
156 | CONFIG_ARCH_S3C64XX=y | ||
157 | # CONFIG_ARCH_SHARK is not set | ||
158 | # CONFIG_ARCH_LH7A40X is not set | ||
159 | # CONFIG_ARCH_DAVINCI is not set | ||
160 | # CONFIG_ARCH_OMAP is not set | ||
161 | # CONFIG_ARCH_MSM is not set | ||
162 | CONFIG_PLAT_S3C64XX=y | ||
163 | CONFIG_CPU_S3C6400_INIT=y | ||
164 | CONFIG_CPU_S3C6400_CLOCK=y | ||
165 | CONFIG_S3C64XX_SETUP_I2C0=y | ||
166 | CONFIG_S3C64XX_SETUP_I2C1=y | ||
167 | CONFIG_PLAT_S3C=y | ||
168 | |||
169 | # | ||
170 | # Boot options | ||
171 | # | ||
172 | CONFIG_S3C_BOOT_ERROR_RESET=y | ||
173 | |||
174 | # | ||
175 | # Power management | ||
176 | # | ||
177 | CONFIG_S3C_LOWLEVEL_UART_PORT=0 | ||
178 | CONFIG_S3C_GPIO_SPACE=0 | ||
179 | CONFIG_S3C_GPIO_TRACK=y | ||
180 | CONFIG_S3C_GPIO_PULL_UPDOWN=y | ||
181 | CONFIG_S3C_GPIO_CFG_S3C24XX=y | ||
182 | CONFIG_S3C_GPIO_CFG_S3C64XX=y | ||
183 | CONFIG_S3C_DEV_HSMMC=y | ||
184 | CONFIG_S3C_DEV_HSMMC1=y | ||
185 | CONFIG_S3C_DEV_I2C1=y | ||
186 | CONFIG_CPU_S3C6410=y | ||
187 | CONFIG_S3C6410_SETUP_SDHCI=y | ||
188 | CONFIG_MACH_SMDK6410=y | ||
189 | CONFIG_SMDK6410_SD_CH0=y | ||
190 | # CONFIG_SMDK6410_SD_CH1 is not set | ||
191 | |||
192 | # | ||
193 | # Processor Type | ||
194 | # | ||
195 | CONFIG_CPU_32=y | ||
196 | CONFIG_CPU_V6=y | ||
197 | CONFIG_CPU_32v6K=y | ||
198 | CONFIG_CPU_32v6=y | ||
199 | CONFIG_CPU_ABRT_EV6=y | ||
200 | CONFIG_CPU_PABRT_NOIFAR=y | ||
201 | CONFIG_CPU_CACHE_V6=y | ||
202 | CONFIG_CPU_CACHE_VIPT=y | ||
203 | CONFIG_CPU_COPY_V6=y | ||
204 | CONFIG_CPU_TLB_V6=y | ||
205 | CONFIG_CPU_HAS_ASID=y | ||
206 | CONFIG_CPU_CP15=y | ||
207 | CONFIG_CPU_CP15_MMU=y | ||
208 | |||
209 | # | ||
210 | # Processor Features | ||
211 | # | ||
212 | CONFIG_ARM_THUMB=y | ||
213 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
214 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
215 | # CONFIG_CPU_BPREDICT_DISABLE is not set | ||
216 | # CONFIG_OUTER_CACHE is not set | ||
217 | CONFIG_ARM_VIC=y | ||
218 | |||
219 | # | ||
220 | # Bus support | ||
221 | # | ||
222 | # CONFIG_PCI_SYSCALL is not set | ||
223 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
224 | # CONFIG_PCCARD is not set | ||
225 | |||
226 | # | ||
227 | # Kernel Features | ||
228 | # | ||
229 | CONFIG_VMSPLIT_3G=y | ||
230 | # CONFIG_VMSPLIT_2G is not set | ||
231 | # CONFIG_VMSPLIT_1G is not set | ||
232 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
233 | # CONFIG_PREEMPT is not set | ||
234 | CONFIG_HZ=100 | ||
235 | CONFIG_AEABI=y | ||
236 | CONFIG_OABI_COMPAT=y | ||
237 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
238 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
239 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
240 | CONFIG_SELECT_MEMORY_MODEL=y | ||
241 | CONFIG_FLATMEM_MANUAL=y | ||
242 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
243 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
244 | CONFIG_FLATMEM=y | ||
245 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
246 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
247 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
248 | # CONFIG_RESOURCES_64BIT is not set | ||
249 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
250 | CONFIG_ZONE_DMA_FLAG=0 | ||
251 | CONFIG_VIRT_TO_BUS=y | ||
252 | CONFIG_UNEVICTABLE_LRU=y | ||
253 | CONFIG_ALIGNMENT_TRAP=y | ||
254 | |||
255 | # | ||
256 | # Boot options | ||
257 | # | ||
258 | CONFIG_ZBOOT_ROM_TEXT=0 | ||
259 | CONFIG_ZBOOT_ROM_BSS=0 | ||
260 | CONFIG_CMDLINE="console=ttySAC0,115200 root=/dev/ram init=/bin/bash initrd=0x51000000,4M" | ||
261 | # CONFIG_XIP_KERNEL is not set | ||
262 | # CONFIG_KEXEC is not set | ||
263 | |||
264 | # | ||
265 | # CPU Power Management | ||
266 | # | ||
267 | # CONFIG_CPU_IDLE is not set | ||
268 | |||
269 | # | ||
270 | # Floating point emulation | ||
271 | # | ||
272 | |||
273 | # | ||
274 | # At least one emulation must be selected | ||
275 | # | ||
276 | # CONFIG_FPE_NWFPE is not set | ||
277 | # CONFIG_FPE_FASTFPE is not set | ||
278 | CONFIG_VFP=y | ||
279 | |||
280 | # | ||
281 | # Userspace binary formats | ||
282 | # | ||
283 | CONFIG_BINFMT_ELF=y | ||
284 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
285 | CONFIG_HAVE_AOUT=y | ||
286 | # CONFIG_BINFMT_AOUT is not set | ||
287 | # CONFIG_BINFMT_MISC is not set | ||
288 | |||
289 | # | ||
290 | # Power management options | ||
291 | # | ||
292 | # CONFIG_PM is not set | ||
293 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
294 | # CONFIG_NET is not set | ||
295 | |||
296 | # | ||
297 | # Device Drivers | ||
298 | # | ||
299 | |||
300 | # | ||
301 | # Generic Driver Options | ||
302 | # | ||
303 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
304 | CONFIG_STANDALONE=y | ||
305 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
306 | CONFIG_FW_LOADER=y | ||
307 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
308 | CONFIG_EXTRA_FIRMWARE="" | ||
309 | # CONFIG_DEBUG_DRIVER is not set | ||
310 | # CONFIG_DEBUG_DEVRES is not set | ||
311 | # CONFIG_SYS_HYPERVISOR is not set | ||
312 | # CONFIG_MTD is not set | ||
313 | # CONFIG_PARPORT is not set | ||
314 | CONFIG_BLK_DEV=y | ||
315 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
316 | CONFIG_BLK_DEV_LOOP=y | ||
317 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
318 | CONFIG_BLK_DEV_RAM=y | ||
319 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
320 | CONFIG_BLK_DEV_RAM_SIZE=4096 | ||
321 | # CONFIG_BLK_DEV_XIP is not set | ||
322 | # CONFIG_CDROM_PKTCDVD is not set | ||
323 | CONFIG_MISC_DEVICES=y | ||
324 | # CONFIG_EEPROM_93CX6 is not set | ||
325 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
326 | CONFIG_HAVE_IDE=y | ||
327 | # CONFIG_IDE is not set | ||
328 | |||
329 | # | ||
330 | # SCSI device support | ||
331 | # | ||
332 | # CONFIG_RAID_ATTRS is not set | ||
333 | # CONFIG_SCSI is not set | ||
334 | # CONFIG_SCSI_DMA is not set | ||
335 | # CONFIG_SCSI_NETLINK is not set | ||
336 | # CONFIG_ATA is not set | ||
337 | # CONFIG_MD is not set | ||
338 | |||
339 | # | ||
340 | # Input device support | ||
341 | # | ||
342 | CONFIG_INPUT=y | ||
343 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
344 | # CONFIG_INPUT_POLLDEV is not set | ||
345 | |||
346 | # | ||
347 | # Userland interfaces | ||
348 | # | ||
349 | CONFIG_INPUT_MOUSEDEV=y | ||
350 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
351 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
352 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
353 | # CONFIG_INPUT_JOYDEV is not set | ||
354 | # CONFIG_INPUT_EVDEV is not set | ||
355 | # CONFIG_INPUT_EVBUG is not set | ||
356 | |||
357 | # | ||
358 | # Input Device Drivers | ||
359 | # | ||
360 | CONFIG_INPUT_KEYBOARD=y | ||
361 | CONFIG_KEYBOARD_ATKBD=y | ||
362 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
363 | # CONFIG_KEYBOARD_LKKBD is not set | ||
364 | # CONFIG_KEYBOARD_XTKBD is not set | ||
365 | # CONFIG_KEYBOARD_NEWTON is not set | ||
366 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
367 | # CONFIG_KEYBOARD_GPIO is not set | ||
368 | CONFIG_INPUT_MOUSE=y | ||
369 | CONFIG_MOUSE_PS2=y | ||
370 | CONFIG_MOUSE_PS2_ALPS=y | ||
371 | CONFIG_MOUSE_PS2_LOGIPS2PP=y | ||
372 | CONFIG_MOUSE_PS2_SYNAPTICS=y | ||
373 | CONFIG_MOUSE_PS2_LIFEBOOK=y | ||
374 | CONFIG_MOUSE_PS2_TRACKPOINT=y | ||
375 | # CONFIG_MOUSE_PS2_ELANTECH is not set | ||
376 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set | ||
377 | # CONFIG_MOUSE_SERIAL is not set | ||
378 | # CONFIG_MOUSE_APPLETOUCH is not set | ||
379 | # CONFIG_MOUSE_BCM5974 is not set | ||
380 | # CONFIG_MOUSE_VSXXXAA is not set | ||
381 | # CONFIG_MOUSE_GPIO is not set | ||
382 | # CONFIG_INPUT_JOYSTICK is not set | ||
383 | # CONFIG_INPUT_TABLET is not set | ||
384 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
385 | # CONFIG_INPUT_MISC is not set | ||
386 | |||
387 | # | ||
388 | # Hardware I/O ports | ||
389 | # | ||
390 | CONFIG_SERIO=y | ||
391 | CONFIG_SERIO_SERPORT=y | ||
392 | CONFIG_SERIO_LIBPS2=y | ||
393 | # CONFIG_SERIO_RAW is not set | ||
394 | # CONFIG_GAMEPORT is not set | ||
395 | |||
396 | # | ||
397 | # Character devices | ||
398 | # | ||
399 | CONFIG_VT=y | ||
400 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
401 | CONFIG_VT_CONSOLE=y | ||
402 | CONFIG_HW_CONSOLE=y | ||
403 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
404 | CONFIG_DEVKMEM=y | ||
405 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
406 | |||
407 | # | ||
408 | # Serial drivers | ||
409 | # | ||
410 | CONFIG_SERIAL_8250=y | ||
411 | # CONFIG_SERIAL_8250_CONSOLE is not set | ||
412 | CONFIG_SERIAL_8250_NR_UARTS=4 | ||
413 | CONFIG_SERIAL_8250_RUNTIME_UARTS=4 | ||
414 | # CONFIG_SERIAL_8250_EXTENDED is not set | ||
415 | |||
416 | # | ||
417 | # Non-8250 serial port support | ||
418 | # | ||
419 | CONFIG_SERIAL_SAMSUNG=y | ||
420 | CONFIG_SERIAL_SAMSUNG_UARTS=4 | ||
421 | # CONFIG_SERIAL_SAMSUNG_DEBUG is not set | ||
422 | CONFIG_SERIAL_SAMSUNG_CONSOLE=y | ||
423 | CONFIG_SERIAL_S3C6400=y | ||
424 | CONFIG_SERIAL_CORE=y | ||
425 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
426 | CONFIG_UNIX98_PTYS=y | ||
427 | CONFIG_LEGACY_PTYS=y | ||
428 | CONFIG_LEGACY_PTY_COUNT=256 | ||
429 | # CONFIG_IPMI_HANDLER is not set | ||
430 | CONFIG_HW_RANDOM=y | ||
431 | # CONFIG_NVRAM is not set | ||
432 | # CONFIG_R3964 is not set | ||
433 | # CONFIG_RAW_DRIVER is not set | ||
434 | # CONFIG_TCG_TPM is not set | ||
435 | CONFIG_I2C=y | ||
436 | CONFIG_I2C_BOARDINFO=y | ||
437 | CONFIG_I2C_CHARDEV=y | ||
438 | CONFIG_I2C_HELPER_AUTO=y | ||
439 | |||
440 | # | ||
441 | # I2C Hardware Bus support | ||
442 | # | ||
443 | |||
444 | # | ||
445 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
446 | # | ||
447 | # CONFIG_I2C_GPIO is not set | ||
448 | # CONFIG_I2C_OCORES is not set | ||
449 | CONFIG_I2C_S3C2410=y | ||
450 | # CONFIG_I2C_SIMTEC is not set | ||
451 | |||
452 | # | ||
453 | # External I2C/SMBus adapter drivers | ||
454 | # | ||
455 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
456 | # CONFIG_I2C_TAOS_EVM is not set | ||
457 | |||
458 | # | ||
459 | # Other I2C/SMBus bus drivers | ||
460 | # | ||
461 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
462 | # CONFIG_I2C_STUB is not set | ||
463 | |||
464 | # | ||
465 | # Miscellaneous I2C Chip support | ||
466 | # | ||
467 | # CONFIG_DS1682 is not set | ||
468 | CONFIG_AT24=y | ||
469 | # CONFIG_SENSORS_EEPROM is not set | ||
470 | # CONFIG_SENSORS_PCF8574 is not set | ||
471 | # CONFIG_PCF8575 is not set | ||
472 | # CONFIG_SENSORS_PCA9539 is not set | ||
473 | # CONFIG_SENSORS_PCF8591 is not set | ||
474 | # CONFIG_TPS65010 is not set | ||
475 | # CONFIG_SENSORS_MAX6875 is not set | ||
476 | # CONFIG_SENSORS_TSL2550 is not set | ||
477 | # CONFIG_I2C_DEBUG_CORE is not set | ||
478 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
479 | # CONFIG_I2C_DEBUG_BUS is not set | ||
480 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
481 | # CONFIG_SPI is not set | ||
482 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
483 | CONFIG_GPIOLIB=y | ||
484 | # CONFIG_DEBUG_GPIO is not set | ||
485 | # CONFIG_GPIO_SYSFS is not set | ||
486 | |||
487 | # | ||
488 | # I2C GPIO expanders: | ||
489 | # | ||
490 | # CONFIG_GPIO_MAX732X is not set | ||
491 | # CONFIG_GPIO_PCA953X is not set | ||
492 | # CONFIG_GPIO_PCF857X is not set | ||
493 | |||
494 | # | ||
495 | # PCI GPIO expanders: | ||
496 | # | ||
497 | |||
498 | # | ||
499 | # SPI GPIO expanders: | ||
500 | # | ||
501 | # CONFIG_W1 is not set | ||
502 | # CONFIG_POWER_SUPPLY is not set | ||
503 | CONFIG_HWMON=y | ||
504 | # CONFIG_HWMON_VID is not set | ||
505 | # CONFIG_SENSORS_AD7414 is not set | ||
506 | # CONFIG_SENSORS_AD7418 is not set | ||
507 | # CONFIG_SENSORS_ADM1021 is not set | ||
508 | # CONFIG_SENSORS_ADM1025 is not set | ||
509 | # CONFIG_SENSORS_ADM1026 is not set | ||
510 | # CONFIG_SENSORS_ADM1029 is not set | ||
511 | # CONFIG_SENSORS_ADM1031 is not set | ||
512 | # CONFIG_SENSORS_ADM9240 is not set | ||
513 | # CONFIG_SENSORS_ADT7470 is not set | ||
514 | # CONFIG_SENSORS_ADT7473 is not set | ||
515 | # CONFIG_SENSORS_ATXP1 is not set | ||
516 | # CONFIG_SENSORS_DS1621 is not set | ||
517 | # CONFIG_SENSORS_F71805F is not set | ||
518 | # CONFIG_SENSORS_F71882FG is not set | ||
519 | # CONFIG_SENSORS_F75375S is not set | ||
520 | # CONFIG_SENSORS_GL518SM is not set | ||
521 | # CONFIG_SENSORS_GL520SM is not set | ||
522 | # CONFIG_SENSORS_IT87 is not set | ||
523 | # CONFIG_SENSORS_LM63 is not set | ||
524 | # CONFIG_SENSORS_LM75 is not set | ||
525 | # CONFIG_SENSORS_LM77 is not set | ||
526 | # CONFIG_SENSORS_LM78 is not set | ||
527 | # CONFIG_SENSORS_LM80 is not set | ||
528 | # CONFIG_SENSORS_LM83 is not set | ||
529 | # CONFIG_SENSORS_LM85 is not set | ||
530 | # CONFIG_SENSORS_LM87 is not set | ||
531 | # CONFIG_SENSORS_LM90 is not set | ||
532 | # CONFIG_SENSORS_LM92 is not set | ||
533 | # CONFIG_SENSORS_LM93 is not set | ||
534 | # CONFIG_SENSORS_MAX1619 is not set | ||
535 | # CONFIG_SENSORS_MAX6650 is not set | ||
536 | # CONFIG_SENSORS_PC87360 is not set | ||
537 | # CONFIG_SENSORS_PC87427 is not set | ||
538 | # CONFIG_SENSORS_DME1737 is not set | ||
539 | # CONFIG_SENSORS_SMSC47M1 is not set | ||
540 | # CONFIG_SENSORS_SMSC47M192 is not set | ||
541 | # CONFIG_SENSORS_SMSC47B397 is not set | ||
542 | # CONFIG_SENSORS_ADS7828 is not set | ||
543 | # CONFIG_SENSORS_THMC50 is not set | ||
544 | # CONFIG_SENSORS_VT1211 is not set | ||
545 | # CONFIG_SENSORS_W83781D is not set | ||
546 | # CONFIG_SENSORS_W83791D is not set | ||
547 | # CONFIG_SENSORS_W83792D is not set | ||
548 | # CONFIG_SENSORS_W83793 is not set | ||
549 | # CONFIG_SENSORS_W83L785TS is not set | ||
550 | # CONFIG_SENSORS_W83L786NG is not set | ||
551 | # CONFIG_SENSORS_W83627HF is not set | ||
552 | # CONFIG_SENSORS_W83627EHF is not set | ||
553 | # CONFIG_HWMON_DEBUG_CHIP is not set | ||
554 | # CONFIG_THERMAL is not set | ||
555 | # CONFIG_THERMAL_HWMON is not set | ||
556 | # CONFIG_WATCHDOG is not set | ||
557 | |||
558 | # | ||
559 | # Sonics Silicon Backplane | ||
560 | # | ||
561 | CONFIG_SSB_POSSIBLE=y | ||
562 | # CONFIG_SSB is not set | ||
563 | |||
564 | # | ||
565 | # Multifunction device drivers | ||
566 | # | ||
567 | # CONFIG_MFD_CORE is not set | ||
568 | # CONFIG_MFD_SM501 is not set | ||
569 | # CONFIG_MFD_ASIC3 is not set | ||
570 | # CONFIG_HTC_EGPIO is not set | ||
571 | # CONFIG_HTC_PASIC3 is not set | ||
572 | # CONFIG_MFD_TMIO is not set | ||
573 | # CONFIG_MFD_T7L66XB is not set | ||
574 | # CONFIG_MFD_TC6387XB is not set | ||
575 | # CONFIG_MFD_TC6393XB is not set | ||
576 | # CONFIG_PMIC_DA903X is not set | ||
577 | # CONFIG_MFD_WM8400 is not set | ||
578 | # CONFIG_MFD_WM8350_I2C is not set | ||
579 | |||
580 | # | ||
581 | # Multimedia devices | ||
582 | # | ||
583 | |||
584 | # | ||
585 | # Multimedia core support | ||
586 | # | ||
587 | # CONFIG_VIDEO_DEV is not set | ||
588 | # CONFIG_VIDEO_MEDIA is not set | ||
589 | |||
590 | # | ||
591 | # Multimedia drivers | ||
592 | # | ||
593 | # CONFIG_DAB is not set | ||
594 | |||
595 | # | ||
596 | # Graphics support | ||
597 | # | ||
598 | # CONFIG_VGASTATE is not set | ||
599 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
600 | # CONFIG_FB is not set | ||
601 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
602 | |||
603 | # | ||
604 | # Display device support | ||
605 | # | ||
606 | # CONFIG_DISPLAY_SUPPORT is not set | ||
607 | |||
608 | # | ||
609 | # Console display driver support | ||
610 | # | ||
611 | # CONFIG_VGA_CONSOLE is not set | ||
612 | CONFIG_DUMMY_CONSOLE=y | ||
613 | # CONFIG_SOUND is not set | ||
614 | CONFIG_HID_SUPPORT=y | ||
615 | CONFIG_HID=y | ||
616 | CONFIG_HID_DEBUG=y | ||
617 | # CONFIG_HIDRAW is not set | ||
618 | # CONFIG_HID_PID is not set | ||
619 | |||
620 | # | ||
621 | # Special HID drivers | ||
622 | # | ||
623 | # CONFIG_HID_COMPAT is not set | ||
624 | CONFIG_USB_SUPPORT=y | ||
625 | CONFIG_USB_ARCH_HAS_HCD=y | ||
626 | # CONFIG_USB_ARCH_HAS_OHCI is not set | ||
627 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
628 | # CONFIG_USB is not set | ||
629 | |||
630 | # | ||
631 | # Enable Host or Gadget support to see Inventra options | ||
632 | # | ||
633 | |||
634 | # | ||
635 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | ||
636 | # | ||
637 | # CONFIG_USB_GADGET is not set | ||
638 | CONFIG_MMC=y | ||
639 | CONFIG_MMC_DEBUG=y | ||
640 | CONFIG_MMC_UNSAFE_RESUME=y | ||
641 | |||
642 | # | ||
643 | # MMC/SD/SDIO Card Drivers | ||
644 | # | ||
645 | CONFIG_MMC_BLOCK=y | ||
646 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
647 | CONFIG_SDIO_UART=y | ||
648 | # CONFIG_MMC_TEST is not set | ||
649 | |||
650 | # | ||
651 | # MMC/SD/SDIO Host Controller Drivers | ||
652 | # | ||
653 | CONFIG_MMC_SDHCI=y | ||
654 | CONFIG_MMC_SDHCI_S3C=y | ||
655 | # CONFIG_MEMSTICK is not set | ||
656 | # CONFIG_ACCESSIBILITY is not set | ||
657 | # CONFIG_NEW_LEDS is not set | ||
658 | CONFIG_RTC_LIB=y | ||
659 | # CONFIG_RTC_CLASS is not set | ||
660 | # CONFIG_DMADEVICES is not set | ||
661 | |||
662 | # | ||
663 | # Voltage and Current regulators | ||
664 | # | ||
665 | # CONFIG_REGULATOR is not set | ||
666 | # CONFIG_REGULATOR_FIXED_VOLTAGE is not set | ||
667 | # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set | ||
668 | # CONFIG_REGULATOR_BQ24022 is not set | ||
669 | # CONFIG_UIO is not set | ||
670 | |||
671 | # | ||
672 | # File systems | ||
673 | # | ||
674 | CONFIG_EXT2_FS=y | ||
675 | # CONFIG_EXT2_FS_XATTR is not set | ||
676 | # CONFIG_EXT2_FS_XIP is not set | ||
677 | CONFIG_EXT3_FS=y | ||
678 | CONFIG_EXT3_FS_XATTR=y | ||
679 | CONFIG_EXT3_FS_POSIX_ACL=y | ||
680 | CONFIG_EXT3_FS_SECURITY=y | ||
681 | # CONFIG_EXT4_FS is not set | ||
682 | CONFIG_JBD=y | ||
683 | CONFIG_FS_MBCACHE=y | ||
684 | # CONFIG_REISERFS_FS is not set | ||
685 | # CONFIG_JFS_FS is not set | ||
686 | CONFIG_FS_POSIX_ACL=y | ||
687 | CONFIG_FILE_LOCKING=y | ||
688 | # CONFIG_XFS_FS is not set | ||
689 | # CONFIG_GFS2_FS is not set | ||
690 | CONFIG_DNOTIFY=y | ||
691 | CONFIG_INOTIFY=y | ||
692 | CONFIG_INOTIFY_USER=y | ||
693 | # CONFIG_QUOTA is not set | ||
694 | # CONFIG_AUTOFS_FS is not set | ||
695 | # CONFIG_AUTOFS4_FS is not set | ||
696 | # CONFIG_FUSE_FS is not set | ||
697 | CONFIG_GENERIC_ACL=y | ||
698 | |||
699 | # | ||
700 | # CD-ROM/DVD Filesystems | ||
701 | # | ||
702 | # CONFIG_ISO9660_FS is not set | ||
703 | # CONFIG_UDF_FS is not set | ||
704 | |||
705 | # | ||
706 | # DOS/FAT/NT Filesystems | ||
707 | # | ||
708 | # CONFIG_MSDOS_FS is not set | ||
709 | # CONFIG_VFAT_FS is not set | ||
710 | # CONFIG_NTFS_FS is not set | ||
711 | |||
712 | # | ||
713 | # Pseudo filesystems | ||
714 | # | ||
715 | CONFIG_PROC_FS=y | ||
716 | CONFIG_PROC_SYSCTL=y | ||
717 | CONFIG_PROC_PAGE_MONITOR=y | ||
718 | CONFIG_SYSFS=y | ||
719 | CONFIG_TMPFS=y | ||
720 | CONFIG_TMPFS_POSIX_ACL=y | ||
721 | # CONFIG_HUGETLB_PAGE is not set | ||
722 | # CONFIG_CONFIGFS_FS is not set | ||
723 | |||
724 | # | ||
725 | # Miscellaneous filesystems | ||
726 | # | ||
727 | # CONFIG_ADFS_FS is not set | ||
728 | # CONFIG_AFFS_FS is not set | ||
729 | # CONFIG_HFS_FS is not set | ||
730 | # CONFIG_HFSPLUS_FS is not set | ||
731 | # CONFIG_BEFS_FS is not set | ||
732 | # CONFIG_BFS_FS is not set | ||
733 | # CONFIG_EFS_FS is not set | ||
734 | CONFIG_CRAMFS=y | ||
735 | # CONFIG_VXFS_FS is not set | ||
736 | # CONFIG_MINIX_FS is not set | ||
737 | # CONFIG_OMFS_FS is not set | ||
738 | # CONFIG_HPFS_FS is not set | ||
739 | # CONFIG_QNX4FS_FS is not set | ||
740 | CONFIG_ROMFS_FS=y | ||
741 | # CONFIG_SYSV_FS is not set | ||
742 | # CONFIG_UFS_FS is not set | ||
743 | |||
744 | # | ||
745 | # Partition Types | ||
746 | # | ||
747 | # CONFIG_PARTITION_ADVANCED is not set | ||
748 | CONFIG_MSDOS_PARTITION=y | ||
749 | # CONFIG_NLS is not set | ||
750 | |||
751 | # | ||
752 | # Kernel hacking | ||
753 | # | ||
754 | # CONFIG_PRINTK_TIME is not set | ||
755 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
756 | CONFIG_ENABLE_MUST_CHECK=y | ||
757 | CONFIG_FRAME_WARN=1024 | ||
758 | CONFIG_MAGIC_SYSRQ=y | ||
759 | # CONFIG_UNUSED_SYMBOLS is not set | ||
760 | # CONFIG_DEBUG_FS is not set | ||
761 | # CONFIG_HEADERS_CHECK is not set | ||
762 | CONFIG_DEBUG_KERNEL=y | ||
763 | # CONFIG_DEBUG_SHIRQ is not set | ||
764 | CONFIG_DETECT_SOFTLOCKUP=y | ||
765 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
766 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
767 | CONFIG_SCHED_DEBUG=y | ||
768 | # CONFIG_SCHEDSTATS is not set | ||
769 | # CONFIG_TIMER_STATS is not set | ||
770 | # CONFIG_DEBUG_OBJECTS is not set | ||
771 | # CONFIG_SLUB_DEBUG_ON is not set | ||
772 | # CONFIG_SLUB_STATS is not set | ||
773 | CONFIG_DEBUG_RT_MUTEXES=y | ||
774 | CONFIG_DEBUG_PI_LIST=y | ||
775 | # CONFIG_RT_MUTEX_TESTER is not set | ||
776 | CONFIG_DEBUG_SPINLOCK=y | ||
777 | CONFIG_DEBUG_MUTEXES=y | ||
778 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
779 | # CONFIG_PROVE_LOCKING is not set | ||
780 | # CONFIG_LOCK_STAT is not set | ||
781 | CONFIG_DEBUG_SPINLOCK_SLEEP=y | ||
782 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
783 | # CONFIG_DEBUG_KOBJECT is not set | ||
784 | CONFIG_DEBUG_BUGVERBOSE=y | ||
785 | CONFIG_DEBUG_INFO=y | ||
786 | # CONFIG_DEBUG_VM is not set | ||
787 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
788 | CONFIG_DEBUG_MEMORY_INIT=y | ||
789 | # CONFIG_DEBUG_LIST is not set | ||
790 | # CONFIG_DEBUG_SG is not set | ||
791 | CONFIG_FRAME_POINTER=y | ||
792 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
793 | # CONFIG_RCU_TORTURE_TEST is not set | ||
794 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
795 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
796 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
797 | # CONFIG_FAULT_INJECTION is not set | ||
798 | # CONFIG_LATENCYTOP is not set | ||
799 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
800 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
801 | |||
802 | # | ||
803 | # Tracers | ||
804 | # | ||
805 | # CONFIG_FUNCTION_TRACER is not set | ||
806 | # CONFIG_SCHED_TRACER is not set | ||
807 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
808 | # CONFIG_BOOT_TRACER is not set | ||
809 | # CONFIG_STACK_TRACER is not set | ||
810 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
811 | # CONFIG_SAMPLES is not set | ||
812 | CONFIG_HAVE_ARCH_KGDB=y | ||
813 | # CONFIG_KGDB is not set | ||
814 | CONFIG_DEBUG_USER=y | ||
815 | CONFIG_DEBUG_ERRORS=y | ||
816 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
817 | CONFIG_DEBUG_LL=y | ||
818 | # CONFIG_DEBUG_ICEDCC is not set | ||
819 | CONFIG_DEBUG_S3C_PORT=y | ||
820 | CONFIG_DEBUG_S3C_UART=0 | ||
821 | |||
822 | # | ||
823 | # Security options | ||
824 | # | ||
825 | # CONFIG_KEYS is not set | ||
826 | # CONFIG_SECURITY is not set | ||
827 | # CONFIG_SECURITYFS is not set | ||
828 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
829 | # CONFIG_CRYPTO is not set | ||
830 | |||
831 | # | ||
832 | # Library routines | ||
833 | # | ||
834 | CONFIG_BITREVERSE=y | ||
835 | # CONFIG_CRC_CCITT is not set | ||
836 | # CONFIG_CRC16 is not set | ||
837 | # CONFIG_CRC_T10DIF is not set | ||
838 | # CONFIG_CRC_ITU_T is not set | ||
839 | CONFIG_CRC32=y | ||
840 | # CONFIG_CRC7 is not set | ||
841 | # CONFIG_LIBCRC32C is not set | ||
842 | CONFIG_ZLIB_INFLATE=y | ||
843 | CONFIG_PLIST=y | ||
844 | CONFIG_HAS_IOMEM=y | ||
845 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h index 263f2c362a30..f87328d4a180 100644 --- a/arch/arm/include/asm/hardware/vic.h +++ b/arch/arm/include/asm/hardware/vic.h | |||
@@ -29,15 +29,17 @@ | |||
29 | #define VIC_INT_SOFT 0x18 | 29 | #define VIC_INT_SOFT 0x18 |
30 | #define VIC_INT_SOFT_CLEAR 0x1c | 30 | #define VIC_INT_SOFT_CLEAR 0x1c |
31 | #define VIC_PROTECT 0x20 | 31 | #define VIC_PROTECT 0x20 |
32 | #define VIC_VECT_ADDR 0x30 | 32 | #define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */ |
33 | #define VIC_DEF_VECT_ADDR 0x34 | 33 | #define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */ |
34 | 34 | ||
35 | #define VIC_VECT_ADDR0 0x100 /* 0 to 15 */ | 35 | #define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */ |
36 | #define VIC_VECT_CNTL0 0x200 /* 0 to 15 */ | 36 | #define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */ |
37 | #define VIC_ITCR 0x300 /* VIC test control register */ | 37 | #define VIC_ITCR 0x300 /* VIC test control register */ |
38 | 38 | ||
39 | #define VIC_VECT_CNTL_ENABLE (1 << 5) | 39 | #define VIC_VECT_CNTL_ENABLE (1 << 5) |
40 | 40 | ||
41 | #define VIC_PL192_VECT_ADDR 0xF00 | ||
42 | |||
41 | #ifndef __ASSEMBLY__ | 43 | #ifndef __ASSEMBLY__ |
42 | void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources); | 44 | void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources); |
43 | #endif | 45 | #endif |
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index 7315569fbfd7..63a30d1dd425 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig | |||
@@ -33,11 +33,6 @@ config S3C2410_GPIO | |||
33 | help | 33 | help |
34 | GPIO code for S3C2410 and similar processors | 34 | GPIO code for S3C2410 and similar processors |
35 | 35 | ||
36 | config S3C2410_CLOCK | ||
37 | bool | ||
38 | help | ||
39 | Clock code for the S3C2410, and similar processors | ||
40 | |||
41 | config SIMTEC_NOR | 36 | config SIMTEC_NOR |
42 | bool | 37 | bool |
43 | help | 38 | help |
@@ -85,6 +80,7 @@ config ARCH_BAST | |||
85 | select PM_SIMTEC if PM | 80 | select PM_SIMTEC if PM |
86 | select SIMTEC_NOR | 81 | select SIMTEC_NOR |
87 | select MACH_BAST_IDE | 82 | select MACH_BAST_IDE |
83 | select S3C24XX_DCLK | ||
88 | select ISA | 84 | select ISA |
89 | help | 85 | help |
90 | Say Y here if you are using the Simtec Electronics EB2410ITX | 86 | Say Y here if you are using the Simtec Electronics EB2410ITX |
@@ -122,6 +118,7 @@ config MACH_TCT_HAMMER | |||
122 | config MACH_VR1000 | 118 | config MACH_VR1000 |
123 | bool "Thorcom VR1000" | 119 | bool "Thorcom VR1000" |
124 | select PM_SIMTEC if PM | 120 | select PM_SIMTEC if PM |
121 | select S3C24XX_DCLK | ||
125 | select SIMTEC_NOR | 122 | select SIMTEC_NOR |
126 | select MACH_BAST_IDE | 123 | select MACH_BAST_IDE |
127 | select CPU_S3C2410 | 124 | select CPU_S3C2410 |
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index 00f31f8c4e78..fca02f82711c 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile | |||
@@ -15,7 +15,6 @@ obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o | |||
15 | obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o | 15 | obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o |
16 | obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o | 16 | obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o |
17 | obj-$(CONFIG_S3C2410_GPIO) += gpio.o | 17 | obj-$(CONFIG_S3C2410_GPIO) += gpio.o |
18 | obj-$(CONFIG_S3C2410_CLOCK) += clock.o | ||
19 | 18 | ||
20 | # Machine support | 19 | # Machine support |
21 | 20 | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-core.h b/arch/arm/mach-s3c2410/include/mach/gpio-core.h new file mode 100644 index 000000000000..6c9fbb99ef14 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/gpio-core.h | |||
@@ -0,0 +1,34 @@ | |||
1 | /* arch/arm/mach-s3c24100/include/mach/gpio-core.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C2410 - GPIO core support | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ARCH_GPIO_CORE_H | ||
16 | #define __ASM_ARCH_GPIO_CORE_H __FILE__ | ||
17 | |||
18 | #include <plat/gpio-core.h> | ||
19 | #include <mach/regs-gpio.h> | ||
20 | |||
21 | extern struct s3c_gpio_chip s3c24xx_gpios[]; | ||
22 | |||
23 | static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin) | ||
24 | { | ||
25 | struct s3c_gpio_chip *chip; | ||
26 | |||
27 | if (pin > S3C2410_GPG10) | ||
28 | return NULL; | ||
29 | |||
30 | chip = &s3c24xx_gpios[pin/32]; | ||
31 | return (S3C2410_GPIO_OFFSET(pin) > chip->chip.ngpio) ? chip : NULL; | ||
32 | } | ||
33 | |||
34 | #endif /* __ASM_ARCH_GPIO_CORE_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h index 3b52b86498a6..e0349af8a483 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio.h | |||
@@ -15,4 +15,10 @@ | |||
15 | #define gpio_set_value __gpio_set_value | 15 | #define gpio_set_value __gpio_set_value |
16 | #define gpio_cansleep __gpio_cansleep | 16 | #define gpio_cansleep __gpio_cansleep |
17 | 17 | ||
18 | /* some boards require extra gpio capacity to support external | ||
19 | * devices that need GPIO. | ||
20 | */ | ||
21 | |||
22 | #define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA) | ||
23 | |||
18 | #include <asm-generic/gpio.h> | 24 | #include <asm-generic/gpio.h> |
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h index 950c71bf1489..9565903d490b 100644 --- a/arch/arm/mach-s3c2410/include/mach/irqs.h +++ b/arch/arm/mach-s3c2410/include/mach/irqs.h | |||
@@ -134,6 +134,8 @@ | |||
134 | #define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ | 134 | #define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */ |
135 | #define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ | 135 | #define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */ |
136 | 136 | ||
137 | #define IRQ_HSMMC0 IRQ_S3C2443_HSMMC | ||
138 | |||
137 | #define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) | 139 | #define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14) |
138 | #define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) | 140 | #define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15) |
139 | #define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16) | 141 | #define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16) |
@@ -160,6 +162,12 @@ | |||
160 | #define NR_IRQS (IRQ_S3C2440_AC97+1) | 162 | #define NR_IRQS (IRQ_S3C2440_AC97+1) |
161 | #endif | 163 | #endif |
162 | 164 | ||
165 | /* compatibility define. */ | ||
166 | #define IRQ_UART3 IRQ_S3C2443_UART3 | ||
167 | #define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3 | ||
168 | #define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 | ||
169 | #define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 | ||
170 | |||
163 | /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ | 171 | /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */ |
164 | #define FIQ_START IRQ_EINT0 | 172 | #define FIQ_START IRQ_EINT0 |
165 | 173 | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h index 23c470c2e5b1..255fdfeaf957 100644 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ b/arch/arm/mach-s3c2410/include/mach/map.h | |||
@@ -13,34 +13,20 @@ | |||
13 | #ifndef __ASM_ARCH_MAP_H | 13 | #ifndef __ASM_ARCH_MAP_H |
14 | #define __ASM_ARCH_MAP_H | 14 | #define __ASM_ARCH_MAP_H |
15 | 15 | ||
16 | #include <plat/map-base.h> | ||
16 | #include <plat/map.h> | 17 | #include <plat/map.h> |
17 | 18 | ||
18 | #define S3C2410_ADDR(x) S3C_ADDR(x) | 19 | #define S3C2410_ADDR(x) S3C_ADDR(x) |
19 | 20 | ||
20 | /* interrupt controller is the first thing we put in, to make | ||
21 | * the assembly code for the irq detection easier | ||
22 | */ | ||
23 | #define S3C24XX_VA_IRQ S3C_VA_IRQ | ||
24 | #define S3C2410_PA_IRQ (0x4A000000) | ||
25 | #define S3C24XX_SZ_IRQ SZ_1M | ||
26 | |||
27 | /* memory controller registers */ | ||
28 | #define S3C24XX_VA_MEMCTRL S3C_VA_MEM | ||
29 | #define S3C2410_PA_MEMCTRL (0x48000000) | ||
30 | #define S3C24XX_SZ_MEMCTRL SZ_1M | ||
31 | |||
32 | /* USB host controller */ | 21 | /* USB host controller */ |
33 | #define S3C2410_PA_USBHOST (0x49000000) | 22 | #define S3C2410_PA_USBHOST (0x49000000) |
34 | #define S3C24XX_SZ_USBHOST SZ_1M | ||
35 | 23 | ||
36 | /* DMA controller */ | 24 | /* DMA controller */ |
37 | #define S3C2410_PA_DMA (0x4B000000) | 25 | #define S3C2410_PA_DMA (0x4B000000) |
38 | #define S3C24XX_SZ_DMA SZ_1M | 26 | #define S3C24XX_SZ_DMA SZ_1M |
39 | 27 | ||
40 | /* Clock and Power management */ | 28 | /* Clock and Power management */ |
41 | #define S3C24XX_VA_CLKPWR S3C_VA_SYS | ||
42 | #define S3C2410_PA_CLKPWR (0x4C000000) | 29 | #define S3C2410_PA_CLKPWR (0x4C000000) |
43 | #define S3C24XX_SZ_CLKPWR SZ_1M | ||
44 | 30 | ||
45 | /* LCD controller */ | 31 | /* LCD controller */ |
46 | #define S3C2410_PA_LCD (0x4D000000) | 32 | #define S3C2410_PA_LCD (0x4D000000) |
@@ -48,48 +34,12 @@ | |||
48 | 34 | ||
49 | /* NAND flash controller */ | 35 | /* NAND flash controller */ |
50 | #define S3C2410_PA_NAND (0x4E000000) | 36 | #define S3C2410_PA_NAND (0x4E000000) |
51 | #define S3C24XX_SZ_NAND SZ_1M | ||
52 | |||
53 | /* UARTs */ | ||
54 | #define S3C24XX_VA_UART S3C_VA_UART | ||
55 | #define S3C2410_PA_UART (0x50000000) | ||
56 | #define S3C24XX_SZ_UART SZ_1M | ||
57 | |||
58 | /* Timers */ | ||
59 | #define S3C24XX_VA_TIMER S3C_VA_TIMER | ||
60 | #define S3C2410_PA_TIMER (0x51000000) | ||
61 | #define S3C24XX_SZ_TIMER SZ_1M | ||
62 | |||
63 | /* USB Device port */ | ||
64 | #define S3C2410_PA_USBDEV (0x52000000) | ||
65 | #define S3C24XX_SZ_USBDEV SZ_1M | ||
66 | |||
67 | /* Watchdog */ | ||
68 | #define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG | ||
69 | #define S3C2410_PA_WATCHDOG (0x53000000) | ||
70 | #define S3C24XX_SZ_WATCHDOG SZ_1M | ||
71 | 37 | ||
72 | /* IIC hardware controller */ | 38 | /* IIC hardware controller */ |
73 | #define S3C2410_PA_IIC (0x54000000) | 39 | #define S3C2410_PA_IIC (0x54000000) |
74 | #define S3C24XX_SZ_IIC SZ_1M | ||
75 | 40 | ||
76 | /* IIS controller */ | 41 | /* IIS controller */ |
77 | #define S3C2410_PA_IIS (0x55000000) | 42 | #define S3C2410_PA_IIS (0x55000000) |
78 | #define S3C24XX_SZ_IIS SZ_1M | ||
79 | |||
80 | /* GPIO ports */ | ||
81 | |||
82 | /* the calculation for the VA of this must ensure that | ||
83 | * it is the same distance apart from the UART in the | ||
84 | * phsyical address space, as the initial mapping for the IO | ||
85 | * is done as a 1:1 maping. This puts it (currently) at | ||
86 | * 0xFA800000, which is not in the way of any current mapping | ||
87 | * by the base system. | ||
88 | */ | ||
89 | |||
90 | #define S3C2410_PA_GPIO (0x56000000) | ||
91 | #define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) | ||
92 | #define S3C24XX_SZ_GPIO SZ_1M | ||
93 | 43 | ||
94 | /* RTC */ | 44 | /* RTC */ |
95 | #define S3C2410_PA_RTC (0x57000000) | 45 | #define S3C2410_PA_RTC (0x57000000) |
@@ -97,15 +47,12 @@ | |||
97 | 47 | ||
98 | /* ADC */ | 48 | /* ADC */ |
99 | #define S3C2410_PA_ADC (0x58000000) | 49 | #define S3C2410_PA_ADC (0x58000000) |
100 | #define S3C24XX_SZ_ADC SZ_1M | ||
101 | 50 | ||
102 | /* SPI */ | 51 | /* SPI */ |
103 | #define S3C2410_PA_SPI (0x59000000) | 52 | #define S3C2410_PA_SPI (0x59000000) |
104 | #define S3C24XX_SZ_SPI SZ_1M | ||
105 | 53 | ||
106 | /* SDI */ | 54 | /* SDI */ |
107 | #define S3C2410_PA_SDI (0x5A000000) | 55 | #define S3C2410_PA_SDI (0x5A000000) |
108 | #define S3C24XX_SZ_SDI SZ_1M | ||
109 | 56 | ||
110 | /* CAMIF */ | 57 | /* CAMIF */ |
111 | #define S3C2440_PA_CAMIF (0x4F000000) | 58 | #define S3C2440_PA_CAMIF (0x4F000000) |
@@ -120,13 +67,6 @@ | |||
120 | #define S3C2443_PA_HSMMC (0x4A800000) | 67 | #define S3C2443_PA_HSMMC (0x4A800000) |
121 | #define S3C2443_SZ_HSMMC (256) | 68 | #define S3C2443_SZ_HSMMC (256) |
122 | 69 | ||
123 | /* ISA style IO, for each machine to sort out mappings for, if it | ||
124 | * implements it. We reserve two 16M regions for ISA. | ||
125 | */ | ||
126 | |||
127 | #define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000) | ||
128 | #define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000) | ||
129 | |||
130 | /* physical addresses of all the chip-select areas */ | 70 | /* physical addresses of all the chip-select areas */ |
131 | 71 | ||
132 | #define S3C2410_CS0 (0x00000000) | 72 | #define S3C2410_CS0 (0x00000000) |
@@ -152,27 +92,16 @@ | |||
152 | #define S3C24XX_PA_TIMER S3C2410_PA_TIMER | 92 | #define S3C24XX_PA_TIMER S3C2410_PA_TIMER |
153 | #define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV | 93 | #define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV |
154 | #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG | 94 | #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG |
155 | #define S3C24XX_PA_IIC S3C2410_PA_IIC | ||
156 | #define S3C24XX_PA_IIS S3C2410_PA_IIS | 95 | #define S3C24XX_PA_IIS S3C2410_PA_IIS |
157 | #define S3C24XX_PA_GPIO S3C2410_PA_GPIO | 96 | #define S3C24XX_PA_GPIO S3C2410_PA_GPIO |
158 | #define S3C24XX_PA_RTC S3C2410_PA_RTC | 97 | #define S3C24XX_PA_RTC S3C2410_PA_RTC |
159 | #define S3C24XX_PA_ADC S3C2410_PA_ADC | 98 | #define S3C24XX_PA_ADC S3C2410_PA_ADC |
160 | #define S3C24XX_PA_SPI S3C2410_PA_SPI | 99 | #define S3C24XX_PA_SPI S3C2410_PA_SPI |
100 | #define S3C24XX_PA_SDI S3C2410_PA_SDI | ||
101 | #define S3C24XX_PA_NAND S3C2410_PA_NAND | ||
161 | 102 | ||
162 | /* deal with the registers that move under the 2412/2413 */ | 103 | #define S3C_PA_IIC S3C2410_PA_IIC |
163 | 104 | #define S3C_PA_UART S3C24XX_PA_UART | |
164 | #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) | 105 | #define S3C_PA_HSMMC0 S3C2443_PA_HSMMC |
165 | #ifndef __ASSEMBLY__ | ||
166 | extern void __iomem *s3c24xx_va_gpio2; | ||
167 | #endif | ||
168 | #ifdef CONFIG_CPU_S3C2412_ONLY | ||
169 | #define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10) | ||
170 | #else | ||
171 | #define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2 | ||
172 | #endif | ||
173 | #else | ||
174 | #define s3c24xx_va_gpio2 S3C24XX_VA_GPIO | ||
175 | #define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO | ||
176 | #endif | ||
177 | 106 | ||
178 | #endif /* __ASM_ARCH_MAP_H */ | 107 | #endif /* __ASM_ARCH_MAP_H */ |
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-clock.h index b3f90aa78076..2a5d90e957fb 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-clock.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-clock.h | |||
@@ -42,13 +42,6 @@ | |||
42 | #define S3C2410_CLKCON_IIS (1<<17) | 42 | #define S3C2410_CLKCON_IIS (1<<17) |
43 | #define S3C2410_CLKCON_SPI (1<<18) | 43 | #define S3C2410_CLKCON_SPI (1<<18) |
44 | 44 | ||
45 | #define S3C2410_PLLCON_MDIVSHIFT 12 | ||
46 | #define S3C2410_PLLCON_PDIVSHIFT 4 | ||
47 | #define S3C2410_PLLCON_SDIVSHIFT 0 | ||
48 | #define S3C2410_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1) | ||
49 | #define S3C2410_PLLCON_PDIVMASK ((1<<5)-1) | ||
50 | #define S3C2410_PLLCON_SDIVMASK 3 | ||
51 | |||
52 | /* DCLKCON register addresses in gpio.h */ | 45 | /* DCLKCON register addresses in gpio.h */ |
53 | 46 | ||
54 | #define S3C2410_DCLKCON_DCLK0EN (1<<0) | 47 | #define S3C2410_DCLKCON_DCLK0EN (1<<0) |
@@ -76,32 +69,6 @@ | |||
76 | #define S3C2410_CLKSLOW_SLOWVAL(x) (x) | 69 | #define S3C2410_CLKSLOW_SLOWVAL(x) (x) |
77 | #define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7) | 70 | #define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7) |
78 | 71 | ||
79 | #ifndef __ASSEMBLY__ | ||
80 | |||
81 | #include <asm/div64.h> | ||
82 | |||
83 | static inline unsigned int | ||
84 | s3c2410_get_pll(unsigned int pllval, unsigned int baseclk) | ||
85 | { | ||
86 | unsigned int mdiv, pdiv, sdiv; | ||
87 | uint64_t fvco; | ||
88 | |||
89 | mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT; | ||
90 | pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT; | ||
91 | sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT; | ||
92 | |||
93 | mdiv &= S3C2410_PLLCON_MDIVMASK; | ||
94 | pdiv &= S3C2410_PLLCON_PDIVMASK; | ||
95 | sdiv &= S3C2410_PLLCON_SDIVMASK; | ||
96 | |||
97 | fvco = (uint64_t)baseclk * (mdiv + 8); | ||
98 | do_div(fvco, (pdiv + 2) << sdiv); | ||
99 | |||
100 | return (unsigned int)fvco; | ||
101 | } | ||
102 | |||
103 | #endif /* __ASSEMBLY__ */ | ||
104 | |||
105 | #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) | 72 | #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) |
106 | 73 | ||
107 | /* extra registers */ | 74 | /* extra registers */ |
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index 528080ceac44..321077613067 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h | |||
@@ -1053,13 +1053,6 @@ | |||
1053 | #define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C) | 1053 | #define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C) |
1054 | #define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90) | 1054 | #define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90) |
1055 | 1055 | ||
1056 | /* values for S3C2410_EXTINT0/1/2 */ | ||
1057 | #define S3C2410_EXTINT_LOWLEV (0x00) | ||
1058 | #define S3C2410_EXTINT_HILEV (0x01) | ||
1059 | #define S3C2410_EXTINT_FALLEDGE (0x02) | ||
1060 | #define S3C2410_EXTINT_RISEEDGE (0x04) | ||
1061 | #define S3C2410_EXTINT_BOTHEDGE (0x06) | ||
1062 | |||
1063 | /* interrupt filtering conrrol for EINT16..EINT23 */ | 1056 | /* interrupt filtering conrrol for EINT16..EINT23 */ |
1064 | #define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94) | 1057 | #define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94) |
1065 | #define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98) | 1058 | #define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98) |
diff --git a/arch/arm/mach-s3c2410/include/mach/spi.h b/arch/arm/mach-s3c2410/include/mach/spi.h index 46d46f5b99f2..774f3adfe8ad 100644 --- a/arch/arm/mach-s3c2410/include/mach/spi.h +++ b/arch/arm/mach-s3c2410/include/mach/spi.h | |||
@@ -22,5 +22,12 @@ struct s3c2410_spi_info { | |||
22 | void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol); | 22 | void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol); |
23 | }; | 23 | }; |
24 | 24 | ||
25 | /* Standard setup / suspend routines for SPI GPIO pins. */ | ||
26 | |||
27 | extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi, | ||
28 | int enable); | ||
29 | |||
30 | extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi, | ||
31 | int enable); | ||
25 | 32 | ||
26 | #endif /* __ASM_ARCH_SPI_H */ | 33 | #endif /* __ASM_ARCH_SPI_H */ |
diff --git a/arch/arm/mach-s3c2410/include/mach/tick.h b/arch/arm/mach-s3c2410/include/mach/tick.h new file mode 100644 index 000000000000..544da41979db --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/tick.h | |||
@@ -0,0 +1,15 @@ | |||
1 | /* linux/arch/arm/mach-s3c2410/include/mach/tick.h | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * S3C2410 - timer tick support | ||
8 | */ | ||
9 | |||
10 | #define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0)) | ||
11 | |||
12 | static inline int s3c24xx_ostimer_pending(void) | ||
13 | { | ||
14 | return __raw_readl(S3C2410_SRCPND) & SRCPND_TIMER4; | ||
15 | } | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/uncompress.h b/arch/arm/mach-s3c2410/include/mach/uncompress.h index ab39491beee2..c9432103750d 100644 --- a/arch/arm/mach-s3c2410/include/mach/uncompress.h +++ b/arch/arm/mach-s3c2410/include/mach/uncompress.h | |||
@@ -1,3 +1,4 @@ | |||
1 | |||
1 | /* arch/arm/mach-s3c2410/include/mach/uncompress.h | 2 | /* arch/arm/mach-s3c2410/include/mach/uncompress.h |
2 | * | 3 | * |
3 | * Copyright (c) 2003, 2007 Simtec Electronics | 4 | * Copyright (c) 2003, 2007 Simtec Electronics |
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c index d061fea01900..6d6995afeb43 100644 --- a/arch/arm/mach-s3c2410/mach-amlm5900.c +++ b/arch/arm/mach-s3c2410/mach-amlm5900.c | |||
@@ -52,6 +52,7 @@ | |||
52 | #include <mach/regs-lcd.h> | 52 | #include <mach/regs-lcd.h> |
53 | #include <mach/regs-gpio.h> | 53 | #include <mach/regs-gpio.h> |
54 | 54 | ||
55 | #include <plat/iic.h> | ||
55 | #include <plat/devs.h> | 56 | #include <plat/devs.h> |
56 | #include <plat/cpu.h> | 57 | #include <plat/cpu.h> |
57 | 58 | ||
@@ -150,7 +151,7 @@ static struct platform_device *amlm5900_devices[] __initdata = { | |||
150 | #endif | 151 | #endif |
151 | &s3c_device_adc, | 152 | &s3c_device_adc, |
152 | &s3c_device_wdt, | 153 | &s3c_device_wdt, |
153 | &s3c_device_i2c, | 154 | &s3c_device_i2c0, |
154 | &s3c_device_usb, | 155 | &s3c_device_usb, |
155 | &s3c_device_rtc, | 156 | &s3c_device_rtc, |
156 | &s3c_device_usbgadget, | 157 | &s3c_device_usbgadget, |
@@ -233,6 +234,7 @@ static void __init amlm5900_init(void) | |||
233 | #ifdef CONFIG_FB_S3C2410 | 234 | #ifdef CONFIG_FB_S3C2410 |
234 | s3c24xx_fb_set_platdata(&amlm5900_fb_info); | 235 | s3c24xx_fb_set_platdata(&amlm5900_fb_info); |
235 | #endif | 236 | #endif |
237 | s3c_i2c0_set_platdata(NULL); | ||
236 | platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices)); | 238 | platform_add_devices(amlm5900_devices, ARRAY_SIZE(amlm5900_devices)); |
237 | } | 239 | } |
238 | 240 | ||
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index c04c24444e0d..01bd76725b92 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c | |||
@@ -406,7 +406,7 @@ static struct platform_device bast_sio = { | |||
406 | * standard 100KHz i2c bus frequency | 406 | * standard 100KHz i2c bus frequency |
407 | */ | 407 | */ |
408 | 408 | ||
409 | static struct s3c2410_platform_i2c bast_i2c_info = { | 409 | static struct s3c2410_platform_i2c __initdata bast_i2c_info = { |
410 | .flags = 0, | 410 | .flags = 0, |
411 | .slave_addr = 0x10, | 411 | .slave_addr = 0x10, |
412 | .bus_freq = 100*1000, | 412 | .bus_freq = 100*1000, |
@@ -553,7 +553,7 @@ static struct platform_device *bast_devices[] __initdata = { | |||
553 | &s3c_device_usb, | 553 | &s3c_device_usb, |
554 | &s3c_device_lcd, | 554 | &s3c_device_lcd, |
555 | &s3c_device_wdt, | 555 | &s3c_device_wdt, |
556 | &s3c_device_i2c, | 556 | &s3c_device_i2c0, |
557 | &s3c_device_rtc, | 557 | &s3c_device_rtc, |
558 | &s3c_device_nand, | 558 | &s3c_device_nand, |
559 | &bast_device_dm9k, | 559 | &bast_device_dm9k, |
@@ -588,7 +588,8 @@ static void __init bast_map_io(void) | |||
588 | s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks)); | 588 | s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks)); |
589 | 589 | ||
590 | s3c_device_nand.dev.platform_data = &bast_nand_info; | 590 | s3c_device_nand.dev.platform_data = &bast_nand_info; |
591 | s3c_device_i2c.dev.platform_data = &bast_i2c_info; | 591 | |
592 | s3c_i2c0_set_platdata(&bast_i2c_info); | ||
592 | 593 | ||
593 | s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); | 594 | s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); |
594 | s3c24xx_init_clocks(0); | 595 | s3c24xx_init_clocks(0); |
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 32d550fcff4d..821a1668c3ac 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c | |||
@@ -39,10 +39,12 @@ | |||
39 | #include <mach/h1940-latch.h> | 39 | #include <mach/h1940-latch.h> |
40 | #include <mach/fb.h> | 40 | #include <mach/fb.h> |
41 | #include <plat/udc.h> | 41 | #include <plat/udc.h> |
42 | #include <plat/iic.h> | ||
42 | 43 | ||
43 | #include <plat/clock.h> | 44 | #include <plat/clock.h> |
44 | #include <plat/devs.h> | 45 | #include <plat/devs.h> |
45 | #include <plat/cpu.h> | 46 | #include <plat/cpu.h> |
47 | #include <plat/pll.h> | ||
46 | #include <plat/pm.h> | 48 | #include <plat/pm.h> |
47 | 49 | ||
48 | static struct map_desc h1940_iodesc[] __initdata = { | 50 | static struct map_desc h1940_iodesc[] __initdata = { |
@@ -183,7 +185,7 @@ static struct platform_device *h1940_devices[] __initdata = { | |||
183 | &s3c_device_usb, | 185 | &s3c_device_usb, |
184 | &s3c_device_lcd, | 186 | &s3c_device_lcd, |
185 | &s3c_device_wdt, | 187 | &s3c_device_wdt, |
186 | &s3c_device_i2c, | 188 | &s3c_device_i2c0, |
187 | &s3c_device_iis, | 189 | &s3c_device_iis, |
188 | &s3c_device_usbgadget, | 190 | &s3c_device_usbgadget, |
189 | &s3c_device_leds, | 191 | &s3c_device_leds, |
@@ -215,6 +217,7 @@ static void __init h1940_init(void) | |||
215 | 217 | ||
216 | s3c24xx_fb_set_platdata(&h1940_fb_info); | 218 | s3c24xx_fb_set_platdata(&h1940_fb_info); |
217 | s3c24xx_udc_set_platdata(&h1940_udc_cfg); | 219 | s3c24xx_udc_set_platdata(&h1940_udc_cfg); |
220 | s3c_i2c0_set_platdata(NULL); | ||
218 | 221 | ||
219 | /* Turn off suspend on both USB ports, and switch the | 222 | /* Turn off suspend on both USB ports, and switch the |
220 | * selectable USB port to USB device mode. */ | 223 | * selectable USB port to USB device mode. */ |
@@ -223,10 +226,9 @@ static void __init h1940_init(void) | |||
223 | S3C2410_MISCCR_USBSUSPND0 | | 226 | S3C2410_MISCCR_USBSUSPND0 | |
224 | S3C2410_MISCCR_USBSUSPND1, 0x0); | 227 | S3C2410_MISCCR_USBSUSPND1, 0x0); |
225 | 228 | ||
226 | tmp = ( | 229 | tmp = (0x78 << S3C24XX_PLLCON_MDIVSHIFT) |
227 | 0x78 << S3C2410_PLLCON_MDIVSHIFT) | 230 | | (0x02 << S3C24XX_PLLCON_PDIVSHIFT) |
228 | | (0x02 << S3C2410_PLLCON_PDIVSHIFT) | 231 | | (0x03 << S3C24XX_PLLCON_SDIVSHIFT); |
229 | | (0x03 << S3C2410_PLLCON_SDIVSHIFT); | ||
230 | writel(tmp, S3C2410_UPLLCON); | 232 | writel(tmp, S3C2410_UPLLCON); |
231 | 233 | ||
232 | platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices)); | 234 | platform_add_devices(h1940_devices, ARRAY_SIZE(h1940_devices)); |
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c index 7a7c45d28fe7..05a5e877b49b 100644 --- a/arch/arm/mach-s3c2410/mach-n30.c +++ b/arch/arm/mach-s3c2410/mach-n30.c | |||
@@ -17,7 +17,6 @@ | |||
17 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
18 | #include <linux/types.h> | 18 | #include <linux/types.h> |
19 | 19 | ||
20 | #include <linux/delay.h> | ||
21 | #include <linux/gpio_keys.h> | 20 | #include <linux/gpio_keys.h> |
22 | #include <linux/init.h> | 21 | #include <linux/init.h> |
23 | #include <linux/input.h> | 22 | #include <linux/input.h> |
@@ -320,7 +319,7 @@ static struct s3c2410fb_mach_info n30_fb_info __initdata = { | |||
320 | static struct platform_device *n30_devices[] __initdata = { | 319 | static struct platform_device *n30_devices[] __initdata = { |
321 | &s3c_device_lcd, | 320 | &s3c_device_lcd, |
322 | &s3c_device_wdt, | 321 | &s3c_device_wdt, |
323 | &s3c_device_i2c, | 322 | &s3c_device_i2c0, |
324 | &s3c_device_iis, | 323 | &s3c_device_iis, |
325 | &s3c_device_usb, | 324 | &s3c_device_usb, |
326 | &s3c_device_usbgadget, | 325 | &s3c_device_usbgadget, |
@@ -332,7 +331,7 @@ static struct platform_device *n30_devices[] __initdata = { | |||
332 | static struct platform_device *n35_devices[] __initdata = { | 331 | static struct platform_device *n35_devices[] __initdata = { |
333 | &s3c_device_lcd, | 332 | &s3c_device_lcd, |
334 | &s3c_device_wdt, | 333 | &s3c_device_wdt, |
335 | &s3c_device_i2c, | 334 | &s3c_device_i2c0, |
336 | &s3c_device_iis, | 335 | &s3c_device_iis, |
337 | &s3c_device_usbgadget, | 336 | &s3c_device_usbgadget, |
338 | &n35_button_device, | 337 | &n35_button_device, |
@@ -501,7 +500,7 @@ static void __init n30_init_irq(void) | |||
501 | static void __init n30_init(void) | 500 | static void __init n30_init(void) |
502 | { | 501 | { |
503 | s3c24xx_fb_set_platdata(&n30_fb_info); | 502 | s3c24xx_fb_set_platdata(&n30_fb_info); |
504 | s3c_device_i2c.dev.platform_data = &n30_i2ccfg; | 503 | s3c_device_i2c0.dev.platform_data = &n30_i2ccfg; |
505 | s3c24xx_udc_set_platdata(&n30_udc_cfg); | 504 | s3c24xx_udc_set_platdata(&n30_udc_cfg); |
506 | 505 | ||
507 | /* Turn off suspend on both USB ports, and switch the | 506 | /* Turn off suspend on both USB ports, and switch the |
diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c index d8255cf87e44..f6c7261a4a12 100644 --- a/arch/arm/mach-s3c2410/mach-otom.c +++ b/arch/arm/mach-s3c2410/mach-otom.c | |||
@@ -35,6 +35,7 @@ | |||
35 | #include <plat/s3c2410.h> | 35 | #include <plat/s3c2410.h> |
36 | #include <plat/clock.h> | 36 | #include <plat/clock.h> |
37 | #include <plat/devs.h> | 37 | #include <plat/devs.h> |
38 | #include <plat/iic.h> | ||
38 | #include <plat/cpu.h> | 39 | #include <plat/cpu.h> |
39 | 40 | ||
40 | static struct map_desc otom11_iodesc[] __initdata = { | 41 | static struct map_desc otom11_iodesc[] __initdata = { |
@@ -94,7 +95,7 @@ static struct platform_device *otom11_devices[] __initdata = { | |||
94 | &s3c_device_usb, | 95 | &s3c_device_usb, |
95 | &s3c_device_lcd, | 96 | &s3c_device_lcd, |
96 | &s3c_device_wdt, | 97 | &s3c_device_wdt, |
97 | &s3c_device_i2c, | 98 | &s3c_device_i2c0, |
98 | &s3c_device_iis, | 99 | &s3c_device_iis, |
99 | &s3c_device_rtc, | 100 | &s3c_device_rtc, |
100 | &otom_device_nor, | 101 | &otom_device_nor, |
@@ -109,6 +110,7 @@ static void __init otom11_map_io(void) | |||
109 | 110 | ||
110 | static void __init otom11_init(void) | 111 | static void __init otom11_init(void) |
111 | { | 112 | { |
113 | s3c_i2c0_set_platdata(NULL); | ||
112 | platform_add_devices(otom11_devices, ARRAY_SIZE(otom11_devices)); | 114 | platform_add_devices(otom11_devices, ARRAY_SIZE(otom11_devices)); |
113 | } | 115 | } |
114 | 116 | ||
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c index ef868472f6a4..9678a53ceeb1 100644 --- a/arch/arm/mach-s3c2410/mach-qt2410.c +++ b/arch/arm/mach-s3c2410/mach-qt2410.c | |||
@@ -54,6 +54,7 @@ | |||
54 | #include <plat/udc.h> | 54 | #include <plat/udc.h> |
55 | #include <mach/spi.h> | 55 | #include <mach/spi.h> |
56 | #include <mach/spi-gpio.h> | 56 | #include <mach/spi-gpio.h> |
57 | #include <plat/iic.h> | ||
57 | 58 | ||
58 | #include <plat/common-smdk.h> | 59 | #include <plat/common-smdk.h> |
59 | #include <plat/devs.h> | 60 | #include <plat/devs.h> |
@@ -247,7 +248,7 @@ static struct platform_device *qt2410_devices[] __initdata = { | |||
247 | &s3c_device_usb, | 248 | &s3c_device_usb, |
248 | &s3c_device_lcd, | 249 | &s3c_device_lcd, |
249 | &s3c_device_wdt, | 250 | &s3c_device_wdt, |
250 | &s3c_device_i2c, | 251 | &s3c_device_i2c0, |
251 | &s3c_device_iis, | 252 | &s3c_device_iis, |
252 | &s3c_device_sdi, | 253 | &s3c_device_sdi, |
253 | &s3c_device_usbgadget, | 254 | &s3c_device_usbgadget, |
@@ -349,6 +350,7 @@ static void __init qt2410_machine_init(void) | |||
349 | s3c2410_gpio_setpin(S3C2410_GPB0, 1); | 350 | s3c2410_gpio_setpin(S3C2410_GPB0, 1); |
350 | 351 | ||
351 | s3c24xx_udc_set_platdata(&qt2410_udc_cfg); | 352 | s3c24xx_udc_set_platdata(&qt2410_udc_cfg); |
353 | s3c_i2c0_set_platdata(NULL); | ||
352 | 354 | ||
353 | s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT); | 355 | s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT); |
354 | 356 | ||
diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c index 152527bb2872..c49126ccb1d5 100644 --- a/arch/arm/mach-s3c2410/mach-smdk2410.c +++ b/arch/arm/mach-s3c2410/mach-smdk2410.c | |||
@@ -47,6 +47,7 @@ | |||
47 | #include <asm/mach-types.h> | 47 | #include <asm/mach-types.h> |
48 | 48 | ||
49 | #include <plat/regs-serial.h> | 49 | #include <plat/regs-serial.h> |
50 | #include <plat/iic.h> | ||
50 | 51 | ||
51 | #include <plat/devs.h> | 52 | #include <plat/devs.h> |
52 | #include <plat/cpu.h> | 53 | #include <plat/cpu.h> |
@@ -89,7 +90,7 @@ static struct platform_device *smdk2410_devices[] __initdata = { | |||
89 | &s3c_device_usb, | 90 | &s3c_device_usb, |
90 | &s3c_device_lcd, | 91 | &s3c_device_lcd, |
91 | &s3c_device_wdt, | 92 | &s3c_device_wdt, |
92 | &s3c_device_i2c, | 93 | &s3c_device_i2c0, |
93 | &s3c_device_iis, | 94 | &s3c_device_iis, |
94 | }; | 95 | }; |
95 | 96 | ||
@@ -102,6 +103,7 @@ static void __init smdk2410_map_io(void) | |||
102 | 103 | ||
103 | static void __init smdk2410_init(void) | 104 | static void __init smdk2410_init(void) |
104 | { | 105 | { |
106 | s3c_i2c0_set_platdata(NULL); | ||
105 | platform_add_devices(smdk2410_devices, ARRAY_SIZE(smdk2410_devices)); | 107 | platform_add_devices(smdk2410_devices, ARRAY_SIZE(smdk2410_devices)); |
106 | smdk_machine_init(); | 108 | smdk_machine_init(); |
107 | } | 109 | } |
diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c index 309dcf4c870a..8fdb0430bd48 100644 --- a/arch/arm/mach-s3c2410/mach-tct_hammer.c +++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c | |||
@@ -45,6 +45,7 @@ | |||
45 | #include <asm/mach-types.h> | 45 | #include <asm/mach-types.h> |
46 | 46 | ||
47 | #include <plat/regs-serial.h> | 47 | #include <plat/regs-serial.h> |
48 | #include <plat/iic.h> | ||
48 | #include <plat/devs.h> | 49 | #include <plat/devs.h> |
49 | #include <plat/cpu.h> | 50 | #include <plat/cpu.h> |
50 | 51 | ||
@@ -127,7 +128,7 @@ static struct s3c2410_uartcfg tct_hammer_uartcfgs[] = { | |||
127 | static struct platform_device *tct_hammer_devices[] __initdata = { | 128 | static struct platform_device *tct_hammer_devices[] __initdata = { |
128 | &s3c_device_adc, | 129 | &s3c_device_adc, |
129 | &s3c_device_wdt, | 130 | &s3c_device_wdt, |
130 | &s3c_device_i2c, | 131 | &s3c_device_i2c0, |
131 | &s3c_device_usb, | 132 | &s3c_device_usb, |
132 | &s3c_device_rtc, | 133 | &s3c_device_rtc, |
133 | &s3c_device_usbgadget, | 134 | &s3c_device_usbgadget, |
@@ -146,6 +147,7 @@ static void __init tct_hammer_map_io(void) | |||
146 | 147 | ||
147 | static void __init tct_hammer_init(void) | 148 | static void __init tct_hammer_init(void) |
148 | { | 149 | { |
150 | s3c_i2c0_set_platdata(NULL); | ||
149 | platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices)); | 151 | platform_add_devices(tct_hammer_devices, ARRAY_SIZE(tct_hammer_devices)); |
150 | } | 152 | } |
151 | 153 | ||
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c index 941353af16dc..61a1ea9c5c5c 100644 --- a/arch/arm/mach-s3c2410/mach-vr1000.c +++ b/arch/arm/mach-s3c2410/mach-vr1000.c | |||
@@ -47,6 +47,7 @@ | |||
47 | #include <plat/clock.h> | 47 | #include <plat/clock.h> |
48 | #include <plat/devs.h> | 48 | #include <plat/devs.h> |
49 | #include <plat/cpu.h> | 49 | #include <plat/cpu.h> |
50 | #include <plat/iic.h> | ||
50 | 51 | ||
51 | #include "usb-simtec.h" | 52 | #include "usb-simtec.h" |
52 | #include "nor-simtec.h" | 53 | #include "nor-simtec.h" |
@@ -334,7 +335,7 @@ static struct platform_device *vr1000_devices[] __initdata = { | |||
334 | &s3c_device_usb, | 335 | &s3c_device_usb, |
335 | &s3c_device_lcd, | 336 | &s3c_device_lcd, |
336 | &s3c_device_wdt, | 337 | &s3c_device_wdt, |
337 | &s3c_device_i2c, | 338 | &s3c_device_i2c0, |
338 | &s3c_device_adc, | 339 | &s3c_device_adc, |
339 | &serial_device, | 340 | &serial_device, |
340 | &vr1000_dm9k0, | 341 | &vr1000_dm9k0, |
@@ -384,6 +385,7 @@ static void __init vr1000_map_io(void) | |||
384 | 385 | ||
385 | static void __init vr1000_init(void) | 386 | static void __init vr1000_init(void) |
386 | { | 387 | { |
388 | s3c_i2c0_set_platdata(NULL); | ||
387 | platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices)); | 389 | platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices)); |
388 | 390 | ||
389 | i2c_register_board_info(0, vr1000_i2c_devs, | 391 | i2c_register_board_info(0, vr1000_i2c_devs, |
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c index ac79b536c4c3..feb141b1f915 100644 --- a/arch/arm/mach-s3c2410/s3c2410.c +++ b/arch/arm/mach-s3c2410/s3c2410.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <linux/list.h> | 16 | #include <linux/list.h> |
17 | #include <linux/timer.h> | 17 | #include <linux/timer.h> |
18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
19 | #include <linux/clk.h> | ||
19 | #include <linux/sysdev.h> | 20 | #include <linux/sysdev.h> |
20 | #include <linux/serial_core.h> | 21 | #include <linux/serial_core.h> |
21 | #include <linux/platform_device.h> | 22 | #include <linux/platform_device.h> |
@@ -28,6 +29,8 @@ | |||
28 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
29 | #include <asm/irq.h> | 30 | #include <asm/irq.h> |
30 | 31 | ||
32 | #include <plat/cpu-freq.h> | ||
33 | |||
31 | #include <mach/regs-clock.h> | 34 | #include <mach/regs-clock.h> |
32 | #include <plat/regs-serial.h> | 35 | #include <plat/regs-serial.h> |
33 | 36 | ||
@@ -35,6 +38,7 @@ | |||
35 | #include <plat/cpu.h> | 38 | #include <plat/cpu.h> |
36 | #include <plat/devs.h> | 39 | #include <plat/devs.h> |
37 | #include <plat/clock.h> | 40 | #include <plat/clock.h> |
41 | #include <plat/pll.h> | ||
38 | 42 | ||
39 | /* Initial IO mappings */ | 43 | /* Initial IO mappings */ |
40 | 44 | ||
@@ -59,25 +63,28 @@ void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no) | |||
59 | * machine specific initialisation. | 63 | * machine specific initialisation. |
60 | */ | 64 | */ |
61 | 65 | ||
62 | void __init s3c2410_map_io(struct map_desc *mach_desc, int mach_size) | 66 | void __init s3c2410_map_io(void) |
63 | { | 67 | { |
64 | /* register our io-tables */ | ||
65 | |||
66 | iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc)); | 68 | iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc)); |
67 | iotable_init(mach_desc, mach_size); | ||
68 | } | 69 | } |
69 | 70 | ||
70 | void __init s3c2410_init_clocks(int xtal) | 71 | void __init_or_cpufreq s3c2410_setup_clocks(void) |
71 | { | 72 | { |
73 | struct clk *xtal_clk; | ||
72 | unsigned long tmp; | 74 | unsigned long tmp; |
75 | unsigned long xtal; | ||
73 | unsigned long fclk; | 76 | unsigned long fclk; |
74 | unsigned long hclk; | 77 | unsigned long hclk; |
75 | unsigned long pclk; | 78 | unsigned long pclk; |
76 | 79 | ||
80 | xtal_clk = clk_get(NULL, "xtal"); | ||
81 | xtal = clk_get_rate(xtal_clk); | ||
82 | clk_put(xtal_clk); | ||
83 | |||
77 | /* now we've got our machine bits initialised, work out what | 84 | /* now we've got our machine bits initialised, work out what |
78 | * clocks we've got */ | 85 | * clocks we've got */ |
79 | 86 | ||
80 | fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal); | 87 | fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal); |
81 | 88 | ||
82 | tmp = __raw_readl(S3C2410_CLKDIVN); | 89 | tmp = __raw_readl(S3C2410_CLKDIVN); |
83 | 90 | ||
@@ -95,7 +102,13 @@ void __init s3c2410_init_clocks(int xtal) | |||
95 | * console to use them | 102 | * console to use them |
96 | */ | 103 | */ |
97 | 104 | ||
98 | s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); | 105 | s3c24xx_setup_clocks(fclk, hclk, pclk); |
106 | } | ||
107 | |||
108 | void __init s3c2410_init_clocks(int xtal) | ||
109 | { | ||
110 | s3c24xx_register_baseclocks(xtal); | ||
111 | s3c2410_setup_clocks(); | ||
99 | s3c2410_baseclk_add(); | 112 | s3c2410_baseclk_add(); |
100 | } | 113 | } |
101 | 114 | ||
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c index 96d9eb15424f..a037df5e1c2d 100644 --- a/arch/arm/mach-s3c2412/clock.c +++ b/arch/arm/mach-s3c2412/clock.c | |||
@@ -93,12 +93,6 @@ static int s3c2412_upll_enable(struct clk *clk, int enable) | |||
93 | 93 | ||
94 | /* clock selections */ | 94 | /* clock selections */ |
95 | 95 | ||
96 | /* CPU EXTCLK input */ | ||
97 | static struct clk clk_ext = { | ||
98 | .name = "extclk", | ||
99 | .id = -1, | ||
100 | }; | ||
101 | |||
102 | static struct clk clk_erefclk = { | 96 | static struct clk clk_erefclk = { |
103 | .name = "erefclk", | 97 | .name = "erefclk", |
104 | .id = -1, | 98 | .id = -1, |
@@ -773,5 +767,6 @@ int __init s3c2412_baseclk_add(void) | |||
773 | s3c2412_clkcon_enable(clkp, 0); | 767 | s3c2412_clkcon_enable(clkp, 0); |
774 | } | 768 | } |
775 | 769 | ||
770 | s3c_pwmclk_init(); | ||
776 | return 0; | 771 | return 0; |
777 | } | 772 | } |
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c index 25ff1ec9f8ad..ecddbbb34832 100644 --- a/arch/arm/mach-s3c2412/mach-jive.c +++ b/arch/arm/mach-s3c2412/mach-jive.c | |||
@@ -17,7 +17,6 @@ | |||
17 | #include <linux/timer.h> | 17 | #include <linux/timer.h> |
18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
19 | #include <linux/sysdev.h> | 19 | #include <linux/sysdev.h> |
20 | #include <linux/delay.h> | ||
21 | #include <linux/serial_core.h> | 20 | #include <linux/serial_core.h> |
22 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
23 | #include <linux/i2c.h> | 22 | #include <linux/i2c.h> |
@@ -53,6 +52,7 @@ | |||
53 | #include <plat/cpu.h> | 52 | #include <plat/cpu.h> |
54 | #include <plat/pm.h> | 53 | #include <plat/pm.h> |
55 | #include <plat/udc.h> | 54 | #include <plat/udc.h> |
55 | #include <plat/iic.h> | ||
56 | 56 | ||
57 | static struct map_desc jive_iodesc[] __initdata = { | 57 | static struct map_desc jive_iodesc[] __initdata = { |
58 | }; | 58 | }; |
@@ -398,11 +398,12 @@ static struct s3c2410_spigpio_info jive_lcd_spi = { | |||
398 | .bus_num = 1, | 398 | .bus_num = 1, |
399 | .pin_clk = S3C2410_GPG8, | 399 | .pin_clk = S3C2410_GPG8, |
400 | .pin_mosi = S3C2410_GPB8, | 400 | .pin_mosi = S3C2410_GPB8, |
401 | .num_chipselect = 1, | ||
401 | .chip_select = jive_lcd_spi_chipselect, | 402 | .chip_select = jive_lcd_spi_chipselect, |
402 | }; | 403 | }; |
403 | 404 | ||
404 | static struct platform_device jive_device_lcdspi = { | 405 | static struct platform_device jive_device_lcdspi = { |
405 | .name = "s3c24xx-spi-gpio", | 406 | .name = "spi_s3c24xx_gpio", |
406 | .id = 1, | 407 | .id = 1, |
407 | .num_resources = 0, | 408 | .num_resources = 0, |
408 | .dev.platform_data = &jive_lcd_spi, | 409 | .dev.platform_data = &jive_lcd_spi, |
@@ -419,11 +420,12 @@ static struct s3c2410_spigpio_info jive_wm8750_spi = { | |||
419 | .bus_num = 2, | 420 | .bus_num = 2, |
420 | .pin_clk = S3C2410_GPB4, | 421 | .pin_clk = S3C2410_GPB4, |
421 | .pin_mosi = S3C2410_GPB9, | 422 | .pin_mosi = S3C2410_GPB9, |
423 | .num_chipselect = 1, | ||
422 | .chip_select = jive_wm8750_chipselect, | 424 | .chip_select = jive_wm8750_chipselect, |
423 | }; | 425 | }; |
424 | 426 | ||
425 | static struct platform_device jive_device_wm8750 = { | 427 | static struct platform_device jive_device_wm8750 = { |
426 | .name = "s3c24xx-spi-gpio", | 428 | .name = "spi_s3c24xx_gpio", |
427 | .id = 2, | 429 | .id = 2, |
428 | .num_resources = 0, | 430 | .num_resources = 0, |
429 | .dev.platform_data = &jive_wm8750_spi, | 431 | .dev.platform_data = &jive_wm8750_spi, |
@@ -450,14 +452,14 @@ static struct spi_board_info __initdata jive_spi_devs[] = { | |||
450 | 452 | ||
451 | /* I2C bus and device configuration. */ | 453 | /* I2C bus and device configuration. */ |
452 | 454 | ||
453 | static struct s3c2410_platform_i2c jive_i2c_cfg = { | 455 | static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = { |
454 | .max_freq = 80 * 1000, | 456 | .max_freq = 80 * 1000, |
455 | .bus_freq = 50 * 1000, | 457 | .bus_freq = 50 * 1000, |
456 | .flags = S3C_IICFLG_FILTER, | 458 | .flags = S3C_IICFLG_FILTER, |
457 | .sda_delay = 2, | 459 | .sda_delay = 2, |
458 | }; | 460 | }; |
459 | 461 | ||
460 | static struct i2c_board_info jive_i2c_devs[] = { | 462 | static struct i2c_board_info jive_i2c_devs[] __initdata = { |
461 | [0] = { | 463 | [0] = { |
462 | I2C_BOARD_INFO("lis302dl", 0x1c), | 464 | I2C_BOARD_INFO("lis302dl", 0x1c), |
463 | .irq = IRQ_EINT14, | 465 | .irq = IRQ_EINT14, |
@@ -470,7 +472,7 @@ static struct platform_device *jive_devices[] __initdata = { | |||
470 | &s3c_device_usb, | 472 | &s3c_device_usb, |
471 | &s3c_device_rtc, | 473 | &s3c_device_rtc, |
472 | &s3c_device_wdt, | 474 | &s3c_device_wdt, |
473 | &s3c_device_i2c, | 475 | &s3c_device_i2c0, |
474 | &s3c_device_lcd, | 476 | &s3c_device_lcd, |
475 | &jive_device_lcdspi, | 477 | &jive_device_lcdspi, |
476 | &jive_device_wm8750, | 478 | &jive_device_wm8750, |
@@ -663,7 +665,7 @@ static void __init jive_machine_init(void) | |||
663 | 665 | ||
664 | spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs)); | 666 | spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs)); |
665 | 667 | ||
666 | s3c_device_i2c.dev.platform_data = &jive_i2c_cfg; | 668 | s3c_i2c0_set_platdata(&jive_i2c_cfg); |
667 | i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs)); | 669 | i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs)); |
668 | 670 | ||
669 | pm_power_off = jive_power_off; | 671 | pm_power_off = jive_power_off; |
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c index 8fd17b8d5679..eba66aa6bd20 100644 --- a/arch/arm/mach-s3c2412/mach-smdk2413.c +++ b/arch/arm/mach-s3c2412/mach-smdk2413.c | |||
@@ -38,6 +38,7 @@ | |||
38 | 38 | ||
39 | #include <mach/idle.h> | 39 | #include <mach/idle.h> |
40 | #include <plat/udc.h> | 40 | #include <plat/udc.h> |
41 | #include <plat/iic.h> | ||
41 | #include <mach/fb.h> | 42 | #include <mach/fb.h> |
42 | 43 | ||
43 | #include <plat/s3c2410.h> | 44 | #include <plat/s3c2410.h> |
@@ -105,7 +106,7 @@ static struct platform_device *smdk2413_devices[] __initdata = { | |||
105 | &s3c_device_usb, | 106 | &s3c_device_usb, |
106 | //&s3c_device_lcd, | 107 | //&s3c_device_lcd, |
107 | &s3c_device_wdt, | 108 | &s3c_device_wdt, |
108 | &s3c_device_i2c, | 109 | &s3c_device_i2c0, |
109 | &s3c_device_iis, | 110 | &s3c_device_iis, |
110 | &s3c_device_usbgadget, | 111 | &s3c_device_usbgadget, |
111 | }; | 112 | }; |
@@ -142,6 +143,7 @@ static void __init smdk2413_machine_init(void) | |||
142 | 143 | ||
143 | 144 | ||
144 | s3c24xx_udc_set_platdata(&smdk2413_udc_cfg); | 145 | s3c24xx_udc_set_platdata(&smdk2413_udc_cfg); |
146 | s3c_i2c0_set_platdata(NULL); | ||
145 | 147 | ||
146 | platform_add_devices(smdk2413_devices, ARRAY_SIZE(smdk2413_devices)); | 148 | platform_add_devices(smdk2413_devices, ARRAY_SIZE(smdk2413_devices)); |
147 | smdk_machine_init(); | 149 | smdk_machine_init(); |
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c index da32a6cb17ae..11e8ad49fc7b 100644 --- a/arch/arm/mach-s3c2412/mach-vstms.c +++ b/arch/arm/mach-s3c2412/mach-vstms.c | |||
@@ -39,6 +39,7 @@ | |||
39 | #include <mach/idle.h> | 39 | #include <mach/idle.h> |
40 | #include <mach/fb.h> | 40 | #include <mach/fb.h> |
41 | 41 | ||
42 | #include <plat/iic.h> | ||
42 | #include <plat/nand.h> | 43 | #include <plat/nand.h> |
43 | 44 | ||
44 | #include <plat/s3c2410.h> | 45 | #include <plat/s3c2410.h> |
@@ -122,7 +123,7 @@ static struct s3c2410_platform_nand vstms_nand_info = { | |||
122 | static struct platform_device *vstms_devices[] __initdata = { | 123 | static struct platform_device *vstms_devices[] __initdata = { |
123 | &s3c_device_usb, | 124 | &s3c_device_usb, |
124 | &s3c_device_wdt, | 125 | &s3c_device_wdt, |
125 | &s3c_device_i2c, | 126 | &s3c_device_i2c0, |
126 | &s3c_device_iis, | 127 | &s3c_device_iis, |
127 | &s3c_device_rtc, | 128 | &s3c_device_rtc, |
128 | &s3c_device_nand, | 129 | &s3c_device_nand, |
@@ -151,6 +152,7 @@ static void __init vstms_map_io(void) | |||
151 | 152 | ||
152 | static void __init vstms_init(void) | 153 | static void __init vstms_init(void) |
153 | { | 154 | { |
155 | s3c_i2c0_set_platdata(NULL); | ||
154 | platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices)); | 156 | platform_add_devices(vstms_devices, ARRAY_SIZE(vstms_devices)); |
155 | } | 157 | } |
156 | 158 | ||
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c index a086818e117e..5b5aba69ec3f 100644 --- a/arch/arm/mach-s3c2412/s3c2412.c +++ b/arch/arm/mach-s3c2412/s3c2412.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <linux/list.h> | 16 | #include <linux/list.h> |
17 | #include <linux/timer.h> | 17 | #include <linux/timer.h> |
18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
19 | #include <linux/clk.h> | ||
19 | #include <linux/delay.h> | 20 | #include <linux/delay.h> |
20 | #include <linux/sysdev.h> | 21 | #include <linux/sysdev.h> |
21 | #include <linux/serial_core.h> | 22 | #include <linux/serial_core.h> |
@@ -33,6 +34,8 @@ | |||
33 | #include <mach/reset.h> | 34 | #include <mach/reset.h> |
34 | #include <mach/idle.h> | 35 | #include <mach/idle.h> |
35 | 36 | ||
37 | #include <plat/cpu-freq.h> | ||
38 | |||
36 | #include <mach/regs-clock.h> | 39 | #include <mach/regs-clock.h> |
37 | #include <plat/regs-serial.h> | 40 | #include <plat/regs-serial.h> |
38 | #include <mach/regs-power.h> | 41 | #include <mach/regs-power.h> |
@@ -47,6 +50,7 @@ | |||
47 | #include <plat/devs.h> | 50 | #include <plat/devs.h> |
48 | #include <plat/clock.h> | 51 | #include <plat/clock.h> |
49 | #include <plat/pm.h> | 52 | #include <plat/pm.h> |
53 | #include <plat/pll.h> | ||
50 | 54 | ||
51 | #ifndef CONFIG_CPU_S3C2412_ONLY | 55 | #ifndef CONFIG_CPU_S3C2412_ONLY |
52 | void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO; | 56 | void __iomem *s3c24xx_va_gpio2 = S3C24XX_VA_GPIO; |
@@ -136,7 +140,7 @@ static void s3c2412_hard_reset(void) | |||
136 | * machine specific initialisation. | 140 | * machine specific initialisation. |
137 | */ | 141 | */ |
138 | 142 | ||
139 | void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size) | 143 | void __init s3c2412_map_io(void) |
140 | { | 144 | { |
141 | /* move base of IO */ | 145 | /* move base of IO */ |
142 | 146 | ||
@@ -153,20 +157,25 @@ void __init s3c2412_map_io(struct map_desc *mach_desc, int mach_size) | |||
153 | /* register our io-tables */ | 157 | /* register our io-tables */ |
154 | 158 | ||
155 | iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc)); | 159 | iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc)); |
156 | iotable_init(mach_desc, mach_size); | ||
157 | } | 160 | } |
158 | 161 | ||
159 | void __init s3c2412_init_clocks(int xtal) | 162 | void __init_or_cpufreq s3c2412_setup_clocks(void) |
160 | { | 163 | { |
164 | struct clk *xtal_clk; | ||
161 | unsigned long tmp; | 165 | unsigned long tmp; |
166 | unsigned long xtal; | ||
162 | unsigned long fclk; | 167 | unsigned long fclk; |
163 | unsigned long hclk; | 168 | unsigned long hclk; |
164 | unsigned long pclk; | 169 | unsigned long pclk; |
165 | 170 | ||
171 | xtal_clk = clk_get(NULL, "xtal"); | ||
172 | xtal = clk_get_rate(xtal_clk); | ||
173 | clk_put(xtal_clk); | ||
174 | |||
166 | /* now we've got our machine bits initialised, work out what | 175 | /* now we've got our machine bits initialised, work out what |
167 | * clocks we've got */ | 176 | * clocks we've got */ |
168 | 177 | ||
169 | fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2); | 178 | fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2); |
170 | 179 | ||
171 | clk_mpll.rate = fclk; | 180 | clk_mpll.rate = fclk; |
172 | 181 | ||
@@ -183,11 +192,17 @@ void __init s3c2412_init_clocks(int xtal) | |||
183 | printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", | 192 | printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", |
184 | print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); | 193 | print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); |
185 | 194 | ||
195 | s3c24xx_setup_clocks(fclk, hclk, pclk); | ||
196 | } | ||
197 | |||
198 | void __init s3c2412_init_clocks(int xtal) | ||
199 | { | ||
186 | /* initialise the clocks here, to allow other things like the | 200 | /* initialise the clocks here, to allow other things like the |
187 | * console to use them | 201 | * console to use them |
188 | */ | 202 | */ |
189 | 203 | ||
190 | s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); | 204 | s3c24xx_register_baseclocks(xtal); |
205 | s3c2412_setup_clocks(); | ||
191 | s3c2412_baseclk_add(); | 206 | s3c2412_baseclk_add(); |
192 | } | 207 | } |
193 | 208 | ||
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig index 0429d255b0d8..cde5ae9a4340 100644 --- a/arch/arm/mach-s3c2440/Kconfig +++ b/arch/arm/mach-s3c2440/Kconfig | |||
@@ -29,8 +29,10 @@ menu "S3C2440 Machines" | |||
29 | config MACH_ANUBIS | 29 | config MACH_ANUBIS |
30 | bool "Simtec Electronics ANUBIS" | 30 | bool "Simtec Electronics ANUBIS" |
31 | select CPU_S3C2440 | 31 | select CPU_S3C2440 |
32 | select S3C24XX_DCLK | ||
32 | select PM_SIMTEC if PM | 33 | select PM_SIMTEC if PM |
33 | select HAVE_PATA_PLATFORM | 34 | select HAVE_PATA_PLATFORM |
35 | select S3C24XX_GPIO_EXTRA64 | ||
34 | help | 36 | help |
35 | Say Y here if you are using the Simtec Electronics ANUBIS | 37 | Say Y here if you are using the Simtec Electronics ANUBIS |
36 | development system | 38 | development system |
@@ -38,7 +40,9 @@ config MACH_ANUBIS | |||
38 | config MACH_OSIRIS | 40 | config MACH_OSIRIS |
39 | bool "Simtec IM2440D20 (OSIRIS) module" | 41 | bool "Simtec IM2440D20 (OSIRIS) module" |
40 | select CPU_S3C2440 | 42 | select CPU_S3C2440 |
43 | select S3C24XX_DCLK | ||
41 | select PM_SIMTEC if PM | 44 | select PM_SIMTEC if PM |
45 | select S3C24XX_GPIO_EXTRA128 | ||
42 | help | 46 | help |
43 | Say Y here if you are using the Simtec IM2440D20 module, also | 47 | Say Y here if you are using the Simtec IM2440D20 module, also |
44 | known as the Osiris. | 48 | known as the Osiris. |
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c index 334379bdfc6e..b05d56e230a1 100644 --- a/arch/arm/mach-s3c2440/mach-anubis.c +++ b/arch/arm/mach-s3c2440/mach-anubis.c | |||
@@ -40,6 +40,7 @@ | |||
40 | #include <mach/regs-mem.h> | 40 | #include <mach/regs-mem.h> |
41 | #include <mach/regs-lcd.h> | 41 | #include <mach/regs-lcd.h> |
42 | #include <plat/nand.h> | 42 | #include <plat/nand.h> |
43 | #include <plat/iic.h> | ||
43 | 44 | ||
44 | #include <linux/mtd/mtd.h> | 45 | #include <linux/mtd/mtd.h> |
45 | #include <linux/mtd/nand.h> | 46 | #include <linux/mtd/nand.h> |
@@ -366,6 +367,8 @@ static struct sm501_initdata anubis_sm501_initdata = { | |||
366 | .mask = 0, | 367 | .mask = 0, |
367 | }, | 368 | }, |
368 | 369 | ||
370 | .devices = SM501_USE_GPIO, | ||
371 | |||
369 | /* set the SDRAM and bus clocks */ | 372 | /* set the SDRAM and bus clocks */ |
370 | .mclk = 72 * MHZ, | 373 | .mclk = 72 * MHZ, |
371 | .m1xclk = 144 * MHZ, | 374 | .m1xclk = 144 * MHZ, |
@@ -373,10 +376,12 @@ static struct sm501_initdata anubis_sm501_initdata = { | |||
373 | 376 | ||
374 | static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = { | 377 | static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = { |
375 | [0] = { | 378 | [0] = { |
379 | .bus_num = 1, | ||
376 | .pin_scl = 44, | 380 | .pin_scl = 44, |
377 | .pin_sda = 45, | 381 | .pin_sda = 45, |
378 | }, | 382 | }, |
379 | [1] = { | 383 | [1] = { |
384 | .bus_num = 2, | ||
380 | .pin_scl = 40, | 385 | .pin_scl = 40, |
381 | .pin_sda = 41, | 386 | .pin_sda = 41, |
382 | }, | 387 | }, |
@@ -384,6 +389,7 @@ static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = { | |||
384 | 389 | ||
385 | static struct sm501_platdata anubis_sm501_platdata = { | 390 | static struct sm501_platdata anubis_sm501_platdata = { |
386 | .init = &anubis_sm501_initdata, | 391 | .init = &anubis_sm501_initdata, |
392 | .gpio_base = -1, | ||
387 | .gpio_i2c = anubis_sm501_gpio_i2c, | 393 | .gpio_i2c = anubis_sm501_gpio_i2c, |
388 | .gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c), | 394 | .gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c), |
389 | }; | 395 | }; |
@@ -404,7 +410,7 @@ static struct platform_device *anubis_devices[] __initdata = { | |||
404 | &s3c_device_usb, | 410 | &s3c_device_usb, |
405 | &s3c_device_wdt, | 411 | &s3c_device_wdt, |
406 | &s3c_device_adc, | 412 | &s3c_device_adc, |
407 | &s3c_device_i2c, | 413 | &s3c_device_i2c0, |
408 | &s3c_device_rtc, | 414 | &s3c_device_rtc, |
409 | &s3c_device_nand, | 415 | &s3c_device_nand, |
410 | &anubis_device_ide0, | 416 | &anubis_device_ide0, |
@@ -468,6 +474,7 @@ static void __init anubis_map_io(void) | |||
468 | 474 | ||
469 | static void __init anubis_init(void) | 475 | static void __init anubis_init(void) |
470 | { | 476 | { |
477 | s3c_i2c0_set_platdata(NULL); | ||
471 | platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices)); | 478 | platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices)); |
472 | 479 | ||
473 | i2c_register_board_info(0, anubis_i2c_devs, | 480 | i2c_register_board_info(0, anubis_i2c_devs, |
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c index 07b42a0207d1..0a6d0a5d961b 100644 --- a/arch/arm/mach-s3c2440/mach-at2440evb.c +++ b/arch/arm/mach-s3c2440/mach-at2440evb.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <asm/mach/irq.h> | 28 | #include <asm/mach/irq.h> |
29 | 29 | ||
30 | #include <mach/hardware.h> | 30 | #include <mach/hardware.h> |
31 | #include <mach/fb.h> | ||
31 | #include <asm/irq.h> | 32 | #include <asm/irq.h> |
32 | #include <asm/mach-types.h> | 33 | #include <asm/mach-types.h> |
33 | 34 | ||
@@ -36,6 +37,7 @@ | |||
36 | #include <mach/regs-mem.h> | 37 | #include <mach/regs-mem.h> |
37 | #include <mach/regs-lcd.h> | 38 | #include <mach/regs-lcd.h> |
38 | #include <plat/nand.h> | 39 | #include <plat/nand.h> |
40 | #include <plat/iic.h> | ||
39 | 41 | ||
40 | #include <linux/mtd/mtd.h> | 42 | #include <linux/mtd/mtd.h> |
41 | #include <linux/mtd/nand.h> | 43 | #include <linux/mtd/nand.h> |
@@ -45,6 +47,7 @@ | |||
45 | #include <plat/clock.h> | 47 | #include <plat/clock.h> |
46 | #include <plat/devs.h> | 48 | #include <plat/devs.h> |
47 | #include <plat/cpu.h> | 49 | #include <plat/cpu.h> |
50 | #include <asm/plat-s3c24xx/mci.h> | ||
48 | 51 | ||
49 | static struct map_desc at2440evb_iodesc[] __initdata = { | 52 | static struct map_desc at2440evb_iodesc[] __initdata = { |
50 | /* Nothing here */ | 53 | /* Nothing here */ |
@@ -162,19 +165,60 @@ static struct platform_device at2440evb_device_eth = { | |||
162 | }, | 165 | }, |
163 | }; | 166 | }; |
164 | 167 | ||
168 | static struct s3c24xx_mci_pdata at2440evb_mci_pdata = { | ||
169 | .gpio_detect = S3C2410_GPG10, | ||
170 | }; | ||
171 | |||
172 | /* 7" LCD panel */ | ||
173 | |||
174 | static struct s3c2410fb_display at2440evb_lcd_cfg __initdata = { | ||
175 | |||
176 | .lcdcon5 = S3C2410_LCDCON5_FRM565 | | ||
177 | S3C2410_LCDCON5_INVVLINE | | ||
178 | S3C2410_LCDCON5_INVVFRAME | | ||
179 | S3C2410_LCDCON5_PWREN | | ||
180 | S3C2410_LCDCON5_HWSWP, | ||
181 | |||
182 | .type = S3C2410_LCDCON1_TFT, | ||
183 | |||
184 | .width = 800, | ||
185 | .height = 480, | ||
186 | |||
187 | .pixclock = 33333, /* HCLK 60 MHz, divisor 2 */ | ||
188 | .xres = 800, | ||
189 | .yres = 480, | ||
190 | .bpp = 16, | ||
191 | .left_margin = 88, | ||
192 | .right_margin = 40, | ||
193 | .hsync_len = 128, | ||
194 | .upper_margin = 32, | ||
195 | .lower_margin = 11, | ||
196 | .vsync_len = 2, | ||
197 | }; | ||
198 | |||
199 | static struct s3c2410fb_mach_info at2440evb_fb_info __initdata = { | ||
200 | .displays = &at2440evb_lcd_cfg, | ||
201 | .num_displays = 1, | ||
202 | .default_display = 0, | ||
203 | }; | ||
204 | |||
165 | static struct platform_device *at2440evb_devices[] __initdata = { | 205 | static struct platform_device *at2440evb_devices[] __initdata = { |
166 | &s3c_device_usb, | 206 | &s3c_device_usb, |
167 | &s3c_device_wdt, | 207 | &s3c_device_wdt, |
168 | &s3c_device_adc, | 208 | &s3c_device_adc, |
169 | &s3c_device_i2c, | 209 | &s3c_device_i2c0, |
170 | &s3c_device_rtc, | 210 | &s3c_device_rtc, |
171 | &s3c_device_nand, | 211 | &s3c_device_nand, |
212 | &s3c_device_sdi, | ||
213 | &s3c_device_lcd, | ||
172 | &at2440evb_device_eth, | 214 | &at2440evb_device_eth, |
173 | }; | 215 | }; |
174 | 216 | ||
175 | static void __init at2440evb_map_io(void) | 217 | static void __init at2440evb_map_io(void) |
176 | { | 218 | { |
177 | s3c_device_nand.dev.platform_data = &at2440evb_nand_info; | 219 | s3c_device_nand.dev.platform_data = &at2440evb_nand_info; |
220 | s3c_device_sdi.name = "s3c2440-sdi"; | ||
221 | s3c_device_sdi.dev.platform_data = &at2440evb_mci_pdata; | ||
178 | 222 | ||
179 | s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc)); | 223 | s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc)); |
180 | s3c24xx_init_clocks(16934400); | 224 | s3c24xx_init_clocks(16934400); |
@@ -183,6 +227,9 @@ static void __init at2440evb_map_io(void) | |||
183 | 227 | ||
184 | static void __init at2440evb_init(void) | 228 | static void __init at2440evb_init(void) |
185 | { | 229 | { |
230 | s3c24xx_fb_set_platdata(&at2440evb_fb_info); | ||
231 | s3c_i2c0_set_platdata(NULL); | ||
232 | |||
186 | platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices)); | 233 | platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices)); |
187 | } | 234 | } |
188 | 235 | ||
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c index a546307fd53d..7aeaa972d7f5 100644 --- a/arch/arm/mach-s3c2440/mach-nexcoder.c +++ b/arch/arm/mach-s3c2440/mach-nexcoder.c | |||
@@ -37,6 +37,7 @@ | |||
37 | //#include <asm/debug-ll.h> | 37 | //#include <asm/debug-ll.h> |
38 | #include <mach/regs-gpio.h> | 38 | #include <mach/regs-gpio.h> |
39 | #include <plat/regs-serial.h> | 39 | #include <plat/regs-serial.h> |
40 | #include <plat/iic.h> | ||
40 | 41 | ||
41 | #include <plat/s3c2410.h> | 42 | #include <plat/s3c2410.h> |
42 | #include <plat/s3c2440.h> | 43 | #include <plat/s3c2440.h> |
@@ -107,7 +108,7 @@ static struct platform_device *nexcoder_devices[] __initdata = { | |||
107 | &s3c_device_usb, | 108 | &s3c_device_usb, |
108 | &s3c_device_lcd, | 109 | &s3c_device_lcd, |
109 | &s3c_device_wdt, | 110 | &s3c_device_wdt, |
110 | &s3c_device_i2c, | 111 | &s3c_device_i2c0, |
111 | &s3c_device_iis, | 112 | &s3c_device_iis, |
112 | &s3c_device_rtc, | 113 | &s3c_device_rtc, |
113 | &s3c_device_camif, | 114 | &s3c_device_camif, |
@@ -142,6 +143,7 @@ static void __init nexcoder_map_io(void) | |||
142 | 143 | ||
143 | static void __init nexcoder_init(void) | 144 | static void __init nexcoder_init(void) |
144 | { | 145 | { |
146 | s3c_i2c0_set_platdata(NULL); | ||
145 | platform_add_devices(nexcoder_devices, ARRAY_SIZE(nexcoder_devices)); | 147 | platform_add_devices(nexcoder_devices, ARRAY_SIZE(nexcoder_devices)); |
146 | }; | 148 | }; |
147 | 149 | ||
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c index 884a3c7ae75f..41a00f57e5da 100644 --- a/arch/arm/mach-s3c2440/mach-osiris.c +++ b/arch/arm/mach-s3c2440/mach-osiris.c | |||
@@ -38,6 +38,7 @@ | |||
38 | #include <mach/regs-mem.h> | 38 | #include <mach/regs-mem.h> |
39 | #include <mach/regs-lcd.h> | 39 | #include <mach/regs-lcd.h> |
40 | #include <plat/nand.h> | 40 | #include <plat/nand.h> |
41 | #include <plat/iic.h> | ||
41 | 42 | ||
42 | #include <linux/mtd/mtd.h> | 43 | #include <linux/mtd/mtd.h> |
43 | #include <linux/mtd/nand.h> | 44 | #include <linux/mtd/nand.h> |
@@ -335,7 +336,7 @@ static struct i2c_board_info osiris_i2c_devs[] __initdata = { | |||
335 | /* Standard Osiris devices */ | 336 | /* Standard Osiris devices */ |
336 | 337 | ||
337 | static struct platform_device *osiris_devices[] __initdata = { | 338 | static struct platform_device *osiris_devices[] __initdata = { |
338 | &s3c_device_i2c, | 339 | &s3c_device_i2c0, |
339 | &s3c_device_wdt, | 340 | &s3c_device_wdt, |
340 | &s3c_device_nand, | 341 | &s3c_device_nand, |
341 | &osiris_pcmcia, | 342 | &osiris_pcmcia, |
@@ -398,6 +399,8 @@ static void __init osiris_init(void) | |||
398 | sysdev_class_register(&osiris_pm_sysclass); | 399 | sysdev_class_register(&osiris_pm_sysclass); |
399 | sysdev_register(&osiris_pm_sysdev); | 400 | sysdev_register(&osiris_pm_sysdev); |
400 | 401 | ||
402 | s3c_i2c0_set_platdata(NULL); | ||
403 | |||
401 | i2c_register_board_info(0, osiris_i2c_devs, | 404 | i2c_register_board_info(0, osiris_i2c_devs, |
402 | ARRAY_SIZE(osiris_i2c_devs)); | 405 | ARRAY_SIZE(osiris_i2c_devs)); |
403 | 406 | ||
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c index fbd081de592f..12d378f84ad2 100644 --- a/arch/arm/mach-s3c2440/mach-rx3715.c +++ b/arch/arm/mach-s3c2440/mach-rx3715.c | |||
@@ -179,7 +179,7 @@ static struct platform_device *rx3715_devices[] __initdata = { | |||
179 | &s3c_device_usb, | 179 | &s3c_device_usb, |
180 | &s3c_device_lcd, | 180 | &s3c_device_lcd, |
181 | &s3c_device_wdt, | 181 | &s3c_device_wdt, |
182 | &s3c_device_i2c, | 182 | &s3c_device_i2c0, |
183 | &s3c_device_iis, | 183 | &s3c_device_iis, |
184 | &s3c_device_nand, | 184 | &s3c_device_nand, |
185 | }; | 185 | }; |
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c index fefeaaa4155f..db6eafbd4d90 100644 --- a/arch/arm/mach-s3c2440/mach-smdk2440.c +++ b/arch/arm/mach-s3c2440/mach-smdk2440.c | |||
@@ -37,6 +37,7 @@ | |||
37 | 37 | ||
38 | #include <mach/idle.h> | 38 | #include <mach/idle.h> |
39 | #include <mach/fb.h> | 39 | #include <mach/fb.h> |
40 | #include <plat/iic.h> | ||
40 | 41 | ||
41 | #include <plat/s3c2410.h> | 42 | #include <plat/s3c2410.h> |
42 | #include <plat/s3c2440.h> | 43 | #include <plat/s3c2440.h> |
@@ -152,7 +153,7 @@ static struct platform_device *smdk2440_devices[] __initdata = { | |||
152 | &s3c_device_usb, | 153 | &s3c_device_usb, |
153 | &s3c_device_lcd, | 154 | &s3c_device_lcd, |
154 | &s3c_device_wdt, | 155 | &s3c_device_wdt, |
155 | &s3c_device_i2c, | 156 | &s3c_device_i2c0, |
156 | &s3c_device_iis, | 157 | &s3c_device_iis, |
157 | }; | 158 | }; |
158 | 159 | ||
@@ -166,6 +167,7 @@ static void __init smdk2440_map_io(void) | |||
166 | static void __init smdk2440_machine_init(void) | 167 | static void __init smdk2440_machine_init(void) |
167 | { | 168 | { |
168 | s3c24xx_fb_set_platdata(&smdk2440_fb_info); | 169 | s3c24xx_fb_set_platdata(&smdk2440_fb_info); |
170 | s3c_i2c0_set_platdata(NULL); | ||
169 | 171 | ||
170 | platform_add_devices(smdk2440_devices, ARRAY_SIZE(smdk2440_devices)); | 172 | platform_add_devices(smdk2440_devices, ARRAY_SIZE(smdk2440_devices)); |
171 | smdk_machine_init(); | 173 | smdk_machine_init(); |
diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig index 14252f573754..212141baebec 100644 --- a/arch/arm/mach-s3c2443/Kconfig +++ b/arch/arm/mach-s3c2443/Kconfig | |||
@@ -24,6 +24,7 @@ config MACH_SMDK2443 | |||
24 | bool "SMDK2443" | 24 | bool "SMDK2443" |
25 | select CPU_S3C2443 | 25 | select CPU_S3C2443 |
26 | select MACH_SMDK | 26 | select MACH_SMDK |
27 | select S3C_DEV_HSMMC | ||
27 | help | 28 | help |
28 | Say Y here if you are using an SMDK2443 | 29 | Say Y here if you are using an SMDK2443 |
29 | 30 | ||
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index f854e7385e3c..2785d69c95b0 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c | |||
@@ -29,7 +29,6 @@ | |||
29 | #include <linux/sysdev.h> | 29 | #include <linux/sysdev.h> |
30 | #include <linux/clk.h> | 30 | #include <linux/clk.h> |
31 | #include <linux/mutex.h> | 31 | #include <linux/mutex.h> |
32 | #include <linux/delay.h> | ||
33 | #include <linux/serial_core.h> | 32 | #include <linux/serial_core.h> |
34 | #include <linux/io.h> | 33 | #include <linux/io.h> |
35 | 34 | ||
@@ -39,6 +38,8 @@ | |||
39 | 38 | ||
40 | #include <mach/regs-s3c2443-clock.h> | 39 | #include <mach/regs-s3c2443-clock.h> |
41 | 40 | ||
41 | #include <plat/cpu-freq.h> | ||
42 | |||
42 | #include <plat/s3c2443.h> | 43 | #include <plat/s3c2443.h> |
43 | #include <plat/clock.h> | 44 | #include <plat/clock.h> |
44 | #include <plat/cpu.h> | 45 | #include <plat/cpu.h> |
@@ -145,12 +146,6 @@ static unsigned long s3c2443_roundrate_clksrc256(struct clk *clk, | |||
145 | 146 | ||
146 | /* clock selections */ | 147 | /* clock selections */ |
147 | 148 | ||
148 | /* CPU EXTCLK input */ | ||
149 | static struct clk clk_ext = { | ||
150 | .name = "ext", | ||
151 | .id = -1, | ||
152 | }; | ||
153 | |||
154 | static struct clk clk_mpllref = { | 149 | static struct clk clk_mpllref = { |
155 | .name = "mpllref", | 150 | .name = "mpllref", |
156 | .parent = &clk_xtal, | 151 | .parent = &clk_xtal, |
@@ -165,14 +160,6 @@ static struct clk clk_mpll = { | |||
165 | }; | 160 | }; |
166 | #endif | 161 | #endif |
167 | 162 | ||
168 | static struct clk clk_epllref; | ||
169 | |||
170 | static struct clk clk_epll = { | ||
171 | .name = "epll", | ||
172 | .parent = &clk_epllref, | ||
173 | .id = -1, | ||
174 | }; | ||
175 | |||
176 | static struct clk clk_i2s_ext = { | 163 | static struct clk clk_i2s_ext = { |
177 | .name = "i2s-ext", | 164 | .name = "i2s-ext", |
178 | .id = -1, | 165 | .id = -1, |
@@ -1011,22 +998,20 @@ static struct clk *clks[] __initdata = { | |||
1011 | &clk_prediv, | 998 | &clk_prediv, |
1012 | }; | 999 | }; |
1013 | 1000 | ||
1014 | void __init s3c2443_init_clocks(int xtal) | 1001 | void __init_or_cpufreq s3c2443_setup_clocks(void) |
1015 | { | 1002 | { |
1016 | unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); | ||
1017 | unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); | 1003 | unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); |
1018 | unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); | 1004 | unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); |
1005 | struct clk *xtal_clk; | ||
1006 | unsigned long xtal; | ||
1019 | unsigned long pll; | 1007 | unsigned long pll; |
1020 | unsigned long fclk; | 1008 | unsigned long fclk; |
1021 | unsigned long hclk; | 1009 | unsigned long hclk; |
1022 | unsigned long pclk; | 1010 | unsigned long pclk; |
1023 | struct clk *clkp; | ||
1024 | int ret; | ||
1025 | int ptr; | ||
1026 | 1011 | ||
1027 | /* s3c2443 parents h and p clocks from prediv */ | 1012 | xtal_clk = clk_get(NULL, "xtal"); |
1028 | clk_h.parent = &clk_prediv; | 1013 | xtal = clk_get_rate(xtal_clk); |
1029 | clk_p.parent = &clk_prediv; | 1014 | clk_put(xtal_clk); |
1030 | 1015 | ||
1031 | pll = s3c2443_get_mpll(mpllcon, xtal); | 1016 | pll = s3c2443_get_mpll(mpllcon, xtal); |
1032 | clk_msysclk.rate = pll; | 1017 | clk_msysclk.rate = pll; |
@@ -1036,13 +1021,29 @@ void __init s3c2443_init_clocks(int xtal) | |||
1036 | hclk /= s3c2443_get_hdiv(clkdiv0); | 1021 | hclk /= s3c2443_get_hdiv(clkdiv0); |
1037 | pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); | 1022 | pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); |
1038 | 1023 | ||
1039 | s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); | 1024 | s3c24xx_setup_clocks(fclk, hclk, pclk); |
1040 | 1025 | ||
1041 | printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n", | 1026 | printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n", |
1042 | (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on", | 1027 | (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on", |
1043 | print_mhz(pll), print_mhz(fclk), | 1028 | print_mhz(pll), print_mhz(fclk), |
1044 | print_mhz(hclk), print_mhz(pclk)); | 1029 | print_mhz(hclk), print_mhz(pclk)); |
1045 | 1030 | ||
1031 | s3c24xx_setup_clocks(fclk, hclk, pclk); | ||
1032 | } | ||
1033 | |||
1034 | void __init s3c2443_init_clocks(int xtal) | ||
1035 | { | ||
1036 | struct clk *clkp; | ||
1037 | unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); | ||
1038 | int ret; | ||
1039 | int ptr; | ||
1040 | |||
1041 | /* s3c2443 parents h and p clocks from prediv */ | ||
1042 | clk_h.parent = &clk_prediv; | ||
1043 | clk_p.parent = &clk_prediv; | ||
1044 | |||
1045 | s3c24xx_register_baseclocks(xtal); | ||
1046 | s3c2443_setup_clocks(); | ||
1046 | s3c2443_clk_initparents(); | 1047 | s3c2443_clk_initparents(); |
1047 | 1048 | ||
1048 | for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { | 1049 | for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { |
@@ -1056,7 +1057,7 @@ void __init s3c2443_init_clocks(int xtal) | |||
1056 | } | 1057 | } |
1057 | 1058 | ||
1058 | clk_epll.rate = s3c2443_get_epll(epllcon, xtal); | 1059 | clk_epll.rate = s3c2443_get_epll(epllcon, xtal); |
1059 | 1060 | clk_epll.parent = &clk_epllref; | |
1060 | clk_usb_bus.parent = &clk_usb_bus_host; | 1061 | clk_usb_bus.parent = &clk_usb_bus_host; |
1061 | 1062 | ||
1062 | /* ensure usb bus clock is within correct rate of 48MHz */ | 1063 | /* ensure usb bus clock is within correct rate of 48MHz */ |
@@ -1105,4 +1106,6 @@ void __init s3c2443_init_clocks(int xtal) | |||
1105 | 1106 | ||
1106 | (clkp->enable)(clkp, 0); | 1107 | (clkp->enable)(clkp, 0); |
1107 | } | 1108 | } |
1109 | |||
1110 | s3c_pwmclk_init(); | ||
1108 | } | 1111 | } |
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c index a7fe65f3dcc1..039a46243105 100644 --- a/arch/arm/mach-s3c2443/mach-smdk2443.c +++ b/arch/arm/mach-s3c2443/mach-smdk2443.c | |||
@@ -37,6 +37,7 @@ | |||
37 | 37 | ||
38 | #include <mach/idle.h> | 38 | #include <mach/idle.h> |
39 | #include <mach/fb.h> | 39 | #include <mach/fb.h> |
40 | #include <plat/iic.h> | ||
40 | 41 | ||
41 | #include <plat/s3c2410.h> | 42 | #include <plat/s3c2410.h> |
42 | #include <plat/s3c2440.h> | 43 | #include <plat/s3c2440.h> |
@@ -103,8 +104,8 @@ static struct s3c2410_uartcfg smdk2443_uartcfgs[] __initdata = { | |||
103 | 104 | ||
104 | static struct platform_device *smdk2443_devices[] __initdata = { | 105 | static struct platform_device *smdk2443_devices[] __initdata = { |
105 | &s3c_device_wdt, | 106 | &s3c_device_wdt, |
106 | &s3c_device_i2c, | 107 | &s3c_device_i2c0, |
107 | &s3c_device_hsmmc, | 108 | &s3c_device_hsmmc0, |
108 | }; | 109 | }; |
109 | 110 | ||
110 | static void __init smdk2443_map_io(void) | 111 | static void __init smdk2443_map_io(void) |
@@ -116,6 +117,7 @@ static void __init smdk2443_map_io(void) | |||
116 | 117 | ||
117 | static void __init smdk2443_machine_init(void) | 118 | static void __init smdk2443_machine_init(void) |
118 | { | 119 | { |
120 | s3c_i2c0_set_platdata(NULL); | ||
119 | platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices)); | 121 | platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices)); |
120 | smdk_machine_init(); | 122 | smdk_machine_init(); |
121 | } | 123 | } |
diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c index bbeddf9ddcb1..ce2ec3298930 100644 --- a/arch/arm/mach-s3c2443/s3c2443.c +++ b/arch/arm/mach-s3c2443/s3c2443.c | |||
@@ -81,10 +81,9 @@ void __init s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no) | |||
81 | * machine specific initialisation. | 81 | * machine specific initialisation. |
82 | */ | 82 | */ |
83 | 83 | ||
84 | void __init s3c2443_map_io(struct map_desc *mach_desc, int mach_size) | 84 | void __init s3c2443_map_io(void) |
85 | { | 85 | { |
86 | iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc)); | 86 | iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc)); |
87 | iotable_init(mach_desc, mach_size); | ||
88 | } | 87 | } |
89 | 88 | ||
90 | /* need to register class before we actually register the device, and | 89 | /* need to register class before we actually register the device, and |
diff --git a/arch/arm/mach-s3c24a0/include/mach/debug-macro.S b/arch/arm/mach-s3c24a0/include/mach/debug-macro.S new file mode 100644 index 000000000000..f0ef0ab475f6 --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/debug-macro.S | |||
@@ -0,0 +1,28 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/debug-macro.S | ||
2 | * | ||
3 | * This program is free software; you can redistribute it and/or modify | ||
4 | * it under the terms of the GNU General Public License version 2 as | ||
5 | * published by the Free Software Foundation. | ||
6 | */ | ||
7 | |||
8 | /* pull in the relevant register and map files. */ | ||
9 | |||
10 | #include <mach/map.h> | ||
11 | #include <plat/regs-serial.h> | ||
12 | |||
13 | .macro addruart, rx | ||
14 | mrc p15, 0, \rx, c1, c0 | ||
15 | tst \rx, #1 | ||
16 | ldreq \rx, = S3C24XX_PA_UART | ||
17 | ldrne \rx, = S3C24XX_VA_UART | ||
18 | #if CONFIG_DEBUG_S3C_UART != 0 | ||
19 | add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART) | ||
20 | #endif | ||
21 | .endm | ||
22 | |||
23 | /* include the reset of the code which will do the work, we're only | ||
24 | * compiling for a single cpu processor type so the default of s3c2440 | ||
25 | * will be fine with us. | ||
26 | */ | ||
27 | |||
28 | #include <plat/debug-macro.S> | ||
diff --git a/arch/arm/mach-s3c24a0/include/mach/irqs.h b/arch/arm/mach-s3c24a0/include/mach/irqs.h new file mode 100644 index 000000000000..ae8c0e359783 --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/irqs.h | |||
@@ -0,0 +1,115 @@ | |||
1 | /* linux/arch/arm/mach-s3c24a0/include/mach/irqs.h | ||
2 | * | ||
3 | * Copyright (c) 2003-2005 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | |||
12 | #ifndef __ASM_ARCH_24A0_IRQS_H | ||
13 | #define __ASM_ARCH_24A0_IRQS_H __FILE__ | ||
14 | |||
15 | #define IRQ_EINT0t2 S3C2410_IRQ(0) /* 16 */ | ||
16 | /* for generic entry-macro.S */ | ||
17 | #define IRQ_EINT0 IRQ_EINT0t2 | ||
18 | |||
19 | #define IRQ_EINT3t6 S3C2410_IRQ(1) | ||
20 | #define IRQ_EINT7t10 S3C2410_IRQ(2) | ||
21 | #define IRQ_EINT11t14 S3C2410_IRQ(3) | ||
22 | #define IRQ_EINT15t18 S3C2410_IRQ(4) /* 20 */ | ||
23 | #define IRQ_TICK S3C2410_IRQ(5) | ||
24 | #define IRQ_DCTQ S3C2410_IRQ(6) | ||
25 | #define IRQ_MC S3C2410_IRQ(7) | ||
26 | #define IRQ_ME S3C2410_IRQ(8) /* 24 */ | ||
27 | #define IRQ_KEYPAD S3C2410_IRQ(9) | ||
28 | #define IRQ_TIMER0 S3C2410_IRQ(10) | ||
29 | #define IRQ_TIMER1 S3C2410_IRQ(11) | ||
30 | #define IRQ_TIMER2 S3C2410_IRQ(12) | ||
31 | #define IRQ_TIMER3_4 S3C2410_IRQ(13) | ||
32 | #define IRQ_OS_TIMER IRQ_TIMER3_4 | ||
33 | #define IRQ_LCD S3C2410_IRQ(14) | ||
34 | #define IRQ_CAM_C S3C2410_IRQ(15) | ||
35 | #define IRQ_WDT_BATFLT S3C2410_IRQ(16) /* 32 */ | ||
36 | #define IRQ_UART0 S3C2410_IRQ(17) | ||
37 | #define IRQ_CAM_P S3C2410_IRQ(18) | ||
38 | #define IRQ_MODEM S3C2410_IRQ(19) | ||
39 | #define IRQ_DMA S3C2410_IRQ(20) | ||
40 | #define IRQ_SDI S3C2410_IRQ(21) | ||
41 | #define IRQ_SPI0 S3C2410_IRQ(22) | ||
42 | #define IRQ_UART1 S3C2410_IRQ(23) | ||
43 | #define IRQ_AC97_NFLASH S3C2410_IRQ(24) /* 40 */ | ||
44 | #define IRQ_USBD S3C2410_IRQ(25) | ||
45 | #define IRQ_USBH S3C2410_IRQ(26) | ||
46 | #define IRQ_IIC S3C2410_IRQ(27) | ||
47 | #define IRQ_IRDA_MSTICK S3C2410_IRQ(28) /* 44 */ | ||
48 | #define IRQ_VLX_SPI1 S3C2410_IRQ(29) | ||
49 | #define IRQ_RTC S3C2410_IRQ(30) /* 46 */ | ||
50 | #define IRQ_ADC_PEN S3C2410_IRQ(31) | ||
51 | |||
52 | /* interrupts generated from the external interrupts sources */ | ||
53 | #define IRQ_EINT00 S3C2410_IRQ(32) /* 48 */ | ||
54 | #define IRQ_EINT1 S3C2410_IRQ(33) | ||
55 | #define IRQ_EINT2 S3C2410_IRQ(34) | ||
56 | #define IRQ_EINT3 S3C2410_IRQ(35) | ||
57 | #define IRQ_EINT4 S3C2410_IRQ(36) | ||
58 | #define IRQ_EINT5 S3C2410_IRQ(37) | ||
59 | #define IRQ_EINT6 S3C2410_IRQ(38) | ||
60 | #define IRQ_EINT7 S3C2410_IRQ(39) | ||
61 | #define IRQ_EINT8 S3C2410_IRQ(40) | ||
62 | #define IRQ_EINT9 S3C2410_IRQ(41) | ||
63 | #define IRQ_EINT10 S3C2410_IRQ(42) | ||
64 | #define IRQ_EINT11 S3C2410_IRQ(43) | ||
65 | #define IRQ_EINT12 S3C2410_IRQ(44) | ||
66 | #define IRQ_EINT13 S3C2410_IRQ(45) | ||
67 | #define IRQ_EINT14 S3C2410_IRQ(46) | ||
68 | #define IRQ_EINT15 S3C2410_IRQ(47) | ||
69 | #define IRQ_EINT16 S3C2410_IRQ(48) | ||
70 | #define IRQ_EINT17 S3C2410_IRQ(49) | ||
71 | #define IRQ_EINT18 S3C2410_IRQ(50) | ||
72 | |||
73 | /* SUB IRQS */ | ||
74 | #define IRQ_S3CUART_RX0 S3C2410_IRQ(51) /* 67 */ | ||
75 | #define IRQ_S3CUART_TX0 S3C2410_IRQ(52) | ||
76 | #define IRQ_S3CUART_ERR0 S3C2410_IRQ(53) | ||
77 | |||
78 | #define IRQ_S3CUART_RX1 S3C2410_IRQ(54) | ||
79 | #define IRQ_S3CUART_TX1 S3C2410_IRQ(55) | ||
80 | #define IRQ_S3CUART_ERR1 S3C2410_IRQ(56) | ||
81 | |||
82 | #define IRQ_S3CUART_RX2 (0x0) | ||
83 | #define IRQ_S3CUART_TX2 (0x0) | ||
84 | #define IRQ_S3CUART_ERR2 (0x0) | ||
85 | |||
86 | |||
87 | #define IRQ_IRDA S3C2410_IRQ(57) | ||
88 | #define IRQ_MSTICK S3C2410_IRQ(58) | ||
89 | #define IRQ_RESERVED0 S3C2410_IRQ(59) | ||
90 | #define IRQ_RESERVED1 S3C2410_IRQ(60) | ||
91 | #define IRQ_RESERVED2 S3C2410_IRQ(61) | ||
92 | #define IRQ_TIMER3 S3C2410_IRQ(62) | ||
93 | #define IRQ_TIMER4 S3C2410_IRQ(63) | ||
94 | #define IRQ_WDT S3C2410_IRQ(64) | ||
95 | #define IRQ_BATFLT S3C2410_IRQ(65) | ||
96 | #define IRQ_POST S3C2410_IRQ(66) | ||
97 | #define IRQ_DISP_FIFO S3C2410_IRQ(67) | ||
98 | #define IRQ_PENUP S3C2410_IRQ(68) | ||
99 | #define IRQ_PENDN S3C2410_IRQ(69) | ||
100 | #define IRQ_ADC S3C2410_IRQ(70) | ||
101 | #define IRQ_DISP_FRAME S3C2410_IRQ(71) | ||
102 | #define IRQ_NFLASH S3C2410_IRQ(72) | ||
103 | #define IRQ_AC97 S3C2410_IRQ(73) | ||
104 | #define IRQ_SPI1 S3C2410_IRQ(74) | ||
105 | #define IRQ_VLX S3C2410_IRQ(75) | ||
106 | #define IRQ_DMA0 S3C2410_IRQ(76) | ||
107 | #define IRQ_DMA1 S3C2410_IRQ(77) | ||
108 | #define IRQ_DMA2 S3C2410_IRQ(78) | ||
109 | #define IRQ_DMA3 S3C2410_IRQ(79) | ||
110 | |||
111 | #define IRQ_TC (0x0) | ||
112 | |||
113 | #define NR_IRQS (IRQ_DMA3+1) | ||
114 | |||
115 | #endif /* __ASM_ARCH_24A0_IRQS_H */ | ||
diff --git a/arch/arm/mach-s3c24a0/include/mach/map.h b/arch/arm/mach-s3c24a0/include/mach/map.h new file mode 100644 index 000000000000..a01132717e34 --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/map.h | |||
@@ -0,0 +1,85 @@ | |||
1 | /* linux/arch/arm/mach-s3c24a0/include/mach/map.h | ||
2 | * | ||
3 | * Copyright 2003,2007 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C24A0 - Memory map definitions | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_24A0_MAP_H | ||
15 | #define __ASM_ARCH_24A0_MAP_H __FILE__ | ||
16 | |||
17 | #include <plat/map-base.h> | ||
18 | #include <plat/map.h> | ||
19 | |||
20 | #define S3C24A0_PA_IO_BASE (0x40000000) | ||
21 | #define S3C24A0_PA_CLKPWR (0x40000000) | ||
22 | #define S3C24A0_PA_IRQ (0x40200000) | ||
23 | #define S3C24A0_PA_DMA (0x40400000) | ||
24 | #define S3C24A0_PA_MEMCTRL (0x40C00000) | ||
25 | #define S3C24A0_PA_NAND (0x40C00000) | ||
26 | #define S3C24A0_PA_SROM (0x40C20000) | ||
27 | #define S3C24A0_PA_SDRAM (0x40C40000) | ||
28 | #define S3C24A0_PA_BUSM (0x40CE0000) | ||
29 | #define S3C24A0_PA_USBHOST (0x41000000) | ||
30 | #define S3C24A0_PA_MODEMIF (0x41180000) | ||
31 | #define S3C24A0_PA_IRDA (0x41800000) | ||
32 | #define S3C24A0_PA_TIMER (0x44000000) | ||
33 | #define S3C24A0_PA_WATCHDOG (0x44100000) | ||
34 | #define S3C24A0_PA_RTC (0x44200000) | ||
35 | #define S3C24A0_PA_UART (0x44400000) | ||
36 | #define S3C24A0_PA_UART0 (S3C24A0_PA_UART) | ||
37 | #define S3C24A0_PA_UART1 (S3C24A0_PA_UART + 0x4000) | ||
38 | #define S3C24A0_PA_SPI (0x44500000) | ||
39 | #define S3C24A0_PA_IIC (0x44600000) | ||
40 | #define S3C24A0_PA_IIS (0x44700000) | ||
41 | #define S3C24A0_PA_GPIO (0x44800000) | ||
42 | #define S3C24A0_PA_KEYIF (0x44900000) | ||
43 | #define S3C24A0_PA_USBDEV (0x44A00000) | ||
44 | #define S3C24A0_PA_AC97 (0x45000000) | ||
45 | #define S3C24A0_PA_ADC (0x45800000) | ||
46 | #define S3C24A0_PA_SDI (0x46000000) | ||
47 | #define S3C24A0_PA_MS (0x46100000) | ||
48 | #define S3C24A0_PA_LCD (0x4A000000) | ||
49 | #define S3C24A0_PA_VPOST (0x4A100000) | ||
50 | |||
51 | /* physical addresses of all the chip-select areas */ | ||
52 | |||
53 | #define S3C24A0_CS0 (0x00000000) | ||
54 | #define S3C24A0_CS1 (0x04000000) | ||
55 | #define S3C24A0_CS2 (0x08000000) | ||
56 | #define S3C24A0_CS3 (0x0C000000) | ||
57 | #define S3C24A0_CS4 (0x10000000) | ||
58 | #define S3C24A0_CS5 (0x40000000) | ||
59 | |||
60 | #define S3C24A0_SDRAM_PA (S3C24A0_CS4) | ||
61 | |||
62 | /* Use a single interface for common resources between S3C24XX cpus */ | ||
63 | |||
64 | #define S3C24XX_PA_IRQ S3C24A0_PA_IRQ | ||
65 | #define S3C24XX_PA_MEMCTRL S3C24A0_PA_MEMCTRL | ||
66 | #define S3C24XX_PA_USBHOST S3C24A0_PA_USBHOST | ||
67 | #define S3C24XX_PA_DMA S3C24A0_PA_DMA | ||
68 | #define S3C24XX_PA_CLKPWR S3C24A0_PA_CLKPWR | ||
69 | #define S3C24XX_PA_LCD S3C24A0_PA_LCD | ||
70 | #define S3C24XX_PA_UART S3C24A0_PA_UART | ||
71 | #define S3C24XX_PA_TIMER S3C24A0_PA_TIMER | ||
72 | #define S3C24XX_PA_USBDEV S3C24A0_PA_USBDEV | ||
73 | #define S3C24XX_PA_WATCHDOG S3C24A0_PA_WATCHDOG | ||
74 | #define S3C24XX_PA_IIS S3C24A0_PA_IIS | ||
75 | #define S3C24XX_PA_GPIO S3C24A0_PA_GPIO | ||
76 | #define S3C24XX_PA_RTC S3C24A0_PA_RTC | ||
77 | #define S3C24XX_PA_ADC S3C24A0_PA_ADC | ||
78 | #define S3C24XX_PA_SPI S3C24A0_PA_SPI | ||
79 | #define S3C24XX_PA_SDI S3C24A0_PA_SDI | ||
80 | #define S3C24XX_PA_NAND S3C24A0_PA_NAND | ||
81 | |||
82 | #define S3C_PA_UART S3C24A0_PA_UART | ||
83 | #define S3C_PA_IIC S3C24A0_PA_IIC | ||
84 | |||
85 | #endif /* __ASM_ARCH_24A0_MAP_H */ | ||
diff --git a/arch/arm/mach-s3c24a0/include/mach/memory.h b/arch/arm/mach-s3c24a0/include/mach/memory.h new file mode 100644 index 000000000000..585211ca0187 --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/memory.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* linux/arch/arm/mach-s3c24a0/include/mach/memory.h | ||
2 | * from linux/include/asm-arm/arch-rpc/memory.h | ||
3 | * | ||
4 | * Copyright (C) 1996,1997,1998 Russell King. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_24A0_MEMORY_H | ||
12 | #define __ASM_ARCH_24A0_MEMORY_H __FILE__ | ||
13 | |||
14 | #define PHYS_OFFSET UL(0x10000000) | ||
15 | |||
16 | #define __virt_to_bus(x) __virt_to_phys(x) | ||
17 | #define __bus_to_virt(x) __phys_to_virt(x) | ||
18 | |||
19 | #endif | ||
diff --git a/arch/arm/mach-s3c24a0/include/mach/regs-clock.h b/arch/arm/mach-s3c24a0/include/mach/regs-clock.h new file mode 100644 index 000000000000..af2abd756c30 --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/regs-clock.h | |||
@@ -0,0 +1,88 @@ | |||
1 | /* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h | ||
2 | * | ||
3 | * Copyright (c) 2003,2004,2005,2006 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * S3C24A0 clock register definitions | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_24A0_REGS_CLOCK_H | ||
14 | #define __ASM_ARCH_24A0_REGS_CLOCK_H __FILE__ | ||
15 | |||
16 | #define S3C24A0_MPLLCON S3C2410_CLKREG(0x10) | ||
17 | #define S3C24A0_UPLLCON S3C2410_CLKREG(0x14) | ||
18 | #define S3C24A0_CLKCON S3C2410_CLKREG(0x20) | ||
19 | #define S3C24A0_CLKSRC S3C2410_CLKREG(0x24) | ||
20 | #define S3C24A0_CLKDIVN S3C2410_CLKREG(0x28) | ||
21 | |||
22 | /* CLKCON register bits */ | ||
23 | |||
24 | #define S3C24A0_CLKCON_VLX (1<<29) | ||
25 | #define S3C24A0_CLKCON_VPOST (1<<28) | ||
26 | #define S3C24A0_CLKCON_WDT (1<<27) /* reserved */ | ||
27 | #define S3C24A0_CLKCON_MPEGDCTQ (1<<26) | ||
28 | #define S3C24A0_CLKCON_VPOSTIF (1<<25) | ||
29 | #define S3C24A0_CLKCON_MPEG4IF (1<<24) | ||
30 | #define S3C24A0_CLKCON_CAM_UPLL (1<<23) | ||
31 | #define S3C24A0_CLKCON_LCDC (1<<22) | ||
32 | #define S3C24A0_CLKCON_CAM_HCLK (1<<21) | ||
33 | #define S3C24A0_CLKCON_MPEG4 (1<<20) | ||
34 | #define S3C24A0_CLKCON_KEYPAD (1<<19) | ||
35 | #define S3C24A0_CLKCON_ADC (1<<18) | ||
36 | #define S3C24A0_CLKCON_SDI (1<<17) | ||
37 | #define S3C24A0_CLKCON_MS (1<<16) /* memory stick */ | ||
38 | #define S3C24A0_CLKCON_USBD (1<<15) | ||
39 | #define S3C24A0_CLKCON_GPIO (1<<14) | ||
40 | #define S3C24A0_CLKCON_IIS (1<<13) | ||
41 | #define S3C24A0_CLKCON_IIC (1<<12) | ||
42 | #define S3C24A0_CLKCON_SPI (1<<11) | ||
43 | #define S3C24A0_CLKCON_UART1 (1<<10) | ||
44 | #define S3C24A0_CLKCON_UART0 (1<<9) | ||
45 | #define S3C24A0_CLKCON_PWMT (1<<8) | ||
46 | #define S3C24A0_CLKCON_USBH (1<<7) | ||
47 | #define S3C24A0_CLKCON_AC97 (1<<6) | ||
48 | #define S3C24A0_CLKCON_IrDA (1<<4) | ||
49 | #define S3C24A0_CLKCON_IDLE (1<<2) | ||
50 | #define S3C24A0_CLKCON_MON (1<<1) | ||
51 | #define S3C24A0_CLKCON_STOP (1<<0) | ||
52 | |||
53 | /* CLKSRC register bits */ | ||
54 | |||
55 | #define S3C24A0_CLKSRC_OSC (1<<8) /* CLKSRC */ | ||
56 | #define S3C24A0_CLKSRC_UPLL (1<<7) | ||
57 | #define S3C24A0_CLKSRC_MPLL (1<<5) | ||
58 | #define S3C24A0_CLKSRC_EXT (1<<4) | ||
59 | |||
60 | /* Use a single interface with the common code, for s3c24xx */ | ||
61 | |||
62 | #define S3C2410_MPLLCON S3C24A0_MPLLCON | ||
63 | #define S3C2410_UPLLCON S3C24A0_UPLLCON | ||
64 | #define S3C2410_CLKCON S3C24A0_CLKCON | ||
65 | #define S3C2410_CLKSLOW S3C24A0_CLKSRC | ||
66 | #define S3C2410_CLKDIVN S3C24A0_CLKDIVN | ||
67 | |||
68 | #define S3C2410_CLKCON_IDLE S3C24A0_CLKCON_IDLE | ||
69 | #define S3C2410_CLKCON_POWER S3C24A0_CLKCON_STOP | ||
70 | #define S3C2410_CLKCON_LCDC S3C24A0_CLKCON_LCDC | ||
71 | #define S3C2410_CLKCON_USBH S3C24A0_CLKCON_USBH | ||
72 | #define S3C2410_CLKCON_USBD S3C24A0_CLKCON_USBD | ||
73 | #define S3C2410_CLKCON_PWMT S3C24A0_CLKCON_PWMT | ||
74 | #define S3C2410_CLKCON_SDI S3C24A0_CLKCON_SDI | ||
75 | #define S3C2410_CLKCON_UART0 S3C24A0_CLKCON_UART0 | ||
76 | #define S3C2410_CLKCON_UART1 S3C24A0_CLKCON_UART1 | ||
77 | #define S3C2410_CLKCON_GPIO S3C24A0_CLKCON_GPIO | ||
78 | #define S3C2410_CLKCON_ADC S3C24A0_CLKCON_ADC | ||
79 | #define S3C2410_CLKCON_IIC S3C24A0_CLKCON_IIC | ||
80 | #define S3C2410_CLKCON_IIS S3C24A0_CLKCON_IIS | ||
81 | #define S3C2410_CLKCON_SPI S3C24A0_CLKCON_SPI | ||
82 | |||
83 | #define S3C2410_CLKSLOW_UCLK_OFF S3C24A0_CLKSRC_UPLL | ||
84 | #define S3C2410_CLKSLOW_MPLL_OFF S3C24A0_CLKSRC_MPLL | ||
85 | #define S3C2410_CLKSLOW_SLOW (0xFF) | ||
86 | #define S3C2410_CLKSLOW_GET_SLOWVAL(x) (0x1) | ||
87 | |||
88 | #endif /* __ASM_ARCH_24A0_REGS_CLOCK_H */ | ||
diff --git a/arch/arm/mach-s3c24a0/include/mach/regs-irq.h b/arch/arm/mach-s3c24a0/include/mach/regs-irq.h new file mode 100644 index 000000000000..6086f6f189eb --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/regs-irq.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* linux/arch/arm/mach-s3c24a0/include/mach/regs-irq.h | ||
2 | * | ||
3 | * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk> | ||
4 | * http://www.simtec.co.uk/products/SWLINUX/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | |||
12 | #ifndef ___ASM_ARCH_24A0_REGS_IRQ_H | ||
13 | #define ___ASM_ARCH_24A0_REGS_IRQ_H __FILE__ | ||
14 | |||
15 | |||
16 | #define S3C2410_EINTMASK S3C2410_EINTREG(0x034) | ||
17 | #define S3C2410_EINTPEND S3C2410_EINTREG(0X038) | ||
18 | |||
19 | #define S3C24XX_EINTMASK S3C24XX_EINTREG(0x034) | ||
20 | #define S3C24XX_EINTPEND S3C24XX_EINTREG(0X038) | ||
21 | |||
22 | #endif /* __ASM_ARCH_24A0_REGS_IRQ_H */ | ||
23 | |||
24 | |||
25 | |||
diff --git a/arch/arm/mach-s3c24a0/include/mach/system.h b/arch/arm/mach-s3c24a0/include/mach/system.h new file mode 100644 index 000000000000..bd1bd1957656 --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/system.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* linux/arch/arm/mach-s3c24a0/include/mach/system.h | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C24A0 - System function defines and includes | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <mach/hardware.h> | ||
14 | #include <asm/io.h> | ||
15 | |||
16 | #include <mach/map.h> | ||
17 | |||
18 | static void arch_idle(void) | ||
19 | { | ||
20 | /* currently no specific idle support. */ | ||
21 | } | ||
22 | |||
23 | void (*s3c24xx_reset_hook)(void); | ||
24 | |||
25 | #include <asm/plat-s3c24xx/system-reset.h> | ||
diff --git a/arch/arm/mach-s3c24a0/include/mach/tick.h b/arch/arm/mach-s3c24a0/include/mach/tick.h new file mode 100644 index 000000000000..9dea8ba6fb72 --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/tick.h | |||
@@ -0,0 +1,15 @@ | |||
1 | /* linux/arch/arm/mach-s3c24a0/include/mach/tick.h | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * S3C24A0 - timer tick support | ||
8 | */ | ||
9 | |||
10 | #define SUBSRC_TIMER4 (1 << (IRQ_TIMER4 - IRQ_S3CUART_RX0)) | ||
11 | |||
12 | static inline int s3c24xx_ostimer_pending(void) | ||
13 | { | ||
14 | return __raw_readl(S3C2410_SUBSRCPND) & SUBSRC_TIMER4; | ||
15 | } | ||
diff --git a/arch/arm/mach-s3c24a0/include/mach/timex.h b/arch/arm/mach-s3c24a0/include/mach/timex.h new file mode 100644 index 000000000000..98573424a016 --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/timex.h | |||
@@ -0,0 +1,18 @@ | |||
1 | /* linux/arch/arm/mach-s3c24a0/include/mach/timex.h | ||
2 | * | ||
3 | * Copyright (c) 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C2410 - time parameters | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_TIMEX_H | ||
14 | #define __ASM_ARCH_TIMEX_H | ||
15 | |||
16 | #define CLOCK_TICK_RATE 12000000 | ||
17 | |||
18 | #endif /* __ASM_ARCH_TIMEX_H */ | ||
diff --git a/arch/arm/mach-s3c24a0/include/mach/vmalloc.h b/arch/arm/mach-s3c24a0/include/mach/vmalloc.h new file mode 100644 index 000000000000..4d4fe4849589 --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/vmalloc.h | |||
@@ -0,0 +1,17 @@ | |||
1 | /* linux/include/asm-arm/arch-s3c24ao/vmalloc.h | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics <linux@simtec.co.uk> | ||
4 | |||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License version 2 as | ||
7 | * published by the Free Software Foundation. | ||
8 | * | ||
9 | * S3C24A0 vmalloc definition | ||
10 | */ | ||
11 | |||
12 | #ifndef __ASM_ARCH_VMALLOC_H | ||
13 | #define __ASM_ARCH_VMALLOC_H | ||
14 | |||
15 | #define VMALLOC_END (0xE0000000) | ||
16 | |||
17 | #endif /* __ASM_ARCH_VMALLOC_H */ | ||
diff --git a/arch/arm/mach-s3c6400/Kconfig b/arch/arm/mach-s3c6400/Kconfig new file mode 100644 index 000000000000..6da82b5c09ba --- /dev/null +++ b/arch/arm/mach-s3c6400/Kconfig | |||
@@ -0,0 +1,8 @@ | |||
1 | # arch/arm/mach-s3c6400/Kconfig | ||
2 | # | ||
3 | # Copyright 2008 Openmoko, Inc. | ||
4 | # Simtec Electronics, Ben Dooks <ben@simtec.co.uk> | ||
5 | # | ||
6 | # Licensed under GPLv2 | ||
7 | |||
8 | # Currently nothing here, this will be added later | ||
diff --git a/arch/arm/mach-s3c6400/Makefile b/arch/arm/mach-s3c6400/Makefile new file mode 100644 index 000000000000..8f397db25b87 --- /dev/null +++ b/arch/arm/mach-s3c6400/Makefile | |||
@@ -0,0 +1,15 @@ | |||
1 | # arch/arm/mach-s3c6400/Makefile | ||
2 | # | ||
3 | # Copyright 2008 Openmoko, Inc. | ||
4 | # Copyright 2008 Simtec Electronics | ||
5 | # | ||
6 | # Licensed under GPLv2 | ||
7 | |||
8 | obj-y := | ||
9 | obj-m := | ||
10 | obj-n := | ||
11 | obj- := | ||
12 | |||
13 | # Core support for S3C6400 system | ||
14 | |||
15 | obj-n += blank.o | ||
diff --git a/arch/arm/mach-s3c6400/Makefile.boot b/arch/arm/mach-s3c6400/Makefile.boot new file mode 100644 index 000000000000..ba41fdc0a586 --- /dev/null +++ b/arch/arm/mach-s3c6400/Makefile.boot | |||
@@ -0,0 +1,2 @@ | |||
1 | zreladdr-y := 0x50008000 | ||
2 | params_phys-y := 0x50000100 | ||
diff --git a/arch/arm/mach-s3c6400/include/mach/debug-macro.S b/arch/arm/mach-s3c6400/include/mach/debug-macro.S new file mode 100644 index 000000000000..b18ac5266dfc --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/debug-macro.S | |||
@@ -0,0 +1,39 @@ | |||
1 | /* arch/arm/mach-s3c6400/include/mach/debug-macro.S | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | /* pull in the relevant register and map files. */ | ||
14 | |||
15 | #include <mach/map.h> | ||
16 | #include <plat/regs-serial.h> | ||
17 | |||
18 | /* note, for the boot process to work we have to keep the UART | ||
19 | * virtual address aligned to an 1MiB boundary for the L1 | ||
20 | * mapping the head code makes. We keep the UART virtual address | ||
21 | * aligned and add in the offset when we load the value here. | ||
22 | */ | ||
23 | |||
24 | .macro addruart, rx | ||
25 | mrc p15, 0, \rx, c1, c0 | ||
26 | tst \rx, #1 | ||
27 | ldreq \rx, = S3C_PA_UART | ||
28 | ldrne \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff) | ||
29 | #if CONFIG_DEBUG_S3C_UART != 0 | ||
30 | add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) | ||
31 | #endif | ||
32 | .endm | ||
33 | |||
34 | /* include the reset of the code which will do the work, we're only | ||
35 | * compiling for a single cpu processor type so the default of s3c2440 | ||
36 | * will be fine with us. | ||
37 | */ | ||
38 | |||
39 | #include <plat/debug-macro.S> | ||
diff --git a/arch/arm/mach-s3c6400/include/mach/dma.h b/arch/arm/mach-s3c6400/include/mach/dma.h new file mode 100644 index 000000000000..9771ac2cb07e --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/dma.h | |||
@@ -0,0 +1,16 @@ | |||
1 | /* linux/arch/arm/mach-s3c6400/include/mach/dma.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C6400 - DMA support | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_DMA_H | ||
12 | #define __ASM_ARCH_DMA_H __FILE__ | ||
13 | |||
14 | /* currently nothing here, placeholder */ | ||
15 | |||
16 | #endif /* __ASM_ARCH_IRQ_H */ | ||
diff --git a/arch/arm/mach-s3c6400/include/mach/entry-macro.S b/arch/arm/mach-s3c6400/include/mach/entry-macro.S new file mode 100644 index 000000000000..fbd90d2cf355 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/entry-macro.S | |||
@@ -0,0 +1,44 @@ | |||
1 | /* arch/arm/mach-s3c6400/include/mach/entry-macro.S | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * | ||
8 | * Low-level IRQ helper macros for the Samsung S3C64XX series | ||
9 | * | ||
10 | * This file is licensed under the terms of the GNU General Public | ||
11 | * License version 2. This program is licensed "as is" without any | ||
12 | * warranty of any kind, whether express or implied. | ||
13 | */ | ||
14 | |||
15 | #include <asm/hardware/vic.h> | ||
16 | #include <mach/map.h> | ||
17 | #include <plat/irqs.h> | ||
18 | |||
19 | .macro disable_fiq | ||
20 | .endm | ||
21 | |||
22 | .macro get_irqnr_preamble, base, tmp | ||
23 | ldr \base, =S3C_VA_VIC0 | ||
24 | .endm | ||
25 | |||
26 | .macro arch_ret_to_user, tmp1, tmp2 | ||
27 | .endm | ||
28 | |||
29 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
30 | |||
31 | @ check the vic0 | ||
32 | mov \irqnr, # S3C_IRQ_OFFSET + 31 | ||
33 | ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] | ||
34 | teq \irqstat, #0 | ||
35 | |||
36 | @ otherwise try vic1 | ||
37 | addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0) | ||
38 | addeq \irqnr, \irqnr, #32 | ||
39 | ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] | ||
40 | teqeq \irqstat, #0 | ||
41 | |||
42 | clzne \irqstat, \irqstat | ||
43 | subne \irqnr, \irqnr, \irqstat | ||
44 | .endm | ||
diff --git a/arch/arm/mach-s3c6400/include/mach/gpio-core.h b/arch/arm/mach-s3c6400/include/mach/gpio-core.h new file mode 100644 index 000000000000..d89aae68b0a5 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/gpio-core.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* arch/arm/mach-s3c6400/include/mach/gpio-core.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C64XX - GPIO core support | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ARCH_GPIO_CORE_H | ||
16 | #define __ASM_ARCH_GPIO_CORE_H __FILE__ | ||
17 | |||
18 | /* currently we just include the platform support */ | ||
19 | #include <plat/gpio-core.h> | ||
20 | |||
21 | #endif /* __ASM_ARCH_GPIO_CORE_H */ | ||
diff --git a/arch/arm/mach-s3c6400/include/mach/gpio.h b/arch/arm/mach-s3c6400/include/mach/gpio.h new file mode 100644 index 000000000000..e8e35e8fe731 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/gpio.h | |||
@@ -0,0 +1,96 @@ | |||
1 | /* arch/arm/mach-s3c6400/include/mach/gpio.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * | ||
8 | * S3C6400 - GPIO lib support | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define gpio_get_value __gpio_get_value | ||
16 | #define gpio_set_value __gpio_set_value | ||
17 | #define gpio_cansleep __gpio_cansleep | ||
18 | #define gpio_to_irq __gpio_to_irq | ||
19 | |||
20 | /* GPIO bank sizes */ | ||
21 | #define S3C64XX_GPIO_A_NR (8) | ||
22 | #define S3C64XX_GPIO_B_NR (7) | ||
23 | #define S3C64XX_GPIO_C_NR (8) | ||
24 | #define S3C64XX_GPIO_D_NR (5) | ||
25 | #define S3C64XX_GPIO_E_NR (5) | ||
26 | #define S3C64XX_GPIO_F_NR (16) | ||
27 | #define S3C64XX_GPIO_G_NR (7) | ||
28 | #define S3C64XX_GPIO_H_NR (10) | ||
29 | #define S3C64XX_GPIO_I_NR (16) | ||
30 | #define S3C64XX_GPIO_J_NR (12) | ||
31 | #define S3C64XX_GPIO_K_NR (16) | ||
32 | #define S3C64XX_GPIO_L_NR (15) | ||
33 | #define S3C64XX_GPIO_M_NR (6) | ||
34 | #define S3C64XX_GPIO_N_NR (16) | ||
35 | #define S3C64XX_GPIO_O_NR (16) | ||
36 | #define S3C64XX_GPIO_P_NR (15) | ||
37 | #define S3C64XX_GPIO_Q_NR (9) | ||
38 | |||
39 | /* GPIO bank numbes */ | ||
40 | |||
41 | /* CONFIG_S3C_GPIO_SPACE allows the user to select extra | ||
42 | * space for debugging purposes so that any accidental | ||
43 | * change from one gpio bank to another can be caught. | ||
44 | */ | ||
45 | |||
46 | #define S3C64XX_GPIO_NEXT(__gpio) \ | ||
47 | ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) | ||
48 | |||
49 | enum s3c_gpio_number { | ||
50 | S3C64XX_GPIO_A_START = 0, | ||
51 | S3C64XX_GPIO_B_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_A), | ||
52 | S3C64XX_GPIO_C_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_B), | ||
53 | S3C64XX_GPIO_D_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_C), | ||
54 | S3C64XX_GPIO_E_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_D), | ||
55 | S3C64XX_GPIO_F_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_E), | ||
56 | S3C64XX_GPIO_G_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_F), | ||
57 | S3C64XX_GPIO_H_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_G), | ||
58 | S3C64XX_GPIO_I_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_H), | ||
59 | S3C64XX_GPIO_J_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_I), | ||
60 | S3C64XX_GPIO_K_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_J), | ||
61 | S3C64XX_GPIO_L_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_K), | ||
62 | S3C64XX_GPIO_M_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_L), | ||
63 | S3C64XX_GPIO_N_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_M), | ||
64 | S3C64XX_GPIO_O_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_N), | ||
65 | S3C64XX_GPIO_P_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_O), | ||
66 | S3C64XX_GPIO_Q_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_P), | ||
67 | }; | ||
68 | |||
69 | /* S3C64XX GPIO number definitions. */ | ||
70 | |||
71 | #define S3C64XX_GPA(_nr) (S3C64XX_GPIO_A_START + (_nr)) | ||
72 | #define S3C64XX_GPB(_nr) (S3C64XX_GPIO_B_START + (_nr)) | ||
73 | #define S3C64XX_GPC(_nr) (S3C64XX_GPIO_C_START + (_nr)) | ||
74 | #define S3C64XX_GPD(_nr) (S3C64XX_GPIO_D_START + (_nr)) | ||
75 | #define S3C64XX_GPE(_nr) (S3C64XX_GPIO_E_START + (_nr)) | ||
76 | #define S3C64XX_GPF(_nr) (S3C64XX_GPIO_F_START + (_nr)) | ||
77 | #define S3C64XX_GPG(_nr) (S3C64XX_GPIO_G_START + (_nr)) | ||
78 | #define S3C64XX_GPH(_nr) (S3C64XX_GPIO_H_START + (_nr)) | ||
79 | #define S3C64XX_GPI(_nr) (S3C64XX_GPIO_I_START + (_nr)) | ||
80 | #define S3C64XX_GPJ(_nr) (S3C64XX_GPIO_J_START + (_nr)) | ||
81 | #define S3C64XX_GPK(_nr) (S3C64XX_GPIO_K_START + (_nr)) | ||
82 | #define S3C64XX_GPL(_nr) (S3C64XX_GPIO_L_START + (_nr)) | ||
83 | #define S3C64XX_GPM(_nr) (S3C64XX_GPIO_M_START + (_nr)) | ||
84 | #define S3C64XX_GPN(_nr) (S3C64XX_GPIO_N_START + (_nr)) | ||
85 | #define S3C64XX_GPO(_nr) (S3C64XX_GPIO_O_START + (_nr)) | ||
86 | #define S3C64XX_GPP(_nr) (S3C64XX_GPIO_P_START + (_nr)) | ||
87 | #define S3C64XX_GPQ(_nr) (S3C64XX_GPIO_Q_START + (_nr)) | ||
88 | |||
89 | /* the end of the S3C64XX specific gpios */ | ||
90 | #define S3C64XX_GPIO_END (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1) | ||
91 | #define S3C_GPIO_END S3C64XX_GPIO_END | ||
92 | |||
93 | /* define the number of gpios we need to the one after the GPQ() range */ | ||
94 | #define ARCH_NR_GPIOS (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1) | ||
95 | |||
96 | #include <asm-generic/gpio.h> | ||
diff --git a/arch/arm/mach-s3c6400/include/mach/hardware.h b/arch/arm/mach-s3c6400/include/mach/hardware.h new file mode 100644 index 000000000000..862d033e57a4 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/hardware.h | |||
@@ -0,0 +1,16 @@ | |||
1 | /* linux/arch/arm/mach-s3c6400/include/mach/hardware.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C6400 - Hardware support | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_HARDWARE_H | ||
12 | #define __ASM_ARCH_HARDWARE_H __FILE__ | ||
13 | |||
14 | /* currently nothing here, placeholder */ | ||
15 | |||
16 | #endif /* __ASM_ARCH_IRQ_H */ | ||
diff --git a/arch/arm/mach-s3c6400/include/mach/irqs.h b/arch/arm/mach-s3c6400/include/mach/irqs.h new file mode 100644 index 000000000000..b38c47cffc28 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/irqs.h | |||
@@ -0,0 +1,20 @@ | |||
1 | /* linux/arch/arm/mach-s3c6400/include/mach/irqs.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C6400 - IRQ definitions | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_IRQS_H | ||
12 | #define __ASM_ARCH_IRQS_H __FILE__ | ||
13 | |||
14 | #ifndef __ASM_ARM_IRQ_H | ||
15 | #error "Do not include this directly, instead #include <asm/irq.h>" | ||
16 | #endif | ||
17 | |||
18 | #include <plat/irqs.h> | ||
19 | |||
20 | #endif /* __ASM_ARCH_IRQ_H */ | ||
diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h new file mode 100644 index 000000000000..cff27d813fc6 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/map.h | |||
@@ -0,0 +1,68 @@ | |||
1 | /* linux/arch/arm/mach-s3c6400/include/mach/map.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * | ||
8 | * S3C64XX - Memory map definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ARCH_MAP_H | ||
16 | #define __ASM_ARCH_MAP_H __FILE__ | ||
17 | |||
18 | #include <plat/map-base.h> | ||
19 | |||
20 | /* HSMMC units */ | ||
21 | #define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000)) | ||
22 | #define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0) | ||
23 | #define S3C64XX_PA_HSMMC1 S3C64XX_PA_HSMMC(1) | ||
24 | #define S3C64XX_PA_HSMMC2 S3C64XX_PA_HSMMC(2) | ||
25 | |||
26 | #define S3C_PA_UART (0x7F005000) | ||
27 | #define S3C_PA_UART0 (S3C_PA_UART + 0x00) | ||
28 | #define S3C_PA_UART1 (S3C_PA_UART + 0x400) | ||
29 | #define S3C_PA_UART2 (S3C_PA_UART + 0x800) | ||
30 | #define S3C_PA_UART3 (S3C_PA_UART + 0xC00) | ||
31 | #define S3C_UART_OFFSET (0x400) | ||
32 | |||
33 | /* See notes on UART VA mapping in debug-macro.S */ | ||
34 | #define S3C_VA_UARTx(x) (S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET)) | ||
35 | |||
36 | #define S3C_VA_UART0 S3C_VA_UARTx(0) | ||
37 | #define S3C_VA_UART1 S3C_VA_UARTx(1) | ||
38 | #define S3C_VA_UART2 S3C_VA_UARTx(2) | ||
39 | #define S3C_VA_UART3 S3C_VA_UARTx(3) | ||
40 | |||
41 | #define S3C64XX_PA_FB (0x77100000) | ||
42 | #define S3C64XX_PA_SYSCON (0x7E00F000) | ||
43 | #define S3C64XX_PA_TIMER (0x7F006000) | ||
44 | #define S3C64XX_PA_IIC0 (0x7F004000) | ||
45 | #define S3C64XX_PA_IIC1 (0x7F00F000) | ||
46 | |||
47 | #define S3C64XX_PA_GPIO (0x7F008000) | ||
48 | #define S3C64XX_VA_GPIO S3C_ADDR(0x00500000) | ||
49 | #define S3C64XX_SZ_GPIO SZ_4K | ||
50 | |||
51 | #define S3C64XX_PA_SDRAM (0x50000000) | ||
52 | #define S3C64XX_PA_VIC0 (0x71200000) | ||
53 | #define S3C64XX_PA_VIC1 (0x71300000) | ||
54 | |||
55 | /* place VICs close together */ | ||
56 | #define S3C_VA_VIC0 (S3C_VA_IRQ + 0x00) | ||
57 | #define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) | ||
58 | |||
59 | /* compatibiltiy defines. */ | ||
60 | #define S3C_PA_TIMER S3C64XX_PA_TIMER | ||
61 | #define S3C_PA_HSMMC0 S3C64XX_PA_HSMMC0 | ||
62 | #define S3C_PA_HSMMC1 S3C64XX_PA_HSMMC1 | ||
63 | #define S3C_PA_HSMMC2 S3C64XX_PA_HSMMC2 | ||
64 | #define S3C_PA_IIC S3C64XX_PA_IIC0 | ||
65 | #define S3C_PA_IIC1 S3C64XX_PA_IIC1 | ||
66 | #define S3C_PA_FB S3C64XX_PA_FB | ||
67 | |||
68 | #endif /* __ASM_ARCH_6400_MAP_H */ | ||
diff --git a/arch/arm/mach-s3c6400/include/mach/memory.h b/arch/arm/mach-s3c6400/include/mach/memory.h new file mode 100644 index 000000000000..a3ac84a65480 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/memory.h | |||
@@ -0,0 +1,18 @@ | |||
1 | /* arch/arm/mach-s3c6400/include/mach/memory.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_MEMORY_H | ||
14 | #define __ASM_ARCH_MEMORY_H | ||
15 | |||
16 | #define PHYS_OFFSET UL(0x50000000) | ||
17 | |||
18 | #endif | ||
diff --git a/arch/arm/mach-s3c6400/include/mach/pwm-clock.h b/arch/arm/mach-s3c6400/include/mach/pwm-clock.h new file mode 100644 index 000000000000..b25bedee0d52 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/pwm-clock.h | |||
@@ -0,0 +1,56 @@ | |||
1 | /* linux/arch/arm/mach-s3c6400/include/mach/pwm-clock.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C64xx - pwm clock and timer support | ||
9 | */ | ||
10 | |||
11 | /** | ||
12 | * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk | ||
13 | * @tcfg: The timer TCFG1 register bits shifted down to 0. | ||
14 | * | ||
15 | * Return true if the given configuration from TCFG1 is a TCLK instead | ||
16 | * any of the TDIV clocks. | ||
17 | */ | ||
18 | static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) | ||
19 | { | ||
20 | return tcfg >= S3C64XX_TCFG1_MUX_TCLK; | ||
21 | } | ||
22 | |||
23 | /** | ||
24 | * tcfg_to_divisor() - convert tcfg1 setting to a divisor | ||
25 | * @tcfg1: The tcfg1 setting, shifted down. | ||
26 | * | ||
27 | * Get the divisor value for the given tcfg1 setting. We assume the | ||
28 | * caller has already checked to see if this is not a TCLK source. | ||
29 | */ | ||
30 | static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) | ||
31 | { | ||
32 | return 1 << tcfg1; | ||
33 | } | ||
34 | |||
35 | /** | ||
36 | * pwm_tdiv_has_div1() - does the tdiv setting have a /1 | ||
37 | * | ||
38 | * Return true if we have a /1 in the tdiv setting. | ||
39 | */ | ||
40 | static inline unsigned int pwm_tdiv_has_div1(void) | ||
41 | { | ||
42 | return 1; | ||
43 | } | ||
44 | |||
45 | /** | ||
46 | * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. | ||
47 | * @div: The divisor to calculate the bit information for. | ||
48 | * | ||
49 | * Turn a divisor into the necessary bit field for TCFG1. | ||
50 | */ | ||
51 | static inline unsigned long pwm_tdiv_div_bits(unsigned int div) | ||
52 | { | ||
53 | return ilog2(div); | ||
54 | } | ||
55 | |||
56 | #define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK | ||
diff --git a/arch/arm/mach-s3c6400/include/mach/regs-fb.h b/arch/arm/mach-s3c6400/include/mach/regs-fb.h new file mode 100644 index 000000000000..47019795ce06 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/regs-fb.h | |||
@@ -0,0 +1,259 @@ | |||
1 | /* arch/arm/mach-s3c6400/include/mach/regs-fb.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * | ||
8 | * S3C64XX - new-style framebuffer register definitions | ||
9 | * | ||
10 | * This is the register set for the new style framebuffer interface | ||
11 | * found from the S3C2443 onwards and specifically the S3C64XX series | ||
12 | * S3C6400 and S3C6410. | ||
13 | * | ||
14 | * The file contains the cpu specific items which change between whichever | ||
15 | * architecture is selected. See <plat/regs-fb.h> for the core definitions | ||
16 | * that are the same. | ||
17 | * | ||
18 | * This program is free software; you can redistribute it and/or modify | ||
19 | * it under the terms of the GNU General Public License version 2 as | ||
20 | * published by the Free Software Foundation. | ||
21 | */ | ||
22 | |||
23 | /* include the core definitions here, in case we really do need to | ||
24 | * override them at a later date. | ||
25 | */ | ||
26 | |||
27 | #include <plat/regs-fb.h> | ||
28 | |||
29 | #define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */ | ||
30 | #define VIDCON1_FSTATUS_EVEN (1 << 15) | ||
31 | |||
32 | /* Video timing controls */ | ||
33 | #define VIDTCON0 (0x10) | ||
34 | #define VIDTCON1 (0x14) | ||
35 | #define VIDTCON2 (0x18) | ||
36 | |||
37 | /* Window position controls */ | ||
38 | |||
39 | #define WINCON(_win) (0x20 + ((_win) * 4)) | ||
40 | |||
41 | /* OSD1 and OSD4 do not have register D */ | ||
42 | |||
43 | #define VIDOSD_A(_win) (0x40 + ((_win) * 16)) | ||
44 | #define VIDOSD_B(_win) (0x44 + ((_win) * 16)) | ||
45 | #define VIDOSD_C(_win) (0x48 + ((_win) * 16)) | ||
46 | #define VIDOSD_D(_win) (0x4C + ((_win) * 16)) | ||
47 | |||
48 | /* Video buffer addresses */ | ||
49 | |||
50 | #define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8)) | ||
51 | #define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8)) | ||
52 | #define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8)) | ||
53 | #define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8)) | ||
54 | #define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4)) | ||
55 | |||
56 | #define VIDINTCON0 (0x130) | ||
57 | |||
58 | #define WxKEYCONy(_win, _con) ((0x140 + ((_win) * 8)) + ((_con) * 4)) | ||
59 | |||
60 | /* WINCONx */ | ||
61 | |||
62 | #define WINCONx_CSCWIDTH_MASK (0x3 << 26) | ||
63 | #define WINCONx_CSCWIDTH_SHIFT (26) | ||
64 | #define WINCONx_CSCWIDTH_WIDE (0x0 << 26) | ||
65 | #define WINCONx_CSCWIDTH_NARROW (0x3 << 26) | ||
66 | |||
67 | #define WINCONx_ENLOCAL (1 << 22) | ||
68 | #define WINCONx_BUFSTATUS (1 << 21) | ||
69 | #define WINCONx_BUFSEL (1 << 20) | ||
70 | #define WINCONx_BUFAUTOEN (1 << 19) | ||
71 | #define WINCONx_YCbCr (1 << 13) | ||
72 | |||
73 | #define WINCON1_LOCALSEL_CAMIF (1 << 23) | ||
74 | |||
75 | #define WINCON2_LOCALSEL_CAMIF (1 << 23) | ||
76 | #define WINCON2_BLD_PIX (1 << 6) | ||
77 | |||
78 | #define WINCON2_ALPHA_SEL (1 << 1) | ||
79 | #define WINCON2_BPPMODE_MASK (0xf << 2) | ||
80 | #define WINCON2_BPPMODE_SHIFT (2) | ||
81 | #define WINCON2_BPPMODE_1BPP (0x0 << 2) | ||
82 | #define WINCON2_BPPMODE_2BPP (0x1 << 2) | ||
83 | #define WINCON2_BPPMODE_4BPP (0x2 << 2) | ||
84 | #define WINCON2_BPPMODE_8BPP_1232 (0x4 << 2) | ||
85 | #define WINCON2_BPPMODE_16BPP_565 (0x5 << 2) | ||
86 | #define WINCON2_BPPMODE_16BPP_A1555 (0x6 << 2) | ||
87 | #define WINCON2_BPPMODE_16BPP_I1555 (0x7 << 2) | ||
88 | #define WINCON2_BPPMODE_18BPP_666 (0x8 << 2) | ||
89 | #define WINCON2_BPPMODE_18BPP_A1665 (0x9 << 2) | ||
90 | #define WINCON2_BPPMODE_19BPP_A1666 (0xa << 2) | ||
91 | #define WINCON2_BPPMODE_24BPP_888 (0xb << 2) | ||
92 | #define WINCON2_BPPMODE_24BPP_A1887 (0xc << 2) | ||
93 | #define WINCON2_BPPMODE_25BPP_A1888 (0xd << 2) | ||
94 | #define WINCON2_BPPMODE_28BPP_A4888 (0xd << 2) | ||
95 | |||
96 | #define WINCON3_BLD_PIX (1 << 6) | ||
97 | |||
98 | #define WINCON3_ALPHA_SEL (1 << 1) | ||
99 | #define WINCON3_BPPMODE_MASK (0xf << 2) | ||
100 | #define WINCON3_BPPMODE_SHIFT (2) | ||
101 | #define WINCON3_BPPMODE_1BPP (0x0 << 2) | ||
102 | #define WINCON3_BPPMODE_2BPP (0x1 << 2) | ||
103 | #define WINCON3_BPPMODE_4BPP (0x2 << 2) | ||
104 | #define WINCON3_BPPMODE_16BPP_565 (0x5 << 2) | ||
105 | #define WINCON3_BPPMODE_16BPP_A1555 (0x6 << 2) | ||
106 | #define WINCON3_BPPMODE_16BPP_I1555 (0x7 << 2) | ||
107 | #define WINCON3_BPPMODE_18BPP_666 (0x8 << 2) | ||
108 | #define WINCON3_BPPMODE_18BPP_A1665 (0x9 << 2) | ||
109 | #define WINCON3_BPPMODE_19BPP_A1666 (0xa << 2) | ||
110 | #define WINCON3_BPPMODE_24BPP_888 (0xb << 2) | ||
111 | #define WINCON3_BPPMODE_24BPP_A1887 (0xc << 2) | ||
112 | #define WINCON3_BPPMODE_25BPP_A1888 (0xd << 2) | ||
113 | #define WINCON3_BPPMODE_28BPP_A4888 (0xd << 2) | ||
114 | |||
115 | #define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5) | ||
116 | #define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5) | ||
117 | #define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5) | ||
118 | |||
119 | #define DITHMODE (0x170) | ||
120 | #define WINxMAP(_win) (0x180 + ((_win) * 4)) | ||
121 | |||
122 | |||
123 | #define DITHMODE_R_POS_MASK (0x3 << 5) | ||
124 | #define DITHMODE_R_POS_SHIFT (5) | ||
125 | #define DITHMODE_R_POS_8BIT (0x0 << 5) | ||
126 | #define DITHMODE_R_POS_6BIT (0x1 << 5) | ||
127 | #define DITHMODE_R_POS_5BIT (0x2 << 5) | ||
128 | |||
129 | #define DITHMODE_G_POS_MASK (0x3 << 3) | ||
130 | #define DITHMODE_G_POS_SHIFT (3) | ||
131 | #define DITHMODE_G_POS_8BIT (0x0 << 3) | ||
132 | #define DITHMODE_G_POS_6BIT (0x1 << 3) | ||
133 | #define DITHMODE_G_POS_5BIT (0x2 << 3) | ||
134 | |||
135 | #define DITHMODE_B_POS_MASK (0x3 << 1) | ||
136 | #define DITHMODE_B_POS_SHIFT (1) | ||
137 | #define DITHMODE_B_POS_8BIT (0x0 << 1) | ||
138 | #define DITHMODE_B_POS_6BIT (0x1 << 1) | ||
139 | #define DITHMODE_B_POS_5BIT (0x2 << 1) | ||
140 | |||
141 | #define DITHMODE_DITH_EN (1 << 0) | ||
142 | |||
143 | #define WPALCON (0x1A0) | ||
144 | |||
145 | #define WPALCON_W4PAL_16BPP_A555 (1 << 8) | ||
146 | #define WPALCON_W3PAL_16BPP_A555 (1 << 7) | ||
147 | #define WPALCON_W2PAL_16BPP_A555 (1 << 6) | ||
148 | |||
149 | /* Palette registers */ | ||
150 | |||
151 | #define WIN2_PAL(_entry) (0x300 + ((_entry) * 2)) | ||
152 | #define WIN3_PAL(_entry) (0x320 + ((_entry) * 2)) | ||
153 | #define WIN4_PAL(_entry) (0x340 + ((_entry) * 2)) | ||
154 | #define WIN0_PAL(_entry) (0x400 + ((_entry) * 4)) | ||
155 | #define WIN1_PAL(_entry) (0x800 + ((_entry) * 4)) | ||
156 | |||
157 | /* system specific implementation code for palette sizes, and other | ||
158 | * information that changes depending on which architecture is being | ||
159 | * compiled. | ||
160 | */ | ||
161 | |||
162 | /* return true if window _win has OSD register D */ | ||
163 | #define s3c_fb_has_osd_d(_win) ((_win) != 4 && (_win) != 0) | ||
164 | |||
165 | static inline unsigned int s3c_fb_win_pal_size(unsigned int win) | ||
166 | { | ||
167 | if (win < 2) | ||
168 | return 256; | ||
169 | if (win < 4) | ||
170 | return 16; | ||
171 | if (win == 4) | ||
172 | return 4; | ||
173 | |||
174 | BUG(); /* shouldn't get here */ | ||
175 | } | ||
176 | |||
177 | static inline int s3c_fb_validate_win_bpp(unsigned int win, unsigned int bpp) | ||
178 | { | ||
179 | /* all windows can do 1/2 bpp */ | ||
180 | |||
181 | if ((bpp == 25 || bpp == 19) && win == 0) | ||
182 | return 0; /* win 0 does not have 19 or 25bpp modes */ | ||
183 | |||
184 | if (bpp == 4 && win == 4) | ||
185 | return 0; | ||
186 | |||
187 | if (bpp == 8 && (win >= 3)) | ||
188 | return 0; /* win 3/4 cannot do 8bpp in any mode */ | ||
189 | |||
190 | return 1; | ||
191 | } | ||
192 | |||
193 | static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg) | ||
194 | { | ||
195 | switch (window) { | ||
196 | case 0: return WIN0_PAL(reg); | ||
197 | case 1: return WIN1_PAL(reg); | ||
198 | case 2: return WIN2_PAL(reg); | ||
199 | case 3: return WIN3_PAL(reg); | ||
200 | case 4: return WIN4_PAL(reg); | ||
201 | } | ||
202 | |||
203 | BUG(); | ||
204 | } | ||
205 | |||
206 | static inline int s3c_fb_pal_is16(unsigned int window) | ||
207 | { | ||
208 | return window > 1; | ||
209 | } | ||
210 | |||
211 | struct s3c_fb_palette { | ||
212 | struct fb_bitfield r; | ||
213 | struct fb_bitfield g; | ||
214 | struct fb_bitfield b; | ||
215 | struct fb_bitfield a; | ||
216 | }; | ||
217 | |||
218 | static inline void s3c_fb_init_palette(unsigned int window, | ||
219 | struct s3c_fb_palette *palette) | ||
220 | { | ||
221 | if (window < 2) { | ||
222 | /* Windows 0/1 are 8/8/8 or A/8/8/8 */ | ||
223 | palette->r.offset = 16; | ||
224 | palette->r.length = 8; | ||
225 | palette->g.offset = 8; | ||
226 | palette->g.length = 8; | ||
227 | palette->b.offset = 0; | ||
228 | palette->b.length = 8; | ||
229 | } else { | ||
230 | /* currently we assume RGB 5/6/5 */ | ||
231 | palette->r.offset = 11; | ||
232 | palette->r.length = 5; | ||
233 | palette->g.offset = 5; | ||
234 | palette->g.length = 6; | ||
235 | palette->b.offset = 0; | ||
236 | palette->b.length = 5; | ||
237 | } | ||
238 | } | ||
239 | |||
240 | /* Notes on per-window bpp settings | ||
241 | * | ||
242 | * Value Win0 Win1 Win2 Win3 Win 4 | ||
243 | * 0000 1(P) 1(P) 1(P) 1(P) 1(P) | ||
244 | * 0001 2(P) 2(P) 2(P) 2(P) 2(P) | ||
245 | * 0010 4(P) 4(P) 4(P) 4(P) -none- | ||
246 | * 0011 8(P) 8(P) -none- -none- -none- | ||
247 | * 0100 -none- 8(A232) 8(A232) -none- -none- | ||
248 | * 0101 16(565) 16(565) 16(565) 16(565) 16(565) | ||
249 | * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555) | ||
250 | * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555) | ||
251 | * 1000 18(666) 18(666) 18(666) 18(666) 18(666) | ||
252 | * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665) | ||
253 | * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666) | ||
254 | * 1011 24(888) 24(888) 24(888) 24(888) 24(888) | ||
255 | * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887) | ||
256 | * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888) | ||
257 | * 1110 -none- -none- -none- -none- -none- | ||
258 | * 1111 -none- -none- -none- -none- -none- | ||
259 | */ | ||
diff --git a/arch/arm/mach-s3c6400/include/mach/regs-irq.h b/arch/arm/mach-s3c6400/include/mach/regs-irq.h new file mode 100644 index 000000000000..bcce68a0bb75 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/regs-irq.h | |||
@@ -0,0 +1,20 @@ | |||
1 | /* linux/arch/arm/mach-s3c6400/include/mach/regs-irq.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * | ||
8 | * S3C64XX - IRQ register definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ARCH_REGS_IRQ_H | ||
16 | #define __ASM_ARCH_REGS_IRQ_H __FILE__ | ||
17 | |||
18 | #include <asm/hardware/vic.h> | ||
19 | |||
20 | #endif /* __ASM_ARCH_6400_REGS_IRQ_H */ | ||
diff --git a/arch/arm/mach-s3c6400/include/mach/system.h b/arch/arm/mach-s3c6400/include/mach/system.h new file mode 100644 index 000000000000..652bbc403f0b --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/system.h | |||
@@ -0,0 +1,24 @@ | |||
1 | /* linux/arch/arm/mach-s3c6400/include/mach/system.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C6400 - system implementation | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_ARCH_SYSTEM_H | ||
12 | #define __ASM_ARCH_SYSTEM_H __FILE__ | ||
13 | |||
14 | static void arch_idle(void) | ||
15 | { | ||
16 | /* nothing here yet */ | ||
17 | } | ||
18 | |||
19 | static void arch_reset(char mode) | ||
20 | { | ||
21 | /* nothing here yet */ | ||
22 | } | ||
23 | |||
24 | #endif /* __ASM_ARCH_IRQ_H */ | ||
diff --git a/arch/arm/mach-s3c6400/include/mach/tick.h b/arch/arm/mach-s3c6400/include/mach/tick.h new file mode 100644 index 000000000000..d9c0dc7014ec --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/tick.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* linux/arch/arm/mach-s3c6400/include/mach/tick.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * | ||
8 | * S3C64XX - Timer tick support definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ARCH_TICK_H | ||
16 | #define __ASM_ARCH_TICK_H __FILE__ | ||
17 | |||
18 | /* note, the timer interrutps turn up in 2 places, the vic and then | ||
19 | * the timer block. We take the VIC as the base at the moment. | ||
20 | */ | ||
21 | static inline u32 s3c24xx_ostimer_pending(void) | ||
22 | { | ||
23 | u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS); | ||
24 | return pend & 1 << (IRQ_TIMER4_VIC - S3C64XX_IRQ_VIC0(0)); | ||
25 | } | ||
26 | |||
27 | #define TICK_MAX (0xffffffff) | ||
28 | |||
29 | #endif /* __ASM_ARCH_6400_TICK_H */ | ||
diff --git a/arch/arm/mach-s3c6400/include/mach/uncompress.h b/arch/arm/mach-s3c6400/include/mach/uncompress.h new file mode 100644 index 000000000000..c6a82a20bf2a --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/uncompress.h | |||
@@ -0,0 +1,28 @@ | |||
1 | /* arch/arm/mach-s3c6400/include/mach/uncompress.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * | ||
8 | * S3C6400 - uncompress code | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
16 | #define __ASM_ARCH_UNCOMPRESS_H | ||
17 | |||
18 | #include <mach/map.h> | ||
19 | #include <plat/uncompress.h> | ||
20 | |||
21 | static void arch_detect_cpu(void) | ||
22 | { | ||
23 | /* we do not need to do any cpu detection here at the moment. */ | ||
24 | fifo_mask = S3C2440_UFSTAT_TXMASK; | ||
25 | fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT; | ||
26 | } | ||
27 | |||
28 | #endif /* __ASM_ARCH_UNCOMPRESS_H */ | ||
diff --git a/arch/arm/mach-s3c6410/Kconfig b/arch/arm/mach-s3c6410/Kconfig new file mode 100644 index 000000000000..1d5010070027 --- /dev/null +++ b/arch/arm/mach-s3c6410/Kconfig | |||
@@ -0,0 +1,62 @@ | |||
1 | # arch/arm/mach-s3c6410/Kconfig | ||
2 | # | ||
3 | # Copyright 2008 Openmoko, Inc. | ||
4 | # Copyright 2008 Simtec Electronics | ||
5 | # | ||
6 | # Licensed under GPLv2 | ||
7 | |||
8 | # Configuration options for the S3C6410 CPU | ||
9 | |||
10 | config CPU_S3C6410 | ||
11 | bool | ||
12 | select CPU_S3C6400_INIT | ||
13 | select CPU_S3C6400_CLOCK | ||
14 | help | ||
15 | Enable S3C6410 CPU support | ||
16 | |||
17 | config S3C6410_SETUP_SDHCI | ||
18 | bool | ||
19 | help | ||
20 | Internal helper functions for S3C6410 based SDHCI systems | ||
21 | |||
22 | config MACH_SMDK6410 | ||
23 | bool "SMDK6410" | ||
24 | select CPU_S3C6410 | ||
25 | select S3C_DEV_HSMMC | ||
26 | select S3C_DEV_HSMMC1 | ||
27 | select S3C_DEV_I2C1 | ||
28 | select S3C_DEV_FB | ||
29 | select S3C6410_SETUP_SDHCI | ||
30 | select S3C64XX_SETUP_I2C1 | ||
31 | select S3C64XX_SETUP_FB_24BPP | ||
32 | help | ||
33 | Machine support for the Samsung SMDK6410 | ||
34 | |||
35 | # At least some of the SMDK6410s were shipped with the card detect | ||
36 | # for the MMC/SD slots connected to the same input. This means that | ||
37 | # either the boards need to be altered to have channel0 to an alternate | ||
38 | # configuration or that only one slot can be used. | ||
39 | |||
40 | choice | ||
41 | prompt "SMDK6410 MMC/SD slot setup" | ||
42 | depends on MACH_SMDK6410 | ||
43 | |||
44 | config SMDK6410_SD_CH0 | ||
45 | bool "Use channel 0 only" | ||
46 | depends on MACH_SMDK6410 | ||
47 | help | ||
48 | Select CON7 (channel 0) as the MMC/SD slot, as | ||
49 | at least some SMDK6410 boards come with the | ||
50 | resistors fitted so that the card detects for | ||
51 | channels 0 and 1 are the same. | ||
52 | |||
53 | config SMDK6410_SD_CH1 | ||
54 | bool "Use channel 1 only" | ||
55 | depends on MACH_SMDK6410 | ||
56 | help | ||
57 | Select CON6 (channel 1) as the MMC/SD slot, as | ||
58 | at least some SMDK6410 boards come with the | ||
59 | resistors fitted so that the card detects for | ||
60 | channels 0 and 1 are the same. | ||
61 | |||
62 | endchoice | ||
diff --git a/arch/arm/mach-s3c6410/Makefile b/arch/arm/mach-s3c6410/Makefile new file mode 100644 index 000000000000..2cd4f189036b --- /dev/null +++ b/arch/arm/mach-s3c6410/Makefile | |||
@@ -0,0 +1,23 @@ | |||
1 | # arch/arm/plat-s3c6410/Makefile | ||
2 | # | ||
3 | # Copyright 2008 Openmoko, Inc. | ||
4 | # Copyright 2008 Simtec Electronics | ||
5 | # | ||
6 | # Licensed under GPLv2 | ||
7 | |||
8 | obj-y := | ||
9 | obj-m := | ||
10 | obj-n := | ||
11 | obj- := | ||
12 | |||
13 | # Core support for S3C6410 system | ||
14 | |||
15 | obj-$(CONFIG_CPU_S3C6410) += cpu.o | ||
16 | |||
17 | # Helper and device support | ||
18 | |||
19 | obj-$(CONFIG_S3C6410_SETUP_SDHCI) += setup-sdhci.o | ||
20 | |||
21 | # machine support | ||
22 | |||
23 | obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o | ||
diff --git a/arch/arm/mach-s3c6410/cpu.c b/arch/arm/mach-s3c6410/cpu.c new file mode 100644 index 000000000000..6a73ca6b7a3a --- /dev/null +++ b/arch/arm/mach-s3c6410/cpu.c | |||
@@ -0,0 +1,101 @@ | |||
1 | /* linux/arch/arm/mach-s3c6410/cpu.c | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/types.h> | ||
15 | #include <linux/interrupt.h> | ||
16 | #include <linux/list.h> | ||
17 | #include <linux/timer.h> | ||
18 | #include <linux/init.h> | ||
19 | #include <linux/clk.h> | ||
20 | #include <linux/io.h> | ||
21 | #include <linux/sysdev.h> | ||
22 | #include <linux/serial_core.h> | ||
23 | #include <linux/platform_device.h> | ||
24 | |||
25 | #include <asm/mach/arch.h> | ||
26 | #include <asm/mach/map.h> | ||
27 | #include <asm/mach/irq.h> | ||
28 | |||
29 | #include <mach/hardware.h> | ||
30 | #include <asm/irq.h> | ||
31 | |||
32 | #include <plat/cpu-freq.h> | ||
33 | #include <plat/regs-serial.h> | ||
34 | |||
35 | #include <plat/cpu.h> | ||
36 | #include <plat/devs.h> | ||
37 | #include <plat/clock.h> | ||
38 | #include <plat/sdhci.h> | ||
39 | #include <plat/iic-core.h> | ||
40 | #include <plat/s3c6400.h> | ||
41 | #include <plat/s3c6410.h> | ||
42 | |||
43 | /* Initial IO mappings */ | ||
44 | |||
45 | static struct map_desc s3c6410_iodesc[] __initdata = { | ||
46 | }; | ||
47 | |||
48 | /* s3c6410_map_io | ||
49 | * | ||
50 | * register the standard cpu IO areas | ||
51 | */ | ||
52 | |||
53 | void __init s3c6410_map_io(void) | ||
54 | { | ||
55 | iotable_init(s3c6410_iodesc, ARRAY_SIZE(s3c6410_iodesc)); | ||
56 | |||
57 | /* initialise device information early */ | ||
58 | s3c6410_default_sdhci0(); | ||
59 | s3c6410_default_sdhci1(); | ||
60 | |||
61 | /* the i2c devices are directly compatible with s3c2440 */ | ||
62 | s3c_i2c0_setname("s3c2440-i2c"); | ||
63 | s3c_i2c1_setname("s3c2440-i2c"); | ||
64 | } | ||
65 | |||
66 | void __init s3c6410_init_clocks(int xtal) | ||
67 | { | ||
68 | printk(KERN_DEBUG "%s: initialising clocks\n", __func__); | ||
69 | s3c24xx_register_baseclocks(xtal); | ||
70 | s3c64xx_register_clocks(); | ||
71 | s3c6400_register_clocks(); | ||
72 | s3c6400_setup_clocks(); | ||
73 | } | ||
74 | |||
75 | void __init s3c6410_init_irq(void) | ||
76 | { | ||
77 | /* VIC0 is missing IRQ7, VIC1 is fully populated. */ | ||
78 | s3c64xx_init_irq(~0 & ~(1 << 7), ~0); | ||
79 | } | ||
80 | |||
81 | struct sysdev_class s3c6410_sysclass = { | ||
82 | .name = "s3c6410-core", | ||
83 | }; | ||
84 | |||
85 | static struct sys_device s3c6410_sysdev = { | ||
86 | .cls = &s3c6410_sysclass, | ||
87 | }; | ||
88 | |||
89 | static int __init s3c6410_core_init(void) | ||
90 | { | ||
91 | return sysdev_class_register(&s3c6410_sysclass); | ||
92 | } | ||
93 | |||
94 | core_initcall(s3c6410_core_init); | ||
95 | |||
96 | int __init s3c6410_init(void) | ||
97 | { | ||
98 | printk("S3C6410: Initialising architecture\n"); | ||
99 | |||
100 | return sysdev_register(&s3c6410_sysdev); | ||
101 | } | ||
diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c new file mode 100644 index 000000000000..3c4d47145c83 --- /dev/null +++ b/arch/arm/mach-s3c6410/mach-smdk6410.c | |||
@@ -0,0 +1,185 @@ | |||
1 | /* linux/arch/arm/mach-s3c6410/mach-smdk6410.c | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/types.h> | ||
16 | #include <linux/interrupt.h> | ||
17 | #include <linux/list.h> | ||
18 | #include <linux/timer.h> | ||
19 | #include <linux/init.h> | ||
20 | #include <linux/serial_core.h> | ||
21 | #include <linux/platform_device.h> | ||
22 | #include <linux/io.h> | ||
23 | #include <linux/i2c.h> | ||
24 | #include <linux/fb.h> | ||
25 | #include <linux/gpio.h> | ||
26 | #include <linux/delay.h> | ||
27 | |||
28 | #include <video/platform_lcd.h> | ||
29 | |||
30 | #include <asm/mach/arch.h> | ||
31 | #include <asm/mach/map.h> | ||
32 | #include <asm/mach/irq.h> | ||
33 | |||
34 | #include <mach/hardware.h> | ||
35 | #include <mach/regs-fb.h> | ||
36 | #include <mach/map.h> | ||
37 | |||
38 | #include <asm/irq.h> | ||
39 | #include <asm/mach-types.h> | ||
40 | |||
41 | #include <plat/regs-serial.h> | ||
42 | #include <plat/iic.h> | ||
43 | #include <plat/fb.h> | ||
44 | |||
45 | #include <plat/s3c6410.h> | ||
46 | #include <plat/clock.h> | ||
47 | #include <plat/devs.h> | ||
48 | #include <plat/cpu.h> | ||
49 | |||
50 | #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK | ||
51 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB | ||
52 | #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE | ||
53 | |||
54 | static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = { | ||
55 | [0] = { | ||
56 | .hwport = 0, | ||
57 | .flags = 0, | ||
58 | .ucon = 0x3c5, | ||
59 | .ulcon = 0x03, | ||
60 | .ufcon = 0x51, | ||
61 | }, | ||
62 | [1] = { | ||
63 | .hwport = 1, | ||
64 | .flags = 0, | ||
65 | .ucon = 0x3c5, | ||
66 | .ulcon = 0x03, | ||
67 | .ufcon = 0x51, | ||
68 | }, | ||
69 | }; | ||
70 | |||
71 | /* framebuffer and LCD setup. */ | ||
72 | |||
73 | /* GPF15 = LCD backlight control | ||
74 | * GPF13 => Panel power | ||
75 | * GPN5 = LCD nRESET signal | ||
76 | * PWM_TOUT1 => backlight brightness | ||
77 | */ | ||
78 | |||
79 | static void smdk6410_lcd_power_set(struct plat_lcd_data *pd, | ||
80 | unsigned int power) | ||
81 | { | ||
82 | if (power) { | ||
83 | gpio_direction_output(S3C64XX_GPF(13), 1); | ||
84 | gpio_direction_output(S3C64XX_GPF(15), 1); | ||
85 | |||
86 | /* fire nRESET on power up */ | ||
87 | gpio_direction_output(S3C64XX_GPN(5), 0); | ||
88 | msleep(10); | ||
89 | gpio_direction_output(S3C64XX_GPN(5), 1); | ||
90 | msleep(1); | ||
91 | } else { | ||
92 | gpio_direction_output(S3C64XX_GPF(15), 0); | ||
93 | gpio_direction_output(S3C64XX_GPF(13), 0); | ||
94 | } | ||
95 | } | ||
96 | |||
97 | static struct plat_lcd_data smdk6410_lcd_power_data = { | ||
98 | .set_power = smdk6410_lcd_power_set, | ||
99 | }; | ||
100 | |||
101 | static struct platform_device smdk6410_lcd_powerdev = { | ||
102 | .name = "platform-lcd", | ||
103 | .dev.parent = &s3c_device_fb.dev, | ||
104 | .dev.platform_data = &smdk6410_lcd_power_data, | ||
105 | }; | ||
106 | |||
107 | static struct s3c_fb_pd_win smdk6410_fb_win0 = { | ||
108 | /* this is to ensure we use win0 */ | ||
109 | .win_mode = { | ||
110 | .pixclock = 41094, | ||
111 | .left_margin = 8, | ||
112 | .right_margin = 13, | ||
113 | .upper_margin = 7, | ||
114 | .lower_margin = 5, | ||
115 | .hsync_len = 3, | ||
116 | .vsync_len = 1, | ||
117 | .xres = 800, | ||
118 | .yres = 480, | ||
119 | }, | ||
120 | .max_bpp = 32, | ||
121 | .default_bpp = 16, | ||
122 | }; | ||
123 | |||
124 | /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */ | ||
125 | static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = { | ||
126 | .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, | ||
127 | .win[0] = &smdk6410_fb_win0, | ||
128 | .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, | ||
129 | .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, | ||
130 | }; | ||
131 | |||
132 | struct map_desc smdk6410_iodesc[] = {}; | ||
133 | |||
134 | static struct platform_device *smdk6410_devices[] __initdata = { | ||
135 | #ifdef CONFIG_SMDK6410_SD_CH0 | ||
136 | &s3c_device_hsmmc0, | ||
137 | #endif | ||
138 | #ifdef CONFIG_SMDK6410_SD_CH1 | ||
139 | &s3c_device_hsmmc1, | ||
140 | #endif | ||
141 | &s3c_device_i2c0, | ||
142 | &s3c_device_i2c1, | ||
143 | &s3c_device_fb, | ||
144 | &smdk6410_lcd_powerdev, | ||
145 | }; | ||
146 | |||
147 | static struct i2c_board_info i2c_devs0[] __initdata = { | ||
148 | { I2C_BOARD_INFO("24c08", 0x50), }, | ||
149 | { I2C_BOARD_INFO("WM8580", 0X1b), }, | ||
150 | }; | ||
151 | |||
152 | static struct i2c_board_info i2c_devs1[] __initdata = { | ||
153 | { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */ | ||
154 | }; | ||
155 | |||
156 | static void __init smdk6410_map_io(void) | ||
157 | { | ||
158 | s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc)); | ||
159 | s3c24xx_init_clocks(12000000); | ||
160 | s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs)); | ||
161 | } | ||
162 | |||
163 | static void __init smdk6410_machine_init(void) | ||
164 | { | ||
165 | s3c_i2c0_set_platdata(NULL); | ||
166 | s3c_i2c1_set_platdata(NULL); | ||
167 | s3c_fb_set_platdata(&smdk6410_lcd_pdata); | ||
168 | |||
169 | i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); | ||
170 | i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); | ||
171 | |||
172 | platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices)); | ||
173 | } | ||
174 | |||
175 | MACHINE_START(SMDK6410, "SMDK6410") | ||
176 | /* Maintainer: Ben Dooks <ben@fluff.org> */ | ||
177 | .phys_io = S3C_PA_UART & 0xfff00000, | ||
178 | .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, | ||
179 | .boot_params = S3C64XX_PA_SDRAM + 0x100, | ||
180 | |||
181 | .init_irq = s3c6410_init_irq, | ||
182 | .map_io = smdk6410_map_io, | ||
183 | .init_machine = smdk6410_machine_init, | ||
184 | .timer = &s3c24xx_timer, | ||
185 | MACHINE_END | ||
diff --git a/arch/arm/mach-s3c6410/setup-sdhci.c b/arch/arm/mach-s3c6410/setup-sdhci.c new file mode 100644 index 000000000000..0b5788bd5985 --- /dev/null +++ b/arch/arm/mach-s3c6410/setup-sdhci.c | |||
@@ -0,0 +1,102 @@ | |||
1 | /* linux/arch/arm/mach-s3c6410/setup-sdhci.c | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC) | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/types.h> | ||
17 | #include <linux/interrupt.h> | ||
18 | #include <linux/platform_device.h> | ||
19 | #include <linux/io.h> | ||
20 | |||
21 | #include <linux/mmc/card.h> | ||
22 | #include <linux/mmc/host.h> | ||
23 | |||
24 | #include <mach/gpio.h> | ||
25 | #include <plat/gpio-cfg.h> | ||
26 | #include <plat/regs-sdhci.h> | ||
27 | #include <plat/sdhci.h> | ||
28 | |||
29 | /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ | ||
30 | |||
31 | char *s3c6410_hsmmc_clksrcs[4] = { | ||
32 | [0] = "hsmmc", | ||
33 | [1] = "hsmmc", | ||
34 | [2] = "mmc_bus", | ||
35 | /* [3] = "48m", - note not succesfully used yet */ | ||
36 | }; | ||
37 | |||
38 | void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) | ||
39 | { | ||
40 | unsigned int gpio; | ||
41 | unsigned int end; | ||
42 | |||
43 | end = S3C64XX_GPG(2 + width); | ||
44 | |||
45 | /* Set all the necessary GPG pins to special-function 0 */ | ||
46 | for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) { | ||
47 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
48 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
49 | } | ||
50 | |||
51 | s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); | ||
52 | s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2)); | ||
53 | } | ||
54 | |||
55 | void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, | ||
56 | void __iomem *r, | ||
57 | struct mmc_ios *ios, | ||
58 | struct mmc_card *card) | ||
59 | { | ||
60 | u32 ctrl2, ctrl3; | ||
61 | |||
62 | /* don't need to alter anything acording to card-type */ | ||
63 | |||
64 | writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); | ||
65 | |||
66 | ctrl2 = readl(r + S3C_SDHCI_CONTROL2); | ||
67 | ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; | ||
68 | ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | | ||
69 | S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | | ||
70 | S3C_SDHCI_CTRL2_ENFBCLKRX | | ||
71 | S3C_SDHCI_CTRL2_DFCNT_NONE | | ||
72 | S3C_SDHCI_CTRL2_ENCLKOUTHOLD); | ||
73 | |||
74 | if (ios->clock < 25 * 1000000) | ||
75 | ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | | ||
76 | S3C_SDHCI_CTRL3_FCSEL2 | | ||
77 | S3C_SDHCI_CTRL3_FCSEL1 | | ||
78 | S3C_SDHCI_CTRL3_FCSEL0); | ||
79 | else | ||
80 | ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); | ||
81 | |||
82 | printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3); | ||
83 | writel(ctrl2, r + S3C_SDHCI_CONTROL2); | ||
84 | writel(ctrl3, r + S3C_SDHCI_CONTROL3); | ||
85 | } | ||
86 | |||
87 | void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) | ||
88 | { | ||
89 | unsigned int gpio; | ||
90 | unsigned int end; | ||
91 | |||
92 | end = S3C64XX_GPH(2 + width); | ||
93 | |||
94 | /* Set all the necessary GPG pins to special-function 0 */ | ||
95 | for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) { | ||
96 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
97 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
98 | } | ||
99 | |||
100 | s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP); | ||
101 | s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3)); | ||
102 | } | ||
diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig index 31656c33e05e..def0bb457ca3 100644 --- a/arch/arm/plat-s3c/Kconfig +++ b/arch/arm/plat-s3c/Kconfig | |||
@@ -6,8 +6,8 @@ | |||
6 | 6 | ||
7 | config PLAT_S3C | 7 | config PLAT_S3C |
8 | bool | 8 | bool |
9 | depends on ARCH_S3C2410 | 9 | depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX |
10 | default y if ARCH_S3C2410 | 10 | default y |
11 | select NO_IOPORT | 11 | select NO_IOPORT |
12 | help | 12 | help |
13 | Base platform code for any Samsung S3C device | 13 | Base platform code for any Samsung S3C device |
@@ -16,24 +16,24 @@ config PLAT_S3C | |||
16 | 16 | ||
17 | config CPU_LLSERIAL_S3C2410_ONLY | 17 | config CPU_LLSERIAL_S3C2410_ONLY |
18 | bool | 18 | bool |
19 | depends on ARCH_S3C2410 | 19 | depends on PLAT_S3C |
20 | default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440 | 20 | default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440 |
21 | 21 | ||
22 | config CPU_LLSERIAL_S3C2440_ONLY | 22 | config CPU_LLSERIAL_S3C2440_ONLY |
23 | bool | 23 | bool |
24 | depends on ARCH_S3C2410 | 24 | depends on PLAT_S3C |
25 | default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410 | 25 | default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410 |
26 | 26 | ||
27 | config CPU_LLSERIAL_S3C2410 | 27 | config CPU_LLSERIAL_S3C2410 |
28 | bool | 28 | bool |
29 | depends on ARCH_S3C2410 | 29 | depends on PLAT_S3C |
30 | help | 30 | help |
31 | Selected if there is an S3C2410 (or register compatible) serial | 31 | Selected if there is an S3C2410 (or register compatible) serial |
32 | low-level implementation needed | 32 | low-level implementation needed |
33 | 33 | ||
34 | config CPU_LLSERIAL_S3C2440 | 34 | config CPU_LLSERIAL_S3C2440 |
35 | bool | 35 | bool |
36 | depends on ARCH_S3C2410 | 36 | depends on PLAT_S3C |
37 | help | 37 | help |
38 | Selected if there is an S3C2440 (or register compatible) serial | 38 | Selected if there is an S3C2440 (or register compatible) serial |
39 | low-level implementation needed | 39 | low-level implementation needed |
@@ -57,6 +57,14 @@ config S3C_BOOT_ERROR_RESET | |||
57 | Say y here to use the watchdog to reset the system if the | 57 | Say y here to use the watchdog to reset the system if the |
58 | kernel decompressor detects an error during decompression. | 58 | kernel decompressor detects an error during decompression. |
59 | 59 | ||
60 | config S3C_BOOT_UART_FORCE_FIFO | ||
61 | bool "Force UART FIFO on during boot process" | ||
62 | depends on PLAT_S3C | ||
63 | default y | ||
64 | help | ||
65 | Say Y here to force the UART FIFOs on during the kernel | ||
66 | uncompressor | ||
67 | |||
60 | comment "Power management" | 68 | comment "Power management" |
61 | 69 | ||
62 | config S3C2410_PM_DEBUG | 70 | config S3C2410_PM_DEBUG |
@@ -102,3 +110,73 @@ config S3C_LOWLEVEL_UART_PORT | |||
102 | such as the `Uncompressing...` at start time. The value of | 110 | such as the `Uncompressing...` at start time. The value of |
103 | this configuration should be between zero and two. The port | 111 | this configuration should be between zero and two. The port |
104 | must have been initialised by the boot-loader before use. | 112 | must have been initialised by the boot-loader before use. |
113 | |||
114 | # options for gpiolib support | ||
115 | |||
116 | config S3C_GPIO_SPACE | ||
117 | int "Space between gpio banks" | ||
118 | default 0 | ||
119 | help | ||
120 | Add a number of spare GPIO entries between each bank for debugging | ||
121 | purposes. This allows any problems where an counter overflows from | ||
122 | one bank to another to be caught, at the expense of using a little | ||
123 | more memory. | ||
124 | |||
125 | config S3C_GPIO_TRACK | ||
126 | bool | ||
127 | help | ||
128 | Internal configuration option to enable the s3c specific gpio | ||
129 | chip tracking if the platform requires it. | ||
130 | |||
131 | config S3C_GPIO_PULL_UPDOWN | ||
132 | bool | ||
133 | help | ||
134 | Internal configuration to enable the correct GPIO pull helper | ||
135 | |||
136 | config S3C_GPIO_PULL_DOWN | ||
137 | bool | ||
138 | help | ||
139 | Internal configuration to enable the correct GPIO pull helper | ||
140 | |||
141 | config S3C_GPIO_PULL_UP | ||
142 | bool | ||
143 | help | ||
144 | Internal configuration to enable the correct GPIO pull helper | ||
145 | |||
146 | config S3C_GPIO_CFG_S3C24XX | ||
147 | bool | ||
148 | help | ||
149 | Internal configuration to enable S3C24XX style GPIO configuration | ||
150 | functions. | ||
151 | |||
152 | config S3C_GPIO_CFG_S3C64XX | ||
153 | bool | ||
154 | help | ||
155 | Internal configuration to enable S3C64XX style GPIO configuration | ||
156 | functions. | ||
157 | |||
158 | # device definitions to compile in | ||
159 | |||
160 | config S3C_DEV_HSMMC | ||
161 | bool | ||
162 | depends on PLAT_S3C | ||
163 | help | ||
164 | Compile in platform device definitions for HSMMC code | ||
165 | |||
166 | config S3C_DEV_HSMMC1 | ||
167 | bool | ||
168 | depends on PLAT_S3C | ||
169 | help | ||
170 | Compile in platform device definitions for HSMMC channel 1 | ||
171 | |||
172 | config S3C_DEV_I2C1 | ||
173 | bool | ||
174 | depends on PLAT_S3C | ||
175 | help | ||
176 | Compile in platform device definitions for I2C channel 1 | ||
177 | |||
178 | config S3C_DEV_FB | ||
179 | bool | ||
180 | depends on PLAT_S3C | ||
181 | help | ||
182 | Compile in platform device definition for framebuffer | ||
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index f03d7b35ba37..39195f972d5e 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile | |||
@@ -1,3 +1,27 @@ | |||
1 | # dummy makefile, currently just including asm/arm/plat-s3c/include/plat | 1 | # arch/arm/plat-s3c/Makefile |
2 | # | ||
3 | # Copyright 2008 Simtec Electronics | ||
4 | # | ||
5 | # Licensed under GPLv2 | ||
2 | 6 | ||
3 | obj-n := dummy.o | 7 | obj-y := |
8 | obj-m := | ||
9 | obj-n := | ||
10 | obj- := | ||
11 | |||
12 | # Core support for all Samsung SoCs | ||
13 | |||
14 | obj-y += init.o | ||
15 | obj-y += time.o | ||
16 | obj-y += clock.o | ||
17 | obj-y += pwm-clock.o | ||
18 | obj-y += gpio.o | ||
19 | obj-y += gpio-config.o | ||
20 | |||
21 | # devices | ||
22 | |||
23 | obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o | ||
24 | obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o | ||
25 | obj-y += dev-i2c0.o | ||
26 | obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o | ||
27 | obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o | ||
diff --git a/arch/arm/plat-s3c/clock.c b/arch/arm/plat-s3c/clock.c new file mode 100644 index 000000000000..b6be76e2fe51 --- /dev/null +++ b/arch/arm/plat-s3c/clock.c | |||
@@ -0,0 +1,368 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/clock.c | ||
2 | * | ||
3 | * Copyright (c) 2004-2005 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C24XX Core clock control support | ||
7 | * | ||
8 | * Based on, and code from linux/arch/arm/mach-versatile/clock.c | ||
9 | ** | ||
10 | ** Copyright (C) 2004 ARM Limited. | ||
11 | ** Written by Deep Blue Solutions Limited. | ||
12 | * | ||
13 | * | ||
14 | * This program is free software; you can redistribute it and/or modify | ||
15 | * it under the terms of the GNU General Public License as published by | ||
16 | * the Free Software Foundation; either version 2 of the License, or | ||
17 | * (at your option) any later version. | ||
18 | * | ||
19 | * This program is distributed in the hope that it will be useful, | ||
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
22 | * GNU General Public License for more details. | ||
23 | * | ||
24 | * You should have received a copy of the GNU General Public License | ||
25 | * along with this program; if not, write to the Free Software | ||
26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
27 | */ | ||
28 | |||
29 | #include <linux/init.h> | ||
30 | #include <linux/module.h> | ||
31 | #include <linux/kernel.h> | ||
32 | #include <linux/list.h> | ||
33 | #include <linux/errno.h> | ||
34 | #include <linux/err.h> | ||
35 | #include <linux/platform_device.h> | ||
36 | #include <linux/sysdev.h> | ||
37 | #include <linux/interrupt.h> | ||
38 | #include <linux/ioport.h> | ||
39 | #include <linux/clk.h> | ||
40 | #include <linux/spinlock.h> | ||
41 | #include <linux/io.h> | ||
42 | |||
43 | #include <mach/hardware.h> | ||
44 | #include <asm/irq.h> | ||
45 | |||
46 | #include <plat/cpu-freq.h> | ||
47 | |||
48 | #include <plat/clock.h> | ||
49 | #include <plat/cpu.h> | ||
50 | |||
51 | /* clock information */ | ||
52 | |||
53 | static LIST_HEAD(clocks); | ||
54 | |||
55 | /* We originally used an mutex here, but some contexts (see resume) | ||
56 | * are calling functions such as clk_set_parent() with IRQs disabled | ||
57 | * causing an BUG to be triggered. | ||
58 | */ | ||
59 | DEFINE_SPINLOCK(clocks_lock); | ||
60 | |||
61 | /* enable and disable calls for use with the clk struct */ | ||
62 | |||
63 | static int clk_null_enable(struct clk *clk, int enable) | ||
64 | { | ||
65 | return 0; | ||
66 | } | ||
67 | |||
68 | /* Clock API calls */ | ||
69 | |||
70 | struct clk *clk_get(struct device *dev, const char *id) | ||
71 | { | ||
72 | struct clk *p; | ||
73 | struct clk *clk = ERR_PTR(-ENOENT); | ||
74 | int idno; | ||
75 | |||
76 | if (dev == NULL || dev->bus != &platform_bus_type) | ||
77 | idno = -1; | ||
78 | else | ||
79 | idno = to_platform_device(dev)->id; | ||
80 | |||
81 | spin_lock(&clocks_lock); | ||
82 | |||
83 | list_for_each_entry(p, &clocks, list) { | ||
84 | if (p->id == idno && | ||
85 | strcmp(id, p->name) == 0 && | ||
86 | try_module_get(p->owner)) { | ||
87 | clk = p; | ||
88 | break; | ||
89 | } | ||
90 | } | ||
91 | |||
92 | /* check for the case where a device was supplied, but the | ||
93 | * clock that was being searched for is not device specific */ | ||
94 | |||
95 | if (IS_ERR(clk)) { | ||
96 | list_for_each_entry(p, &clocks, list) { | ||
97 | if (p->id == -1 && strcmp(id, p->name) == 0 && | ||
98 | try_module_get(p->owner)) { | ||
99 | clk = p; | ||
100 | break; | ||
101 | } | ||
102 | } | ||
103 | } | ||
104 | |||
105 | spin_unlock(&clocks_lock); | ||
106 | return clk; | ||
107 | } | ||
108 | |||
109 | void clk_put(struct clk *clk) | ||
110 | { | ||
111 | module_put(clk->owner); | ||
112 | } | ||
113 | |||
114 | int clk_enable(struct clk *clk) | ||
115 | { | ||
116 | if (IS_ERR(clk) || clk == NULL) | ||
117 | return -EINVAL; | ||
118 | |||
119 | clk_enable(clk->parent); | ||
120 | |||
121 | spin_lock(&clocks_lock); | ||
122 | |||
123 | if ((clk->usage++) == 0) | ||
124 | (clk->enable)(clk, 1); | ||
125 | |||
126 | spin_unlock(&clocks_lock); | ||
127 | return 0; | ||
128 | } | ||
129 | |||
130 | void clk_disable(struct clk *clk) | ||
131 | { | ||
132 | if (IS_ERR(clk) || clk == NULL) | ||
133 | return; | ||
134 | |||
135 | spin_lock(&clocks_lock); | ||
136 | |||
137 | if ((--clk->usage) == 0) | ||
138 | (clk->enable)(clk, 0); | ||
139 | |||
140 | spin_unlock(&clocks_lock); | ||
141 | clk_disable(clk->parent); | ||
142 | } | ||
143 | |||
144 | |||
145 | unsigned long clk_get_rate(struct clk *clk) | ||
146 | { | ||
147 | if (IS_ERR(clk)) | ||
148 | return 0; | ||
149 | |||
150 | if (clk->rate != 0) | ||
151 | return clk->rate; | ||
152 | |||
153 | if (clk->get_rate != NULL) | ||
154 | return (clk->get_rate)(clk); | ||
155 | |||
156 | if (clk->parent != NULL) | ||
157 | return clk_get_rate(clk->parent); | ||
158 | |||
159 | return clk->rate; | ||
160 | } | ||
161 | |||
162 | long clk_round_rate(struct clk *clk, unsigned long rate) | ||
163 | { | ||
164 | if (!IS_ERR(clk) && clk->round_rate) | ||
165 | return (clk->round_rate)(clk, rate); | ||
166 | |||
167 | return rate; | ||
168 | } | ||
169 | |||
170 | int clk_set_rate(struct clk *clk, unsigned long rate) | ||
171 | { | ||
172 | int ret; | ||
173 | |||
174 | if (IS_ERR(clk)) | ||
175 | return -EINVAL; | ||
176 | |||
177 | /* We do not default just do a clk->rate = rate as | ||
178 | * the clock may have been made this way by choice. | ||
179 | */ | ||
180 | |||
181 | WARN_ON(clk->set_rate == NULL); | ||
182 | |||
183 | if (clk->set_rate == NULL) | ||
184 | return -EINVAL; | ||
185 | |||
186 | spin_lock(&clocks_lock); | ||
187 | ret = (clk->set_rate)(clk, rate); | ||
188 | spin_unlock(&clocks_lock); | ||
189 | |||
190 | return ret; | ||
191 | } | ||
192 | |||
193 | struct clk *clk_get_parent(struct clk *clk) | ||
194 | { | ||
195 | return clk->parent; | ||
196 | } | ||
197 | |||
198 | int clk_set_parent(struct clk *clk, struct clk *parent) | ||
199 | { | ||
200 | int ret = 0; | ||
201 | |||
202 | if (IS_ERR(clk)) | ||
203 | return -EINVAL; | ||
204 | |||
205 | spin_lock(&clocks_lock); | ||
206 | |||
207 | if (clk->set_parent) | ||
208 | ret = (clk->set_parent)(clk, parent); | ||
209 | |||
210 | spin_unlock(&clocks_lock); | ||
211 | |||
212 | return ret; | ||
213 | } | ||
214 | |||
215 | EXPORT_SYMBOL(clk_get); | ||
216 | EXPORT_SYMBOL(clk_put); | ||
217 | EXPORT_SYMBOL(clk_enable); | ||
218 | EXPORT_SYMBOL(clk_disable); | ||
219 | EXPORT_SYMBOL(clk_get_rate); | ||
220 | EXPORT_SYMBOL(clk_round_rate); | ||
221 | EXPORT_SYMBOL(clk_set_rate); | ||
222 | EXPORT_SYMBOL(clk_get_parent); | ||
223 | EXPORT_SYMBOL(clk_set_parent); | ||
224 | |||
225 | /* base clocks */ | ||
226 | |||
227 | static int clk_default_setrate(struct clk *clk, unsigned long rate) | ||
228 | { | ||
229 | clk->rate = rate; | ||
230 | return 0; | ||
231 | } | ||
232 | |||
233 | struct clk clk_xtal = { | ||
234 | .name = "xtal", | ||
235 | .id = -1, | ||
236 | .rate = 0, | ||
237 | .parent = NULL, | ||
238 | .ctrlbit = 0, | ||
239 | }; | ||
240 | |||
241 | struct clk clk_ext = { | ||
242 | .name = "ext", | ||
243 | .id = -1, | ||
244 | }; | ||
245 | |||
246 | struct clk clk_epll = { | ||
247 | .name = "epll", | ||
248 | .id = -1, | ||
249 | }; | ||
250 | |||
251 | struct clk clk_mpll = { | ||
252 | .name = "mpll", | ||
253 | .id = -1, | ||
254 | .set_rate = clk_default_setrate, | ||
255 | }; | ||
256 | |||
257 | struct clk clk_upll = { | ||
258 | .name = "upll", | ||
259 | .id = -1, | ||
260 | .parent = NULL, | ||
261 | .ctrlbit = 0, | ||
262 | }; | ||
263 | |||
264 | struct clk clk_f = { | ||
265 | .name = "fclk", | ||
266 | .id = -1, | ||
267 | .rate = 0, | ||
268 | .parent = &clk_mpll, | ||
269 | .ctrlbit = 0, | ||
270 | .set_rate = clk_default_setrate, | ||
271 | }; | ||
272 | |||
273 | struct clk clk_h = { | ||
274 | .name = "hclk", | ||
275 | .id = -1, | ||
276 | .rate = 0, | ||
277 | .parent = NULL, | ||
278 | .ctrlbit = 0, | ||
279 | .set_rate = clk_default_setrate, | ||
280 | }; | ||
281 | |||
282 | struct clk clk_p = { | ||
283 | .name = "pclk", | ||
284 | .id = -1, | ||
285 | .rate = 0, | ||
286 | .parent = NULL, | ||
287 | .ctrlbit = 0, | ||
288 | .set_rate = clk_default_setrate, | ||
289 | }; | ||
290 | |||
291 | struct clk clk_usb_bus = { | ||
292 | .name = "usb-bus", | ||
293 | .id = -1, | ||
294 | .rate = 0, | ||
295 | .parent = &clk_upll, | ||
296 | }; | ||
297 | |||
298 | |||
299 | |||
300 | struct clk s3c24xx_uclk = { | ||
301 | .name = "uclk", | ||
302 | .id = -1, | ||
303 | }; | ||
304 | |||
305 | /* initialise the clock system */ | ||
306 | |||
307 | int s3c24xx_register_clock(struct clk *clk) | ||
308 | { | ||
309 | clk->owner = THIS_MODULE; | ||
310 | |||
311 | if (clk->enable == NULL) | ||
312 | clk->enable = clk_null_enable; | ||
313 | |||
314 | /* add to the list of available clocks */ | ||
315 | |||
316 | /* Quick check to see if this clock has already been registered. */ | ||
317 | BUG_ON(clk->list.prev != clk->list.next); | ||
318 | |||
319 | spin_lock(&clocks_lock); | ||
320 | list_add(&clk->list, &clocks); | ||
321 | spin_unlock(&clocks_lock); | ||
322 | |||
323 | return 0; | ||
324 | } | ||
325 | |||
326 | int s3c24xx_register_clocks(struct clk **clks, int nr_clks) | ||
327 | { | ||
328 | int fails = 0; | ||
329 | |||
330 | for (; nr_clks > 0; nr_clks--, clks++) { | ||
331 | if (s3c24xx_register_clock(*clks) < 0) | ||
332 | fails++; | ||
333 | } | ||
334 | |||
335 | return fails; | ||
336 | } | ||
337 | |||
338 | /* initalise all the clocks */ | ||
339 | |||
340 | int __init s3c24xx_register_baseclocks(unsigned long xtal) | ||
341 | { | ||
342 | printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); | ||
343 | |||
344 | clk_xtal.rate = xtal; | ||
345 | |||
346 | /* register our clocks */ | ||
347 | |||
348 | if (s3c24xx_register_clock(&clk_xtal) < 0) | ||
349 | printk(KERN_ERR "failed to register master xtal\n"); | ||
350 | |||
351 | if (s3c24xx_register_clock(&clk_mpll) < 0) | ||
352 | printk(KERN_ERR "failed to register mpll clock\n"); | ||
353 | |||
354 | if (s3c24xx_register_clock(&clk_upll) < 0) | ||
355 | printk(KERN_ERR "failed to register upll clock\n"); | ||
356 | |||
357 | if (s3c24xx_register_clock(&clk_f) < 0) | ||
358 | printk(KERN_ERR "failed to register cpu fclk\n"); | ||
359 | |||
360 | if (s3c24xx_register_clock(&clk_h) < 0) | ||
361 | printk(KERN_ERR "failed to register cpu hclk\n"); | ||
362 | |||
363 | if (s3c24xx_register_clock(&clk_p) < 0) | ||
364 | printk(KERN_ERR "failed to register cpu pclk\n"); | ||
365 | |||
366 | return 0; | ||
367 | } | ||
368 | |||
diff --git a/arch/arm/plat-s3c/dev-fb.c b/arch/arm/plat-s3c/dev-fb.c new file mode 100644 index 000000000000..0454b8ec02e2 --- /dev/null +++ b/arch/arm/plat-s3c/dev-fb.c | |||
@@ -0,0 +1,72 @@ | |||
1 | /* linux/arch/arm/plat-s3c/dev-fb.c | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * S3C series device definition for framebuffer device | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/string.h> | ||
16 | #include <linux/platform_device.h> | ||
17 | #include <linux/fb.h> | ||
18 | |||
19 | #include <mach/map.h> | ||
20 | #include <mach/regs-fb.h> | ||
21 | |||
22 | #include <plat/fb.h> | ||
23 | #include <plat/devs.h> | ||
24 | #include <plat/cpu.h> | ||
25 | |||
26 | static struct resource s3c_fb_resource[] = { | ||
27 | [0] = { | ||
28 | .start = S3C_PA_FB, | ||
29 | .end = S3C_PA_FB + SZ_16K - 1, | ||
30 | .flags = IORESOURCE_MEM, | ||
31 | }, | ||
32 | [1] = { | ||
33 | .start = IRQ_LCD_VSYNC, | ||
34 | .end = IRQ_LCD_VSYNC, | ||
35 | .flags = IORESOURCE_IRQ, | ||
36 | }, | ||
37 | [2] = { | ||
38 | .start = IRQ_LCD_FIFO, | ||
39 | .end = IRQ_LCD_FIFO, | ||
40 | .flags = IORESOURCE_IRQ, | ||
41 | }, | ||
42 | [3] = { | ||
43 | .start = IRQ_LCD_SYSTEM, | ||
44 | .end = IRQ_LCD_SYSTEM, | ||
45 | .flags = IORESOURCE_IRQ, | ||
46 | }, | ||
47 | }; | ||
48 | |||
49 | struct platform_device s3c_device_fb = { | ||
50 | .name = "s3c-fb", | ||
51 | .id = -1, | ||
52 | .num_resources = ARRAY_SIZE(s3c_fb_resource), | ||
53 | .resource = s3c_fb_resource, | ||
54 | .dev.dma_mask = &s3c_device_fb.dev.coherent_dma_mask, | ||
55 | .dev.coherent_dma_mask = 0xffffffffUL, | ||
56 | }; | ||
57 | |||
58 | void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd) | ||
59 | { | ||
60 | struct s3c_fb_platdata *npd; | ||
61 | |||
62 | if (!pd) { | ||
63 | printk(KERN_ERR "%s: no platform data\n", __func__); | ||
64 | return; | ||
65 | } | ||
66 | |||
67 | npd = kmemdup(pd, sizeof(struct s3c_fb_platdata), GFP_KERNEL); | ||
68 | if (!npd) | ||
69 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
70 | |||
71 | s3c_device_fb.dev.platform_data = npd; | ||
72 | } | ||
diff --git a/arch/arm/plat-s3c/dev-hsmmc.c b/arch/arm/plat-s3c/dev-hsmmc.c new file mode 100644 index 000000000000..4c05b39810e2 --- /dev/null +++ b/arch/arm/plat-s3c/dev-hsmmc.c | |||
@@ -0,0 +1,68 @@ | |||
1 | /* linux/arch/arm/plat-s3c/dev-hsmmc.c | ||
2 | * | ||
3 | * Copyright (c) 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * S3C series device definition for hsmmc devices | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/platform_device.h> | ||
16 | #include <linux/mmc/host.h> | ||
17 | |||
18 | #include <mach/map.h> | ||
19 | #include <plat/sdhci.h> | ||
20 | #include <plat/devs.h> | ||
21 | #include <plat/cpu.h> | ||
22 | |||
23 | #define S3C_SZ_HSMMC (0x1000) | ||
24 | |||
25 | static struct resource s3c_hsmmc_resource[] = { | ||
26 | [0] = { | ||
27 | .start = S3C_PA_HSMMC0, | ||
28 | .end = S3C_PA_HSMMC0 + S3C_SZ_HSMMC - 1, | ||
29 | .flags = IORESOURCE_MEM, | ||
30 | }, | ||
31 | [1] = { | ||
32 | .start = IRQ_HSMMC0, | ||
33 | .end = IRQ_HSMMC0, | ||
34 | .flags = IORESOURCE_IRQ, | ||
35 | } | ||
36 | }; | ||
37 | |||
38 | static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL; | ||
39 | |||
40 | struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = { | ||
41 | .max_width = 4, | ||
42 | .host_caps = (MMC_CAP_4_BIT_DATA | | ||
43 | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), | ||
44 | }; | ||
45 | |||
46 | struct platform_device s3c_device_hsmmc0 = { | ||
47 | .name = "s3c-sdhci", | ||
48 | .id = 0, | ||
49 | .num_resources = ARRAY_SIZE(s3c_hsmmc_resource), | ||
50 | .resource = s3c_hsmmc_resource, | ||
51 | .dev = { | ||
52 | .dma_mask = &s3c_device_hsmmc_dmamask, | ||
53 | .coherent_dma_mask = 0xffffffffUL, | ||
54 | .platform_data = &s3c_hsmmc0_def_platdata, | ||
55 | }, | ||
56 | }; | ||
57 | |||
58 | void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd) | ||
59 | { | ||
60 | struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata; | ||
61 | |||
62 | set->max_width = pd->max_width; | ||
63 | |||
64 | if (pd->cfg_gpio) | ||
65 | set->cfg_gpio = pd->cfg_gpio; | ||
66 | if (pd->cfg_card) | ||
67 | set->cfg_card = pd->cfg_card; | ||
68 | } | ||
diff --git a/arch/arm/plat-s3c/dev-hsmmc1.c b/arch/arm/plat-s3c/dev-hsmmc1.c new file mode 100644 index 000000000000..e49bc4cd0ee6 --- /dev/null +++ b/arch/arm/plat-s3c/dev-hsmmc1.c | |||
@@ -0,0 +1,68 @@ | |||
1 | /* linux/arch/arm/plat-s3c/dev-hsmmc1.c | ||
2 | * | ||
3 | * Copyright (c) 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * S3C series device definition for hsmmc device 1 | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/platform_device.h> | ||
16 | #include <linux/mmc/host.h> | ||
17 | |||
18 | #include <mach/map.h> | ||
19 | #include <plat/sdhci.h> | ||
20 | #include <plat/devs.h> | ||
21 | #include <plat/cpu.h> | ||
22 | |||
23 | #define S3C_SZ_HSMMC (0x1000) | ||
24 | |||
25 | static struct resource s3c_hsmmc1_resource[] = { | ||
26 | [0] = { | ||
27 | .start = S3C_PA_HSMMC1, | ||
28 | .end = S3C_PA_HSMMC1 + S3C_SZ_HSMMC - 1, | ||
29 | .flags = IORESOURCE_MEM, | ||
30 | }, | ||
31 | [1] = { | ||
32 | .start = IRQ_HSMMC1, | ||
33 | .end = IRQ_HSMMC1, | ||
34 | .flags = IORESOURCE_IRQ, | ||
35 | } | ||
36 | }; | ||
37 | |||
38 | static u64 s3c_device_hsmmc1_dmamask = 0xffffffffUL; | ||
39 | |||
40 | struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = { | ||
41 | .max_width = 4, | ||
42 | .host_caps = (MMC_CAP_4_BIT_DATA | | ||
43 | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), | ||
44 | }; | ||
45 | |||
46 | struct platform_device s3c_device_hsmmc1 = { | ||
47 | .name = "s3c-sdhci", | ||
48 | .id = 1, | ||
49 | .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource), | ||
50 | .resource = s3c_hsmmc1_resource, | ||
51 | .dev = { | ||
52 | .dma_mask = &s3c_device_hsmmc1_dmamask, | ||
53 | .coherent_dma_mask = 0xffffffffUL, | ||
54 | .platform_data = &s3c_hsmmc1_def_platdata, | ||
55 | }, | ||
56 | }; | ||
57 | |||
58 | void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd) | ||
59 | { | ||
60 | struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata; | ||
61 | |||
62 | set->max_width = pd->max_width; | ||
63 | |||
64 | if (pd->cfg_gpio) | ||
65 | set->cfg_gpio = pd->cfg_gpio; | ||
66 | if (pd->cfg_card) | ||
67 | set->cfg_card = pd->cfg_card; | ||
68 | } | ||
diff --git a/arch/arm/plat-s3c/dev-i2c0.c b/arch/arm/plat-s3c/dev-i2c0.c new file mode 100644 index 000000000000..2c0128c77c6e --- /dev/null +++ b/arch/arm/plat-s3c/dev-i2c0.c | |||
@@ -0,0 +1,71 @@ | |||
1 | /* linux/arch/arm/plat-s3c/dev-i2c0.c | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * S3C series device definition for i2c device 0 | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/string.h> | ||
16 | #include <linux/platform_device.h> | ||
17 | |||
18 | #include <mach/map.h> | ||
19 | |||
20 | #include <plat/regs-iic.h> | ||
21 | #include <plat/iic.h> | ||
22 | #include <plat/devs.h> | ||
23 | #include <plat/cpu.h> | ||
24 | |||
25 | static struct resource s3c_i2c_resource[] = { | ||
26 | [0] = { | ||
27 | .start = S3C_PA_IIC, | ||
28 | .end = S3C_PA_IIC + SZ_4K - 1, | ||
29 | .flags = IORESOURCE_MEM, | ||
30 | }, | ||
31 | [1] = { | ||
32 | .start = IRQ_IIC, | ||
33 | .end = IRQ_IIC, | ||
34 | .flags = IORESOURCE_IRQ, | ||
35 | }, | ||
36 | }; | ||
37 | |||
38 | struct platform_device s3c_device_i2c0 = { | ||
39 | .name = "s3c2410-i2c", | ||
40 | #ifdef CONFIG_S3C_DEV_I2C1 | ||
41 | .id = 0, | ||
42 | #else | ||
43 | .id = -1, | ||
44 | #endif | ||
45 | .num_resources = ARRAY_SIZE(s3c_i2c_resource), | ||
46 | .resource = s3c_i2c_resource, | ||
47 | }; | ||
48 | |||
49 | static struct s3c2410_platform_i2c default_i2c_data0 __initdata = { | ||
50 | .flags = 0, | ||
51 | .slave_addr = 0x10, | ||
52 | .bus_freq = 100*1000, | ||
53 | .max_freq = 400*1000, | ||
54 | .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON, | ||
55 | }; | ||
56 | |||
57 | void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd) | ||
58 | { | ||
59 | struct s3c2410_platform_i2c *npd; | ||
60 | |||
61 | if (!pd) | ||
62 | pd = &default_i2c_data0; | ||
63 | |||
64 | npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL); | ||
65 | if (!npd) | ||
66 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
67 | else if (!npd->cfg_gpio) | ||
68 | npd->cfg_gpio = s3c_i2c0_cfg_gpio; | ||
69 | |||
70 | s3c_device_i2c0.dev.platform_data = npd; | ||
71 | } | ||
diff --git a/arch/arm/plat-s3c/dev-i2c1.c b/arch/arm/plat-s3c/dev-i2c1.c new file mode 100644 index 000000000000..9658fb0aec95 --- /dev/null +++ b/arch/arm/plat-s3c/dev-i2c1.c | |||
@@ -0,0 +1,68 @@ | |||
1 | /* linux/arch/arm/plat-s3c/dev-i2c1.c | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * S3C series device definition for i2c device 1 | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/string.h> | ||
16 | #include <linux/platform_device.h> | ||
17 | |||
18 | #include <mach/map.h> | ||
19 | |||
20 | #include <plat/regs-iic.h> | ||
21 | #include <plat/iic.h> | ||
22 | #include <plat/devs.h> | ||
23 | #include <plat/cpu.h> | ||
24 | |||
25 | static struct resource s3c_i2c_resource[] = { | ||
26 | [0] = { | ||
27 | .start = S3C_PA_IIC1, | ||
28 | .end = S3C_PA_IIC1 + SZ_4K - 1, | ||
29 | .flags = IORESOURCE_MEM, | ||
30 | }, | ||
31 | [1] = { | ||
32 | .start = IRQ_IIC1, | ||
33 | .end = IRQ_IIC1, | ||
34 | .flags = IORESOURCE_IRQ, | ||
35 | }, | ||
36 | }; | ||
37 | |||
38 | struct platform_device s3c_device_i2c1 = { | ||
39 | .name = "s3c2410-i2c", | ||
40 | .id = 1, | ||
41 | .num_resources = ARRAY_SIZE(s3c_i2c_resource), | ||
42 | .resource = s3c_i2c_resource, | ||
43 | }; | ||
44 | |||
45 | static struct s3c2410_platform_i2c default_i2c_data1 __initdata = { | ||
46 | .flags = 0, | ||
47 | .bus_num = 1, | ||
48 | .slave_addr = 0x10, | ||
49 | .bus_freq = 100*1000, | ||
50 | .max_freq = 400*1000, | ||
51 | .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON, | ||
52 | }; | ||
53 | |||
54 | void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd) | ||
55 | { | ||
56 | struct s3c2410_platform_i2c *npd; | ||
57 | |||
58 | if (!pd) | ||
59 | pd = &default_i2c_data1; | ||
60 | |||
61 | npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL); | ||
62 | if (!npd) | ||
63 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
64 | else if (!npd->cfg_gpio) | ||
65 | npd->cfg_gpio = s3c_i2c1_cfg_gpio; | ||
66 | |||
67 | s3c_device_i2c1.dev.platform_data = npd; | ||
68 | } | ||
diff --git a/arch/arm/plat-s3c/gpio-config.c b/arch/arm/plat-s3c/gpio-config.c new file mode 100644 index 000000000000..7642b975a998 --- /dev/null +++ b/arch/arm/plat-s3c/gpio-config.c | |||
@@ -0,0 +1,163 @@ | |||
1 | /* linux/arch/arm/plat-s3c/gpio-config.c | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C series GPIO configuration core | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/gpio.h> | ||
17 | #include <linux/io.h> | ||
18 | |||
19 | #include <mach/gpio-core.h> | ||
20 | #include <plat/gpio-cfg.h> | ||
21 | #include <plat/gpio-cfg-helpers.h> | ||
22 | |||
23 | int s3c_gpio_cfgpin(unsigned int pin, unsigned int config) | ||
24 | { | ||
25 | struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); | ||
26 | unsigned long flags; | ||
27 | int offset; | ||
28 | int ret; | ||
29 | |||
30 | if (!chip) | ||
31 | return -EINVAL; | ||
32 | |||
33 | offset = pin - chip->chip.base; | ||
34 | |||
35 | local_irq_save(flags); | ||
36 | ret = s3c_gpio_do_setcfg(chip, offset, config); | ||
37 | local_irq_restore(flags); | ||
38 | |||
39 | return ret; | ||
40 | } | ||
41 | |||
42 | int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull) | ||
43 | { | ||
44 | struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); | ||
45 | unsigned long flags; | ||
46 | int offset, ret; | ||
47 | |||
48 | if (!chip) | ||
49 | return -EINVAL; | ||
50 | |||
51 | offset = pin - chip->chip.base; | ||
52 | |||
53 | local_irq_save(flags); | ||
54 | ret = s3c_gpio_do_setpull(chip, offset, pull); | ||
55 | local_irq_restore(flags); | ||
56 | |||
57 | return ret; | ||
58 | } | ||
59 | |||
60 | #ifdef CONFIG_S3C_GPIO_CFG_S3C24XX | ||
61 | int s3c_gpio_setcfg_s3c24xx_banka(struct s3c_gpio_chip *chip, | ||
62 | unsigned int off, unsigned int cfg) | ||
63 | { | ||
64 | void __iomem *reg = chip->base; | ||
65 | unsigned int shift = off; | ||
66 | u32 con; | ||
67 | |||
68 | if (s3c_gpio_is_cfg_special(cfg)) { | ||
69 | cfg &= 0xf; | ||
70 | |||
71 | /* Map output to 0, and SFN2 to 1 */ | ||
72 | cfg -= 1; | ||
73 | if (cfg > 1) | ||
74 | return -EINVAL; | ||
75 | |||
76 | cfg <<= shift; | ||
77 | } | ||
78 | |||
79 | con = __raw_readl(reg); | ||
80 | con &= ~(0x1 << shift); | ||
81 | con |= cfg; | ||
82 | __raw_writel(con, reg); | ||
83 | |||
84 | return 0; | ||
85 | } | ||
86 | |||
87 | int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, | ||
88 | unsigned int off, unsigned int cfg) | ||
89 | { | ||
90 | void __iomem *reg = chip->base; | ||
91 | unsigned int shift = off * 2; | ||
92 | u32 con; | ||
93 | |||
94 | if (s3c_gpio_is_cfg_special(cfg)) { | ||
95 | cfg &= 0xf; | ||
96 | if (cfg > 3) | ||
97 | return -EINVAL; | ||
98 | |||
99 | cfg <<= shift; | ||
100 | } | ||
101 | |||
102 | con = __raw_readl(reg); | ||
103 | con &= ~(0x3 << shift); | ||
104 | con |= cfg; | ||
105 | __raw_writel(con, reg); | ||
106 | |||
107 | return 0; | ||
108 | } | ||
109 | #endif | ||
110 | |||
111 | #ifdef CONFIG_S3C_GPIO_CFG_S3C64XX | ||
112 | int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, | ||
113 | unsigned int off, unsigned int cfg) | ||
114 | { | ||
115 | void __iomem *reg = chip->base; | ||
116 | unsigned int shift = (off & 7) * 4; | ||
117 | u32 con; | ||
118 | |||
119 | if (off < 8 && chip->chip.ngpio >= 8) | ||
120 | reg -= 4; | ||
121 | |||
122 | if (s3c_gpio_is_cfg_special(cfg)) { | ||
123 | cfg &= 0xf; | ||
124 | cfg <<= shift; | ||
125 | } | ||
126 | |||
127 | con = __raw_readl(reg); | ||
128 | con &= ~(0xf << shift); | ||
129 | con |= cfg; | ||
130 | __raw_writel(con, reg); | ||
131 | |||
132 | return 0; | ||
133 | } | ||
134 | #endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */ | ||
135 | |||
136 | #ifdef CONFIG_S3C_GPIO_PULL_UPDOWN | ||
137 | int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip, | ||
138 | unsigned int off, s3c_gpio_pull_t pull) | ||
139 | { | ||
140 | void __iomem *reg = chip->base + 0x08; | ||
141 | int shift = off * 2; | ||
142 | u32 pup; | ||
143 | |||
144 | pup = __raw_readl(reg); | ||
145 | pup &= ~(3 << shift); | ||
146 | pup |= pull << shift; | ||
147 | __raw_writel(pup, reg); | ||
148 | |||
149 | return 0; | ||
150 | } | ||
151 | |||
152 | s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip, | ||
153 | unsigned int off) | ||
154 | { | ||
155 | void __iomem *reg = chip->base + 0x08; | ||
156 | int shift = off * 2; | ||
157 | u32 pup = __raw_readl(reg); | ||
158 | |||
159 | pup >>= shift; | ||
160 | pup &= 0x3; | ||
161 | return (__force s3c_gpio_pull_t)pup; | ||
162 | } | ||
163 | #endif | ||
diff --git a/arch/arm/plat-s3c/gpio.c b/arch/arm/plat-s3c/gpio.c new file mode 100644 index 000000000000..d71dd6d9ce5c --- /dev/null +++ b/arch/arm/plat-s3c/gpio.c | |||
@@ -0,0 +1,147 @@ | |||
1 | /* linux/arch/arm/plat-s3c/gpio.c | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * S3C series GPIO core | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/init.h> | ||
16 | #include <linux/io.h> | ||
17 | #include <linux/gpio.h> | ||
18 | |||
19 | #include <plat/gpio-core.h> | ||
20 | |||
21 | #ifdef CONFIG_S3C_GPIO_TRACK | ||
22 | struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; | ||
23 | |||
24 | static __init void s3c_gpiolib_track(struct s3c_gpio_chip *chip) | ||
25 | { | ||
26 | unsigned int gpn; | ||
27 | int i; | ||
28 | |||
29 | gpn = chip->chip.base; | ||
30 | for (i = 0; i < chip->chip.ngpio; i++, gpn++) { | ||
31 | BUG_ON(gpn > ARRAY_SIZE(s3c_gpios)); | ||
32 | s3c_gpios[gpn] = chip; | ||
33 | } | ||
34 | } | ||
35 | #endif /* CONFIG_S3C_GPIO_TRACK */ | ||
36 | |||
37 | /* Default routines for controlling GPIO, based on the original S3C24XX | ||
38 | * GPIO functions which deal with the case where each gpio bank of the | ||
39 | * chip is as following: | ||
40 | * | ||
41 | * base + 0x00: Control register, 2 bits per gpio | ||
42 | * gpio n: 2 bits starting at (2*n) | ||
43 | * 00 = input, 01 = output, others mean special-function | ||
44 | * base + 0x04: Data register, 1 bit per gpio | ||
45 | * bit n: data bit n | ||
46 | */ | ||
47 | |||
48 | static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset) | ||
49 | { | ||
50 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
51 | void __iomem *base = ourchip->base; | ||
52 | unsigned long flags; | ||
53 | unsigned long con; | ||
54 | |||
55 | local_irq_save(flags); | ||
56 | |||
57 | con = __raw_readl(base + 0x00); | ||
58 | con &= ~(3 << (offset * 2)); | ||
59 | |||
60 | __raw_writel(con, base + 0x00); | ||
61 | |||
62 | local_irq_restore(flags); | ||
63 | return 0; | ||
64 | } | ||
65 | |||
66 | static int s3c_gpiolib_output(struct gpio_chip *chip, | ||
67 | unsigned offset, int value) | ||
68 | { | ||
69 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
70 | void __iomem *base = ourchip->base; | ||
71 | unsigned long flags; | ||
72 | unsigned long dat; | ||
73 | unsigned long con; | ||
74 | |||
75 | local_irq_save(flags); | ||
76 | |||
77 | dat = __raw_readl(base + 0x04); | ||
78 | dat &= ~(1 << offset); | ||
79 | if (value) | ||
80 | dat |= 1 << offset; | ||
81 | __raw_writel(dat, base + 0x04); | ||
82 | |||
83 | con = __raw_readl(base + 0x00); | ||
84 | con &= ~(3 << (offset * 2)); | ||
85 | con |= 1 << (offset * 2); | ||
86 | |||
87 | __raw_writel(con, base + 0x00); | ||
88 | __raw_writel(dat, base + 0x04); | ||
89 | |||
90 | local_irq_restore(flags); | ||
91 | return 0; | ||
92 | } | ||
93 | |||
94 | static void s3c_gpiolib_set(struct gpio_chip *chip, | ||
95 | unsigned offset, int value) | ||
96 | { | ||
97 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
98 | void __iomem *base = ourchip->base; | ||
99 | unsigned long flags; | ||
100 | unsigned long dat; | ||
101 | |||
102 | local_irq_save(flags); | ||
103 | |||
104 | dat = __raw_readl(base + 0x04); | ||
105 | dat &= ~(1 << offset); | ||
106 | if (value) | ||
107 | dat |= 1 << offset; | ||
108 | __raw_writel(dat, base + 0x04); | ||
109 | |||
110 | local_irq_restore(flags); | ||
111 | } | ||
112 | |||
113 | static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset) | ||
114 | { | ||
115 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
116 | unsigned long val; | ||
117 | |||
118 | val = __raw_readl(ourchip->base + 0x04); | ||
119 | val >>= offset; | ||
120 | val &= 1; | ||
121 | |||
122 | return val; | ||
123 | } | ||
124 | |||
125 | __init void s3c_gpiolib_add(struct s3c_gpio_chip *chip) | ||
126 | { | ||
127 | struct gpio_chip *gc = &chip->chip; | ||
128 | int ret; | ||
129 | |||
130 | BUG_ON(!chip->base); | ||
131 | BUG_ON(!gc->label); | ||
132 | BUG_ON(!gc->ngpio); | ||
133 | |||
134 | if (!gc->direction_input) | ||
135 | gc->direction_input = s3c_gpiolib_input; | ||
136 | if (!gc->direction_output) | ||
137 | gc->direction_output = s3c_gpiolib_output; | ||
138 | if (!gc->set) | ||
139 | gc->set = s3c_gpiolib_set; | ||
140 | if (!gc->get) | ||
141 | gc->get = s3c_gpiolib_get; | ||
142 | |||
143 | /* gpiochip_add() prints own failure message on error. */ | ||
144 | ret = gpiochip_add(gc); | ||
145 | if (ret >= 0) | ||
146 | s3c_gpiolib_track(chip); | ||
147 | } | ||
diff --git a/arch/arm/plat-s3c/include/mach/io.h b/arch/arm/plat-s3c/include/mach/io.h new file mode 100644 index 000000000000..10d28d66ace3 --- /dev/null +++ b/arch/arm/plat-s3c/include/mach/io.h | |||
@@ -0,0 +1,18 @@ | |||
1 | /* arch/arm/plat-s3c/include/mach/io.h | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben-linux@fluff.org> | ||
5 | * | ||
6 | * Default IO routines for plat-s3c based systems, such as S3C24A0 | ||
7 | */ | ||
8 | |||
9 | #ifndef __ASM_ARM_ARCH_IO_H | ||
10 | #define __ASM_ARM_ARCH_IO_H | ||
11 | |||
12 | /* No current ISA/PCI bus support. */ | ||
13 | #define __io(a) ((void __iomem *)(a)) | ||
14 | #define __mem_pci(a) (a) | ||
15 | |||
16 | #define IO_SPACE_LIMIT (0xFFFFFFFF) | ||
17 | |||
18 | #endif | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/timex.h b/arch/arm/plat-s3c/include/mach/timex.h index 2a425ed0a7e0..2a425ed0a7e0 100644 --- a/arch/arm/mach-s3c2410/include/mach/timex.h +++ b/arch/arm/plat-s3c/include/mach/timex.h | |||
diff --git a/arch/arm/mach-s3c2410/include/mach/vmalloc.h b/arch/arm/plat-s3c/include/mach/vmalloc.h index 315b0078a34d..bfd2ca6e3074 100644 --- a/arch/arm/mach-s3c2410/include/mach/vmalloc.h +++ b/arch/arm/plat-s3c/include/mach/vmalloc.h | |||
@@ -1,4 +1,4 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/vmalloc.h | 1 | /* arch/arm/plat-s3c/include/mach/vmalloc.h |
2 | * | 2 | * |
3 | * from arch/arm/mach-iop3xx/include/mach/vmalloc.h | 3 | * from arch/arm/mach-iop3xx/include/mach/vmalloc.h |
4 | * | 4 | * |
diff --git a/arch/arm/plat-s3c/include/plat/adc.h b/arch/arm/plat-s3c/include/plat/adc.h new file mode 100644 index 000000000000..43df2a404b0b --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/adc.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* arch/arm/plat-s3c/include/plat/adc.h | ||
2 | * | ||
3 | * Copyright (c) 2008 Simtec Electronics | ||
4 | * http://armlinux.simnte.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C24XX ADC driver information | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_PLAT_ADC_H | ||
15 | #define __ASM_PLAT_ADC_H __FILE__ | ||
16 | |||
17 | struct s3c_adc_client; | ||
18 | |||
19 | extern int s3c_adc_start(struct s3c_adc_client *client, | ||
20 | unsigned int channel, unsigned int nr_samples); | ||
21 | |||
22 | extern struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev, | ||
23 | void (*select)(unsigned selected), | ||
24 | void (*conv)(unsigned d0, unsigned d1), | ||
25 | unsigned int is_ts); | ||
26 | |||
27 | extern void s3c_adc_release(struct s3c_adc_client *client); | ||
28 | |||
29 | #endif /* __ASM_PLAT_ADC_H */ | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/clock.h b/arch/arm/plat-s3c/include/plat/clock.h index 235b753cd877..a10622eed43a 100644 --- a/arch/arm/plat-s3c24xx/include/plat/clock.h +++ b/arch/arm/plat-s3c/include/plat/clock.h | |||
@@ -1,5 +1,4 @@ | |||
1 | /* linux/include/asm-arm/plat-s3c24xx/clock.h | 1 | /* linux/arch/arm/plat-s3c/include/plat/clock.h |
2 | * linux/arch/arm/mach-s3c2410/clock.h | ||
3 | * | 2 | * |
4 | * Copyright (c) 2004-2005 Simtec Electronics | 3 | * Copyright (c) 2004-2005 Simtec Electronics |
5 | * http://www.simtec.co.uk/products/SWLINUX/ | 4 | * http://www.simtec.co.uk/products/SWLINUX/ |
@@ -10,6 +9,8 @@ | |||
10 | * published by the Free Software Foundation. | 9 | * published by the Free Software Foundation. |
11 | */ | 10 | */ |
12 | 11 | ||
12 | #include <linux/spinlock.h> | ||
13 | |||
13 | struct clk { | 14 | struct clk { |
14 | struct list_head list; | 15 | struct list_head list; |
15 | struct module *owner; | 16 | struct module *owner; |
@@ -44,21 +45,44 @@ extern struct clk clk_h; | |||
44 | extern struct clk clk_p; | 45 | extern struct clk clk_p; |
45 | extern struct clk clk_mpll; | 46 | extern struct clk clk_mpll; |
46 | extern struct clk clk_upll; | 47 | extern struct clk clk_upll; |
48 | extern struct clk clk_epll; | ||
47 | extern struct clk clk_xtal; | 49 | extern struct clk clk_xtal; |
50 | extern struct clk clk_ext; | ||
51 | |||
52 | /* S3C64XX specific clocks */ | ||
53 | extern struct clk clk_27m; | ||
54 | extern struct clk clk_48m; | ||
48 | 55 | ||
49 | /* exports for arch/arm/mach-s3c2410 | 56 | /* exports for arch/arm/mach-s3c2410 |
50 | * | 57 | * |
51 | * Please DO NOT use these outside of arch/arm/mach-s3c2410 | 58 | * Please DO NOT use these outside of arch/arm/mach-s3c2410 |
52 | */ | 59 | */ |
53 | 60 | ||
54 | extern struct mutex clocks_mutex; | 61 | extern spinlock_t clocks_lock; |
55 | 62 | ||
56 | extern int s3c2410_clkcon_enable(struct clk *clk, int enable); | 63 | extern int s3c2410_clkcon_enable(struct clk *clk, int enable); |
57 | 64 | ||
58 | extern int s3c24xx_register_clock(struct clk *clk); | 65 | extern int s3c24xx_register_clock(struct clk *clk); |
59 | extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks); | 66 | extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks); |
60 | 67 | ||
61 | extern int s3c24xx_setup_clocks(unsigned long xtal, | 68 | extern int s3c24xx_register_baseclocks(unsigned long xtal); |
62 | unsigned long fclk, | 69 | |
63 | unsigned long hclk, | 70 | extern void s3c64xx_register_clocks(void); |
64 | unsigned long pclk); | 71 | |
72 | extern void s3c24xx_setup_clocks(unsigned long fclk, | ||
73 | unsigned long hclk, | ||
74 | unsigned long pclk); | ||
75 | |||
76 | extern void s3c2410_setup_clocks(void); | ||
77 | extern void s3c2412_setup_clocks(void); | ||
78 | extern void s3c244x_setup_clocks(void); | ||
79 | extern void s3c2443_setup_clocks(void); | ||
80 | |||
81 | /* S3C64XX specific functions and clocks */ | ||
82 | |||
83 | extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable); | ||
84 | |||
85 | /* Init for pwm clock code */ | ||
86 | |||
87 | extern void s3c_pwmclk_init(void); | ||
88 | |||
diff --git a/arch/arm/plat-s3c/include/plat/cpu-freq.h b/arch/arm/plat-s3c/include/plat/cpu-freq.h new file mode 100644 index 000000000000..c86a13307e90 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/cpu-freq.h | |||
@@ -0,0 +1,94 @@ | |||
1 | /* arch/arm/plat-s3c/include/plat/cpu-freq.h | ||
2 | * | ||
3 | * Copyright (c) 2006,2007 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C CPU frequency scaling support - driver and board | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/cpufreq.h> | ||
15 | |||
16 | struct s3c_cpufreq_info; | ||
17 | struct s3c_cpufreq_board; | ||
18 | struct s3c_iotimings; | ||
19 | |||
20 | struct s3c_freq { | ||
21 | unsigned long fclk; | ||
22 | unsigned long armclk; | ||
23 | unsigned long hclk_tns; /* in 10ths of ns */ | ||
24 | unsigned long hclk; | ||
25 | unsigned long pclk; | ||
26 | }; | ||
27 | |||
28 | /* wrapper 'struct cpufreq_freqs' so that any drivers receiving the | ||
29 | * notification can use this information that is not provided by just | ||
30 | * having the core frequency alone. | ||
31 | */ | ||
32 | |||
33 | struct s3c_cpufreq_freqs { | ||
34 | struct cpufreq_freqs freqs; | ||
35 | struct s3c_freq old; | ||
36 | struct s3c_freq new; | ||
37 | }; | ||
38 | |||
39 | #define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs) | ||
40 | |||
41 | struct s3c_clkdivs { | ||
42 | int p_divisor; /* fclk / pclk */ | ||
43 | int h_divisor; /* fclk / hclk */ | ||
44 | int arm_divisor; /* not all cpus have this. */ | ||
45 | unsigned char dvs; /* using dvs mode to arm. */ | ||
46 | }; | ||
47 | |||
48 | #define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s)) | ||
49 | |||
50 | struct s3c_pllval { | ||
51 | unsigned long freq; | ||
52 | unsigned long pll_reg; | ||
53 | }; | ||
54 | |||
55 | struct s3c_cpufreq_config { | ||
56 | struct s3c_freq freq; | ||
57 | struct s3c_pllval pll; | ||
58 | struct s3c_clkdivs divs; | ||
59 | struct s3c_cpufreq_info *info; /* for core, not drivers */ | ||
60 | struct s3c_cpufreq_board *board; | ||
61 | }; | ||
62 | |||
63 | /* s3c_cpufreq_board | ||
64 | * | ||
65 | * per-board configuraton information, such as memory refresh and | ||
66 | * how to initialise IO timings. | ||
67 | */ | ||
68 | struct s3c_cpufreq_board { | ||
69 | unsigned int refresh; /* refresh period in ns */ | ||
70 | unsigned int auto_io:1; /* automatically init io timings. */ | ||
71 | unsigned int need_io:1; /* set if needs io timing support. */ | ||
72 | |||
73 | /* any non-zero field in here is taken as an upper limit. */ | ||
74 | struct s3c_freq max; /* frequency limits */ | ||
75 | }; | ||
76 | |||
77 | /* Things depending on frequency scaling. */ | ||
78 | #ifdef CONFIG_CPU_FREQ_S3C | ||
79 | #define __init_or_cpufreq | ||
80 | #else | ||
81 | #define __init_or_cpufreq __init | ||
82 | #endif | ||
83 | |||
84 | /* Board functions */ | ||
85 | |||
86 | #ifdef CONFIG_CPU_FREQ_S3C | ||
87 | extern int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board); | ||
88 | #else | ||
89 | |||
90 | static inline int s3c_cpufreq_setboard(struct s3c_cpufreq_board *board) | ||
91 | { | ||
92 | return 0; | ||
93 | } | ||
94 | #endif /* CONFIG_CPU_FREQ_S3C */ | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h index 23e420e8bd5b..e62ae0fcfe56 100644 --- a/arch/arm/plat-s3c24xx/include/plat/cpu.h +++ b/arch/arm/plat-s3c/include/plat/cpu.h | |||
@@ -1,4 +1,4 @@ | |||
1 | /* linux/include/asm-arm/plat-s3c24xx/cpu.h | 1 | /* linux/arch/arm/plat-s3c/include/plat/cpu.h |
2 | * | 2 | * |
3 | * Copyright (c) 2004-2005 Simtec Electronics | 3 | * Copyright (c) 2004-2005 Simtec Electronics |
4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
@@ -18,7 +18,7 @@ | |||
18 | #define MHZ (1000*1000) | 18 | #define MHZ (1000*1000) |
19 | #endif | 19 | #endif |
20 | 20 | ||
21 | #define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000) | 21 | #define print_mhz(m) ((m) / MHZ), (((m) / 1000) % 1000) |
22 | 22 | ||
23 | /* forward declaration */ | 23 | /* forward declaration */ |
24 | struct s3c24xx_uart_resources; | 24 | struct s3c24xx_uart_resources; |
@@ -26,11 +26,28 @@ struct platform_device; | |||
26 | struct s3c2410_uartcfg; | 26 | struct s3c2410_uartcfg; |
27 | struct map_desc; | 27 | struct map_desc; |
28 | 28 | ||
29 | /* per-cpu initialisation function table. */ | ||
30 | |||
31 | struct cpu_table { | ||
32 | unsigned long idcode; | ||
33 | unsigned long idmask; | ||
34 | void (*map_io)(void); | ||
35 | void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no); | ||
36 | void (*init_clocks)(int xtal); | ||
37 | int (*init)(void); | ||
38 | const char *name; | ||
39 | }; | ||
40 | |||
41 | extern void s3c_init_cpu(unsigned long idcode, | ||
42 | struct cpu_table *cpus, unsigned int cputab_size); | ||
43 | |||
29 | /* core initialisation functions */ | 44 | /* core initialisation functions */ |
30 | 45 | ||
31 | extern void s3c24xx_init_irq(void); | 46 | extern void s3c24xx_init_irq(void); |
47 | extern void s3c64xx_init_irq(u32 vic0, u32 vic1); | ||
32 | 48 | ||
33 | extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); | 49 | extern void s3c24xx_init_io(struct map_desc *mach_desc, int size); |
50 | extern void s3c64xx_init_io(struct map_desc *mach_desc, int size); | ||
34 | 51 | ||
35 | extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); | 52 | extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); |
36 | 53 | ||
diff --git a/arch/arm/plat-s3c/include/plat/debug-macro.S b/arch/arm/plat-s3c/include/plat/debug-macro.S index 4aa7e2e6c001..3634d4e3708b 100644 --- a/arch/arm/plat-s3c/include/plat/debug-macro.S +++ b/arch/arm/plat-s3c/include/plat/debug-macro.S | |||
@@ -20,7 +20,7 @@ | |||
20 | .endm | 20 | .endm |
21 | 21 | ||
22 | #ifndef fifo_level | 22 | #ifndef fifo_level |
23 | #define fifo_level fifo_level_s3c2410 | 23 | #define fifo_level fifo_level_s3c2440 |
24 | #endif | 24 | #endif |
25 | 25 | ||
26 | .macro fifo_full_s3c2440 rd, rx | 26 | .macro fifo_full_s3c2440 rd, rx |
diff --git a/arch/arm/plat-s3c24xx/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h index badaac9d64a8..6b1b5231511c 100644 --- a/arch/arm/plat-s3c24xx/include/plat/devs.h +++ b/arch/arm/plat-s3c/include/plat/devs.h | |||
@@ -17,21 +17,26 @@ struct s3c24xx_uart_resources { | |||
17 | }; | 17 | }; |
18 | 18 | ||
19 | extern struct s3c24xx_uart_resources s3c2410_uart_resources[]; | 19 | extern struct s3c24xx_uart_resources s3c2410_uart_resources[]; |
20 | extern struct s3c24xx_uart_resources s3c64xx_uart_resources[]; | ||
20 | 21 | ||
21 | extern struct platform_device *s3c24xx_uart_devs[]; | 22 | extern struct platform_device *s3c24xx_uart_devs[]; |
22 | extern struct platform_device *s3c24xx_uart_src[]; | 23 | extern struct platform_device *s3c24xx_uart_src[]; |
23 | 24 | ||
24 | extern struct platform_device s3c_device_timer[]; | 25 | extern struct platform_device s3c_device_timer[]; |
25 | 26 | ||
27 | extern struct platform_device s3c_device_fb; | ||
26 | extern struct platform_device s3c_device_usb; | 28 | extern struct platform_device s3c_device_usb; |
27 | extern struct platform_device s3c_device_lcd; | 29 | extern struct platform_device s3c_device_lcd; |
28 | extern struct platform_device s3c_device_wdt; | 30 | extern struct platform_device s3c_device_wdt; |
29 | extern struct platform_device s3c_device_i2c; | 31 | extern struct platform_device s3c_device_i2c0; |
32 | extern struct platform_device s3c_device_i2c1; | ||
30 | extern struct platform_device s3c_device_iis; | 33 | extern struct platform_device s3c_device_iis; |
31 | extern struct platform_device s3c_device_rtc; | 34 | extern struct platform_device s3c_device_rtc; |
32 | extern struct platform_device s3c_device_adc; | 35 | extern struct platform_device s3c_device_adc; |
33 | extern struct platform_device s3c_device_sdi; | 36 | extern struct platform_device s3c_device_sdi; |
34 | extern struct platform_device s3c_device_hsmmc; | 37 | extern struct platform_device s3c_device_hsmmc0; |
38 | extern struct platform_device s3c_device_hsmmc1; | ||
39 | extern struct platform_device s3c_device_hsmmc2; | ||
35 | 40 | ||
36 | extern struct platform_device s3c_device_spi0; | 41 | extern struct platform_device s3c_device_spi0; |
37 | extern struct platform_device s3c_device_spi1; | 42 | extern struct platform_device s3c_device_spi1; |
diff --git a/arch/arm/plat-s3c/include/plat/fb.h b/arch/arm/plat-s3c/include/plat/fb.h new file mode 100644 index 000000000000..214ff561b0dd --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/fb.h | |||
@@ -0,0 +1,73 @@ | |||
1 | /* linux/arch/arm/plat-s3c/include/plat/fb.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * | ||
8 | * S3C - FB platform data definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __PLAT_S3C_FB_H | ||
16 | #define __PLAT_S3C_FB_H __FILE__ | ||
17 | |||
18 | /** | ||
19 | * struct s3c_fb_pd_win - per window setup data | ||
20 | * @win_mode: The display parameters to initialise (not for window 0) | ||
21 | * @virtual_x: The virtual X size. | ||
22 | * @virtual_y: The virtual Y size. | ||
23 | */ | ||
24 | struct s3c_fb_pd_win { | ||
25 | struct fb_videomode win_mode; | ||
26 | |||
27 | unsigned short default_bpp; | ||
28 | unsigned short max_bpp; | ||
29 | unsigned short virtual_x; | ||
30 | unsigned short virtual_y; | ||
31 | }; | ||
32 | |||
33 | /** | ||
34 | * struct s3c_fb_platdata - S3C driver platform specific information | ||
35 | * @setup_gpio: Setup the external GPIO pins to the right state to transfer | ||
36 | * the data from the display system to the connected display | ||
37 | * device. | ||
38 | * @vidcon0: The base vidcon0 values to control the panel data format. | ||
39 | * @vidcon1: The base vidcon1 values to control the panel data output. | ||
40 | * @win: The setup data for each hardware window, or NULL for unused. | ||
41 | * @display_mode: The LCD output display mode. | ||
42 | * | ||
43 | * The platform data supplies the video driver with all the information | ||
44 | * it requires to work with the display(s) attached to the machine. It | ||
45 | * controls the initial mode, the number of display windows (0 is always | ||
46 | * the base framebuffer) that are initialised etc. | ||
47 | * | ||
48 | */ | ||
49 | struct s3c_fb_platdata { | ||
50 | void (*setup_gpio)(void); | ||
51 | |||
52 | struct s3c_fb_pd_win *win[S3C_FB_MAX_WIN]; | ||
53 | |||
54 | u32 vidcon0; | ||
55 | u32 vidcon1; | ||
56 | }; | ||
57 | |||
58 | /** | ||
59 | * s3c_fb_set_platdata() - Setup the FB device with platform data. | ||
60 | * @pd: The platform data to set. The data is copied from the passed structure | ||
61 | * so the machine data can mark the data __initdata so that any unused | ||
62 | * machines will end up dumping their data at runtime. | ||
63 | */ | ||
64 | extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd); | ||
65 | |||
66 | /** | ||
67 | * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD | ||
68 | * | ||
69 | * Initialise the GPIO for an 24bpp LCD display on the RGB interface. | ||
70 | */ | ||
71 | extern void s3c64xx_fb_gpio_setup_24bpp(void); | ||
72 | |||
73 | #endif /* __PLAT_S3C_FB_H */ | ||
diff --git a/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h new file mode 100644 index 000000000000..652e2bbdaa20 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/gpio-cfg-helpers.h | |||
@@ -0,0 +1,176 @@ | |||
1 | /* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * | ||
8 | * S3C Platform - GPIO pin configuration helper definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | /* This is meant for core cpu support, machine or other driver files | ||
16 | * should not be including this header. | ||
17 | */ | ||
18 | |||
19 | #ifndef __PLAT_GPIO_CFG_HELPERS_H | ||
20 | #define __PLAT_GPIO_CFG_HELPERS_H __FILE__ | ||
21 | |||
22 | /* As a note, all gpio configuration functions are entered exclusively, either | ||
23 | * with the relevant lock held or the system prevented from doing anything else | ||
24 | * by disabling interrupts. | ||
25 | */ | ||
26 | |||
27 | static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip, | ||
28 | unsigned int off, unsigned int config) | ||
29 | { | ||
30 | return (chip->config->set_config)(chip, off, config); | ||
31 | } | ||
32 | |||
33 | static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip, | ||
34 | unsigned int off, s3c_gpio_pull_t pull) | ||
35 | { | ||
36 | return (chip->config->set_pull)(chip, off, pull); | ||
37 | } | ||
38 | |||
39 | /** | ||
40 | * s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration. | ||
41 | * @chip: The gpio chip that is being configured. | ||
42 | * @off: The offset for the GPIO being configured. | ||
43 | * @cfg: The configuration value to set. | ||
44 | * | ||
45 | * This helper deal with the GPIO cases where the control register | ||
46 | * has two bits of configuration per gpio, which have the following | ||
47 | * functions: | ||
48 | * 00 = input | ||
49 | * 01 = output | ||
50 | * 1x = special function | ||
51 | */ | ||
52 | extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, | ||
53 | unsigned int off, unsigned int cfg); | ||
54 | |||
55 | /** | ||
56 | * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A) | ||
57 | * @chip: The gpio chip that is being configured. | ||
58 | * @off: The offset for the GPIO being configured. | ||
59 | * @cfg: The configuration value to set. | ||
60 | * | ||
61 | * This helper deal with the GPIO cases where the control register | ||
62 | * has one bit of configuration for the gpio, where setting the bit | ||
63 | * means the pin is in special function mode and unset means output. | ||
64 | */ | ||
65 | extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip, | ||
66 | unsigned int off, unsigned int cfg); | ||
67 | |||
68 | /** | ||
69 | * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config. | ||
70 | * @chip: The gpio chip that is being configured. | ||
71 | * @off: The offset for the GPIO being configured. | ||
72 | * @cfg: The configuration value to set. | ||
73 | * | ||
74 | * This helper deal with the GPIO cases where the control register has 4 bits | ||
75 | * of control per GPIO, generally in the form of: | ||
76 | * 0000 = Input | ||
77 | * 0001 = Output | ||
78 | * others = Special functions (dependant on bank) | ||
79 | * | ||
80 | * Note, since the code to deal with the case where there are two control | ||
81 | * registers instead of one, we do not have a seperate set of functions for | ||
82 | * each case. | ||
83 | */ | ||
84 | extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, | ||
85 | unsigned int off, unsigned int cfg); | ||
86 | |||
87 | |||
88 | /* Pull-{up,down} resistor controls. | ||
89 | * | ||
90 | * S3C2410,S3C2440,S3C24A0 = Pull-UP, | ||
91 | * S3C2412,S3C2413 = Pull-Down | ||
92 | * S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef] | ||
93 | * S3C2443 = Pull-Both [not same as S3C6400] | ||
94 | */ | ||
95 | |||
96 | /** | ||
97 | * s3c_gpio_setpull_1up() - Pull configuration for choice of up or none. | ||
98 | * @chip: The gpio chip that is being configured. | ||
99 | * @off: The offset for the GPIO being configured. | ||
100 | * @param: pull: The pull mode being requested. | ||
101 | * | ||
102 | * This is a helper function for the case where we have GPIOs with one | ||
103 | * bit configuring the presence of a pull-up resistor. | ||
104 | */ | ||
105 | extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip, | ||
106 | unsigned int off, s3c_gpio_pull_t pull); | ||
107 | |||
108 | /** | ||
109 | * s3c_gpio_setpull_1down() - Pull configuration for choice of down or none | ||
110 | * @chip: The gpio chip that is being configured | ||
111 | * @off: The offset for the GPIO being configured | ||
112 | * @param: pull: The pull mode being requested | ||
113 | * | ||
114 | * This is a helper function for the case where we have GPIOs with one | ||
115 | * bit configuring the presence of a pull-down resistor. | ||
116 | */ | ||
117 | extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip, | ||
118 | unsigned int off, s3c_gpio_pull_t pull); | ||
119 | |||
120 | /** | ||
121 | * s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none | ||
122 | * @chip: The gpio chip that is being configured. | ||
123 | * @off: The offset for the GPIO being configured. | ||
124 | * @param: pull: The pull mode being requested. | ||
125 | * | ||
126 | * This is a helper function for the case where we have GPIOs with two | ||
127 | * bits configuring the presence of a pull resistor, in the following | ||
128 | * order: | ||
129 | * 00 = No pull resistor connected | ||
130 | * 01 = Pull-up resistor connected | ||
131 | * 10 = Pull-down resistor connected | ||
132 | */ | ||
133 | extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip, | ||
134 | unsigned int off, s3c_gpio_pull_t pull); | ||
135 | |||
136 | |||
137 | /** | ||
138 | * s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none | ||
139 | * @chip: The gpio chip that the GPIO pin belongs to | ||
140 | * @off: The offset to the pin to get the configuration of. | ||
141 | * | ||
142 | * This helper function reads the state of the pull-{up,down} resistor for the | ||
143 | * given GPIO in the same case as s3c_gpio_setpull_upown. | ||
144 | */ | ||
145 | extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip, | ||
146 | unsigned int off); | ||
147 | |||
148 | /** | ||
149 | * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443. | ||
150 | * @chip: The gpio chip that is being configured. | ||
151 | * @off: The offset for the GPIO being configured. | ||
152 | * @param: pull: The pull mode being requested. | ||
153 | * | ||
154 | * This is a helper function for the case where we have GPIOs with two | ||
155 | * bits configuring the presence of a pull resistor, in the following | ||
156 | * order: | ||
157 | * 00 = Pull-up resistor connected | ||
158 | * 10 = Pull-down resistor connected | ||
159 | * x1 = No pull up resistor | ||
160 | */ | ||
161 | extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip, | ||
162 | unsigned int off, s3c_gpio_pull_t pull); | ||
163 | |||
164 | /** | ||
165 | * s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors | ||
166 | * @chip: The gpio chip that the GPIO pin belongs to. | ||
167 | * @off: The offset to the pin to get the configuration of. | ||
168 | * | ||
169 | * This helper function reads the state of the pull-{up,down} resistor for the | ||
170 | * given GPIO in the same case as s3c_gpio_setpull_upown. | ||
171 | */ | ||
172 | extern s3c_gpio_pull_t s3c_gpio_getpull_s3c24xx(struct s3c_gpio_chip *chip, | ||
173 | unsigned int off); | ||
174 | |||
175 | #endif /* __PLAT_GPIO_CFG_HELPERS_H */ | ||
176 | |||
diff --git a/arch/arm/plat-s3c/include/plat/gpio-cfg.h b/arch/arm/plat-s3c/include/plat/gpio-cfg.h new file mode 100644 index 000000000000..29cd6a86cade --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/gpio-cfg.h | |||
@@ -0,0 +1,110 @@ | |||
1 | /* linux/arch/arm/plat-s3c/include/plat/gpio-cfg.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * | ||
8 | * S3C Platform - GPIO pin configuration | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | /* This file contains the necessary definitions to get the basic gpio | ||
16 | * pin configuration done such as setting a pin to input or output or | ||
17 | * changing the pull-{up,down} configurations. | ||
18 | */ | ||
19 | |||
20 | /* Note, this interface is being added to the s3c64xx arch first and will | ||
21 | * be added to the s3c24xx systems later. | ||
22 | */ | ||
23 | |||
24 | #ifndef __PLAT_GPIO_CFG_H | ||
25 | #define __PLAT_GPIO_CFG_H __FILE__ | ||
26 | |||
27 | typedef unsigned int __bitwise__ s3c_gpio_pull_t; | ||
28 | |||
29 | /* forward declaration if gpio-core.h hasn't been included */ | ||
30 | struct s3c_gpio_chip; | ||
31 | |||
32 | /** | ||
33 | * struct s3c_gpio_cfg GPIO configuration | ||
34 | * @cfg_eint: Configuration setting when used for external interrupt source | ||
35 | * @get_pull: Read the current pull configuration for the GPIO | ||
36 | * @set_pull: Set the current pull configuraiton for the GPIO | ||
37 | * @set_config: Set the current configuration for the GPIO | ||
38 | * @get_config: Read the current configuration for the GPIO | ||
39 | * | ||
40 | * Each chip can have more than one type of GPIO bank available and some | ||
41 | * have different capabilites even when they have the same control register | ||
42 | * layouts. Provide an point to vector control routine and provide any | ||
43 | * per-bank configuration information that other systems such as the | ||
44 | * external interrupt code will need. | ||
45 | */ | ||
46 | struct s3c_gpio_cfg { | ||
47 | unsigned int cfg_eint; | ||
48 | |||
49 | s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs); | ||
50 | int (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs, | ||
51 | s3c_gpio_pull_t pull); | ||
52 | |||
53 | unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs); | ||
54 | int (*set_config)(struct s3c_gpio_chip *chip, unsigned offs, | ||
55 | unsigned config); | ||
56 | }; | ||
57 | |||
58 | #define S3C_GPIO_SPECIAL_MARK (0xfffffff0) | ||
59 | #define S3C_GPIO_SPECIAL(x) (S3C_GPIO_SPECIAL_MARK | (x)) | ||
60 | |||
61 | /* Defines for generic pin configurations */ | ||
62 | #define S3C_GPIO_INPUT (S3C_GPIO_SPECIAL(0)) | ||
63 | #define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1)) | ||
64 | #define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x)) | ||
65 | |||
66 | #define s3c_gpio_is_cfg_special(_cfg) \ | ||
67 | (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK) | ||
68 | |||
69 | /** | ||
70 | * s3c_gpio_cfgpin() - Change the GPIO function of a pin. | ||
71 | * @pin pin The pin number to configure. | ||
72 | * @pin to The configuration for the pin's function. | ||
73 | * | ||
74 | * Configure which function is actually connected to the external | ||
75 | * pin, such as an gpio input, output or some form of special function | ||
76 | * connected to an internal peripheral block. | ||
77 | */ | ||
78 | extern int s3c_gpio_cfgpin(unsigned int pin, unsigned int to); | ||
79 | |||
80 | /* Define values for the pull-{up,down} available for each gpio pin. | ||
81 | * | ||
82 | * These values control the state of the weak pull-{up,down} resistors | ||
83 | * available on most pins on the S3C series. Not all chips support both | ||
84 | * up or down settings, and it may be dependant on the chip that is being | ||
85 | * used to whether the particular mode is available. | ||
86 | */ | ||
87 | #define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00) | ||
88 | #define S3C_GPIO_PULL_DOWN ((__force s3c_gpio_pull_t)0x01) | ||
89 | #define S3C_GPIO_PULL_UP ((__force s3c_gpio_pull_t)0x02) | ||
90 | |||
91 | /** | ||
92 | * s3c_gpio_setpull() - set the state of a gpio pin pull resistor | ||
93 | * @pin: The pin number to configure the pull resistor. | ||
94 | * @pull: The configuration for the pull resistor. | ||
95 | * | ||
96 | * This function sets the state of the pull-{up,down} resistor for the | ||
97 | * specified pin. It will return 0 if successfull, or a negative error | ||
98 | * code if the pin cannot support the requested pull setting. | ||
99 | */ | ||
100 | extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull); | ||
101 | |||
102 | /** | ||
103 | * s3c_gpio_getpull() - get the pull resistor state of a gpio pin | ||
104 | * @pin: The pin number to get the settings for | ||
105 | * | ||
106 | * Read the pull resistor value for the specified pin. | ||
107 | */ | ||
108 | extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin); | ||
109 | |||
110 | #endif /* __PLAT_GPIO_CFG_H */ | ||
diff --git a/arch/arm/plat-s3c/include/plat/gpio-core.h b/arch/arm/plat-s3c/include/plat/gpio-core.h new file mode 100644 index 000000000000..2fc60a580ac8 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/gpio-core.h | |||
@@ -0,0 +1,77 @@ | |||
1 | /* linux/arch/arm/plat-s3c/include/plat/gpio-core.h | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C Platform - GPIO core | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | /* Define the core gpiolib support functions that the s3c platforms may | ||
15 | * need to extend or change depending on the hardware and the s3c chip | ||
16 | * selected at build or found at run time. | ||
17 | * | ||
18 | * These definitions are not intended for driver inclusion, there is | ||
19 | * nothing here that should not live outside the platform and core | ||
20 | * specific code. | ||
21 | */ | ||
22 | |||
23 | struct s3c_gpio_cfg; | ||
24 | |||
25 | /** | ||
26 | * struct s3c_gpio_chip - wrapper for specific implementation of gpio | ||
27 | * @chip: The chip structure to be exported via gpiolib. | ||
28 | * @base: The base pointer to the gpio configuration registers. | ||
29 | * @config: special function and pull-resistor control information. | ||
30 | * | ||
31 | * This wrapper provides the necessary information for the Samsung | ||
32 | * specific gpios being registered with gpiolib. | ||
33 | */ | ||
34 | struct s3c_gpio_chip { | ||
35 | struct gpio_chip chip; | ||
36 | struct s3c_gpio_cfg *config; | ||
37 | void __iomem *base; | ||
38 | }; | ||
39 | |||
40 | static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc) | ||
41 | { | ||
42 | return container_of(gpc, struct s3c_gpio_chip, chip); | ||
43 | } | ||
44 | |||
45 | /** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip. | ||
46 | * @chip: The chip to register | ||
47 | * | ||
48 | * This is a wrapper to gpiochip_add() that takes our specific gpio chip | ||
49 | * information and makes the necessary alterations for the platform and | ||
50 | * notes the information for use with the configuration systems and any | ||
51 | * other parts of the system. | ||
52 | */ | ||
53 | extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip); | ||
54 | |||
55 | /* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios | ||
56 | * for use with the configuration calls, and other parts of the s3c gpiolib | ||
57 | * support code. | ||
58 | * | ||
59 | * Not all s3c support code will need this, as some configurations of cpu | ||
60 | * may only support one or two different configuration options and have an | ||
61 | * easy gpio to s3c_gpio_chip mapping function. If this is the case, then | ||
62 | * the machine support file should provide its own s3c_gpiolib_getchip() | ||
63 | * and any other necessary functions. | ||
64 | */ | ||
65 | |||
66 | #ifdef CONFIG_S3C_GPIO_TRACK | ||
67 | extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; | ||
68 | |||
69 | static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip) | ||
70 | { | ||
71 | return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL; | ||
72 | } | ||
73 | #else | ||
74 | /* machine specific code should provide s3c_gpiolib_getchip */ | ||
75 | |||
76 | static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { } | ||
77 | #endif | ||
diff --git a/arch/arm/plat-s3c/include/plat/iic-core.h b/arch/arm/plat-s3c/include/plat/iic-core.h new file mode 100644 index 000000000000..36397ca20962 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/iic-core.h | |||
@@ -0,0 +1,35 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/iic-core.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C - I2C Controller core functions | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ASM_ARCH_IIC_CORE_H | ||
15 | #define __ASM_ARCH_IIC_CORE_H __FILE__ | ||
16 | |||
17 | /* These functions are only for use with the core support code, such as | ||
18 | * the cpu specific initialisation code | ||
19 | */ | ||
20 | |||
21 | /* re-define device name depending on support. */ | ||
22 | static inline void s3c_i2c0_setname(char *name) | ||
23 | { | ||
24 | /* currently this device is always compiled in */ | ||
25 | s3c_device_i2c0.name = name; | ||
26 | } | ||
27 | |||
28 | static inline void s3c_i2c1_setname(char *name) | ||
29 | { | ||
30 | #ifdef CONFIG_S3C_DEV_I2C1 | ||
31 | s3c_device_i2c1.name = name; | ||
32 | #endif | ||
33 | } | ||
34 | |||
35 | #endif /* __ASM_ARCH_IIC_H */ | ||
diff --git a/arch/arm/plat-s3c/include/plat/iic.h b/arch/arm/plat-s3c/include/plat/iic.h index 5106acaa1d0e..dc1dfcb9bc6c 100644 --- a/arch/arm/plat-s3c/include/plat/iic.h +++ b/arch/arm/plat-s3c/include/plat/iic.h | |||
@@ -28,6 +28,30 @@ struct s3c2410_platform_i2c { | |||
28 | unsigned long max_freq; /* max frequency for the bus */ | 28 | unsigned long max_freq; /* max frequency for the bus */ |
29 | unsigned long min_freq; /* min frequency for the bus */ | 29 | unsigned long min_freq; /* min frequency for the bus */ |
30 | unsigned int sda_delay; /* pclks (s3c2440 only) */ | 30 | unsigned int sda_delay; /* pclks (s3c2440 only) */ |
31 | |||
32 | void (*cfg_gpio)(struct platform_device *dev); | ||
31 | }; | 33 | }; |
32 | 34 | ||
35 | /** | ||
36 | * s3c_i2c0_set_platdata - set platform data for i2c0 device | ||
37 | * @i2c: The platform data to set, or NULL for default data. | ||
38 | * | ||
39 | * Register the given platform data for use with the i2c0 device. This | ||
40 | * call copies the platform data, so the caller can use __initdata for | ||
41 | * their copy. | ||
42 | * | ||
43 | * This call will set cfg_gpio if is null to the default platform | ||
44 | * implementation. | ||
45 | * | ||
46 | * Any user of s3c_device_i2c0 should call this, even if it is with | ||
47 | * NULL to ensure that the device is given the default platform data | ||
48 | * as the driver will no longer carry defaults. | ||
49 | */ | ||
50 | extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c); | ||
51 | extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c); | ||
52 | |||
53 | /* defined by architecture to configure gpio */ | ||
54 | extern void s3c_i2c0_cfg_gpio(struct platform_device *dev); | ||
55 | extern void s3c_i2c1_cfg_gpio(struct platform_device *dev); | ||
56 | |||
33 | #endif /* __ASM_ARCH_IIC_H */ | 57 | #endif /* __ASM_ARCH_IIC_H */ |
diff --git a/arch/arm/plat-s3c/include/plat/map.h b/arch/arm/plat-s3c/include/plat/map-base.h index b84289d32a54..b84289d32a54 100644 --- a/arch/arm/plat-s3c/include/plat/map.h +++ b/arch/arm/plat-s3c/include/plat/map-base.h | |||
diff --git a/arch/arm/plat-s3c/include/plat/regs-fb.h b/arch/arm/plat-s3c/include/plat/regs-fb.h new file mode 100644 index 000000000000..e9ee599d430e --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/regs-fb.h | |||
@@ -0,0 +1,366 @@ | |||
1 | /* arch/arm/plat-s3c/include/plat/regs-fb.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * | ||
8 | * S3C Platform - new-style framebuffer register definitions | ||
9 | * | ||
10 | * This is the register set for the new style framebuffer interface | ||
11 | * found from the S3C2443 onwards into the S3C2416, S3C2450 and the | ||
12 | * S3C64XX series such as the S3C6400 and S3C6410. | ||
13 | * | ||
14 | * The file does not contain the cpu specific items which are based on | ||
15 | * whichever architecture is selected, it only contains the core of the | ||
16 | * register set. See <mach/regs-fb.h> to get the specifics. | ||
17 | * | ||
18 | * Note, we changed to using regs-fb.h as it avoids any clashes with | ||
19 | * the original regs-lcd.h so out of the way of regs-lcd.h as well as | ||
20 | * indicating the newer block is much more than just an LCD interface. | ||
21 | * | ||
22 | * This program is free software; you can redistribute it and/or modify | ||
23 | * it under the terms of the GNU General Public License version 2 as | ||
24 | * published by the Free Software Foundation. | ||
25 | */ | ||
26 | |||
27 | /* Please do not include this file directly, use <mach/regs-fb.h> to | ||
28 | * ensure all the localised SoC support is included as necessary. | ||
29 | */ | ||
30 | |||
31 | /* VIDCON0 */ | ||
32 | |||
33 | #define VIDCON0 (0x00) | ||
34 | #define VIDCON0_INTERLACE (1 << 29) | ||
35 | #define VIDCON0_VIDOUT_MASK (0x3 << 26) | ||
36 | #define VIDCON0_VIDOUT_SHIFT (26) | ||
37 | #define VIDCON0_VIDOUT_RGB (0x0 << 26) | ||
38 | #define VIDCON0_VIDOUT_TV (0x1 << 26) | ||
39 | #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26) | ||
40 | #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26) | ||
41 | |||
42 | #define VIDCON0_L1_DATA_MASK (0x7 << 23) | ||
43 | #define VIDCON0_L1_DATA_SHIFT (23) | ||
44 | #define VIDCON0_L1_DATA_16BPP (0x0 << 23) | ||
45 | #define VIDCON0_L1_DATA_18BPP16 (0x1 << 23) | ||
46 | #define VIDCON0_L1_DATA_18BPP9 (0x2 << 23) | ||
47 | #define VIDCON0_L1_DATA_24BPP (0x3 << 23) | ||
48 | #define VIDCON0_L1_DATA_18BPP (0x4 << 23) | ||
49 | #define VIDCON0_L1_DATA_16BPP8 (0x5 << 23) | ||
50 | |||
51 | #define VIDCON0_L0_DATA_MASK (0x7 << 20) | ||
52 | #define VIDCON0_L0_DATA_SHIFT (20) | ||
53 | #define VIDCON0_L0_DATA_16BPP (0x0 << 20) | ||
54 | #define VIDCON0_L0_DATA_18BPP16 (0x1 << 20) | ||
55 | #define VIDCON0_L0_DATA_18BPP9 (0x2 << 20) | ||
56 | #define VIDCON0_L0_DATA_24BPP (0x3 << 20) | ||
57 | #define VIDCON0_L0_DATA_18BPP (0x4 << 20) | ||
58 | #define VIDCON0_L0_DATA_16BPP8 (0x5 << 20) | ||
59 | |||
60 | #define VIDCON0_PNRMODE_MASK (0x3 << 17) | ||
61 | #define VIDCON0_PNRMODE_SHIFT (17) | ||
62 | #define VIDCON0_PNRMODE_RGB (0x0 << 17) | ||
63 | #define VIDCON0_PNRMODE_BGR (0x1 << 17) | ||
64 | #define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17) | ||
65 | #define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17) | ||
66 | |||
67 | #define VIDCON0_CLKVALUP (1 << 16) | ||
68 | #define VIDCON0_CLKVAL_F_MASK (0xff << 6) | ||
69 | #define VIDCON0_CLKVAL_F_SHIFT (6) | ||
70 | #define VIDCON0_CLKVAL_F_LIMIT (0xff) | ||
71 | #define VIDCON0_CLKVAL_F(_x) ((_x) << 6) | ||
72 | #define VIDCON0_VLCKFREE (1 << 5) | ||
73 | #define VIDCON0_CLKDIR (1 << 4) | ||
74 | |||
75 | #define VIDCON0_CLKSEL_MASK (0x3 << 2) | ||
76 | #define VIDCON0_CLKSEL_SHIFT (2) | ||
77 | #define VIDCON0_CLKSEL_HCLK (0x0 << 2) | ||
78 | #define VIDCON0_CLKSEL_LCD (0x1 << 2) | ||
79 | #define VIDCON0_CLKSEL_27M (0x3 << 2) | ||
80 | |||
81 | #define VIDCON0_ENVID (1 << 1) | ||
82 | #define VIDCON0_ENVID_F (1 << 0) | ||
83 | |||
84 | #define VIDCON1 (0x04) | ||
85 | #define VIDCON1_LINECNT_MASK (0x7ff << 16) | ||
86 | #define VIDCON1_LINECNT_SHIFT (16) | ||
87 | #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff) | ||
88 | #define VIDCON1_VSTATUS_MASK (0x3 << 13) | ||
89 | #define VIDCON1_VSTATUS_SHIFT (13) | ||
90 | #define VIDCON1_VSTATUS_VSYNC (0x0 << 13) | ||
91 | #define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13) | ||
92 | #define VIDCON1_VSTATUS_ACTIVE (0x2 << 13) | ||
93 | #define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13) | ||
94 | |||
95 | #define VIDCON1_INV_VCLK (1 << 7) | ||
96 | #define VIDCON1_INV_HSYNC (1 << 6) | ||
97 | #define VIDCON1_INV_VSYNC (1 << 5) | ||
98 | #define VIDCON1_INV_VDEN (1 << 4) | ||
99 | |||
100 | /* VIDCON2 */ | ||
101 | |||
102 | #define VIDCON2 (0x08) | ||
103 | #define VIDCON2_EN601 (1 << 23) | ||
104 | #define VIDCON2_TVFMTSEL_SW (1 << 14) | ||
105 | |||
106 | #define VIDCON2_TVFMTSEL1_MASK (0x3 << 12) | ||
107 | #define VIDCON2_TVFMTSEL1_SHIFT (12) | ||
108 | #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12) | ||
109 | #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12) | ||
110 | #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12) | ||
111 | |||
112 | #define VIDCON2_ORGYCbCr (1 << 8) | ||
113 | #define VIDCON2_YUVORDCrCb (1 << 7) | ||
114 | |||
115 | /* VIDTCON0 */ | ||
116 | |||
117 | #define VIDTCON0_VBPDE_MASK (0xff << 24) | ||
118 | #define VIDTCON0_VBPDE_SHIFT (24) | ||
119 | #define VIDTCON0_VBPDE_LIMIT (0xff) | ||
120 | #define VIDTCON0_VBPDE(_x) ((_x) << 24) | ||
121 | |||
122 | #define VIDTCON0_VBPD_MASK (0xff << 16) | ||
123 | #define VIDTCON0_VBPD_SHIFT (16) | ||
124 | #define VIDTCON0_VBPD_LIMIT (0xff) | ||
125 | #define VIDTCON0_VBPD(_x) ((_x) << 16) | ||
126 | |||
127 | #define VIDTCON0_VFPD_MASK (0xff << 8) | ||
128 | #define VIDTCON0_VFPD_SHIFT (8) | ||
129 | #define VIDTCON0_VFPD_LIMIT (0xff) | ||
130 | #define VIDTCON0_VFPD(_x) ((_x) << 8) | ||
131 | |||
132 | #define VIDTCON0_VSPW_MASK (0xff << 0) | ||
133 | #define VIDTCON0_VSPW_SHIFT (0) | ||
134 | #define VIDTCON0_VSPW_LIMIT (0xff) | ||
135 | #define VIDTCON0_VSPW(_x) ((_x) << 0) | ||
136 | |||
137 | /* VIDTCON1 */ | ||
138 | |||
139 | #define VIDTCON1_VFPDE_MASK (0xff << 24) | ||
140 | #define VIDTCON1_VFPDE_SHIFT (24) | ||
141 | #define VIDTCON1_VFPDE_LIMIT (0xff) | ||
142 | #define VIDTCON1_VFPDE(_x) ((_x) << 24) | ||
143 | |||
144 | #define VIDTCON1_HBPD_MASK (0xff << 16) | ||
145 | #define VIDTCON1_HBPD_SHIFT (16) | ||
146 | #define VIDTCON1_HBPD_LIMIT (0xff) | ||
147 | #define VIDTCON1_HBPD(_x) ((_x) << 16) | ||
148 | |||
149 | #define VIDTCON1_HFPD_MASK (0xff << 8) | ||
150 | #define VIDTCON1_HFPD_SHIFT (8) | ||
151 | #define VIDTCON1_HFPD_LIMIT (0xff) | ||
152 | #define VIDTCON1_HFPD(_x) ((_x) << 8) | ||
153 | |||
154 | #define VIDTCON1_HSPW_MASK (0xff << 0) | ||
155 | #define VIDTCON1_HSPW_SHIFT (0) | ||
156 | #define VIDTCON1_HSPW_LIMIT (0xff) | ||
157 | #define VIDTCON1_HSPW(_x) ((_x) << 0) | ||
158 | |||
159 | #define VIDTCON2 (0x18) | ||
160 | #define VIDTCON2_LINEVAL_MASK (0x7ff << 11) | ||
161 | #define VIDTCON2_LINEVAL_SHIFT (11) | ||
162 | #define VIDTCON2_LINEVAL_LIMIT (0x7ff) | ||
163 | #define VIDTCON2_LINEVAL(_x) ((_x) << 11) | ||
164 | |||
165 | #define VIDTCON2_HOZVAL_MASK (0x7ff << 0) | ||
166 | #define VIDTCON2_HOZVAL_SHIFT (0) | ||
167 | #define VIDTCON2_HOZVAL_LIMIT (0x7ff) | ||
168 | #define VIDTCON2_HOZVAL(_x) ((_x) << 0) | ||
169 | |||
170 | /* WINCONx */ | ||
171 | |||
172 | |||
173 | #define WINCONx_BITSWP (1 << 18) | ||
174 | #define WINCONx_BYTSWP (1 << 17) | ||
175 | #define WINCONx_HAWSWP (1 << 16) | ||
176 | #define WINCONx_BURSTLEN_MASK (0x3 << 9) | ||
177 | #define WINCONx_BURSTLEN_SHIFT (9) | ||
178 | #define WINCONx_BURSTLEN_16WORD (0x0 << 9) | ||
179 | #define WINCONx_BURSTLEN_8WORD (0x1 << 9) | ||
180 | #define WINCONx_BURSTLEN_4WORD (0x2 << 9) | ||
181 | |||
182 | #define WINCONx_ENWIN (1 << 0) | ||
183 | #define WINCON0_BPPMODE_MASK (0xf << 2) | ||
184 | #define WINCON0_BPPMODE_SHIFT (2) | ||
185 | #define WINCON0_BPPMODE_1BPP (0x0 << 2) | ||
186 | #define WINCON0_BPPMODE_2BPP (0x1 << 2) | ||
187 | #define WINCON0_BPPMODE_4BPP (0x2 << 2) | ||
188 | #define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2) | ||
189 | #define WINCON0_BPPMODE_16BPP_565 (0x5 << 2) | ||
190 | #define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2) | ||
191 | #define WINCON0_BPPMODE_18BPP_666 (0x8 << 2) | ||
192 | #define WINCON0_BPPMODE_24BPP_888 (0xb << 2) | ||
193 | |||
194 | #define WINCON1_BLD_PIX (1 << 6) | ||
195 | |||
196 | #define WINCON1_ALPHA_SEL (1 << 1) | ||
197 | #define WINCON1_BPPMODE_MASK (0xf << 2) | ||
198 | #define WINCON1_BPPMODE_SHIFT (2) | ||
199 | #define WINCON1_BPPMODE_1BPP (0x0 << 2) | ||
200 | #define WINCON1_BPPMODE_2BPP (0x1 << 2) | ||
201 | #define WINCON1_BPPMODE_4BPP (0x2 << 2) | ||
202 | #define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2) | ||
203 | #define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2) | ||
204 | #define WINCON1_BPPMODE_16BPP_565 (0x5 << 2) | ||
205 | #define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2) | ||
206 | #define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2) | ||
207 | #define WINCON1_BPPMODE_18BPP_666 (0x8 << 2) | ||
208 | #define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2) | ||
209 | #define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2) | ||
210 | #define WINCON1_BPPMODE_24BPP_888 (0xb << 2) | ||
211 | #define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2) | ||
212 | #define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2) | ||
213 | #define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2) | ||
214 | |||
215 | |||
216 | #define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11) | ||
217 | #define VIDOSDxA_TOPLEFT_X_SHIFT (11) | ||
218 | #define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff) | ||
219 | #define VIDOSDxA_TOPLEFT_X(_x) ((_x) << 11) | ||
220 | |||
221 | #define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0) | ||
222 | #define VIDOSDxA_TOPLEFT_Y_SHIFT (0) | ||
223 | #define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff) | ||
224 | #define VIDOSDxA_TOPLEFT_Y(_x) ((_x) << 0) | ||
225 | |||
226 | #define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11) | ||
227 | #define VIDOSDxB_BOTRIGHT_X_SHIFT (11) | ||
228 | #define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff) | ||
229 | #define VIDOSDxB_BOTRIGHT_X(_x) ((_x) << 11) | ||
230 | |||
231 | #define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0) | ||
232 | #define VIDOSDxB_BOTRIGHT_Y_SHIFT (0) | ||
233 | #define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff) | ||
234 | #define VIDOSDxB_BOTRIGHT_Y(_x) ((_x) << 0) | ||
235 | |||
236 | /* For VIDOSD[1..4]C */ | ||
237 | #define VIDISD14C_ALPHA0_R(_x) ((_x) << 20) | ||
238 | #define VIDISD14C_ALPHA0_G_MASK (0xf << 16) | ||
239 | #define VIDISD14C_ALPHA0_G_SHIFT (16) | ||
240 | #define VIDISD14C_ALPHA0_G_LIMIT (0xf) | ||
241 | #define VIDISD14C_ALPHA0_G(_x) ((_x) << 16) | ||
242 | #define VIDISD14C_ALPHA0_B_MASK (0xf << 12) | ||
243 | #define VIDISD14C_ALPHA0_B_SHIFT (12) | ||
244 | #define VIDISD14C_ALPHA0_B_LIMIT (0xf) | ||
245 | #define VIDISD14C_ALPHA0_B(_x) ((_x) << 12) | ||
246 | #define VIDISD14C_ALPHA1_R_MASK (0xf << 8) | ||
247 | #define VIDISD14C_ALPHA1_R_SHIFT (8) | ||
248 | #define VIDISD14C_ALPHA1_R_LIMIT (0xf) | ||
249 | #define VIDISD14C_ALPHA1_R(_x) ((_x) << 8) | ||
250 | #define VIDISD14C_ALPHA1_G_MASK (0xf << 4) | ||
251 | #define VIDISD14C_ALPHA1_G_SHIFT (4) | ||
252 | #define VIDISD14C_ALPHA1_G_LIMIT (0xf) | ||
253 | #define VIDISD14C_ALPHA1_G(_x) ((_x) << 4) | ||
254 | #define VIDISD14C_ALPHA1_B_MASK (0xf << 0) | ||
255 | #define VIDISD14C_ALPHA1_B_SHIFT (0) | ||
256 | #define VIDISD14C_ALPHA1_B_LIMIT (0xf) | ||
257 | #define VIDISD14C_ALPHA1_B(_x) ((_x) << 0) | ||
258 | |||
259 | /* Video buffer addresses */ | ||
260 | #define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8)) | ||
261 | #define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8)) | ||
262 | #define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8)) | ||
263 | #define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8)) | ||
264 | #define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4)) | ||
265 | |||
266 | #define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13) | ||
267 | #define VIDW_BUF_SIZE_OFFSET_SHIFT (13) | ||
268 | #define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff) | ||
269 | #define VIDW_BUF_SIZE_OFFSET(_x) ((_x) << 13) | ||
270 | |||
271 | #define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0) | ||
272 | #define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0) | ||
273 | #define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff) | ||
274 | #define VIDW_BUF_SIZE_PAGEWIDTH(_x) ((_x) << 0) | ||
275 | |||
276 | /* Interrupt controls and status */ | ||
277 | |||
278 | #define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20) | ||
279 | #define VIDINTCON0_FIFOINTERVAL_SHIFT (20) | ||
280 | #define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f) | ||
281 | #define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20) | ||
282 | |||
283 | #define VIDINTCON0_INT_SYSMAINCON (1 << 19) | ||
284 | #define VIDINTCON0_INT_SYSSUBCON (1 << 18) | ||
285 | #define VIDINTCON0_INT_I80IFDONE (1 << 17) | ||
286 | |||
287 | #define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15) | ||
288 | #define VIDINTCON0_FRAMESEL0_SHIFT (15) | ||
289 | #define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15) | ||
290 | #define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15) | ||
291 | #define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15) | ||
292 | #define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15) | ||
293 | |||
294 | #define VIDINTCON0_FRAMESEL1 (1 << 14) | ||
295 | #define VIDINTCON0_FRAMESEL1_NONE (0x0 << 14) | ||
296 | #define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 14) | ||
297 | #define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 14) | ||
298 | #define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 14) | ||
299 | |||
300 | #define VIDINTCON0_INT_FRAME (1 << 12) | ||
301 | #define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5) | ||
302 | #define VIDINTCON0_FIFIOSEL_SHIFT (5) | ||
303 | #define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5) | ||
304 | #define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5) | ||
305 | |||
306 | #define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2) | ||
307 | #define VIDINTCON0_FIFOLEVEL_SHIFT (2) | ||
308 | #define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2) | ||
309 | #define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2) | ||
310 | #define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2) | ||
311 | #define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2) | ||
312 | #define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2) | ||
313 | |||
314 | #define VIDINTCON0_INT_FIFO_MASK (0x3 << 0) | ||
315 | #define VIDINTCON0_INT_FIFO_SHIFT (0) | ||
316 | #define VIDINTCON0_INT_ENABLE (1 << 0) | ||
317 | |||
318 | #define VIDINTCON1 (0x134) | ||
319 | #define VIDINTCON1_INT_I180 (1 << 2) | ||
320 | #define VIDINTCON1_INT_FRAME (1 << 1) | ||
321 | #define VIDINTCON1_INT_FIFO (1 << 0) | ||
322 | |||
323 | /* Window colour-key control registers */ | ||
324 | |||
325 | #define WxKEYCON0_KEYBL_EN (1 << 26) | ||
326 | #define WxKEYCON0_KEYEN_F (1 << 25) | ||
327 | #define WxKEYCON0_DIRCON (1 << 24) | ||
328 | #define WxKEYCON0_COMPKEY_MASK (0xffffff << 0) | ||
329 | #define WxKEYCON0_COMPKEY_SHIFT (0) | ||
330 | #define WxKEYCON0_COMPKEY_LIMIT (0xffffff) | ||
331 | #define WxKEYCON0_COMPKEY(_x) ((_x) << 0) | ||
332 | #define WxKEYCON1_COLVAL_MASK (0xffffff << 0) | ||
333 | #define WxKEYCON1_COLVAL_SHIFT (0) | ||
334 | #define WxKEYCON1_COLVAL_LIMIT (0xffffff) | ||
335 | #define WxKEYCON1_COLVAL(_x) ((_x) << 0) | ||
336 | |||
337 | |||
338 | /* Window blanking (MAP) */ | ||
339 | |||
340 | #define WINxMAP_MAP (1 << 24) | ||
341 | #define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0) | ||
342 | #define WINxMAP_MAP_COLOUR_SHIFT (0) | ||
343 | #define WINxMAP_MAP_COLOUR_LIMIT (0xffffff) | ||
344 | #define WINxMAP_MAP_COLOUR(_x) ((_x) << 0) | ||
345 | |||
346 | #define WPALCON_PAL_UPDATE (1 << 9) | ||
347 | #define WPALCON_W1PAL_MASK (0x7 << 3) | ||
348 | #define WPALCON_W1PAL_SHIFT (3) | ||
349 | #define WPALCON_W1PAL_25BPP_A888 (0x0 << 3) | ||
350 | #define WPALCON_W1PAL_24BPP (0x1 << 3) | ||
351 | #define WPALCON_W1PAL_19BPP_A666 (0x2 << 3) | ||
352 | #define WPALCON_W1PAL_18BPP_A665 (0x3 << 3) | ||
353 | #define WPALCON_W1PAL_18BPP (0x4 << 3) | ||
354 | #define WPALCON_W1PAL_16BPP_A555 (0x5 << 3) | ||
355 | #define WPALCON_W1PAL_16BPP_565 (0x6 << 3) | ||
356 | |||
357 | #define WPALCON_W0PAL_MASK (0x7 << 0) | ||
358 | #define WPALCON_W0PAL_SHIFT (0) | ||
359 | #define WPALCON_W0PAL_25BPP_A888 (0x0 << 0) | ||
360 | #define WPALCON_W0PAL_24BPP (0x1 << 0) | ||
361 | #define WPALCON_W0PAL_19BPP_A666 (0x2 << 0) | ||
362 | #define WPALCON_W0PAL_18BPP_A665 (0x3 << 0) | ||
363 | #define WPALCON_W0PAL_18BPP (0x4 << 0) | ||
364 | #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0) | ||
365 | #define WPALCON_W0PAL_16BPP_565 (0x6 << 0) | ||
366 | |||
diff --git a/arch/arm/plat-s3c/include/plat/regs-irqtype.h b/arch/arm/plat-s3c/include/plat/regs-irqtype.h new file mode 100644 index 000000000000..c63cd3fc5ad3 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/regs-irqtype.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* arch/arm/plat-s3c/include/plat/regs-irqtype.h | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * S3C - IRQ detection types. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | /* values for S3C2410_EXTINT0/1/2 and other cpus in the series, including | ||
15 | * the S3C64XX | ||
16 | */ | ||
17 | #define S3C2410_EXTINT_LOWLEV (0x00) | ||
18 | #define S3C2410_EXTINT_HILEV (0x01) | ||
19 | #define S3C2410_EXTINT_FALLEDGE (0x02) | ||
20 | #define S3C2410_EXTINT_RISEEDGE (0x04) | ||
21 | #define S3C2410_EXTINT_BOTHEDGE (0x06) | ||
diff --git a/arch/arm/plat-s3c/include/plat/regs-sdhci.h b/arch/arm/plat-s3c/include/plat/regs-sdhci.h new file mode 100644 index 000000000000..e34049ad44cc --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/regs-sdhci.h | |||
@@ -0,0 +1,87 @@ | |||
1 | /* linux/arch/arm/plat-s3c/include/plat/regs-sdhci.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * | ||
8 | * S3C Platform - SDHCI (HSMMC) register definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __PLAT_S3C_SDHCI_REGS_H | ||
16 | #define __PLAT_S3C_SDHCI_REGS_H __FILE__ | ||
17 | |||
18 | #define S3C_SDHCI_CONTROL2 (0x80) | ||
19 | #define S3C_SDHCI_CONTROL3 (0x84) | ||
20 | #define S3C64XX_SDHCI_CONTROL4 (0x8C) | ||
21 | |||
22 | #define S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR (1 << 31) | ||
23 | #define S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK (1 << 30) | ||
24 | #define S3C_SDHCI_CTRL2_CDINVRXD3 (1 << 29) | ||
25 | #define S3C_SDHCI_CTRL2_SLCARDOUT (1 << 28) | ||
26 | |||
27 | #define S3C_SDHCI_CTRL2_FLTCLKSEL_MASK (0xf << 24) | ||
28 | #define S3C_SDHCI_CTRL2_FLTCLKSEL_SHIFT (24) | ||
29 | #define S3C_SDHCI_CTRL2_FLTCLKSEL(_x) ((_x) << 24) | ||
30 | |||
31 | #define S3C_SDHCI_CTRL2_LVLDAT_MASK (0xff << 16) | ||
32 | #define S3C_SDHCI_CTRL2_LVLDAT_SHIFT (16) | ||
33 | #define S3C_SDHCI_CTRL2_LVLDAT(_x) ((_x) << 16) | ||
34 | |||
35 | #define S3C_SDHCI_CTRL2_ENFBCLKTX (1 << 15) | ||
36 | #define S3C_SDHCI_CTRL2_ENFBCLKRX (1 << 14) | ||
37 | #define S3C_SDHCI_CTRL2_SDCDSEL (1 << 13) | ||
38 | #define S3C_SDHCI_CTRL2_SDSIGPC (1 << 12) | ||
39 | #define S3C_SDHCI_CTRL2_ENBUSYCHKTXSTART (1 << 11) | ||
40 | |||
41 | #define S3C_SDHCI_CTRL2_DFCNT_MASK (0x3 << 9) | ||
42 | #define S3C_SDHCI_CTRL2_DFCNT_SHIFT (9) | ||
43 | #define S3C_SDHCI_CTRL2_DFCNT_NONE (0x0 << 9) | ||
44 | #define S3C_SDHCI_CTRL2_DFCNT_4SDCLK (0x1 << 9) | ||
45 | #define S3C_SDHCI_CTRL2_DFCNT_16SDCLK (0x2 << 9) | ||
46 | #define S3C_SDHCI_CTRL2_DFCNT_64SDCLK (0x3 << 9) | ||
47 | |||
48 | #define S3C_SDHCI_CTRL2_ENCLKOUTHOLD (1 << 8) | ||
49 | #define S3C_SDHCI_CTRL2_RWAITMODE (1 << 7) | ||
50 | #define S3C_SDHCI_CTRL2_DISBUFRD (1 << 6) | ||
51 | #define S3C_SDHCI_CTRL2_SELBASECLK_MASK (0x3 << 4) | ||
52 | #define S3C_SDHCI_CTRL2_SELBASECLK_SHIFT (4) | ||
53 | #define S3C_SDHCI_CTRL2_PWRSYNC (1 << 3) | ||
54 | #define S3C_SDHCI_CTRL2_ENCLKOUTMSKCON (1 << 1) | ||
55 | #define S3C_SDHCI_CTRL2_HWINITFIN (1 << 0) | ||
56 | |||
57 | #define S3C_SDHCI_CTRL3_FCSEL3 (1 << 31) | ||
58 | #define S3C_SDHCI_CTRL3_FCSEL2 (1 << 23) | ||
59 | #define S3C_SDHCI_CTRL3_FCSEL1 (1 << 15) | ||
60 | #define S3C_SDHCI_CTRL3_FCSEL0 (1 << 7) | ||
61 | |||
62 | #define S3C_SDHCI_CTRL3_FIA3_MASK (0x7f << 24) | ||
63 | #define S3C_SDHCI_CTRL3_FIA3_SHIFT (24) | ||
64 | #define S3C_SDHCI_CTRL3_FIA3(_x) ((_x) << 24) | ||
65 | |||
66 | #define S3C_SDHCI_CTRL3_FIA2_MASK (0x7f << 16) | ||
67 | #define S3C_SDHCI_CTRL3_FIA2_SHIFT (16) | ||
68 | #define S3C_SDHCI_CTRL3_FIA2(_x) ((_x) << 16) | ||
69 | |||
70 | #define S3C_SDHCI_CTRL3_FIA1_MASK (0x7f << 8) | ||
71 | #define S3C_SDHCI_CTRL3_FIA1_SHIFT (8) | ||
72 | #define S3C_SDHCI_CTRL3_FIA1(_x) ((_x) << 8) | ||
73 | |||
74 | #define S3C_SDHCI_CTRL3_FIA0_MASK (0x7f << 0) | ||
75 | #define S3C_SDHCI_CTRL3_FIA0_SHIFT (0) | ||
76 | #define S3C_SDHCI_CTRL3_FIA0(_x) ((_x) << 0) | ||
77 | |||
78 | #define S3C64XX_SDHCI_CONTROL4_DRIVE_MASK (0x3 << 16) | ||
79 | #define S3C64XX_SDHCI_CONTROL4_DRIVE_SHIFT (16) | ||
80 | #define S3C64XX_SDHCI_CONTROL4_DRIVE_2mA (0x0 << 16) | ||
81 | #define S3C64XX_SDHCI_CONTROL4_DRIVE_4mA (0x1 << 16) | ||
82 | #define S3C64XX_SDHCI_CONTROL4_DRIVE_7mA (0x2 << 16) | ||
83 | #define S3C64XX_SDHCI_CONTROL4_DRIVE_9mA (0x3 << 16) | ||
84 | |||
85 | #define S3C64XX_SDHCI_CONTROL4_BUSY (1) | ||
86 | |||
87 | #endif /* __PLAT_S3C_SDHCI_REGS_H */ | ||
diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h index a0daa647b92c..487d7d2a7e1d 100644 --- a/arch/arm/plat-s3c/include/plat/regs-serial.h +++ b/arch/arm/plat-s3c/include/plat/regs-serial.h | |||
@@ -77,6 +77,12 @@ | |||
77 | #define S3C2440_UCON_FCLK (3<<10) | 77 | #define S3C2440_UCON_FCLK (3<<10) |
78 | #define S3C2443_UCON_EPLL (3<<10) | 78 | #define S3C2443_UCON_EPLL (3<<10) |
79 | 79 | ||
80 | #define S3C6400_UCON_CLKMASK (3<<10) | ||
81 | #define S3C6400_UCON_PCLK (0<<10) | ||
82 | #define S3C6400_UCON_PCLK2 (2<<10) | ||
83 | #define S3C6400_UCON_UCLK0 (1<<10) | ||
84 | #define S3C6400_UCON_UCLK1 (3<<10) | ||
85 | |||
80 | #define S3C2440_UCON2_FCLK_EN (1<<15) | 86 | #define S3C2440_UCON2_FCLK_EN (1<<15) |
81 | #define S3C2440_UCON0_DIVMASK (15 << 12) | 87 | #define S3C2440_UCON0_DIVMASK (15 << 12) |
82 | #define S3C2440_UCON1_DIVMASK (15 << 12) | 88 | #define S3C2440_UCON1_DIVMASK (15 << 12) |
@@ -149,6 +155,14 @@ | |||
149 | #define S3C2410_UFSTAT_RXMASK (15<<0) | 155 | #define S3C2410_UFSTAT_RXMASK (15<<0) |
150 | #define S3C2410_UFSTAT_RXSHIFT (0) | 156 | #define S3C2410_UFSTAT_RXSHIFT (0) |
151 | 157 | ||
158 | /* UFSTAT S3C24A0 */ | ||
159 | #define S3C24A0_UFSTAT_TXFULL (1 << 14) | ||
160 | #define S3C24A0_UFSTAT_RXFULL (1 << 6) | ||
161 | #define S3C24A0_UFSTAT_TXMASK (63 << 8) | ||
162 | #define S3C24A0_UFSTAT_TXSHIFT (8) | ||
163 | #define S3C24A0_UFSTAT_RXMASK (63) | ||
164 | #define S3C24A0_UFSTAT_RXSHIFT (0) | ||
165 | |||
152 | /* UFSTAT S3C2443 same as S3C2440 */ | 166 | /* UFSTAT S3C2443 same as S3C2440 */ |
153 | #define S3C2440_UFSTAT_TXFULL (1<<14) | 167 | #define S3C2440_UFSTAT_TXFULL (1<<14) |
154 | #define S3C2440_UFSTAT_RXFULL (1<<6) | 168 | #define S3C2440_UFSTAT_RXFULL (1<<6) |
@@ -224,7 +238,7 @@ struct s3c2410_uartcfg { | |||
224 | * or platform_add_device() before the console_initcall() | 238 | * or platform_add_device() before the console_initcall() |
225 | */ | 239 | */ |
226 | 240 | ||
227 | extern struct platform_device *s3c24xx_uart_devs[3]; | 241 | extern struct platform_device *s3c24xx_uart_devs[4]; |
228 | 242 | ||
229 | #endif /* __ASSEMBLY__ */ | 243 | #endif /* __ASSEMBLY__ */ |
230 | 244 | ||
diff --git a/arch/arm/plat-s3c/include/plat/regs-timer.h b/arch/arm/plat-s3c/include/plat/regs-timer.h index cc0eedd53e38..d097d92f8cc7 100644 --- a/arch/arm/plat-s3c/include/plat/regs-timer.h +++ b/arch/arm/plat-s3c/include/plat/regs-timer.h | |||
@@ -10,7 +10,6 @@ | |||
10 | * S3C2410 Timer configuration | 10 | * S3C2410 Timer configuration |
11 | */ | 11 | */ |
12 | 12 | ||
13 | |||
14 | #ifndef __ASM_ARCH_REGS_TIMER_H | 13 | #ifndef __ASM_ARCH_REGS_TIMER_H |
15 | #define __ASM_ARCH_REGS_TIMER_H | 14 | #define __ASM_ARCH_REGS_TIMER_H |
16 | 15 | ||
@@ -21,6 +20,8 @@ | |||
21 | #define S3C2410_TCFG1 S3C_TIMERREG(0x04) | 20 | #define S3C2410_TCFG1 S3C_TIMERREG(0x04) |
22 | #define S3C2410_TCON S3C_TIMERREG(0x08) | 21 | #define S3C2410_TCON S3C_TIMERREG(0x08) |
23 | 22 | ||
23 | #define S3C64XX_TINT_CSTAT S3C_TIMERREG(0x44) | ||
24 | |||
24 | #define S3C2410_TCFG_PRESCALER0_MASK (255<<0) | 25 | #define S3C2410_TCFG_PRESCALER0_MASK (255<<0) |
25 | #define S3C2410_TCFG_PRESCALER1_MASK (255<<8) | 26 | #define S3C2410_TCFG_PRESCALER1_MASK (255<<8) |
26 | #define S3C2410_TCFG_PRESCALER1_SHIFT (8) | 27 | #define S3C2410_TCFG_PRESCALER1_SHIFT (8) |
@@ -72,6 +73,14 @@ | |||
72 | #define S3C2410_TCFG1_MUX_TCLK (4<<0) | 73 | #define S3C2410_TCFG1_MUX_TCLK (4<<0) |
73 | #define S3C2410_TCFG1_MUX_MASK (15<<0) | 74 | #define S3C2410_TCFG1_MUX_MASK (15<<0) |
74 | 75 | ||
76 | #define S3C64XX_TCFG1_MUX_DIV1 (0<<0) | ||
77 | #define S3C64XX_TCFG1_MUX_DIV2 (1<<0) | ||
78 | #define S3C64XX_TCFG1_MUX_DIV4 (2<<0) | ||
79 | #define S3C64XX_TCFG1_MUX_DIV8 (3<<0) | ||
80 | #define S3C64XX_TCFG1_MUX_DIV16 (4<<0) | ||
81 | #define S3C64XX_TCFG1_MUX_TCLK (5<<0) /* 3 sets of TCLK */ | ||
82 | #define S3C64XX_TCFG1_MUX_MASK (15<<0) | ||
83 | |||
75 | #define S3C2410_TCFG1_SHIFT(x) ((x) * 4) | 84 | #define S3C2410_TCFG1_SHIFT(x) ((x) * 4) |
76 | 85 | ||
77 | /* for each timer, we have an count buffer, an compare buffer and | 86 | /* for each timer, we have an count buffer, an compare buffer and |
diff --git a/arch/arm/plat-s3c/include/plat/sdhci.h b/arch/arm/plat-s3c/include/plat/sdhci.h new file mode 100644 index 000000000000..c4ca3920ca4b --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/sdhci.h | |||
@@ -0,0 +1,108 @@ | |||
1 | /* linux/arch/arm/plat-s3c/include/plat/sdhci.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * Ben Dooks <ben@simtec.co.uk> | ||
7 | * | ||
8 | * S3C Platform - SDHCI (HSMMC) platform data definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __PLAT_S3C_SDHCI_H | ||
16 | #define __PLAT_S3C_SDHCI_H __FILE__ | ||
17 | |||
18 | struct platform_device; | ||
19 | struct mmc_host; | ||
20 | struct mmc_card; | ||
21 | struct mmc_ios; | ||
22 | |||
23 | /** | ||
24 | * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI | ||
25 | * @max_width: The maximum number of data bits supported. | ||
26 | * @host_caps: Standard MMC host capabilities bit field. | ||
27 | * @cfg_gpio: Configure the GPIO for a specific card bit-width | ||
28 | * @cfg_card: Configure the interface for a specific card and speed. This | ||
29 | * is necessary the controllers and/or GPIO blocks require the | ||
30 | * changing of driver-strength and other controls dependant on | ||
31 | * the card and speed of operation. | ||
32 | * | ||
33 | * Initialisation data specific to either the machine or the platform | ||
34 | * for the device driver to use or call-back when configuring gpio or | ||
35 | * card speed information. | ||
36 | */ | ||
37 | struct s3c_sdhci_platdata { | ||
38 | unsigned int max_width; | ||
39 | unsigned int host_caps; | ||
40 | |||
41 | char **clocks; /* set of clock sources */ | ||
42 | |||
43 | void (*cfg_gpio)(struct platform_device *dev, int width); | ||
44 | void (*cfg_card)(struct platform_device *dev, | ||
45 | void __iomem *regbase, | ||
46 | struct mmc_ios *ios, | ||
47 | struct mmc_card *card); | ||
48 | }; | ||
49 | |||
50 | /** | ||
51 | * s3c_sdhci0_set_platdata - Set platform data for S3C SDHCI device. | ||
52 | * @pd: Platform data to register to device. | ||
53 | * | ||
54 | * Register the given platform data for use withe S3C SDHCI device. | ||
55 | * The call will copy the platform data, so the board definitions can | ||
56 | * make the structure itself __initdata. | ||
57 | */ | ||
58 | extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd); | ||
59 | extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd); | ||
60 | |||
61 | /* Default platform data, exported so that per-cpu initialisation can | ||
62 | * set the correct one when there are more than one cpu type selected. | ||
63 | */ | ||
64 | |||
65 | extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata; | ||
66 | extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata; | ||
67 | |||
68 | /* Helper function availablity */ | ||
69 | |||
70 | #ifdef CONFIG_S3C6410_SETUP_SDHCI | ||
71 | extern char *s3c6410_hsmmc_clksrcs[4]; | ||
72 | |||
73 | extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w); | ||
74 | extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w); | ||
75 | |||
76 | extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev, | ||
77 | void __iomem *r, | ||
78 | struct mmc_ios *ios, | ||
79 | struct mmc_card *card); | ||
80 | |||
81 | #ifdef CONFIG_S3C_DEV_HSMMC | ||
82 | static inline void s3c6410_default_sdhci0(void) | ||
83 | { | ||
84 | s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs; | ||
85 | s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio; | ||
86 | s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; | ||
87 | } | ||
88 | #else | ||
89 | static inline void s3c6410_default_sdhci0(void) { } | ||
90 | #endif /* CONFIG_S3C_DEV_HSMMC */ | ||
91 | |||
92 | #ifdef CONFIG_S3C_DEV_HSMMC1 | ||
93 | static inline void s3c6410_default_sdhci1(void) | ||
94 | { | ||
95 | s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs; | ||
96 | s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci1_cfg_gpio; | ||
97 | s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card; | ||
98 | } | ||
99 | #else | ||
100 | static inline void s3c6410_default_sdhci1(void) { } | ||
101 | #endif /* CONFIG_S3C_DEV_HSMMC1 */ | ||
102 | |||
103 | #else | ||
104 | static inline void s3c6410_default_sdhci0(void) { } | ||
105 | static inline void s3c6410_default_sdhci1(void) { } | ||
106 | #endif /* CONFIG_S3C6410_SETUP_SDHCI */ | ||
107 | |||
108 | #endif /* __PLAT_S3C_SDHCI_H */ | ||
diff --git a/arch/arm/plat-s3c/include/plat/uncompress.h b/arch/arm/plat-s3c/include/plat/uncompress.h index 8a8a927292e0..6061de87f225 100644 --- a/arch/arm/plat-s3c/include/plat/uncompress.h +++ b/arch/arm/plat-s3c/include/plat/uncompress.h | |||
@@ -37,7 +37,7 @@ static void arch_detect_cpu(void); | |||
37 | /* how many bytes we allow into the FIFO at a time in FIFO mode */ | 37 | /* how many bytes we allow into the FIFO at a time in FIFO mode */ |
38 | #define FIFO_MAX (14) | 38 | #define FIFO_MAX (14) |
39 | 39 | ||
40 | #define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT) | 40 | #define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT) |
41 | 41 | ||
42 | static __inline__ void | 42 | static __inline__ void |
43 | uart_wr(unsigned int reg, unsigned int val) | 43 | uart_wr(unsigned int reg, unsigned int val) |
@@ -139,6 +139,28 @@ static void arch_decomp_error(const char *x) | |||
139 | 139 | ||
140 | static void error(char *err); | 140 | static void error(char *err); |
141 | 141 | ||
142 | #ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO | ||
143 | static inline void arch_enable_uart_fifo(void) | ||
144 | { | ||
145 | u32 fifocon = uart_rd(S3C2410_UFCON); | ||
146 | |||
147 | if (!(fifocon & S3C2410_UFCON_FIFOMODE)) { | ||
148 | fifocon |= S3C2410_UFCON_RESETBOTH; | ||
149 | uart_wr(S3C2410_UFCON, fifocon); | ||
150 | |||
151 | /* wait for fifo reset to complete */ | ||
152 | while (1) { | ||
153 | fifocon = uart_rd(S3C2410_UFCON); | ||
154 | if (!(fifocon & S3C2410_UFCON_RESETBOTH)) | ||
155 | break; | ||
156 | } | ||
157 | } | ||
158 | } | ||
159 | #else | ||
160 | #define arch_enable_uart_fifo() do { } while(0) | ||
161 | #endif | ||
162 | |||
163 | |||
142 | static void | 164 | static void |
143 | arch_decomp_setup(void) | 165 | arch_decomp_setup(void) |
144 | { | 166 | { |
@@ -149,6 +171,12 @@ arch_decomp_setup(void) | |||
149 | 171 | ||
150 | arch_detect_cpu(); | 172 | arch_detect_cpu(); |
151 | arch_decomp_wdog_start(); | 173 | arch_decomp_wdog_start(); |
174 | |||
175 | /* Enable the UART FIFOs if they where not enabled and our | ||
176 | * configuration says we should turn them on. | ||
177 | */ | ||
178 | |||
179 | arch_enable_uart_fifo(); | ||
152 | } | 180 | } |
153 | 181 | ||
154 | 182 | ||
diff --git a/arch/arm/plat-s3c/init.c b/arch/arm/plat-s3c/init.c new file mode 100644 index 000000000000..6790edfaca6f --- /dev/null +++ b/arch/arm/plat-s3c/init.c | |||
@@ -0,0 +1,160 @@ | |||
1 | /* linux/arch/arm/plat-s3c/init.c | ||
2 | * | ||
3 | * Copyright (c) 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * S3C series CPU initialisation | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/init.h> | ||
15 | #include <linux/module.h> | ||
16 | #include <linux/interrupt.h> | ||
17 | #include <linux/ioport.h> | ||
18 | #include <linux/serial_core.h> | ||
19 | #include <linux/platform_device.h> | ||
20 | |||
21 | #include <mach/hardware.h> | ||
22 | |||
23 | #include <asm/mach/arch.h> | ||
24 | #include <asm/mach/map.h> | ||
25 | |||
26 | #include <plat/cpu.h> | ||
27 | #include <plat/devs.h> | ||
28 | #include <plat/clock.h> | ||
29 | |||
30 | #include <plat/regs-serial.h> | ||
31 | |||
32 | static struct cpu_table *cpu; | ||
33 | |||
34 | static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode, | ||
35 | struct cpu_table *tab, | ||
36 | unsigned int count) | ||
37 | { | ||
38 | for (; count != 0; count--, tab++) { | ||
39 | if ((idcode & tab->idmask) == tab->idcode) | ||
40 | return tab; | ||
41 | } | ||
42 | |||
43 | return NULL; | ||
44 | } | ||
45 | |||
46 | void __init s3c_init_cpu(unsigned long idcode, | ||
47 | struct cpu_table *cputab, unsigned int cputab_size) | ||
48 | { | ||
49 | cpu = s3c_lookup_cpu(idcode, cputab, cputab_size); | ||
50 | |||
51 | if (cpu == NULL) { | ||
52 | printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode); | ||
53 | panic("Unknown S3C24XX CPU"); | ||
54 | } | ||
55 | |||
56 | printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode); | ||
57 | |||
58 | if (cpu->map_io == NULL || cpu->init == NULL) { | ||
59 | printk(KERN_ERR "CPU %s support not enabled\n", cpu->name); | ||
60 | panic("Unsupported Samsung CPU"); | ||
61 | } | ||
62 | |||
63 | cpu->map_io(); | ||
64 | } | ||
65 | |||
66 | /* s3c24xx_init_clocks | ||
67 | * | ||
68 | * Initialise the clock subsystem and associated information from the | ||
69 | * given master crystal value. | ||
70 | * | ||
71 | * xtal = 0 -> use default PLL crystal value (normally 12MHz) | ||
72 | * != 0 -> PLL crystal value in Hz | ||
73 | */ | ||
74 | |||
75 | void __init s3c24xx_init_clocks(int xtal) | ||
76 | { | ||
77 | if (xtal == 0) | ||
78 | xtal = 12*1000*1000; | ||
79 | |||
80 | if (cpu == NULL) | ||
81 | panic("s3c24xx_init_clocks: no cpu setup?\n"); | ||
82 | |||
83 | if (cpu->init_clocks == NULL) | ||
84 | panic("s3c24xx_init_clocks: cpu has no clock init\n"); | ||
85 | else | ||
86 | (cpu->init_clocks)(xtal); | ||
87 | } | ||
88 | |||
89 | /* uart management */ | ||
90 | |||
91 | static int nr_uarts __initdata = 0; | ||
92 | |||
93 | static struct s3c2410_uartcfg uart_cfgs[CONFIG_SERIAL_SAMSUNG_UARTS]; | ||
94 | |||
95 | /* s3c24xx_init_uartdevs | ||
96 | * | ||
97 | * copy the specified platform data and configuration into our central | ||
98 | * set of devices, before the data is thrown away after the init process. | ||
99 | * | ||
100 | * This also fills in the array passed to the serial driver for the | ||
101 | * early initialisation of the console. | ||
102 | */ | ||
103 | |||
104 | void __init s3c24xx_init_uartdevs(char *name, | ||
105 | struct s3c24xx_uart_resources *res, | ||
106 | struct s3c2410_uartcfg *cfg, int no) | ||
107 | { | ||
108 | struct platform_device *platdev; | ||
109 | struct s3c2410_uartcfg *cfgptr = uart_cfgs; | ||
110 | struct s3c24xx_uart_resources *resp; | ||
111 | int uart; | ||
112 | |||
113 | memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no); | ||
114 | |||
115 | for (uart = 0; uart < no; uart++, cfg++, cfgptr++) { | ||
116 | platdev = s3c24xx_uart_src[cfgptr->hwport]; | ||
117 | |||
118 | resp = res + cfgptr->hwport; | ||
119 | |||
120 | s3c24xx_uart_devs[uart] = platdev; | ||
121 | |||
122 | platdev->name = name; | ||
123 | platdev->resource = resp->resources; | ||
124 | platdev->num_resources = resp->nr_resources; | ||
125 | |||
126 | platdev->dev.platform_data = cfgptr; | ||
127 | } | ||
128 | |||
129 | nr_uarts = no; | ||
130 | } | ||
131 | |||
132 | void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) | ||
133 | { | ||
134 | if (cpu == NULL) | ||
135 | return; | ||
136 | |||
137 | if (cpu->init_uarts == NULL) { | ||
138 | printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n"); | ||
139 | } else | ||
140 | (cpu->init_uarts)(cfg, no); | ||
141 | } | ||
142 | |||
143 | static int __init s3c_arch_init(void) | ||
144 | { | ||
145 | int ret; | ||
146 | |||
147 | // do the correct init for cpu | ||
148 | |||
149 | if (cpu == NULL) | ||
150 | panic("s3c_arch_init: NULL cpu\n"); | ||
151 | |||
152 | ret = (cpu->init)(); | ||
153 | if (ret != 0) | ||
154 | return ret; | ||
155 | |||
156 | ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts); | ||
157 | return ret; | ||
158 | } | ||
159 | |||
160 | arch_initcall(s3c_arch_init); | ||
diff --git a/arch/arm/plat-s3c24xx/pwm-clock.c b/arch/arm/plat-s3c/pwm-clock.c index 3fad68a1e6bc..a318215ab535 100644 --- a/arch/arm/plat-s3c24xx/pwm-clock.c +++ b/arch/arm/plat-s3c/pwm-clock.c | |||
@@ -14,20 +14,20 @@ | |||
14 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
15 | #include <linux/list.h> | 15 | #include <linux/list.h> |
16 | #include <linux/errno.h> | 16 | #include <linux/errno.h> |
17 | #include <linux/log2.h> | ||
17 | #include <linux/clk.h> | 18 | #include <linux/clk.h> |
18 | #include <linux/err.h> | 19 | #include <linux/err.h> |
19 | #include <linux/io.h> | 20 | #include <linux/io.h> |
20 | 21 | ||
21 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
23 | #include <mach/map.h> | ||
22 | #include <asm/irq.h> | 24 | #include <asm/irq.h> |
23 | 25 | ||
24 | #include <mach/regs-clock.h> | ||
25 | #include <mach/regs-gpio.h> | ||
26 | |||
27 | #include <plat/clock.h> | 26 | #include <plat/clock.h> |
28 | #include <plat/cpu.h> | 27 | #include <plat/cpu.h> |
29 | 28 | ||
30 | #include <plat/regs-timer.h> | 29 | #include <plat/regs-timer.h> |
30 | #include <mach/pwm-clock.h> | ||
31 | 31 | ||
32 | /* Each of the timers 0 through 5 go through the following | 32 | /* Each of the timers 0 through 5 go through the following |
33 | * clock tree, with the inputs depending on the timers. | 33 | * clock tree, with the inputs depending on the timers. |
@@ -73,11 +73,13 @@ | |||
73 | * tclk -------------------------/ | 73 | * tclk -------------------------/ |
74 | */ | 74 | */ |
75 | 75 | ||
76 | static unsigned long clk_pwm_scaler_getrate(struct clk *clk) | 76 | static struct clk clk_timer_scaler[]; |
77 | |||
78 | static unsigned long clk_pwm_scaler_get_rate(struct clk *clk) | ||
77 | { | 79 | { |
78 | unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0); | 80 | unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0); |
79 | 81 | ||
80 | if (clk->id == 1) { | 82 | if (clk == &clk_timer_scaler[1]) { |
81 | tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK; | 83 | tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK; |
82 | tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT; | 84 | tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT; |
83 | } else { | 85 | } else { |
@@ -87,18 +89,61 @@ static unsigned long clk_pwm_scaler_getrate(struct clk *clk) | |||
87 | return clk_get_rate(clk->parent) / (tcfg0 + 1); | 89 | return clk_get_rate(clk->parent) / (tcfg0 + 1); |
88 | } | 90 | } |
89 | 91 | ||
90 | /* TODO - add set rate calls. */ | 92 | static unsigned long clk_pwm_scaler_round_rate(struct clk *clk, |
93 | unsigned long rate) | ||
94 | { | ||
95 | unsigned long parent_rate = clk_get_rate(clk->parent); | ||
96 | unsigned long divisor = parent_rate / rate; | ||
97 | |||
98 | if (divisor > 256) | ||
99 | divisor = 256; | ||
100 | else if (divisor < 2) | ||
101 | divisor = 2; | ||
102 | |||
103 | return parent_rate / divisor; | ||
104 | } | ||
105 | |||
106 | static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate) | ||
107 | { | ||
108 | unsigned long round = clk_pwm_scaler_round_rate(clk, rate); | ||
109 | unsigned long tcfg0; | ||
110 | unsigned long divisor; | ||
111 | unsigned long flags; | ||
112 | |||
113 | divisor = clk_get_rate(clk->parent) / round; | ||
114 | divisor--; | ||
115 | |||
116 | local_irq_save(flags); | ||
117 | tcfg0 = __raw_readl(S3C2410_TCFG0); | ||
118 | |||
119 | if (clk == &clk_timer_scaler[1]) { | ||
120 | tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK; | ||
121 | tcfg0 |= divisor << S3C2410_TCFG_PRESCALER1_SHIFT; | ||
122 | } else { | ||
123 | tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK; | ||
124 | tcfg0 |= divisor; | ||
125 | } | ||
126 | |||
127 | __raw_writel(tcfg0, S3C2410_TCFG0); | ||
128 | local_irq_restore(flags); | ||
129 | |||
130 | return 0; | ||
131 | } | ||
91 | 132 | ||
92 | static struct clk clk_timer_scaler[] = { | 133 | static struct clk clk_timer_scaler[] = { |
93 | [0] = { | 134 | [0] = { |
94 | .name = "pwm-scaler0", | 135 | .name = "pwm-scaler0", |
95 | .id = -1, | 136 | .id = -1, |
96 | .get_rate = clk_pwm_scaler_getrate, | 137 | .get_rate = clk_pwm_scaler_get_rate, |
138 | .set_rate = clk_pwm_scaler_set_rate, | ||
139 | .round_rate = clk_pwm_scaler_round_rate, | ||
97 | }, | 140 | }, |
98 | [1] = { | 141 | [1] = { |
99 | .name = "pwm-scaler1", | 142 | .name = "pwm-scaler1", |
100 | .id = -1, | 143 | .id = -1, |
101 | .get_rate = clk_pwm_scaler_getrate, | 144 | .get_rate = clk_pwm_scaler_get_rate, |
145 | .set_rate = clk_pwm_scaler_set_rate, | ||
146 | .round_rate = clk_pwm_scaler_round_rate, | ||
102 | }, | 147 | }, |
103 | }; | 148 | }; |
104 | 149 | ||
@@ -123,11 +168,6 @@ static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk) | |||
123 | return container_of(clk, struct pwm_tdiv_clk, clk); | 168 | return container_of(clk, struct pwm_tdiv_clk, clk); |
124 | } | 169 | } |
125 | 170 | ||
126 | static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) | ||
127 | { | ||
128 | return 1 << (1 + tcfg1); | ||
129 | } | ||
130 | |||
131 | static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk) | 171 | static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk) |
132 | { | 172 | { |
133 | unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); | 173 | unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1); |
@@ -136,7 +176,7 @@ static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk) | |||
136 | tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id); | 176 | tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id); |
137 | tcfg1 &= S3C2410_TCFG1_MUX_MASK; | 177 | tcfg1 &= S3C2410_TCFG1_MUX_MASK; |
138 | 178 | ||
139 | if (tcfg1 == S3C2410_TCFG1_MUX_TCLK) | 179 | if (pwm_cfg_src_is_tclk(tcfg1)) |
140 | divisor = to_tdiv(clk)->divisor; | 180 | divisor = to_tdiv(clk)->divisor; |
141 | else | 181 | else |
142 | divisor = tcfg_to_divisor(tcfg1); | 182 | divisor = tcfg_to_divisor(tcfg1); |
@@ -153,7 +193,9 @@ static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk, | |||
153 | parent_rate = clk_get_rate(clk->parent); | 193 | parent_rate = clk_get_rate(clk->parent); |
154 | divisor = parent_rate / rate; | 194 | divisor = parent_rate / rate; |
155 | 195 | ||
156 | if (divisor <= 2) | 196 | if (divisor <= 1 && pwm_tdiv_has_div1()) |
197 | divisor = 1; | ||
198 | else if (divisor <= 2) | ||
157 | divisor = 2; | 199 | divisor = 2; |
158 | else if (divisor <= 4) | 200 | else if (divisor <= 4) |
159 | divisor = 4; | 201 | divisor = 4; |
@@ -167,25 +209,7 @@ static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk, | |||
167 | 209 | ||
168 | static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk) | 210 | static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk) |
169 | { | 211 | { |
170 | unsigned long bits; | 212 | return pwm_tdiv_div_bits(divclk->divisor); |
171 | |||
172 | switch (divclk->divisor) { | ||
173 | case 2: | ||
174 | bits = S3C2410_TCFG1_MUX_DIV2; | ||
175 | break; | ||
176 | case 4: | ||
177 | bits = S3C2410_TCFG1_MUX_DIV4; | ||
178 | break; | ||
179 | case 8: | ||
180 | bits = S3C2410_TCFG1_MUX_DIV8; | ||
181 | break; | ||
182 | case 16: | ||
183 | default: | ||
184 | bits = S3C2410_TCFG1_MUX_DIV16; | ||
185 | break; | ||
186 | } | ||
187 | |||
188 | return bits; | ||
189 | } | 213 | } |
190 | 214 | ||
191 | static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk) | 215 | static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk) |
@@ -226,7 +250,7 @@ static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate) | |||
226 | /* Update the current MUX settings if we are currently | 250 | /* Update the current MUX settings if we are currently |
227 | * selected as the clock source for this clock. */ | 251 | * selected as the clock source for this clock. */ |
228 | 252 | ||
229 | if (tcfg1 != S3C2410_TCFG1_MUX_TCLK) | 253 | if (!pwm_cfg_src_is_tclk(tcfg1)) |
230 | clk_pwm_tdiv_update(divclk); | 254 | clk_pwm_tdiv_update(divclk); |
231 | 255 | ||
232 | return 0; | 256 | return 0; |
@@ -313,7 +337,7 @@ static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent) | |||
313 | unsigned long shift = S3C2410_TCFG1_SHIFT(id); | 337 | unsigned long shift = S3C2410_TCFG1_SHIFT(id); |
314 | 338 | ||
315 | if (parent == s3c24xx_pwmclk_tclk(id)) | 339 | if (parent == s3c24xx_pwmclk_tclk(id)) |
316 | bits = S3C2410_TCFG1_MUX_TCLK << shift; | 340 | bits = S3C_TCFG1_MUX_TCLK << shift; |
317 | else if (parent == s3c24xx_pwmclk_tdiv(id)) | 341 | else if (parent == s3c24xx_pwmclk_tdiv(id)) |
318 | bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift; | 342 | bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift; |
319 | else | 343 | else |
@@ -375,7 +399,7 @@ static __init int clk_pwm_tin_register(struct clk *pwm) | |||
375 | tcfg1 >>= S3C2410_TCFG1_SHIFT(id); | 399 | tcfg1 >>= S3C2410_TCFG1_SHIFT(id); |
376 | tcfg1 &= S3C2410_TCFG1_MUX_MASK; | 400 | tcfg1 &= S3C2410_TCFG1_MUX_MASK; |
377 | 401 | ||
378 | if (tcfg1 == S3C2410_TCFG1_MUX_TCLK) | 402 | if (pwm_cfg_src_is_tclk(tcfg1)) |
379 | parent = s3c24xx_pwmclk_tclk(id); | 403 | parent = s3c24xx_pwmclk_tclk(id); |
380 | else | 404 | else |
381 | parent = s3c24xx_pwmclk_tdiv(id); | 405 | parent = s3c24xx_pwmclk_tdiv(id); |
@@ -383,7 +407,16 @@ static __init int clk_pwm_tin_register(struct clk *pwm) | |||
383 | return clk_set_parent(pwm, parent); | 407 | return clk_set_parent(pwm, parent); |
384 | } | 408 | } |
385 | 409 | ||
386 | static __init int s3c24xx_pwmclk_init(void) | 410 | /** |
411 | * s3c_pwmclk_init() - initialise pwm clocks | ||
412 | * | ||
413 | * Initialise and register the clocks which provide the inputs for the | ||
414 | * pwm timer blocks. | ||
415 | * | ||
416 | * Note, this call is required by the time core, so must be called after | ||
417 | * the base clocks are added and before any of the initcalls are run. | ||
418 | */ | ||
419 | __init void s3c_pwmclk_init(void) | ||
387 | { | 420 | { |
388 | struct clk *clk_timers; | 421 | struct clk *clk_timers; |
389 | unsigned int clk; | 422 | unsigned int clk; |
@@ -392,7 +425,7 @@ static __init int s3c24xx_pwmclk_init(void) | |||
392 | clk_timers = clk_get(NULL, "timers"); | 425 | clk_timers = clk_get(NULL, "timers"); |
393 | if (IS_ERR(clk_timers)) { | 426 | if (IS_ERR(clk_timers)) { |
394 | printk(KERN_ERR "%s: no parent clock\n", __func__); | 427 | printk(KERN_ERR "%s: no parent clock\n", __func__); |
395 | return -EINVAL; | 428 | return; |
396 | } | 429 | } |
397 | 430 | ||
398 | for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) { | 431 | for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) { |
@@ -400,7 +433,7 @@ static __init int s3c24xx_pwmclk_init(void) | |||
400 | ret = s3c24xx_register_clock(&clk_timer_scaler[clk]); | 433 | ret = s3c24xx_register_clock(&clk_timer_scaler[clk]); |
401 | if (ret < 0) { | 434 | if (ret < 0) { |
402 | printk(KERN_ERR "error adding pwm scaler%d clock\n", clk); | 435 | printk(KERN_ERR "error adding pwm scaler%d clock\n", clk); |
403 | goto err; | 436 | return; |
404 | } | 437 | } |
405 | } | 438 | } |
406 | 439 | ||
@@ -408,7 +441,7 @@ static __init int s3c24xx_pwmclk_init(void) | |||
408 | ret = s3c24xx_register_clock(&clk_timer_tclk[clk]); | 441 | ret = s3c24xx_register_clock(&clk_timer_tclk[clk]); |
409 | if (ret < 0) { | 442 | if (ret < 0) { |
410 | printk(KERN_ERR "error adding pww tclk%d\n", clk); | 443 | printk(KERN_ERR "error adding pww tclk%d\n", clk); |
411 | goto err; | 444 | return; |
412 | } | 445 | } |
413 | } | 446 | } |
414 | 447 | ||
@@ -416,7 +449,7 @@ static __init int s3c24xx_pwmclk_init(void) | |||
416 | ret = clk_pwm_tdiv_register(clk); | 449 | ret = clk_pwm_tdiv_register(clk); |
417 | if (ret < 0) { | 450 | if (ret < 0) { |
418 | printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk); | 451 | printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk); |
419 | goto err; | 452 | return; |
420 | } | 453 | } |
421 | } | 454 | } |
422 | 455 | ||
@@ -424,14 +457,7 @@ static __init int s3c24xx_pwmclk_init(void) | |||
424 | ret = clk_pwm_tin_register(&clk_tin[clk]); | 457 | ret = clk_pwm_tin_register(&clk_tin[clk]); |
425 | if (ret < 0) { | 458 | if (ret < 0) { |
426 | printk(KERN_ERR "error adding pwm%d tin clock\n", clk); | 459 | printk(KERN_ERR "error adding pwm%d tin clock\n", clk); |
427 | goto err; | 460 | return; |
428 | } | 461 | } |
429 | } | 462 | } |
430 | |||
431 | return 0; | ||
432 | |||
433 | err: | ||
434 | return ret; | ||
435 | } | 463 | } |
436 | |||
437 | arch_initcall(s3c24xx_pwmclk_init); | ||
diff --git a/arch/arm/plat-s3c24xx/time.c b/arch/arm/plat-s3c/time.c index c51916236ac0..3b27b29da478 100644 --- a/arch/arm/plat-s3c24xx/time.c +++ b/arch/arm/plat-s3c/time.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <linux/err.h> | 26 | #include <linux/err.h> |
27 | #include <linux/clk.h> | 27 | #include <linux/clk.h> |
28 | #include <linux/io.h> | 28 | #include <linux/io.h> |
29 | #include <linux/platform_device.h> | ||
29 | 30 | ||
30 | #include <asm/system.h> | 31 | #include <asm/system.h> |
31 | #include <asm/leds.h> | 32 | #include <asm/leds.h> |
@@ -36,6 +37,7 @@ | |||
36 | #include <plat/regs-timer.h> | 37 | #include <plat/regs-timer.h> |
37 | #include <mach/regs-irq.h> | 38 | #include <mach/regs-irq.h> |
38 | #include <asm/mach/time.h> | 39 | #include <asm/mach/time.h> |
40 | #include <mach/tick.h> | ||
39 | 41 | ||
40 | #include <plat/clock.h> | 42 | #include <plat/clock.h> |
41 | #include <plat/cpu.h> | 43 | #include <plat/cpu.h> |
@@ -43,6 +45,10 @@ | |||
43 | static unsigned long timer_startval; | 45 | static unsigned long timer_startval; |
44 | static unsigned long timer_usec_ticks; | 46 | static unsigned long timer_usec_ticks; |
45 | 47 | ||
48 | #ifndef TICK_MAX | ||
49 | #define TICK_MAX (0xffff) | ||
50 | #endif | ||
51 | |||
46 | #define TIMER_USEC_SHIFT 16 | 52 | #define TIMER_USEC_SHIFT 16 |
47 | 53 | ||
48 | /* we use the shifted arithmetic to work out the ratio of timer ticks | 54 | /* we use the shifted arithmetic to work out the ratio of timer ticks |
@@ -91,23 +97,19 @@ static inline unsigned long timer_ticks_to_usec(unsigned long ticks) | |||
91 | * IRQs are disabled before entering here from do_gettimeofday() | 97 | * IRQs are disabled before entering here from do_gettimeofday() |
92 | */ | 98 | */ |
93 | 99 | ||
94 | #define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0)) | ||
95 | |||
96 | static unsigned long s3c2410_gettimeoffset (void) | 100 | static unsigned long s3c2410_gettimeoffset (void) |
97 | { | 101 | { |
98 | unsigned long tdone; | 102 | unsigned long tdone; |
99 | unsigned long irqpend; | ||
100 | unsigned long tval; | 103 | unsigned long tval; |
101 | 104 | ||
102 | /* work out how many ticks have gone since last timer interrupt */ | 105 | /* work out how many ticks have gone since last timer interrupt */ |
103 | 106 | ||
104 | tval = __raw_readl(S3C2410_TCNTO(4)); | 107 | tval = __raw_readl(S3C2410_TCNTO(4)); |
105 | tdone = timer_startval - tval; | 108 | tdone = timer_startval - tval; |
106 | 109 | ||
107 | /* check to see if there is an interrupt pending */ | 110 | /* check to see if there is an interrupt pending */ |
108 | 111 | ||
109 | irqpend = __raw_readl(S3C2410_SRCPND); | 112 | if (s3c24xx_ostimer_pending()) { |
110 | if (irqpend & SRCPND_TIMER4) { | ||
111 | /* re-read the timer, and try and fix up for the missed | 113 | /* re-read the timer, and try and fix up for the missed |
112 | * interrupt. Note, the interrupt may go off before the | 114 | * interrupt. Note, the interrupt may go off before the |
113 | * timer has re-loaded from wrapping. | 115 | * timer has re-loaded from wrapping. |
@@ -144,7 +146,11 @@ static struct irqaction s3c2410_timer_irq = { | |||
144 | machine_is_bast() || \ | 146 | machine_is_bast() || \ |
145 | machine_is_vr1000() || \ | 147 | machine_is_vr1000() || \ |
146 | machine_is_anubis() || \ | 148 | machine_is_anubis() || \ |
147 | machine_is_osiris() ) | 149 | machine_is_osiris()) |
150 | |||
151 | static struct clk *tin; | ||
152 | static struct clk *tdiv; | ||
153 | static struct clk *timerclk; | ||
148 | 154 | ||
149 | /* | 155 | /* |
150 | * Set up timer interrupt, and return the current time in seconds. | 156 | * Set up timer interrupt, and return the current time in seconds. |
@@ -159,13 +165,7 @@ static void s3c2410_timer_setup (void) | |||
159 | unsigned long tcfg1; | 165 | unsigned long tcfg1; |
160 | unsigned long tcfg0; | 166 | unsigned long tcfg0; |
161 | 167 | ||
162 | tcnt = 0xffff; /* default value for tcnt */ | 168 | tcnt = TICK_MAX; /* default value for tcnt */ |
163 | |||
164 | /* read the current timer configuration bits */ | ||
165 | |||
166 | tcon = __raw_readl(S3C2410_TCON); | ||
167 | tcfg1 = __raw_readl(S3C2410_TCFG1); | ||
168 | tcfg0 = __raw_readl(S3C2410_TCFG0); | ||
169 | 169 | ||
170 | /* configure the system for whichever machine is in use */ | 170 | /* configure the system for whichever machine is in use */ |
171 | 171 | ||
@@ -174,11 +174,13 @@ static void s3c2410_timer_setup (void) | |||
174 | timer_usec_ticks = timer_mask_usec_ticks(1, 12000000); | 174 | timer_usec_ticks = timer_mask_usec_ticks(1, 12000000); |
175 | tcnt = 12000000 / HZ; | 175 | tcnt = 12000000 / HZ; |
176 | 176 | ||
177 | tcfg1 = __raw_readl(S3C2410_TCFG1); | ||
177 | tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK; | 178 | tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK; |
178 | tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1; | 179 | tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1; |
180 | __raw_writel(tcfg1, S3C2410_TCFG1); | ||
179 | } else { | 181 | } else { |
180 | unsigned long pclk; | 182 | unsigned long pclk; |
181 | struct clk *clk; | 183 | struct clk *tscaler; |
182 | 184 | ||
183 | /* for the h1940 (and others), we use the pclk from the core | 185 | /* for the h1940 (and others), we use the pclk from the core |
184 | * to generate the timer values. since values around 50 to | 186 | * to generate the timer values. since values around 50 to |
@@ -189,38 +191,34 @@ static void s3c2410_timer_setup (void) | |||
189 | * (8.45 ticks per usec) | 191 | * (8.45 ticks per usec) |
190 | */ | 192 | */ |
191 | 193 | ||
192 | /* this is used as default if no other timer can be found */ | 194 | pclk = clk_get_rate(timerclk); |
193 | |||
194 | clk = clk_get(NULL, "timers"); | ||
195 | if (IS_ERR(clk)) | ||
196 | panic("failed to get clock for system timer"); | ||
197 | |||
198 | clk_enable(clk); | ||
199 | |||
200 | pclk = clk_get_rate(clk); | ||
201 | 195 | ||
202 | /* configure clock tick */ | 196 | /* configure clock tick */ |
203 | 197 | ||
204 | timer_usec_ticks = timer_mask_usec_ticks(6, pclk); | 198 | timer_usec_ticks = timer_mask_usec_ticks(6, pclk); |
205 | 199 | ||
206 | tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK; | 200 | tscaler = clk_get_parent(tdiv); |
207 | tcfg1 |= S3C2410_TCFG1_MUX4_DIV2; | ||
208 | 201 | ||
209 | tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK; | 202 | clk_set_rate(tscaler, pclk / 3); |
210 | tcfg0 |= ((6 - 1) / 2) << S3C2410_TCFG_PRESCALER1_SHIFT; | 203 | clk_set_rate(tdiv, pclk / 6); |
204 | clk_set_parent(tin, tdiv); | ||
211 | 205 | ||
212 | tcnt = (pclk / 6) / HZ; | 206 | tcnt = clk_get_rate(tin) / HZ; |
213 | } | 207 | } |
214 | 208 | ||
209 | tcon = __raw_readl(S3C2410_TCON); | ||
210 | tcfg0 = __raw_readl(S3C2410_TCFG0); | ||
211 | tcfg1 = __raw_readl(S3C2410_TCFG1); | ||
212 | |||
215 | /* timers reload after counting zero, so reduce the count by 1 */ | 213 | /* timers reload after counting zero, so reduce the count by 1 */ |
216 | 214 | ||
217 | tcnt--; | 215 | tcnt--; |
218 | 216 | ||
219 | printk("timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n", | 217 | printk(KERN_DEBUG "timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n", |
220 | tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks); | 218 | tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks); |
221 | 219 | ||
222 | /* check to see if timer is within 16bit range... */ | 220 | /* check to see if timer is within 16bit range... */ |
223 | if (tcnt > 0xffff) { | 221 | if (tcnt > TICK_MAX) { |
224 | panic("setup_timer: HZ is too small, cannot configure timer!"); | 222 | panic("setup_timer: HZ is too small, cannot configure timer!"); |
225 | return; | 223 | return; |
226 | } | 224 | } |
@@ -247,8 +245,35 @@ static void s3c2410_timer_setup (void) | |||
247 | __raw_writel(tcon, S3C2410_TCON); | 245 | __raw_writel(tcon, S3C2410_TCON); |
248 | } | 246 | } |
249 | 247 | ||
250 | static void __init s3c2410_timer_init (void) | 248 | static void __init s3c2410_timer_resources(void) |
249 | { | ||
250 | struct platform_device tmpdev; | ||
251 | |||
252 | tmpdev.dev.bus = &platform_bus_type; | ||
253 | tmpdev.id = 4; | ||
254 | |||
255 | timerclk = clk_get(NULL, "timers"); | ||
256 | if (IS_ERR(timerclk)) | ||
257 | panic("failed to get clock for system timer"); | ||
258 | |||
259 | clk_enable(timerclk); | ||
260 | |||
261 | if (!use_tclk1_12()) { | ||
262 | tin = clk_get(&tmpdev.dev, "pwm-tin"); | ||
263 | if (IS_ERR(tin)) | ||
264 | panic("failed to get pwm-tin clock for system timer"); | ||
265 | |||
266 | tdiv = clk_get(&tmpdev.dev, "pwm-tdiv"); | ||
267 | if (IS_ERR(tdiv)) | ||
268 | panic("failed to get pwm-tdiv clock for system timer"); | ||
269 | } | ||
270 | |||
271 | clk_enable(tin); | ||
272 | } | ||
273 | |||
274 | static void __init s3c2410_timer_init(void) | ||
251 | { | 275 | { |
276 | s3c2410_timer_resources(); | ||
252 | s3c2410_timer_setup(); | 277 | s3c2410_timer_setup(); |
253 | setup_irq(IRQ_TIMER4, &s3c2410_timer_irq); | 278 | setup_irq(IRQ_TIMER4, &s3c2410_timer_irq); |
254 | } | 279 | } |
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig index 0af3872fb763..2c8a2f5d75ff 100644 --- a/arch/arm/plat-s3c24xx/Kconfig +++ b/arch/arm/plat-s3c24xx/Kconfig | |||
@@ -6,8 +6,8 @@ | |||
6 | 6 | ||
7 | config PLAT_S3C24XX | 7 | config PLAT_S3C24XX |
8 | bool | 8 | bool |
9 | depends on ARCH_S3C2410 | 9 | depends on ARCH_S3C2410 || ARCH_S3C24A0 |
10 | default y if ARCH_S3C2410 | 10 | default y |
11 | select NO_IOPORT | 11 | select NO_IOPORT |
12 | select ARCH_REQUIRE_GPIOLIB | 12 | select ARCH_REQUIRE_GPIOLIB |
13 | help | 13 | help |
@@ -15,6 +15,19 @@ config PLAT_S3C24XX | |||
15 | 15 | ||
16 | if PLAT_S3C24XX | 16 | if PLAT_S3C24XX |
17 | 17 | ||
18 | # code that is shared between a number of the s3c24xx implementations | ||
19 | |||
20 | config S3C2410_CLOCK | ||
21 | bool | ||
22 | help | ||
23 | Clock code for the S3C2410, and similar processors which | ||
24 | is currently includes the S3C2410, S3C2440, S3C2442. | ||
25 | |||
26 | config S3C24XX_DCLK | ||
27 | bool | ||
28 | help | ||
29 | Clock code for supporting DCLK/CLKOUT on S3C24XX architectures | ||
30 | |||
18 | config CPU_S3C244X | 31 | config CPU_S3C244X |
19 | bool | 32 | bool |
20 | depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442) | 33 | depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442) |
@@ -28,6 +41,27 @@ config S3C24XX_PWM | |||
28 | Support for exporting the PWM timer blocks via the pwm device | 41 | Support for exporting the PWM timer blocks via the pwm device |
29 | system. | 42 | system. |
30 | 43 | ||
44 | |||
45 | # gpio configurations | ||
46 | |||
47 | config S3C24XX_GPIO_EXTRA | ||
48 | int | ||
49 | default 128 if S3C24XX_GPIO_EXTRA128 | ||
50 | default 64 if S3C24XX_GPIO_EXTRA64 | ||
51 | default 0 | ||
52 | |||
53 | config S3C24XX_GPIO_EXTRA64 | ||
54 | bool | ||
55 | help | ||
56 | Add an extra 64 gpio numbers to the available GPIO pool. This is | ||
57 | available for boards that need extra gpios for external devices. | ||
58 | |||
59 | config S3C24XX_GPIO_EXTRA128 | ||
60 | bool | ||
61 | help | ||
62 | Add an extra 128 gpio numbers to the available GPIO pool. This is | ||
63 | available for boards that need extra gpios for external devices. | ||
64 | |||
31 | config PM_SIMTEC | 65 | config PM_SIMTEC |
32 | bool | 66 | bool |
33 | help | 67 | help |
@@ -49,6 +83,29 @@ config S3C2410_DMA_DEBUG | |||
49 | Enable debugging output for the DMA code. This option sends info | 83 | Enable debugging output for the DMA code. This option sends info |
50 | to the kernel log, at priority KERN_DEBUG. | 84 | to the kernel log, at priority KERN_DEBUG. |
51 | 85 | ||
86 | config S3C24XX_ADC | ||
87 | bool "ADC common driver support" | ||
88 | help | ||
89 | Core support for the ADC block found in the S3C24XX SoC systems | ||
90 | for drivers such as the touchscreen and hwmon to use to share | ||
91 | this resource. | ||
92 | |||
93 | # SPI default pin configuration code | ||
94 | |||
95 | config S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13 | ||
96 | bool | ||
97 | help | ||
98 | SPI GPIO configuration code for BUS0 when connected to | ||
99 | GPE11, GPE12 and GPE13. | ||
100 | |||
101 | config S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7 | ||
102 | bool | ||
103 | help | ||
104 | SPI GPIO configuration code for BUS 1 when connected to | ||
105 | GPG5, GPG6 and GPG7. | ||
106 | |||
107 | # common code for s3c24xx based machines, such as the SMDKs. | ||
108 | |||
52 | config MACH_SMDK | 109 | config MACH_SMDK |
53 | bool | 110 | bool |
54 | help | 111 | help |
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index d82767b2b833..1e0767b266b8 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile | |||
@@ -17,9 +17,8 @@ obj-y += irq.o | |||
17 | obj-y += devs.o | 17 | obj-y += devs.o |
18 | obj-y += gpio.o | 18 | obj-y += gpio.o |
19 | obj-y += gpiolib.o | 19 | obj-y += gpiolib.o |
20 | obj-y += time.o | ||
21 | obj-y += clock.o | 20 | obj-y += clock.o |
22 | obj-y += pwm-clock.o | 21 | obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o |
23 | 22 | ||
24 | # Architecture dependant builds | 23 | # Architecture dependant builds |
25 | 24 | ||
@@ -30,5 +29,18 @@ obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o | |||
30 | obj-$(CONFIG_PM) += pm.o | 29 | obj-$(CONFIG_PM) += pm.o |
31 | obj-$(CONFIG_PM) += sleep.o | 30 | obj-$(CONFIG_PM) += sleep.o |
32 | obj-$(CONFIG_HAVE_PWM) += pwm.o | 31 | obj-$(CONFIG_HAVE_PWM) += pwm.o |
32 | obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o | ||
33 | obj-$(CONFIG_S3C2410_DMA) += dma.o | 33 | obj-$(CONFIG_S3C2410_DMA) += dma.o |
34 | obj-$(CONFIG_S3C24XX_ADC) += adc.o | ||
35 | |||
36 | # device specific setup and/or initialisation | ||
37 | obj-$(CONFIG_ARCH_S3C2410) += setup-i2c.o | ||
38 | |||
39 | # SPI gpio central GPIO functions | ||
40 | |||
41 | obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o | ||
42 | obj-$(CONFIG_S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7) += spi-bus1-gpg5_6_7.o | ||
43 | |||
44 | # machine common support | ||
45 | |||
34 | obj-$(CONFIG_MACH_SMDK) += common-smdk.o | 46 | obj-$(CONFIG_MACH_SMDK) += common-smdk.o |
diff --git a/arch/arm/plat-s3c24xx/adc.c b/arch/arm/plat-s3c24xx/adc.c new file mode 100644 index 000000000000..9a5c767e0a42 --- /dev/null +++ b/arch/arm/plat-s3c24xx/adc.c | |||
@@ -0,0 +1,372 @@ | |||
1 | /* arch/arm/plat-s3c24xx/adc.c | ||
2 | * | ||
3 | * Copyright (c) 2008 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org> | ||
6 | * | ||
7 | * S3C24XX ADC device core | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License. | ||
12 | */ | ||
13 | |||
14 | #include <linux/module.h> | ||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/platform_device.h> | ||
17 | #include <linux/list.h> | ||
18 | #include <linux/err.h> | ||
19 | #include <linux/clk.h> | ||
20 | #include <linux/interrupt.h> | ||
21 | #include <linux/io.h> | ||
22 | |||
23 | #include <plat/regs-adc.h> | ||
24 | #include <plat/adc.h> | ||
25 | |||
26 | /* This driver is designed to control the usage of the ADC block between | ||
27 | * the touchscreen and any other drivers that may need to use it, such as | ||
28 | * the hwmon driver. | ||
29 | * | ||
30 | * Priority will be given to the touchscreen driver, but as this itself is | ||
31 | * rate limited it should not starve other requests which are processed in | ||
32 | * order that they are received. | ||
33 | * | ||
34 | * Each user registers to get a client block which uniquely identifies it | ||
35 | * and stores information such as the necessary functions to callback when | ||
36 | * action is required. | ||
37 | */ | ||
38 | |||
39 | struct s3c_adc_client { | ||
40 | struct platform_device *pdev; | ||
41 | struct list_head pend; | ||
42 | |||
43 | unsigned int nr_samples; | ||
44 | unsigned char is_ts; | ||
45 | unsigned char channel; | ||
46 | |||
47 | void (*select_cb)(unsigned selected); | ||
48 | void (*convert_cb)(unsigned val1, unsigned val2); | ||
49 | }; | ||
50 | |||
51 | struct adc_device { | ||
52 | struct platform_device *pdev; | ||
53 | struct platform_device *owner; | ||
54 | struct clk *clk; | ||
55 | struct s3c_adc_client *cur; | ||
56 | struct s3c_adc_client *ts_pend; | ||
57 | void __iomem *regs; | ||
58 | |||
59 | unsigned int prescale; | ||
60 | |||
61 | int irq; | ||
62 | }; | ||
63 | |||
64 | static struct adc_device *adc_dev; | ||
65 | |||
66 | static LIST_HEAD(adc_pending); | ||
67 | |||
68 | #define adc_dbg(_adc, msg...) dev_dbg(&(_adc)->pdev->dev, msg) | ||
69 | |||
70 | static inline void s3c_adc_convert(struct adc_device *adc) | ||
71 | { | ||
72 | unsigned con = readl(adc->regs + S3C2410_ADCCON); | ||
73 | |||
74 | con |= S3C2410_ADCCON_ENABLE_START; | ||
75 | writel(con, adc->regs + S3C2410_ADCCON); | ||
76 | } | ||
77 | |||
78 | static inline void s3c_adc_select(struct adc_device *adc, | ||
79 | struct s3c_adc_client *client) | ||
80 | { | ||
81 | unsigned con = readl(adc->regs + S3C2410_ADCCON); | ||
82 | |||
83 | client->select_cb(1); | ||
84 | |||
85 | con &= ~S3C2410_ADCCON_MUXMASK; | ||
86 | con &= ~S3C2410_ADCCON_STDBM; | ||
87 | con &= ~S3C2410_ADCCON_STARTMASK; | ||
88 | |||
89 | if (!client->is_ts) | ||
90 | con |= S3C2410_ADCCON_SELMUX(client->channel); | ||
91 | |||
92 | writel(con, adc->regs + S3C2410_ADCCON); | ||
93 | } | ||
94 | |||
95 | static void s3c_adc_dbgshow(struct adc_device *adc) | ||
96 | { | ||
97 | adc_dbg(adc, "CON=%08x, TSC=%08x, DLY=%08x\n", | ||
98 | readl(adc->regs + S3C2410_ADCCON), | ||
99 | readl(adc->regs + S3C2410_ADCTSC), | ||
100 | readl(adc->regs + S3C2410_ADCDLY)); | ||
101 | } | ||
102 | |||
103 | void s3c_adc_try(struct adc_device *adc) | ||
104 | { | ||
105 | struct s3c_adc_client *next = adc->ts_pend; | ||
106 | |||
107 | if (!next && !list_empty(&adc_pending)) { | ||
108 | next = list_first_entry(&adc_pending, | ||
109 | struct s3c_adc_client, pend); | ||
110 | list_del(&next->pend); | ||
111 | } else | ||
112 | adc->ts_pend = NULL; | ||
113 | |||
114 | if (next) { | ||
115 | adc_dbg(adc, "new client is %p\n", next); | ||
116 | adc->cur = next; | ||
117 | s3c_adc_select(adc, next); | ||
118 | s3c_adc_convert(adc); | ||
119 | s3c_adc_dbgshow(adc); | ||
120 | } | ||
121 | } | ||
122 | |||
123 | int s3c_adc_start(struct s3c_adc_client *client, | ||
124 | unsigned int channel, unsigned int nr_samples) | ||
125 | { | ||
126 | struct adc_device *adc = adc_dev; | ||
127 | unsigned long flags; | ||
128 | |||
129 | if (!adc) { | ||
130 | printk(KERN_ERR "%s: failed to find adc\n", __func__); | ||
131 | return -EINVAL; | ||
132 | } | ||
133 | |||
134 | if (client->is_ts && adc->ts_pend) | ||
135 | return -EAGAIN; | ||
136 | |||
137 | local_irq_save(flags); | ||
138 | |||
139 | client->channel = channel; | ||
140 | client->nr_samples = nr_samples; | ||
141 | |||
142 | if (client->is_ts) | ||
143 | adc->ts_pend = client; | ||
144 | else | ||
145 | list_add_tail(&client->pend, &adc_pending); | ||
146 | |||
147 | if (!adc->cur) | ||
148 | s3c_adc_try(adc); | ||
149 | local_irq_restore(flags); | ||
150 | |||
151 | return 0; | ||
152 | } | ||
153 | EXPORT_SYMBOL_GPL(s3c_adc_start); | ||
154 | |||
155 | static void s3c_adc_default_select(unsigned select) | ||
156 | { | ||
157 | } | ||
158 | |||
159 | struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev, | ||
160 | void (*select)(unsigned int selected), | ||
161 | void (*conv)(unsigned d0, unsigned d1), | ||
162 | unsigned int is_ts) | ||
163 | { | ||
164 | struct s3c_adc_client *client; | ||
165 | |||
166 | WARN_ON(!pdev); | ||
167 | WARN_ON(!conv); | ||
168 | |||
169 | if (!select) | ||
170 | select = s3c_adc_default_select; | ||
171 | |||
172 | if (!conv || !pdev) | ||
173 | return ERR_PTR(-EINVAL); | ||
174 | |||
175 | client = kzalloc(sizeof(struct s3c_adc_client), GFP_KERNEL); | ||
176 | if (!client) { | ||
177 | dev_err(&pdev->dev, "no memory for adc client\n"); | ||
178 | return ERR_PTR(-ENOMEM); | ||
179 | } | ||
180 | |||
181 | client->pdev = pdev; | ||
182 | client->is_ts = is_ts; | ||
183 | client->select_cb = select; | ||
184 | client->convert_cb = conv; | ||
185 | |||
186 | return client; | ||
187 | } | ||
188 | EXPORT_SYMBOL_GPL(s3c_adc_register); | ||
189 | |||
190 | void s3c_adc_release(struct s3c_adc_client *client) | ||
191 | { | ||
192 | /* We should really check that nothing is in progress. */ | ||
193 | kfree(client); | ||
194 | } | ||
195 | EXPORT_SYMBOL_GPL(s3c_adc_release); | ||
196 | |||
197 | static irqreturn_t s3c_adc_irq(int irq, void *pw) | ||
198 | { | ||
199 | struct adc_device *adc = pw; | ||
200 | struct s3c_adc_client *client = adc->cur; | ||
201 | unsigned long flags; | ||
202 | unsigned data0, data1; | ||
203 | |||
204 | if (!client) { | ||
205 | dev_warn(&adc->pdev->dev, "%s: no adc pending\n", __func__); | ||
206 | return IRQ_HANDLED; | ||
207 | } | ||
208 | |||
209 | data0 = readl(adc->regs + S3C2410_ADCDAT0); | ||
210 | data1 = readl(adc->regs + S3C2410_ADCDAT1); | ||
211 | adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1); | ||
212 | |||
213 | (client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff); | ||
214 | |||
215 | if (--client->nr_samples > 0) { | ||
216 | /* fire another conversion for this */ | ||
217 | |||
218 | client->select_cb(1); | ||
219 | s3c_adc_convert(adc); | ||
220 | } else { | ||
221 | local_irq_save(flags); | ||
222 | (client->select_cb)(0); | ||
223 | adc->cur = NULL; | ||
224 | |||
225 | s3c_adc_try(adc); | ||
226 | local_irq_restore(flags); | ||
227 | } | ||
228 | |||
229 | return IRQ_HANDLED; | ||
230 | } | ||
231 | |||
232 | static int s3c_adc_probe(struct platform_device *pdev) | ||
233 | { | ||
234 | struct device *dev = &pdev->dev; | ||
235 | struct adc_device *adc; | ||
236 | struct resource *regs; | ||
237 | int ret; | ||
238 | |||
239 | adc = kzalloc(sizeof(struct adc_device), GFP_KERNEL); | ||
240 | if (adc == NULL) { | ||
241 | dev_err(dev, "failed to allocate adc_device\n"); | ||
242 | return -ENOMEM; | ||
243 | } | ||
244 | |||
245 | adc->pdev = pdev; | ||
246 | adc->prescale = S3C2410_ADCCON_PRSCVL(49); | ||
247 | |||
248 | adc->irq = platform_get_irq(pdev, 1); | ||
249 | if (adc->irq <= 0) { | ||
250 | dev_err(dev, "failed to get adc irq\n"); | ||
251 | ret = -ENOENT; | ||
252 | goto err_alloc; | ||
253 | } | ||
254 | |||
255 | ret = request_irq(adc->irq, s3c_adc_irq, 0, dev_name(dev), adc); | ||
256 | if (ret < 0) { | ||
257 | dev_err(dev, "failed to attach adc irq\n"); | ||
258 | goto err_alloc; | ||
259 | } | ||
260 | |||
261 | adc->clk = clk_get(dev, "adc"); | ||
262 | if (IS_ERR(adc->clk)) { | ||
263 | dev_err(dev, "failed to get adc clock\n"); | ||
264 | ret = PTR_ERR(adc->clk); | ||
265 | goto err_irq; | ||
266 | } | ||
267 | |||
268 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
269 | if (!regs) { | ||
270 | dev_err(dev, "failed to find registers\n"); | ||
271 | ret = -ENXIO; | ||
272 | goto err_clk; | ||
273 | } | ||
274 | |||
275 | adc->regs = ioremap(regs->start, resource_size(regs)); | ||
276 | if (!adc->regs) { | ||
277 | dev_err(dev, "failed to map registers\n"); | ||
278 | ret = -ENXIO; | ||
279 | goto err_clk; | ||
280 | } | ||
281 | |||
282 | clk_enable(adc->clk); | ||
283 | |||
284 | writel(adc->prescale | S3C2410_ADCCON_PRSCEN, | ||
285 | adc->regs + S3C2410_ADCCON); | ||
286 | |||
287 | dev_info(dev, "attached adc driver\n"); | ||
288 | |||
289 | platform_set_drvdata(pdev, adc); | ||
290 | adc_dev = adc; | ||
291 | |||
292 | return 0; | ||
293 | |||
294 | err_clk: | ||
295 | clk_put(adc->clk); | ||
296 | |||
297 | err_irq: | ||
298 | free_irq(adc->irq, adc); | ||
299 | |||
300 | err_alloc: | ||
301 | kfree(adc); | ||
302 | return ret; | ||
303 | } | ||
304 | |||
305 | static int s3c_adc_remove(struct platform_device *pdev) | ||
306 | { | ||
307 | struct adc_device *adc = platform_get_drvdata(pdev); | ||
308 | |||
309 | iounmap(adc->regs); | ||
310 | free_irq(adc->irq, adc); | ||
311 | clk_disable(adc->clk); | ||
312 | clk_put(adc->clk); | ||
313 | kfree(adc); | ||
314 | |||
315 | return 0; | ||
316 | } | ||
317 | |||
318 | #ifdef CONFIG_PM | ||
319 | static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state) | ||
320 | { | ||
321 | struct adc_device *adc = platform_get_drvdata(pdev); | ||
322 | u32 con; | ||
323 | |||
324 | con = readl(adc->regs + S3C2410_ADCCON); | ||
325 | con |= S3C2410_ADCCON_STDBM; | ||
326 | writel(con, adc->regs + S3C2410_ADCCON); | ||
327 | |||
328 | clk_disable(adc->clk); | ||
329 | |||
330 | return 0; | ||
331 | } | ||
332 | |||
333 | static int s3c_adc_resume(struct platform_device *pdev) | ||
334 | { | ||
335 | struct adc_device *adc = platform_get_drvdata(pdev); | ||
336 | |||
337 | clk_enable(adc->clk); | ||
338 | |||
339 | writel(adc->prescale | S3C2410_ADCCON_PRSCEN, | ||
340 | adc->regs + S3C2410_ADCCON); | ||
341 | |||
342 | return 0; | ||
343 | } | ||
344 | |||
345 | #else | ||
346 | #define s3c_adc_suspend NULL | ||
347 | #define s3c_adc_resume NULL | ||
348 | #endif | ||
349 | |||
350 | static struct platform_driver s3c_adc_driver = { | ||
351 | .driver = { | ||
352 | .name = "s3c24xx-adc", | ||
353 | .owner = THIS_MODULE, | ||
354 | }, | ||
355 | .probe = s3c_adc_probe, | ||
356 | .remove = __devexit_p(s3c_adc_remove), | ||
357 | .suspend = s3c_adc_suspend, | ||
358 | .resume = s3c_adc_resume, | ||
359 | }; | ||
360 | |||
361 | static int __init adc_init(void) | ||
362 | { | ||
363 | int ret; | ||
364 | |||
365 | ret = platform_driver_register(&s3c_adc_driver); | ||
366 | if (ret) | ||
367 | printk(KERN_ERR "%s: failed to add adc driver\n", __func__); | ||
368 | |||
369 | return ret; | ||
370 | } | ||
371 | |||
372 | arch_initcall(adc_init); | ||
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c new file mode 100644 index 000000000000..5b75a797b5ab --- /dev/null +++ b/arch/arm/plat-s3c24xx/clock-dclk.c | |||
@@ -0,0 +1,194 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/clock-dclk.c | ||
2 | * | ||
3 | * Copyright (c) 2004,2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | * | ||
11 | * S3C24XX - definitions for DCLK and CLKOUT registers | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/errno.h> | ||
16 | #include <linux/clk.h> | ||
17 | #include <linux/io.h> | ||
18 | |||
19 | #include <mach/regs-clock.h> | ||
20 | #include <mach/regs-gpio.h> | ||
21 | |||
22 | #include <plat/clock.h> | ||
23 | #include <plat/cpu.h> | ||
24 | |||
25 | /* clocks that could be registered by external code */ | ||
26 | |||
27 | static int s3c24xx_dclk_enable(struct clk *clk, int enable) | ||
28 | { | ||
29 | unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON); | ||
30 | |||
31 | if (enable) | ||
32 | dclkcon |= clk->ctrlbit; | ||
33 | else | ||
34 | dclkcon &= ~clk->ctrlbit; | ||
35 | |||
36 | __raw_writel(dclkcon, S3C24XX_DCLKCON); | ||
37 | |||
38 | return 0; | ||
39 | } | ||
40 | |||
41 | static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent) | ||
42 | { | ||
43 | unsigned long dclkcon; | ||
44 | unsigned int uclk; | ||
45 | |||
46 | if (parent == &clk_upll) | ||
47 | uclk = 1; | ||
48 | else if (parent == &clk_p) | ||
49 | uclk = 0; | ||
50 | else | ||
51 | return -EINVAL; | ||
52 | |||
53 | clk->parent = parent; | ||
54 | |||
55 | dclkcon = __raw_readl(S3C24XX_DCLKCON); | ||
56 | |||
57 | if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) { | ||
58 | if (uclk) | ||
59 | dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK; | ||
60 | else | ||
61 | dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK; | ||
62 | } else { | ||
63 | if (uclk) | ||
64 | dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK; | ||
65 | else | ||
66 | dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK; | ||
67 | } | ||
68 | |||
69 | __raw_writel(dclkcon, S3C24XX_DCLKCON); | ||
70 | |||
71 | return 0; | ||
72 | } | ||
73 | static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate) | ||
74 | { | ||
75 | unsigned long div; | ||
76 | |||
77 | if ((rate == 0) || !clk->parent) | ||
78 | return 0; | ||
79 | |||
80 | div = clk_get_rate(clk->parent) / rate; | ||
81 | if (div < 2) | ||
82 | div = 2; | ||
83 | else if (div > 16) | ||
84 | div = 16; | ||
85 | |||
86 | return div; | ||
87 | } | ||
88 | |||
89 | static unsigned long s3c24xx_round_dclk_rate(struct clk *clk, | ||
90 | unsigned long rate) | ||
91 | { | ||
92 | unsigned long div = s3c24xx_calc_div(clk, rate); | ||
93 | |||
94 | if (div == 0) | ||
95 | return 0; | ||
96 | |||
97 | return clk_get_rate(clk->parent) / div; | ||
98 | } | ||
99 | |||
100 | static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate) | ||
101 | { | ||
102 | unsigned long mask, data, div = s3c24xx_calc_div(clk, rate); | ||
103 | |||
104 | if (div == 0) | ||
105 | return -EINVAL; | ||
106 | |||
107 | if (clk == &s3c24xx_dclk0) { | ||
108 | mask = S3C2410_DCLKCON_DCLK0_DIV_MASK | | ||
109 | S3C2410_DCLKCON_DCLK0_CMP_MASK; | ||
110 | data = S3C2410_DCLKCON_DCLK0_DIV(div) | | ||
111 | S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2); | ||
112 | } else if (clk == &s3c24xx_dclk1) { | ||
113 | mask = S3C2410_DCLKCON_DCLK1_DIV_MASK | | ||
114 | S3C2410_DCLKCON_DCLK1_CMP_MASK; | ||
115 | data = S3C2410_DCLKCON_DCLK1_DIV(div) | | ||
116 | S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2); | ||
117 | } else | ||
118 | return -EINVAL; | ||
119 | |||
120 | clk->rate = clk_get_rate(clk->parent) / div; | ||
121 | __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data), | ||
122 | S3C24XX_DCLKCON); | ||
123 | return clk->rate; | ||
124 | } | ||
125 | static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) | ||
126 | { | ||
127 | unsigned long mask; | ||
128 | unsigned long source; | ||
129 | |||
130 | /* calculate the MISCCR setting for the clock */ | ||
131 | |||
132 | if (parent == &clk_xtal) | ||
133 | source = S3C2410_MISCCR_CLK0_MPLL; | ||
134 | else if (parent == &clk_upll) | ||
135 | source = S3C2410_MISCCR_CLK0_UPLL; | ||
136 | else if (parent == &clk_f) | ||
137 | source = S3C2410_MISCCR_CLK0_FCLK; | ||
138 | else if (parent == &clk_h) | ||
139 | source = S3C2410_MISCCR_CLK0_HCLK; | ||
140 | else if (parent == &clk_p) | ||
141 | source = S3C2410_MISCCR_CLK0_PCLK; | ||
142 | else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0) | ||
143 | source = S3C2410_MISCCR_CLK0_DCLK0; | ||
144 | else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1) | ||
145 | source = S3C2410_MISCCR_CLK0_DCLK0; | ||
146 | else | ||
147 | return -EINVAL; | ||
148 | |||
149 | clk->parent = parent; | ||
150 | |||
151 | if (clk == &s3c24xx_clkout0) | ||
152 | mask = S3C2410_MISCCR_CLK0_MASK; | ||
153 | else { | ||
154 | source <<= 4; | ||
155 | mask = S3C2410_MISCCR_CLK1_MASK; | ||
156 | } | ||
157 | |||
158 | s3c2410_modify_misccr(mask, source); | ||
159 | return 0; | ||
160 | } | ||
161 | |||
162 | /* external clock definitions */ | ||
163 | |||
164 | struct clk s3c24xx_dclk0 = { | ||
165 | .name = "dclk0", | ||
166 | .id = -1, | ||
167 | .ctrlbit = S3C2410_DCLKCON_DCLK0EN, | ||
168 | .enable = s3c24xx_dclk_enable, | ||
169 | .set_parent = s3c24xx_dclk_setparent, | ||
170 | .set_rate = s3c24xx_set_dclk_rate, | ||
171 | .round_rate = s3c24xx_round_dclk_rate, | ||
172 | }; | ||
173 | |||
174 | struct clk s3c24xx_dclk1 = { | ||
175 | .name = "dclk1", | ||
176 | .id = -1, | ||
177 | .ctrlbit = S3C2410_DCLKCON_DCLK1EN, | ||
178 | .enable = s3c24xx_dclk_enable, | ||
179 | .set_parent = s3c24xx_dclk_setparent, | ||
180 | .set_rate = s3c24xx_set_dclk_rate, | ||
181 | .round_rate = s3c24xx_round_dclk_rate, | ||
182 | }; | ||
183 | |||
184 | struct clk s3c24xx_clkout0 = { | ||
185 | .name = "clkout0", | ||
186 | .id = -1, | ||
187 | .set_parent = s3c24xx_clkout_setparent, | ||
188 | }; | ||
189 | |||
190 | struct clk s3c24xx_clkout1 = { | ||
191 | .name = "clkout1", | ||
192 | .id = -1, | ||
193 | .set_parent = s3c24xx_clkout_setparent, | ||
194 | }; | ||
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c index a005ddbd9ef3..8474d05274bd 100644 --- a/arch/arm/plat-s3c24xx/clock.c +++ b/arch/arm/plat-s3c24xx/clock.c | |||
@@ -27,18 +27,8 @@ | |||
27 | */ | 27 | */ |
28 | 28 | ||
29 | #include <linux/init.h> | 29 | #include <linux/init.h> |
30 | #include <linux/module.h> | ||
31 | #include <linux/kernel.h> | 30 | #include <linux/kernel.h> |
32 | #include <linux/list.h> | ||
33 | #include <linux/errno.h> | ||
34 | #include <linux/err.h> | ||
35 | #include <linux/platform_device.h> | ||
36 | #include <linux/sysdev.h> | ||
37 | #include <linux/interrupt.h> | ||
38 | #include <linux/ioport.h> | ||
39 | #include <linux/clk.h> | 31 | #include <linux/clk.h> |
40 | #include <linux/mutex.h> | ||
41 | #include <linux/delay.h> | ||
42 | #include <linux/io.h> | 32 | #include <linux/io.h> |
43 | 33 | ||
44 | #include <mach/hardware.h> | 34 | #include <mach/hardware.h> |
@@ -47,490 +37,23 @@ | |||
47 | #include <mach/regs-clock.h> | 37 | #include <mach/regs-clock.h> |
48 | #include <mach/regs-gpio.h> | 38 | #include <mach/regs-gpio.h> |
49 | 39 | ||
40 | #include <plat/cpu-freq.h> | ||
41 | |||
50 | #include <plat/clock.h> | 42 | #include <plat/clock.h> |
51 | #include <plat/cpu.h> | 43 | #include <plat/cpu.h> |
52 | 44 | #include <plat/pll.h> | |
53 | /* clock information */ | ||
54 | |||
55 | static LIST_HEAD(clocks); | ||
56 | |||
57 | DEFINE_MUTEX(clocks_mutex); | ||
58 | |||
59 | /* enable and disable calls for use with the clk struct */ | ||
60 | |||
61 | static int clk_null_enable(struct clk *clk, int enable) | ||
62 | { | ||
63 | return 0; | ||
64 | } | ||
65 | |||
66 | /* Clock API calls */ | ||
67 | |||
68 | struct clk *clk_get(struct device *dev, const char *id) | ||
69 | { | ||
70 | struct clk *p; | ||
71 | struct clk *clk = ERR_PTR(-ENOENT); | ||
72 | int idno; | ||
73 | |||
74 | if (dev == NULL || dev->bus != &platform_bus_type) | ||
75 | idno = -1; | ||
76 | else | ||
77 | idno = to_platform_device(dev)->id; | ||
78 | |||
79 | mutex_lock(&clocks_mutex); | ||
80 | |||
81 | list_for_each_entry(p, &clocks, list) { | ||
82 | if (p->id == idno && | ||
83 | strcmp(id, p->name) == 0 && | ||
84 | try_module_get(p->owner)) { | ||
85 | clk = p; | ||
86 | break; | ||
87 | } | ||
88 | } | ||
89 | |||
90 | /* check for the case where a device was supplied, but the | ||
91 | * clock that was being searched for is not device specific */ | ||
92 | |||
93 | if (IS_ERR(clk)) { | ||
94 | list_for_each_entry(p, &clocks, list) { | ||
95 | if (p->id == -1 && strcmp(id, p->name) == 0 && | ||
96 | try_module_get(p->owner)) { | ||
97 | clk = p; | ||
98 | break; | ||
99 | } | ||
100 | } | ||
101 | } | ||
102 | |||
103 | mutex_unlock(&clocks_mutex); | ||
104 | return clk; | ||
105 | } | ||
106 | |||
107 | void clk_put(struct clk *clk) | ||
108 | { | ||
109 | module_put(clk->owner); | ||
110 | } | ||
111 | |||
112 | int clk_enable(struct clk *clk) | ||
113 | { | ||
114 | if (IS_ERR(clk) || clk == NULL) | ||
115 | return -EINVAL; | ||
116 | |||
117 | clk_enable(clk->parent); | ||
118 | |||
119 | mutex_lock(&clocks_mutex); | ||
120 | |||
121 | if ((clk->usage++) == 0) | ||
122 | (clk->enable)(clk, 1); | ||
123 | |||
124 | mutex_unlock(&clocks_mutex); | ||
125 | return 0; | ||
126 | } | ||
127 | |||
128 | void clk_disable(struct clk *clk) | ||
129 | { | ||
130 | if (IS_ERR(clk) || clk == NULL) | ||
131 | return; | ||
132 | |||
133 | mutex_lock(&clocks_mutex); | ||
134 | |||
135 | if ((--clk->usage) == 0) | ||
136 | (clk->enable)(clk, 0); | ||
137 | |||
138 | mutex_unlock(&clocks_mutex); | ||
139 | clk_disable(clk->parent); | ||
140 | } | ||
141 | |||
142 | |||
143 | unsigned long clk_get_rate(struct clk *clk) | ||
144 | { | ||
145 | if (IS_ERR(clk)) | ||
146 | return 0; | ||
147 | |||
148 | if (clk->rate != 0) | ||
149 | return clk->rate; | ||
150 | |||
151 | if (clk->get_rate != NULL) | ||
152 | return (clk->get_rate)(clk); | ||
153 | |||
154 | if (clk->parent != NULL) | ||
155 | return clk_get_rate(clk->parent); | ||
156 | |||
157 | return clk->rate; | ||
158 | } | ||
159 | |||
160 | long clk_round_rate(struct clk *clk, unsigned long rate) | ||
161 | { | ||
162 | if (!IS_ERR(clk) && clk->round_rate) | ||
163 | return (clk->round_rate)(clk, rate); | ||
164 | |||
165 | return rate; | ||
166 | } | ||
167 | |||
168 | int clk_set_rate(struct clk *clk, unsigned long rate) | ||
169 | { | ||
170 | int ret; | ||
171 | |||
172 | if (IS_ERR(clk)) | ||
173 | return -EINVAL; | ||
174 | |||
175 | /* We do not default just do a clk->rate = rate as | ||
176 | * the clock may have been made this way by choice. | ||
177 | */ | ||
178 | |||
179 | WARN_ON(clk->set_rate == NULL); | ||
180 | |||
181 | if (clk->set_rate == NULL) | ||
182 | return -EINVAL; | ||
183 | |||
184 | mutex_lock(&clocks_mutex); | ||
185 | ret = (clk->set_rate)(clk, rate); | ||
186 | mutex_unlock(&clocks_mutex); | ||
187 | |||
188 | return ret; | ||
189 | } | ||
190 | |||
191 | struct clk *clk_get_parent(struct clk *clk) | ||
192 | { | ||
193 | return clk->parent; | ||
194 | } | ||
195 | |||
196 | int clk_set_parent(struct clk *clk, struct clk *parent) | ||
197 | { | ||
198 | int ret = 0; | ||
199 | |||
200 | if (IS_ERR(clk)) | ||
201 | return -EINVAL; | ||
202 | |||
203 | mutex_lock(&clocks_mutex); | ||
204 | |||
205 | if (clk->set_parent) | ||
206 | ret = (clk->set_parent)(clk, parent); | ||
207 | |||
208 | mutex_unlock(&clocks_mutex); | ||
209 | |||
210 | return ret; | ||
211 | } | ||
212 | |||
213 | EXPORT_SYMBOL(clk_get); | ||
214 | EXPORT_SYMBOL(clk_put); | ||
215 | EXPORT_SYMBOL(clk_enable); | ||
216 | EXPORT_SYMBOL(clk_disable); | ||
217 | EXPORT_SYMBOL(clk_get_rate); | ||
218 | EXPORT_SYMBOL(clk_round_rate); | ||
219 | EXPORT_SYMBOL(clk_set_rate); | ||
220 | EXPORT_SYMBOL(clk_get_parent); | ||
221 | EXPORT_SYMBOL(clk_set_parent); | ||
222 | |||
223 | /* base clocks */ | ||
224 | |||
225 | static int clk_default_setrate(struct clk *clk, unsigned long rate) | ||
226 | { | ||
227 | clk->rate = rate; | ||
228 | return 0; | ||
229 | } | ||
230 | |||
231 | struct clk clk_xtal = { | ||
232 | .name = "xtal", | ||
233 | .id = -1, | ||
234 | .rate = 0, | ||
235 | .parent = NULL, | ||
236 | .ctrlbit = 0, | ||
237 | }; | ||
238 | |||
239 | struct clk clk_mpll = { | ||
240 | .name = "mpll", | ||
241 | .id = -1, | ||
242 | .set_rate = clk_default_setrate, | ||
243 | }; | ||
244 | |||
245 | struct clk clk_upll = { | ||
246 | .name = "upll", | ||
247 | .id = -1, | ||
248 | .parent = NULL, | ||
249 | .ctrlbit = 0, | ||
250 | }; | ||
251 | |||
252 | struct clk clk_f = { | ||
253 | .name = "fclk", | ||
254 | .id = -1, | ||
255 | .rate = 0, | ||
256 | .parent = &clk_mpll, | ||
257 | .ctrlbit = 0, | ||
258 | .set_rate = clk_default_setrate, | ||
259 | }; | ||
260 | |||
261 | struct clk clk_h = { | ||
262 | .name = "hclk", | ||
263 | .id = -1, | ||
264 | .rate = 0, | ||
265 | .parent = NULL, | ||
266 | .ctrlbit = 0, | ||
267 | .set_rate = clk_default_setrate, | ||
268 | }; | ||
269 | |||
270 | struct clk clk_p = { | ||
271 | .name = "pclk", | ||
272 | .id = -1, | ||
273 | .rate = 0, | ||
274 | .parent = NULL, | ||
275 | .ctrlbit = 0, | ||
276 | .set_rate = clk_default_setrate, | ||
277 | }; | ||
278 | |||
279 | struct clk clk_usb_bus = { | ||
280 | .name = "usb-bus", | ||
281 | .id = -1, | ||
282 | .rate = 0, | ||
283 | .parent = &clk_upll, | ||
284 | }; | ||
285 | |||
286 | /* clocks that could be registered by external code */ | ||
287 | |||
288 | static int s3c24xx_dclk_enable(struct clk *clk, int enable) | ||
289 | { | ||
290 | unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON); | ||
291 | |||
292 | if (enable) | ||
293 | dclkcon |= clk->ctrlbit; | ||
294 | else | ||
295 | dclkcon &= ~clk->ctrlbit; | ||
296 | |||
297 | __raw_writel(dclkcon, S3C24XX_DCLKCON); | ||
298 | |||
299 | return 0; | ||
300 | } | ||
301 | |||
302 | static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent) | ||
303 | { | ||
304 | unsigned long dclkcon; | ||
305 | unsigned int uclk; | ||
306 | |||
307 | if (parent == &clk_upll) | ||
308 | uclk = 1; | ||
309 | else if (parent == &clk_p) | ||
310 | uclk = 0; | ||
311 | else | ||
312 | return -EINVAL; | ||
313 | |||
314 | clk->parent = parent; | ||
315 | |||
316 | dclkcon = __raw_readl(S3C24XX_DCLKCON); | ||
317 | |||
318 | if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) { | ||
319 | if (uclk) | ||
320 | dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK; | ||
321 | else | ||
322 | dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK; | ||
323 | } else { | ||
324 | if (uclk) | ||
325 | dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK; | ||
326 | else | ||
327 | dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK; | ||
328 | } | ||
329 | |||
330 | __raw_writel(dclkcon, S3C24XX_DCLKCON); | ||
331 | |||
332 | return 0; | ||
333 | } | ||
334 | |||
335 | static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate) | ||
336 | { | ||
337 | unsigned long div; | ||
338 | |||
339 | if ((rate == 0) || !clk->parent) | ||
340 | return 0; | ||
341 | |||
342 | div = clk_get_rate(clk->parent) / rate; | ||
343 | if (div < 2) | ||
344 | div = 2; | ||
345 | else if (div > 16) | ||
346 | div = 16; | ||
347 | |||
348 | return div; | ||
349 | } | ||
350 | |||
351 | static unsigned long s3c24xx_round_dclk_rate(struct clk *clk, | ||
352 | unsigned long rate) | ||
353 | { | ||
354 | unsigned long div = s3c24xx_calc_div(clk, rate); | ||
355 | |||
356 | if (div == 0) | ||
357 | return 0; | ||
358 | |||
359 | return clk_get_rate(clk->parent) / div; | ||
360 | } | ||
361 | |||
362 | static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate) | ||
363 | { | ||
364 | unsigned long mask, data, div = s3c24xx_calc_div(clk, rate); | ||
365 | |||
366 | if (div == 0) | ||
367 | return -EINVAL; | ||
368 | |||
369 | if (clk == &s3c24xx_dclk0) { | ||
370 | mask = S3C2410_DCLKCON_DCLK0_DIV_MASK | | ||
371 | S3C2410_DCLKCON_DCLK0_CMP_MASK; | ||
372 | data = S3C2410_DCLKCON_DCLK0_DIV(div) | | ||
373 | S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2); | ||
374 | } else if (clk == &s3c24xx_dclk1) { | ||
375 | mask = S3C2410_DCLKCON_DCLK1_DIV_MASK | | ||
376 | S3C2410_DCLKCON_DCLK1_CMP_MASK; | ||
377 | data = S3C2410_DCLKCON_DCLK1_DIV(div) | | ||
378 | S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2); | ||
379 | } else | ||
380 | return -EINVAL; | ||
381 | |||
382 | clk->rate = clk_get_rate(clk->parent) / div; | ||
383 | __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data), | ||
384 | S3C24XX_DCLKCON); | ||
385 | return clk->rate; | ||
386 | } | ||
387 | |||
388 | static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent) | ||
389 | { | ||
390 | unsigned long mask; | ||
391 | unsigned long source; | ||
392 | |||
393 | /* calculate the MISCCR setting for the clock */ | ||
394 | |||
395 | if (parent == &clk_xtal) | ||
396 | source = S3C2410_MISCCR_CLK0_MPLL; | ||
397 | else if (parent == &clk_upll) | ||
398 | source = S3C2410_MISCCR_CLK0_UPLL; | ||
399 | else if (parent == &clk_f) | ||
400 | source = S3C2410_MISCCR_CLK0_FCLK; | ||
401 | else if (parent == &clk_h) | ||
402 | source = S3C2410_MISCCR_CLK0_HCLK; | ||
403 | else if (parent == &clk_p) | ||
404 | source = S3C2410_MISCCR_CLK0_PCLK; | ||
405 | else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0) | ||
406 | source = S3C2410_MISCCR_CLK0_DCLK0; | ||
407 | else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1) | ||
408 | source = S3C2410_MISCCR_CLK0_DCLK0; | ||
409 | else | ||
410 | return -EINVAL; | ||
411 | |||
412 | clk->parent = parent; | ||
413 | |||
414 | if (clk == &s3c24xx_clkout0) | ||
415 | mask = S3C2410_MISCCR_CLK0_MASK; | ||
416 | else { | ||
417 | source <<= 4; | ||
418 | mask = S3C2410_MISCCR_CLK1_MASK; | ||
419 | } | ||
420 | |||
421 | s3c2410_modify_misccr(mask, source); | ||
422 | return 0; | ||
423 | } | ||
424 | |||
425 | /* external clock definitions */ | ||
426 | |||
427 | struct clk s3c24xx_dclk0 = { | ||
428 | .name = "dclk0", | ||
429 | .id = -1, | ||
430 | .ctrlbit = S3C2410_DCLKCON_DCLK0EN, | ||
431 | .enable = s3c24xx_dclk_enable, | ||
432 | .set_parent = s3c24xx_dclk_setparent, | ||
433 | .set_rate = s3c24xx_set_dclk_rate, | ||
434 | .round_rate = s3c24xx_round_dclk_rate, | ||
435 | }; | ||
436 | |||
437 | struct clk s3c24xx_dclk1 = { | ||
438 | .name = "dclk1", | ||
439 | .id = -1, | ||
440 | .ctrlbit = S3C2410_DCLKCON_DCLK1EN, | ||
441 | .enable = s3c24xx_dclk_enable, | ||
442 | .set_parent = s3c24xx_dclk_setparent, | ||
443 | .set_rate = s3c24xx_set_dclk_rate, | ||
444 | .round_rate = s3c24xx_round_dclk_rate, | ||
445 | }; | ||
446 | |||
447 | struct clk s3c24xx_clkout0 = { | ||
448 | .name = "clkout0", | ||
449 | .id = -1, | ||
450 | .set_parent = s3c24xx_clkout_setparent, | ||
451 | }; | ||
452 | |||
453 | struct clk s3c24xx_clkout1 = { | ||
454 | .name = "clkout1", | ||
455 | .id = -1, | ||
456 | .set_parent = s3c24xx_clkout_setparent, | ||
457 | }; | ||
458 | |||
459 | struct clk s3c24xx_uclk = { | ||
460 | .name = "uclk", | ||
461 | .id = -1, | ||
462 | }; | ||
463 | |||
464 | /* initialise the clock system */ | ||
465 | |||
466 | int s3c24xx_register_clock(struct clk *clk) | ||
467 | { | ||
468 | clk->owner = THIS_MODULE; | ||
469 | |||
470 | if (clk->enable == NULL) | ||
471 | clk->enable = clk_null_enable; | ||
472 | |||
473 | /* add to the list of available clocks */ | ||
474 | |||
475 | mutex_lock(&clocks_mutex); | ||
476 | list_add(&clk->list, &clocks); | ||
477 | mutex_unlock(&clocks_mutex); | ||
478 | |||
479 | return 0; | ||
480 | } | ||
481 | |||
482 | int s3c24xx_register_clocks(struct clk **clks, int nr_clks) | ||
483 | { | ||
484 | int fails = 0; | ||
485 | |||
486 | for (; nr_clks > 0; nr_clks--, clks++) { | ||
487 | if (s3c24xx_register_clock(*clks) < 0) | ||
488 | fails++; | ||
489 | } | ||
490 | |||
491 | return fails; | ||
492 | } | ||
493 | 45 | ||
494 | /* initalise all the clocks */ | 46 | /* initalise all the clocks */ |
495 | 47 | ||
496 | int __init s3c24xx_setup_clocks(unsigned long xtal, | 48 | void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk, |
497 | unsigned long fclk, | 49 | unsigned long hclk, |
498 | unsigned long hclk, | 50 | unsigned long pclk) |
499 | unsigned long pclk) | ||
500 | { | 51 | { |
501 | printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); | 52 | clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), |
502 | 53 | clk_xtal.rate); | |
503 | /* initialise the main system clocks */ | ||
504 | |||
505 | clk_xtal.rate = xtal; | ||
506 | clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal); | ||
507 | 54 | ||
508 | clk_mpll.rate = fclk; | 55 | clk_mpll.rate = fclk; |
509 | clk_h.rate = hclk; | 56 | clk_h.rate = hclk; |
510 | clk_p.rate = pclk; | 57 | clk_p.rate = pclk; |
511 | clk_f.rate = fclk; | 58 | clk_f.rate = fclk; |
512 | |||
513 | /* assume uart clocks are correctly setup */ | ||
514 | |||
515 | /* register our clocks */ | ||
516 | |||
517 | if (s3c24xx_register_clock(&clk_xtal) < 0) | ||
518 | printk(KERN_ERR "failed to register master xtal\n"); | ||
519 | |||
520 | if (s3c24xx_register_clock(&clk_mpll) < 0) | ||
521 | printk(KERN_ERR "failed to register mpll clock\n"); | ||
522 | |||
523 | if (s3c24xx_register_clock(&clk_upll) < 0) | ||
524 | printk(KERN_ERR "failed to register upll clock\n"); | ||
525 | |||
526 | if (s3c24xx_register_clock(&clk_f) < 0) | ||
527 | printk(KERN_ERR "failed to register cpu fclk\n"); | ||
528 | |||
529 | if (s3c24xx_register_clock(&clk_h) < 0) | ||
530 | printk(KERN_ERR "failed to register cpu hclk\n"); | ||
531 | |||
532 | if (s3c24xx_register_clock(&clk_p) < 0) | ||
533 | printk(KERN_ERR "failed to register cpu pclk\n"); | ||
534 | |||
535 | return 0; | ||
536 | } | 59 | } |
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c index 22a329513c0f..542062f8cbc1 100644 --- a/arch/arm/plat-s3c24xx/cpu.c +++ b/arch/arm/plat-s3c24xx/cpu.c | |||
@@ -30,7 +30,6 @@ | |||
30 | #include <linux/platform_device.h> | 30 | #include <linux/platform_device.h> |
31 | #include <linux/delay.h> | 31 | #include <linux/delay.h> |
32 | #include <linux/io.h> | 32 | #include <linux/io.h> |
33 | #include <linux/delay.h> | ||
34 | 33 | ||
35 | #include <mach/hardware.h> | 34 | #include <mach/hardware.h> |
36 | #include <asm/irq.h> | 35 | #include <asm/irq.h> |
@@ -55,16 +54,6 @@ | |||
55 | #include <plat/s3c2442.h> | 54 | #include <plat/s3c2442.h> |
56 | #include <plat/s3c2443.h> | 55 | #include <plat/s3c2443.h> |
57 | 56 | ||
58 | struct cpu_table { | ||
59 | unsigned long idcode; | ||
60 | unsigned long idmask; | ||
61 | void (*map_io)(struct map_desc *mach_desc, int size); | ||
62 | void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no); | ||
63 | void (*init_clocks)(int xtal); | ||
64 | int (*init)(void); | ||
65 | const char *name; | ||
66 | }; | ||
67 | |||
68 | /* table of supported CPUs */ | 57 | /* table of supported CPUs */ |
69 | 58 | ||
70 | static const char name_s3c2400[] = "S3C2400"; | 59 | static const char name_s3c2400[] = "S3C2400"; |
@@ -169,23 +158,7 @@ static struct map_desc s3c_iodesc[] __initdata = { | |||
169 | IODESC_ENT(UART) | 158 | IODESC_ENT(UART) |
170 | }; | 159 | }; |
171 | 160 | ||
172 | static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode) | 161 | /* read cpu identificaiton code */ |
173 | { | ||
174 | struct cpu_table *tab; | ||
175 | int count; | ||
176 | |||
177 | tab = cpu_ids; | ||
178 | for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) { | ||
179 | if ((idcode & tab->idmask) == tab->idcode) | ||
180 | return tab; | ||
181 | } | ||
182 | |||
183 | return NULL; | ||
184 | } | ||
185 | |||
186 | /* cpu information */ | ||
187 | |||
188 | static struct cpu_table *cpu; | ||
189 | 162 | ||
190 | static unsigned long s3c24xx_read_idcode_v5(void) | 163 | static unsigned long s3c24xx_read_idcode_v5(void) |
191 | { | 164 | { |
@@ -231,6 +204,7 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) | |||
231 | unsigned long idcode = 0x0; | 204 | unsigned long idcode = 0x0; |
232 | 205 | ||
233 | /* initialise the io descriptors we need for initialisation */ | 206 | /* initialise the io descriptors we need for initialisation */ |
207 | iotable_init(mach_desc, size); | ||
234 | iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); | 208 | iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); |
235 | 209 | ||
236 | if (cpu_architecture() >= CPU_ARCH_ARMv5) { | 210 | if (cpu_architecture() >= CPU_ARCH_ARMv5) { |
@@ -239,117 +213,7 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) | |||
239 | idcode = s3c24xx_read_idcode_v4(); | 213 | idcode = s3c24xx_read_idcode_v4(); |
240 | } | 214 | } |
241 | 215 | ||
242 | cpu = s3c_lookup_cpu(idcode); | ||
243 | |||
244 | if (cpu == NULL) { | ||
245 | printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode); | ||
246 | panic("Unknown S3C24XX CPU"); | ||
247 | } | ||
248 | |||
249 | printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode); | ||
250 | |||
251 | if (cpu->map_io == NULL || cpu->init == NULL) { | ||
252 | printk(KERN_ERR "CPU %s support not enabled\n", cpu->name); | ||
253 | panic("Unsupported S3C24XX CPU"); | ||
254 | } | ||
255 | |||
256 | arm_pm_restart = s3c24xx_pm_restart; | 216 | arm_pm_restart = s3c24xx_pm_restart; |
257 | 217 | ||
258 | (cpu->map_io)(mach_desc, size); | 218 | s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); |
259 | } | ||
260 | |||
261 | /* s3c24xx_init_clocks | ||
262 | * | ||
263 | * Initialise the clock subsystem and associated information from the | ||
264 | * given master crystal value. | ||
265 | * | ||
266 | * xtal = 0 -> use default PLL crystal value (normally 12MHz) | ||
267 | * != 0 -> PLL crystal value in Hz | ||
268 | */ | ||
269 | |||
270 | void __init s3c24xx_init_clocks(int xtal) | ||
271 | { | ||
272 | if (xtal == 0) | ||
273 | xtal = 12*1000*1000; | ||
274 | |||
275 | if (cpu == NULL) | ||
276 | panic("s3c24xx_init_clocks: no cpu setup?\n"); | ||
277 | |||
278 | if (cpu->init_clocks == NULL) | ||
279 | panic("s3c24xx_init_clocks: cpu has no clock init\n"); | ||
280 | else | ||
281 | (cpu->init_clocks)(xtal); | ||
282 | } | 219 | } |
283 | |||
284 | /* uart management */ | ||
285 | |||
286 | static int nr_uarts __initdata = 0; | ||
287 | |||
288 | static struct s3c2410_uartcfg uart_cfgs[3]; | ||
289 | |||
290 | /* s3c24xx_init_uartdevs | ||
291 | * | ||
292 | * copy the specified platform data and configuration into our central | ||
293 | * set of devices, before the data is thrown away after the init process. | ||
294 | * | ||
295 | * This also fills in the array passed to the serial driver for the | ||
296 | * early initialisation of the console. | ||
297 | */ | ||
298 | |||
299 | void __init s3c24xx_init_uartdevs(char *name, | ||
300 | struct s3c24xx_uart_resources *res, | ||
301 | struct s3c2410_uartcfg *cfg, int no) | ||
302 | { | ||
303 | struct platform_device *platdev; | ||
304 | struct s3c2410_uartcfg *cfgptr = uart_cfgs; | ||
305 | struct s3c24xx_uart_resources *resp; | ||
306 | int uart; | ||
307 | |||
308 | memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no); | ||
309 | |||
310 | for (uart = 0; uart < no; uart++, cfg++, cfgptr++) { | ||
311 | platdev = s3c24xx_uart_src[cfgptr->hwport]; | ||
312 | |||
313 | resp = res + cfgptr->hwport; | ||
314 | |||
315 | s3c24xx_uart_devs[uart] = platdev; | ||
316 | |||
317 | platdev->name = name; | ||
318 | platdev->resource = resp->resources; | ||
319 | platdev->num_resources = resp->nr_resources; | ||
320 | |||
321 | platdev->dev.platform_data = cfgptr; | ||
322 | } | ||
323 | |||
324 | nr_uarts = no; | ||
325 | } | ||
326 | |||
327 | void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) | ||
328 | { | ||
329 | if (cpu == NULL) | ||
330 | return; | ||
331 | |||
332 | if (cpu->init_uarts == NULL) { | ||
333 | printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n"); | ||
334 | } else | ||
335 | (cpu->init_uarts)(cfg, no); | ||
336 | } | ||
337 | |||
338 | static int __init s3c_arch_init(void) | ||
339 | { | ||
340 | int ret; | ||
341 | |||
342 | // do the correct init for cpu | ||
343 | |||
344 | if (cpu == NULL) | ||
345 | panic("s3c_arch_init: NULL cpu\n"); | ||
346 | |||
347 | ret = (cpu->init)(); | ||
348 | if (ret != 0) | ||
349 | return ret; | ||
350 | |||
351 | ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts); | ||
352 | return ret; | ||
353 | } | ||
354 | |||
355 | arch_initcall(s3c_arch_init); | ||
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index adf535aaf43a..16ac01d9b8ab 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c | |||
@@ -76,6 +76,19 @@ static struct resource s3c2410_uart2_resource[] = { | |||
76 | } | 76 | } |
77 | }; | 77 | }; |
78 | 78 | ||
79 | static struct resource s3c2410_uart3_resource[] = { | ||
80 | [0] = { | ||
81 | .start = S3C2443_PA_UART3, | ||
82 | .end = S3C2443_PA_UART3 + 0x3fff, | ||
83 | .flags = IORESOURCE_MEM, | ||
84 | }, | ||
85 | [1] = { | ||
86 | .start = IRQ_S3CUART_RX3, | ||
87 | .end = IRQ_S3CUART_ERR3, | ||
88 | .flags = IORESOURCE_IRQ, | ||
89 | }, | ||
90 | }; | ||
91 | |||
79 | struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { | 92 | struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { |
80 | [0] = { | 93 | [0] = { |
81 | .resources = s3c2410_uart0_resource, | 94 | .resources = s3c2410_uart0_resource, |
@@ -89,6 +102,10 @@ struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = { | |||
89 | .resources = s3c2410_uart2_resource, | 102 | .resources = s3c2410_uart2_resource, |
90 | .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource), | 103 | .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource), |
91 | }, | 104 | }, |
105 | [3] = { | ||
106 | .resources = s3c2410_uart3_resource, | ||
107 | .nr_resources = ARRAY_SIZE(s3c2410_uart3_resource), | ||
108 | }, | ||
92 | }; | 109 | }; |
93 | 110 | ||
94 | /* yart devices */ | 111 | /* yart devices */ |
@@ -105,13 +122,18 @@ static struct platform_device s3c24xx_uart_device2 = { | |||
105 | .id = 2, | 122 | .id = 2, |
106 | }; | 123 | }; |
107 | 124 | ||
108 | struct platform_device *s3c24xx_uart_src[3] = { | 125 | static struct platform_device s3c24xx_uart_device3 = { |
126 | .id = 3, | ||
127 | }; | ||
128 | |||
129 | struct platform_device *s3c24xx_uart_src[4] = { | ||
109 | &s3c24xx_uart_device0, | 130 | &s3c24xx_uart_device0, |
110 | &s3c24xx_uart_device1, | 131 | &s3c24xx_uart_device1, |
111 | &s3c24xx_uart_device2, | 132 | &s3c24xx_uart_device2, |
133 | &s3c24xx_uart_device3, | ||
112 | }; | 134 | }; |
113 | 135 | ||
114 | struct platform_device *s3c24xx_uart_devs[3] = { | 136 | struct platform_device *s3c24xx_uart_devs[4] = { |
115 | }; | 137 | }; |
116 | 138 | ||
117 | /* USB Host Controller */ | 139 | /* USB Host Controller */ |
@@ -192,8 +214,8 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd) | |||
192 | 214 | ||
193 | static struct resource s3c_nand_resource[] = { | 215 | static struct resource s3c_nand_resource[] = { |
194 | [0] = { | 216 | [0] = { |
195 | .start = S3C2410_PA_NAND, | 217 | .start = S3C24XX_PA_NAND, |
196 | .end = S3C2410_PA_NAND + S3C24XX_SZ_NAND - 1, | 218 | .end = S3C24XX_PA_NAND + S3C24XX_SZ_NAND - 1, |
197 | .flags = IORESOURCE_MEM, | 219 | .flags = IORESOURCE_MEM, |
198 | } | 220 | } |
199 | }; | 221 | }; |
@@ -271,31 +293,6 @@ struct platform_device s3c_device_wdt = { | |||
271 | 293 | ||
272 | EXPORT_SYMBOL(s3c_device_wdt); | 294 | EXPORT_SYMBOL(s3c_device_wdt); |
273 | 295 | ||
274 | /* I2C */ | ||
275 | |||
276 | static struct resource s3c_i2c_resource[] = { | ||
277 | [0] = { | ||
278 | .start = S3C24XX_PA_IIC, | ||
279 | .end = S3C24XX_PA_IIC + S3C24XX_SZ_IIC - 1, | ||
280 | .flags = IORESOURCE_MEM, | ||
281 | }, | ||
282 | [1] = { | ||
283 | .start = IRQ_IIC, | ||
284 | .end = IRQ_IIC, | ||
285 | .flags = IORESOURCE_IRQ, | ||
286 | } | ||
287 | |||
288 | }; | ||
289 | |||
290 | struct platform_device s3c_device_i2c = { | ||
291 | .name = "s3c2410-i2c", | ||
292 | .id = -1, | ||
293 | .num_resources = ARRAY_SIZE(s3c_i2c_resource), | ||
294 | .resource = s3c_i2c_resource, | ||
295 | }; | ||
296 | |||
297 | EXPORT_SYMBOL(s3c_device_i2c); | ||
298 | |||
299 | /* IIS */ | 296 | /* IIS */ |
300 | 297 | ||
301 | static struct resource s3c_iis_resource[] = { | 298 | static struct resource s3c_iis_resource[] = { |
@@ -372,18 +369,26 @@ static struct resource s3c_adc_resource[] = { | |||
372 | }; | 369 | }; |
373 | 370 | ||
374 | struct platform_device s3c_device_adc = { | 371 | struct platform_device s3c_device_adc = { |
375 | .name = "s3c2410-adc", | 372 | .name = "s3c24xx-adc", |
376 | .id = -1, | 373 | .id = -1, |
377 | .num_resources = ARRAY_SIZE(s3c_adc_resource), | 374 | .num_resources = ARRAY_SIZE(s3c_adc_resource), |
378 | .resource = s3c_adc_resource, | 375 | .resource = s3c_adc_resource, |
379 | }; | 376 | }; |
380 | 377 | ||
378 | /* HWMON */ | ||
379 | |||
380 | struct platform_device s3c_device_hwmon = { | ||
381 | .name = "s3c24xx-hwmon", | ||
382 | .id = -1, | ||
383 | .dev.parent = &s3c_device_adc.dev, | ||
384 | }; | ||
385 | |||
381 | /* SDI */ | 386 | /* SDI */ |
382 | 387 | ||
383 | static struct resource s3c_sdi_resource[] = { | 388 | static struct resource s3c_sdi_resource[] = { |
384 | [0] = { | 389 | [0] = { |
385 | .start = S3C2410_PA_SDI, | 390 | .start = S3C24XX_PA_SDI, |
386 | .end = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1, | 391 | .end = S3C24XX_PA_SDI + S3C24XX_SZ_SDI - 1, |
387 | .flags = IORESOURCE_MEM, | 392 | .flags = IORESOURCE_MEM, |
388 | }, | 393 | }, |
389 | [1] = { | 394 | [1] = { |
@@ -403,36 +408,6 @@ struct platform_device s3c_device_sdi = { | |||
403 | 408 | ||
404 | EXPORT_SYMBOL(s3c_device_sdi); | 409 | EXPORT_SYMBOL(s3c_device_sdi); |
405 | 410 | ||
406 | /* High-speed MMC/SD */ | ||
407 | |||
408 | static struct resource s3c_hsmmc_resource[] = { | ||
409 | [0] = { | ||
410 | .start = S3C2443_PA_HSMMC, | ||
411 | .end = S3C2443_PA_HSMMC + S3C2443_SZ_HSMMC - 1, | ||
412 | .flags = IORESOURCE_MEM, | ||
413 | }, | ||
414 | [1] = { | ||
415 | .start = IRQ_S3C2443_HSMMC, | ||
416 | .end = IRQ_S3C2443_HSMMC, | ||
417 | .flags = IORESOURCE_IRQ, | ||
418 | } | ||
419 | }; | ||
420 | |||
421 | static u64 s3c_device_hsmmc_dmamask = 0xffffffffUL; | ||
422 | |||
423 | struct platform_device s3c_device_hsmmc = { | ||
424 | .name = "s3c-sdhci", | ||
425 | .id = -1, | ||
426 | .num_resources = ARRAY_SIZE(s3c_hsmmc_resource), | ||
427 | .resource = s3c_hsmmc_resource, | ||
428 | .dev = { | ||
429 | .dma_mask = &s3c_device_hsmmc_dmamask, | ||
430 | .coherent_dma_mask = 0xffffffffUL | ||
431 | } | ||
432 | }; | ||
433 | |||
434 | |||
435 | |||
436 | /* SPI (0) */ | 411 | /* SPI (0) */ |
437 | 412 | ||
438 | static struct resource s3c_spi0_resource[] = { | 413 | static struct resource s3c_spi0_resource[] = { |
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index 63bb22b973e3..aee2aeb46c60 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c | |||
@@ -25,7 +25,6 @@ | |||
25 | #include <linux/sysdev.h> | 25 | #include <linux/sysdev.h> |
26 | #include <linux/slab.h> | 26 | #include <linux/slab.h> |
27 | #include <linux/errno.h> | 27 | #include <linux/errno.h> |
28 | #include <linux/delay.h> | ||
29 | #include <linux/io.h> | 28 | #include <linux/io.h> |
30 | 29 | ||
31 | #include <asm/system.h> | 30 | #include <asm/system.h> |
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c index 3caec6bad3eb..f95c6c9d9f1a 100644 --- a/arch/arm/plat-s3c24xx/gpiolib.c +++ b/arch/arm/plat-s3c24xx/gpiolib.c | |||
@@ -19,104 +19,12 @@ | |||
19 | #include <linux/io.h> | 19 | #include <linux/io.h> |
20 | #include <linux/gpio.h> | 20 | #include <linux/gpio.h> |
21 | 21 | ||
22 | #include <plat/gpio-core.h> | ||
22 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
23 | #include <asm/irq.h> | 24 | #include <asm/irq.h> |
24 | 25 | ||
25 | #include <mach/regs-gpio.h> | 26 | #include <mach/regs-gpio.h> |
26 | 27 | ||
27 | struct s3c24xx_gpio_chip { | ||
28 | struct gpio_chip chip; | ||
29 | void __iomem *base; | ||
30 | }; | ||
31 | |||
32 | static inline struct s3c24xx_gpio_chip *to_s3c_chip(struct gpio_chip *gpc) | ||
33 | { | ||
34 | return container_of(gpc, struct s3c24xx_gpio_chip, chip); | ||
35 | } | ||
36 | |||
37 | /* these routines are exported for use by other parts of the platform | ||
38 | * and system support, but are not intended to be used directly by the | ||
39 | * drivers themsevles. | ||
40 | */ | ||
41 | |||
42 | static int s3c24xx_gpiolib_input(struct gpio_chip *chip, unsigned offset) | ||
43 | { | ||
44 | struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); | ||
45 | void __iomem *base = ourchip->base; | ||
46 | unsigned long flags; | ||
47 | unsigned long con; | ||
48 | |||
49 | local_irq_save(flags); | ||
50 | |||
51 | con = __raw_readl(base + 0x00); | ||
52 | con &= ~(3 << (offset * 2)); | ||
53 | con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2); | ||
54 | |||
55 | __raw_writel(con, base + 0x00); | ||
56 | |||
57 | local_irq_restore(flags); | ||
58 | return 0; | ||
59 | } | ||
60 | |||
61 | static int s3c24xx_gpiolib_output(struct gpio_chip *chip, | ||
62 | unsigned offset, int value) | ||
63 | { | ||
64 | struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); | ||
65 | void __iomem *base = ourchip->base; | ||
66 | unsigned long flags; | ||
67 | unsigned long dat; | ||
68 | unsigned long con; | ||
69 | |||
70 | local_irq_save(flags); | ||
71 | |||
72 | dat = __raw_readl(base + 0x04); | ||
73 | dat &= ~(1 << offset); | ||
74 | if (value) | ||
75 | dat |= 1 << offset; | ||
76 | __raw_writel(dat, base + 0x04); | ||
77 | |||
78 | con = __raw_readl(base + 0x00); | ||
79 | con &= ~(3 << (offset * 2)); | ||
80 | con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2); | ||
81 | |||
82 | __raw_writel(con, base + 0x00); | ||
83 | __raw_writel(dat, base + 0x04); | ||
84 | |||
85 | local_irq_restore(flags); | ||
86 | return 0; | ||
87 | } | ||
88 | |||
89 | static void s3c24xx_gpiolib_set(struct gpio_chip *chip, | ||
90 | unsigned offset, int value) | ||
91 | { | ||
92 | struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); | ||
93 | void __iomem *base = ourchip->base; | ||
94 | unsigned long flags; | ||
95 | unsigned long dat; | ||
96 | |||
97 | local_irq_save(flags); | ||
98 | |||
99 | dat = __raw_readl(base + 0x04); | ||
100 | dat &= ~(1 << offset); | ||
101 | if (value) | ||
102 | dat |= 1 << offset; | ||
103 | __raw_writel(dat, base + 0x04); | ||
104 | |||
105 | local_irq_restore(flags); | ||
106 | } | ||
107 | |||
108 | static int s3c24xx_gpiolib_get(struct gpio_chip *chip, unsigned offset) | ||
109 | { | ||
110 | struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); | ||
111 | unsigned long val; | ||
112 | |||
113 | val = __raw_readl(ourchip->base + 0x04); | ||
114 | val >>= offset; | ||
115 | val &= 1; | ||
116 | |||
117 | return val; | ||
118 | } | ||
119 | |||
120 | static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset) | 28 | static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset) |
121 | { | 29 | { |
122 | return -EINVAL; | 30 | return -EINVAL; |
@@ -125,7 +33,7 @@ static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset) | |||
125 | static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip, | 33 | static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip, |
126 | unsigned offset, int value) | 34 | unsigned offset, int value) |
127 | { | 35 | { |
128 | struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip); | 36 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); |
129 | void __iomem *base = ourchip->base; | 37 | void __iomem *base = ourchip->base; |
130 | unsigned long flags; | 38 | unsigned long flags; |
131 | unsigned long dat; | 39 | unsigned long dat; |
@@ -151,7 +59,7 @@ static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip, | |||
151 | return 0; | 59 | return 0; |
152 | } | 60 | } |
153 | 61 | ||
154 | static struct s3c24xx_gpio_chip gpios[] = { | 62 | struct s3c_gpio_chip s3c24xx_gpios[] = { |
155 | [0] = { | 63 | [0] = { |
156 | .base = S3C24XX_GPIO_BASE(S3C2410_GPA0), | 64 | .base = S3C24XX_GPIO_BASE(S3C2410_GPA0), |
157 | .chip = { | 65 | .chip = { |
@@ -161,8 +69,6 @@ static struct s3c24xx_gpio_chip gpios[] = { | |||
161 | .ngpio = 24, | 69 | .ngpio = 24, |
162 | .direction_input = s3c24xx_gpiolib_banka_input, | 70 | .direction_input = s3c24xx_gpiolib_banka_input, |
163 | .direction_output = s3c24xx_gpiolib_banka_output, | 71 | .direction_output = s3c24xx_gpiolib_banka_output, |
164 | .set = s3c24xx_gpiolib_set, | ||
165 | .get = s3c24xx_gpiolib_get, | ||
166 | }, | 72 | }, |
167 | }, | 73 | }, |
168 | [1] = { | 74 | [1] = { |
@@ -172,10 +78,6 @@ static struct s3c24xx_gpio_chip gpios[] = { | |||
172 | .owner = THIS_MODULE, | 78 | .owner = THIS_MODULE, |
173 | .label = "GPIOB", | 79 | .label = "GPIOB", |
174 | .ngpio = 16, | 80 | .ngpio = 16, |
175 | .direction_input = s3c24xx_gpiolib_input, | ||
176 | .direction_output = s3c24xx_gpiolib_output, | ||
177 | .set = s3c24xx_gpiolib_set, | ||
178 | .get = s3c24xx_gpiolib_get, | ||
179 | }, | 81 | }, |
180 | }, | 82 | }, |
181 | [2] = { | 83 | [2] = { |
@@ -185,10 +87,6 @@ static struct s3c24xx_gpio_chip gpios[] = { | |||
185 | .owner = THIS_MODULE, | 87 | .owner = THIS_MODULE, |
186 | .label = "GPIOC", | 88 | .label = "GPIOC", |
187 | .ngpio = 16, | 89 | .ngpio = 16, |
188 | .direction_input = s3c24xx_gpiolib_input, | ||
189 | .direction_output = s3c24xx_gpiolib_output, | ||
190 | .set = s3c24xx_gpiolib_set, | ||
191 | .get = s3c24xx_gpiolib_get, | ||
192 | }, | 90 | }, |
193 | }, | 91 | }, |
194 | [3] = { | 92 | [3] = { |
@@ -198,10 +96,6 @@ static struct s3c24xx_gpio_chip gpios[] = { | |||
198 | .owner = THIS_MODULE, | 96 | .owner = THIS_MODULE, |
199 | .label = "GPIOD", | 97 | .label = "GPIOD", |
200 | .ngpio = 16, | 98 | .ngpio = 16, |
201 | .direction_input = s3c24xx_gpiolib_input, | ||
202 | .direction_output = s3c24xx_gpiolib_output, | ||
203 | .set = s3c24xx_gpiolib_set, | ||
204 | .get = s3c24xx_gpiolib_get, | ||
205 | }, | 99 | }, |
206 | }, | 100 | }, |
207 | [4] = { | 101 | [4] = { |
@@ -211,10 +105,6 @@ static struct s3c24xx_gpio_chip gpios[] = { | |||
211 | .label = "GPIOE", | 105 | .label = "GPIOE", |
212 | .owner = THIS_MODULE, | 106 | .owner = THIS_MODULE, |
213 | .ngpio = 16, | 107 | .ngpio = 16, |
214 | .direction_input = s3c24xx_gpiolib_input, | ||
215 | .direction_output = s3c24xx_gpiolib_output, | ||
216 | .set = s3c24xx_gpiolib_set, | ||
217 | .get = s3c24xx_gpiolib_get, | ||
218 | }, | 108 | }, |
219 | }, | 109 | }, |
220 | [5] = { | 110 | [5] = { |
@@ -224,10 +114,6 @@ static struct s3c24xx_gpio_chip gpios[] = { | |||
224 | .owner = THIS_MODULE, | 114 | .owner = THIS_MODULE, |
225 | .label = "GPIOF", | 115 | .label = "GPIOF", |
226 | .ngpio = 8, | 116 | .ngpio = 8, |
227 | .direction_input = s3c24xx_gpiolib_input, | ||
228 | .direction_output = s3c24xx_gpiolib_output, | ||
229 | .set = s3c24xx_gpiolib_set, | ||
230 | .get = s3c24xx_gpiolib_get, | ||
231 | }, | 117 | }, |
232 | }, | 118 | }, |
233 | [6] = { | 119 | [6] = { |
@@ -237,21 +123,17 @@ static struct s3c24xx_gpio_chip gpios[] = { | |||
237 | .owner = THIS_MODULE, | 123 | .owner = THIS_MODULE, |
238 | .label = "GPIOG", | 124 | .label = "GPIOG", |
239 | .ngpio = 10, | 125 | .ngpio = 10, |
240 | .direction_input = s3c24xx_gpiolib_input, | ||
241 | .direction_output = s3c24xx_gpiolib_output, | ||
242 | .set = s3c24xx_gpiolib_set, | ||
243 | .get = s3c24xx_gpiolib_get, | ||
244 | }, | 126 | }, |
245 | }, | 127 | }, |
246 | }; | 128 | }; |
247 | 129 | ||
248 | static __init int s3c24xx_gpiolib_init(void) | 130 | static __init int s3c24xx_gpiolib_init(void) |
249 | { | 131 | { |
250 | struct s3c24xx_gpio_chip *chip = gpios; | 132 | struct s3c_gpio_chip *chip = s3c24xx_gpios; |
251 | int gpn; | 133 | int gpn; |
252 | 134 | ||
253 | for (gpn = 0; gpn < ARRAY_SIZE(gpios); gpn++, chip++) | 135 | for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) |
254 | gpiochip_add(&chip->chip); | 136 | s3c_gpiolib_add(chip); |
255 | 137 | ||
256 | return 0; | 138 | return 0; |
257 | } | 139 | } |
diff --git a/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h b/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h new file mode 100644 index 000000000000..a087de21bc20 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h | |||
@@ -0,0 +1,55 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/include/mach/pwm-clock.h | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * S3C24xx - pwm clock and timer support | ||
8 | */ | ||
9 | |||
10 | /** | ||
11 | * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk | ||
12 | * @cfg: The timer TCFG1 register bits shifted down to 0. | ||
13 | * | ||
14 | * Return true if the given configuration from TCFG1 is a TCLK instead | ||
15 | * any of the TDIV clocks. | ||
16 | */ | ||
17 | static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) | ||
18 | { | ||
19 | return tcfg == S3C2410_TCFG1_MUX_TCLK; | ||
20 | } | ||
21 | |||
22 | /** | ||
23 | * tcfg_to_divisor() - convert tcfg1 setting to a divisor | ||
24 | * @tcfg1: The tcfg1 setting, shifted down. | ||
25 | * | ||
26 | * Get the divisor value for the given tcfg1 setting. We assume the | ||
27 | * caller has already checked to see if this is not a TCLK source. | ||
28 | */ | ||
29 | static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) | ||
30 | { | ||
31 | return 1 << (1 + tcfg1); | ||
32 | } | ||
33 | |||
34 | /** | ||
35 | * pwm_tdiv_has_div1() - does the tdiv setting have a /1 | ||
36 | * | ||
37 | * Return true if we have a /1 in the tdiv setting. | ||
38 | */ | ||
39 | static inline unsigned int pwm_tdiv_has_div1(void) | ||
40 | { | ||
41 | return 0; | ||
42 | } | ||
43 | |||
44 | /** | ||
45 | * pwm_tdiv_div_bits() - calculate TCFG1 divisor value. | ||
46 | * @div: The divisor to calculate the bit information for. | ||
47 | * | ||
48 | * Turn a divisor into the necessary bit field for TCFG1. | ||
49 | */ | ||
50 | static inline unsigned long pwm_tdiv_div_bits(unsigned int div) | ||
51 | { | ||
52 | return ilog2(div) - 1; | ||
53 | } | ||
54 | |||
55 | #define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h new file mode 100644 index 000000000000..fef8ea8b8e1e --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/map.h | |||
@@ -0,0 +1,99 @@ | |||
1 | /* linux/include/asm-arm/plat-s3c24xx/map.h | ||
2 | * | ||
3 | * Copyright (c) 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C24XX - Memory map definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_PLAT_S3C24XX_MAP_H | ||
14 | #define __ASM_PLAT_S3C24XX_MAP_H | ||
15 | |||
16 | /* interrupt controller is the first thing we put in, to make | ||
17 | * the assembly code for the irq detection easier | ||
18 | */ | ||
19 | #define S3C24XX_VA_IRQ S3C_VA_IRQ | ||
20 | #define S3C2410_PA_IRQ (0x4A000000) | ||
21 | #define S3C24XX_SZ_IRQ SZ_1M | ||
22 | |||
23 | /* memory controller registers */ | ||
24 | #define S3C24XX_VA_MEMCTRL S3C_VA_MEM | ||
25 | #define S3C2410_PA_MEMCTRL (0x48000000) | ||
26 | #define S3C24XX_SZ_MEMCTRL SZ_1M | ||
27 | |||
28 | /* UARTs */ | ||
29 | #define S3C24XX_VA_UART S3C_VA_UART | ||
30 | #define S3C2410_PA_UART (0x50000000) | ||
31 | #define S3C24XX_SZ_UART SZ_1M | ||
32 | #define S3C_UART_OFFSET (0x4000) | ||
33 | |||
34 | /* Timers */ | ||
35 | #define S3C24XX_VA_TIMER S3C_VA_TIMER | ||
36 | #define S3C2410_PA_TIMER (0x51000000) | ||
37 | #define S3C24XX_SZ_TIMER SZ_1M | ||
38 | |||
39 | /* Clock and Power management */ | ||
40 | #define S3C24XX_VA_CLKPWR S3C_VA_SYS | ||
41 | #define S3C24XX_SZ_CLKPWR SZ_1M | ||
42 | |||
43 | /* USB Device port */ | ||
44 | #define S3C2410_PA_USBDEV (0x52000000) | ||
45 | #define S3C24XX_SZ_USBDEV SZ_1M | ||
46 | |||
47 | /* Watchdog */ | ||
48 | #define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG | ||
49 | #define S3C2410_PA_WATCHDOG (0x53000000) | ||
50 | #define S3C24XX_SZ_WATCHDOG SZ_1M | ||
51 | |||
52 | /* Standard size definitions for peripheral blocks. */ | ||
53 | |||
54 | #define S3C24XX_SZ_IIS SZ_1M | ||
55 | #define S3C24XX_SZ_ADC SZ_1M | ||
56 | #define S3C24XX_SZ_SPI SZ_1M | ||
57 | #define S3C24XX_SZ_SDI SZ_1M | ||
58 | #define S3C24XX_SZ_NAND SZ_1M | ||
59 | #define S3C24XX_SZ_USBHOST SZ_1M | ||
60 | |||
61 | /* GPIO ports */ | ||
62 | |||
63 | /* the calculation for the VA of this must ensure that | ||
64 | * it is the same distance apart from the UART in the | ||
65 | * phsyical address space, as the initial mapping for the IO | ||
66 | * is done as a 1:1 maping. This puts it (currently) at | ||
67 | * 0xFA800000, which is not in the way of any current mapping | ||
68 | * by the base system. | ||
69 | */ | ||
70 | |||
71 | #define S3C2410_PA_GPIO (0x56000000) | ||
72 | #define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) | ||
73 | #define S3C24XX_SZ_GPIO SZ_1M | ||
74 | |||
75 | |||
76 | /* ISA style IO, for each machine to sort out mappings for, if it | ||
77 | * implements it. We reserve two 16M regions for ISA. | ||
78 | */ | ||
79 | |||
80 | #define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000) | ||
81 | #define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000) | ||
82 | |||
83 | /* deal with the registers that move under the 2412/2413 */ | ||
84 | |||
85 | #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) | ||
86 | #ifndef __ASSEMBLY__ | ||
87 | extern void __iomem *s3c24xx_va_gpio2; | ||
88 | #endif | ||
89 | #ifdef CONFIG_CPU_S3C2412_ONLY | ||
90 | #define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10) | ||
91 | #else | ||
92 | #define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2 | ||
93 | #endif | ||
94 | #else | ||
95 | #define s3c24xx_va_gpio2 S3C24XX_VA_GPIO | ||
96 | #define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO | ||
97 | #endif | ||
98 | |||
99 | #endif /* __ASM_PLAT_S3C24XX_MAP_H */ | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/pll.h b/arch/arm/plat-s3c24xx/include/plat/pll.h new file mode 100644 index 000000000000..7ea8bffa7a9c --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/pll.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/include/plat/pll.h | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * S3C24xx - common pll registers and code | ||
8 | */ | ||
9 | |||
10 | #define S3C24XX_PLLCON_MDIVSHIFT 12 | ||
11 | #define S3C24XX_PLLCON_PDIVSHIFT 4 | ||
12 | #define S3C24XX_PLLCON_SDIVSHIFT 0 | ||
13 | #define S3C24XX_PLLCON_MDIVMASK ((1<<(1+(19-12)))-1) | ||
14 | #define S3C24XX_PLLCON_PDIVMASK ((1<<5)-1) | ||
15 | #define S3C24XX_PLLCON_SDIVMASK 3 | ||
16 | |||
17 | #include <asm/div64.h> | ||
18 | |||
19 | static inline unsigned int | ||
20 | s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk) | ||
21 | { | ||
22 | unsigned int mdiv, pdiv, sdiv; | ||
23 | uint64_t fvco; | ||
24 | |||
25 | mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT; | ||
26 | pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT; | ||
27 | sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT; | ||
28 | |||
29 | mdiv &= S3C24XX_PLLCON_MDIVMASK; | ||
30 | pdiv &= S3C24XX_PLLCON_PDIVMASK; | ||
31 | sdiv &= S3C24XX_PLLCON_SDIVMASK; | ||
32 | |||
33 | fvco = (uint64_t)baseclk * (mdiv + 8); | ||
34 | do_div(fvco, (pdiv + 2) << sdiv); | ||
35 | |||
36 | return (unsigned int)fvco; | ||
37 | } | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2400.h b/arch/arm/plat-s3c24xx/include/plat/s3c2400.h index 3a5a16821af8..b3feaea5c70b 100644 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2400.h +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2400.h | |||
@@ -17,7 +17,7 @@ | |||
17 | 17 | ||
18 | extern int s3c2400_init(void); | 18 | extern int s3c2400_init(void); |
19 | 19 | ||
20 | extern void s3c2400_map_io(struct map_desc *mach_desc, int size); | 20 | extern void s3c2400_map_io(void); |
21 | 21 | ||
22 | extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no); | 22 | extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no); |
23 | 23 | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h index 3cd1ec677b3f..a9ac9e29759e 100644 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h | |||
@@ -15,7 +15,7 @@ | |||
15 | 15 | ||
16 | extern int s3c2410_init(void); | 16 | extern int s3c2410_init(void); |
17 | 17 | ||
18 | extern void s3c2410_map_io(struct map_desc *mach_desc, int size); | 18 | extern void s3c2410_map_io(void); |
19 | 19 | ||
20 | extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); | 20 | extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no); |
21 | 21 | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2412.h b/arch/arm/plat-s3c24xx/include/plat/s3c2412.h index 3ec97685e781..bb15d3b68be5 100644 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2412.h +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2412.h | |||
@@ -14,7 +14,7 @@ | |||
14 | 14 | ||
15 | extern int s3c2412_init(void); | 15 | extern int s3c2412_init(void); |
16 | 16 | ||
17 | extern void s3c2412_map_io(struct map_desc *mach_desc, int size); | 17 | extern void s3c2412_map_io(void); |
18 | 18 | ||
19 | extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no); | 19 | extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no); |
20 | 20 | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h index 11d83b5c84e6..815b107ed890 100644 --- a/arch/arm/plat-s3c24xx/include/plat/s3c2443.h +++ b/arch/arm/plat-s3c24xx/include/plat/s3c2443.h | |||
@@ -16,7 +16,7 @@ struct s3c2410_uartcfg; | |||
16 | 16 | ||
17 | extern int s3c2443_init(void); | 17 | extern int s3c2443_init(void); |
18 | 18 | ||
19 | extern void s3c2443_map_io(struct map_desc *mach_desc, int size); | 19 | extern void s3c2443_map_io(void); |
20 | 20 | ||
21 | extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no); | 21 | extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no); |
22 | 22 | ||
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c index 963f7a4f26f2..0192ecdc1442 100644 --- a/arch/arm/plat-s3c24xx/irq.c +++ b/arch/arm/plat-s3c24xx/irq.c | |||
@@ -62,6 +62,7 @@ | |||
62 | 62 | ||
63 | #include <asm/mach/irq.h> | 63 | #include <asm/mach/irq.h> |
64 | 64 | ||
65 | #include <plat/regs-irqtype.h> | ||
65 | #include <mach/regs-irq.h> | 66 | #include <mach/regs-irq.h> |
66 | #include <mach/regs-gpio.h> | 67 | #include <mach/regs-gpio.h> |
67 | 68 | ||
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c index 8efb57ad5019..34ef18e5b2a1 100644 --- a/arch/arm/plat-s3c24xx/pm.c +++ b/arch/arm/plat-s3c24xx/pm.c | |||
@@ -33,7 +33,6 @@ | |||
33 | #include <linux/interrupt.h> | 33 | #include <linux/interrupt.h> |
34 | #include <linux/crc32.h> | 34 | #include <linux/crc32.h> |
35 | #include <linux/ioport.h> | 35 | #include <linux/ioport.h> |
36 | #include <linux/delay.h> | ||
37 | #include <linux/serial_core.h> | 36 | #include <linux/serial_core.h> |
38 | #include <linux/io.h> | 37 | #include <linux/io.h> |
39 | 38 | ||
@@ -76,11 +75,13 @@ static struct sleep_save core_save[] = { | |||
76 | SAVE_ITEM(S3C2410_BANKCON4), | 75 | SAVE_ITEM(S3C2410_BANKCON4), |
77 | SAVE_ITEM(S3C2410_BANKCON5), | 76 | SAVE_ITEM(S3C2410_BANKCON5), |
78 | 77 | ||
78 | #ifndef CONFIG_CPU_FREQ | ||
79 | SAVE_ITEM(S3C2410_CLKDIVN), | 79 | SAVE_ITEM(S3C2410_CLKDIVN), |
80 | SAVE_ITEM(S3C2410_MPLLCON), | 80 | SAVE_ITEM(S3C2410_MPLLCON), |
81 | SAVE_ITEM(S3C2410_REFRESH), | ||
82 | #endif | ||
81 | SAVE_ITEM(S3C2410_UPLLCON), | 83 | SAVE_ITEM(S3C2410_UPLLCON), |
82 | SAVE_ITEM(S3C2410_CLKSLOW), | 84 | SAVE_ITEM(S3C2410_CLKSLOW), |
83 | SAVE_ITEM(S3C2410_REFRESH), | ||
84 | }; | 85 | }; |
85 | 86 | ||
86 | static struct gpio_sleep { | 87 | static struct gpio_sleep { |
diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/plat-s3c24xx/s3c2410-clock.c index 4e07943c1e29..b61bdb793734 100644 --- a/arch/arm/mach-s3c2410/clock.c +++ b/arch/arm/plat-s3c24xx/s3c2410-clock.c | |||
@@ -272,5 +272,6 @@ int __init s3c2410_baseclk_add(void) | |||
272 | (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on", | 272 | (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on", |
273 | (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on"); | 273 | (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on"); |
274 | 274 | ||
275 | s3c_pwmclk_init(); | ||
275 | return 0; | 276 | return 0; |
276 | } | 277 | } |
diff --git a/arch/arm/plat-s3c24xx/s3c244x-clock.c b/arch/arm/plat-s3c24xx/s3c244x-clock.c index 7c09773ff9fc..dde41f171aff 100644 --- a/arch/arm/plat-s3c24xx/s3c244x-clock.c +++ b/arch/arm/plat-s3c24xx/s3c244x-clock.c | |||
@@ -31,7 +31,6 @@ | |||
31 | #include <linux/sysdev.h> | 31 | #include <linux/sysdev.h> |
32 | #include <linux/interrupt.h> | 32 | #include <linux/interrupt.h> |
33 | #include <linux/ioport.h> | 33 | #include <linux/ioport.h> |
34 | #include <linux/mutex.h> | ||
35 | #include <linux/clk.h> | 34 | #include <linux/clk.h> |
36 | #include <linux/io.h> | 35 | #include <linux/io.h> |
37 | 36 | ||
@@ -102,13 +101,13 @@ static int s3c244x_clk_add(struct sys_device *sysdev) | |||
102 | if (clk_get_rate(clock_upll) > (94 * MHZ)) { | 101 | if (clk_get_rate(clock_upll) > (94 * MHZ)) { |
103 | clk_usb_bus.rate = clk_get_rate(clock_upll) / 2; | 102 | clk_usb_bus.rate = clk_get_rate(clock_upll) / 2; |
104 | 103 | ||
105 | mutex_lock(&clocks_mutex); | 104 | spin_lock(&clocks_lock); |
106 | 105 | ||
107 | clkdivn = __raw_readl(S3C2410_CLKDIVN); | 106 | clkdivn = __raw_readl(S3C2410_CLKDIVN); |
108 | clkdivn |= S3C2440_CLKDIVN_UCLK; | 107 | clkdivn |= S3C2440_CLKDIVN_UCLK; |
109 | __raw_writel(clkdivn, S3C2410_CLKDIVN); | 108 | __raw_writel(clkdivn, S3C2410_CLKDIVN); |
110 | 109 | ||
111 | mutex_unlock(&clocks_mutex); | 110 | spin_unlock(&clocks_lock); |
112 | } | 111 | } |
113 | 112 | ||
114 | return 0; | 113 | return 0; |
diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c index c0344fac4a94..c1de6bb0101b 100644 --- a/arch/arm/plat-s3c24xx/s3c244x.c +++ b/arch/arm/plat-s3c24xx/s3c244x.c | |||
@@ -29,6 +29,8 @@ | |||
29 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
30 | #include <asm/irq.h> | 30 | #include <asm/irq.h> |
31 | 31 | ||
32 | #include <plat/cpu-freq.h> | ||
33 | |||
32 | #include <mach/regs-clock.h> | 34 | #include <mach/regs-clock.h> |
33 | #include <plat/regs-serial.h> | 35 | #include <plat/regs-serial.h> |
34 | #include <mach/regs-gpio.h> | 36 | #include <mach/regs-gpio.h> |
@@ -42,6 +44,7 @@ | |||
42 | #include <plat/devs.h> | 44 | #include <plat/devs.h> |
43 | #include <plat/cpu.h> | 45 | #include <plat/cpu.h> |
44 | #include <plat/pm.h> | 46 | #include <plat/pm.h> |
47 | #include <plat/pll.h> | ||
45 | 48 | ||
46 | static struct map_desc s3c244x_iodesc[] __initdata = { | 49 | static struct map_desc s3c244x_iodesc[] __initdata = { |
47 | IODESC_ENT(CLKPWR), | 50 | IODESC_ENT(CLKPWR), |
@@ -56,32 +59,34 @@ void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no) | |||
56 | s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no); | 59 | s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no); |
57 | } | 60 | } |
58 | 61 | ||
59 | void __init s3c244x_map_io(struct map_desc *mach_desc, int size) | 62 | void __init s3c244x_map_io(void) |
60 | { | 63 | { |
61 | /* register our io-tables */ | 64 | /* register our io-tables */ |
62 | 65 | ||
63 | iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc)); | 66 | iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc)); |
64 | iotable_init(mach_desc, size); | ||
65 | 67 | ||
66 | /* rename any peripherals used differing from the s3c2410 */ | 68 | /* rename any peripherals used differing from the s3c2410 */ |
67 | 69 | ||
68 | s3c_device_sdi.name = "s3c2440-sdi"; | 70 | s3c_device_sdi.name = "s3c2440-sdi"; |
69 | s3c_device_i2c.name = "s3c2440-i2c"; | 71 | s3c_device_i2c0.name = "s3c2440-i2c"; |
70 | s3c_device_nand.name = "s3c2440-nand"; | 72 | s3c_device_nand.name = "s3c2440-nand"; |
71 | s3c_device_usbgadget.name = "s3c2440-usbgadget"; | 73 | s3c_device_usbgadget.name = "s3c2440-usbgadget"; |
72 | } | 74 | } |
73 | 75 | ||
74 | void __init s3c244x_init_clocks(int xtal) | 76 | void __init_or_cpufreq s3c244x_setup_clocks(void) |
75 | { | 77 | { |
78 | struct clk *xtal_clk; | ||
76 | unsigned long clkdiv; | 79 | unsigned long clkdiv; |
77 | unsigned long camdiv; | 80 | unsigned long camdiv; |
81 | unsigned long xtal; | ||
78 | unsigned long hclk, fclk, pclk; | 82 | unsigned long hclk, fclk, pclk; |
79 | int hdiv = 1; | 83 | int hdiv = 1; |
80 | 84 | ||
81 | /* now we've got our machine bits initialised, work out what | 85 | xtal_clk = clk_get(NULL, "xtal"); |
82 | * clocks we've got */ | 86 | xtal = clk_get_rate(xtal_clk); |
87 | clk_put(xtal_clk); | ||
83 | 88 | ||
84 | fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2; | 89 | fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2; |
85 | 90 | ||
86 | clkdiv = __raw_readl(S3C2410_CLKDIVN); | 91 | clkdiv = __raw_readl(S3C2410_CLKDIVN); |
87 | camdiv = __raw_readl(S3C2440_CAMDIVN); | 92 | camdiv = __raw_readl(S3C2440_CAMDIVN); |
@@ -107,18 +112,24 @@ void __init s3c244x_init_clocks(int xtal) | |||
107 | } | 112 | } |
108 | 113 | ||
109 | hclk = fclk / hdiv; | 114 | hclk = fclk / hdiv; |
110 | pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1); | 115 | pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1); |
111 | 116 | ||
112 | /* print brief summary of clocks, etc */ | 117 | /* print brief summary of clocks, etc */ |
113 | 118 | ||
114 | printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", | 119 | printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", |
115 | print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); | 120 | print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); |
116 | 121 | ||
122 | s3c24xx_setup_clocks(fclk, hclk, pclk); | ||
123 | } | ||
124 | |||
125 | void __init s3c244x_init_clocks(int xtal) | ||
126 | { | ||
117 | /* initialise the clocks here, to allow other things like the | 127 | /* initialise the clocks here, to allow other things like the |
118 | * console to use them, and to add new ones after the initialisation | 128 | * console to use them, and to add new ones after the initialisation |
119 | */ | 129 | */ |
120 | 130 | ||
121 | s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); | 131 | s3c24xx_register_baseclocks(xtal); |
132 | s3c244x_setup_clocks(); | ||
122 | s3c2410_baseclk_add(); | 133 | s3c2410_baseclk_add(); |
123 | } | 134 | } |
124 | 135 | ||
diff --git a/arch/arm/plat-s3c24xx/s3c244x.h b/arch/arm/plat-s3c24xx/s3c244x.h index f8ed17676a35..6aab5eaae2b4 100644 --- a/arch/arm/plat-s3c24xx/s3c244x.h +++ b/arch/arm/plat-s3c24xx/s3c244x.h | |||
@@ -12,7 +12,7 @@ | |||
12 | 12 | ||
13 | #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) | 13 | #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) |
14 | 14 | ||
15 | extern void s3c244x_map_io(struct map_desc *mach_desc, int size); | 15 | extern void s3c244x_map_io(void); |
16 | 16 | ||
17 | extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no); | 17 | extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no); |
18 | 18 | ||
diff --git a/arch/arm/plat-s3c24xx/setup-i2c.c b/arch/arm/plat-s3c24xx/setup-i2c.c new file mode 100644 index 000000000000..d62b7e7fb355 --- /dev/null +++ b/arch/arm/plat-s3c24xx/setup-i2c.c | |||
@@ -0,0 +1,25 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/setup-i2c.c | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C24XX Base setup for i2c device | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/kernel.h> | ||
14 | |||
15 | struct platform_device; | ||
16 | |||
17 | #include <plat/iic.h> | ||
18 | #include <mach/hardware.h> | ||
19 | #include <mach/regs-gpio.h> | ||
20 | |||
21 | void s3c_i2c0_cfg_gpio(struct platform_device *dev) | ||
22 | { | ||
23 | s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA); | ||
24 | s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL); | ||
25 | } | ||
diff --git a/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c new file mode 100644 index 000000000000..8b403cbb53d2 --- /dev/null +++ b/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c | |||
@@ -0,0 +1,37 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/spi-bus0-gpe11_12_13.c | ||
2 | * | ||
3 | * Copyright (c) 2008 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C24XX SPI - gpio configuration for bus 0 on gpe11,12,13 | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | |||
16 | #include <mach/hardware.h> | ||
17 | |||
18 | #include <mach/spi.h> | ||
19 | #include <mach/regs-gpio.h> | ||
20 | |||
21 | void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi, | ||
22 | int enable) | ||
23 | { | ||
24 | if (enable) { | ||
25 | s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_SPICLK0); | ||
26 | s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_SPIMOSI0); | ||
27 | s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_SPIMISO0); | ||
28 | s3c2410_gpio_pullup(S3C2410_GPE11, 0); | ||
29 | s3c2410_gpio_pullup(S3C2410_GPE13, 0); | ||
30 | } else { | ||
31 | s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPIO_INPUT); | ||
32 | s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPIO_INPUT); | ||
33 | s3c2410_gpio_pullup(S3C2410_GPE11, 1); | ||
34 | s3c2410_gpio_pullup(S3C2410_GPE12, 1); | ||
35 | s3c2410_gpio_pullup(S3C2410_GPE13, 1); | ||
36 | } | ||
37 | } | ||
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c new file mode 100644 index 000000000000..8fccd4e549f0 --- /dev/null +++ b/arch/arm/plat-s3c24xx/spi-bus1-gpg5_6_7.c | |||
@@ -0,0 +1,37 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/spi-bus0-gpg5_6_7.c | ||
2 | * | ||
3 | * Copyright (c) 2008 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C24XX SPI - gpio configuration for bus 1 on gpg5,6,7 | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | |||
16 | #include <mach/hardware.h> | ||
17 | |||
18 | #include <mach/spi.h> | ||
19 | #include <mach/regs-gpio.h> | ||
20 | |||
21 | void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi, | ||
22 | int enable) | ||
23 | { | ||
24 | if (enable) { | ||
25 | s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPG7_SPICLK1); | ||
26 | s3c2410_gpio_cfgpin(S3C2410_GPG6, S3C2410_GPG6_SPIMOSI1); | ||
27 | s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPG5_SPIMISO1); | ||
28 | s3c2410_gpio_pullup(S3C2410_GPG5, 0); | ||
29 | s3c2410_gpio_pullup(S3C2410_GPG6, 0); | ||
30 | } else { | ||
31 | s3c2410_gpio_cfgpin(S3C2410_GPG7, S3C2410_GPIO_INPUT); | ||
32 | s3c2410_gpio_cfgpin(S3C2410_GPG5, S3C2410_GPIO_INPUT); | ||
33 | s3c2410_gpio_pullup(S3C2410_GPG5, 1); | ||
34 | s3c2410_gpio_pullup(S3C2410_GPG6, 1); | ||
35 | s3c2410_gpio_pullup(S3C2410_GPG7, 1); | ||
36 | } | ||
37 | } | ||
diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig new file mode 100644 index 000000000000..54375a00a7d2 --- /dev/null +++ b/arch/arm/plat-s3c64xx/Kconfig | |||
@@ -0,0 +1,62 @@ | |||
1 | # arch/arm/plat-s3c64xx/Kconfig | ||
2 | # | ||
3 | # Copyright 2008 Openmoko, Inc. | ||
4 | # Copyright 2008 Simtec Electronics | ||
5 | # Ben Dooks <ben@simtec.co.uk> | ||
6 | # | ||
7 | # Licensed under GPLv2 | ||
8 | |||
9 | config PLAT_S3C64XX | ||
10 | bool | ||
11 | depends on ARCH_S3C64XX | ||
12 | default y | ||
13 | select CPU_V6 | ||
14 | select PLAT_S3C | ||
15 | select ARM_VIC | ||
16 | select NO_IOPORT | ||
17 | select ARCH_REQUIRE_GPIOLIB | ||
18 | select S3C_GPIO_TRACK | ||
19 | select S3C_GPIO_PULL_UPDOWN | ||
20 | select S3C_GPIO_CFG_S3C24XX | ||
21 | select S3C_GPIO_CFG_S3C64XX | ||
22 | help | ||
23 | Base platform code for any Samsung S3C64XX device | ||
24 | |||
25 | if PLAT_S3C64XX | ||
26 | |||
27 | # Configuration options shared by all S3C64XX implementations | ||
28 | |||
29 | config CPU_S3C6400_INIT | ||
30 | bool | ||
31 | help | ||
32 | Common initialisation code for the S3C6400 that is shared | ||
33 | by other CPUs in the series, such as the S3C6410. | ||
34 | |||
35 | config CPU_S3C6400_CLOCK | ||
36 | bool | ||
37 | help | ||
38 | Common clock support code for the S3C6400 that is shared | ||
39 | by other CPUs in the series, such as the S3C6410. | ||
40 | |||
41 | # platform specific device setup | ||
42 | |||
43 | config S3C64XX_SETUP_I2C0 | ||
44 | bool | ||
45 | default y | ||
46 | help | ||
47 | Common setup code for i2c bus 0. | ||
48 | |||
49 | Note, currently since i2c0 is always compiled, this setup helper | ||
50 | is always compiled with it. | ||
51 | |||
52 | config S3C64XX_SETUP_I2C1 | ||
53 | bool | ||
54 | help | ||
55 | Common setup code for i2c bus 1. | ||
56 | |||
57 | config S3C64XX_SETUP_FB_24BPP | ||
58 | bool | ||
59 | help | ||
60 | Common setup code for S3C64XX with an 24bpp RGB display helper. | ||
61 | |||
62 | endif | ||
diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile new file mode 100644 index 000000000000..2e6d79bf8f33 --- /dev/null +++ b/arch/arm/plat-s3c64xx/Makefile | |||
@@ -0,0 +1,31 @@ | |||
1 | # arch/arm/plat-s3c64xx/Makefile | ||
2 | # | ||
3 | # Copyright 2008 Openmoko, Inc. | ||
4 | # Copyright 2008 Simtec Electronics | ||
5 | # | ||
6 | # Licensed under GPLv2 | ||
7 | |||
8 | obj-y := | ||
9 | obj-m := | ||
10 | obj-n := dummy.o | ||
11 | obj- := | ||
12 | |||
13 | # Core files | ||
14 | |||
15 | obj-y += dev-uart.o | ||
16 | obj-y += cpu.o | ||
17 | obj-y += irq.o | ||
18 | obj-y += irq-eint.o | ||
19 | obj-y += clock.o | ||
20 | obj-y += gpiolib.o | ||
21 | |||
22 | # CPU support | ||
23 | |||
24 | obj-$(CONFIG_CPU_S3C6400_INIT) += s3c6400-init.o | ||
25 | obj-$(CONFIG_CPU_S3C6400_CLOCK) += s3c6400-clock.o | ||
26 | |||
27 | # Device setup | ||
28 | |||
29 | obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o | ||
30 | obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o | ||
31 | obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o | ||
diff --git a/arch/arm/plat-s3c64xx/clock.c b/arch/arm/plat-s3c64xx/clock.c new file mode 100644 index 000000000000..136c982c68e1 --- /dev/null +++ b/arch/arm/plat-s3c64xx/clock.c | |||
@@ -0,0 +1,281 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/clock.c | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C64XX Base clock support | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/init.h> | ||
16 | #include <linux/module.h> | ||
17 | #include <linux/interrupt.h> | ||
18 | #include <linux/ioport.h> | ||
19 | #include <linux/io.h> | ||
20 | |||
21 | #include <mach/hardware.h> | ||
22 | #include <mach/map.h> | ||
23 | |||
24 | #include <plat/regs-sys.h> | ||
25 | #include <plat/regs-clock.h> | ||
26 | #include <plat/cpu.h> | ||
27 | #include <plat/devs.h> | ||
28 | #include <plat/clock.h> | ||
29 | |||
30 | struct clk clk_27m = { | ||
31 | .name = "clk_27m", | ||
32 | .id = -1, | ||
33 | .rate = 27000000, | ||
34 | }; | ||
35 | |||
36 | static int clk_48m_ctrl(struct clk *clk, int enable) | ||
37 | { | ||
38 | unsigned long flags; | ||
39 | u32 val; | ||
40 | |||
41 | /* can't rely on clock lock, this register has other usages */ | ||
42 | local_irq_save(flags); | ||
43 | |||
44 | val = __raw_readl(S3C64XX_OTHERS); | ||
45 | if (enable) | ||
46 | val |= S3C64XX_OTHERS_USBMASK; | ||
47 | else | ||
48 | val &= ~S3C64XX_OTHERS_USBMASK; | ||
49 | |||
50 | __raw_writel(val, S3C64XX_OTHERS); | ||
51 | local_irq_restore(flags); | ||
52 | |||
53 | return 0; | ||
54 | } | ||
55 | |||
56 | struct clk clk_48m = { | ||
57 | .name = "clk_48m", | ||
58 | .id = -1, | ||
59 | .rate = 48000000, | ||
60 | .enable = clk_48m_ctrl, | ||
61 | }; | ||
62 | |||
63 | static int inline s3c64xx_gate(void __iomem *reg, | ||
64 | struct clk *clk, | ||
65 | int enable) | ||
66 | { | ||
67 | unsigned int ctrlbit = clk->ctrlbit; | ||
68 | u32 con; | ||
69 | |||
70 | con = __raw_readl(reg); | ||
71 | |||
72 | if (enable) | ||
73 | con |= ctrlbit; | ||
74 | else | ||
75 | con &= ~ctrlbit; | ||
76 | |||
77 | __raw_writel(con, reg); | ||
78 | return 0; | ||
79 | } | ||
80 | |||
81 | static int s3c64xx_pclk_ctrl(struct clk *clk, int enable) | ||
82 | { | ||
83 | return s3c64xx_gate(S3C_PCLK_GATE, clk, enable); | ||
84 | } | ||
85 | |||
86 | static int s3c64xx_hclk_ctrl(struct clk *clk, int enable) | ||
87 | { | ||
88 | return s3c64xx_gate(S3C_HCLK_GATE, clk, enable); | ||
89 | } | ||
90 | |||
91 | int s3c64xx_sclk_ctrl(struct clk *clk, int enable) | ||
92 | { | ||
93 | return s3c64xx_gate(S3C_SCLK_GATE, clk, enable); | ||
94 | } | ||
95 | |||
96 | static struct clk init_clocks_disable[] = { | ||
97 | { | ||
98 | .name = "nand", | ||
99 | .id = -1, | ||
100 | .parent = &clk_h, | ||
101 | }, { | ||
102 | .name = "adc", | ||
103 | .id = -1, | ||
104 | .parent = &clk_p, | ||
105 | .enable = s3c64xx_pclk_ctrl, | ||
106 | .ctrlbit = S3C_CLKCON_PCLK_TSADC, | ||
107 | }, { | ||
108 | .name = "i2c", | ||
109 | .id = -1, | ||
110 | .parent = &clk_p, | ||
111 | .enable = s3c64xx_pclk_ctrl, | ||
112 | .ctrlbit = S3C_CLKCON_PCLK_IIC, | ||
113 | }, { | ||
114 | .name = "iis", | ||
115 | .id = 0, | ||
116 | .parent = &clk_p, | ||
117 | .enable = s3c64xx_pclk_ctrl, | ||
118 | .ctrlbit = S3C_CLKCON_PCLK_IIS0, | ||
119 | }, { | ||
120 | .name = "iis", | ||
121 | .id = 1, | ||
122 | .parent = &clk_p, | ||
123 | .enable = s3c64xx_pclk_ctrl, | ||
124 | .ctrlbit = S3C_CLKCON_PCLK_IIS1, | ||
125 | }, { | ||
126 | .name = "spi", | ||
127 | .id = 0, | ||
128 | .parent = &clk_p, | ||
129 | .enable = s3c64xx_pclk_ctrl, | ||
130 | .ctrlbit = S3C_CLKCON_PCLK_SPI0, | ||
131 | }, { | ||
132 | .name = "spi", | ||
133 | .id = 1, | ||
134 | .parent = &clk_p, | ||
135 | .enable = s3c64xx_pclk_ctrl, | ||
136 | .ctrlbit = S3C_CLKCON_PCLK_SPI1, | ||
137 | }, { | ||
138 | .name = "48m", | ||
139 | .id = 0, | ||
140 | .parent = &clk_48m, | ||
141 | .enable = s3c64xx_sclk_ctrl, | ||
142 | .ctrlbit = S3C_CLKCON_SCLK_MMC0_48, | ||
143 | }, { | ||
144 | .name = "48m", | ||
145 | .id = 1, | ||
146 | .parent = &clk_48m, | ||
147 | .enable = s3c64xx_sclk_ctrl, | ||
148 | .ctrlbit = S3C_CLKCON_SCLK_MMC1_48, | ||
149 | }, { | ||
150 | .name = "48m", | ||
151 | .id = 2, | ||
152 | .parent = &clk_48m, | ||
153 | .enable = s3c64xx_sclk_ctrl, | ||
154 | .ctrlbit = S3C_CLKCON_SCLK_MMC2_48, | ||
155 | }, | ||
156 | }; | ||
157 | |||
158 | static struct clk init_clocks[] = { | ||
159 | { | ||
160 | .name = "lcd", | ||
161 | .id = -1, | ||
162 | .parent = &clk_h, | ||
163 | .enable = s3c64xx_hclk_ctrl, | ||
164 | .ctrlbit = S3C_CLKCON_HCLK_LCD, | ||
165 | }, { | ||
166 | .name = "gpio", | ||
167 | .id = -1, | ||
168 | .parent = &clk_p, | ||
169 | .enable = s3c64xx_pclk_ctrl, | ||
170 | .ctrlbit = S3C_CLKCON_PCLK_GPIO, | ||
171 | }, { | ||
172 | .name = "usb-host", | ||
173 | .id = -1, | ||
174 | .parent = &clk_h, | ||
175 | .enable = s3c64xx_hclk_ctrl, | ||
176 | .ctrlbit = S3C_CLKCON_SCLK_UHOST, | ||
177 | }, { | ||
178 | .name = "hsmmc", | ||
179 | .id = 0, | ||
180 | .parent = &clk_h, | ||
181 | .enable = s3c64xx_hclk_ctrl, | ||
182 | .ctrlbit = S3C_CLKCON_HCLK_HSMMC0, | ||
183 | }, { | ||
184 | .name = "hsmmc", | ||
185 | .id = 1, | ||
186 | .parent = &clk_h, | ||
187 | .enable = s3c64xx_hclk_ctrl, | ||
188 | .ctrlbit = S3C_CLKCON_HCLK_HSMMC1, | ||
189 | }, { | ||
190 | .name = "hsmmc", | ||
191 | .id = 2, | ||
192 | .parent = &clk_h, | ||
193 | .enable = s3c64xx_hclk_ctrl, | ||
194 | .ctrlbit = S3C_CLKCON_HCLK_HSMMC2, | ||
195 | }, { | ||
196 | .name = "timers", | ||
197 | .id = -1, | ||
198 | .parent = &clk_p, | ||
199 | .enable = s3c64xx_pclk_ctrl, | ||
200 | .ctrlbit = S3C_CLKCON_PCLK_PWM, | ||
201 | }, { | ||
202 | .name = "uart", | ||
203 | .id = 0, | ||
204 | .parent = &clk_p, | ||
205 | .enable = s3c64xx_pclk_ctrl, | ||
206 | .ctrlbit = S3C_CLKCON_PCLK_UART0, | ||
207 | }, { | ||
208 | .name = "uart", | ||
209 | .id = 1, | ||
210 | .parent = &clk_p, | ||
211 | .enable = s3c64xx_pclk_ctrl, | ||
212 | .ctrlbit = S3C_CLKCON_PCLK_UART1, | ||
213 | }, { | ||
214 | .name = "uart", | ||
215 | .id = 2, | ||
216 | .parent = &clk_p, | ||
217 | .enable = s3c64xx_pclk_ctrl, | ||
218 | .ctrlbit = S3C_CLKCON_PCLK_UART2, | ||
219 | }, { | ||
220 | .name = "uart", | ||
221 | .id = 3, | ||
222 | .parent = &clk_p, | ||
223 | .enable = s3c64xx_pclk_ctrl, | ||
224 | .ctrlbit = S3C_CLKCON_PCLK_UART3, | ||
225 | }, { | ||
226 | .name = "rtc", | ||
227 | .id = -1, | ||
228 | .parent = &clk_p, | ||
229 | .enable = s3c64xx_pclk_ctrl, | ||
230 | .ctrlbit = S3C_CLKCON_PCLK_RTC, | ||
231 | }, { | ||
232 | .name = "watchdog", | ||
233 | .id = -1, | ||
234 | .parent = &clk_p, | ||
235 | .ctrlbit = S3C_CLKCON_PCLK_WDT, | ||
236 | }, { | ||
237 | .name = "ac97", | ||
238 | .id = -1, | ||
239 | .parent = &clk_p, | ||
240 | .ctrlbit = S3C_CLKCON_PCLK_AC97, | ||
241 | } | ||
242 | }; | ||
243 | |||
244 | static struct clk *clks[] __initdata = { | ||
245 | &clk_ext, | ||
246 | &clk_epll, | ||
247 | &clk_27m, | ||
248 | &clk_48m, | ||
249 | }; | ||
250 | |||
251 | void s3c64xx_register_clocks(void) | ||
252 | { | ||
253 | struct clk *clkp; | ||
254 | int ret; | ||
255 | int ptr; | ||
256 | |||
257 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | ||
258 | |||
259 | clkp = init_clocks; | ||
260 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) { | ||
261 | ret = s3c24xx_register_clock(clkp); | ||
262 | if (ret < 0) { | ||
263 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
264 | clkp->name, ret); | ||
265 | } | ||
266 | } | ||
267 | |||
268 | clkp = init_clocks_disable; | ||
269 | for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { | ||
270 | |||
271 | ret = s3c24xx_register_clock(clkp); | ||
272 | if (ret < 0) { | ||
273 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
274 | clkp->name, ret); | ||
275 | } | ||
276 | |||
277 | (clkp->enable)(clkp, 0); | ||
278 | } | ||
279 | |||
280 | s3c_pwmclk_init(); | ||
281 | } | ||
diff --git a/arch/arm/plat-s3c64xx/cpu.c b/arch/arm/plat-s3c64xx/cpu.c new file mode 100644 index 000000000000..fbde183a4560 --- /dev/null +++ b/arch/arm/plat-s3c64xx/cpu.c | |||
@@ -0,0 +1,114 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/cpu.c | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C64XX CPU Support | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/init.h> | ||
16 | #include <linux/module.h> | ||
17 | #include <linux/interrupt.h> | ||
18 | #include <linux/ioport.h> | ||
19 | #include <linux/serial_core.h> | ||
20 | #include <linux/platform_device.h> | ||
21 | #include <linux/io.h> | ||
22 | |||
23 | #include <mach/hardware.h> | ||
24 | #include <mach/map.h> | ||
25 | |||
26 | #include <asm/mach/arch.h> | ||
27 | #include <asm/mach/map.h> | ||
28 | |||
29 | #include <plat/regs-serial.h> | ||
30 | |||
31 | #include <plat/cpu.h> | ||
32 | #include <plat/devs.h> | ||
33 | #include <plat/clock.h> | ||
34 | |||
35 | #include <plat/s3c6400.h> | ||
36 | #include <plat/s3c6410.h> | ||
37 | |||
38 | /* table of supported CPUs */ | ||
39 | |||
40 | static const char name_s3c6400[] = "S3C6400"; | ||
41 | static const char name_s3c6410[] = "S3C6410"; | ||
42 | |||
43 | static struct cpu_table cpu_ids[] __initdata = { | ||
44 | { | ||
45 | .idcode = 0x36400000, | ||
46 | .idmask = 0xfffff000, | ||
47 | .map_io = s3c6400_map_io, | ||
48 | .init_clocks = s3c6400_init_clocks, | ||
49 | .init_uarts = s3c6400_init_uarts, | ||
50 | .init = s3c6400_init, | ||
51 | .name = name_s3c6400, | ||
52 | }, { | ||
53 | .idcode = 0x36410100, | ||
54 | .idmask = 0xffffff00, | ||
55 | .map_io = s3c6410_map_io, | ||
56 | .init_clocks = s3c6410_init_clocks, | ||
57 | .init_uarts = s3c6410_init_uarts, | ||
58 | .init = s3c6410_init, | ||
59 | .name = name_s3c6410, | ||
60 | }, | ||
61 | }; | ||
62 | |||
63 | /* minimal IO mapping */ | ||
64 | |||
65 | /* see notes on uart map in arch/arm/mach-s3c6400/include/mach/debug-macro.S */ | ||
66 | #define UART_OFFS (S3C_PA_UART & 0xfffff) | ||
67 | |||
68 | static struct map_desc s3c_iodesc[] __initdata = { | ||
69 | { | ||
70 | .virtual = (unsigned long)S3C_VA_SYS, | ||
71 | .pfn = __phys_to_pfn(S3C64XX_PA_SYSCON), | ||
72 | .length = SZ_4K, | ||
73 | .type = MT_DEVICE, | ||
74 | }, { | ||
75 | .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS), | ||
76 | .pfn = __phys_to_pfn(S3C_PA_UART), | ||
77 | .length = SZ_4K, | ||
78 | .type = MT_DEVICE, | ||
79 | }, { | ||
80 | .virtual = (unsigned long)S3C_VA_VIC0, | ||
81 | .pfn = __phys_to_pfn(S3C64XX_PA_VIC0), | ||
82 | .length = SZ_16K, | ||
83 | .type = MT_DEVICE, | ||
84 | }, { | ||
85 | .virtual = (unsigned long)S3C_VA_VIC1, | ||
86 | .pfn = __phys_to_pfn(S3C64XX_PA_VIC1), | ||
87 | .length = SZ_16K, | ||
88 | .type = MT_DEVICE, | ||
89 | }, { | ||
90 | .virtual = (unsigned long)S3C_VA_TIMER, | ||
91 | .pfn = __phys_to_pfn(S3C_PA_TIMER), | ||
92 | .length = SZ_16K, | ||
93 | .type = MT_DEVICE, | ||
94 | }, { | ||
95 | .virtual = (unsigned long)S3C64XX_VA_GPIO, | ||
96 | .pfn = __phys_to_pfn(S3C64XX_PA_GPIO), | ||
97 | .length = SZ_4K, | ||
98 | .type = MT_DEVICE, | ||
99 | }, | ||
100 | }; | ||
101 | |||
102 | /* read cpu identification code */ | ||
103 | |||
104 | void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) | ||
105 | { | ||
106 | unsigned long idcode; | ||
107 | |||
108 | /* initialise the io descriptors we need for initialisation */ | ||
109 | iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); | ||
110 | iotable_init(mach_desc, size); | ||
111 | |||
112 | idcode = __raw_readl(S3C_VA_SYS + 0x118); | ||
113 | s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); | ||
114 | } | ||
diff --git a/arch/arm/plat-s3c64xx/dev-uart.c b/arch/arm/plat-s3c64xx/dev-uart.c new file mode 100644 index 000000000000..62c11a6fc7ba --- /dev/null +++ b/arch/arm/plat-s3c64xx/dev-uart.c | |||
@@ -0,0 +1,176 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/dev-uart.c | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * Base S3C64XX UART resource and device definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/types.h> | ||
18 | #include <linux/interrupt.h> | ||
19 | #include <linux/list.h> | ||
20 | #include <linux/platform_device.h> | ||
21 | |||
22 | #include <asm/mach/arch.h> | ||
23 | #include <asm/mach/irq.h> | ||
24 | #include <mach/hardware.h> | ||
25 | #include <mach/map.h> | ||
26 | |||
27 | #include <plat/devs.h> | ||
28 | |||
29 | /* Serial port registrations */ | ||
30 | |||
31 | /* 64xx uarts are closer together */ | ||
32 | |||
33 | static struct resource s3c64xx_uart0_resource[] = { | ||
34 | [0] = { | ||
35 | .start = S3C_PA_UART0, | ||
36 | .end = S3C_PA_UART0 + 0x100, | ||
37 | .flags = IORESOURCE_MEM, | ||
38 | }, | ||
39 | [1] = { | ||
40 | .start = IRQ_S3CUART_RX0, | ||
41 | .end = IRQ_S3CUART_RX0, | ||
42 | .flags = IORESOURCE_IRQ, | ||
43 | }, | ||
44 | [2] = { | ||
45 | .start = IRQ_S3CUART_TX0, | ||
46 | .end = IRQ_S3CUART_TX0, | ||
47 | .flags = IORESOURCE_IRQ, | ||
48 | |||
49 | }, | ||
50 | [3] = { | ||
51 | .start = IRQ_S3CUART_ERR0, | ||
52 | .end = IRQ_S3CUART_ERR0, | ||
53 | .flags = IORESOURCE_IRQ, | ||
54 | } | ||
55 | }; | ||
56 | |||
57 | static struct resource s3c64xx_uart1_resource[] = { | ||
58 | [0] = { | ||
59 | .start = S3C_PA_UART1, | ||
60 | .end = S3C_PA_UART1 + 0x100, | ||
61 | .flags = IORESOURCE_MEM, | ||
62 | }, | ||
63 | [1] = { | ||
64 | .start = IRQ_S3CUART_RX1, | ||
65 | .end = IRQ_S3CUART_RX1, | ||
66 | .flags = IORESOURCE_IRQ, | ||
67 | }, | ||
68 | [2] = { | ||
69 | .start = IRQ_S3CUART_TX1, | ||
70 | .end = IRQ_S3CUART_TX1, | ||
71 | .flags = IORESOURCE_IRQ, | ||
72 | |||
73 | }, | ||
74 | [3] = { | ||
75 | .start = IRQ_S3CUART_ERR1, | ||
76 | .end = IRQ_S3CUART_ERR1, | ||
77 | .flags = IORESOURCE_IRQ, | ||
78 | }, | ||
79 | }; | ||
80 | |||
81 | static struct resource s3c6xx_uart2_resource[] = { | ||
82 | [0] = { | ||
83 | .start = S3C_PA_UART2, | ||
84 | .end = S3C_PA_UART2 + 0x100, | ||
85 | .flags = IORESOURCE_MEM, | ||
86 | }, | ||
87 | [1] = { | ||
88 | .start = IRQ_S3CUART_RX2, | ||
89 | .end = IRQ_S3CUART_RX2, | ||
90 | .flags = IORESOURCE_IRQ, | ||
91 | }, | ||
92 | [2] = { | ||
93 | .start = IRQ_S3CUART_TX2, | ||
94 | .end = IRQ_S3CUART_TX2, | ||
95 | .flags = IORESOURCE_IRQ, | ||
96 | |||
97 | }, | ||
98 | [3] = { | ||
99 | .start = IRQ_S3CUART_ERR2, | ||
100 | .end = IRQ_S3CUART_ERR2, | ||
101 | .flags = IORESOURCE_IRQ, | ||
102 | }, | ||
103 | }; | ||
104 | |||
105 | static struct resource s3c64xx_uart3_resource[] = { | ||
106 | [0] = { | ||
107 | .start = S3C_PA_UART3, | ||
108 | .end = S3C_PA_UART3 + 0x100, | ||
109 | .flags = IORESOURCE_MEM, | ||
110 | }, | ||
111 | [1] = { | ||
112 | .start = IRQ_S3CUART_RX3, | ||
113 | .end = IRQ_S3CUART_RX3, | ||
114 | .flags = IORESOURCE_IRQ, | ||
115 | }, | ||
116 | [2] = { | ||
117 | .start = IRQ_S3CUART_TX3, | ||
118 | .end = IRQ_S3CUART_TX3, | ||
119 | .flags = IORESOURCE_IRQ, | ||
120 | |||
121 | }, | ||
122 | [3] = { | ||
123 | .start = IRQ_S3CUART_ERR3, | ||
124 | .end = IRQ_S3CUART_ERR3, | ||
125 | .flags = IORESOURCE_IRQ, | ||
126 | }, | ||
127 | }; | ||
128 | |||
129 | |||
130 | struct s3c24xx_uart_resources s3c64xx_uart_resources[] __initdata = { | ||
131 | [0] = { | ||
132 | .resources = s3c64xx_uart0_resource, | ||
133 | .nr_resources = ARRAY_SIZE(s3c64xx_uart0_resource), | ||
134 | }, | ||
135 | [1] = { | ||
136 | .resources = s3c64xx_uart1_resource, | ||
137 | .nr_resources = ARRAY_SIZE(s3c64xx_uart1_resource), | ||
138 | }, | ||
139 | [2] = { | ||
140 | .resources = s3c6xx_uart2_resource, | ||
141 | .nr_resources = ARRAY_SIZE(s3c6xx_uart2_resource), | ||
142 | }, | ||
143 | [3] = { | ||
144 | .resources = s3c64xx_uart3_resource, | ||
145 | .nr_resources = ARRAY_SIZE(s3c64xx_uart3_resource), | ||
146 | }, | ||
147 | }; | ||
148 | |||
149 | /* uart devices */ | ||
150 | |||
151 | static struct platform_device s3c24xx_uart_device0 = { | ||
152 | .id = 0, | ||
153 | }; | ||
154 | |||
155 | static struct platform_device s3c24xx_uart_device1 = { | ||
156 | .id = 1, | ||
157 | }; | ||
158 | |||
159 | static struct platform_device s3c24xx_uart_device2 = { | ||
160 | .id = 2, | ||
161 | }; | ||
162 | |||
163 | static struct platform_device s3c24xx_uart_device3 = { | ||
164 | .id = 3, | ||
165 | }; | ||
166 | |||
167 | struct platform_device *s3c24xx_uart_src[4] = { | ||
168 | &s3c24xx_uart_device0, | ||
169 | &s3c24xx_uart_device1, | ||
170 | &s3c24xx_uart_device2, | ||
171 | &s3c24xx_uart_device3, | ||
172 | }; | ||
173 | |||
174 | struct platform_device *s3c24xx_uart_devs[4] = { | ||
175 | }; | ||
176 | |||
diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c new file mode 100644 index 000000000000..cc62941d7b5c --- /dev/null +++ b/arch/arm/plat-s3c64xx/gpiolib.c | |||
@@ -0,0 +1,420 @@ | |||
1 | /* arch/arm/plat-s3c64xx/gpiolib.c | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C64XX - GPIOlib support | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/irq.h> | ||
17 | #include <linux/io.h> | ||
18 | |||
19 | #include <mach/map.h> | ||
20 | #include <mach/gpio.h> | ||
21 | #include <mach/gpio-core.h> | ||
22 | |||
23 | #include <plat/gpio-cfg.h> | ||
24 | #include <plat/gpio-cfg-helpers.h> | ||
25 | #include <plat/regs-gpio.h> | ||
26 | |||
27 | /* GPIO bank summary: | ||
28 | * | ||
29 | * Bank GPIOs Style SlpCon ExtInt Group | ||
30 | * A 8 4Bit Yes 1 | ||
31 | * B 7 4Bit Yes 1 | ||
32 | * C 8 4Bit Yes 2 | ||
33 | * D 5 4Bit Yes 3 | ||
34 | * E 5 4Bit Yes None | ||
35 | * F 16 2Bit Yes 4 [1] | ||
36 | * G 7 4Bit Yes 5 | ||
37 | * H 10 4Bit[2] Yes 6 | ||
38 | * I 16 2Bit Yes None | ||
39 | * J 12 2Bit Yes None | ||
40 | * K 16 4Bit[2] No None | ||
41 | * L 15 4Bit[2] No None | ||
42 | * M 6 4Bit No IRQ_EINT | ||
43 | * N 16 2Bit No IRQ_EINT | ||
44 | * O 16 2Bit Yes 7 | ||
45 | * P 15 2Bit Yes 8 | ||
46 | * Q 9 2Bit Yes 9 | ||
47 | * | ||
48 | * [1] BANKF pins 14,15 do not form part of the external interrupt sources | ||
49 | * [2] BANK has two control registers, GPxCON0 and GPxCON1 | ||
50 | */ | ||
51 | |||
52 | #define OFF_GPCON (0x00) | ||
53 | #define OFF_GPDAT (0x04) | ||
54 | |||
55 | #define con_4bit_shift(__off) ((__off) * 4) | ||
56 | |||
57 | #if 1 | ||
58 | #define gpio_dbg(x...) do { } while(0) | ||
59 | #else | ||
60 | #define gpio_dbg(x...) printk(KERN_DEBUG ## x) | ||
61 | #endif | ||
62 | |||
63 | /* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where | ||
64 | * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the | ||
65 | * following example: | ||
66 | * | ||
67 | * base + 0x00: Control register, 4 bits per gpio | ||
68 | * gpio n: 4 bits starting at (4*n) | ||
69 | * 0000 = input, 0001 = output, others mean special-function | ||
70 | * base + 0x04: Data register, 1 bit per gpio | ||
71 | * bit n: data bit n | ||
72 | * | ||
73 | * Note, since the data register is one bit per gpio and is at base + 0x4 | ||
74 | * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of | ||
75 | * the output. | ||
76 | */ | ||
77 | |||
78 | static int s3c64xx_gpiolib_4bit_input(struct gpio_chip *chip, unsigned offset) | ||
79 | { | ||
80 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
81 | void __iomem *base = ourchip->base; | ||
82 | unsigned long con; | ||
83 | |||
84 | con = __raw_readl(base + OFF_GPCON); | ||
85 | con &= ~(0xf << con_4bit_shift(offset)); | ||
86 | __raw_writel(con, base + OFF_GPCON); | ||
87 | |||
88 | gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con); | ||
89 | |||
90 | return 0; | ||
91 | } | ||
92 | |||
93 | static int s3c64xx_gpiolib_4bit_output(struct gpio_chip *chip, | ||
94 | unsigned offset, int value) | ||
95 | { | ||
96 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
97 | void __iomem *base = ourchip->base; | ||
98 | unsigned long con; | ||
99 | unsigned long dat; | ||
100 | |||
101 | con = __raw_readl(base + OFF_GPCON); | ||
102 | con &= ~(0xf << con_4bit_shift(offset)); | ||
103 | con |= 0x1 << con_4bit_shift(offset); | ||
104 | |||
105 | dat = __raw_readl(base + OFF_GPDAT); | ||
106 | if (value) | ||
107 | dat |= 1 << offset; | ||
108 | else | ||
109 | dat &= ~(1 << offset); | ||
110 | |||
111 | __raw_writel(dat, base + OFF_GPDAT); | ||
112 | __raw_writel(con, base + OFF_GPCON); | ||
113 | __raw_writel(dat, base + OFF_GPDAT); | ||
114 | |||
115 | gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); | ||
116 | |||
117 | return 0; | ||
118 | } | ||
119 | |||
120 | /* The next set of routines are for the case where the GPIO configuration | ||
121 | * registers are 4 bits per GPIO but there is more than one register (the | ||
122 | * bank has more than 8 GPIOs. | ||
123 | * | ||
124 | * This case is the similar to the 4 bit case, but the registers are as | ||
125 | * follows: | ||
126 | * | ||
127 | * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs) | ||
128 | * gpio n: 4 bits starting at (4*n) | ||
129 | * 0000 = input, 0001 = output, others mean special-function | ||
130 | * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs) | ||
131 | * gpio n: 4 bits starting at (4*n) | ||
132 | * 0000 = input, 0001 = output, others mean special-function | ||
133 | * base + 0x08: Data register, 1 bit per gpio | ||
134 | * bit n: data bit n | ||
135 | * | ||
136 | * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we | ||
137 | * store the 'base + 0x4' address so that these routines see the data | ||
138 | * register at ourchip->base + 0x04. | ||
139 | */ | ||
140 | |||
141 | static int s3c64xx_gpiolib_4bit2_input(struct gpio_chip *chip, unsigned offset) | ||
142 | { | ||
143 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
144 | void __iomem *base = ourchip->base; | ||
145 | void __iomem *regcon = base; | ||
146 | unsigned long con; | ||
147 | |||
148 | if (offset > 7) | ||
149 | offset -= 8; | ||
150 | else | ||
151 | regcon -= 4; | ||
152 | |||
153 | con = __raw_readl(regcon); | ||
154 | con &= ~(0xf << con_4bit_shift(offset)); | ||
155 | __raw_writel(con, regcon); | ||
156 | |||
157 | gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con); | ||
158 | |||
159 | return 0; | ||
160 | |||
161 | } | ||
162 | |||
163 | static int s3c64xx_gpiolib_4bit2_output(struct gpio_chip *chip, | ||
164 | unsigned offset, int value) | ||
165 | { | ||
166 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
167 | void __iomem *base = ourchip->base; | ||
168 | void __iomem *regcon = base; | ||
169 | unsigned long con; | ||
170 | unsigned long dat; | ||
171 | |||
172 | if (offset > 7) | ||
173 | offset -= 8; | ||
174 | else | ||
175 | regcon -= 4; | ||
176 | |||
177 | con = __raw_readl(regcon); | ||
178 | con &= ~(0xf << con_4bit_shift(offset)); | ||
179 | con |= 0x1 << con_4bit_shift(offset); | ||
180 | |||
181 | dat = __raw_readl(base + OFF_GPDAT); | ||
182 | if (value) | ||
183 | dat |= 1 << offset; | ||
184 | else | ||
185 | dat &= ~(1 << offset); | ||
186 | |||
187 | __raw_writel(dat, base + OFF_GPDAT); | ||
188 | __raw_writel(con, regcon); | ||
189 | __raw_writel(dat, base + OFF_GPDAT); | ||
190 | |||
191 | gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat); | ||
192 | |||
193 | return 0; | ||
194 | } | ||
195 | |||
196 | static struct s3c_gpio_cfg gpio_4bit_cfg_noint = { | ||
197 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | ||
198 | .set_pull = s3c_gpio_setpull_updown, | ||
199 | .get_pull = s3c_gpio_getpull_updown, | ||
200 | }; | ||
201 | |||
202 | static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = { | ||
203 | .cfg_eint = 7, | ||
204 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | ||
205 | .set_pull = s3c_gpio_setpull_updown, | ||
206 | .get_pull = s3c_gpio_getpull_updown, | ||
207 | }; | ||
208 | |||
209 | static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = { | ||
210 | .cfg_eint = 3, | ||
211 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | ||
212 | .set_pull = s3c_gpio_setpull_updown, | ||
213 | .get_pull = s3c_gpio_getpull_updown, | ||
214 | }; | ||
215 | |||
216 | static struct s3c_gpio_chip gpio_4bit[] = { | ||
217 | { | ||
218 | .base = S3C64XX_GPA_BASE, | ||
219 | .config = &gpio_4bit_cfg_eint0111, | ||
220 | .chip = { | ||
221 | .base = S3C64XX_GPA(0), | ||
222 | .ngpio = S3C64XX_GPIO_A_NR, | ||
223 | .label = "GPA", | ||
224 | }, | ||
225 | }, { | ||
226 | .base = S3C64XX_GPB_BASE, | ||
227 | .config = &gpio_4bit_cfg_eint0111, | ||
228 | .chip = { | ||
229 | .base = S3C64XX_GPB(0), | ||
230 | .ngpio = S3C64XX_GPIO_B_NR, | ||
231 | .label = "GPB", | ||
232 | }, | ||
233 | }, { | ||
234 | .base = S3C64XX_GPC_BASE, | ||
235 | .config = &gpio_4bit_cfg_eint0111, | ||
236 | .chip = { | ||
237 | .base = S3C64XX_GPC(0), | ||
238 | .ngpio = S3C64XX_GPIO_C_NR, | ||
239 | .label = "GPC", | ||
240 | }, | ||
241 | }, { | ||
242 | .base = S3C64XX_GPD_BASE, | ||
243 | .config = &gpio_4bit_cfg_eint0111, | ||
244 | .chip = { | ||
245 | .base = S3C64XX_GPD(0), | ||
246 | .ngpio = S3C64XX_GPIO_D_NR, | ||
247 | .label = "GPD", | ||
248 | }, | ||
249 | }, { | ||
250 | .base = S3C64XX_GPE_BASE, | ||
251 | .config = &gpio_4bit_cfg_noint, | ||
252 | .chip = { | ||
253 | .base = S3C64XX_GPE(0), | ||
254 | .ngpio = S3C64XX_GPIO_E_NR, | ||
255 | .label = "GPE", | ||
256 | }, | ||
257 | }, { | ||
258 | .base = S3C64XX_GPG_BASE, | ||
259 | .config = &gpio_4bit_cfg_eint0111, | ||
260 | .chip = { | ||
261 | .base = S3C64XX_GPG(0), | ||
262 | .ngpio = S3C64XX_GPIO_G_NR, | ||
263 | .label = "GPG", | ||
264 | }, | ||
265 | }, { | ||
266 | .base = S3C64XX_GPM_BASE, | ||
267 | .config = &gpio_4bit_cfg_eint0011, | ||
268 | .chip = { | ||
269 | .base = S3C64XX_GPM(0), | ||
270 | .ngpio = S3C64XX_GPIO_M_NR, | ||
271 | .label = "GPM", | ||
272 | }, | ||
273 | }, | ||
274 | }; | ||
275 | |||
276 | static struct s3c_gpio_chip gpio_4bit2[] = { | ||
277 | { | ||
278 | .base = S3C64XX_GPH_BASE + 0x4, | ||
279 | .config = &gpio_4bit_cfg_eint0111, | ||
280 | .chip = { | ||
281 | .base = S3C64XX_GPH(0), | ||
282 | .ngpio = S3C64XX_GPIO_H_NR, | ||
283 | .label = "GPH", | ||
284 | }, | ||
285 | }, { | ||
286 | .base = S3C64XX_GPK_BASE + 0x4, | ||
287 | .config = &gpio_4bit_cfg_noint, | ||
288 | .chip = { | ||
289 | .base = S3C64XX_GPK(0), | ||
290 | .ngpio = S3C64XX_GPIO_K_NR, | ||
291 | .label = "GPK", | ||
292 | }, | ||
293 | }, { | ||
294 | .base = S3C64XX_GPL_BASE + 0x4, | ||
295 | .config = &gpio_4bit_cfg_eint0011, | ||
296 | .chip = { | ||
297 | .base = S3C64XX_GPL(0), | ||
298 | .ngpio = S3C64XX_GPIO_L_NR, | ||
299 | .label = "GPL", | ||
300 | }, | ||
301 | }, | ||
302 | }; | ||
303 | |||
304 | static struct s3c_gpio_cfg gpio_2bit_cfg_noint = { | ||
305 | .set_config = s3c_gpio_setcfg_s3c24xx, | ||
306 | .set_pull = s3c_gpio_setpull_updown, | ||
307 | .get_pull = s3c_gpio_getpull_updown, | ||
308 | }; | ||
309 | |||
310 | static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = { | ||
311 | .cfg_eint = 2, | ||
312 | .set_config = s3c_gpio_setcfg_s3c24xx, | ||
313 | .set_pull = s3c_gpio_setpull_updown, | ||
314 | .get_pull = s3c_gpio_getpull_updown, | ||
315 | }; | ||
316 | |||
317 | static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = { | ||
318 | .cfg_eint = 3, | ||
319 | .set_config = s3c_gpio_setcfg_s3c24xx, | ||
320 | .set_pull = s3c_gpio_setpull_updown, | ||
321 | .get_pull = s3c_gpio_getpull_updown, | ||
322 | }; | ||
323 | |||
324 | static struct s3c_gpio_chip gpio_2bit[] = { | ||
325 | { | ||
326 | .base = S3C64XX_GPF_BASE, | ||
327 | .config = &gpio_2bit_cfg_eint11, | ||
328 | .chip = { | ||
329 | .base = S3C64XX_GPF(0), | ||
330 | .ngpio = S3C64XX_GPIO_F_NR, | ||
331 | .label = "GPF", | ||
332 | }, | ||
333 | }, { | ||
334 | .base = S3C64XX_GPI_BASE, | ||
335 | .config = &gpio_2bit_cfg_noint, | ||
336 | .chip = { | ||
337 | .base = S3C64XX_GPI(0), | ||
338 | .ngpio = S3C64XX_GPIO_I_NR, | ||
339 | .label = "GPI", | ||
340 | }, | ||
341 | }, { | ||
342 | .base = S3C64XX_GPJ_BASE, | ||
343 | .config = &gpio_2bit_cfg_noint, | ||
344 | .chip = { | ||
345 | .base = S3C64XX_GPJ(0), | ||
346 | .ngpio = S3C64XX_GPIO_J_NR, | ||
347 | .label = "GPJ", | ||
348 | }, | ||
349 | }, { | ||
350 | .base = S3C64XX_GPN_BASE, | ||
351 | .config = &gpio_2bit_cfg_eint10, | ||
352 | .chip = { | ||
353 | .base = S3C64XX_GPN(0), | ||
354 | .ngpio = S3C64XX_GPIO_N_NR, | ||
355 | .label = "GPN", | ||
356 | }, | ||
357 | }, { | ||
358 | .base = S3C64XX_GPO_BASE, | ||
359 | .config = &gpio_2bit_cfg_eint11, | ||
360 | .chip = { | ||
361 | .base = S3C64XX_GPO(0), | ||
362 | .ngpio = S3C64XX_GPIO_O_NR, | ||
363 | .label = "GPO", | ||
364 | }, | ||
365 | }, { | ||
366 | .base = S3C64XX_GPP_BASE, | ||
367 | .config = &gpio_2bit_cfg_eint11, | ||
368 | .chip = { | ||
369 | .base = S3C64XX_GPP(0), | ||
370 | .ngpio = S3C64XX_GPIO_P_NR, | ||
371 | .label = "GPP", | ||
372 | }, | ||
373 | }, { | ||
374 | .base = S3C64XX_GPQ_BASE, | ||
375 | .config = &gpio_2bit_cfg_eint11, | ||
376 | .chip = { | ||
377 | .base = S3C64XX_GPQ(0), | ||
378 | .ngpio = S3C64XX_GPIO_Q_NR, | ||
379 | .label = "GPQ", | ||
380 | }, | ||
381 | }, | ||
382 | }; | ||
383 | |||
384 | static __init void s3c64xx_gpiolib_add_4bit(struct s3c_gpio_chip *chip) | ||
385 | { | ||
386 | chip->chip.direction_input = s3c64xx_gpiolib_4bit_input; | ||
387 | chip->chip.direction_output = s3c64xx_gpiolib_4bit_output; | ||
388 | } | ||
389 | |||
390 | static __init void s3c64xx_gpiolib_add_4bit2(struct s3c_gpio_chip *chip) | ||
391 | { | ||
392 | chip->chip.direction_input = s3c64xx_gpiolib_4bit2_input; | ||
393 | chip->chip.direction_output = s3c64xx_gpiolib_4bit2_output; | ||
394 | } | ||
395 | |||
396 | static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips, | ||
397 | int nr_chips, | ||
398 | void (*fn)(struct s3c_gpio_chip *)) | ||
399 | { | ||
400 | for (; nr_chips > 0; nr_chips--, chips++) { | ||
401 | if (fn) | ||
402 | (fn)(chips); | ||
403 | s3c_gpiolib_add(chips); | ||
404 | } | ||
405 | } | ||
406 | |||
407 | static __init int s3c64xx_gpiolib_init(void) | ||
408 | { | ||
409 | s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit), | ||
410 | s3c64xx_gpiolib_add_4bit); | ||
411 | |||
412 | s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2), | ||
413 | s3c64xx_gpiolib_add_4bit2); | ||
414 | |||
415 | s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), NULL); | ||
416 | |||
417 | return 0; | ||
418 | } | ||
419 | |||
420 | arch_initcall(s3c64xx_gpiolib_init); | ||
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h new file mode 100644 index 000000000000..9aa0e427d113 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h | |||
@@ -0,0 +1,48 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-a.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank A register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPACON (S3C64XX_GPA_BASE + 0x00) | ||
16 | #define S3C64XX_GPADAT (S3C64XX_GPA_BASE + 0x04) | ||
17 | #define S3C64XX_GPAPUD (S3C64XX_GPA_BASE + 0x08) | ||
18 | #define S3C64XX_GPACONSLP (S3C64XX_GPA_BASE + 0x0c) | ||
19 | #define S3C64XX_GPAPUDSLP (S3C64XX_GPA_BASE + 0x10) | ||
20 | |||
21 | #define S3C64XX_GPA_CONMASK(__gpio) (0xf << ((__gpio) * 4)) | ||
22 | #define S3C64XX_GPA_INPUT(__gpio) (0x0 << ((__gpio) * 4)) | ||
23 | #define S3C64XX_GPA_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) | ||
24 | |||
25 | #define S3C64XX_GPA0_UART_RXD0 (0x02 << 0) | ||
26 | #define S3C64XX_GPA0_EINT_G1_0 (0x07 << 0) | ||
27 | |||
28 | #define S3C64XX_GPA1_UART_TXD0 (0x02 << 4) | ||
29 | #define S3C64XX_GPA1_EINT_G1_1 (0x07 << 4) | ||
30 | |||
31 | #define S3C64XX_GPA2_UART_nCTS0 (0x02 << 8) | ||
32 | #define S3C64XX_GPA2_EINT_G1_2 (0x07 << 8) | ||
33 | |||
34 | #define S3C64XX_GPA3_UART_nRTS0 (0x02 << 12) | ||
35 | #define S3C64XX_GPA3_EINT_G1_3 (0x07 << 12) | ||
36 | |||
37 | #define S3C64XX_GPA4_UART_RXD1 (0x02 << 16) | ||
38 | #define S3C64XX_GPA4_EINT_G1_4 (0x07 << 16) | ||
39 | |||
40 | #define S3C64XX_GPA5_UART_TXD1 (0x02 << 20) | ||
41 | #define S3C64XX_GPA5_EINT_G1_5 (0x07 << 20) | ||
42 | |||
43 | #define S3C64XX_GPA6_UART_nCTS1 (0x02 << 24) | ||
44 | #define S3C64XX_GPA6_EINT_G1_6 (0x07 << 24) | ||
45 | |||
46 | #define S3C64XX_GPA7_UART_nRTS1 (0x02 << 28) | ||
47 | #define S3C64XX_GPA7_EINT_G1_7 (0x07 << 28) | ||
48 | |||
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h new file mode 100644 index 000000000000..3933adb4d50a --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h | |||
@@ -0,0 +1,60 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-b.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank B register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPBCON (S3C64XX_GPB_BASE + 0x00) | ||
16 | #define S3C64XX_GPBDAT (S3C64XX_GPB_BASE + 0x04) | ||
17 | #define S3C64XX_GPBPUD (S3C64XX_GPB_BASE + 0x08) | ||
18 | #define S3C64XX_GPBCONSLP (S3C64XX_GPB_BASE + 0x0c) | ||
19 | #define S3C64XX_GPBPUDSLP (S3C64XX_GPB_BASE + 0x10) | ||
20 | |||
21 | #define S3C64XX_GPB_CONMASK(__gpio) (0xf << ((__gpio) * 4)) | ||
22 | #define S3C64XX_GPB_INPUT(__gpio) (0x0 << ((__gpio) * 4)) | ||
23 | #define S3C64XX_GPB_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) | ||
24 | |||
25 | #define S3C64XX_GPB0_UART_RXD2 (0x02 << 0) | ||
26 | #define S3C64XX_GPB0_EXTDMA_REQ (0x03 << 0) | ||
27 | #define S3C64XX_GPB0_IrDA_RXD (0x04 << 0) | ||
28 | #define S3C64XX_GPB0_ADDR_CF0 (0x05 << 0) | ||
29 | #define S3C64XX_GPB0_EINT_G1_8 (0x07 << 0) | ||
30 | |||
31 | #define S3C64XX_GPB1_UART_TXD2 (0x02 << 4) | ||
32 | #define S3C64XX_GPB1_EXTDMA_ACK (0x03 << 4) | ||
33 | #define S3C64XX_GPB1_IrDA_TXD (0x04 << 4) | ||
34 | #define S3C64XX_GPB1_ADDR_CF1 (0x05 << 4) | ||
35 | #define S3C64XX_GPB1_EINT_G1_9 (0x07 << 4) | ||
36 | |||
37 | #define S3C64XX_GPB2_UART_RXD3 (0x02 << 8) | ||
38 | #define S3C64XX_GPB2_IrDA_RXD (0x03 << 8) | ||
39 | #define S3C64XX_GPB2_EXTDMA_REQ (0x04 << 8) | ||
40 | #define S3C64XX_GPB2_ADDR_CF2 (0x05 << 8) | ||
41 | #define S3C64XX_GPB2_I2C_SCL1 (0x06 << 8) | ||
42 | #define S3C64XX_GPB2_EINT_G1_10 (0x07 << 8) | ||
43 | |||
44 | #define S3C64XX_GPB3_UART_TXD3 (0x02 << 12) | ||
45 | #define S3C64XX_GPB3_IrDA_TXD (0x03 << 12) | ||
46 | #define S3C64XX_GPB3_EXTDMA_ACK (0x04 << 12) | ||
47 | #define S3C64XX_GPB3_I2C_SDA1 (0x06 << 12) | ||
48 | #define S3C64XX_GPB3_EINT_G1_11 (0x07 << 12) | ||
49 | |||
50 | #define S3C64XX_GPB4_IrDA_SDBW (0x02 << 16) | ||
51 | #define S3C64XX_GPB4_CAM_FIELD (0x03 << 16) | ||
52 | #define S3C64XX_GPB4_CF_DATA_DIR (0x04 << 16) | ||
53 | #define S3C64XX_GPB4_EINT_G1_12 (0x07 << 16) | ||
54 | |||
55 | #define S3C64XX_GPB5_I2C_SCL0 (0x02 << 20) | ||
56 | #define S3C64XX_GPB5_EINT_G1_13 (0x07 << 20) | ||
57 | |||
58 | #define S3C64XX_GPB6_I2C_SDA0 (0x02 << 24) | ||
59 | #define S3C64XX_GPB6_EINT_G1_14 (0x07 << 24) | ||
60 | |||
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h new file mode 100644 index 000000000000..c47daf7e2723 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h | |||
@@ -0,0 +1,53 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-c.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank C register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPCCON (S3C64XX_GPC_BASE + 0x00) | ||
16 | #define S3C64XX_GPCDAT (S3C64XX_GPC_BASE + 0x04) | ||
17 | #define S3C64XX_GPCPUD (S3C64XX_GPC_BASE + 0x08) | ||
18 | #define S3C64XX_GPCCONSLP (S3C64XX_GPC_BASE + 0x0c) | ||
19 | #define S3C64XX_GPCPUDSLP (S3C64XX_GPC_BASE + 0x10) | ||
20 | |||
21 | #define S3C64XX_GPC_CONMASK(__gpio) (0xf << ((__gpio) * 4)) | ||
22 | #define S3C64XX_GPC_INPUT(__gpio) (0x0 << ((__gpio) * 4)) | ||
23 | #define S3C64XX_GPC_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) | ||
24 | |||
25 | #define S3C64XX_GPC0_SPI_MISO0 (0x02 << 0) | ||
26 | #define S3C64XX_GPC0_EINT_G2_0 (0x07 << 0) | ||
27 | |||
28 | #define S3C64XX_GPC1_SPI_CLKO (0x02 << 4) | ||
29 | #define S3C64XX_GPC1_EINT_G2_1 (0x07 << 4) | ||
30 | |||
31 | #define S3C64XX_GPC2_SPI_MOSIO (0x02 << 8) | ||
32 | #define S3C64XX_GPC2_EINT_G2_2 (0x07 << 8) | ||
33 | |||
34 | #define S3C64XX_GPC3_SPI_nCSO (0x02 << 12) | ||
35 | #define S3C64XX_GPC3_EINT_G2_3 (0x07 << 12) | ||
36 | |||
37 | #define S3C64XX_GPC4_SPI_MISO1 (0x02 << 16) | ||
38 | #define S3C64XX_GPC4_MMC2_CMD (0x03 << 16) | ||
39 | #define S3C64XX_GPC4_I2S0_V40_DO (0x05 << 16) | ||
40 | #define S3C64XX_GPC4_EINT_G2_4 (0x07 << 16) | ||
41 | |||
42 | #define S3C64XX_GPC5_SPI_CLK1 (0x02 << 20) | ||
43 | #define S3C64XX_GPC5_MMC2_CLK (0x03 << 20) | ||
44 | #define S3C64XX_GPC5_I2S1_V40_DO (0x05 << 20) | ||
45 | #define S3C64XX_GPC5_EINT_G2_5 (0x07 << 20) | ||
46 | |||
47 | #define S3C64XX_GPC6_SPI_MOSI1 (0x02 << 24) | ||
48 | #define S3C64XX_GPC6_EINT_G2_6 (0x07 << 24) | ||
49 | |||
50 | #define S3C64XX_GPC7_SPI_nCS1 (0x02 << 28) | ||
51 | #define S3C64XX_GPC7_I2S2_V40_DO (0x05 << 28) | ||
52 | #define S3C64XX_GPC7_EINT_G2_7 (0x07 << 28) | ||
53 | |||
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h new file mode 100644 index 000000000000..6fe4a49c26f0 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h | |||
@@ -0,0 +1,49 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-d.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank D register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPDCON (S3C64XX_GPD_BASE + 0x00) | ||
16 | #define S3C64XX_GPDDAT (S3C64XX_GPD_BASE + 0x04) | ||
17 | #define S3C64XX_GPDPUD (S3C64XX_GPD_BASE + 0x08) | ||
18 | #define S3C64XX_GPDCONSLP (S3C64XX_GPD_BASE + 0x0c) | ||
19 | #define S3C64XX_GPDPUDSLP (S3C64XX_GPD_BASE + 0x10) | ||
20 | |||
21 | #define S3C64XX_GPD_CONMASK(__gpio) (0xf << ((__gpio) * 4)) | ||
22 | #define S3C64XX_GPD_INPUT(__gpio) (0x0 << ((__gpio) * 4)) | ||
23 | #define S3C64XX_GPD_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) | ||
24 | |||
25 | #define S3C64XX_GPD0_PCM0_SCLK (0x02 << 0) | ||
26 | #define S3C64XX_GPD0_I2S0_CLK (0x03 << 0) | ||
27 | #define S3C64XX_GPD0_AC97_BITCLK (0x04 << 0) | ||
28 | #define S3C64XX_GPD0_EINT_G3_0 (0x07 << 0) | ||
29 | |||
30 | #define S3C64XX_GPD1_PCM0_EXTCLK (0x02 << 4) | ||
31 | #define S3C64XX_GPD1_I2S0_CDCLK (0x03 << 4) | ||
32 | #define S3C64XX_GPD1_AC97_nRESET (0x04 << 4) | ||
33 | #define S3C64XX_GPD1_EINT_G3_1 (0x07 << 4) | ||
34 | |||
35 | #define S3C64XX_GPD2_PCM0_FSYNC (0x02 << 8) | ||
36 | #define S3C64XX_GPD2_I2S0_LRCLK (0x03 << 8) | ||
37 | #define S3C64XX_GPD2_AC97_SYNC (0x04 << 8) | ||
38 | #define S3C64XX_GPD2_EINT_G3_2 (0x07 << 8) | ||
39 | |||
40 | #define S3C64XX_GPD3_PCM0_SIN (0x02 << 12) | ||
41 | #define S3C64XX_GPD3_I2S0_DI (0x03 << 12) | ||
42 | #define S3C64XX_GPD3_AC97_SDI (0x04 << 12) | ||
43 | #define S3C64XX_GPD3_EINT_G3_3 (0x07 << 12) | ||
44 | |||
45 | #define S3C64XX_GPD4_PCM0_SOUT (0x02 << 16) | ||
46 | #define S3C64XX_GPD4_I2S0_D0 (0x03 << 16) | ||
47 | #define S3C64XX_GPD4_AC97_SDO (0x04 << 16) | ||
48 | #define S3C64XX_GPD4_EINT_G3_4 (0x07 << 16) | ||
49 | |||
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h new file mode 100644 index 000000000000..7fcf3d8e0a48 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h | |||
@@ -0,0 +1,44 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-e.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank E register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPECON (S3C64XX_GPE_BASE + 0x00) | ||
16 | #define S3C64XX_GPEDAT (S3C64XX_GPE_BASE + 0x04) | ||
17 | #define S3C64XX_GPEPUD (S3C64XX_GPE_BASE + 0x08) | ||
18 | #define S3C64XX_GPECONSLP (S3C64XX_GPE_BASE + 0x0c) | ||
19 | #define S3C64XX_GPEPUDSLP (S3C64XX_GPE_BASE + 0x10) | ||
20 | |||
21 | #define S3C64XX_GPE_CONMASK(__gpio) (0xf << ((__gpio) * 4)) | ||
22 | #define S3C64XX_GPE_INPUT(__gpio) (0x0 << ((__gpio) * 4)) | ||
23 | #define S3C64XX_GPE_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) | ||
24 | |||
25 | #define S3C64XX_GPE0_PCM1_SCLK (0x02 << 0) | ||
26 | #define S3C64XX_GPE0_I2S1_CLK (0x03 << 0) | ||
27 | #define S3C64XX_GPE0_AC97_BITCLK (0x04 << 0) | ||
28 | |||
29 | #define S3C64XX_GPE1_PCM1_EXTCLK (0x02 << 4) | ||
30 | #define S3C64XX_GPE1_I2S1_CDCLK (0x03 << 4) | ||
31 | #define S3C64XX_GPE1_AC97_nRESET (0x04 << 4) | ||
32 | |||
33 | #define S3C64XX_GPE2_PCM1_FSYNC (0x02 << 8) | ||
34 | #define S3C64XX_GPE2_I2S1_LRCLK (0x03 << 8) | ||
35 | #define S3C64XX_GPE2_AC97_SYNC (0x04 << 8) | ||
36 | |||
37 | #define S3C64XX_GPE3_PCM1_SIN (0x02 << 12) | ||
38 | #define S3C64XX_GPE3_I2S1_DI (0x03 << 12) | ||
39 | #define S3C64XX_GPE3_AC97_SDI (0x04 << 12) | ||
40 | |||
41 | #define S3C64XX_GPE4_PCM1_SOUT (0x02 << 16) | ||
42 | #define S3C64XX_GPE4_I2S1_D0 (0x03 << 16) | ||
43 | #define S3C64XX_GPE4_AC97_SDO (0x04 << 16) | ||
44 | |||
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h new file mode 100644 index 000000000000..f3faff974a18 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h | |||
@@ -0,0 +1,71 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-f.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank F register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPFCON (S3C64XX_GPF_BASE + 0x00) | ||
16 | #define S3C64XX_GPFDAT (S3C64XX_GPF_BASE + 0x04) | ||
17 | #define S3C64XX_GPFPUD (S3C64XX_GPF_BASE + 0x08) | ||
18 | #define S3C64XX_GPFCONSLP (S3C64XX_GPF_BASE + 0x0c) | ||
19 | #define S3C64XX_GPFPUDSLP (S3C64XX_GPF_BASE + 0x10) | ||
20 | |||
21 | #define S3C64XX_GPF_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | ||
22 | #define S3C64XX_GPF_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | ||
23 | #define S3C64XX_GPF_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | ||
24 | |||
25 | #define S3C64XX_GPF0_CAMIF_CLK (0x02 << 0) | ||
26 | #define S3C64XX_GPF0_EINT_G4_0 (0x03 << 0) | ||
27 | |||
28 | #define S3C64XX_GPF1_CAMIF_HREF (0x02 << 2) | ||
29 | #define S3C64XX_GPF1_EINT_G4_1 (0x03 << 2) | ||
30 | |||
31 | #define S3C64XX_GPF2_CAMIF_PCLK (0x02 << 4) | ||
32 | #define S3C64XX_GPF2_EINT_G4_2 (0x03 << 4) | ||
33 | |||
34 | #define S3C64XX_GPF3_CAMIF_nRST (0x02 << 6) | ||
35 | #define S3C64XX_GPF3_EINT_G4_3 (0x03 << 6) | ||
36 | |||
37 | #define S3C64XX_GPF4_CAMIF_VSYNC (0x02 << 8) | ||
38 | #define S3C64XX_GPF4_EINT_G4_4 (0x03 << 8) | ||
39 | |||
40 | #define S3C64XX_GPF5_CAMIF_YDATA0 (0x02 << 10) | ||
41 | #define S3C64XX_GPF5_EINT_G4_5 (0x03 << 10) | ||
42 | |||
43 | #define S3C64XX_GPF6_CAMIF_YDATA1 (0x02 << 12) | ||
44 | #define S3C64XX_GPF6_EINT_G4_6 (0x03 << 12) | ||
45 | |||
46 | #define S3C64XX_GPF7_CAMIF_YDATA2 (0x02 << 14) | ||
47 | #define S3C64XX_GPF7_EINT_G4_7 (0x03 << 14) | ||
48 | |||
49 | #define S3C64XX_GPF8_CAMIF_YDATA3 (0x02 << 16) | ||
50 | #define S3C64XX_GPF8_EINT_G4_8 (0x03 << 16) | ||
51 | |||
52 | #define S3C64XX_GPF9_CAMIF_YDATA4 (0x02 << 18) | ||
53 | #define S3C64XX_GPF9_EINT_G4_9 (0x03 << 18) | ||
54 | |||
55 | #define S3C64XX_GPF10_CAMIF_YDATA5 (0x02 << 20) | ||
56 | #define S3C64XX_GPF10_EINT_G4_10 (0x03 << 20) | ||
57 | |||
58 | #define S3C64XX_GPF11_CAMIF_YDATA6 (0x02 << 22) | ||
59 | #define S3C64XX_GPF11_EINT_G4_11 (0x03 << 22) | ||
60 | |||
61 | #define S3C64XX_GPF12_CAMIF_YDATA7 (0x02 << 24) | ||
62 | #define S3C64XX_GPF12_EINT_G4_12 (0x03 << 24) | ||
63 | |||
64 | #define S3C64XX_GPF13_PWM_ECLK (0x02 << 26) | ||
65 | #define S3C64XX_GPF13_EINT_G4_13 (0x03 << 26) | ||
66 | |||
67 | #define S3C64XX_GPF14_PWM_TOUT0 (0x02 << 28) | ||
68 | #define S3C64XX_GPF14_CLKOUT0 (0x03 << 28) | ||
69 | |||
70 | #define S3C64XX_GPF15_PWM_TOUT1 (0x02 << 30) | ||
71 | |||
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h new file mode 100644 index 000000000000..35bbd2378e55 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h | |||
@@ -0,0 +1,42 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-g.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank G register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPGCON (S3C64XX_GPG_BASE + 0x00) | ||
16 | #define S3C64XX_GPGDAT (S3C64XX_GPG_BASE + 0x04) | ||
17 | #define S3C64XX_GPGPUD (S3C64XX_GPG_BASE + 0x08) | ||
18 | #define S3C64XX_GPGCONSLP (S3C64XX_GPG_BASE + 0x0c) | ||
19 | #define S3C64XX_GPGPUDSLP (S3C64XX_GPG_BASE + 0x10) | ||
20 | |||
21 | #define S3C64XX_GPG_CONMASK(__gpio) (0xf << ((__gpio) * 4)) | ||
22 | #define S3C64XX_GPG_INPUT(__gpio) (0x0 << ((__gpio) * 4)) | ||
23 | #define S3C64XX_GPG_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) | ||
24 | |||
25 | #define S3C64XX_GPG0_MMC0_CLK (0x02 << 0) | ||
26 | #define S3C64XX_GPG0_EINT_G5_0 (0x07 << 0) | ||
27 | |||
28 | #define S3C64XX_GPG1_MMC0_CMD (0x02 << 4) | ||
29 | #define S3C64XX_GPG1_EINT_G5_1 (0x07 << 4) | ||
30 | |||
31 | #define S3C64XX_GPG2_MMC0_DATA0 (0x02 << 8) | ||
32 | #define S3C64XX_GPG2_EINT_G5_2 (0x07 << 8) | ||
33 | |||
34 | #define S3C64XX_GPG3_MMC0_DATA1 (0x02 << 12) | ||
35 | #define S3C64XX_GPG3_EINT_G5_3 (0x07 << 12) | ||
36 | |||
37 | #define S3C64XX_GPG4_MMC0_DATA2 (0x02 << 16) | ||
38 | #define S3C64XX_GPG4_EINT_G5_4 (0x07 << 16) | ||
39 | |||
40 | #define S3C64XX_GPG5_MMC0_DATA3 (0x02 << 20) | ||
41 | #define S3C64XX_GPG5_EINT_G5_5 (0x07 << 20) | ||
42 | |||
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h new file mode 100644 index 000000000000..81549516572f --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h | |||
@@ -0,0 +1,74 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank H register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPHCON0 (S3C64XX_GPH_BASE + 0x00) | ||
16 | #define S3C64XX_GPHCON1 (S3C64XX_GPH_BASE + 0x04) | ||
17 | #define S3C64XX_GPHDAT (S3C64XX_GPH_BASE + 0x08) | ||
18 | #define S3C64XX_GPHPUD (S3C64XX_GPH_BASE + 0x0c) | ||
19 | #define S3C64XX_GPHCONSLP (S3C64XX_GPH_BASE + 0x10) | ||
20 | #define S3C64XX_GPHPUDSLP (S3C64XX_GPH_BASE + 0x14) | ||
21 | |||
22 | #define S3C64XX_GPH_CONMASK(__gpio) (0xf << ((__gpio) * 4)) | ||
23 | #define S3C64XX_GPH_INPUT(__gpio) (0x0 << ((__gpio) * 4)) | ||
24 | #define S3C64XX_GPH_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) | ||
25 | |||
26 | #define S3C64XX_GPH0_MMC1_CLK (0x02 << 0) | ||
27 | #define S3C64XX_GPH0_KP_COL0 (0x04 << 0) | ||
28 | #define S3C64XX_GPH0_EINT_G6_0 (0x07 << 0) | ||
29 | |||
30 | #define S3C64XX_GPH1_MMC1_CMD (0x02 << 4) | ||
31 | #define S3C64XX_GPH1_KP_COL1 (0x04 << 4) | ||
32 | #define S3C64XX_GPH1_EINT_G6_1 (0x07 << 4) | ||
33 | |||
34 | #define S3C64XX_GPH2_MMC1_DATA0 (0x02 << 8) | ||
35 | #define S3C64XX_GPH2_KP_COL2 (0x04 << 8) | ||
36 | #define S3C64XX_GPH2_EINT_G6_2 (0x07 << 8) | ||
37 | |||
38 | #define S3C64XX_GPH3_MMC1_DATA1 (0x02 << 12) | ||
39 | #define S3C64XX_GPH3_KP_COL3 (0x04 << 12) | ||
40 | #define S3C64XX_GPH3_EINT_G6_3 (0x07 << 12) | ||
41 | |||
42 | #define S3C64XX_GPH4_MMC1_DATA2 (0x02 << 16) | ||
43 | #define S3C64XX_GPH4_KP_COL4 (0x04 << 16) | ||
44 | #define S3C64XX_GPH4_EINT_G6_4 (0x07 << 16) | ||
45 | |||
46 | #define S3C64XX_GPH5_MMC1_DATA3 (0x02 << 20) | ||
47 | #define S3C64XX_GPH5_KP_COL5 (0x04 << 20) | ||
48 | #define S3C64XX_GPH5_EINT_G6_5 (0x07 << 20) | ||
49 | |||
50 | #define S3C64XX_GPH6_MMC1_DATA4 (0x02 << 24) | ||
51 | #define S3C64XX_GPH6_MMC2_DATA0 (0x03 << 24) | ||
52 | #define S3C64XX_GPH6_KP_COL6 (0x04 << 24) | ||
53 | #define S3C64XX_GPH6_I2S_V40_BCLK (0x05 << 24) | ||
54 | #define S3C64XX_GPH6_ADDR_CF0 (0x06 << 24) | ||
55 | #define S3C64XX_GPH6_EINT_G6_6 (0x07 << 24) | ||
56 | |||
57 | #define S3C64XX_GPH7_MMC1_DATA5 (0x02 << 28) | ||
58 | #define S3C64XX_GPH7_MMC2_DATA1 (0x03 << 28) | ||
59 | #define S3C64XX_GPH7_KP_COL7 (0x04 << 28) | ||
60 | #define S3C64XX_GPH7_I2S_V40_CDCLK (0x05 << 28) | ||
61 | #define S3C64XX_GPH7_ADDR_CF1 (0x06 << 28) | ||
62 | #define S3C64XX_GPH7_EINT_G6_7 (0x07 << 28) | ||
63 | |||
64 | #define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 32) | ||
65 | #define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 32) | ||
66 | #define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 32) | ||
67 | #define S3C64XX_GPH8_ADDR_CF2 (0x06 << 32) | ||
68 | #define S3C64XX_GPH8_EINT_G6_8 (0x07 << 32) | ||
69 | |||
70 | #define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 36) | ||
71 | #define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 36) | ||
72 | #define S3C64XX_GPH9_I2S_V40_DI (0x05 << 36) | ||
73 | #define S3C64XX_GPH9_EINT_G6_9 (0x07 << 36) | ||
74 | |||
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h new file mode 100644 index 000000000000..ce9ebe335566 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h | |||
@@ -0,0 +1,40 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-i.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank I register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPICON (S3C64XX_GPI_BASE + 0x00) | ||
16 | #define S3C64XX_GPIDAT (S3C64XX_GPI_BASE + 0x04) | ||
17 | #define S3C64XX_GPIPUD (S3C64XX_GPI_BASE + 0x08) | ||
18 | #define S3C64XX_GPICONSLP (S3C64XX_GPI_BASE + 0x0c) | ||
19 | #define S3C64XX_GPIPUDSLP (S3C64XX_GPI_BASE + 0x10) | ||
20 | |||
21 | #define S3C64XX_GPI_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | ||
22 | #define S3C64XX_GPI_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | ||
23 | #define S3C64XX_GPI_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | ||
24 | |||
25 | #define S3C64XX_GPI0_VD0 (0x02 << 0) | ||
26 | #define S3C64XX_GPI1_VD1 (0x02 << 2) | ||
27 | #define S3C64XX_GPI2_VD2 (0x02 << 4) | ||
28 | #define S3C64XX_GPI3_VD3 (0x02 << 6) | ||
29 | #define S3C64XX_GPI4_VD4 (0x02 << 8) | ||
30 | #define S3C64XX_GPI5_VD5 (0x02 << 10) | ||
31 | #define S3C64XX_GPI6_VD6 (0x02 << 12) | ||
32 | #define S3C64XX_GPI7_VD7 (0x02 << 14) | ||
33 | #define S3C64XX_GPI8_VD8 (0x02 << 16) | ||
34 | #define S3C64XX_GPI9_VD9 (0x02 << 18) | ||
35 | #define S3C64XX_GPI10_VD10 (0x02 << 20) | ||
36 | #define S3C64XX_GPI11_VD11 (0x02 << 22) | ||
37 | #define S3C64XX_GPI12_VD12 (0x02 << 24) | ||
38 | #define S3C64XX_GPI13_VD13 (0x02 << 26) | ||
39 | #define S3C64XX_GPI14_VD14 (0x02 << 28) | ||
40 | #define S3C64XX_GPI15_VD15 (0x02 << 30) | ||
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h new file mode 100644 index 000000000000..21a906299d30 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h | |||
@@ -0,0 +1,36 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-j.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank J register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPJCON (S3C64XX_GPJ_BASE + 0x00) | ||
16 | #define S3C64XX_GPJDAT (S3C64XX_GPJ_BASE + 0x04) | ||
17 | #define S3C64XX_GPJPUD (S3C64XX_GPJ_BASE + 0x08) | ||
18 | #define S3C64XX_GPJCONSLP (S3C64XX_GPJ_BASE + 0x0c) | ||
19 | #define S3C64XX_GPJPUDSLP (S3C64XX_GPJ_BASE + 0x10) | ||
20 | |||
21 | #define S3C64XX_GPJ_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | ||
22 | #define S3C64XX_GPJ_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | ||
23 | #define S3C64XX_GPJ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | ||
24 | |||
25 | #define S3C64XX_GPJ0_VD16 (0x02 << 0) | ||
26 | #define S3C64XX_GPJ1_VD17 (0x02 << 2) | ||
27 | #define S3C64XX_GPJ2_VD18 (0x02 << 4) | ||
28 | #define S3C64XX_GPJ3_VD19 (0x02 << 6) | ||
29 | #define S3C64XX_GPJ4_VD20 (0x02 << 8) | ||
30 | #define S3C64XX_GPJ5_VD21 (0x02 << 10) | ||
31 | #define S3C64XX_GPJ6_VD22 (0x02 << 12) | ||
32 | #define S3C64XX_GPJ7_VD23 (0x02 << 14) | ||
33 | #define S3C64XX_GPJ8_LCD_HSYNC (0x02 << 16) | ||
34 | #define S3C64XX_GPJ9_LCD_VSYNC (0x02 << 18) | ||
35 | #define S3C64XX_GPJ10_LCD_VDEN (0x02 << 20) | ||
36 | #define S3C64XX_GPJ11_LCD_VCLK (0x02 << 22) | ||
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h new file mode 100644 index 000000000000..569e76120881 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h | |||
@@ -0,0 +1,54 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-n.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank N register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPNCON (S3C64XX_GPN_BASE + 0x00) | ||
16 | #define S3C64XX_GPNDAT (S3C64XX_GPN_BASE + 0x04) | ||
17 | #define S3C64XX_GPNPUD (S3C64XX_GPN_BASE + 0x08) | ||
18 | |||
19 | #define S3C64XX_GPN_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | ||
20 | #define S3C64XX_GPN_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | ||
21 | #define S3C64XX_GPN_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | ||
22 | |||
23 | #define S3C64XX_GPN0_EINT0 (0x02 << 0) | ||
24 | #define S3C64XX_GPN0_KP_ROW0 (0x03 << 0) | ||
25 | |||
26 | #define S3C64XX_GPN1_EINT1 (0x02 << 2) | ||
27 | #define S3C64XX_GPN1_KP_ROW1 (0x03 << 2) | ||
28 | |||
29 | #define S3C64XX_GPN2_EINT2 (0x02 << 4) | ||
30 | #define S3C64XX_GPN2_KP_ROW2 (0x03 << 4) | ||
31 | |||
32 | #define S3C64XX_GPN3_EINT3 (0x02 << 6) | ||
33 | #define S3C64XX_GPN3_KP_ROW3 (0x03 << 6) | ||
34 | |||
35 | #define S3C64XX_GPN4_EINT4 (0x02 << 8) | ||
36 | #define S3C64XX_GPN4_KP_ROW4 (0x03 << 8) | ||
37 | |||
38 | #define S3C64XX_GPN5_EINT5 (0x02 << 10) | ||
39 | #define S3C64XX_GPN5_KP_ROW5 (0x03 << 10) | ||
40 | |||
41 | #define S3C64XX_GPN6_EINT6 (0x02 << 12) | ||
42 | #define S3C64XX_GPN6_KP_ROW6 (0x03 << 12) | ||
43 | |||
44 | #define S3C64XX_GPN7_EINT7 (0x02 << 14) | ||
45 | #define S3C64XX_GPN7_KP_ROW7 (0x03 << 14) | ||
46 | |||
47 | #define S3C64XX_GPN8_EINT8 (0x02 << 16) | ||
48 | #define S3C64XX_GPN9_EINT9 (0x02 << 18) | ||
49 | #define S3C64XX_GPN10_EINT10 (0x02 << 20) | ||
50 | #define S3C64XX_GPN11_EINT11 (0x02 << 22) | ||
51 | #define S3C64XX_GPN12_EINT12 (0x02 << 24) | ||
52 | #define S3C64XX_GPN13_EINT13 (0x02 << 26) | ||
53 | #define S3C64XX_GPN14_EINT14 (0x02 << 28) | ||
54 | #define S3C64XX_GPN15_EINT15 (0x02 << 30) | ||
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h new file mode 100644 index 000000000000..b09e12954b57 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h | |||
@@ -0,0 +1,70 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-o.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank O register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPOCON (S3C64XX_GPO_BASE + 0x00) | ||
16 | #define S3C64XX_GPODAT (S3C64XX_GPO_BASE + 0x04) | ||
17 | #define S3C64XX_GPOPUD (S3C64XX_GPO_BASE + 0x08) | ||
18 | #define S3C64XX_GPOCONSLP (S3C64XX_GPO_BASE + 0x0c) | ||
19 | #define S3C64XX_GPOPUDSLP (S3C64XX_GPO_BASE + 0x10) | ||
20 | |||
21 | #define S3C64XX_GPO_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | ||
22 | #define S3C64XX_GPO_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | ||
23 | #define S3C64XX_GPO_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | ||
24 | |||
25 | #define S3C64XX_GPO0_MEM0_nCS2 (0x02 << 0) | ||
26 | #define S3C64XX_GPO0_EINT_G7_0 (0x03 << 0) | ||
27 | |||
28 | #define S3C64XX_GPO1_MEM0_nCS3 (0x02 << 2) | ||
29 | #define S3C64XX_GPO1_EINT_G7_1 (0x03 << 2) | ||
30 | |||
31 | #define S3C64XX_GPO2_MEM0_nCS4 (0x02 << 4) | ||
32 | #define S3C64XX_GPO2_EINT_G7_2 (0x03 << 4) | ||
33 | |||
34 | #define S3C64XX_GPO3_MEM0_nCS5 (0x02 << 6) | ||
35 | #define S3C64XX_GPO3_EINT_G7_3 (0x03 << 6) | ||
36 | |||
37 | #define S3C64XX_GPO4_EINT_G7_4 (0x03 << 8) | ||
38 | |||
39 | #define S3C64XX_GPO5_EINT_G7_5 (0x03 << 10) | ||
40 | |||
41 | #define S3C64XX_GPO6_MEM0_ADDR6 (0x02 << 12) | ||
42 | #define S3C64XX_GPO6_EINT_G7_6 (0x03 << 12) | ||
43 | |||
44 | #define S3C64XX_GPO7_MEM0_ADDR7 (0x02 << 14) | ||
45 | #define S3C64XX_GPO7_EINT_G7_7 (0x03 << 14) | ||
46 | |||
47 | #define S3C64XX_GPO8_MEM0_ADDR8 (0x02 << 16) | ||
48 | #define S3C64XX_GPO8_EINT_G7_8 (0x03 << 16) | ||
49 | |||
50 | #define S3C64XX_GPO9_MEM0_ADDR9 (0x02 << 18) | ||
51 | #define S3C64XX_GPO9_EINT_G7_9 (0x03 << 18) | ||
52 | |||
53 | #define S3C64XX_GPO10_MEM0_ADDR10 (0x02 << 20) | ||
54 | #define S3C64XX_GPO10_EINT_G7_10 (0x03 << 20) | ||
55 | |||
56 | #define S3C64XX_GPO11_MEM0_ADDR11 (0x02 << 22) | ||
57 | #define S3C64XX_GPO11_EINT_G7_11 (0x03 << 22) | ||
58 | |||
59 | #define S3C64XX_GPO12_MEM0_ADDR12 (0x02 << 24) | ||
60 | #define S3C64XX_GPO12_EINT_G7_12 (0x03 << 24) | ||
61 | |||
62 | #define S3C64XX_GPO13_MEM0_ADDR13 (0x02 << 26) | ||
63 | #define S3C64XX_GPO13_EINT_G7_13 (0x03 << 26) | ||
64 | |||
65 | #define S3C64XX_GPO14_MEM0_ADDR14 (0x02 << 28) | ||
66 | #define S3C64XX_GPO14_EINT_G7_14 (0x03 << 28) | ||
67 | |||
68 | #define S3C64XX_GPO15_MEM0_ADDR15 (0x02 << 30) | ||
69 | #define S3C64XX_GPO15_EINT_G7_15 (0x03 << 30) | ||
70 | |||
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h new file mode 100644 index 000000000000..92f00517926b --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h | |||
@@ -0,0 +1,69 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-p.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank P register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPPCON (S3C64XX_GPP_BASE + 0x00) | ||
16 | #define S3C64XX_GPPDAT (S3C64XX_GPP_BASE + 0x04) | ||
17 | #define S3C64XX_GPPPUD (S3C64XX_GPP_BASE + 0x08) | ||
18 | #define S3C64XX_GPPCONSLP (S3C64XX_GPP_BASE + 0x0c) | ||
19 | #define S3C64XX_GPPPUDSLP (S3C64XX_GPP_BASE + 0x10) | ||
20 | |||
21 | #define S3C64XX_GPP_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | ||
22 | #define S3C64XX_GPP_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | ||
23 | #define S3C64XX_GPP_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | ||
24 | |||
25 | #define S3C64XX_GPP0_MEM0_ADDRV (0x02 << 0) | ||
26 | #define S3C64XX_GPP0_EINT_G8_0 (0x03 << 0) | ||
27 | |||
28 | #define S3C64XX_GPP1_MEM0_SMCLK (0x02 << 2) | ||
29 | #define S3C64XX_GPP1_EINT_G8_1 (0x03 << 2) | ||
30 | |||
31 | #define S3C64XX_GPP2_MEM0_nWAIT (0x02 << 4) | ||
32 | #define S3C64XX_GPP2_EINT_G8_2 (0x03 << 4) | ||
33 | |||
34 | #define S3C64XX_GPP3_MEM0_RDY0_ALE (0x02 << 6) | ||
35 | #define S3C64XX_GPP3_EINT_G8_3 (0x03 << 6) | ||
36 | |||
37 | #define S3C64XX_GPP4_MEM0_RDY1_CLE (0x02 << 8) | ||
38 | #define S3C64XX_GPP4_EINT_G8_4 (0x03 << 8) | ||
39 | |||
40 | #define S3C64XX_GPP5_MEM0_INTsm0_FWE (0x02 << 10) | ||
41 | #define S3C64XX_GPP5_EINT_G8_5 (0x03 << 10) | ||
42 | |||
43 | #define S3C64XX_GPP6_MEM0_(null) (0x02 << 12) | ||
44 | #define S3C64XX_GPP6_EINT_G8_6 (0x03 << 12) | ||
45 | |||
46 | #define S3C64XX_GPP7_MEM0_INTsm1_FRE (0x02 << 14) | ||
47 | #define S3C64XX_GPP7_EINT_G8_7 (0x03 << 14) | ||
48 | |||
49 | #define S3C64XX_GPP8_MEM0_RPn_RnB (0x02 << 16) | ||
50 | #define S3C64XX_GPP8_EINT_G8_8 (0x03 << 16) | ||
51 | |||
52 | #define S3C64XX_GPP9_MEM0_ATA_RESET (0x02 << 18) | ||
53 | #define S3C64XX_GPP9_EINT_G8_9 (0x03 << 18) | ||
54 | |||
55 | #define S3C64XX_GPP10_MEM0_ATA_INPACK (0x02 << 20) | ||
56 | #define S3C64XX_GPP10_EINT_G8_10 (0x03 << 20) | ||
57 | |||
58 | #define S3C64XX_GPP11_MEM0_ATA_REG (0x02 << 22) | ||
59 | #define S3C64XX_GPP11_EINT_G8_11 (0x03 << 22) | ||
60 | |||
61 | #define S3C64XX_GPP12_MEM0_ATA_WE (0x02 << 24) | ||
62 | #define S3C64XX_GPP12_EINT_G8_12 (0x03 << 24) | ||
63 | |||
64 | #define S3C64XX_GPP13_MEM0_ATA_OE (0x02 << 26) | ||
65 | #define S3C64XX_GPP13_EINT_G8_13 (0x03 << 26) | ||
66 | |||
67 | #define S3C64XX_GPP14_MEM0_ATA_CD (0x02 << 28) | ||
68 | #define S3C64XX_GPP14_EINT_G8_14 (0x03 << 28) | ||
69 | |||
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h new file mode 100644 index 000000000000..565e60aaee47 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h | |||
@@ -0,0 +1,46 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/plat/gpio-bank-q.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * GPIO Bank Q register and configuration definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C64XX_GPQCON (S3C64XX_GPQ_BASE + 0x00) | ||
16 | #define S3C64XX_GPQDAT (S3C64XX_GPQ_BASE + 0x04) | ||
17 | #define S3C64XX_GPQPUD (S3C64XX_GPQ_BASE + 0x08) | ||
18 | #define S3C64XX_GPQCONSLP (S3C64XX_GPQ_BASE + 0x0c) | ||
19 | #define S3C64XX_GPQPUDSLP (S3C64XX_GPQ_BASE + 0x10) | ||
20 | |||
21 | #define S3C64XX_GPQ_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) | ||
22 | #define S3C64XX_GPQ_INPUT(__gpio) (0x0 << ((__gpio) * 2)) | ||
23 | #define S3C64XX_GPQ_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) | ||
24 | |||
25 | #define S3C64XX_GPQ0_MEM0_ADDR18_RAS (0x02 << 0) | ||
26 | #define S3C64XX_GPQ0_EINT_G9_0 (0x03 << 0) | ||
27 | |||
28 | #define S3C64XX_GPQ1_MEM0_ADDR19_CAS (0x02 << 2) | ||
29 | #define S3C64XX_GPQ1_EINT_G9_1 (0x03 << 2) | ||
30 | |||
31 | #define S3C64XX_GPQ2_EINT_G9_2 (0x03 << 4) | ||
32 | |||
33 | #define S3C64XX_GPQ3_EINT_G9_3 (0x03 << 6) | ||
34 | |||
35 | #define S3C64XX_GPQ4_EINT_G9_4 (0x03 << 8) | ||
36 | |||
37 | #define S3C64XX_GPQ5_EINT_G9_5 (0x03 << 10) | ||
38 | |||
39 | #define S3C64XX_GPQ6_EINT_G9_6 (0x03 << 12) | ||
40 | |||
41 | #define S3C64XX_GPQ7_MEM0_ADDR17_WENDMC (0x02 << 14) | ||
42 | #define S3C64XX_GPQ7_EINT_G9_7 (0x03 << 14) | ||
43 | |||
44 | #define S3C64XX_GPQ8_MEM0_ADDR16_APDMC (0x02 << 16) | ||
45 | #define S3C64XX_GPQ8_EINT_G9_8 (0x03 << 16) | ||
46 | |||
diff --git a/arch/arm/plat-s3c64xx/include/plat/irqs.h b/arch/arm/plat-s3c64xx/include/plat/irqs.h new file mode 100644 index 000000000000..02e8dd4c97d5 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/irqs.h | |||
@@ -0,0 +1,201 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/mach/irqs.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C64XX - Common IRQ support | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_PLAT_S3C64XX_IRQS_H | ||
12 | #define __ASM_PLAT_S3C64XX_IRQS_H __FILE__ | ||
13 | |||
14 | /* we keep the first set of CPU IRQs out of the range of | ||
15 | * the ISA space, so that the PC104 has them to itself | ||
16 | * and we don't end up having to do horrible things to the | ||
17 | * standard ISA drivers.... | ||
18 | * | ||
19 | * note, since we're using the VICs, our start must be a | ||
20 | * mulitple of 32 to allow the common code to work | ||
21 | */ | ||
22 | |||
23 | #define S3C_IRQ_OFFSET (32) | ||
24 | |||
25 | #define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) | ||
26 | |||
27 | #define S3C_VIC0_BASE S3C_IRQ(0) | ||
28 | #define S3C_VIC1_BASE S3C_IRQ(32) | ||
29 | |||
30 | /* UART interrupts, each UART has 4 intterupts per channel so | ||
31 | * use the space between the ISA and S3C main interrupts. Note, these | ||
32 | * are not in the same order as the S3C24XX series! */ | ||
33 | |||
34 | #define IRQ_S3CUART_BASE0 (16) | ||
35 | #define IRQ_S3CUART_BASE1 (20) | ||
36 | #define IRQ_S3CUART_BASE2 (24) | ||
37 | #define IRQ_S3CUART_BASE3 (28) | ||
38 | |||
39 | #define UART_IRQ_RXD (0) | ||
40 | #define UART_IRQ_ERR (1) | ||
41 | #define UART_IRQ_TXD (2) | ||
42 | #define UART_IRQ_MODEM (3) | ||
43 | |||
44 | #define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD) | ||
45 | #define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD) | ||
46 | #define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR) | ||
47 | |||
48 | #define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD) | ||
49 | #define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD) | ||
50 | #define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR) | ||
51 | |||
52 | #define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD) | ||
53 | #define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD) | ||
54 | #define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR) | ||
55 | |||
56 | #define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD) | ||
57 | #define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD) | ||
58 | #define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR) | ||
59 | |||
60 | /* VIC based IRQs */ | ||
61 | |||
62 | #define S3C64XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x)) | ||
63 | #define S3C64XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x)) | ||
64 | |||
65 | /* VIC0 */ | ||
66 | |||
67 | #define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0) | ||
68 | #define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1) | ||
69 | #define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2) | ||
70 | #define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3) | ||
71 | #define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4) | ||
72 | #define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5) | ||
73 | #define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5) | ||
74 | #define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6) | ||
75 | #define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6) | ||
76 | #define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7) | ||
77 | #define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8) | ||
78 | #define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8) | ||
79 | #define IRQ_POST0 S3C64XX_IRQ_VIC0(9) | ||
80 | #define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10) | ||
81 | #define IRQ_2D S3C64XX_IRQ_VIC0(11) | ||
82 | #define IRQ_TVENC S3C64XX_IRQ_VIC0(12) | ||
83 | #define IRQ_SCALER S3C64XX_IRQ_VIC0(13) | ||
84 | #define IRQ_BATF S3C64XX_IRQ_VIC0(14) | ||
85 | #define IRQ_JPEG S3C64XX_IRQ_VIC0(15) | ||
86 | #define IRQ_MFC S3C64XX_IRQ_VIC0(16) | ||
87 | #define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17) | ||
88 | #define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18) | ||
89 | #define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19) | ||
90 | #define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20) | ||
91 | #define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21) | ||
92 | #define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22) | ||
93 | #define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23) | ||
94 | #define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24) | ||
95 | #define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25) | ||
96 | #define IRQ_WDT S3C64XX_IRQ_VIC0(26) | ||
97 | #define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27) | ||
98 | #define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28) | ||
99 | #define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29) | ||
100 | #define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30) | ||
101 | #define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31) | ||
102 | |||
103 | /* VIC1 */ | ||
104 | |||
105 | #define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0) | ||
106 | #define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1) | ||
107 | #define IRQ_PCM0 S3C64XX_IRQ_VIC1(2) | ||
108 | #define IRQ_PCM1 S3C64XX_IRQ_VIC1(3) | ||
109 | #define IRQ_AC97 S3C64XX_IRQ_VIC1(4) | ||
110 | #define IRQ_UART0 S3C64XX_IRQ_VIC1(5) | ||
111 | #define IRQ_UART1 S3C64XX_IRQ_VIC1(6) | ||
112 | #define IRQ_UART2 S3C64XX_IRQ_VIC1(7) | ||
113 | #define IRQ_UART3 S3C64XX_IRQ_VIC1(8) | ||
114 | #define IRQ_DMA0 S3C64XX_IRQ_VIC1(9) | ||
115 | #define IRQ_DMA1 S3C64XX_IRQ_VIC1(10) | ||
116 | #define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11) | ||
117 | #define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12) | ||
118 | #define IRQ_NFC S3C64XX_IRQ_VIC1(13) | ||
119 | #define IRQ_CFCON S3C64XX_IRQ_VIC1(14) | ||
120 | #define IRQ_UHOST S3C64XX_IRQ_VIC1(15) | ||
121 | #define IRQ_SPI0 S3C64XX_IRQ_VIC1(16) | ||
122 | #define IRQ_SPI1 S3C64XX_IRQ_VIC1(17) | ||
123 | #define IRQ_IIC S3C64XX_IRQ_VIC1(18) | ||
124 | #define IRQ_HSItx S3C64XX_IRQ_VIC1(19) | ||
125 | #define IRQ_HSIrx S3C64XX_IRQ_VIC1(20) | ||
126 | #define IRQ_RESERVED S3C64XX_IRQ_VIC1(21) | ||
127 | #define IRQ_MSM S3C64XX_IRQ_VIC1(22) | ||
128 | #define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23) | ||
129 | #define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24) | ||
130 | #define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25) | ||
131 | #define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ | ||
132 | #define IRQ_OTG S3C64XX_IRQ_VIC1(26) | ||
133 | #define IRQ_IRDA S3C64XX_IRQ_VIC1(27) | ||
134 | #define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28) | ||
135 | #define IRQ_SEC S3C64XX_IRQ_VIC1(29) | ||
136 | #define IRQ_PENDN S3C64XX_IRQ_VIC1(30) | ||
137 | #define IRQ_TC IRQ_PENDN | ||
138 | #define IRQ_ADC S3C64XX_IRQ_VIC1(31) | ||
139 | |||
140 | #define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x)) | ||
141 | |||
142 | #define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0) | ||
143 | #define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1) | ||
144 | #define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2) | ||
145 | #define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3) | ||
146 | #define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4) | ||
147 | |||
148 | /* compatibility for device defines */ | ||
149 | |||
150 | #define IRQ_IIC1 IRQ_S3C6410_IIC1 | ||
151 | |||
152 | /* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series | ||
153 | * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE | ||
154 | * which we place after the pair of VICs. */ | ||
155 | |||
156 | #define S3C_IRQ_EINT_BASE S3C_IRQ(64+5) | ||
157 | |||
158 | #define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) | ||
159 | #define IRQ_EINT(x) S3C_EINT(x) | ||
160 | |||
161 | /* Next the external interrupt groups. These are similar to the IRQ_EINT(x) | ||
162 | * that they are sourced from the GPIO pins but with a different scheme for | ||
163 | * priority and source indication. | ||
164 | * | ||
165 | * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO | ||
166 | * interrupts, but for historical reasons they are kept apart from these | ||
167 | * next interrupts. | ||
168 | * | ||
169 | * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the | ||
170 | * machine specific support files. | ||
171 | */ | ||
172 | |||
173 | #define IRQ_EINT_GROUP1_NR (15) | ||
174 | #define IRQ_EINT_GROUP2_NR (8) | ||
175 | #define IRQ_EINT_GROUP3_NR (5) | ||
176 | #define IRQ_EINT_GROUP4_NR (14) | ||
177 | #define IRQ_EINT_GROUP5_NR (7) | ||
178 | #define IRQ_EINT_GROUP6_NR (10) | ||
179 | #define IRQ_EINT_GROUP7_NR (16) | ||
180 | #define IRQ_EINT_GROUP8_NR (15) | ||
181 | #define IRQ_EINT_GROUP9_NR (9) | ||
182 | |||
183 | #define IRQ_EINT_GROUP_BASE S3C_EINT(28) | ||
184 | #define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) | ||
185 | #define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) | ||
186 | #define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) | ||
187 | #define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) | ||
188 | #define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) | ||
189 | #define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) | ||
190 | #define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) | ||
191 | #define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) | ||
192 | #define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) | ||
193 | |||
194 | #define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##__BASE + (x)) | ||
195 | |||
196 | /* Set the default NR_IRQS */ | ||
197 | |||
198 | #define NR_IRQS (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) | ||
199 | |||
200 | #endif /* __ASM_PLAT_S3C64XX_IRQS_H */ | ||
201 | |||
diff --git a/arch/arm/plat-s3c64xx/include/plat/pll.h b/arch/arm/plat-s3c64xx/include/plat/pll.h new file mode 100644 index 000000000000..90bbd72fdc4e --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/pll.h | |||
@@ -0,0 +1,74 @@ | |||
1 | /* arch/arm/plat-s3c64xx/include/plat/pll.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C64XX PLL code | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #define S3C6400_PLL_MDIV_MASK ((1 << (25-16+1)) - 1) | ||
16 | #define S3C6400_PLL_PDIV_MASK ((1 << (13-8+1)) - 1) | ||
17 | #define S3C6400_PLL_SDIV_MASK ((1 << (2-0+1)) - 1) | ||
18 | #define S3C6400_PLL_MDIV_SHIFT (16) | ||
19 | #define S3C6400_PLL_PDIV_SHIFT (8) | ||
20 | #define S3C6400_PLL_SDIV_SHIFT (0) | ||
21 | |||
22 | #include <asm/div64.h> | ||
23 | |||
24 | static inline unsigned long s3c6400_get_pll(unsigned long baseclk, | ||
25 | u32 pllcon) | ||
26 | { | ||
27 | u32 mdiv, pdiv, sdiv; | ||
28 | u64 fvco = baseclk; | ||
29 | |||
30 | mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK; | ||
31 | pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK; | ||
32 | sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK; | ||
33 | |||
34 | fvco *= mdiv; | ||
35 | do_div(fvco, (pdiv << sdiv)); | ||
36 | |||
37 | return (unsigned long)fvco; | ||
38 | } | ||
39 | |||
40 | #define S3C6400_EPLL_MDIV_MASK ((1 << (23-16)) - 1) | ||
41 | #define S3C6400_EPLL_PDIV_MASK ((1 << (13-8)) - 1) | ||
42 | #define S3C6400_EPLL_SDIV_MASK ((1 << (2-0)) - 1) | ||
43 | #define S3C6400_EPLL_MDIV_SHIFT (16) | ||
44 | #define S3C6400_EPLL_PDIV_SHIFT (8) | ||
45 | #define S3C6400_EPLL_SDIV_SHIFT (0) | ||
46 | #define S3C6400_EPLL_KDIV_MASK (0xffff) | ||
47 | |||
48 | static inline unsigned long s3c6400_get_epll(unsigned long baseclk) | ||
49 | { | ||
50 | unsigned long result; | ||
51 | u32 epll0 = __raw_readl(S3C_EPLL_CON0); | ||
52 | u32 epll1 = __raw_readl(S3C_EPLL_CON1); | ||
53 | u32 mdiv, pdiv, sdiv, kdiv; | ||
54 | u64 tmp; | ||
55 | |||
56 | mdiv = (epll0 >> S3C6400_EPLL_MDIV_SHIFT) & S3C6400_EPLL_MDIV_MASK; | ||
57 | pdiv = (epll0 >> S3C6400_EPLL_PDIV_SHIFT) & S3C6400_EPLL_PDIV_MASK; | ||
58 | sdiv = (epll0 >> S3C6400_EPLL_SDIV_SHIFT) & S3C6400_EPLL_SDIV_MASK; | ||
59 | kdiv = epll1 & S3C6400_EPLL_KDIV_MASK; | ||
60 | |||
61 | /* We need to multiple baseclk by mdiv (the integer part) and kdiv | ||
62 | * which is in 2^16ths, so shift mdiv up (does not overflow) and | ||
63 | * add kdiv before multiplying. The use of tmp is to avoid any | ||
64 | * overflows before shifting bac down into result when multipling | ||
65 | * by the mdiv and kdiv pair. | ||
66 | */ | ||
67 | |||
68 | tmp = baseclk; | ||
69 | tmp *= (mdiv << 16) + kdiv; | ||
70 | do_div(tmp, (pdiv << sdiv)); | ||
71 | result = tmp >> 16; | ||
72 | |||
73 | return result; | ||
74 | } | ||
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-clock.h b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h new file mode 100644 index 000000000000..b1082c163247 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/regs-clock.h | |||
@@ -0,0 +1,224 @@ | |||
1 | /* arch/arm/plat-s3c64xx/include/plat/regs-clock.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C64XX clock register definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __PLAT_REGS_CLOCK_H | ||
16 | #define __PLAT_REGS_CLOCK_H __FILE__ | ||
17 | |||
18 | #define S3C_CLKREG(x) (S3C_VA_SYS + (x)) | ||
19 | |||
20 | #define S3C_APLL_LOCK S3C_CLKREG(0x00) | ||
21 | #define S3C_MPLL_LOCK S3C_CLKREG(0x04) | ||
22 | #define S3C_EPLL_LOCK S3C_CLKREG(0x08) | ||
23 | #define S3C_APLL_CON S3C_CLKREG(0x0C) | ||
24 | #define S3C_MPLL_CON S3C_CLKREG(0x10) | ||
25 | #define S3C_EPLL_CON0 S3C_CLKREG(0x14) | ||
26 | #define S3C_EPLL_CON1 S3C_CLKREG(0x18) | ||
27 | #define S3C_CLK_SRC S3C_CLKREG(0x1C) | ||
28 | #define S3C_CLK_DIV0 S3C_CLKREG(0x20) | ||
29 | #define S3C_CLK_DIV1 S3C_CLKREG(0x24) | ||
30 | #define S3C_CLK_DIV2 S3C_CLKREG(0x28) | ||
31 | #define S3C_CLK_OUT S3C_CLKREG(0x2C) | ||
32 | #define S3C_HCLK_GATE S3C_CLKREG(0x30) | ||
33 | #define S3C_PCLK_GATE S3C_CLKREG(0x34) | ||
34 | #define S3C_SCLK_GATE S3C_CLKREG(0x38) | ||
35 | |||
36 | /* CLKDIV0 */ | ||
37 | #define S3C6400_CLKDIV0_MFC_MASK (0xf << 28) | ||
38 | #define S3C6400_CLKDIV0_MFC_SHIFT (28) | ||
39 | #define S3C6400_CLKDIV0_JPEG_MASK (0xf << 24) | ||
40 | #define S3C6400_CLKDIV0_JPEG_SHIFT (24) | ||
41 | #define S3C6400_CLKDIV0_CAM_MASK (0xf << 20) | ||
42 | #define S3C6400_CLKDIV0_CAM_SHIFT (20) | ||
43 | #define S3C6400_CLKDIV0_SECURITY_MASK (0x3 << 18) | ||
44 | #define S3C6400_CLKDIV0_SECURITY_SHIFT (18) | ||
45 | #define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) | ||
46 | #define S3C6400_CLKDIV0_PCLK_SHIFT (12) | ||
47 | #define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9) | ||
48 | #define S3C6400_CLKDIV0_HCLK2_SHIFT (9) | ||
49 | #define S3C6400_CLKDIV0_HCLK_MASK (0x1 << 8) | ||
50 | #define S3C6400_CLKDIV0_HCLK_SHIFT (8) | ||
51 | #define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4) | ||
52 | #define S3C6400_CLKDIV0_MPLL_SHIFT (4) | ||
53 | #define S3C6400_CLKDIV0_ARM_MASK (0x3 << 0) | ||
54 | #define S3C6410_CLKDIV0_ARM_MASK (0x7 << 0) | ||
55 | #define S3C6400_CLKDIV0_ARM_SHIFT (0) | ||
56 | |||
57 | /* CLKDIV1 */ | ||
58 | #define S3C6410_CLKDIV1_FIMC_MASK (0xf << 24) | ||
59 | #define S3C6410_CLKDIV1_FIMC_SHIFT (24) | ||
60 | #define S3C6400_CLKDIV1_UHOST_MASK (0xf << 20) | ||
61 | #define S3C6400_CLKDIV1_UHOST_SHIFT (20) | ||
62 | #define S3C6400_CLKDIV1_SCALER_MASK (0xf << 16) | ||
63 | #define S3C6400_CLKDIV1_SCALER_SHIFT (16) | ||
64 | #define S3C6400_CLKDIV1_LCD_MASK (0xf << 12) | ||
65 | #define S3C6400_CLKDIV1_LCD_SHIFT (12) | ||
66 | #define S3C6400_CLKDIV1_MMC2_MASK (0xf << 8) | ||
67 | #define S3C6400_CLKDIV1_MMC2_SHIFT (8) | ||
68 | #define S3C6400_CLKDIV1_MMC1_MASK (0xf << 4) | ||
69 | #define S3C6400_CLKDIV1_MMC1_SHIFT (4) | ||
70 | #define S3C6400_CLKDIV1_MMC0_MASK (0xf << 0) | ||
71 | #define S3C6400_CLKDIV1_MMC0_SHIFT (0) | ||
72 | |||
73 | /* CLKDIV2 */ | ||
74 | #define S3C6410_CLKDIV2_AUDIO2_MASK (0xf << 24) | ||
75 | #define S3C6410_CLKDIV2_AUDIO2_SHIFT (24) | ||
76 | #define S3C6400_CLKDIV2_IRDA_MASK (0xf << 20) | ||
77 | #define S3C6400_CLKDIV2_IRDA_SHIFT (20) | ||
78 | #define S3C6400_CLKDIV2_UART_MASK (0xf << 16) | ||
79 | #define S3C6400_CLKDIV2_UART_SHIFT (16) | ||
80 | #define S3C6400_CLKDIV2_AUDIO1_MASK (0xf << 12) | ||
81 | #define S3C6400_CLKDIV2_AUDIO1_SHIFT (12) | ||
82 | #define S3C6400_CLKDIV2_AUDIO0_MASK (0xf << 8) | ||
83 | #define S3C6400_CLKDIV2_AUDIO0_SHIFT (8) | ||
84 | #define S3C6400_CLKDIV2_SPI1_MASK (0xf << 4) | ||
85 | #define S3C6400_CLKDIV2_SPI1_SHIFT (4) | ||
86 | #define S3C6400_CLKDIV2_SPI0_MASK (0xf << 0) | ||
87 | #define S3C6400_CLKDIV2_SPI0_SHIFT (0) | ||
88 | |||
89 | /* HCLK GATE Registers */ | ||
90 | #define S3C_CLKCON_HCLK_BUS (1<<30) | ||
91 | #define S3C_CLKCON_HCLK_SECUR (1<<29) | ||
92 | #define S3C_CLKCON_HCLK_SDMA1 (1<<28) | ||
93 | #define S3C_CLKCON_HCLK_SDMA2 (1<<27) | ||
94 | #define S3C_CLKCON_HCLK_UHOST (1<<26) | ||
95 | #define S3C_CLKCON_HCLK_IROM (1<<25) | ||
96 | #define S3C_CLKCON_HCLK_DDR1 (1<<24) | ||
97 | #define S3C_CLKCON_HCLK_DDR0 (1<<23) | ||
98 | #define S3C_CLKCON_HCLK_MEM1 (1<<22) | ||
99 | #define S3C_CLKCON_HCLK_MEM0 (1<<21) | ||
100 | #define S3C_CLKCON_HCLK_USB (1<<20) | ||
101 | #define S3C_CLKCON_HCLK_HSMMC2 (1<<19) | ||
102 | #define S3C_CLKCON_HCLK_HSMMC1 (1<<18) | ||
103 | #define S3C_CLKCON_HCLK_HSMMC0 (1<<17) | ||
104 | #define S3C_CLKCON_HCLK_MDP (1<<16) | ||
105 | #define S3C_CLKCON_HCLK_DHOST (1<<15) | ||
106 | #define S3C_CLKCON_HCLK_IHOST (1<<14) | ||
107 | #define S3C_CLKCON_HCLK_DMA1 (1<<13) | ||
108 | #define S3C_CLKCON_HCLK_DMA0 (1<<12) | ||
109 | #define S3C_CLKCON_HCLK_JPEG (1<<11) | ||
110 | #define S3C_CLKCON_HCLK_CAMIF (1<<10) | ||
111 | #define S3C_CLKCON_HCLK_SCALER (1<<9) | ||
112 | #define S3C_CLKCON_HCLK_2D (1<<8) | ||
113 | #define S3C_CLKCON_HCLK_TV (1<<7) | ||
114 | #define S3C_CLKCON_HCLK_POST0 (1<<5) | ||
115 | #define S3C_CLKCON_HCLK_ROT (1<<4) | ||
116 | #define S3C_CLKCON_HCLK_LCD (1<<3) | ||
117 | #define S3C_CLKCON_HCLK_TZIC (1<<2) | ||
118 | #define S3C_CLKCON_HCLK_INTC (1<<1) | ||
119 | #define S3C_CLKCON_HCLK_MFC (1<<0) | ||
120 | |||
121 | /* PCLK GATE Registers */ | ||
122 | #define S3C6410_CLKCON_PCLK_I2C1 (1<<27) | ||
123 | #define S3C6410_CLKCON_PCLK_IIS2 (1<<26) | ||
124 | #define S3C_CLKCON_PCLK_SKEY (1<<24) | ||
125 | #define S3C_CLKCON_PCLK_CHIPID (1<<23) | ||
126 | #define S3C_CLKCON_PCLK_SPI1 (1<<22) | ||
127 | #define S3C_CLKCON_PCLK_SPI0 (1<<21) | ||
128 | #define S3C_CLKCON_PCLK_HSIRX (1<<20) | ||
129 | #define S3C_CLKCON_PCLK_HSITX (1<<19) | ||
130 | #define S3C_CLKCON_PCLK_GPIO (1<<18) | ||
131 | #define S3C_CLKCON_PCLK_IIC (1<<17) | ||
132 | #define S3C_CLKCON_PCLK_IIS1 (1<<16) | ||
133 | #define S3C_CLKCON_PCLK_IIS0 (1<<15) | ||
134 | #define S3C_CLKCON_PCLK_AC97 (1<<14) | ||
135 | #define S3C_CLKCON_PCLK_TZPC (1<<13) | ||
136 | #define S3C_CLKCON_PCLK_TSADC (1<<12) | ||
137 | #define S3C_CLKCON_PCLK_KEYPAD (1<<11) | ||
138 | #define S3C_CLKCON_PCLK_IRDA (1<<10) | ||
139 | #define S3C_CLKCON_PCLK_PCM1 (1<<9) | ||
140 | #define S3C_CLKCON_PCLK_PCM0 (1<<8) | ||
141 | #define S3C_CLKCON_PCLK_PWM (1<<7) | ||
142 | #define S3C_CLKCON_PCLK_RTC (1<<6) | ||
143 | #define S3C_CLKCON_PCLK_WDT (1<<5) | ||
144 | #define S3C_CLKCON_PCLK_UART3 (1<<4) | ||
145 | #define S3C_CLKCON_PCLK_UART2 (1<<3) | ||
146 | #define S3C_CLKCON_PCLK_UART1 (1<<2) | ||
147 | #define S3C_CLKCON_PCLK_UART0 (1<<1) | ||
148 | #define S3C_CLKCON_PCLK_MFC (1<<0) | ||
149 | |||
150 | /* SCLK GATE Registers */ | ||
151 | #define S3C_CLKCON_SCLK_UHOST (1<<30) | ||
152 | #define S3C_CLKCON_SCLK_MMC2_48 (1<<29) | ||
153 | #define S3C_CLKCON_SCLK_MMC1_48 (1<<28) | ||
154 | #define S3C_CLKCON_SCLK_MMC0_48 (1<<27) | ||
155 | #define S3C_CLKCON_SCLK_MMC2 (1<<26) | ||
156 | #define S3C_CLKCON_SCLK_MMC1 (1<<25) | ||
157 | #define S3C_CLKCON_SCLK_MMC0 (1<<24) | ||
158 | #define S3C_CLKCON_SCLK_SPI1_48 (1<<23) | ||
159 | #define S3C_CLKCON_SCLK_SPI0_48 (1<<22) | ||
160 | #define S3C_CLKCON_SCLK_SPI1 (1<<21) | ||
161 | #define S3C_CLKCON_SCLK_SPI0 (1<<20) | ||
162 | #define S3C_CLKCON_SCLK_DAC27 (1<<19) | ||
163 | #define S3C_CLKCON_SCLK_TV27 (1<<18) | ||
164 | #define S3C_CLKCON_SCLK_SCALER27 (1<<17) | ||
165 | #define S3C_CLKCON_SCLK_SCALER (1<<16) | ||
166 | #define S3C_CLKCON_SCLK_LCD27 (1<<15) | ||
167 | #define S3C_CLKCON_SCLK_LCD (1<<14) | ||
168 | #define S3C6400_CLKCON_SCLK_POST1_27 (1<<13) | ||
169 | #define S3C6410_CLKCON_FIMC (1<<13) | ||
170 | #define S3C_CLKCON_SCLK_POST0_27 (1<<12) | ||
171 | #define S3C6400_CLKCON_SCLK_POST1 (1<<11) | ||
172 | #define S3C6410_CLKCON_SCLK_AUDIO2 (1<<11) | ||
173 | #define S3C_CLKCON_SCLK_POST0 (1<<10) | ||
174 | #define S3C_CLKCON_SCLK_AUDIO1 (1<<9) | ||
175 | #define S3C_CLKCON_SCLK_AUDIO0 (1<<8) | ||
176 | #define S3C_CLKCON_SCLK_SECUR (1<<7) | ||
177 | #define S3C_CLKCON_SCLK_IRDA (1<<6) | ||
178 | #define S3C_CLKCON_SCLK_UART (1<<5) | ||
179 | #define S3C_CLKCON_SCLK_ONENAND (1<<4) | ||
180 | #define S3C_CLKCON_SCLK_MFC (1<<3) | ||
181 | #define S3C_CLKCON_SCLK_CAM (1<<2) | ||
182 | #define S3C_CLKCON_SCLK_JPEG (1<<1) | ||
183 | |||
184 | /* CLKSRC */ | ||
185 | |||
186 | #define S3C6400_CLKSRC_APLL_MOUT (1 << 0) | ||
187 | #define S3C6400_CLKSRC_MPLL_MOUT (1 << 1) | ||
188 | #define S3C6400_CLKSRC_EPLL_MOUT (1 << 2) | ||
189 | #define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0) | ||
190 | #define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1) | ||
191 | #define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2) | ||
192 | #define S3C6400_CLKSRC_MFC (1 << 4) | ||
193 | |||
194 | #define S3C6410_CLKSRC_TV27_MASK (0x1 << 31) | ||
195 | #define S3C6410_CLKSRC_TV27_SHIFT (31) | ||
196 | #define S3C6410_CLKSRC_DAC27_MASK (0x1 << 30) | ||
197 | #define S3C6410_CLKSRC_DAC27_SHIFT (30) | ||
198 | #define S3C6400_CLKSRC_SCALER_MASK (0x3 << 28) | ||
199 | #define S3C6400_CLKSRC_SCALER_SHIFT (28) | ||
200 | #define S3C6400_CLKSRC_LCD_MASK (0x3 << 26) | ||
201 | #define S3C6400_CLKSRC_LCD_SHIFT (26) | ||
202 | #define S3C6400_CLKSRC_IRDA_MASK (0x3 << 24) | ||
203 | #define S3C6400_CLKSRC_IRDA_SHIFT (24) | ||
204 | #define S3C6400_CLKSRC_MMC2_MASK (0x3 << 22) | ||
205 | #define S3C6400_CLKSRC_MMC2_SHIFT (22) | ||
206 | #define S3C6400_CLKSRC_MMC1_MASK (0x3 << 20) | ||
207 | #define S3C6400_CLKSRC_MMC1_SHIFT (20) | ||
208 | #define S3C6400_CLKSRC_MMC0_MASK (0x3 << 18) | ||
209 | #define S3C6400_CLKSRC_MMC0_SHIFT (18) | ||
210 | #define S3C6400_CLKSRC_SPI1_MASK (0x3 << 16) | ||
211 | #define S3C6400_CLKSRC_SPI1_SHIFT (16) | ||
212 | #define S3C6400_CLKSRC_SPI0_MASK (0x3 << 14) | ||
213 | #define S3C6400_CLKSRC_SPI0_SHIFT (14) | ||
214 | #define S3C6400_CLKSRC_UART_MASK (0x1 << 13) | ||
215 | #define S3C6400_CLKSRC_UART_SHIFT (13) | ||
216 | #define S3C6400_CLKSRC_AUDIO1_MASK (0x7 << 10) | ||
217 | #define S3C6400_CLKSRC_AUDIO1_SHIFT (10) | ||
218 | #define S3C6400_CLKSRC_AUDIO0_MASK (0x7 << 7) | ||
219 | #define S3C6400_CLKSRC_AUDIO0_SHIFT (7) | ||
220 | #define S3C6400_CLKSRC_UHOST_MASK (0x3 << 5) | ||
221 | #define S3C6400_CLKSRC_UHOST_SHIFT (5) | ||
222 | |||
223 | |||
224 | #endif /* _PLAT_REGS_CLOCK_H */ | ||
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h new file mode 100644 index 000000000000..75b873d82808 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/regs-gpio.h | |||
@@ -0,0 +1,35 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C64XX - GPIO register definitions | ||
9 | */ | ||
10 | |||
11 | #ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H | ||
12 | #define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__ | ||
13 | |||
14 | /* Base addresses for each of the banks */ | ||
15 | |||
16 | #define S3C64XX_GPA_BASE (S3C64XX_VA_GPIO + 0x0000) | ||
17 | #define S3C64XX_GPB_BASE (S3C64XX_VA_GPIO + 0x0020) | ||
18 | #define S3C64XX_GPC_BASE (S3C64XX_VA_GPIO + 0x0040) | ||
19 | #define S3C64XX_GPD_BASE (S3C64XX_VA_GPIO + 0x0060) | ||
20 | #define S3C64XX_GPE_BASE (S3C64XX_VA_GPIO + 0x0080) | ||
21 | #define S3C64XX_GPF_BASE (S3C64XX_VA_GPIO + 0x00A0) | ||
22 | #define S3C64XX_GPG_BASE (S3C64XX_VA_GPIO + 0x00C0) | ||
23 | #define S3C64XX_GPH_BASE (S3C64XX_VA_GPIO + 0x00E0) | ||
24 | #define S3C64XX_GPI_BASE (S3C64XX_VA_GPIO + 0x0100) | ||
25 | #define S3C64XX_GPJ_BASE (S3C64XX_VA_GPIO + 0x0120) | ||
26 | #define S3C64XX_GPK_BASE (S3C64XX_VA_GPIO + 0x0800) | ||
27 | #define S3C64XX_GPL_BASE (S3C64XX_VA_GPIO + 0x0810) | ||
28 | #define S3C64XX_GPM_BASE (S3C64XX_VA_GPIO + 0x0820) | ||
29 | #define S3C64XX_GPN_BASE (S3C64XX_VA_GPIO + 0x0830) | ||
30 | #define S3C64XX_GPO_BASE (S3C64XX_VA_GPIO + 0x0140) | ||
31 | #define S3C64XX_GPP_BASE (S3C64XX_VA_GPIO + 0x0160) | ||
32 | #define S3C64XX_GPQ_BASE (S3C64XX_VA_GPIO + 0x0180) | ||
33 | |||
34 | #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */ | ||
35 | |||
diff --git a/arch/arm/plat-s3c64xx/include/plat/regs-sys.h b/arch/arm/plat-s3c64xx/include/plat/regs-sys.h new file mode 100644 index 000000000000..d8ed82917096 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/regs-sys.h | |||
@@ -0,0 +1,24 @@ | |||
1 | /* arch/arm/plat-s3c64xx/include/plat/regs-sys.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C64XX system register definitions | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __PLAT_REGS_SYS_H | ||
16 | #define __PLAT_REGS_SYS_H __FILE__ | ||
17 | |||
18 | #define S3C_SYSREG(x) (S3C_VA_SYS + (x)) | ||
19 | |||
20 | #define S3C64XX_OTHERS S3C_SYSREG(0x900) | ||
21 | |||
22 | #define S3C64XX_OTHERS_USBMASK (1 << 16) | ||
23 | |||
24 | #endif /* _PLAT_REGS_SYS_H */ | ||
diff --git a/arch/arm/plat-s3c64xx/include/plat/s3c6400.h b/arch/arm/plat-s3c64xx/include/plat/s3c6400.h new file mode 100644 index 000000000000..571eaa2e54f1 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/s3c6400.h | |||
@@ -0,0 +1,35 @@ | |||
1 | /* arch/arm/plat-s3c64xx/include/plat/s3c6400.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * Header file for s3c6400 cpu support | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | /* Common init code for S3C6400 related SoCs */ | ||
16 | |||
17 | extern void s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
18 | extern void s3c6400_register_clocks(void); | ||
19 | extern void s3c6400_setup_clocks(void); | ||
20 | |||
21 | #ifdef CONFIG_CPU_S3C6400 | ||
22 | |||
23 | extern int s3c6400_init(void); | ||
24 | extern void s3c6400_map_io(void); | ||
25 | extern void s3c6400_init_clocks(int xtal); | ||
26 | |||
27 | #define s3c6400_init_uarts s3c6400_common_init_uarts | ||
28 | |||
29 | #else | ||
30 | #define s3c6400_init_clocks NULL | ||
31 | #define s3c6400_init_uarts NULL | ||
32 | #define s3c6400_map_io NULL | ||
33 | #define s3c6400_init NULL | ||
34 | #endif | ||
35 | |||
diff --git a/arch/arm/plat-s3c64xx/include/plat/s3c6410.h b/arch/arm/plat-s3c64xx/include/plat/s3c6410.h new file mode 100644 index 000000000000..50dcdd6f6800 --- /dev/null +++ b/arch/arm/plat-s3c64xx/include/plat/s3c6410.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* arch/arm/plat-s3c64xx/include/plat/s3c6410.h | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * Header file for s3c6410 cpu support | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifdef CONFIG_CPU_S3C6410 | ||
16 | |||
17 | extern int s3c6410_init(void); | ||
18 | extern void s3c6410_init_irq(void); | ||
19 | extern void s3c6410_map_io(void); | ||
20 | extern void s3c6410_init_clocks(int xtal); | ||
21 | |||
22 | #define s3c6410_init_uarts s3c6400_common_init_uarts | ||
23 | |||
24 | #else | ||
25 | #define s3c6410_init_clocks NULL | ||
26 | #define s3c6410_init_uarts NULL | ||
27 | #define s3c6410_map_io NULL | ||
28 | #define s3c6410_init NULL | ||
29 | #endif | ||
diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c new file mode 100644 index 000000000000..1f7cc0067f5c --- /dev/null +++ b/arch/arm/plat-s3c64xx/irq-eint.c | |||
@@ -0,0 +1,202 @@ | |||
1 | /* arch/arm/plat-s3c64xx/irq-eint.c | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C64XX - Interrupt handling for IRQ_EINT(x) | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/interrupt.h> | ||
17 | #include <linux/irq.h> | ||
18 | #include <linux/io.h> | ||
19 | |||
20 | #include <asm/hardware/vic.h> | ||
21 | |||
22 | #include <plat/regs-irqtype.h> | ||
23 | |||
24 | #include <mach/map.h> | ||
25 | #include <plat/cpu.h> | ||
26 | |||
27 | /* GPIO is 0x7F008xxx, */ | ||
28 | #define S3C64XX_GPIOREG(x) (S3C64XX_VA_GPIO + (x)) | ||
29 | |||
30 | #define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900) | ||
31 | #define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904) | ||
32 | #define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910) | ||
33 | #define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914) | ||
34 | #define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918) | ||
35 | #define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C) | ||
36 | |||
37 | #define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920) | ||
38 | #define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924) | ||
39 | |||
40 | |||
41 | #define eint_offset(irq) ((irq) - IRQ_EINT(0)) | ||
42 | #define eint_irq_to_bit(irq) (1 << eint_offset(irq)) | ||
43 | |||
44 | static inline void s3c_irq_eint_mask(unsigned int irq) | ||
45 | { | ||
46 | u32 mask; | ||
47 | |||
48 | mask = __raw_readl(S3C64XX_EINT0MASK); | ||
49 | mask |= eint_irq_to_bit(irq); | ||
50 | __raw_writel(mask, S3C64XX_EINT0MASK); | ||
51 | } | ||
52 | |||
53 | static void s3c_irq_eint_unmask(unsigned int irq) | ||
54 | { | ||
55 | u32 mask; | ||
56 | |||
57 | mask = __raw_readl(S3C64XX_EINT0MASK); | ||
58 | mask |= eint_irq_to_bit(irq); | ||
59 | __raw_writel(mask, S3C64XX_EINT0MASK); | ||
60 | } | ||
61 | |||
62 | static inline void s3c_irq_eint_ack(unsigned int irq) | ||
63 | { | ||
64 | __raw_writel(eint_irq_to_bit(irq), S3C64XX_EINT0PEND); | ||
65 | } | ||
66 | |||
67 | static void s3c_irq_eint_maskack(unsigned int irq) | ||
68 | { | ||
69 | /* compiler should in-line these */ | ||
70 | s3c_irq_eint_mask(irq); | ||
71 | s3c_irq_eint_ack(irq); | ||
72 | } | ||
73 | |||
74 | static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) | ||
75 | { | ||
76 | int offs = eint_offset(irq); | ||
77 | int shift; | ||
78 | u32 ctrl, mask; | ||
79 | u32 newvalue = 0; | ||
80 | void __iomem *reg; | ||
81 | |||
82 | if (offs > 27) | ||
83 | return -EINVAL; | ||
84 | |||
85 | if (offs <= 15) | ||
86 | reg = S3C64XX_EINT0CON0; | ||
87 | else | ||
88 | reg = S3C64XX_EINT0CON1; | ||
89 | |||
90 | switch (type) { | ||
91 | case IRQ_TYPE_NONE: | ||
92 | printk(KERN_WARNING "No edge setting!\n"); | ||
93 | break; | ||
94 | |||
95 | case IRQ_TYPE_EDGE_RISING: | ||
96 | newvalue = S3C2410_EXTINT_RISEEDGE; | ||
97 | break; | ||
98 | |||
99 | case IRQ_TYPE_EDGE_FALLING: | ||
100 | newvalue = S3C2410_EXTINT_FALLEDGE; | ||
101 | break; | ||
102 | |||
103 | case IRQ_TYPE_EDGE_BOTH: | ||
104 | newvalue = S3C2410_EXTINT_BOTHEDGE; | ||
105 | break; | ||
106 | |||
107 | case IRQ_TYPE_LEVEL_LOW: | ||
108 | newvalue = S3C2410_EXTINT_LOWLEV; | ||
109 | break; | ||
110 | |||
111 | case IRQ_TYPE_LEVEL_HIGH: | ||
112 | newvalue = S3C2410_EXTINT_HILEV; | ||
113 | break; | ||
114 | |||
115 | default: | ||
116 | printk(KERN_ERR "No such irq type %d", type); | ||
117 | return -1; | ||
118 | } | ||
119 | |||
120 | shift = (offs / 2) * 4; | ||
121 | mask = 0x7 << shift; | ||
122 | |||
123 | ctrl = __raw_readl(reg); | ||
124 | ctrl &= ~mask; | ||
125 | ctrl |= newvalue << shift; | ||
126 | __raw_writel(ctrl, reg); | ||
127 | |||
128 | return 0; | ||
129 | } | ||
130 | |||
131 | static struct irq_chip s3c_irq_eint = { | ||
132 | .name = "s3c-eint", | ||
133 | .mask = s3c_irq_eint_mask, | ||
134 | .unmask = s3c_irq_eint_unmask, | ||
135 | .mask_ack = s3c_irq_eint_maskack, | ||
136 | .ack = s3c_irq_eint_ack, | ||
137 | .set_type = s3c_irq_eint_set_type, | ||
138 | }; | ||
139 | |||
140 | /* s3c_irq_demux_eint | ||
141 | * | ||
142 | * This function demuxes the IRQ from the group0 external interrupts, | ||
143 | * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into | ||
144 | * the specific handlers s3c_irq_demux_eintX_Y. | ||
145 | */ | ||
146 | static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end) | ||
147 | { | ||
148 | u32 status = __raw_readl(S3C64XX_EINT0PEND); | ||
149 | u32 mask = __raw_readl(S3C64XX_EINT0MASK); | ||
150 | unsigned int irq; | ||
151 | |||
152 | status &= ~mask; | ||
153 | status >>= start; | ||
154 | status &= (1 << (end - start + 1)) - 1; | ||
155 | |||
156 | for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) { | ||
157 | if (status & 1) | ||
158 | generic_handle_irq(irq); | ||
159 | |||
160 | status >>= 1; | ||
161 | } | ||
162 | } | ||
163 | |||
164 | static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc) | ||
165 | { | ||
166 | s3c_irq_demux_eint(0, 3); | ||
167 | } | ||
168 | |||
169 | static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc) | ||
170 | { | ||
171 | s3c_irq_demux_eint(4, 11); | ||
172 | } | ||
173 | |||
174 | static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc) | ||
175 | { | ||
176 | s3c_irq_demux_eint(12, 19); | ||
177 | } | ||
178 | |||
179 | static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc) | ||
180 | { | ||
181 | s3c_irq_demux_eint(20, 27); | ||
182 | } | ||
183 | |||
184 | int __init s3c64xx_init_irq_eint(void) | ||
185 | { | ||
186 | int irq; | ||
187 | |||
188 | for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) { | ||
189 | set_irq_chip(irq, &s3c_irq_eint); | ||
190 | set_irq_handler(irq, handle_level_irq); | ||
191 | set_irq_flags(irq, IRQF_VALID); | ||
192 | } | ||
193 | |||
194 | set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3); | ||
195 | set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11); | ||
196 | set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19); | ||
197 | set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27); | ||
198 | |||
199 | return 0; | ||
200 | } | ||
201 | |||
202 | arch_initcall(s3c64xx_init_irq_eint); | ||
diff --git a/arch/arm/plat-s3c64xx/irq.c b/arch/arm/plat-s3c64xx/irq.c new file mode 100644 index 000000000000..a94f1d5e819d --- /dev/null +++ b/arch/arm/plat-s3c64xx/irq.c | |||
@@ -0,0 +1,257 @@ | |||
1 | /* arch/arm/plat-s3c64xx/irq.c | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C64XX - Interrupt handling | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/interrupt.h> | ||
17 | #include <linux/irq.h> | ||
18 | #include <linux/io.h> | ||
19 | |||
20 | #include <asm/hardware/vic.h> | ||
21 | |||
22 | #include <mach/map.h> | ||
23 | #include <plat/regs-timer.h> | ||
24 | #include <plat/cpu.h> | ||
25 | |||
26 | /* Timer interrupt handling */ | ||
27 | |||
28 | static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq) | ||
29 | { | ||
30 | generic_handle_irq(sub_irq); | ||
31 | } | ||
32 | |||
33 | static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc) | ||
34 | { | ||
35 | s3c_irq_demux_timer(irq, IRQ_TIMER0); | ||
36 | } | ||
37 | |||
38 | static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc) | ||
39 | { | ||
40 | s3c_irq_demux_timer(irq, IRQ_TIMER1); | ||
41 | } | ||
42 | |||
43 | static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc) | ||
44 | { | ||
45 | s3c_irq_demux_timer(irq, IRQ_TIMER2); | ||
46 | } | ||
47 | |||
48 | static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc) | ||
49 | { | ||
50 | s3c_irq_demux_timer(irq, IRQ_TIMER3); | ||
51 | } | ||
52 | |||
53 | static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc) | ||
54 | { | ||
55 | s3c_irq_demux_timer(irq, IRQ_TIMER4); | ||
56 | } | ||
57 | |||
58 | /* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ | ||
59 | |||
60 | static void s3c_irq_timer_mask(unsigned int irq) | ||
61 | { | ||
62 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | ||
63 | |||
64 | reg &= 0x1f; /* mask out pending interrupts */ | ||
65 | reg &= ~(1 << (irq - IRQ_TIMER0)); | ||
66 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | ||
67 | } | ||
68 | |||
69 | static void s3c_irq_timer_unmask(unsigned int irq) | ||
70 | { | ||
71 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | ||
72 | |||
73 | reg &= 0x1f; /* mask out pending interrupts */ | ||
74 | reg |= 1 << (irq - IRQ_TIMER0); | ||
75 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | ||
76 | } | ||
77 | |||
78 | static void s3c_irq_timer_ack(unsigned int irq) | ||
79 | { | ||
80 | u32 reg = __raw_readl(S3C64XX_TINT_CSTAT); | ||
81 | |||
82 | reg &= 0x1f; | ||
83 | reg |= (1 << 5) << (irq - IRQ_TIMER0); | ||
84 | __raw_writel(reg, S3C64XX_TINT_CSTAT); | ||
85 | } | ||
86 | |||
87 | static struct irq_chip s3c_irq_timer = { | ||
88 | .name = "s3c-timer", | ||
89 | .mask = s3c_irq_timer_mask, | ||
90 | .unmask = s3c_irq_timer_unmask, | ||
91 | .ack = s3c_irq_timer_ack, | ||
92 | }; | ||
93 | |||
94 | struct uart_irq { | ||
95 | void __iomem *regs; | ||
96 | unsigned int base_irq; | ||
97 | unsigned int parent_irq; | ||
98 | }; | ||
99 | |||
100 | /* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] | ||
101 | * are consecutive when looking up the interrupt in the demux routines. | ||
102 | */ | ||
103 | static struct uart_irq uart_irqs[] = { | ||
104 | [0] = { | ||
105 | .regs = S3C_VA_UART0, | ||
106 | .base_irq = IRQ_S3CUART_BASE0, | ||
107 | .parent_irq = IRQ_UART0, | ||
108 | }, | ||
109 | [1] = { | ||
110 | .regs = S3C_VA_UART1, | ||
111 | .base_irq = IRQ_S3CUART_BASE1, | ||
112 | .parent_irq = IRQ_UART1, | ||
113 | }, | ||
114 | [2] = { | ||
115 | .regs = S3C_VA_UART2, | ||
116 | .base_irq = IRQ_S3CUART_BASE2, | ||
117 | .parent_irq = IRQ_UART2, | ||
118 | }, | ||
119 | [3] = { | ||
120 | .regs = S3C_VA_UART3, | ||
121 | .base_irq = IRQ_S3CUART_BASE3, | ||
122 | .parent_irq = IRQ_UART3, | ||
123 | }, | ||
124 | }; | ||
125 | |||
126 | static inline void __iomem *s3c_irq_uart_base(unsigned int irq) | ||
127 | { | ||
128 | struct uart_irq *uirq = get_irq_chip_data(irq); | ||
129 | return uirq->regs; | ||
130 | } | ||
131 | |||
132 | static inline unsigned int s3c_irq_uart_bit(unsigned int irq) | ||
133 | { | ||
134 | return irq & 3; | ||
135 | } | ||
136 | |||
137 | /* UART interrupt registers, not worth adding to seperate include header */ | ||
138 | #define S3C64XX_UINTP 0x30 | ||
139 | #define S3C64XX_UINTSP 0x34 | ||
140 | #define S3C64XX_UINTM 0x38 | ||
141 | |||
142 | static void s3c_irq_uart_mask(unsigned int irq) | ||
143 | { | ||
144 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
145 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
146 | u32 reg; | ||
147 | |||
148 | reg = __raw_readl(regs + S3C64XX_UINTM); | ||
149 | reg |= (1 << bit); | ||
150 | __raw_writel(reg, regs + S3C64XX_UINTM); | ||
151 | } | ||
152 | |||
153 | static void s3c_irq_uart_maskack(unsigned int irq) | ||
154 | { | ||
155 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
156 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
157 | u32 reg; | ||
158 | |||
159 | reg = __raw_readl(regs + S3C64XX_UINTM); | ||
160 | reg |= (1 << bit); | ||
161 | __raw_writel(reg, regs + S3C64XX_UINTM); | ||
162 | __raw_writel(1 << bit, regs + S3C64XX_UINTP); | ||
163 | } | ||
164 | |||
165 | static void s3c_irq_uart_unmask(unsigned int irq) | ||
166 | { | ||
167 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
168 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
169 | u32 reg; | ||
170 | |||
171 | reg = __raw_readl(regs + S3C64XX_UINTM); | ||
172 | reg &= ~(1 << bit); | ||
173 | __raw_writel(reg, regs + S3C64XX_UINTM); | ||
174 | } | ||
175 | |||
176 | static void s3c_irq_uart_ack(unsigned int irq) | ||
177 | { | ||
178 | void __iomem *regs = s3c_irq_uart_base(irq); | ||
179 | unsigned int bit = s3c_irq_uart_bit(irq); | ||
180 | |||
181 | __raw_writel(1 << bit, regs + S3C64XX_UINTP); | ||
182 | } | ||
183 | |||
184 | static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) | ||
185 | { | ||
186 | struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0]; | ||
187 | u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); | ||
188 | int base = uirq->base_irq; | ||
189 | |||
190 | if (pend & (1 << 0)) | ||
191 | generic_handle_irq(base); | ||
192 | if (pend & (1 << 1)) | ||
193 | generic_handle_irq(base + 1); | ||
194 | if (pend & (1 << 2)) | ||
195 | generic_handle_irq(base + 2); | ||
196 | if (pend & (1 << 3)) | ||
197 | generic_handle_irq(base + 3); | ||
198 | } | ||
199 | |||
200 | static struct irq_chip s3c_irq_uart = { | ||
201 | .name = "s3c-uart", | ||
202 | .mask = s3c_irq_uart_mask, | ||
203 | .unmask = s3c_irq_uart_unmask, | ||
204 | .mask_ack = s3c_irq_uart_maskack, | ||
205 | .ack = s3c_irq_uart_ack, | ||
206 | }; | ||
207 | |||
208 | static void __init s3c64xx_uart_irq(struct uart_irq *uirq) | ||
209 | { | ||
210 | void *reg_base = uirq->regs; | ||
211 | unsigned int irq; | ||
212 | int offs; | ||
213 | |||
214 | /* mask all interrupts at the start. */ | ||
215 | __raw_writel(0xf, reg_base + S3C64XX_UINTM); | ||
216 | |||
217 | for (offs = 0; offs < 3; offs++) { | ||
218 | irq = uirq->base_irq + offs; | ||
219 | |||
220 | set_irq_chip(irq, &s3c_irq_uart); | ||
221 | set_irq_chip_data(irq, uirq); | ||
222 | set_irq_handler(irq, handle_level_irq); | ||
223 | set_irq_flags(irq, IRQF_VALID); | ||
224 | } | ||
225 | |||
226 | set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); | ||
227 | } | ||
228 | |||
229 | void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid) | ||
230 | { | ||
231 | int uart, irq; | ||
232 | |||
233 | printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); | ||
234 | |||
235 | /* initialise the pair of VICs */ | ||
236 | vic_init(S3C_VA_VIC0, S3C_VIC0_BASE, vic0_valid); | ||
237 | vic_init(S3C_VA_VIC1, S3C_VIC1_BASE, vic1_valid); | ||
238 | |||
239 | /* add the timer sub-irqs */ | ||
240 | |||
241 | set_irq_chained_handler(IRQ_TIMER0_VIC, s3c_irq_demux_timer0); | ||
242 | set_irq_chained_handler(IRQ_TIMER1_VIC, s3c_irq_demux_timer1); | ||
243 | set_irq_chained_handler(IRQ_TIMER2_VIC, s3c_irq_demux_timer2); | ||
244 | set_irq_chained_handler(IRQ_TIMER3_VIC, s3c_irq_demux_timer3); | ||
245 | set_irq_chained_handler(IRQ_TIMER4_VIC, s3c_irq_demux_timer4); | ||
246 | |||
247 | for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) { | ||
248 | set_irq_chip(irq, &s3c_irq_timer); | ||
249 | set_irq_handler(irq, handle_level_irq); | ||
250 | set_irq_flags(irq, IRQF_VALID); | ||
251 | } | ||
252 | |||
253 | for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++) | ||
254 | s3c64xx_uart_irq(&uart_irqs[uart]); | ||
255 | } | ||
256 | |||
257 | |||
diff --git a/arch/arm/plat-s3c64xx/s3c6400-clock.c b/arch/arm/plat-s3c64xx/s3c6400-clock.c new file mode 100644 index 000000000000..8d9a0cada668 --- /dev/null +++ b/arch/arm/plat-s3c64xx/s3c6400-clock.c | |||
@@ -0,0 +1,655 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/s3c6400-clock.c | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C6400 based common clock support | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/init.h> | ||
16 | #include <linux/module.h> | ||
17 | #include <linux/kernel.h> | ||
18 | #include <linux/list.h> | ||
19 | #include <linux/errno.h> | ||
20 | #include <linux/err.h> | ||
21 | #include <linux/clk.h> | ||
22 | #include <linux/sysdev.h> | ||
23 | #include <linux/io.h> | ||
24 | |||
25 | #include <mach/hardware.h> | ||
26 | #include <mach/map.h> | ||
27 | |||
28 | #include <plat/cpu-freq.h> | ||
29 | |||
30 | #include <plat/regs-clock.h> | ||
31 | #include <plat/clock.h> | ||
32 | #include <plat/cpu.h> | ||
33 | #include <plat/pll.h> | ||
34 | |||
35 | /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call | ||
36 | * ext_xtal_mux for want of an actual name from the manual. | ||
37 | */ | ||
38 | |||
39 | struct clk clk_ext_xtal_mux = { | ||
40 | .name = "ext_xtal", | ||
41 | .id = -1, | ||
42 | }; | ||
43 | |||
44 | #define clk_fin_apll clk_ext_xtal_mux | ||
45 | #define clk_fin_mpll clk_ext_xtal_mux | ||
46 | #define clk_fin_epll clk_ext_xtal_mux | ||
47 | |||
48 | #define clk_fout_mpll clk_mpll | ||
49 | |||
50 | struct clk_sources { | ||
51 | unsigned int nr_sources; | ||
52 | struct clk **sources; | ||
53 | }; | ||
54 | |||
55 | struct clksrc_clk { | ||
56 | struct clk clk; | ||
57 | unsigned int mask; | ||
58 | unsigned int shift; | ||
59 | |||
60 | struct clk_sources *sources; | ||
61 | |||
62 | unsigned int divider_shift; | ||
63 | void __iomem *reg_divider; | ||
64 | }; | ||
65 | |||
66 | struct clk clk_fout_apll = { | ||
67 | .name = "fout_apll", | ||
68 | .id = -1, | ||
69 | }; | ||
70 | |||
71 | static struct clk *clk_src_apll_list[] = { | ||
72 | [0] = &clk_fin_apll, | ||
73 | [1] = &clk_fout_apll, | ||
74 | }; | ||
75 | |||
76 | static struct clk_sources clk_src_apll = { | ||
77 | .sources = clk_src_apll_list, | ||
78 | .nr_sources = ARRAY_SIZE(clk_src_apll_list), | ||
79 | }; | ||
80 | |||
81 | struct clksrc_clk clk_mout_apll = { | ||
82 | .clk = { | ||
83 | .name = "mout_apll", | ||
84 | .id = -1, | ||
85 | }, | ||
86 | .shift = S3C6400_CLKSRC_APLL_MOUT_SHIFT, | ||
87 | .mask = S3C6400_CLKSRC_APLL_MOUT, | ||
88 | .sources = &clk_src_apll, | ||
89 | }; | ||
90 | |||
91 | struct clk clk_fout_epll = { | ||
92 | .name = "fout_epll", | ||
93 | .id = -1, | ||
94 | }; | ||
95 | |||
96 | static struct clk *clk_src_epll_list[] = { | ||
97 | [0] = &clk_fin_epll, | ||
98 | [1] = &clk_fout_epll, | ||
99 | }; | ||
100 | |||
101 | static struct clk_sources clk_src_epll = { | ||
102 | .sources = clk_src_epll_list, | ||
103 | .nr_sources = ARRAY_SIZE(clk_src_epll_list), | ||
104 | }; | ||
105 | |||
106 | struct clksrc_clk clk_mout_epll = { | ||
107 | .clk = { | ||
108 | .name = "mout_epll", | ||
109 | .id = -1, | ||
110 | }, | ||
111 | .shift = S3C6400_CLKSRC_EPLL_MOUT_SHIFT, | ||
112 | .mask = S3C6400_CLKSRC_EPLL_MOUT, | ||
113 | .sources = &clk_src_epll, | ||
114 | }; | ||
115 | |||
116 | static struct clk *clk_src_mpll_list[] = { | ||
117 | [0] = &clk_fin_mpll, | ||
118 | [1] = &clk_fout_mpll, | ||
119 | }; | ||
120 | |||
121 | static struct clk_sources clk_src_mpll = { | ||
122 | .sources = clk_src_mpll_list, | ||
123 | .nr_sources = ARRAY_SIZE(clk_src_mpll_list), | ||
124 | }; | ||
125 | |||
126 | struct clksrc_clk clk_mout_mpll = { | ||
127 | .clk = { | ||
128 | .name = "mout_mpll", | ||
129 | .id = -1, | ||
130 | }, | ||
131 | .shift = S3C6400_CLKSRC_MPLL_MOUT_SHIFT, | ||
132 | .mask = S3C6400_CLKSRC_MPLL_MOUT, | ||
133 | .sources = &clk_src_mpll, | ||
134 | }; | ||
135 | |||
136 | static unsigned long s3c64xx_clk_doutmpll_get_rate(struct clk *clk) | ||
137 | { | ||
138 | unsigned long rate = clk_get_rate(clk->parent); | ||
139 | |||
140 | printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); | ||
141 | |||
142 | if (__raw_readl(S3C_CLK_DIV0) & S3C6400_CLKDIV0_MPLL_MASK) | ||
143 | rate /= 2; | ||
144 | |||
145 | return rate; | ||
146 | } | ||
147 | |||
148 | struct clk clk_dout_mpll = { | ||
149 | .name = "dout_mpll", | ||
150 | .id = -1, | ||
151 | .parent = &clk_mout_mpll.clk, | ||
152 | .get_rate = s3c64xx_clk_doutmpll_get_rate, | ||
153 | }; | ||
154 | |||
155 | static struct clk *clkset_spi_mmc_list[] = { | ||
156 | &clk_mout_epll.clk, | ||
157 | &clk_dout_mpll, | ||
158 | &clk_fin_epll, | ||
159 | &clk_27m, | ||
160 | }; | ||
161 | |||
162 | static struct clk_sources clkset_spi_mmc = { | ||
163 | .sources = clkset_spi_mmc_list, | ||
164 | .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), | ||
165 | }; | ||
166 | |||
167 | static struct clk *clkset_irda_list[] = { | ||
168 | &clk_mout_epll.clk, | ||
169 | &clk_dout_mpll, | ||
170 | NULL, | ||
171 | &clk_27m, | ||
172 | }; | ||
173 | |||
174 | static struct clk_sources clkset_irda = { | ||
175 | .sources = clkset_irda_list, | ||
176 | .nr_sources = ARRAY_SIZE(clkset_irda_list), | ||
177 | }; | ||
178 | |||
179 | static struct clk *clkset_uart_list[] = { | ||
180 | &clk_mout_epll.clk, | ||
181 | &clk_dout_mpll, | ||
182 | NULL, | ||
183 | NULL | ||
184 | }; | ||
185 | |||
186 | static struct clk_sources clkset_uart = { | ||
187 | .sources = clkset_uart_list, | ||
188 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | ||
189 | }; | ||
190 | |||
191 | static struct clk *clkset_uhost_list[] = { | ||
192 | &clk_mout_epll.clk, | ||
193 | &clk_dout_mpll, | ||
194 | &clk_fin_epll, | ||
195 | &clk_48m, | ||
196 | }; | ||
197 | |||
198 | static struct clk_sources clkset_uhost = { | ||
199 | .sources = clkset_uhost_list, | ||
200 | .nr_sources = ARRAY_SIZE(clkset_uhost_list), | ||
201 | }; | ||
202 | |||
203 | |||
204 | /* The peripheral clocks are all controlled via clocksource followed | ||
205 | * by an optional divider and gate stage. We currently roll this into | ||
206 | * one clock which hides the intermediate clock from the mux. | ||
207 | * | ||
208 | * Note, the JPEG clock can only be an even divider... | ||
209 | * | ||
210 | * The scaler and LCD clocks depend on the S3C64XX version, and also | ||
211 | * have a common parent divisor so are not included here. | ||
212 | */ | ||
213 | |||
214 | static inline struct clksrc_clk *to_clksrc(struct clk *clk) | ||
215 | { | ||
216 | return container_of(clk, struct clksrc_clk, clk); | ||
217 | } | ||
218 | |||
219 | static unsigned long s3c64xx_getrate_clksrc(struct clk *clk) | ||
220 | { | ||
221 | struct clksrc_clk *sclk = to_clksrc(clk); | ||
222 | unsigned long rate = clk_get_rate(clk->parent); | ||
223 | u32 clkdiv = __raw_readl(sclk->reg_divider); | ||
224 | |||
225 | clkdiv >>= sclk->divider_shift; | ||
226 | clkdiv &= 0xf; | ||
227 | clkdiv++; | ||
228 | |||
229 | rate /= clkdiv; | ||
230 | return rate; | ||
231 | } | ||
232 | |||
233 | static int s3c64xx_setrate_clksrc(struct clk *clk, unsigned long rate) | ||
234 | { | ||
235 | struct clksrc_clk *sclk = to_clksrc(clk); | ||
236 | void __iomem *reg = sclk->reg_divider; | ||
237 | unsigned int div; | ||
238 | u32 val; | ||
239 | |||
240 | rate = clk_round_rate(clk, rate); | ||
241 | div = clk_get_rate(clk->parent) / rate; | ||
242 | |||
243 | val = __raw_readl(reg); | ||
244 | val &= ~sclk->mask; | ||
245 | val |= (rate - 1) << sclk->shift; | ||
246 | __raw_writel(val, reg); | ||
247 | |||
248 | return 0; | ||
249 | } | ||
250 | |||
251 | static int s3c64xx_setparent_clksrc(struct clk *clk, struct clk *parent) | ||
252 | { | ||
253 | struct clksrc_clk *sclk = to_clksrc(clk); | ||
254 | struct clk_sources *srcs = sclk->sources; | ||
255 | u32 clksrc = __raw_readl(S3C_CLK_SRC); | ||
256 | int src_nr = -1; | ||
257 | int ptr; | ||
258 | |||
259 | for (ptr = 0; ptr < srcs->nr_sources; ptr++) | ||
260 | if (srcs->sources[ptr] == parent) { | ||
261 | src_nr = ptr; | ||
262 | break; | ||
263 | } | ||
264 | |||
265 | if (src_nr >= 0) { | ||
266 | clksrc &= ~sclk->mask; | ||
267 | clksrc |= src_nr << sclk->shift; | ||
268 | |||
269 | __raw_writel(clksrc, S3C_CLK_SRC); | ||
270 | return 0; | ||
271 | } | ||
272 | |||
273 | return -EINVAL; | ||
274 | } | ||
275 | |||
276 | static unsigned long s3c64xx_roundrate_clksrc(struct clk *clk, | ||
277 | unsigned long rate) | ||
278 | { | ||
279 | unsigned long parent_rate = clk_get_rate(clk->parent); | ||
280 | int div; | ||
281 | |||
282 | if (rate > parent_rate) | ||
283 | rate = parent_rate; | ||
284 | else { | ||
285 | div = rate / parent_rate; | ||
286 | |||
287 | if (div == 0) | ||
288 | div = 1; | ||
289 | if (div > 16) | ||
290 | div = 16; | ||
291 | |||
292 | rate = parent_rate / div; | ||
293 | } | ||
294 | |||
295 | return rate; | ||
296 | } | ||
297 | |||
298 | static struct clksrc_clk clk_mmc0 = { | ||
299 | .clk = { | ||
300 | .name = "mmc_bus", | ||
301 | .id = 0, | ||
302 | .ctrlbit = S3C_CLKCON_SCLK_MMC0, | ||
303 | .enable = s3c64xx_sclk_ctrl, | ||
304 | .set_parent = s3c64xx_setparent_clksrc, | ||
305 | .get_rate = s3c64xx_getrate_clksrc, | ||
306 | .set_rate = s3c64xx_setrate_clksrc, | ||
307 | .round_rate = s3c64xx_roundrate_clksrc, | ||
308 | }, | ||
309 | .shift = S3C6400_CLKSRC_MMC0_SHIFT, | ||
310 | .mask = S3C6400_CLKSRC_MMC0_MASK, | ||
311 | .sources = &clkset_spi_mmc, | ||
312 | .divider_shift = S3C6400_CLKDIV1_MMC0_SHIFT, | ||
313 | .reg_divider = S3C_CLK_DIV1, | ||
314 | }; | ||
315 | |||
316 | static struct clksrc_clk clk_mmc1 = { | ||
317 | .clk = { | ||
318 | .name = "mmc_bus", | ||
319 | .id = 1, | ||
320 | .ctrlbit = S3C_CLKCON_SCLK_MMC1, | ||
321 | .enable = s3c64xx_sclk_ctrl, | ||
322 | .get_rate = s3c64xx_getrate_clksrc, | ||
323 | .set_rate = s3c64xx_setrate_clksrc, | ||
324 | .set_parent = s3c64xx_setparent_clksrc, | ||
325 | .round_rate = s3c64xx_roundrate_clksrc, | ||
326 | }, | ||
327 | .shift = S3C6400_CLKSRC_MMC1_SHIFT, | ||
328 | .mask = S3C6400_CLKSRC_MMC1_MASK, | ||
329 | .sources = &clkset_spi_mmc, | ||
330 | .divider_shift = S3C6400_CLKDIV1_MMC1_SHIFT, | ||
331 | .reg_divider = S3C_CLK_DIV1, | ||
332 | }; | ||
333 | |||
334 | static struct clksrc_clk clk_mmc2 = { | ||
335 | .clk = { | ||
336 | .name = "mmc_bus", | ||
337 | .id = 2, | ||
338 | .ctrlbit = S3C_CLKCON_SCLK_MMC2, | ||
339 | .enable = s3c64xx_sclk_ctrl, | ||
340 | .get_rate = s3c64xx_getrate_clksrc, | ||
341 | .set_rate = s3c64xx_setrate_clksrc, | ||
342 | .set_parent = s3c64xx_setparent_clksrc, | ||
343 | .round_rate = s3c64xx_roundrate_clksrc, | ||
344 | }, | ||
345 | .shift = S3C6400_CLKSRC_MMC2_SHIFT, | ||
346 | .mask = S3C6400_CLKSRC_MMC2_MASK, | ||
347 | .sources = &clkset_spi_mmc, | ||
348 | .divider_shift = S3C6400_CLKDIV1_MMC2_SHIFT, | ||
349 | .reg_divider = S3C_CLK_DIV1, | ||
350 | }; | ||
351 | |||
352 | static struct clksrc_clk clk_usbhost = { | ||
353 | .clk = { | ||
354 | .name = "usb-host-bus", | ||
355 | .id = -1, | ||
356 | .ctrlbit = S3C_CLKCON_SCLK_UHOST, | ||
357 | .enable = s3c64xx_sclk_ctrl, | ||
358 | .set_parent = s3c64xx_setparent_clksrc, | ||
359 | .get_rate = s3c64xx_getrate_clksrc, | ||
360 | .set_rate = s3c64xx_setrate_clksrc, | ||
361 | .round_rate = s3c64xx_roundrate_clksrc, | ||
362 | }, | ||
363 | .shift = S3C6400_CLKSRC_UHOST_SHIFT, | ||
364 | .mask = S3C6400_CLKSRC_UHOST_MASK, | ||
365 | .sources = &clkset_uhost, | ||
366 | .divider_shift = S3C6400_CLKDIV1_UHOST_SHIFT, | ||
367 | .reg_divider = S3C_CLK_DIV1, | ||
368 | }; | ||
369 | |||
370 | static struct clksrc_clk clk_uart_uclk1 = { | ||
371 | .clk = { | ||
372 | .name = "uclk1", | ||
373 | .id = -1, | ||
374 | .ctrlbit = S3C_CLKCON_SCLK_UART, | ||
375 | .enable = s3c64xx_sclk_ctrl, | ||
376 | .set_parent = s3c64xx_setparent_clksrc, | ||
377 | .get_rate = s3c64xx_getrate_clksrc, | ||
378 | .set_rate = s3c64xx_setrate_clksrc, | ||
379 | .round_rate = s3c64xx_roundrate_clksrc, | ||
380 | }, | ||
381 | .shift = S3C6400_CLKSRC_UART_SHIFT, | ||
382 | .mask = S3C6400_CLKSRC_UART_MASK, | ||
383 | .sources = &clkset_uart, | ||
384 | .divider_shift = S3C6400_CLKDIV2_UART_SHIFT, | ||
385 | .reg_divider = S3C_CLK_DIV2, | ||
386 | }; | ||
387 | |||
388 | /* Where does UCLK0 come from? */ | ||
389 | |||
390 | static struct clksrc_clk clk_spi0 = { | ||
391 | .clk = { | ||
392 | .name = "spi-bus", | ||
393 | .id = 0, | ||
394 | .ctrlbit = S3C_CLKCON_SCLK_SPI0, | ||
395 | .enable = s3c64xx_sclk_ctrl, | ||
396 | .set_parent = s3c64xx_setparent_clksrc, | ||
397 | .get_rate = s3c64xx_getrate_clksrc, | ||
398 | .set_rate = s3c64xx_setrate_clksrc, | ||
399 | .round_rate = s3c64xx_roundrate_clksrc, | ||
400 | }, | ||
401 | .shift = S3C6400_CLKSRC_SPI0_SHIFT, | ||
402 | .mask = S3C6400_CLKSRC_SPI0_MASK, | ||
403 | .sources = &clkset_spi_mmc, | ||
404 | .divider_shift = S3C6400_CLKDIV2_SPI0_SHIFT, | ||
405 | .reg_divider = S3C_CLK_DIV2, | ||
406 | }; | ||
407 | |||
408 | static struct clksrc_clk clk_spi1 = { | ||
409 | .clk = { | ||
410 | .name = "spi-bus", | ||
411 | .id = 1, | ||
412 | .ctrlbit = S3C_CLKCON_SCLK_SPI1, | ||
413 | .enable = s3c64xx_sclk_ctrl, | ||
414 | .set_parent = s3c64xx_setparent_clksrc, | ||
415 | .get_rate = s3c64xx_getrate_clksrc, | ||
416 | .set_rate = s3c64xx_setrate_clksrc, | ||
417 | .round_rate = s3c64xx_roundrate_clksrc, | ||
418 | }, | ||
419 | .shift = S3C6400_CLKSRC_SPI1_SHIFT, | ||
420 | .mask = S3C6400_CLKSRC_SPI1_MASK, | ||
421 | .sources = &clkset_spi_mmc, | ||
422 | .divider_shift = S3C6400_CLKDIV2_SPI1_SHIFT, | ||
423 | .reg_divider = S3C_CLK_DIV2, | ||
424 | }; | ||
425 | |||
426 | static struct clk clk_iis_cd0 = { | ||
427 | .name = "iis_cdclk0", | ||
428 | .id = -1, | ||
429 | }; | ||
430 | |||
431 | static struct clk clk_iis_cd1 = { | ||
432 | .name = "iis_cdclk1", | ||
433 | .id = -1, | ||
434 | }; | ||
435 | |||
436 | static struct clk clk_pcm_cd = { | ||
437 | .name = "pcm_cdclk", | ||
438 | .id = -1, | ||
439 | }; | ||
440 | |||
441 | static struct clk *clkset_audio0_list[] = { | ||
442 | [0] = &clk_mout_epll.clk, | ||
443 | [1] = &clk_dout_mpll, | ||
444 | [2] = &clk_fin_epll, | ||
445 | [3] = &clk_iis_cd0, | ||
446 | [4] = &clk_pcm_cd, | ||
447 | }; | ||
448 | |||
449 | static struct clk_sources clkset_audio0 = { | ||
450 | .sources = clkset_audio0_list, | ||
451 | .nr_sources = ARRAY_SIZE(clkset_audio0_list), | ||
452 | }; | ||
453 | |||
454 | static struct clksrc_clk clk_audio0 = { | ||
455 | .clk = { | ||
456 | .name = "audio-bus", | ||
457 | .id = 0, | ||
458 | .ctrlbit = S3C_CLKCON_SCLK_AUDIO0, | ||
459 | .enable = s3c64xx_sclk_ctrl, | ||
460 | .set_parent = s3c64xx_setparent_clksrc, | ||
461 | .get_rate = s3c64xx_getrate_clksrc, | ||
462 | .set_rate = s3c64xx_setrate_clksrc, | ||
463 | .round_rate = s3c64xx_roundrate_clksrc, | ||
464 | }, | ||
465 | .shift = S3C6400_CLKSRC_AUDIO0_SHIFT, | ||
466 | .mask = S3C6400_CLKSRC_AUDIO0_MASK, | ||
467 | .sources = &clkset_audio0, | ||
468 | .divider_shift = S3C6400_CLKDIV2_AUDIO0_SHIFT, | ||
469 | .reg_divider = S3C_CLK_DIV2, | ||
470 | }; | ||
471 | |||
472 | static struct clk *clkset_audio1_list[] = { | ||
473 | [0] = &clk_mout_epll.clk, | ||
474 | [1] = &clk_dout_mpll, | ||
475 | [2] = &clk_fin_epll, | ||
476 | [3] = &clk_iis_cd1, | ||
477 | [4] = &clk_pcm_cd, | ||
478 | }; | ||
479 | |||
480 | static struct clk_sources clkset_audio1 = { | ||
481 | .sources = clkset_audio1_list, | ||
482 | .nr_sources = ARRAY_SIZE(clkset_audio1_list), | ||
483 | }; | ||
484 | |||
485 | static struct clksrc_clk clk_audio1 = { | ||
486 | .clk = { | ||
487 | .name = "audio-bus", | ||
488 | .id = 1, | ||
489 | .ctrlbit = S3C_CLKCON_SCLK_AUDIO1, | ||
490 | .enable = s3c64xx_sclk_ctrl, | ||
491 | .set_parent = s3c64xx_setparent_clksrc, | ||
492 | .get_rate = s3c64xx_getrate_clksrc, | ||
493 | .set_rate = s3c64xx_setrate_clksrc, | ||
494 | .round_rate = s3c64xx_roundrate_clksrc, | ||
495 | }, | ||
496 | .shift = S3C6400_CLKSRC_AUDIO1_SHIFT, | ||
497 | .mask = S3C6400_CLKSRC_AUDIO1_MASK, | ||
498 | .sources = &clkset_audio1, | ||
499 | .divider_shift = S3C6400_CLKDIV2_AUDIO1_SHIFT, | ||
500 | .reg_divider = S3C_CLK_DIV2, | ||
501 | }; | ||
502 | |||
503 | static struct clksrc_clk clk_irda = { | ||
504 | .clk = { | ||
505 | .name = "irda-bus", | ||
506 | .id = 0, | ||
507 | .ctrlbit = S3C_CLKCON_SCLK_IRDA, | ||
508 | .enable = s3c64xx_sclk_ctrl, | ||
509 | .set_parent = s3c64xx_setparent_clksrc, | ||
510 | .get_rate = s3c64xx_getrate_clksrc, | ||
511 | .set_rate = s3c64xx_setrate_clksrc, | ||
512 | .round_rate = s3c64xx_roundrate_clksrc, | ||
513 | }, | ||
514 | .shift = S3C6400_CLKSRC_IRDA_SHIFT, | ||
515 | .mask = S3C6400_CLKSRC_IRDA_MASK, | ||
516 | .sources = &clkset_irda, | ||
517 | .divider_shift = S3C6400_CLKDIV2_IRDA_SHIFT, | ||
518 | .reg_divider = S3C_CLK_DIV2, | ||
519 | }; | ||
520 | |||
521 | /* Clock initialisation code */ | ||
522 | |||
523 | static struct clksrc_clk *init_parents[] = { | ||
524 | &clk_mout_apll, | ||
525 | &clk_mout_epll, | ||
526 | &clk_mout_mpll, | ||
527 | &clk_mmc0, | ||
528 | &clk_mmc1, | ||
529 | &clk_mmc2, | ||
530 | &clk_usbhost, | ||
531 | &clk_uart_uclk1, | ||
532 | &clk_spi0, | ||
533 | &clk_spi1, | ||
534 | &clk_audio0, | ||
535 | &clk_audio1, | ||
536 | &clk_irda, | ||
537 | }; | ||
538 | |||
539 | static void __init_or_cpufreq s3c6400_set_clksrc(struct clksrc_clk *clk) | ||
540 | { | ||
541 | struct clk_sources *srcs = clk->sources; | ||
542 | u32 clksrc = __raw_readl(S3C_CLK_SRC); | ||
543 | |||
544 | clksrc &= clk->mask; | ||
545 | clksrc >>= clk->shift; | ||
546 | |||
547 | if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) { | ||
548 | printk(KERN_ERR "%s: bad source %d\n", | ||
549 | clk->clk.name, clksrc); | ||
550 | return; | ||
551 | } | ||
552 | |||
553 | clk->clk.parent = srcs->sources[clksrc]; | ||
554 | |||
555 | printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n", | ||
556 | clk->clk.name, clk->clk.parent->name, clksrc, | ||
557 | clk_get_rate(&clk->clk)); | ||
558 | } | ||
559 | |||
560 | #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) | ||
561 | |||
562 | void __init_or_cpufreq s3c6400_setup_clocks(void) | ||
563 | { | ||
564 | struct clk *xtal_clk; | ||
565 | unsigned long xtal; | ||
566 | unsigned long fclk; | ||
567 | unsigned long hclk; | ||
568 | unsigned long hclk2; | ||
569 | unsigned long pclk; | ||
570 | unsigned long epll; | ||
571 | unsigned long apll; | ||
572 | unsigned long mpll; | ||
573 | unsigned int ptr; | ||
574 | u32 clkdiv0; | ||
575 | |||
576 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); | ||
577 | |||
578 | clkdiv0 = __raw_readl(S3C_CLK_DIV0); | ||
579 | printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0); | ||
580 | |||
581 | xtal_clk = clk_get(NULL, "xtal"); | ||
582 | BUG_ON(IS_ERR(xtal_clk)); | ||
583 | |||
584 | xtal = clk_get_rate(xtal_clk); | ||
585 | clk_put(xtal_clk); | ||
586 | |||
587 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); | ||
588 | |||
589 | epll = s3c6400_get_epll(xtal); | ||
590 | mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON)); | ||
591 | apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON)); | ||
592 | |||
593 | fclk = mpll; | ||
594 | |||
595 | printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n", | ||
596 | apll, mpll, epll); | ||
597 | |||
598 | hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2); | ||
599 | hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK); | ||
600 | pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK); | ||
601 | |||
602 | printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n", | ||
603 | hclk2, hclk, pclk); | ||
604 | |||
605 | clk_fout_mpll.rate = mpll; | ||
606 | clk_fout_epll.rate = epll; | ||
607 | clk_fout_apll.rate = apll; | ||
608 | |||
609 | clk_h.rate = hclk; | ||
610 | clk_p.rate = pclk; | ||
611 | clk_f.rate = fclk; | ||
612 | |||
613 | for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) | ||
614 | s3c6400_set_clksrc(init_parents[ptr]); | ||
615 | } | ||
616 | |||
617 | static struct clk *clks[] __initdata = { | ||
618 | &clk_ext_xtal_mux, | ||
619 | &clk_iis_cd0, | ||
620 | &clk_iis_cd1, | ||
621 | &clk_pcm_cd, | ||
622 | &clk_mout_epll.clk, | ||
623 | &clk_fout_epll, | ||
624 | &clk_mout_mpll.clk, | ||
625 | &clk_dout_mpll, | ||
626 | &clk_mmc0.clk, | ||
627 | &clk_mmc1.clk, | ||
628 | &clk_mmc2.clk, | ||
629 | &clk_usbhost.clk, | ||
630 | &clk_uart_uclk1.clk, | ||
631 | &clk_spi0.clk, | ||
632 | &clk_spi1.clk, | ||
633 | &clk_audio0.clk, | ||
634 | &clk_audio1.clk, | ||
635 | &clk_irda.clk, | ||
636 | }; | ||
637 | |||
638 | void __init s3c6400_register_clocks(void) | ||
639 | { | ||
640 | struct clk *clkp; | ||
641 | int ret; | ||
642 | int ptr; | ||
643 | |||
644 | for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { | ||
645 | clkp = clks[ptr]; | ||
646 | ret = s3c24xx_register_clock(clkp); | ||
647 | if (ret < 0) { | ||
648 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
649 | clkp->name, ret); | ||
650 | } | ||
651 | } | ||
652 | |||
653 | clk_mpll.parent = &clk_mout_mpll.clk; | ||
654 | clk_epll.parent = &clk_mout_epll.clk; | ||
655 | } | ||
diff --git a/arch/arm/plat-s3c64xx/s3c6400-init.c b/arch/arm/plat-s3c64xx/s3c6400-init.c new file mode 100644 index 000000000000..6c28f39df097 --- /dev/null +++ b/arch/arm/plat-s3c64xx/s3c6400-init.c | |||
@@ -0,0 +1,29 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/s3c6400-init.c | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C6400 - CPU initialisation (common with other S3C64XX chips) | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/types.h> | ||
17 | #include <linux/init.h> | ||
18 | |||
19 | #include <plat/cpu.h> | ||
20 | #include <plat/devs.h> | ||
21 | #include <plat/s3c6400.h> | ||
22 | #include <plat/s3c6410.h> | ||
23 | |||
24 | /* uart registration process */ | ||
25 | |||
26 | void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) | ||
27 | { | ||
28 | s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no); | ||
29 | } | ||
diff --git a/arch/arm/plat-s3c64xx/setup-fb-24bpp.c b/arch/arm/plat-s3c64xx/setup-fb-24bpp.c new file mode 100644 index 000000000000..8e28e448dd20 --- /dev/null +++ b/arch/arm/plat-s3c64xx/setup-fb-24bpp.c | |||
@@ -0,0 +1,37 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/setup-fb-24bpp.c | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * Base S3C64XX setup information for 24bpp LCD framebuffer | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/types.h> | ||
17 | #include <linux/fb.h> | ||
18 | |||
19 | #include <mach/regs-fb.h> | ||
20 | #include <mach/gpio.h> | ||
21 | #include <plat/fb.h> | ||
22 | #include <plat/gpio-cfg.h> | ||
23 | |||
24 | extern void s3c64xx_fb_gpio_setup_24bpp(void) | ||
25 | { | ||
26 | unsigned int gpio; | ||
27 | |||
28 | for (gpio = S3C64XX_GPI(0); gpio <= S3C64XX_GPI(15); gpio++) { | ||
29 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
30 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
31 | } | ||
32 | |||
33 | for (gpio = S3C64XX_GPJ(0); gpio <= S3C64XX_GPJ(11); gpio++) { | ||
34 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
35 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
36 | } | ||
37 | } | ||
diff --git a/arch/arm/plat-s3c64xx/setup-i2c0.c b/arch/arm/plat-s3c64xx/setup-i2c0.c new file mode 100644 index 000000000000..364480763728 --- /dev/null +++ b/arch/arm/plat-s3c64xx/setup-i2c0.c | |||
@@ -0,0 +1,31 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/setup-i2c0.c | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * Base S3C64XX I2C bus 0 gpio configuration | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/types.h> | ||
17 | |||
18 | struct platform_device; /* don't need the contents */ | ||
19 | |||
20 | #include <mach/gpio.h> | ||
21 | #include <plat/iic.h> | ||
22 | #include <plat/gpio-bank-b.h> | ||
23 | #include <plat/gpio-cfg.h> | ||
24 | |||
25 | void s3c_i2c0_cfg_gpio(struct platform_device *dev) | ||
26 | { | ||
27 | s3c_gpio_cfgpin(S3C64XX_GPB(5), S3C64XX_GPB5_I2C_SCL0); | ||
28 | s3c_gpio_cfgpin(S3C64XX_GPB(6), S3C64XX_GPB6_I2C_SDA0); | ||
29 | s3c_gpio_setpull(S3C64XX_GPB(5), S3C_GPIO_PULL_UP); | ||
30 | s3c_gpio_setpull(S3C64XX_GPB(6), S3C_GPIO_PULL_UP); | ||
31 | } | ||
diff --git a/arch/arm/plat-s3c64xx/setup-i2c1.c b/arch/arm/plat-s3c64xx/setup-i2c1.c new file mode 100644 index 000000000000..bbe229bd90ca --- /dev/null +++ b/arch/arm/plat-s3c64xx/setup-i2c1.c | |||
@@ -0,0 +1,31 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/setup-i2c1.c | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * Base S3C64XX I2C bus 1 gpio configuration | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/types.h> | ||
17 | |||
18 | struct platform_device; /* don't need the contents */ | ||
19 | |||
20 | #include <mach/gpio.h> | ||
21 | #include <plat/iic.h> | ||
22 | #include <plat/gpio-bank-b.h> | ||
23 | #include <plat/gpio-cfg.h> | ||
24 | |||
25 | void s3c_i2c1_cfg_gpio(struct platform_device *dev) | ||
26 | { | ||
27 | s3c_gpio_cfgpin(S3C64XX_GPB(2), S3C64XX_GPB2_I2C_SCL1); | ||
28 | s3c_gpio_cfgpin(S3C64XX_GPB(3), S3C64XX_GPB3_I2C_SDA1); | ||
29 | s3c_gpio_setpull(S3C64XX_GPB(2), S3C_GPIO_PULL_UP); | ||
30 | s3c_gpio_setpull(S3C64XX_GPB(3), S3C_GPIO_PULL_UP); | ||
31 | } | ||