diff options
author | Steven Whitehouse <swhiteho@redhat.com> | 2006-08-29 11:39:34 -0400 |
---|---|---|
committer | Steven Whitehouse <swhiteho@redhat.com> | 2006-08-29 11:39:34 -0400 |
commit | 83b7a664a0c7c39ccfa4c72535dc1c001d4e7a18 (patch) | |
tree | 5ba3bbbe977c2047658b41e22d6b2abd5686bf15 /arch/arm | |
parent | 8638460540749ddb1beca9e9a68d655a6fe6df65 (diff) | |
parent | d96299537e43681942ea272e00b0e529aa5b5fa4 (diff) |
Merge branch 'master' into gfs2
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/Makefile | 3 | ||||
-rw-r--r-- | arch/arm/common/dmabounce.c | 8 | ||||
-rw-r--r-- | arch/arm/common/rtctime.c | 1 | ||||
-rw-r--r-- | arch/arm/common/sa1111.c | 6 | ||||
-rw-r--r-- | arch/arm/kernel/Makefile | 3 | ||||
-rw-r--r-- | arch/arm/kernel/entry-armv.S | 21 | ||||
-rw-r--r-- | arch/arm/kernel/head.S | 2 | ||||
-rw-r--r-- | arch/arm/kernel/isa.c | 63 | ||||
-rw-r--r-- | arch/arm/kernel/traps.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-footbridge/dc21285.c | 1 | ||||
-rw-r--r-- | arch/arm/mach-integrator/pci_v3.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/common-pci.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-ixp4xx/gtwx5715-setup.c | 7 | ||||
-rw-r--r-- | arch/arm/mach-pxa/corgi_ssp.c | 20 | ||||
-rw-r--r-- | arch/arm/mach-pxa/ssp.c | 35 | ||||
-rw-r--r-- | arch/arm/mach-s3c2410/Makefile | 36 | ||||
-rw-r--r-- | arch/arm/mach-s3c2410/dma.c | 163 | ||||
-rw-r--r-- | arch/arm/mach-sa1100/ssp.c | 46 | ||||
-rw-r--r-- | arch/arm/mach-versatile/core.c | 2 | ||||
-rw-r--r-- | arch/arm/mm/Kconfig | 13 | ||||
-rw-r--r-- | arch/arm/vfp/vfp.h | 8 | ||||
-rw-r--r-- | arch/arm/vfp/vfpdouble.c | 30 | ||||
-rw-r--r-- | arch/arm/vfp/vfpmodule.c | 4 | ||||
-rw-r--r-- | arch/arm/vfp/vfpsingle.c | 35 |
24 files changed, 380 insertions, 133 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 3345c6d0fd1e..92873cdee31f 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
@@ -47,7 +47,8 @@ comma = , | |||
47 | # testing for a specific architecture or later rather impossible. | 47 | # testing for a specific architecture or later rather impossible. |
48 | arch-$(CONFIG_CPU_32v6) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6) | 48 | arch-$(CONFIG_CPU_32v6) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6) |
49 | arch-$(CONFIG_CPU_32v6K) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k) | 49 | arch-$(CONFIG_CPU_32v6K) :=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k) |
50 | arch-$(CONFIG_CPU_32v5) :=-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4) | 50 | arch-$(CONFIG_CPU_32v5) :=-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t) |
51 | arch-$(CONFIG_CPU_32v4T) :=-D__LINUX_ARM_ARCH__=4 -march=armv4t | ||
51 | arch-$(CONFIG_CPU_32v4) :=-D__LINUX_ARM_ARCH__=4 -march=armv4 | 52 | arch-$(CONFIG_CPU_32v4) :=-D__LINUX_ARM_ARCH__=4 -march=armv4 |
52 | arch-$(CONFIG_CPU_32v3) :=-D__LINUX_ARM_ARCH__=3 -march=armv3 | 53 | arch-$(CONFIG_CPU_32v3) :=-D__LINUX_ARM_ARCH__=3 -march=armv3 |
53 | 54 | ||
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c index 5b7c26395b44..028bdc9228fb 100644 --- a/arch/arm/common/dmabounce.c +++ b/arch/arm/common/dmabounce.c | |||
@@ -179,17 +179,19 @@ alloc_safe_buffer(struct dmabounce_device_info *device_info, void *ptr, | |||
179 | static inline struct safe_buffer * | 179 | static inline struct safe_buffer * |
180 | find_safe_buffer(struct dmabounce_device_info *device_info, dma_addr_t safe_dma_addr) | 180 | find_safe_buffer(struct dmabounce_device_info *device_info, dma_addr_t safe_dma_addr) |
181 | { | 181 | { |
182 | struct safe_buffer *b = NULL; | 182 | struct safe_buffer *b, *rb = NULL; |
183 | unsigned long flags; | 183 | unsigned long flags; |
184 | 184 | ||
185 | read_lock_irqsave(&device_info->lock, flags); | 185 | read_lock_irqsave(&device_info->lock, flags); |
186 | 186 | ||
187 | list_for_each_entry(b, &device_info->safe_buffers, node) | 187 | list_for_each_entry(b, &device_info->safe_buffers, node) |
188 | if (b->safe_dma_addr == safe_dma_addr) | 188 | if (b->safe_dma_addr == safe_dma_addr) { |
189 | rb = b; | ||
189 | break; | 190 | break; |
191 | } | ||
190 | 192 | ||
191 | read_unlock_irqrestore(&device_info->lock, flags); | 193 | read_unlock_irqrestore(&device_info->lock, flags); |
192 | return b; | 194 | return rb; |
193 | } | 195 | } |
194 | 196 | ||
195 | static inline void | 197 | static inline void |
diff --git a/arch/arm/common/rtctime.c b/arch/arm/common/rtctime.c index 35c9a64ac14c..4e5445cfb0ea 100644 --- a/arch/arm/common/rtctime.c +++ b/arch/arm/common/rtctime.c | |||
@@ -68,6 +68,7 @@ void rtc_next_alarm_time(struct rtc_time *next, struct rtc_time *now, struct rtc | |||
68 | rtc_time_to_tm(next_time, next); | 68 | rtc_time_to_tm(next_time, next); |
69 | } | 69 | } |
70 | } | 70 | } |
71 | EXPORT_SYMBOL(rtc_next_alarm_time); | ||
71 | 72 | ||
72 | static inline int rtc_arm_read_time(struct rtc_ops *ops, struct rtc_time *tm) | 73 | static inline int rtc_arm_read_time(struct rtc_ops *ops, struct rtc_time *tm) |
73 | { | 74 | { |
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index a331c12cead9..29818bd3248f 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c | |||
@@ -618,7 +618,7 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq) | |||
618 | { | 618 | { |
619 | struct sa1111 *sachip; | 619 | struct sa1111 *sachip; |
620 | unsigned long id; | 620 | unsigned long id; |
621 | unsigned int has_devs, val; | 621 | unsigned int has_devs; |
622 | int i, ret = -ENODEV; | 622 | int i, ret = -ENODEV; |
623 | 623 | ||
624 | sachip = kzalloc(sizeof(struct sa1111), GFP_KERNEL); | 624 | sachip = kzalloc(sizeof(struct sa1111), GFP_KERNEL); |
@@ -669,6 +669,9 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq) | |||
669 | sa1111_wake(sachip); | 669 | sa1111_wake(sachip); |
670 | 670 | ||
671 | #ifdef CONFIG_ARCH_SA1100 | 671 | #ifdef CONFIG_ARCH_SA1100 |
672 | { | ||
673 | unsigned int val; | ||
674 | |||
672 | /* | 675 | /* |
673 | * The SDRAM configuration of the SA1110 and the SA1111 must | 676 | * The SDRAM configuration of the SA1110 and the SA1111 must |
674 | * match. This is very important to ensure that SA1111 accesses | 677 | * match. This is very important to ensure that SA1111 accesses |
@@ -692,6 +695,7 @@ __sa1111_probe(struct device *me, struct resource *mem, int irq) | |||
692 | * Enable the SA1110 memory bus request and grant signals. | 695 | * Enable the SA1110 memory bus request and grant signals. |
693 | */ | 696 | */ |
694 | sa1110_mb_enable(); | 697 | sa1110_mb_enable(); |
698 | } | ||
695 | #endif | 699 | #endif |
696 | 700 | ||
697 | /* | 701 | /* |
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index f0c0cdb1c183..1320a0efca73 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile | |||
@@ -13,12 +13,11 @@ obj-y := compat.o entry-armv.o entry-common.o irq.o \ | |||
13 | obj-$(CONFIG_APM) += apm.o | 13 | obj-$(CONFIG_APM) += apm.o |
14 | obj-$(CONFIG_ISA_DMA_API) += dma.o | 14 | obj-$(CONFIG_ISA_DMA_API) += dma.o |
15 | obj-$(CONFIG_ARCH_ACORN) += ecard.o | 15 | obj-$(CONFIG_ARCH_ACORN) += ecard.o |
16 | obj-$(CONFIG_FOOTBRIDGE) += isa.o | ||
17 | obj-$(CONFIG_FIQ) += fiq.o | 16 | obj-$(CONFIG_FIQ) += fiq.o |
18 | obj-$(CONFIG_MODULES) += armksyms.o module.o | 17 | obj-$(CONFIG_MODULES) += armksyms.o module.o |
19 | obj-$(CONFIG_ARTHUR) += arthur.o | 18 | obj-$(CONFIG_ARTHUR) += arthur.o |
20 | obj-$(CONFIG_ISA_DMA) += dma-isa.o | 19 | obj-$(CONFIG_ISA_DMA) += dma-isa.o |
21 | obj-$(CONFIG_PCI) += bios32.o | 20 | obj-$(CONFIG_PCI) += bios32.o isa.o |
22 | obj-$(CONFIG_SMP) += smp.o | 21 | obj-$(CONFIG_SMP) += smp.o |
23 | obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o | 22 | obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o |
24 | 23 | ||
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 7ea5f01dfc7b..de4e33137901 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S | |||
@@ -634,6 +634,14 @@ ENTRY(__switch_to) | |||
634 | * purpose. | 634 | * purpose. |
635 | */ | 635 | */ |
636 | 636 | ||
637 | .macro usr_ret, reg | ||
638 | #ifdef CONFIG_ARM_THUMB | ||
639 | bx \reg | ||
640 | #else | ||
641 | mov pc, \reg | ||
642 | #endif | ||
643 | .endm | ||
644 | |||
637 | .align 5 | 645 | .align 5 |
638 | .globl __kuser_helper_start | 646 | .globl __kuser_helper_start |
639 | __kuser_helper_start: | 647 | __kuser_helper_start: |
@@ -675,7 +683,7 @@ __kuser_memory_barrier: @ 0xffff0fa0 | |||
675 | #if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP) | 683 | #if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP) |
676 | mcr p15, 0, r0, c7, c10, 5 @ dmb | 684 | mcr p15, 0, r0, c7, c10, 5 @ dmb |
677 | #endif | 685 | #endif |
678 | mov pc, lr | 686 | usr_ret lr |
679 | 687 | ||
680 | .align 5 | 688 | .align 5 |
681 | 689 | ||
@@ -778,7 +786,7 @@ __kuser_cmpxchg: @ 0xffff0fc0 | |||
778 | mov r0, #-1 | 786 | mov r0, #-1 |
779 | adds r0, r0, #0 | 787 | adds r0, r0, #0 |
780 | #endif | 788 | #endif |
781 | mov pc, lr | 789 | usr_ret lr |
782 | 790 | ||
783 | #else | 791 | #else |
784 | 792 | ||
@@ -792,7 +800,7 @@ __kuser_cmpxchg: @ 0xffff0fc0 | |||
792 | #ifdef CONFIG_SMP | 800 | #ifdef CONFIG_SMP |
793 | mcr p15, 0, r0, c7, c10, 5 @ dmb | 801 | mcr p15, 0, r0, c7, c10, 5 @ dmb |
794 | #endif | 802 | #endif |
795 | mov pc, lr | 803 | usr_ret lr |
796 | 804 | ||
797 | #endif | 805 | #endif |
798 | 806 | ||
@@ -834,16 +842,11 @@ __kuser_cmpxchg: @ 0xffff0fc0 | |||
834 | __kuser_get_tls: @ 0xffff0fe0 | 842 | __kuser_get_tls: @ 0xffff0fe0 |
835 | 843 | ||
836 | #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) | 844 | #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL) |
837 | |||
838 | ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 | 845 | ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0 |
839 | mov pc, lr | ||
840 | |||
841 | #else | 846 | #else |
842 | |||
843 | mrc p15, 0, r0, c13, c0, 3 @ read TLS register | 847 | mrc p15, 0, r0, c13, c0, 3 @ read TLS register |
844 | mov pc, lr | ||
845 | |||
846 | #endif | 848 | #endif |
849 | usr_ret lr | ||
847 | 850 | ||
848 | .rep 5 | 851 | .rep 5 |
849 | .word 0 @ pad up to __kuser_helper_version | 852 | .word 0 @ pad up to __kuser_helper_version |
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 4fe386eea4b4..5365d4e5949e 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S | |||
@@ -118,7 +118,7 @@ ENTRY(secondary_startup) | |||
118 | sub r4, r4, r5 @ mmu has been enabled | 118 | sub r4, r4, r5 @ mmu has been enabled |
119 | ldr r4, [r7, r4] @ get secondary_data.pgdir | 119 | ldr r4, [r7, r4] @ get secondary_data.pgdir |
120 | adr lr, __enable_mmu @ return address | 120 | adr lr, __enable_mmu @ return address |
121 | add pc, r10, #12 @ initialise processor | 121 | add pc, r10, #PROCINFO_INITFUNC @ initialise processor |
122 | @ (return control reg) | 122 | @ (return control reg) |
123 | 123 | ||
124 | /* | 124 | /* |
diff --git a/arch/arm/kernel/isa.c b/arch/arm/kernel/isa.c index 685c3e591a7e..54bbd9fe255c 100644 --- a/arch/arm/kernel/isa.c +++ b/arch/arm/kernel/isa.c | |||
@@ -3,21 +3,14 @@ | |||
3 | * | 3 | * |
4 | * Copyright (C) 1999 Phil Blundell | 4 | * Copyright (C) 1999 Phil Blundell |
5 | * | 5 | * |
6 | * ISA shared memory and I/O port support | ||
7 | */ | ||
8 | |||
9 | /* | ||
10 | * This program is free software; you can redistribute it and/or | 6 | * This program is free software; you can redistribute it and/or |
11 | * modify it under the terms of the GNU General Public License | 7 | * modify it under the terms of the GNU General Public License |
12 | * as published by the Free Software Foundation; either version | 8 | * as published by the Free Software Foundation; either version |
13 | * 2 of the License, or (at your option) any later version. | 9 | * 2 of the License, or (at your option) any later version. |
10 | * | ||
11 | * ISA shared memory and I/O port support, and is required to support | ||
12 | * iopl, inb, outb and friends in userspace via glibc emulation. | ||
14 | */ | 13 | */ |
15 | |||
16 | /* | ||
17 | * Nothing about this is actually ARM specific. One day we could move | ||
18 | * it into kernel/resource.c or some place like that. | ||
19 | */ | ||
20 | |||
21 | #include <linux/stddef.h> | 14 | #include <linux/stddef.h> |
22 | #include <linux/types.h> | 15 | #include <linux/types.h> |
23 | #include <linux/fs.h> | 16 | #include <linux/fs.h> |
@@ -27,21 +20,49 @@ | |||
27 | static unsigned int isa_membase, isa_portbase, isa_portshift; | 20 | static unsigned int isa_membase, isa_portbase, isa_portshift; |
28 | 21 | ||
29 | static ctl_table ctl_isa_vars[4] = { | 22 | static ctl_table ctl_isa_vars[4] = { |
30 | {BUS_ISA_MEM_BASE, "membase", &isa_membase, | 23 | { |
31 | sizeof(isa_membase), 0444, NULL, &proc_dointvec}, | 24 | .ctl_name = BUS_ISA_MEM_BASE, |
32 | {BUS_ISA_PORT_BASE, "portbase", &isa_portbase, | 25 | .procname = "membase", |
33 | sizeof(isa_portbase), 0444, NULL, &proc_dointvec}, | 26 | .data = &isa_membase, |
34 | {BUS_ISA_PORT_SHIFT, "portshift", &isa_portshift, | 27 | .maxlen = sizeof(isa_membase), |
35 | sizeof(isa_portshift), 0444, NULL, &proc_dointvec}, | 28 | .mode = 0444, |
36 | {0} | 29 | .proc_handler = &proc_dointvec, |
30 | }, { | ||
31 | .ctl_name = BUS_ISA_PORT_BASE, | ||
32 | .procname = "portbase", | ||
33 | .data = &isa_portbase, | ||
34 | .maxlen = sizeof(isa_portbase), | ||
35 | .mode = 0444, | ||
36 | .proc_handler = &proc_dointvec, | ||
37 | }, { | ||
38 | .ctl_name = BUS_ISA_PORT_SHIFT, | ||
39 | .procname = "portshift", | ||
40 | .data = &isa_portshift, | ||
41 | .maxlen = sizeof(isa_portshift), | ||
42 | .mode = 0444, | ||
43 | .proc_handler = &proc_dointvec, | ||
44 | }, {0} | ||
37 | }; | 45 | }; |
38 | 46 | ||
39 | static struct ctl_table_header *isa_sysctl_header; | 47 | static struct ctl_table_header *isa_sysctl_header; |
40 | 48 | ||
41 | static ctl_table ctl_isa[2] = {{CTL_BUS_ISA, "isa", NULL, 0, 0555, ctl_isa_vars}, | 49 | static ctl_table ctl_isa[2] = { |
42 | {0}}; | 50 | { |
43 | static ctl_table ctl_bus[2] = {{CTL_BUS, "bus", NULL, 0, 0555, ctl_isa}, | 51 | .ctl_name = CTL_BUS_ISA, |
44 | {0}}; | 52 | .procname = "isa", |
53 | .mode = 0555, | ||
54 | .child = ctl_isa_vars, | ||
55 | }, {0} | ||
56 | }; | ||
57 | |||
58 | static ctl_table ctl_bus[2] = { | ||
59 | { | ||
60 | .ctl_name = CTL_BUS, | ||
61 | .procname = "bus", | ||
62 | .mode = 0555, | ||
63 | .child = ctl_isa, | ||
64 | }, {0} | ||
65 | }; | ||
45 | 66 | ||
46 | void __init | 67 | void __init |
47 | register_isa_ports(unsigned int membase, unsigned int portbase, unsigned int portshift) | 68 | register_isa_ports(unsigned int membase, unsigned int portbase, unsigned int portshift) |
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 4e29dd03e582..aeeed806f991 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c | |||
@@ -233,7 +233,7 @@ NORET_TYPE void die(const char *str, struct pt_regs *regs, int err) | |||
233 | spin_unlock_irq(&die_lock); | 233 | spin_unlock_irq(&die_lock); |
234 | 234 | ||
235 | if (panic_on_oops) | 235 | if (panic_on_oops) |
236 | panic("Fatal exception: panic_on_oops"); | 236 | panic("Fatal exception"); |
237 | 237 | ||
238 | do_exit(SIGSEGV); | 238 | do_exit(SIGSEGV); |
239 | } | 239 | } |
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c index 607ed1f5b3f8..823e25d4547e 100644 --- a/arch/arm/mach-footbridge/dc21285.c +++ b/arch/arm/mach-footbridge/dc21285.c | |||
@@ -35,7 +35,6 @@ | |||
35 | 35 | ||
36 | extern int setup_arm_irq(int, struct irqaction *); | 36 | extern int setup_arm_irq(int, struct irqaction *); |
37 | extern void pcibios_report_status(u_int status_mask, int warn); | 37 | extern void pcibios_report_status(u_int status_mask, int warn); |
38 | extern void register_isa_ports(unsigned int, unsigned int, unsigned int); | ||
39 | 38 | ||
40 | static unsigned long | 39 | static unsigned long |
41 | dc21285_base_address(struct pci_bus *bus, unsigned int devfn) | 40 | dc21285_base_address(struct pci_bus *bus, unsigned int devfn) |
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index f9043592e299..4418f6d7572d 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c | |||
@@ -600,4 +600,6 @@ void __init pci_v3_postinit(void) | |||
600 | printk(KERN_ERR "PCI: unable to grab local bus timeout " | 600 | printk(KERN_ERR "PCI: unable to grab local bus timeout " |
601 | "interrupt: %d\n", ret); | 601 | "interrupt: %d\n", ret); |
602 | #endif | 602 | #endif |
603 | |||
604 | register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0); | ||
603 | } | 605 | } |
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c index 2d40fe1145f0..9562177b5fe1 100644 --- a/arch/arm/mach-ixp4xx/common-pci.c +++ b/arch/arm/mach-ixp4xx/common-pci.c | |||
@@ -532,8 +532,6 @@ pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) | |||
532 | return -EIO; | 532 | return -EIO; |
533 | } | 533 | } |
534 | 534 | ||
535 | EXPORT_SYMBOL(pci_set_dma_mask); | ||
536 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); | ||
537 | EXPORT_SYMBOL(ixp4xx_pci_read); | 535 | EXPORT_SYMBOL(ixp4xx_pci_read); |
538 | EXPORT_SYMBOL(ixp4xx_pci_write); | 536 | EXPORT_SYMBOL(ixp4xx_pci_write); |
539 | 537 | ||
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c index 654e2eed81fb..30f1300e0e21 100644 --- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c +++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c | |||
@@ -107,9 +107,9 @@ static struct flash_platform_data gtwx5715_flash_data = { | |||
107 | .width = 2, | 107 | .width = 2, |
108 | }; | 108 | }; |
109 | 109 | ||
110 | static struct gtw5715_flash_resource = { | 110 | static struct resource gtwx5715_flash_resource = { |
111 | .flags = IORESOURCE_MEM, | 111 | .flags = IORESOURCE_MEM, |
112 | } | 112 | }; |
113 | 113 | ||
114 | static struct platform_device gtwx5715_flash = { | 114 | static struct platform_device gtwx5715_flash = { |
115 | .name = "IXP4XX-Flash", | 115 | .name = "IXP4XX-Flash", |
@@ -130,9 +130,6 @@ static void __init gtwx5715_init(void) | |||
130 | { | 130 | { |
131 | ixp4xx_sys_init(); | 131 | ixp4xx_sys_init(); |
132 | 132 | ||
133 | if (!flash_resource) | ||
134 | printk(KERN_ERR "Could not allocate flash resource\n"); | ||
135 | |||
136 | gtwx5715_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); | 133 | gtwx5715_flash_resource.start = IXP4XX_EXP_BUS_BASE(0); |
137 | gtwx5715_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_8M - 1; | 134 | gtwx5715_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_8M - 1; |
138 | 135 | ||
diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c index f9421318cb7a..ff6b4ee037f5 100644 --- a/arch/arm/mach-pxa/corgi_ssp.c +++ b/arch/arm/mach-pxa/corgi_ssp.c | |||
@@ -47,14 +47,15 @@ static struct corgissp_machinfo *ssp_machinfo; | |||
47 | */ | 47 | */ |
48 | unsigned long corgi_ssp_ads7846_putget(ulong data) | 48 | unsigned long corgi_ssp_ads7846_putget(ulong data) |
49 | { | 49 | { |
50 | unsigned long ret,flag; | 50 | unsigned long flag; |
51 | u32 ret = 0; | ||
51 | 52 | ||
52 | spin_lock_irqsave(&corgi_ssp_lock, flag); | 53 | spin_lock_irqsave(&corgi_ssp_lock, flag); |
53 | if (ssp_machinfo->cs_ads7846 >= 0) | 54 | if (ssp_machinfo->cs_ads7846 >= 0) |
54 | GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846); | 55 | GPCR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846); |
55 | 56 | ||
56 | ssp_write_word(&corgi_ssp_dev,data); | 57 | ssp_write_word(&corgi_ssp_dev,data); |
57 | ret = ssp_read_word(&corgi_ssp_dev); | 58 | ssp_read_word(&corgi_ssp_dev, &ret); |
58 | 59 | ||
59 | if (ssp_machinfo->cs_ads7846 >= 0) | 60 | if (ssp_machinfo->cs_ads7846 >= 0) |
60 | GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846); | 61 | GPSR(ssp_machinfo->cs_ads7846) = GPIO_bit(ssp_machinfo->cs_ads7846); |
@@ -88,7 +89,9 @@ void corgi_ssp_ads7846_put(ulong data) | |||
88 | 89 | ||
89 | unsigned long corgi_ssp_ads7846_get(void) | 90 | unsigned long corgi_ssp_ads7846_get(void) |
90 | { | 91 | { |
91 | return ssp_read_word(&corgi_ssp_dev); | 92 | u32 ret = 0; |
93 | ssp_read_word(&corgi_ssp_dev, &ret); | ||
94 | return ret; | ||
92 | } | 95 | } |
93 | 96 | ||
94 | EXPORT_SYMBOL(corgi_ssp_ads7846_putget); | 97 | EXPORT_SYMBOL(corgi_ssp_ads7846_putget); |
@@ -104,6 +107,7 @@ EXPORT_SYMBOL(corgi_ssp_ads7846_get); | |||
104 | unsigned long corgi_ssp_dac_put(ulong data) | 107 | unsigned long corgi_ssp_dac_put(ulong data) |
105 | { | 108 | { |
106 | unsigned long flag, sscr1 = SSCR1_SPH; | 109 | unsigned long flag, sscr1 = SSCR1_SPH; |
110 | u32 tmp; | ||
107 | 111 | ||
108 | spin_lock_irqsave(&corgi_ssp_lock, flag); | 112 | spin_lock_irqsave(&corgi_ssp_lock, flag); |
109 | 113 | ||
@@ -118,7 +122,7 @@ unsigned long corgi_ssp_dac_put(ulong data) | |||
118 | GPCR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon); | 122 | GPCR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon); |
119 | ssp_write_word(&corgi_ssp_dev,data); | 123 | ssp_write_word(&corgi_ssp_dev,data); |
120 | /* Read null data back from device to prevent SSP overflow */ | 124 | /* Read null data back from device to prevent SSP overflow */ |
121 | ssp_read_word(&corgi_ssp_dev); | 125 | ssp_read_word(&corgi_ssp_dev, &tmp); |
122 | if (ssp_machinfo->cs_lcdcon >= 0) | 126 | if (ssp_machinfo->cs_lcdcon >= 0) |
123 | GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon); | 127 | GPSR(ssp_machinfo->cs_lcdcon) = GPIO_bit(ssp_machinfo->cs_lcdcon); |
124 | 128 | ||
@@ -150,7 +154,7 @@ EXPORT_SYMBOL(corgi_ssp_blduty_set); | |||
150 | int corgi_ssp_max1111_get(ulong data) | 154 | int corgi_ssp_max1111_get(ulong data) |
151 | { | 155 | { |
152 | unsigned long flag; | 156 | unsigned long flag; |
153 | int voltage,voltage1,voltage2; | 157 | long voltage = 0, voltage1 = 0, voltage2 = 0; |
154 | 158 | ||
155 | spin_lock_irqsave(&corgi_ssp_lock, flag); | 159 | spin_lock_irqsave(&corgi_ssp_lock, flag); |
156 | if (ssp_machinfo->cs_max1111 >= 0) | 160 | if (ssp_machinfo->cs_max1111 >= 0) |
@@ -163,15 +167,15 @@ int corgi_ssp_max1111_get(ulong data) | |||
163 | 167 | ||
164 | /* TB1/RB1 */ | 168 | /* TB1/RB1 */ |
165 | ssp_write_word(&corgi_ssp_dev,data); | 169 | ssp_write_word(&corgi_ssp_dev,data); |
166 | ssp_read_word(&corgi_ssp_dev); /* null read */ | 170 | ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1); /* null read */ |
167 | 171 | ||
168 | /* TB12/RB2 */ | 172 | /* TB12/RB2 */ |
169 | ssp_write_word(&corgi_ssp_dev,0); | 173 | ssp_write_word(&corgi_ssp_dev,0); |
170 | voltage1=ssp_read_word(&corgi_ssp_dev); | 174 | ssp_read_word(&corgi_ssp_dev, (u32*)&voltage1); |
171 | 175 | ||
172 | /* TB13/RB3*/ | 176 | /* TB13/RB3*/ |
173 | ssp_write_word(&corgi_ssp_dev,0); | 177 | ssp_write_word(&corgi_ssp_dev,0); |
174 | voltage2=ssp_read_word(&corgi_ssp_dev); | 178 | ssp_read_word(&corgi_ssp_dev, (u32*)&voltage2); |
175 | 179 | ||
176 | ssp_disable(&corgi_ssp_dev); | 180 | ssp_disable(&corgi_ssp_dev); |
177 | ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846)); | 181 | ssp_config(&corgi_ssp_dev, (SSCR0_National | (SSCR0_DSS & 0x0b )), 0, 0, SSCR0_SerClkDiv(ssp_machinfo->clk_ads7846)); |
diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c index 93096befd017..1fddfeaa630d 100644 --- a/arch/arm/mach-pxa/ssp.c +++ b/arch/arm/mach-pxa/ssp.c | |||
@@ -40,6 +40,8 @@ | |||
40 | 40 | ||
41 | #define PXA_SSP_PORTS 3 | 41 | #define PXA_SSP_PORTS 3 |
42 | 42 | ||
43 | #define TIMEOUT 100000 | ||
44 | |||
43 | struct ssp_info_ { | 45 | struct ssp_info_ { |
44 | int irq; | 46 | int irq; |
45 | u32 clock; | 47 | u32 clock; |
@@ -92,13 +94,18 @@ static irqreturn_t ssp_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |||
92 | * The caller is expected to perform the necessary locking. | 94 | * The caller is expected to perform the necessary locking. |
93 | * | 95 | * |
94 | * Returns: | 96 | * Returns: |
95 | * %-ETIMEDOUT timeout occurred (for future) | 97 | * %-ETIMEDOUT timeout occurred |
96 | * 0 success | 98 | * 0 success |
97 | */ | 99 | */ |
98 | int ssp_write_word(struct ssp_dev *dev, u32 data) | 100 | int ssp_write_word(struct ssp_dev *dev, u32 data) |
99 | { | 101 | { |
100 | while (!(SSSR_P(dev->port) & SSSR_TNF)) | 102 | int timeout = TIMEOUT; |
103 | |||
104 | while (!(SSSR_P(dev->port) & SSSR_TNF)) { | ||
105 | if (!--timeout) | ||
106 | return -ETIMEDOUT; | ||
101 | cpu_relax(); | 107 | cpu_relax(); |
108 | } | ||
102 | 109 | ||
103 | SSDR_P(dev->port) = data; | 110 | SSDR_P(dev->port) = data; |
104 | 111 | ||
@@ -117,15 +124,21 @@ int ssp_write_word(struct ssp_dev *dev, u32 data) | |||
117 | * The caller is expected to perform the necessary locking. | 124 | * The caller is expected to perform the necessary locking. |
118 | * | 125 | * |
119 | * Returns: | 126 | * Returns: |
120 | * %-ETIMEDOUT timeout occurred (for future) | 127 | * %-ETIMEDOUT timeout occurred |
121 | * 32-bit data success | 128 | * 32-bit data success |
122 | */ | 129 | */ |
123 | int ssp_read_word(struct ssp_dev *dev) | 130 | int ssp_read_word(struct ssp_dev *dev, u32 *data) |
124 | { | 131 | { |
125 | while (!(SSSR_P(dev->port) & SSSR_RNE)) | 132 | int timeout = TIMEOUT; |
133 | |||
134 | while (!(SSSR_P(dev->port) & SSSR_RNE)) { | ||
135 | if (!--timeout) | ||
136 | return -ETIMEDOUT; | ||
126 | cpu_relax(); | 137 | cpu_relax(); |
138 | } | ||
127 | 139 | ||
128 | return SSDR_P(dev->port); | 140 | *data = SSDR_P(dev->port); |
141 | return 0; | ||
129 | } | 142 | } |
130 | 143 | ||
131 | /** | 144 | /** |
@@ -136,13 +149,21 @@ int ssp_read_word(struct ssp_dev *dev) | |||
136 | * | 149 | * |
137 | * The caller is expected to perform the necessary locking. | 150 | * The caller is expected to perform the necessary locking. |
138 | */ | 151 | */ |
139 | void ssp_flush(struct ssp_dev *dev) | 152 | int ssp_flush(struct ssp_dev *dev) |
140 | { | 153 | { |
154 | int timeout = TIMEOUT * 2; | ||
155 | |||
141 | do { | 156 | do { |
142 | while (SSSR_P(dev->port) & SSSR_RNE) { | 157 | while (SSSR_P(dev->port) & SSSR_RNE) { |
158 | if (!--timeout) | ||
159 | return -ETIMEDOUT; | ||
143 | (void) SSDR_P(dev->port); | 160 | (void) SSDR_P(dev->port); |
144 | } | 161 | } |
162 | if (!--timeout) | ||
163 | return -ETIMEDOUT; | ||
145 | } while (SSSR_P(dev->port) & SSSR_BSY); | 164 | } while (SSSR_P(dev->port) & SSSR_BSY); |
165 | |||
166 | return 0; | ||
146 | } | 167 | } |
147 | 168 | ||
148 | /** | 169 | /** |
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index 0c7938645df6..273e05f2b8de 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile | |||
@@ -10,45 +10,47 @@ obj-m := | |||
10 | obj-n := | 10 | obj-n := |
11 | obj- := | 11 | obj- := |
12 | 12 | ||
13 | # DMA | ||
14 | obj-$(CONFIG_S3C2410_DMA) += dma.o | ||
15 | |||
13 | # S3C2400 support files | 16 | # S3C2400 support files |
14 | obj-$(CONFIG_CPU_S3C2400) += s3c2400-gpio.o | 17 | obj-$(CONFIG_CPU_S3C2400) += s3c2400-gpio.o |
15 | 18 | ||
16 | # S3C2410 support files | 19 | # S3C2410 support files |
17 | 20 | ||
18 | obj-$(CONFIG_CPU_S3C2410) += s3c2410.o | 21 | obj-$(CONFIG_CPU_S3C2410) += s3c2410.o |
19 | obj-$(CONFIG_CPU_S3C2410) += s3c2410-gpio.o | 22 | obj-$(CONFIG_CPU_S3C2410) += s3c2410-gpio.o |
20 | obj-$(CONFIG_S3C2410_DMA) += dma.o | ||
21 | 23 | ||
22 | # Power Management support | 24 | # Power Management support |
23 | 25 | ||
24 | obj-$(CONFIG_PM) += pm.o sleep.o | 26 | obj-$(CONFIG_PM) += pm.o sleep.o |
25 | obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o | 27 | obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o |
26 | 28 | ||
27 | # S3C2412 support | 29 | # S3C2412 support |
28 | obj-$(CONFIG_CPU_S3C2412) += s3c2412.o | 30 | obj-$(CONFIG_CPU_S3C2412) += s3c2412.o |
29 | obj-$(CONFIG_CPU_S3C2412) += s3c2412-clock.o | 31 | obj-$(CONFIG_CPU_S3C2412) += s3c2412-clock.o |
30 | 32 | ||
31 | # | 33 | # |
32 | # S3C244X support | 34 | # S3C244X support |
33 | 35 | ||
34 | obj-$(CONFIG_CPU_S3C244X) += s3c244x.o | 36 | obj-$(CONFIG_CPU_S3C244X) += s3c244x.o |
35 | obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o | 37 | obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o |
36 | 38 | ||
37 | # Clock control | 39 | # Clock control |
38 | 40 | ||
39 | obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o | 41 | obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o |
40 | 42 | ||
41 | # S3C2440 support | 43 | # S3C2440 support |
42 | 44 | ||
43 | obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o | 45 | obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o |
44 | obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o | 46 | obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o |
45 | obj-$(CONFIG_CPU_S3C2440) += s3c2440-clock.o | 47 | obj-$(CONFIG_CPU_S3C2440) += s3c2440-clock.o |
46 | obj-$(CONFIG_CPU_S3C2440) += s3c2410-gpio.o | 48 | obj-$(CONFIG_CPU_S3C2440) += s3c2410-gpio.o |
47 | 49 | ||
48 | # S3C2442 support | 50 | # S3C2442 support |
49 | 51 | ||
50 | obj-$(CONFIG_CPU_S3C2442) += s3c2442.o | 52 | obj-$(CONFIG_CPU_S3C2442) += s3c2442.o |
51 | obj-$(CONFIG_CPU_S3C2442) += s3c2442-clock.o | 53 | obj-$(CONFIG_CPU_S3C2442) += s3c2442-clock.o |
52 | 54 | ||
53 | # bast extras | 55 | # bast extras |
54 | 56 | ||
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c index 094cc52745c5..25855452fe8c 100644 --- a/arch/arm/mach-s3c2410/dma.c +++ b/arch/arm/mach-s3c2410/dma.c | |||
@@ -112,7 +112,7 @@ dmadbg_capture(s3c2410_dma_chan_t *chan, struct s3c2410_dma_regstate *regs) | |||
112 | } | 112 | } |
113 | 113 | ||
114 | static void | 114 | static void |
115 | dmadbg_showregs(const char *fname, int line, s3c2410_dma_chan_t *chan, | 115 | dmadbg_dumpregs(const char *fname, int line, s3c2410_dma_chan_t *chan, |
116 | struct s3c2410_dma_regstate *regs) | 116 | struct s3c2410_dma_regstate *regs) |
117 | { | 117 | { |
118 | printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n", | 118 | printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n", |
@@ -132,7 +132,16 @@ dmadbg_showchan(const char *fname, int line, s3c2410_dma_chan_t *chan) | |||
132 | chan->number, fname, line, chan->load_state, | 132 | chan->number, fname, line, chan->load_state, |
133 | chan->curr, chan->next, chan->end); | 133 | chan->curr, chan->next, chan->end); |
134 | 134 | ||
135 | dmadbg_showregs(fname, line, chan, &state); | 135 | dmadbg_dumpregs(fname, line, chan, &state); |
136 | } | ||
137 | |||
138 | static void | ||
139 | dmadbg_showregs(const char *fname, int line, s3c2410_dma_chan_t *chan) | ||
140 | { | ||
141 | struct s3c2410_dma_regstate state; | ||
142 | |||
143 | dmadbg_capture(chan, &state); | ||
144 | dmadbg_dumpregs(fname, line, chan, &state); | ||
136 | } | 145 | } |
137 | 146 | ||
138 | #define dbg_showregs(chan) dmadbg_showregs(__FUNCTION__, __LINE__, (chan)) | 147 | #define dbg_showregs(chan) dmadbg_showregs(__FUNCTION__, __LINE__, (chan)) |
@@ -253,10 +262,14 @@ s3c2410_dma_loadbuffer(s3c2410_dma_chan_t *chan, | |||
253 | buf->next); | 262 | buf->next); |
254 | reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0; | 263 | reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0; |
255 | } else { | 264 | } else { |
256 | pr_debug("load_state is %d => autoreload\n", chan->load_state); | 265 | //pr_debug("load_state is %d => autoreload\n", chan->load_state); |
257 | reload = S3C2410_DCON_AUTORELOAD; | 266 | reload = S3C2410_DCON_AUTORELOAD; |
258 | } | 267 | } |
259 | 268 | ||
269 | if ((buf->data & 0xf0000000) != 0x30000000) { | ||
270 | dmawarn("dmaload: buffer is %p\n", (void *)buf->data); | ||
271 | } | ||
272 | |||
260 | writel(buf->data, chan->addr_reg); | 273 | writel(buf->data, chan->addr_reg); |
261 | 274 | ||
262 | dma_wrreg(chan, S3C2410_DMA_DCON, | 275 | dma_wrreg(chan, S3C2410_DMA_DCON, |
@@ -370,7 +383,7 @@ static int s3c2410_dma_start(s3c2410_dma_chan_t *chan) | |||
370 | tmp |= S3C2410_DMASKTRIG_ON; | 383 | tmp |= S3C2410_DMASKTRIG_ON; |
371 | dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); | 384 | dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); |
372 | 385 | ||
373 | pr_debug("wrote %08lx to DMASKTRIG\n", tmp); | 386 | pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp); |
374 | 387 | ||
375 | #if 0 | 388 | #if 0 |
376 | /* the dma buffer loads should take care of clearing the AUTO | 389 | /* the dma buffer loads should take care of clearing the AUTO |
@@ -384,7 +397,30 @@ static int s3c2410_dma_start(s3c2410_dma_chan_t *chan) | |||
384 | 397 | ||
385 | dbg_showchan(chan); | 398 | dbg_showchan(chan); |
386 | 399 | ||
400 | /* if we've only loaded one buffer onto the channel, then chec | ||
401 | * to see if we have another, and if so, try and load it so when | ||
402 | * the first buffer is finished, the new one will be loaded onto | ||
403 | * the channel */ | ||
404 | |||
405 | if (chan->next != NULL) { | ||
406 | if (chan->load_state == S3C2410_DMALOAD_1LOADED) { | ||
407 | |||
408 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | ||
409 | pr_debug("%s: buff not yet loaded, no more todo\n", | ||
410 | __FUNCTION__); | ||
411 | } else { | ||
412 | chan->load_state = S3C2410_DMALOAD_1RUNNING; | ||
413 | s3c2410_dma_loadbuffer(chan, chan->next); | ||
414 | } | ||
415 | |||
416 | } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) { | ||
417 | s3c2410_dma_loadbuffer(chan, chan->next); | ||
418 | } | ||
419 | } | ||
420 | |||
421 | |||
387 | local_irq_restore(flags); | 422 | local_irq_restore(flags); |
423 | |||
388 | return 0; | 424 | return 0; |
389 | } | 425 | } |
390 | 426 | ||
@@ -436,12 +472,11 @@ int s3c2410_dma_enqueue(unsigned int channel, void *id, | |||
436 | buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC); | 472 | buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC); |
437 | if (buf == NULL) { | 473 | if (buf == NULL) { |
438 | pr_debug("%s: out of memory (%ld alloc)\n", | 474 | pr_debug("%s: out of memory (%ld alloc)\n", |
439 | __FUNCTION__, sizeof(*buf)); | 475 | __FUNCTION__, (long)sizeof(*buf)); |
440 | return -ENOMEM; | 476 | return -ENOMEM; |
441 | } | 477 | } |
442 | 478 | ||
443 | pr_debug("%s: new buffer %p\n", __FUNCTION__, buf); | 479 | //pr_debug("%s: new buffer %p\n", __FUNCTION__, buf); |
444 | |||
445 | //dbg_showchan(chan); | 480 | //dbg_showchan(chan); |
446 | 481 | ||
447 | buf->next = NULL; | 482 | buf->next = NULL; |
@@ -537,14 +572,20 @@ s3c2410_dma_lastxfer(s3c2410_dma_chan_t *chan) | |||
537 | case S3C2410_DMALOAD_1LOADED: | 572 | case S3C2410_DMALOAD_1LOADED: |
538 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | 573 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { |
539 | /* flag error? */ | 574 | /* flag error? */ |
540 | printk(KERN_ERR "dma%d: timeout waiting for load\n", | 575 | printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n", |
541 | chan->number); | 576 | chan->number, __FUNCTION__); |
542 | return; | 577 | return; |
543 | } | 578 | } |
544 | break; | 579 | break; |
545 | 580 | ||
581 | case S3C2410_DMALOAD_1LOADED_1RUNNING: | ||
582 | /* I belive in this case we do not have anything to do | ||
583 | * until the next buffer comes along, and we turn off the | ||
584 | * reload */ | ||
585 | return; | ||
586 | |||
546 | default: | 587 | default: |
547 | pr_debug("dma%d: lastxfer: unhandled load_state %d with no next", | 588 | pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n", |
548 | chan->number, chan->load_state); | 589 | chan->number, chan->load_state); |
549 | return; | 590 | return; |
550 | 591 | ||
@@ -629,7 +670,14 @@ s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs) | |||
629 | } else { | 670 | } else { |
630 | } | 671 | } |
631 | 672 | ||
632 | if (chan->next != NULL) { | 673 | /* only reload if the channel is still running... our buffer done |
674 | * routine may have altered the state by requesting the dma channel | ||
675 | * to stop or shutdown... */ | ||
676 | |||
677 | /* todo: check that when the channel is shut-down from inside this | ||
678 | * function, we cope with unsetting reload, etc */ | ||
679 | |||
680 | if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) { | ||
633 | unsigned long flags; | 681 | unsigned long flags; |
634 | 682 | ||
635 | switch (chan->load_state) { | 683 | switch (chan->load_state) { |
@@ -644,8 +692,8 @@ s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs) | |||
644 | case S3C2410_DMALOAD_1LOADED: | 692 | case S3C2410_DMALOAD_1LOADED: |
645 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | 693 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { |
646 | /* flag error? */ | 694 | /* flag error? */ |
647 | printk(KERN_ERR "dma%d: timeout waiting for load\n", | 695 | printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n", |
648 | chan->number); | 696 | chan->number, __FUNCTION__); |
649 | return IRQ_HANDLED; | 697 | return IRQ_HANDLED; |
650 | } | 698 | } |
651 | 699 | ||
@@ -678,8 +726,6 @@ s3c2410_dma_irq(int irq, void *devpw, struct pt_regs *regs) | |||
678 | return IRQ_HANDLED; | 726 | return IRQ_HANDLED; |
679 | } | 727 | } |
680 | 728 | ||
681 | |||
682 | |||
683 | /* s3c2410_request_dma | 729 | /* s3c2410_request_dma |
684 | * | 730 | * |
685 | * get control of an dma channel | 731 | * get control of an dma channel |
@@ -718,11 +764,17 @@ int s3c2410_dma_request(unsigned int channel, s3c2410_dma_client_t *client, | |||
718 | pr_debug("dma%d: %s : requesting irq %d\n", | 764 | pr_debug("dma%d: %s : requesting irq %d\n", |
719 | channel, __FUNCTION__, chan->irq); | 765 | channel, __FUNCTION__, chan->irq); |
720 | 766 | ||
767 | chan->irq_claimed = 1; | ||
768 | local_irq_restore(flags); | ||
769 | |||
721 | err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED, | 770 | err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED, |
722 | client->name, (void *)chan); | 771 | client->name, (void *)chan); |
723 | 772 | ||
773 | local_irq_save(flags); | ||
774 | |||
724 | if (err) { | 775 | if (err) { |
725 | chan->in_use = 0; | 776 | chan->in_use = 0; |
777 | chan->irq_claimed = 0; | ||
726 | local_irq_restore(flags); | 778 | local_irq_restore(flags); |
727 | 779 | ||
728 | printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n", | 780 | printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n", |
@@ -730,7 +782,6 @@ int s3c2410_dma_request(unsigned int channel, s3c2410_dma_client_t *client, | |||
730 | return err; | 782 | return err; |
731 | } | 783 | } |
732 | 784 | ||
733 | chan->irq_claimed = 1; | ||
734 | chan->irq_enabled = 1; | 785 | chan->irq_enabled = 1; |
735 | } | 786 | } |
736 | 787 | ||
@@ -810,6 +861,7 @@ static int s3c2410_dma_dostop(s3c2410_dma_chan_t *chan) | |||
810 | 861 | ||
811 | tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); | 862 | tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); |
812 | tmp |= S3C2410_DMASKTRIG_STOP; | 863 | tmp |= S3C2410_DMASKTRIG_STOP; |
864 | //tmp &= ~S3C2410_DMASKTRIG_ON; | ||
813 | dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); | 865 | dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); |
814 | 866 | ||
815 | #if 0 | 867 | #if 0 |
@@ -819,6 +871,7 @@ static int s3c2410_dma_dostop(s3c2410_dma_chan_t *chan) | |||
819 | dma_wrreg(chan, S3C2410_DMA_DCON, tmp); | 871 | dma_wrreg(chan, S3C2410_DMA_DCON, tmp); |
820 | #endif | 872 | #endif |
821 | 873 | ||
874 | /* should stop do this, or should we wait for flush? */ | ||
822 | chan->state = S3C2410_DMA_IDLE; | 875 | chan->state = S3C2410_DMA_IDLE; |
823 | chan->load_state = S3C2410_DMALOAD_NONE; | 876 | chan->load_state = S3C2410_DMALOAD_NONE; |
824 | 877 | ||
@@ -827,6 +880,22 @@ static int s3c2410_dma_dostop(s3c2410_dma_chan_t *chan) | |||
827 | return 0; | 880 | return 0; |
828 | } | 881 | } |
829 | 882 | ||
883 | void s3c2410_dma_waitforstop(s3c2410_dma_chan_t *chan) | ||
884 | { | ||
885 | unsigned long tmp; | ||
886 | unsigned int timeout = 0x10000; | ||
887 | |||
888 | while (timeout-- > 0) { | ||
889 | tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); | ||
890 | |||
891 | if (!(tmp & S3C2410_DMASKTRIG_ON)) | ||
892 | return; | ||
893 | } | ||
894 | |||
895 | pr_debug("dma%d: failed to stop?\n", chan->number); | ||
896 | } | ||
897 | |||
898 | |||
830 | /* s3c2410_dma_flush | 899 | /* s3c2410_dma_flush |
831 | * | 900 | * |
832 | * stop the channel, and remove all current and pending transfers | 901 | * stop the channel, and remove all current and pending transfers |
@@ -837,7 +906,9 @@ static int s3c2410_dma_flush(s3c2410_dma_chan_t *chan) | |||
837 | s3c2410_dma_buf_t *buf, *next; | 906 | s3c2410_dma_buf_t *buf, *next; |
838 | unsigned long flags; | 907 | unsigned long flags; |
839 | 908 | ||
840 | pr_debug("%s:\n", __FUNCTION__); | 909 | pr_debug("%s: chan %p (%d)\n", __FUNCTION__, chan, chan->number); |
910 | |||
911 | dbg_showchan(chan); | ||
841 | 912 | ||
842 | local_irq_save(flags); | 913 | local_irq_save(flags); |
843 | 914 | ||
@@ -864,11 +935,64 @@ static int s3c2410_dma_flush(s3c2410_dma_chan_t *chan) | |||
864 | } | 935 | } |
865 | } | 936 | } |
866 | 937 | ||
938 | dbg_showregs(chan); | ||
939 | |||
940 | s3c2410_dma_waitforstop(chan); | ||
941 | |||
942 | #if 0 | ||
943 | /* should also clear interrupts, according to WinCE BSP */ | ||
944 | { | ||
945 | unsigned long tmp; | ||
946 | |||
947 | tmp = dma_rdreg(chan, S3C2410_DMA_DCON); | ||
948 | tmp |= S3C2410_DCON_NORELOAD; | ||
949 | dma_wrreg(chan, S3C2410_DMA_DCON, tmp); | ||
950 | } | ||
951 | #endif | ||
952 | |||
953 | dbg_showregs(chan); | ||
954 | |||
867 | local_irq_restore(flags); | 955 | local_irq_restore(flags); |
868 | 956 | ||
869 | return 0; | 957 | return 0; |
870 | } | 958 | } |
871 | 959 | ||
960 | int | ||
961 | s3c2410_dma_started(s3c2410_dma_chan_t *chan) | ||
962 | { | ||
963 | unsigned long flags; | ||
964 | |||
965 | local_irq_save(flags); | ||
966 | |||
967 | dbg_showchan(chan); | ||
968 | |||
969 | /* if we've only loaded one buffer onto the channel, then chec | ||
970 | * to see if we have another, and if so, try and load it so when | ||
971 | * the first buffer is finished, the new one will be loaded onto | ||
972 | * the channel */ | ||
973 | |||
974 | if (chan->next != NULL) { | ||
975 | if (chan->load_state == S3C2410_DMALOAD_1LOADED) { | ||
976 | |||
977 | if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { | ||
978 | pr_debug("%s: buff not yet loaded, no more todo\n", | ||
979 | __FUNCTION__); | ||
980 | } else { | ||
981 | chan->load_state = S3C2410_DMALOAD_1RUNNING; | ||
982 | s3c2410_dma_loadbuffer(chan, chan->next); | ||
983 | } | ||
984 | |||
985 | } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) { | ||
986 | s3c2410_dma_loadbuffer(chan, chan->next); | ||
987 | } | ||
988 | } | ||
989 | |||
990 | |||
991 | local_irq_restore(flags); | ||
992 | |||
993 | return 0; | ||
994 | |||
995 | } | ||
872 | 996 | ||
873 | int | 997 | int |
874 | s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op) | 998 | s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op) |
@@ -885,14 +1009,15 @@ s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op) | |||
885 | return s3c2410_dma_dostop(chan); | 1009 | return s3c2410_dma_dostop(chan); |
886 | 1010 | ||
887 | case S3C2410_DMAOP_PAUSE: | 1011 | case S3C2410_DMAOP_PAUSE: |
888 | return -ENOENT; | ||
889 | |||
890 | case S3C2410_DMAOP_RESUME: | 1012 | case S3C2410_DMAOP_RESUME: |
891 | return -ENOENT; | 1013 | return -ENOENT; |
892 | 1014 | ||
893 | case S3C2410_DMAOP_FLUSH: | 1015 | case S3C2410_DMAOP_FLUSH: |
894 | return s3c2410_dma_flush(chan); | 1016 | return s3c2410_dma_flush(chan); |
895 | 1017 | ||
1018 | case S3C2410_DMAOP_STARTED: | ||
1019 | return s3c2410_dma_started(chan); | ||
1020 | |||
896 | case S3C2410_DMAOP_TIMEOUT: | 1021 | case S3C2410_DMAOP_TIMEOUT: |
897 | return 0; | 1022 | return 0; |
898 | 1023 | ||
diff --git a/arch/arm/mach-sa1100/ssp.c b/arch/arm/mach-sa1100/ssp.c index 1604dadf27fc..5eba5fbbb561 100644 --- a/arch/arm/mach-sa1100/ssp.c +++ b/arch/arm/mach-sa1100/ssp.c | |||
@@ -23,6 +23,8 @@ | |||
23 | #include <asm/hardware.h> | 23 | #include <asm/hardware.h> |
24 | #include <asm/hardware/ssp.h> | 24 | #include <asm/hardware/ssp.h> |
25 | 25 | ||
26 | #define TIMEOUT 100000 | ||
27 | |||
26 | static irqreturn_t ssp_interrupt(int irq, void *dev_id, struct pt_regs *regs) | 28 | static irqreturn_t ssp_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
27 | { | 29 | { |
28 | unsigned int status = Ser4SSSR; | 30 | unsigned int status = Ser4SSSR; |
@@ -47,18 +49,27 @@ static irqreturn_t ssp_interrupt(int irq, void *dev_id, struct pt_regs *regs) | |||
47 | * The caller is expected to perform the necessary locking. | 49 | * The caller is expected to perform the necessary locking. |
48 | * | 50 | * |
49 | * Returns: | 51 | * Returns: |
50 | * %-ETIMEDOUT timeout occurred (for future) | 52 | * %-ETIMEDOUT timeout occurred |
51 | * 0 success | 53 | * 0 success |
52 | */ | 54 | */ |
53 | int ssp_write_word(u16 data) | 55 | int ssp_write_word(u16 data) |
54 | { | 56 | { |
55 | while (!(Ser4SSSR & SSSR_TNF)) | 57 | int timeout = TIMEOUT; |
58 | |||
59 | while (!(Ser4SSSR & SSSR_TNF)) { | ||
60 | if (!--timeout) | ||
61 | return -ETIMEDOUT; | ||
56 | cpu_relax(); | 62 | cpu_relax(); |
63 | } | ||
57 | 64 | ||
58 | Ser4SSDR = data; | 65 | Ser4SSDR = data; |
59 | 66 | ||
60 | while (!(Ser4SSSR & SSSR_BSY)) | 67 | timeout = TIMEOUT; |
68 | while (!(Ser4SSSR & SSSR_BSY)) { | ||
69 | if (!--timeout) | ||
70 | return -ETIMEDOUT; | ||
61 | cpu_relax(); | 71 | cpu_relax(); |
72 | } | ||
62 | 73 | ||
63 | return 0; | 74 | return 0; |
64 | } | 75 | } |
@@ -75,15 +86,22 @@ int ssp_write_word(u16 data) | |||
75 | * The caller is expected to perform the necessary locking. | 86 | * The caller is expected to perform the necessary locking. |
76 | * | 87 | * |
77 | * Returns: | 88 | * Returns: |
78 | * %-ETIMEDOUT timeout occurred (for future) | 89 | * %-ETIMEDOUT timeout occurred |
79 | * 16-bit data success | 90 | * 16-bit data success |
80 | */ | 91 | */ |
81 | int ssp_read_word(void) | 92 | int ssp_read_word(u16 *data) |
82 | { | 93 | { |
83 | while (!(Ser4SSSR & SSSR_RNE)) | 94 | int timeout = TIMEOUT; |
95 | |||
96 | while (!(Ser4SSSR & SSSR_RNE)) { | ||
97 | if (!--timeout) | ||
98 | return -ETIMEDOUT; | ||
84 | cpu_relax(); | 99 | cpu_relax(); |
100 | } | ||
101 | |||
102 | *data = (u16)Ser4SSDR; | ||
85 | 103 | ||
86 | return Ser4SSDR; | 104 | return 0; |
87 | } | 105 | } |
88 | 106 | ||
89 | /** | 107 | /** |
@@ -93,14 +111,26 @@ int ssp_read_word(void) | |||
93 | * is empty. | 111 | * is empty. |
94 | * | 112 | * |
95 | * The caller is expected to perform the necessary locking. | 113 | * The caller is expected to perform the necessary locking. |
114 | * | ||
115 | * Returns: | ||
116 | * %-ETIMEDOUT timeout occurred | ||
117 | * 0 success | ||
96 | */ | 118 | */ |
97 | void ssp_flush(void) | 119 | int ssp_flush(void) |
98 | { | 120 | { |
121 | int timeout = TIMEOUT * 2; | ||
122 | |||
99 | do { | 123 | do { |
100 | while (Ser4SSSR & SSSR_RNE) { | 124 | while (Ser4SSSR & SSSR_RNE) { |
125 | if (!--timeout) | ||
126 | return -ETIMEDOUT; | ||
101 | (void) Ser4SSDR; | 127 | (void) Ser4SSDR; |
102 | } | 128 | } |
129 | if (!--timeout) | ||
130 | return -ETIMEDOUT; | ||
103 | } while (Ser4SSSR & SSSR_BSY); | 131 | } while (Ser4SSSR & SSSR_BSY); |
132 | |||
133 | return 0; | ||
104 | } | 134 | } |
105 | 135 | ||
106 | /** | 136 | /** |
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index c4e3f8c68479..f2bbef07b1e4 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c | |||
@@ -285,7 +285,7 @@ static struct flash_platform_data versatile_flash_data = { | |||
285 | 285 | ||
286 | static struct resource versatile_flash_resource = { | 286 | static struct resource versatile_flash_resource = { |
287 | .start = VERSATILE_FLASH_BASE, | 287 | .start = VERSATILE_FLASH_BASE, |
288 | .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE, | 288 | .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1, |
289 | .flags = IORESOURCE_MEM, | 289 | .flags = IORESOURCE_MEM, |
290 | }; | 290 | }; |
291 | 291 | ||
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index 5f80f184cd32..b4f220dd5eb8 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig | |||
@@ -46,7 +46,7 @@ config CPU_ARM710 | |||
46 | config CPU_ARM720T | 46 | config CPU_ARM720T |
47 | bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR | 47 | bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR |
48 | default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X | 48 | default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X |
49 | select CPU_32v4 | 49 | select CPU_32v4T |
50 | select CPU_ABRT_LV4T | 50 | select CPU_ABRT_LV4T |
51 | select CPU_CACHE_V4 | 51 | select CPU_CACHE_V4 |
52 | select CPU_CACHE_VIVT | 52 | select CPU_CACHE_VIVT |
@@ -64,7 +64,7 @@ config CPU_ARM920T | |||
64 | bool "Support ARM920T processor" | 64 | bool "Support ARM920T processor" |
65 | depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200 | 65 | depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200 |
66 | default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200 | 66 | default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200 |
67 | select CPU_32v4 | 67 | select CPU_32v4T |
68 | select CPU_ABRT_EV4T | 68 | select CPU_ABRT_EV4T |
69 | select CPU_CACHE_V4WT | 69 | select CPU_CACHE_V4WT |
70 | select CPU_CACHE_VIVT | 70 | select CPU_CACHE_VIVT |
@@ -85,7 +85,7 @@ config CPU_ARM922T | |||
85 | bool "Support ARM922T processor" if ARCH_INTEGRATOR | 85 | bool "Support ARM922T processor" if ARCH_INTEGRATOR |
86 | depends on ARCH_LH7A40X || ARCH_INTEGRATOR | 86 | depends on ARCH_LH7A40X || ARCH_INTEGRATOR |
87 | default y if ARCH_LH7A40X | 87 | default y if ARCH_LH7A40X |
88 | select CPU_32v4 | 88 | select CPU_32v4T |
89 | select CPU_ABRT_EV4T | 89 | select CPU_ABRT_EV4T |
90 | select CPU_CACHE_V4WT | 90 | select CPU_CACHE_V4WT |
91 | select CPU_CACHE_VIVT | 91 | select CPU_CACHE_VIVT |
@@ -104,7 +104,7 @@ config CPU_ARM925T | |||
104 | bool "Support ARM925T processor" if ARCH_OMAP1 | 104 | bool "Support ARM925T processor" if ARCH_OMAP1 |
105 | depends on ARCH_OMAP15XX | 105 | depends on ARCH_OMAP15XX |
106 | default y if ARCH_OMAP15XX | 106 | default y if ARCH_OMAP15XX |
107 | select CPU_32v4 | 107 | select CPU_32v4T |
108 | select CPU_ABRT_EV4T | 108 | select CPU_ABRT_EV4T |
109 | select CPU_CACHE_V4WT | 109 | select CPU_CACHE_V4WT |
110 | select CPU_CACHE_VIVT | 110 | select CPU_CACHE_VIVT |
@@ -285,6 +285,11 @@ config CPU_32v4 | |||
285 | select TLS_REG_EMUL if SMP || !MMU | 285 | select TLS_REG_EMUL if SMP || !MMU |
286 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP | 286 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
287 | 287 | ||
288 | config CPU_32v4T | ||
289 | bool | ||
290 | select TLS_REG_EMUL if SMP || !MMU | ||
291 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP | ||
292 | |||
288 | config CPU_32v5 | 293 | config CPU_32v5 |
289 | bool | 294 | bool |
290 | select TLS_REG_EMUL if SMP || !MMU | 295 | select TLS_REG_EMUL if SMP || !MMU |
diff --git a/arch/arm/vfp/vfp.h b/arch/arm/vfp/vfp.h index 4b97950984e9..5fbdf81a8aaf 100644 --- a/arch/arm/vfp/vfp.h +++ b/arch/arm/vfp/vfp.h | |||
@@ -353,3 +353,11 @@ u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand); | |||
353 | * A special flag to tell the normalisation code not to normalise. | 353 | * A special flag to tell the normalisation code not to normalise. |
354 | */ | 354 | */ |
355 | #define VFP_NAN_FLAG 0x100 | 355 | #define VFP_NAN_FLAG 0x100 |
356 | |||
357 | /* | ||
358 | * A bit pattern used to indicate the initial (unset) value of the | ||
359 | * exception mask, in case nothing handles an instruction. This | ||
360 | * doesn't include the NAN flag, which get masked out before | ||
361 | * we check for an error. | ||
362 | */ | ||
363 | #define VFP_EXCEPTION_ERROR ((u32)-1 & ~VFP_NAN_FLAG) | ||
diff --git a/arch/arm/vfp/vfpdouble.c b/arch/arm/vfp/vfpdouble.c index 009038c8113e..04bd3425b29b 100644 --- a/arch/arm/vfp/vfpdouble.c +++ b/arch/arm/vfp/vfpdouble.c | |||
@@ -465,7 +465,7 @@ static u32 vfp_double_fcvts(int sd, int unused, int dm, u32 fpscr) | |||
465 | */ | 465 | */ |
466 | if (tm & (VFP_INFINITY|VFP_NAN)) { | 466 | if (tm & (VFP_INFINITY|VFP_NAN)) { |
467 | vsd.exponent = 255; | 467 | vsd.exponent = 255; |
468 | if (tm & VFP_NAN) | 468 | if (tm == VFP_QNAN) |
469 | vsd.significand |= VFP_SINGLE_SIGNIFICAND_QNAN; | 469 | vsd.significand |= VFP_SINGLE_SIGNIFICAND_QNAN; |
470 | goto pack_nan; | 470 | goto pack_nan; |
471 | } else if (tm & VFP_ZERO) | 471 | } else if (tm & VFP_ZERO) |
@@ -1127,7 +1127,7 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr) | |||
1127 | { | 1127 | { |
1128 | u32 op = inst & FOP_MASK; | 1128 | u32 op = inst & FOP_MASK; |
1129 | u32 exceptions = 0; | 1129 | u32 exceptions = 0; |
1130 | unsigned int dd = vfp_get_dd(inst); | 1130 | unsigned int dest; |
1131 | unsigned int dn = vfp_get_dn(inst); | 1131 | unsigned int dn = vfp_get_dn(inst); |
1132 | unsigned int dm = vfp_get_dm(inst); | 1132 | unsigned int dm = vfp_get_dm(inst); |
1133 | unsigned int vecitr, veclen, vecstride; | 1133 | unsigned int vecitr, veclen, vecstride; |
@@ -1137,10 +1137,20 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr) | |||
1137 | vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)) * 2; | 1137 | vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)) * 2; |
1138 | 1138 | ||
1139 | /* | 1139 | /* |
1140 | * fcvtds takes an sN register number as destination, not dN. | ||
1141 | * It also always operates on scalars. | ||
1142 | */ | ||
1143 | if ((inst & FEXT_MASK) == FEXT_FCVT) { | ||
1144 | veclen = 0; | ||
1145 | dest = vfp_get_sd(inst); | ||
1146 | } else | ||
1147 | dest = vfp_get_dd(inst); | ||
1148 | |||
1149 | /* | ||
1140 | * If destination bank is zero, vector length is always '1'. | 1150 | * If destination bank is zero, vector length is always '1'. |
1141 | * ARM DDI0100F C5.1.3, C5.3.2. | 1151 | * ARM DDI0100F C5.1.3, C5.3.2. |
1142 | */ | 1152 | */ |
1143 | if (FREG_BANK(dd) == 0) | 1153 | if (FREG_BANK(dest) == 0) |
1144 | veclen = 0; | 1154 | veclen = 0; |
1145 | 1155 | ||
1146 | pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride, | 1156 | pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride, |
@@ -1153,16 +1163,20 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr) | |||
1153 | for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) { | 1163 | for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) { |
1154 | u32 except; | 1164 | u32 except; |
1155 | 1165 | ||
1156 | if (op == FOP_EXT) | 1166 | if (op == FOP_EXT && (inst & FEXT_MASK) == FEXT_FCVT) |
1167 | pr_debug("VFP: itr%d (s%u) = op[%u] (d%u)\n", | ||
1168 | vecitr >> FPSCR_LENGTH_BIT, | ||
1169 | dest, dn, dm); | ||
1170 | else if (op == FOP_EXT) | ||
1157 | pr_debug("VFP: itr%d (d%u) = op[%u] (d%u)\n", | 1171 | pr_debug("VFP: itr%d (d%u) = op[%u] (d%u)\n", |
1158 | vecitr >> FPSCR_LENGTH_BIT, | 1172 | vecitr >> FPSCR_LENGTH_BIT, |
1159 | dd, dn, dm); | 1173 | dest, dn, dm); |
1160 | else | 1174 | else |
1161 | pr_debug("VFP: itr%d (d%u) = (d%u) op[%u] (d%u)\n", | 1175 | pr_debug("VFP: itr%d (d%u) = (d%u) op[%u] (d%u)\n", |
1162 | vecitr >> FPSCR_LENGTH_BIT, | 1176 | vecitr >> FPSCR_LENGTH_BIT, |
1163 | dd, dn, FOP_TO_IDX(op), dm); | 1177 | dest, dn, FOP_TO_IDX(op), dm); |
1164 | 1178 | ||
1165 | except = fop(dd, dn, dm, fpscr); | 1179 | except = fop(dest, dn, dm, fpscr); |
1166 | pr_debug("VFP: itr%d: exceptions=%08x\n", | 1180 | pr_debug("VFP: itr%d: exceptions=%08x\n", |
1167 | vecitr >> FPSCR_LENGTH_BIT, except); | 1181 | vecitr >> FPSCR_LENGTH_BIT, except); |
1168 | 1182 | ||
@@ -1180,7 +1194,7 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr) | |||
1180 | * we encounter an exception. We continue. | 1194 | * we encounter an exception. We continue. |
1181 | */ | 1195 | */ |
1182 | 1196 | ||
1183 | dd = FREG_BANK(dd) + ((FREG_IDX(dd) + vecstride) & 6); | 1197 | dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 6); |
1184 | dn = FREG_BANK(dn) + ((FREG_IDX(dn) + vecstride) & 6); | 1198 | dn = FREG_BANK(dn) + ((FREG_IDX(dn) + vecstride) & 6); |
1185 | if (FREG_BANK(dm) != 0) | 1199 | if (FREG_BANK(dm) != 0) |
1186 | dm = FREG_BANK(dm) + ((FREG_IDX(dm) + vecstride) & 6); | 1200 | dm = FREG_BANK(dm) + ((FREG_IDX(dm) + vecstride) & 6); |
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 9d265d5e748c..4178f6cc3d37 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c | |||
@@ -131,7 +131,7 @@ static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_ | |||
131 | 131 | ||
132 | pr_debug("VFP: raising exceptions %08x\n", exceptions); | 132 | pr_debug("VFP: raising exceptions %08x\n", exceptions); |
133 | 133 | ||
134 | if (exceptions == (u32)-1) { | 134 | if (exceptions == VFP_EXCEPTION_ERROR) { |
135 | vfp_panic("unhandled bounce"); | 135 | vfp_panic("unhandled bounce"); |
136 | vfp_raise_sigfpe(0, regs); | 136 | vfp_raise_sigfpe(0, regs); |
137 | return; | 137 | return; |
@@ -170,7 +170,7 @@ static void vfp_raise_exceptions(u32 exceptions, u32 inst, u32 fpscr, struct pt_ | |||
170 | */ | 170 | */ |
171 | static u32 vfp_emulate_instruction(u32 inst, u32 fpscr, struct pt_regs *regs) | 171 | static u32 vfp_emulate_instruction(u32 inst, u32 fpscr, struct pt_regs *regs) |
172 | { | 172 | { |
173 | u32 exceptions = (u32)-1; | 173 | u32 exceptions = VFP_EXCEPTION_ERROR; |
174 | 174 | ||
175 | pr_debug("VFP: emulate: INST=0x%08x SCR=0x%08x\n", inst, fpscr); | 175 | pr_debug("VFP: emulate: INST=0x%08x SCR=0x%08x\n", inst, fpscr); |
176 | 176 | ||
diff --git a/arch/arm/vfp/vfpsingle.c b/arch/arm/vfp/vfpsingle.c index dae2c2f46052..78d7cac5f36b 100644 --- a/arch/arm/vfp/vfpsingle.c +++ b/arch/arm/vfp/vfpsingle.c | |||
@@ -506,7 +506,7 @@ static u32 vfp_single_fcvtd(int dd, int unused, s32 m, u32 fpscr) | |||
506 | */ | 506 | */ |
507 | if (tm & (VFP_INFINITY|VFP_NAN)) { | 507 | if (tm & (VFP_INFINITY|VFP_NAN)) { |
508 | vdd.exponent = 2047; | 508 | vdd.exponent = 2047; |
509 | if (tm & VFP_NAN) | 509 | if (tm == VFP_QNAN) |
510 | vdd.significand |= VFP_DOUBLE_SIGNIFICAND_QNAN; | 510 | vdd.significand |= VFP_DOUBLE_SIGNIFICAND_QNAN; |
511 | goto pack_nan; | 511 | goto pack_nan; |
512 | } else if (tm & VFP_ZERO) | 512 | } else if (tm & VFP_ZERO) |
@@ -514,10 +514,6 @@ static u32 vfp_single_fcvtd(int dd, int unused, s32 m, u32 fpscr) | |||
514 | else | 514 | else |
515 | vdd.exponent = vsm.exponent + (1023 - 127); | 515 | vdd.exponent = vsm.exponent + (1023 - 127); |
516 | 516 | ||
517 | /* | ||
518 | * Technically, if bit 0 of dd is set, this is an invalid | ||
519 | * instruction. However, we ignore this for efficiency. | ||
520 | */ | ||
521 | return vfp_double_normaliseround(dd, &vdd, fpscr, exceptions, "fcvtd"); | 517 | return vfp_double_normaliseround(dd, &vdd, fpscr, exceptions, "fcvtd"); |
522 | 518 | ||
523 | pack_nan: | 519 | pack_nan: |
@@ -1174,7 +1170,7 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr) | |||
1174 | { | 1170 | { |
1175 | u32 op = inst & FOP_MASK; | 1171 | u32 op = inst & FOP_MASK; |
1176 | u32 exceptions = 0; | 1172 | u32 exceptions = 0; |
1177 | unsigned int sd = vfp_get_sd(inst); | 1173 | unsigned int dest; |
1178 | unsigned int sn = vfp_get_sn(inst); | 1174 | unsigned int sn = vfp_get_sn(inst); |
1179 | unsigned int sm = vfp_get_sm(inst); | 1175 | unsigned int sm = vfp_get_sm(inst); |
1180 | unsigned int vecitr, veclen, vecstride; | 1176 | unsigned int vecitr, veclen, vecstride; |
@@ -1184,10 +1180,22 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr) | |||
1184 | vecstride = 1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK); | 1180 | vecstride = 1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK); |
1185 | 1181 | ||
1186 | /* | 1182 | /* |
1183 | * fcvtsd takes a dN register number as destination, not sN. | ||
1184 | * Technically, if bit 0 of dd is set, this is an invalid | ||
1185 | * instruction. However, we ignore this for efficiency. | ||
1186 | * It also only operates on scalars. | ||
1187 | */ | ||
1188 | if ((inst & FEXT_MASK) == FEXT_FCVT) { | ||
1189 | veclen = 0; | ||
1190 | dest = vfp_get_dd(inst); | ||
1191 | } else | ||
1192 | dest = vfp_get_sd(inst); | ||
1193 | |||
1194 | /* | ||
1187 | * If destination bank is zero, vector length is always '1'. | 1195 | * If destination bank is zero, vector length is always '1'. |
1188 | * ARM DDI0100F C5.1.3, C5.3.2. | 1196 | * ARM DDI0100F C5.1.3, C5.3.2. |
1189 | */ | 1197 | */ |
1190 | if (FREG_BANK(sd) == 0) | 1198 | if (FREG_BANK(dest) == 0) |
1191 | veclen = 0; | 1199 | veclen = 0; |
1192 | 1200 | ||
1193 | pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride, | 1201 | pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride, |
@@ -1201,15 +1209,18 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr) | |||
1201 | s32 m = vfp_get_float(sm); | 1209 | s32 m = vfp_get_float(sm); |
1202 | u32 except; | 1210 | u32 except; |
1203 | 1211 | ||
1204 | if (op == FOP_EXT) | 1212 | if (op == FOP_EXT && (inst & FEXT_MASK) == FEXT_FCVT) |
1213 | pr_debug("VFP: itr%d (d%u) = op[%u] (s%u=%08x)\n", | ||
1214 | vecitr >> FPSCR_LENGTH_BIT, dest, sn, sm, m); | ||
1215 | else if (op == FOP_EXT) | ||
1205 | pr_debug("VFP: itr%d (s%u) = op[%u] (s%u=%08x)\n", | 1216 | pr_debug("VFP: itr%d (s%u) = op[%u] (s%u=%08x)\n", |
1206 | vecitr >> FPSCR_LENGTH_BIT, sd, sn, sm, m); | 1217 | vecitr >> FPSCR_LENGTH_BIT, dest, sn, sm, m); |
1207 | else | 1218 | else |
1208 | pr_debug("VFP: itr%d (s%u) = (s%u) op[%u] (s%u=%08x)\n", | 1219 | pr_debug("VFP: itr%d (s%u) = (s%u) op[%u] (s%u=%08x)\n", |
1209 | vecitr >> FPSCR_LENGTH_BIT, sd, sn, | 1220 | vecitr >> FPSCR_LENGTH_BIT, dest, sn, |
1210 | FOP_TO_IDX(op), sm, m); | 1221 | FOP_TO_IDX(op), sm, m); |
1211 | 1222 | ||
1212 | except = fop(sd, sn, m, fpscr); | 1223 | except = fop(dest, sn, m, fpscr); |
1213 | pr_debug("VFP: itr%d: exceptions=%08x\n", | 1224 | pr_debug("VFP: itr%d: exceptions=%08x\n", |
1214 | vecitr >> FPSCR_LENGTH_BIT, except); | 1225 | vecitr >> FPSCR_LENGTH_BIT, except); |
1215 | 1226 | ||
@@ -1227,7 +1238,7 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr) | |||
1227 | * we encounter an exception. We continue. | 1238 | * we encounter an exception. We continue. |
1228 | */ | 1239 | */ |
1229 | 1240 | ||
1230 | sd = FREG_BANK(sd) + ((FREG_IDX(sd) + vecstride) & 7); | 1241 | dest = FREG_BANK(dest) + ((FREG_IDX(dest) + vecstride) & 7); |
1231 | sn = FREG_BANK(sn) + ((FREG_IDX(sn) + vecstride) & 7); | 1242 | sn = FREG_BANK(sn) + ((FREG_IDX(sn) + vecstride) & 7); |
1232 | if (FREG_BANK(sm) != 0) | 1243 | if (FREG_BANK(sm) != 0) |
1233 | sm = FREG_BANK(sm) + ((FREG_IDX(sm) + vecstride) & 7); | 1244 | sm = FREG_BANK(sm) + ((FREG_IDX(sm) + vecstride) & 7); |