aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm
diff options
context:
space:
mode:
authorPaul Mackerras <paulus@samba.org>2006-06-12 03:53:34 -0400
committerPaul Mackerras <paulus@samba.org>2006-06-12 03:53:34 -0400
commit7a0c58d0513c246ac5438ef4a55ce8b93395ae0e (patch)
treed18f58349ced242aa62e622e381e60933f71d451 /arch/arm
parent6218a761bbc27acc65248c80024875bcc06d52b1 (diff)
parent289a1e995e74734b5ec76ca8a5490058f4fecc24 (diff)
Merge branch 'merge'
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig.debug2
-rw-r--r--arch/arm/mach-ep93xx/ts72xx.c8
-rw-r--r--arch/arm/mach-ixp23xx/core.c18
-rw-r--r--arch/arm/mach-ixp4xx/Kconfig2
-rw-r--r--arch/arm/mach-pxa/mainstone.c1
-rw-r--r--arch/arm/mach-s3c2410/Kconfig2
6 files changed, 23 insertions, 10 deletions
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 5d3acff8c596..d22f38b957db 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -101,7 +101,7 @@ config DEBUG_S3C2410_UART
101 help 101 help
102 Choice for UART for kernel low-level using S3C2410 UARTS, 102 Choice for UART for kernel low-level using S3C2410 UARTS,
103 should be between zero and two. The port must have been 103 should be between zero and two. The port must have been
104 initalised by the boot-loader before use. 104 initialised by the boot-loader before use.
105 105
106 The uncompressor code port configuration is now handled 106 The uncompressor code port configuration is now handled
107 by CONFIG_S3C2410_LOWLEVEL_UART_PORT. 107 by CONFIG_S3C2410_LOWLEVEL_UART_PORT.
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 9be01b0c3f48..e24566b88a78 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -111,21 +111,21 @@ static void __init ts72xx_map_io(void)
111 } 111 }
112} 112}
113 113
114static unsigned char ts72xx_rtc_readb(unsigned long addr) 114static unsigned char ts72xx_rtc_readbyte(unsigned long addr)
115{ 115{
116 __raw_writeb(addr, TS72XX_RTC_INDEX_VIRT_BASE); 116 __raw_writeb(addr, TS72XX_RTC_INDEX_VIRT_BASE);
117 return __raw_readb(TS72XX_RTC_DATA_VIRT_BASE); 117 return __raw_readb(TS72XX_RTC_DATA_VIRT_BASE);
118} 118}
119 119
120static void ts72xx_rtc_writeb(unsigned char value, unsigned long addr) 120static void ts72xx_rtc_writebyte(unsigned char value, unsigned long addr)
121{ 121{
122 __raw_writeb(addr, TS72XX_RTC_INDEX_VIRT_BASE); 122 __raw_writeb(addr, TS72XX_RTC_INDEX_VIRT_BASE);
123 __raw_writeb(value, TS72XX_RTC_DATA_VIRT_BASE); 123 __raw_writeb(value, TS72XX_RTC_DATA_VIRT_BASE);
124} 124}
125 125
126static struct m48t86_ops ts72xx_rtc_ops = { 126static struct m48t86_ops ts72xx_rtc_ops = {
127 .readb = ts72xx_rtc_readb, 127 .readbyte = ts72xx_rtc_readbyte,
128 .writeb = ts72xx_rtc_writeb, 128 .writebyte = ts72xx_rtc_writebyte,
129}; 129};
130 130
131static struct platform_device ts72xx_rtc_device = { 131static struct platform_device ts72xx_rtc_device = {
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index 092ee12ced42..affd1d5d7440 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -178,8 +178,12 @@ static int ixp23xx_irq_set_type(unsigned int irq, unsigned int type)
178 178
179static void ixp23xx_irq_mask(unsigned int irq) 179static void ixp23xx_irq_mask(unsigned int irq)
180{ 180{
181 volatile unsigned long *intr_reg = IXP23XX_INTR_EN1 + (irq / 32); 181 volatile unsigned long *intr_reg;
182 182
183 if (irq >= 56)
184 irq += 8;
185
186 intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
183 *intr_reg &= ~(1 << (irq % 32)); 187 *intr_reg &= ~(1 << (irq % 32));
184} 188}
185 189
@@ -199,17 +203,25 @@ static void ixp23xx_irq_ack(unsigned int irq)
199 */ 203 */
200static void ixp23xx_irq_level_unmask(unsigned int irq) 204static void ixp23xx_irq_level_unmask(unsigned int irq)
201{ 205{
202 volatile unsigned long *intr_reg = IXP23XX_INTR_EN1 + (irq / 32); 206 volatile unsigned long *intr_reg;
203 207
204 ixp23xx_irq_ack(irq); 208 ixp23xx_irq_ack(irq);
205 209
210 if (irq >= 56)
211 irq += 8;
212
213 intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
206 *intr_reg |= (1 << (irq % 32)); 214 *intr_reg |= (1 << (irq % 32));
207} 215}
208 216
209static void ixp23xx_irq_edge_unmask(unsigned int irq) 217static void ixp23xx_irq_edge_unmask(unsigned int irq)
210{ 218{
211 volatile unsigned long *intr_reg = IXP23XX_INTR_EN1 + (irq / 32); 219 volatile unsigned long *intr_reg;
220
221 if (irq >= 56)
222 irq += 8;
212 223
224 intr_reg = IXP23XX_INTR_EN1 + (irq / 32);
213 *intr_reg |= (1 << (irq % 32)); 225 *intr_reg |= (1 << (irq % 32));
214} 226}
215 227
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 2a39f9e481ad..3b23f43cb160 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -141,7 +141,7 @@ config IXP4XX_INDIRECT_PCI
141 2) If > 64MB of memory space is required, the IXP4xx can be 141 2) If > 64MB of memory space is required, the IXP4xx can be
142 configured to use indirect registers to access PCI This allows 142 configured to use indirect registers to access PCI This allows
143 for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus. 143 for up to 128MB (0x48000000 to 0x4fffffff) of memory on the bus.
144 The disadvantadge of this is that every PCI access requires 144 The disadvantage of this is that every PCI access requires
145 three local register accesses plus a spinlock, but in some 145 three local register accesses plus a spinlock, but in some
146 cases the performance hit is acceptable. In addition, you cannot 146 cases the performance hit is acceptable. In addition, you cannot
147 mmap() PCI devices in this case due to the indirect nature 147 mmap() PCI devices in this case due to the indirect nature
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 02e188d98e7d..b307f11951df 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -493,6 +493,7 @@ static void __init mainstone_map_io(void)
493MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)") 493MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
494 /* Maintainer: MontaVista Software Inc. */ 494 /* Maintainer: MontaVista Software Inc. */
495 .phys_io = 0x40000000, 495 .phys_io = 0x40000000,
496 .boot_params = 0xa0000100, /* BLOB boot parameter setting */
496 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, 497 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
497 .map_io = mainstone_map_io, 498 .map_io = mainstone_map_io,
498 .init_irq = mainstone_init_irq, 499 .init_irq = mainstone_init_irq,
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index ce7d81000695..970f98dadffc 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -170,7 +170,7 @@ config S3C2410_PM_DEBUG
170 depends on ARCH_S3C2410 && PM 170 depends on ARCH_S3C2410 && PM
171 help 171 help
172 Say Y here if you want verbose debugging from the PM Suspend and 172 Say Y here if you want verbose debugging from the PM Suspend and
173 Resume code. See `Documentation/arm/Samsing-S3C24XX/Suspend.txt` 173 Resume code. See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt>
174 for more information. 174 for more information.
175 175
176config S3C2410_PM_CHECK 176config S3C2410_PM_CHECK