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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2006-09-27 14:57:54 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-09-27 14:57:54 -0400
commit2dc94310bd94d0906febea7d0f7c188da620c952 (patch)
tree6de4096f1887e2c00966177354b1c378e59bd632 /arch/arm
parentc06015148fa9a3cc452ec7121b8c3f59f4a7d6ac (diff)
parentfb60cf4ab52f3520c2119aa42f7d4ed8e7594eb6 (diff)
Merge master.kernel.org:/pub/scm/linux/kernel/git/tmlind/linux-omap-upstream into devel
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-omap1/clock.c107
-rw-r--r--arch/arm/mach-omap1/clock.h14
-rw-r--r--arch/arm/mach-omap1/mux.c11
-rw-r--r--arch/arm/mach-omap2/board-apollon.c7
-rw-r--r--arch/arm/mach-omap2/clock.c146
-rw-r--r--arch/arm/mach-omap2/clock.h20
-rw-r--r--arch/arm/mach-omap2/gpmc.c180
-rw-r--r--arch/arm/mach-omap2/irq.c12
-rw-r--r--arch/arm/mach-omap2/mux.c14
-rw-r--r--arch/arm/mach-omap2/prcm.c10
-rw-r--r--arch/arm/plat-omap/clock.c26
-rw-r--r--arch/arm/plat-omap/devices.c20
-rw-r--r--arch/arm/plat-omap/dma.c95
-rw-r--r--arch/arm/plat-omap/dmtimer.c76
-rw-r--r--arch/arm/plat-omap/gpio.c45
-rw-r--r--arch/arm/plat-omap/mcbsp.c9
-rw-r--r--arch/arm/plat-omap/pm.c670
-rw-r--r--arch/arm/plat-omap/sram.c5
-rw-r--r--arch/arm/plat-omap/timer32k.c38
19 files changed, 652 insertions, 853 deletions
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index f1958e882e86..638490e62d5f 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -20,6 +20,7 @@
20#include <linux/clk.h> 20#include <linux/clk.h>
21 21
22#include <asm/io.h> 22#include <asm/io.h>
23#include <asm/mach-types.h>
23 24
24#include <asm/arch/cpu.h> 25#include <asm/arch/cpu.h>
25#include <asm/arch/usb.h> 26#include <asm/arch/usb.h>
@@ -586,77 +587,53 @@ static int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
586 *-------------------------------------------------------------------------*/ 587 *-------------------------------------------------------------------------*/
587 588
588#ifdef CONFIG_OMAP_RESET_CLOCKS 589#ifdef CONFIG_OMAP_RESET_CLOCKS
589/*
590 * Resets some clocks that may be left on from bootloader,
591 * but leaves serial clocks on. See also omap_late_clk_reset().
592 */
593static inline void omap1_early_clk_reset(void)
594{
595 //omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
596}
597 590
598static int __init omap1_late_clk_reset(void) 591static void __init omap1_clk_disable_unused(struct clk *clk)
599{ 592{
600 /* Turn off all unused clocks */
601 struct clk *p;
602 __u32 regval32; 593 __u32 regval32;
603 594
604 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ 595 /* Clocks in the DSP domain need api_ck. Just assume bootloader
605 regval32 = omap_readw(SOFT_REQ_REG) & (1 << 4); 596 * has not enabled any DSP clocks */
606 omap_writew(regval32, SOFT_REQ_REG); 597 if ((u32)clk->enable_reg == DSP_IDLECT2) {
607 omap_writew(0, SOFT_REQ_REG2); 598 printk(KERN_INFO "Skipping reset check for DSP domain "
608 599 "clock \"%s\"\n", clk->name);
609 list_for_each_entry(p, &clocks, node) { 600 return;
610 if (p->usecount > 0 || (p->flags & ALWAYS_ENABLED) || 601 }
611 p->enable_reg == 0)
612 continue;
613
614 /* Clocks in the DSP domain need api_ck. Just assume bootloader
615 * has not enabled any DSP clocks */
616 if ((u32)p->enable_reg == DSP_IDLECT2) {
617 printk(KERN_INFO "Skipping reset check for DSP domain "
618 "clock \"%s\"\n", p->name);
619 continue;
620 }
621 602
622 /* Is the clock already disabled? */ 603 /* Is the clock already disabled? */
623 if (p->flags & ENABLE_REG_32BIT) { 604 if (clk->flags & ENABLE_REG_32BIT) {
624 if (p->flags & VIRTUAL_IO_ADDRESS) 605 if (clk->flags & VIRTUAL_IO_ADDRESS)
625 regval32 = __raw_readl(p->enable_reg); 606 regval32 = __raw_readl(clk->enable_reg);
626 else
627 regval32 = omap_readl(p->enable_reg);
628 } else {
629 if (p->flags & VIRTUAL_IO_ADDRESS)
630 regval32 = __raw_readw(p->enable_reg);
631 else 607 else
632 regval32 = omap_readw(p->enable_reg); 608 regval32 = omap_readl(clk->enable_reg);
633 } 609 } else {
634 610 if (clk->flags & VIRTUAL_IO_ADDRESS)
635 if ((regval32 & (1 << p->enable_bit)) == 0) 611 regval32 = __raw_readw(clk->enable_reg);
636 continue; 612 else
613 regval32 = omap_readw(clk->enable_reg);
614 }
637 615
638 /* FIXME: This clock seems to be necessary but no-one 616 if ((regval32 & (1 << clk->enable_bit)) == 0)
639 * has asked for its activation. */ 617 return;
640 if (p == &tc2_ck // FIX: pm.c (SRAM), CCP, Camera
641 || p == &ck_dpll1out.clk // FIX: SoSSI, SSR
642 || p == &arm_gpio_ck // FIX: GPIO code for 1510
643 ) {
644 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
645 p->name);
646 continue;
647 }
648 618
649 printk(KERN_INFO "Disabling unused clock \"%s\"... ", p->name); 619 /* FIXME: This clock seems to be necessary but no-one
650 p->disable(p); 620 * has asked for its activation. */
651 printk(" done\n"); 621 if (clk == &tc2_ck // FIX: pm.c (SRAM), CCP, Camera
622 || clk == &ck_dpll1out.clk // FIX: SoSSI, SSR
623 || clk == &arm_gpio_ck // FIX: GPIO code for 1510
624 ) {
625 printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n",
626 clk->name);
627 return;
652 } 628 }
653 629
654 return 0; 630 printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
631 clk->disable(clk);
632 printk(" done\n");
655} 633}
656late_initcall(omap1_late_clk_reset);
657 634
658#else 635#else
659#define omap1_early_clk_reset() {} 636#define omap1_clk_disable_unused NULL
660#endif 637#endif
661 638
662static struct clk_functions omap1_clk_functions = { 639static struct clk_functions omap1_clk_functions = {
@@ -664,6 +641,7 @@ static struct clk_functions omap1_clk_functions = {
664 .clk_disable = omap1_clk_disable, 641 .clk_disable = omap1_clk_disable,
665 .clk_round_rate = omap1_clk_round_rate, 642 .clk_round_rate = omap1_clk_round_rate,
666 .clk_set_rate = omap1_clk_set_rate, 643 .clk_set_rate = omap1_clk_set_rate,
644 .clk_disable_unused = omap1_clk_disable_unused,
667}; 645};
668 646
669int __init omap1_clk_init(void) 647int __init omap1_clk_init(void)
@@ -671,8 +649,13 @@ int __init omap1_clk_init(void)
671 struct clk ** clkp; 649 struct clk ** clkp;
672 const struct omap_clock_config *info; 650 const struct omap_clock_config *info;
673 int crystal_type = 0; /* Default 12 MHz */ 651 int crystal_type = 0; /* Default 12 MHz */
652 u32 reg;
653
654 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
655 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
656 omap_writew(reg, SOFT_REQ_REG);
657 omap_writew(0, SOFT_REQ_REG2);
674 658
675 omap1_early_clk_reset();
676 clk_init(&omap1_clk_functions); 659 clk_init(&omap1_clk_functions);
677 660
678 /* By default all idlect1 clocks are allowed to idle */ 661 /* By default all idlect1 clocks are allowed to idle */
@@ -772,6 +755,12 @@ int __init omap1_clk_init(void)
772 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL); 755 omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
773#endif 756#endif
774 757
758 /* Amstrad Delta wants BCLK high when inactive */
759 if (machine_is_ams_delta())
760 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
761 (1 << SDW_MCLK_INV_BIT),
762 ULPD_CLOCK_CTRL);
763
775 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ 764 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
776 /* (on 730, bit 13 must not be cleared) */ 765 /* (on 730, bit 13 must not be cleared) */
777 if (cpu_is_omap730()) 766 if (cpu_is_omap730())
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index b7c68819c4e7..f7df00205c4a 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -89,6 +89,7 @@ struct arm_idlect1_clk {
89#define EN_DSPTIMCK 5 89#define EN_DSPTIMCK 5
90 90
91/* Various register defines for clock controls scattered around OMAP chip */ 91/* Various register defines for clock controls scattered around OMAP chip */
92#define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */
92#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */ 93#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
93#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */ 94#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
94#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */ 95#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
@@ -741,6 +742,18 @@ static struct clk i2c_fck = {
741 .disable = &omap1_clk_disable_generic, 742 .disable = &omap1_clk_disable_generic,
742}; 743};
743 744
745static struct clk i2c_ick = {
746 .name = "i2c_ick",
747 .id = 1,
748 .flags = CLOCK_IN_OMAP16XX |
749 VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT |
750 ALWAYS_ENABLED,
751 .parent = &armper_ck.clk,
752 .recalc = &followparent_recalc,
753 .enable = &omap1_clk_enable_generic,
754 .disable = &omap1_clk_disable_generic,
755};
756
744static struct clk * onchip_clks[] = { 757static struct clk * onchip_clks[] = {
745 /* non-ULPD clocks */ 758 /* non-ULPD clocks */
746 &ck_ref, 759 &ck_ref,
@@ -790,6 +803,7 @@ static struct clk * onchip_clks[] = {
790 /* Virtual clocks */ 803 /* Virtual clocks */
791 &virtual_ck_mpu, 804 &virtual_ck_mpu,
792 &i2c_fck, 805 &i2c_fck,
806 &i2c_ick,
793}; 807};
794 808
795#endif 809#endif
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index fa74ef7af15f..5432335bc493 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -199,6 +199,17 @@ MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
199MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1) 199MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
200MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1) 200MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1)
201 201
202/* OMAP-1610 SPI */
203MUX_CFG("U19_1610_SPIF_SCK", 7, 21, 6, 1, 15, 0, 1, 1, 1)
204MUX_CFG("U18_1610_SPIF_DIN", 8, 0, 6, 1, 18, 1, 1, 0, 1)
205MUX_CFG("P20_1610_SPIF_DIN", 6, 27, 4, 1, 7, 1, 1, 0, 1)
206MUX_CFG("W21_1610_SPIF_DOUT", 8, 3, 6, 1, 19, 0, 1, 0, 1)
207MUX_CFG("R18_1610_SPIF_DOUT", 7, 9, 3, 1, 11, 0, 1, 0, 1)
208MUX_CFG("N14_1610_SPIF_CS0", 8, 9, 6, 1, 21, 0, 1, 1, 1)
209MUX_CFG("N15_1610_SPIF_CS1", 7, 18, 6, 1, 14, 0, 1, 1, 1)
210MUX_CFG("T19_1610_SPIF_CS2", 7, 15, 4, 1, 13, 0, 1, 1, 1)
211MUX_CFG("P15_1610_SPIF_CS3", 8, 12, 3, 1, 22, 0, 1, 1, 1)
212
202/* OMAP-1610 Flash */ 213/* OMAP-1610 Flash */
203MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1) 214MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1)
204MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1) 215MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1)
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 7993b7bae2bd..2db6b732b084 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -166,8 +166,8 @@ static struct omap_uart_config apollon_uart_config __initdata = {
166 166
167static struct omap_mmc_config apollon_mmc_config __initdata = { 167static struct omap_mmc_config apollon_mmc_config __initdata = {
168 .mmc [0] = { 168 .mmc [0] = {
169 .enabled = 0, 169 .enabled = 1,
170 .wire4 = 0, 170 .wire4 = 1,
171 .wp_pin = -1, 171 .wp_pin = -1,
172 .power_pin = -1, 172 .power_pin = -1,
173 .switch_pin = -1, 173 .switch_pin = -1,
@@ -257,6 +257,9 @@ static void __init omap_apollon_init(void)
257 /* REVISIT: where's the correct place */ 257 /* REVISIT: where's the correct place */
258 omap_cfg_reg(W19_24XX_SYS_NIRQ); 258 omap_cfg_reg(W19_24XX_SYS_NIRQ);
259 259
260 /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */
261 CONTROL_DEVCONF |= (1 << 24);
262
260 /* 263 /*
261 * Make sure the serial ports are muxed on at this point. 264 * Make sure the serial ports are muxed on at this point.
262 * You have to mux them off in device drivers later on 265 * You have to mux them off in device drivers later on
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index d1b648a4efbf..0de201c3d50b 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -32,10 +32,14 @@
32#include "memory.h" 32#include "memory.h"
33#include "clock.h" 33#include "clock.h"
34 34
35#undef DEBUG
36
35//#define DOWN_VARIABLE_DPLL 1 /* Experimental */ 37//#define DOWN_VARIABLE_DPLL 1 /* Experimental */
36 38
37static struct prcm_config *curr_prcm_set; 39static struct prcm_config *curr_prcm_set;
38static u32 curr_perf_level = PRCM_FULL_SPEED; 40static u32 curr_perf_level = PRCM_FULL_SPEED;
41static struct clk *vclk;
42static struct clk *sclk;
39 43
40/*------------------------------------------------------------------------- 44/*-------------------------------------------------------------------------
41 * Omap2 specific clock functions 45 * Omap2 specific clock functions
@@ -79,6 +83,14 @@ static void omap2_propagate_rate(struct clk * clk)
79 propagate_rate(clk); 83 propagate_rate(clk);
80} 84}
81 85
86static void omap2_set_osc_ck(int enable)
87{
88 if (enable)
89 PRCM_CLKSRC_CTRL &= ~(0x3 << 3);
90 else
91 PRCM_CLKSRC_CTRL |= 0x3 << 3;
92}
93
82/* Enable an APLL if off */ 94/* Enable an APLL if off */
83static void omap2_clk_fixed_enable(struct clk *clk) 95static void omap2_clk_fixed_enable(struct clk *clk)
84{ 96{
@@ -101,12 +113,54 @@ static void omap2_clk_fixed_enable(struct clk *clk)
101 else if (clk == &apll54_ck) 113 else if (clk == &apll54_ck)
102 cval = (1 << 6); 114 cval = (1 << 6);
103 115
104 while (!CM_IDLEST_CKGEN & cval) { /* Wait for lock */ 116 while (!(CM_IDLEST_CKGEN & cval)) { /* Wait for lock */
105 ++i; 117 ++i;
106 udelay(1); 118 udelay(1);
107 if (i == 100000) 119 if (i == 100000) {
120 printk(KERN_ERR "Clock %s didn't lock\n", clk->name);
121 break;
122 }
123 }
124}
125
126static void omap2_clk_wait_ready(struct clk *clk)
127{
128 unsigned long reg, other_reg, st_reg;
129 u32 bit;
130 int i;
131
132 reg = (unsigned long) clk->enable_reg;
133 if (reg == (unsigned long) &CM_FCLKEN1_CORE ||
134 reg == (unsigned long) &CM_FCLKEN2_CORE)
135 other_reg = (reg & ~0xf0) | 0x10;
136 else if (reg == (unsigned long) &CM_ICLKEN1_CORE ||
137 reg == (unsigned long) &CM_ICLKEN2_CORE)
138 other_reg = (reg & ~0xf0) | 0x00;
139 else
140 return;
141
142 /* No check for DSS or cam clocks */
143 if ((reg & 0x0f) == 0) {
144 if (clk->enable_bit <= 1 || clk->enable_bit == 31)
145 return;
146 }
147
148 /* Check if both functional and interface clocks
149 * are running. */
150 bit = 1 << clk->enable_bit;
151 if (!(__raw_readl(other_reg) & bit))
152 return;
153 st_reg = (other_reg & ~0xf0) | 0x20;
154 i = 0;
155 while (!(__raw_readl(st_reg) & bit)) {
156 i++;
157 if (i == 100000) {
158 printk(KERN_ERR "Timeout enabling clock %s\n", clk->name);
108 break; 159 break;
160 }
109 } 161 }
162 if (i)
163 pr_debug("Clock %s stable after %d loops\n", clk->name, i);
110} 164}
111 165
112/* Enables clock without considering parent dependencies or use count 166/* Enables clock without considering parent dependencies or use count
@@ -119,6 +173,11 @@ static int _omap2_clk_enable(struct clk * clk)
119 if (clk->flags & ALWAYS_ENABLED) 173 if (clk->flags & ALWAYS_ENABLED)
120 return 0; 174 return 0;
121 175
176 if (unlikely(clk == &osc_ck)) {
177 omap2_set_osc_ck(1);
178 return 0;
179 }
180
122 if (unlikely(clk->enable_reg == 0)) { 181 if (unlikely(clk->enable_reg == 0)) {
123 printk(KERN_ERR "clock.c: Enable for %s without enable code\n", 182 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
124 clk->name); 183 clk->name);
@@ -133,6 +192,9 @@ static int _omap2_clk_enable(struct clk * clk)
133 regval32 = __raw_readl(clk->enable_reg); 192 regval32 = __raw_readl(clk->enable_reg);
134 regval32 |= (1 << clk->enable_bit); 193 regval32 |= (1 << clk->enable_bit);
135 __raw_writel(regval32, clk->enable_reg); 194 __raw_writel(regval32, clk->enable_reg);
195 wmb();
196
197 omap2_clk_wait_ready(clk);
136 198
137 return 0; 199 return 0;
138} 200}
@@ -155,6 +217,11 @@ static void _omap2_clk_disable(struct clk *clk)
155{ 217{
156 u32 regval32; 218 u32 regval32;
157 219
220 if (unlikely(clk == &osc_ck)) {
221 omap2_set_osc_ck(0);
222 return;
223 }
224
158 if (clk->enable_reg == 0) 225 if (clk->enable_reg == 0)
159 return; 226 return;
160 227
@@ -166,6 +233,7 @@ static void _omap2_clk_disable(struct clk *clk)
166 regval32 = __raw_readl(clk->enable_reg); 233 regval32 = __raw_readl(clk->enable_reg);
167 regval32 &= ~(1 << clk->enable_bit); 234 regval32 &= ~(1 << clk->enable_bit);
168 __raw_writel(regval32, clk->enable_reg); 235 __raw_writel(regval32, clk->enable_reg);
236 wmb();
169} 237}
170 238
171static int omap2_clk_enable(struct clk *clk) 239static int omap2_clk_enable(struct clk *clk)
@@ -695,12 +763,14 @@ static int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
695 reg_val = __raw_readl(reg); 763 reg_val = __raw_readl(reg);
696 reg_val &= ~(field_mask << div_off); 764 reg_val &= ~(field_mask << div_off);
697 reg_val |= (field_val << div_off); 765 reg_val |= (field_val << div_off);
698
699 __raw_writel(reg_val, reg); 766 __raw_writel(reg_val, reg);
767 wmb();
700 clk->rate = clk->parent->rate / field_val; 768 clk->rate = clk->parent->rate / field_val;
701 769
702 if (clk->flags & DELAYED_APP) 770 if (clk->flags & DELAYED_APP) {
703 __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL); 771 __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
772 wmb();
773 }
704 ret = 0; 774 ret = 0;
705 } else if (clk->set_rate != 0) 775 } else if (clk->set_rate != 0)
706 ret = clk->set_rate(clk, rate); 776 ret = clk->set_rate(clk, rate);
@@ -836,10 +906,12 @@ static int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
836 reg_val = __raw_readl(reg) & ~(field_mask << src_off); 906 reg_val = __raw_readl(reg) & ~(field_mask << src_off);
837 reg_val |= (field_val << src_off); 907 reg_val |= (field_val << src_off);
838 __raw_writel(reg_val, reg); 908 __raw_writel(reg_val, reg);
909 wmb();
839 910
840 if (clk->flags & DELAYED_APP) 911 if (clk->flags & DELAYED_APP) {
841 __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL); 912 __raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
842 913 wmb();
914 }
843 if (clk->usecount > 0) 915 if (clk->usecount > 0)
844 _omap2_clk_enable(clk); 916 _omap2_clk_enable(clk);
845 917
@@ -953,12 +1025,29 @@ static int omap2_select_table_rate(struct clk * clk, unsigned long rate)
953 * Omap2 clock reset and init functions 1025 * Omap2 clock reset and init functions
954 *-------------------------------------------------------------------------*/ 1026 *-------------------------------------------------------------------------*/
955 1027
1028#ifdef CONFIG_OMAP_RESET_CLOCKS
1029static void __init omap2_clk_disable_unused(struct clk *clk)
1030{
1031 u32 regval32;
1032
1033 regval32 = __raw_readl(clk->enable_reg);
1034 if ((regval32 & (1 << clk->enable_bit)) == 0)
1035 return;
1036
1037 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
1038 _omap2_clk_disable(clk);
1039}
1040#else
1041#define omap2_clk_disable_unused NULL
1042#endif
1043
956static struct clk_functions omap2_clk_functions = { 1044static struct clk_functions omap2_clk_functions = {
957 .clk_enable = omap2_clk_enable, 1045 .clk_enable = omap2_clk_enable,
958 .clk_disable = omap2_clk_disable, 1046 .clk_disable = omap2_clk_disable,
959 .clk_round_rate = omap2_clk_round_rate, 1047 .clk_round_rate = omap2_clk_round_rate,
960 .clk_set_rate = omap2_clk_set_rate, 1048 .clk_set_rate = omap2_clk_set_rate,
961 .clk_set_parent = omap2_clk_set_parent, 1049 .clk_set_parent = omap2_clk_set_parent,
1050 .clk_disable_unused = omap2_clk_disable_unused,
962}; 1051};
963 1052
964static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys) 1053static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
@@ -984,27 +1073,19 @@ static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
984 sys->rate = sclk; 1073 sys->rate = sclk;
985} 1074}
986 1075
987#ifdef CONFIG_OMAP_RESET_CLOCKS 1076/*
988static void __init omap2_disable_unused_clocks(void) 1077 * Set clocks for bypass mode for reboot to work.
1078 */
1079void omap2_clk_prepare_for_reboot(void)
989{ 1080{
990 struct clk *ck; 1081 u32 rate;
991 u32 regval32;
992 1082
993 list_for_each_entry(ck, &clocks, node) { 1083 if (vclk == NULL || sclk == NULL)
994 if (ck->usecount > 0 || (ck->flags & ALWAYS_ENABLED) || 1084 return;
995 ck->enable_reg == 0)
996 continue;
997
998 regval32 = __raw_readl(ck->enable_reg);
999 if ((regval32 & (1 << ck->enable_bit)) == 0)
1000 continue;
1001 1085
1002 printk(KERN_INFO "Disabling unused clock \"%s\"\n", ck->name); 1086 rate = clk_get_rate(sclk);
1003 _omap2_clk_disable(ck); 1087 clk_set_rate(vclk, rate);
1004 }
1005} 1088}
1006late_initcall(omap2_disable_unused_clocks);
1007#endif
1008 1089
1009/* 1090/*
1010 * Switch the MPU rate if specified on cmdline. 1091 * Switch the MPU rate if specified on cmdline.
@@ -1077,8 +1158,27 @@ int __init omap2_clk_init(void)
1077 */ 1158 */
1078 clk_enable(&sync_32k_ick); 1159 clk_enable(&sync_32k_ick);
1079 clk_enable(&omapctrl_ick); 1160 clk_enable(&omapctrl_ick);
1161
1162 /* Force the APLLs active during bootup to avoid disabling and
1163 * enabling them unnecessarily. */
1164 clk_enable(&apll96_ck);
1165 clk_enable(&apll54_ck);
1166
1080 if (cpu_is_omap2430()) 1167 if (cpu_is_omap2430())
1081 clk_enable(&sdrc_ick); 1168 clk_enable(&sdrc_ick);
1082 1169
1170 /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
1171 vclk = clk_get(NULL, "virt_prcm_set");
1172 sclk = clk_get(NULL, "sys_ck");
1173
1174 return 0;
1175}
1176
1177static int __init omap2_disable_aplls(void)
1178{
1179 clk_disable(&apll96_ck);
1180 clk_disable(&apll54_ck);
1181
1083 return 0; 1182 return 0;
1084} 1183}
1184late_initcall(omap2_disable_aplls);
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2781dfbc5164..8816f5a33a28 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -560,7 +560,7 @@ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */
560 .name = "osc_ck", 560 .name = "osc_ck",
561 .rate = 26000000, /* fixed up in clock init */ 561 .rate = 26000000, /* fixed up in clock init */
562 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 562 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
563 RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, 563 RATE_FIXED | RATE_PROPAGATES,
564}; 564};
565 565
566/* With out modem likely 12MHz, with modem likely 13MHz */ 566/* With out modem likely 12MHz, with modem likely 13MHz */
@@ -1368,7 +1368,8 @@ static struct clk mcbsp5_fck = {
1368}; 1368};
1369 1369
1370static struct clk mcspi1_ick = { 1370static struct clk mcspi1_ick = {
1371 .name = "mcspi1_ick", 1371 .name = "mcspi_ick",
1372 .id = 1,
1372 .parent = &l4_ck, 1373 .parent = &l4_ck,
1373 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1374 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1374 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 1375 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
@@ -1377,7 +1378,8 @@ static struct clk mcspi1_ick = {
1377}; 1378};
1378 1379
1379static struct clk mcspi1_fck = { 1380static struct clk mcspi1_fck = {
1380 .name = "mcspi1_fck", 1381 .name = "mcspi_fck",
1382 .id = 1,
1381 .parent = &func_48m_ck, 1383 .parent = &func_48m_ck,
1382 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1384 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1383 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1385 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
@@ -1386,7 +1388,8 @@ static struct clk mcspi1_fck = {
1386}; 1388};
1387 1389
1388static struct clk mcspi2_ick = { 1390static struct clk mcspi2_ick = {
1389 .name = "mcspi2_ick", 1391 .name = "mcspi_ick",
1392 .id = 2,
1390 .parent = &l4_ck, 1393 .parent = &l4_ck,
1391 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1394 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1392 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE, 1395 .enable_reg = (void __iomem *)&CM_ICLKEN1_CORE,
@@ -1395,7 +1398,8 @@ static struct clk mcspi2_ick = {
1395}; 1398};
1396 1399
1397static struct clk mcspi2_fck = { 1400static struct clk mcspi2_fck = {
1398 .name = "mcspi2_fck", 1401 .name = "mcspi_fck",
1402 .id = 2,
1399 .parent = &func_48m_ck, 1403 .parent = &func_48m_ck,
1400 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1404 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1401 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE, 1405 .enable_reg = (void __iomem *)&CM_FCLKEN1_CORE,
@@ -1404,7 +1408,8 @@ static struct clk mcspi2_fck = {
1404}; 1408};
1405 1409
1406static struct clk mcspi3_ick = { 1410static struct clk mcspi3_ick = {
1407 .name = "mcspi3_ick", 1411 .name = "mcspi_ick",
1412 .id = 3,
1408 .parent = &l4_ck, 1413 .parent = &l4_ck,
1409 .flags = CLOCK_IN_OMAP243X, 1414 .flags = CLOCK_IN_OMAP243X,
1410 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE, 1415 .enable_reg = (void __iomem *)&CM_ICLKEN2_CORE,
@@ -1413,7 +1418,8 @@ static struct clk mcspi3_ick = {
1413}; 1418};
1414 1419
1415static struct clk mcspi3_fck = { 1420static struct clk mcspi3_fck = {
1416 .name = "mcspi3_fck", 1421 .name = "mcspi_fck",
1422 .id = 3,
1417 .parent = &func_48m_ck, 1423 .parent = &func_48m_ck,
1418 .flags = CLOCK_IN_OMAP243X, 1424 .flags = CLOCK_IN_OMAP243X,
1419 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE, 1425 .enable_reg = (void __iomem *)&CM_FCLKEN2_CORE,
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index c7a48f921fef..f4f04d87df32 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -13,6 +13,8 @@
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/clk.h> 15#include <linux/clk.h>
16#include <linux/ioport.h>
17#include <linux/spinlock.h>
16 18
17#include <asm/io.h> 19#include <asm/io.h>
18#include <asm/arch/gpmc.h> 20#include <asm/arch/gpmc.h>
@@ -41,6 +43,19 @@
41#define GPMC_CS0 0x60 43#define GPMC_CS0 0x60
42#define GPMC_CS_SIZE 0x30 44#define GPMC_CS_SIZE 0x30
43 45
46#define GPMC_CS_NUM 8
47#define GPMC_MEM_START 0x00000000
48#define GPMC_MEM_END 0x3FFFFFFF
49#define BOOT_ROM_SPACE 0x100000 /* 1MB */
50
51#define GPMC_CHUNK_SHIFT 24 /* 16 MB */
52#define GPMC_SECTION_SHIFT 28 /* 128 MB */
53
54static struct resource gpmc_mem_root;
55static struct resource gpmc_cs_mem[GPMC_CS_NUM];
56static spinlock_t gpmc_mem_lock = SPIN_LOCK_UNLOCKED;
57static unsigned gpmc_cs_map;
58
44static void __iomem *gpmc_base = 59static void __iomem *gpmc_base =
45 (void __iomem *) IO_ADDRESS(GPMC_BASE); 60 (void __iomem *) IO_ADDRESS(GPMC_BASE);
46static void __iomem *gpmc_cs_base = 61static void __iomem *gpmc_cs_base =
@@ -187,9 +202,168 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
187 return 0; 202 return 0;
188} 203}
189 204
190unsigned long gpmc_cs_get_base_addr(int cs) 205static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
206{
207 u32 l;
208 u32 mask;
209
210 mask = (1 << GPMC_SECTION_SHIFT) - size;
211 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
212 l &= ~0x3f;
213 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
214 l &= ~(0x0f << 8);
215 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
216 l |= 1 << 6; /* CSVALID */
217 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
218}
219
220static void gpmc_cs_disable_mem(int cs)
221{
222 u32 l;
223
224 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
225 l &= ~(1 << 6); /* CSVALID */
226 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
227}
228
229static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
230{
231 u32 l;
232 u32 mask;
233
234 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
235 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
236 mask = (l >> 8) & 0x0f;
237 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
238}
239
240static int gpmc_cs_mem_enabled(int cs)
241{
242 u32 l;
243
244 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
245 return l & (1 << 6);
246}
247
248static void gpmc_cs_set_reserved(int cs, int reserved)
191{ 249{
192 return (gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7) & 0x1f) << 24; 250 gpmc_cs_map &= ~(1 << cs);
251 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
252}
253
254static int gpmc_cs_reserved(int cs)
255{
256 return gpmc_cs_map & (1 << cs);
257}
258
259static unsigned long gpmc_mem_align(unsigned long size)
260{
261 int order;
262
263 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
264 order = GPMC_CHUNK_SHIFT - 1;
265 do {
266 size >>= 1;
267 order++;
268 } while (size);
269 size = 1 << order;
270 return size;
271}
272
273static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
274{
275 struct resource *res = &gpmc_cs_mem[cs];
276 int r;
277
278 size = gpmc_mem_align(size);
279 spin_lock(&gpmc_mem_lock);
280 res->start = base;
281 res->end = base + size - 1;
282 r = request_resource(&gpmc_mem_root, res);
283 spin_unlock(&gpmc_mem_lock);
284
285 return r;
286}
287
288int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
289{
290 struct resource *res = &gpmc_cs_mem[cs];
291 int r = -1;
292
293 if (cs > GPMC_CS_NUM)
294 return -ENODEV;
295
296 size = gpmc_mem_align(size);
297 if (size > (1 << GPMC_SECTION_SHIFT))
298 return -ENOMEM;
299
300 spin_lock(&gpmc_mem_lock);
301 if (gpmc_cs_reserved(cs)) {
302 r = -EBUSY;
303 goto out;
304 }
305 if (gpmc_cs_mem_enabled(cs))
306 r = adjust_resource(res, res->start & ~(size - 1), size);
307 if (r < 0)
308 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
309 size, NULL, NULL);
310 if (r < 0)
311 goto out;
312
313 gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
314 *base = res->start;
315 gpmc_cs_set_reserved(cs, 1);
316out:
317 spin_unlock(&gpmc_mem_lock);
318 return r;
319}
320
321void gpmc_cs_free(int cs)
322{
323 spin_lock(&gpmc_mem_lock);
324 if (cs >= GPMC_CS_NUM || !gpmc_cs_reserved(cs)) {
325 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
326 BUG();
327 spin_unlock(&gpmc_mem_lock);
328 return;
329 }
330 gpmc_cs_disable_mem(cs);
331 release_resource(&gpmc_cs_mem[cs]);
332 gpmc_cs_set_reserved(cs, 0);
333 spin_unlock(&gpmc_mem_lock);
334}
335
336void __init gpmc_mem_init(void)
337{
338 int cs;
339 unsigned long boot_rom_space = 0;
340
341 if (cpu_is_omap242x()) {
342 u32 l;
343 l = omap_readl(OMAP242X_CONTROL_STATUS);
344 /* In case of internal boot the 1st MB is redirected to the
345 * boot ROM memory space.
346 */
347 if (l & (1 << 3))
348 boot_rom_space = BOOT_ROM_SPACE;
349 } else
350 /* We assume internal boot if the mode can't be
351 * determined.
352 */
353 boot_rom_space = BOOT_ROM_SPACE;
354 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
355 gpmc_mem_root.end = GPMC_MEM_END;
356
357 /* Reserve all regions that has been set up by bootloader */
358 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
359 u32 base, size;
360
361 if (!gpmc_cs_mem_enabled(cs))
362 continue;
363 gpmc_cs_get_memconf(cs, &base, &size);
364 if (gpmc_cs_insert_mem(cs, base, size) < 0)
365 BUG();
366 }
193} 367}
194 368
195void __init gpmc_init(void) 369void __init gpmc_init(void)
@@ -206,4 +380,6 @@ void __init gpmc_init(void)
206 l &= 0x03 << 3; 380 l &= 0x03 << 3;
207 l |= (0x02 << 3) | (1 << 0); 381 l |= (0x02 << 3) | (1 << 0);
208 gpmc_write_reg(GPMC_SYSCONFIG, l); 382 gpmc_write_reg(GPMC_SYSCONFIG, l);
383
384 gpmc_mem_init();
209} 385}
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index dfc3b35cc1ff..1ed2fff4691a 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -41,18 +41,6 @@ static struct omap_irq_bank {
41 .nr_irqs = 96, 41 .nr_irqs = 96,
42 }, { 42 }, {
43 /* XXX: DSP INTC */ 43 /* XXX: DSP INTC */
44
45#if 0
46 /*
47 * Commented out for now until we fix the IVA clocking
48 */
49#ifdef CONFIG_ARCH_OMAP2420
50 }, {
51 /* IVA INTC (2420 only) */
52 .base_reg = OMAP24XX_IVA_INTC_BASE,
53 .nr_irqs = 16, /* Actually 32, but only 16 are used */
54#endif
55#endif
56 } 44 }
57}; 45};
58 46
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 60ef084faffd..f538d0fdb13c 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -104,6 +104,20 @@ MUX_CFG_24XX("P20_24XX_TSC_IRQ", 0x108, 0, 0, 0, 1)
104MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1) 104MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1)
105MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1) 105MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1)
106 106
107/* MMC/SDIO */
108MUX_CFG_24XX("G19_24XX_MMC_CLKO", 0x0f3, 0, 0, 0, 1)
109MUX_CFG_24XX("H18_24XX_MMC_CMD", 0x0f4, 0, 0, 0, 1)
110MUX_CFG_24XX("F20_24XX_MMC_DAT0", 0x0f5, 0, 0, 0, 1)
111MUX_CFG_24XX("H14_24XX_MMC_DAT1", 0x0f6, 0, 0, 0, 1)
112MUX_CFG_24XX("E19_24XX_MMC_DAT2", 0x0f7, 0, 0, 0, 1)
113MUX_CFG_24XX("D19_24XX_MMC_DAT3", 0x0f8, 0, 0, 0, 1)
114MUX_CFG_24XX("F19_24XX_MMC_DAT_DIR0", 0x0f9, 0, 0, 0, 1)
115MUX_CFG_24XX("E20_24XX_MMC_DAT_DIR1", 0x0fa, 0, 0, 0, 1)
116MUX_CFG_24XX("F18_24XX_MMC_DAT_DIR2", 0x0fb, 0, 0, 0, 1)
117MUX_CFG_24XX("E18_24XX_MMC_DAT_DIR3", 0x0fc, 0, 0, 0, 1)
118MUX_CFG_24XX("G18_24XX_MMC_CMD_DIR", 0x0fd, 0, 0, 0, 1)
119MUX_CFG_24XX("H15_24XX_MMC_CLKI", 0x0fe, 0, 0, 0, 1)
120
107/* Keypad GPIO*/ 121/* Keypad GPIO*/
108MUX_CFG_24XX("T19_24XX_KBR0", 0x106, 3, 1, 1, 1) 122MUX_CFG_24XX("T19_24XX_KBR0", 0x106, 3, 1, 1, 1)
109MUX_CFG_24XX("R19_24XX_KBR1", 0x107, 3, 1, 1, 1) 123MUX_CFG_24XX("R19_24XX_KBR1", 0x107, 3, 1, 1, 1)
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index c2bf57ef6825..90f530540c65 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -19,6 +19,8 @@
19 19
20#include "prcm-regs.h" 20#include "prcm-regs.h"
21 21
22extern void omap2_clk_prepare_for_reboot(void);
23
22u32 omap_prcm_get_reset_sources(void) 24u32 omap_prcm_get_reset_sources(void)
23{ 25{
24 return RM_RSTST_WKUP & 0x7f; 26 return RM_RSTST_WKUP & 0x7f;
@@ -28,12 +30,6 @@ EXPORT_SYMBOL(omap_prcm_get_reset_sources);
28/* Resets clock rates and reboots the system. Only called from system.h */ 30/* Resets clock rates and reboots the system. Only called from system.h */
29void omap_prcm_arch_reset(char mode) 31void omap_prcm_arch_reset(char mode)
30{ 32{
31 u32 rate; 33 omap2_clk_prepare_for_reboot();
32 struct clk *vclk, *sclk;
33
34 vclk = clk_get(NULL, "virt_prcm_set");
35 sclk = clk_get(NULL, "sys_ck");
36 rate = clk_get_rate(sclk);
37 clk_set_rate(vclk, rate); /* go to bypass for OMAP limitation */
38 RM_RSTCTRL_WKUP |= 2; 34 RM_RSTCTRL_WKUP |= 2;
39} 35}
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 7f45c7c3e673..f1179ad4be1b 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -100,6 +100,7 @@ void clk_disable(struct clk *clk)
100 return; 100 return;
101 101
102 spin_lock_irqsave(&clockfw_lock, flags); 102 spin_lock_irqsave(&clockfw_lock, flags);
103 BUG_ON(clk->usecount == 0);
103 if (arch_clock->clk_disable) 104 if (arch_clock->clk_disable)
104 arch_clock->clk_disable(clk); 105 arch_clock->clk_disable(clk);
105 spin_unlock_irqrestore(&clockfw_lock, flags); 106 spin_unlock_irqrestore(&clockfw_lock, flags);
@@ -322,6 +323,31 @@ EXPORT_SYMBOL(clk_allow_idle);
322 323
323/*-------------------------------------------------------------------------*/ 324/*-------------------------------------------------------------------------*/
324 325
326#ifdef CONFIG_OMAP_RESET_CLOCKS
327/*
328 * Disable any unused clocks left on by the bootloader
329 */
330static int __init clk_disable_unused(void)
331{
332 struct clk *ck;
333 unsigned long flags;
334
335 list_for_each_entry(ck, &clocks, node) {
336 if (ck->usecount > 0 || (ck->flags & ALWAYS_ENABLED) ||
337 ck->enable_reg == 0)
338 continue;
339
340 spin_lock_irqsave(&clockfw_lock, flags);
341 if (arch_clock->clk_disable_unused)
342 arch_clock->clk_disable_unused(ck);
343 spin_unlock_irqrestore(&clockfw_lock, flags);
344 }
345
346 return 0;
347}
348late_initcall(clk_disable_unused);
349#endif
350
325int __init clk_init(struct clk_functions * custom_clocks) 351int __init clk_init(struct clk_functions * custom_clocks)
326{ 352{
327 if (!custom_clocks) { 353 if (!custom_clocks) {
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 1812f237d12f..dbc3f44e07a6 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -148,7 +148,7 @@ static inline void omap_init_kp(void) {}
148 148
149#ifdef CONFIG_ARCH_OMAP24XX 149#ifdef CONFIG_ARCH_OMAP24XX
150#define OMAP_MMC1_BASE 0x4809c000 150#define OMAP_MMC1_BASE 0x4809c000
151#define OMAP_MMC1_INT 83 151#define OMAP_MMC1_INT INT_24XX_MMC_IRQ
152#else 152#else
153#define OMAP_MMC1_BASE 0xfffb7800 153#define OMAP_MMC1_BASE 0xfffb7800
154#define OMAP_MMC1_INT INT_MMC 154#define OMAP_MMC1_INT INT_MMC
@@ -225,7 +225,14 @@ static void __init omap_init_mmc(void)
225 /* block 1 is always available and has just one pinout option */ 225 /* block 1 is always available and has just one pinout option */
226 mmc = &mmc_conf->mmc[0]; 226 mmc = &mmc_conf->mmc[0];
227 if (mmc->enabled) { 227 if (mmc->enabled) {
228 if (!cpu_is_omap24xx()) { 228 if (cpu_is_omap24xx()) {
229 omap_cfg_reg(H18_24XX_MMC_CMD);
230 omap_cfg_reg(H15_24XX_MMC_CLKI);
231 omap_cfg_reg(G19_24XX_MMC_CLKO);
232 omap_cfg_reg(F20_24XX_MMC_DAT0);
233 omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
234 omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
235 } else {
229 omap_cfg_reg(MMC_CMD); 236 omap_cfg_reg(MMC_CMD);
230 omap_cfg_reg(MMC_CLK); 237 omap_cfg_reg(MMC_CLK);
231 omap_cfg_reg(MMC_DAT0); 238 omap_cfg_reg(MMC_DAT0);
@@ -236,7 +243,14 @@ static void __init omap_init_mmc(void)
236 } 243 }
237 } 244 }
238 if (mmc->wire4) { 245 if (mmc->wire4) {
239 if (!cpu_is_omap24xx()) { 246 if (cpu_is_omap24xx()) {
247 omap_cfg_reg(H14_24XX_MMC_DAT1);
248 omap_cfg_reg(E19_24XX_MMC_DAT2);
249 omap_cfg_reg(D19_24XX_MMC_DAT3);
250 omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
251 omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
252 omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
253 } else {
240 omap_cfg_reg(MMC_DAT1); 254 omap_cfg_reg(MMC_DAT1);
241 /* NOTE: DAT2 can be on W10 (here) or M15 */ 255 /* NOTE: DAT2 can be on W10 (here) or M15 */
242 if (!mmc->nomux) 256 if (!mmc->nomux)
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 9eddc9507147..1bbb431843ce 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -119,32 +119,41 @@ static void clear_lch_regs(int lch)
119 omap_writew(0, lch_base + i); 119 omap_writew(0, lch_base + i);
120} 120}
121 121
122void omap_set_dma_priority(int dst_port, int priority) 122void omap_set_dma_priority(int lch, int dst_port, int priority)
123{ 123{
124 unsigned long reg; 124 unsigned long reg;
125 u32 l; 125 u32 l;
126 126
127 switch (dst_port) { 127 if (cpu_class_is_omap1()) {
128 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */ 128 switch (dst_port) {
129 reg = OMAP_TC_OCPT1_PRIOR; 129 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
130 break; 130 reg = OMAP_TC_OCPT1_PRIOR;
131 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */ 131 break;
132 reg = OMAP_TC_OCPT2_PRIOR; 132 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
133 break; 133 reg = OMAP_TC_OCPT2_PRIOR;
134 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */ 134 break;
135 reg = OMAP_TC_EMIFF_PRIOR; 135 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
136 break; 136 reg = OMAP_TC_EMIFF_PRIOR;
137 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */ 137 break;
138 reg = OMAP_TC_EMIFS_PRIOR; 138 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
139 break; 139 reg = OMAP_TC_EMIFS_PRIOR;
140 default: 140 break;
141 BUG(); 141 default:
142 return; 142 BUG();
143 return;
144 }
145 l = omap_readl(reg);
146 l &= ~(0xf << 8);
147 l |= (priority & 0xf) << 8;
148 omap_writel(l, reg);
149 }
150
151 if (cpu_is_omap24xx()) {
152 if (priority)
153 OMAP_DMA_CCR_REG(lch) |= (1 << 6);
154 else
155 OMAP_DMA_CCR_REG(lch) &= ~(1 << 6);
143 } 156 }
144 l = omap_readl(reg);
145 l &= ~(0xf << 8);
146 l |= (priority & 0xf) << 8;
147 omap_writel(l, reg);
148} 157}
149 158
150void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, 159void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
@@ -234,6 +243,14 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
234 OMAP1_DMA_LCH_CTRL_REG(lch) = w; 243 OMAP1_DMA_LCH_CTRL_REG(lch) = w;
235} 244}
236 245
246void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
247{
248 if (cpu_is_omap24xx()) {
249 OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16);
250 OMAP_DMA_CSDP_REG(lch) |= (mode << 16);
251 }
252}
253
237/* Note that src_port is only for omap1 */ 254/* Note that src_port is only for omap1 */
238void omap_set_dma_src_params(int lch, int src_port, int src_amode, 255void omap_set_dma_src_params(int lch, int src_port, int src_amode,
239 unsigned long src_start, 256 unsigned long src_start,
@@ -698,6 +715,32 @@ void omap_stop_dma(int lch)
698} 715}
699 716
700/* 717/*
718 * Allows changing the DMA callback function or data. This may be needed if
719 * the driver shares a single DMA channel for multiple dma triggers.
720 */
721int omap_set_dma_callback(int lch,
722 void (* callback)(int lch, u16 ch_status, void *data),
723 void *data)
724{
725 unsigned long flags;
726
727 if (lch < 0)
728 return -ENODEV;
729
730 spin_lock_irqsave(&dma_chan_lock, flags);
731 if (dma_chan[lch].dev_id == -1) {
732 printk(KERN_ERR "DMA callback for not set for free channel\n");
733 spin_unlock_irqrestore(&dma_chan_lock, flags);
734 return -EINVAL;
735 }
736 dma_chan[lch].callback = callback;
737 dma_chan[lch].data = data;
738 spin_unlock_irqrestore(&dma_chan_lock, flags);
739
740 return 0;
741}
742
743/*
701 * Returns current physical source address for the given DMA channel. 744 * Returns current physical source address for the given DMA channel.
702 * If the channel is running the caller must disable interrupts prior calling 745 * If the channel is running the caller must disable interrupts prior calling
703 * this function and process the returned value before re-enabling interrupt to 746 * this function and process the returned value before re-enabling interrupt to
@@ -1339,6 +1382,14 @@ static int __init omap_init_dma(void)
1339 dma_chan_count = 16; 1382 dma_chan_count = 16;
1340 } else 1383 } else
1341 dma_chan_count = 9; 1384 dma_chan_count = 9;
1385 if (cpu_is_omap16xx()) {
1386 u16 w;
1387
1388 /* this would prevent OMAP sleep */
1389 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
1390 w &= ~(1 << 8);
1391 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
1392 }
1342 } else if (cpu_is_omap24xx()) { 1393 } else if (cpu_is_omap24xx()) {
1343 u8 revision = omap_readb(OMAP_DMA4_REVISION); 1394 u8 revision = omap_readb(OMAP_DMA4_REVISION);
1344 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", 1395 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
@@ -1414,11 +1465,13 @@ EXPORT_SYMBOL(omap_request_dma);
1414EXPORT_SYMBOL(omap_free_dma); 1465EXPORT_SYMBOL(omap_free_dma);
1415EXPORT_SYMBOL(omap_start_dma); 1466EXPORT_SYMBOL(omap_start_dma);
1416EXPORT_SYMBOL(omap_stop_dma); 1467EXPORT_SYMBOL(omap_stop_dma);
1468EXPORT_SYMBOL(omap_set_dma_callback);
1417EXPORT_SYMBOL(omap_enable_dma_irq); 1469EXPORT_SYMBOL(omap_enable_dma_irq);
1418EXPORT_SYMBOL(omap_disable_dma_irq); 1470EXPORT_SYMBOL(omap_disable_dma_irq);
1419 1471
1420EXPORT_SYMBOL(omap_set_dma_transfer_params); 1472EXPORT_SYMBOL(omap_set_dma_transfer_params);
1421EXPORT_SYMBOL(omap_set_dma_color_mode); 1473EXPORT_SYMBOL(omap_set_dma_color_mode);
1474EXPORT_SYMBOL(omap_set_dma_write_mode);
1422 1475
1423EXPORT_SYMBOL(omap_set_dma_src_params); 1476EXPORT_SYMBOL(omap_set_dma_src_params);
1424EXPORT_SYMBOL(omap_set_dma_src_index); 1477EXPORT_SYMBOL(omap_set_dma_src_index);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 50524436de63..bcbb8d7392be 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -75,10 +75,14 @@ struct omap_dm_timer {
75#endif 75#endif
76 void __iomem *io_base; 76 void __iomem *io_base;
77 unsigned reserved:1; 77 unsigned reserved:1;
78 unsigned enabled:1;
78}; 79};
79 80
80#ifdef CONFIG_ARCH_OMAP1 81#ifdef CONFIG_ARCH_OMAP1
81 82
83#define omap_dm_clk_enable(x)
84#define omap_dm_clk_disable(x)
85
82static struct omap_dm_timer dm_timers[] = { 86static struct omap_dm_timer dm_timers[] = {
83 { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 }, 87 { .phys_base = 0xfffb1400, .irq = INT_1610_GPTIMER1 },
84 { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 }, 88 { .phys_base = 0xfffb1c00, .irq = INT_1610_GPTIMER2 },
@@ -92,6 +96,9 @@ static struct omap_dm_timer dm_timers[] = {
92 96
93#elif defined(CONFIG_ARCH_OMAP2) 97#elif defined(CONFIG_ARCH_OMAP2)
94 98
99#define omap_dm_clk_enable(x) clk_enable(x)
100#define omap_dm_clk_disable(x) clk_disable(x)
101
95static struct omap_dm_timer dm_timers[] = { 102static struct omap_dm_timer dm_timers[] = {
96 { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 }, 103 { .phys_base = 0x48028000, .irq = INT_24XX_GPTIMER1 },
97 { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 }, 104 { .phys_base = 0x4802a000, .irq = INT_24XX_GPTIMER2 },
@@ -154,24 +161,28 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
154{ 161{
155 u32 l; 162 u32 l;
156 163
157 if (timer != &dm_timers[0]) { 164 if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
158 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); 165 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
159 omap_dm_timer_wait_for_reset(timer); 166 omap_dm_timer_wait_for_reset(timer);
160 } 167 }
161 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_SYS_CLK); 168 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
162 169
163 /* Set to smart-idle mode */ 170 /* Set to smart-idle mode */
164 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG); 171 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
165 l |= 0x02 << 3; 172 l |= 0x02 << 3;
173
174 if (cpu_class_is_omap2() && timer == &dm_timers[0]) {
175 /* Enable wake-up only for GPT1 on OMAP2 CPUs*/
176 l |= 1 << 2;
177 /* Non-posted mode */
178 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0);
179 }
166 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l); 180 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
167} 181}
168 182
169static void omap_dm_timer_prepare(struct omap_dm_timer *timer) 183static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
170{ 184{
171#ifdef CONFIG_ARCH_OMAP2 185 omap_dm_timer_enable(timer);
172 clk_enable(timer->iclk);
173 clk_enable(timer->fclk);
174#endif
175 omap_dm_timer_reset(timer); 186 omap_dm_timer_reset(timer);
176} 187}
177 188
@@ -223,15 +234,36 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
223 234
224void omap_dm_timer_free(struct omap_dm_timer *timer) 235void omap_dm_timer_free(struct omap_dm_timer *timer)
225{ 236{
237 omap_dm_timer_enable(timer);
226 omap_dm_timer_reset(timer); 238 omap_dm_timer_reset(timer);
227#ifdef CONFIG_ARCH_OMAP2 239 omap_dm_timer_disable(timer);
228 clk_disable(timer->iclk); 240
229 clk_disable(timer->fclk);
230#endif
231 WARN_ON(!timer->reserved); 241 WARN_ON(!timer->reserved);
232 timer->reserved = 0; 242 timer->reserved = 0;
233} 243}
234 244
245void omap_dm_timer_enable(struct omap_dm_timer *timer)
246{
247 if (timer->enabled)
248 return;
249
250 omap_dm_clk_enable(timer->fclk);
251 omap_dm_clk_enable(timer->iclk);
252
253 timer->enabled = 1;
254}
255
256void omap_dm_timer_disable(struct omap_dm_timer *timer)
257{
258 if (!timer->enabled)
259 return;
260
261 omap_dm_clk_disable(timer->iclk);
262 omap_dm_clk_disable(timer->fclk);
263
264 timer->enabled = 0;
265}
266
235int omap_dm_timer_get_irq(struct omap_dm_timer *timer) 267int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
236{ 268{
237 return timer->irq; 269 return timer->irq;
@@ -276,7 +308,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
276 308
277struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) 309struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
278{ 310{
279 return timer->fclk; 311 return timer->fclk;
280} 312}
281 313
282__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) 314__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
@@ -406,11 +438,16 @@ void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
406 unsigned int value) 438 unsigned int value)
407{ 439{
408 omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value); 440 omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
441 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
409} 442}
410 443
411unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) 444unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
412{ 445{
413 return omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG); 446 unsigned int l;
447
448 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_STAT_REG);
449
450 return l;
414} 451}
415 452
416void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) 453void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
@@ -420,12 +457,16 @@ void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
420 457
421unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) 458unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
422{ 459{
423 return omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG); 460 unsigned int l;
461
462 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
463
464 return l;
424} 465}
425 466
426void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) 467void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
427{ 468{
428 return omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); 469 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value);
429} 470}
430 471
431int omap_dm_timers_active(void) 472int omap_dm_timers_active(void)
@@ -436,9 +477,14 @@ int omap_dm_timers_active(void)
436 struct omap_dm_timer *timer; 477 struct omap_dm_timer *timer;
437 478
438 timer = &dm_timers[i]; 479 timer = &dm_timers[i];
480
481 if (!timer->enabled)
482 continue;
483
439 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) & 484 if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
440 OMAP_TIMER_CTRL_ST) 485 OMAP_TIMER_CTRL_ST) {
441 return 1; 486 return 1;
487 }
442 } 488 }
443 return 0; 489 return 0;
444} 490}
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index cd7f973fb286..f55f99ae58ae 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -94,6 +94,8 @@
94#define OMAP24XX_GPIO_SYSCONFIG 0x0010 94#define OMAP24XX_GPIO_SYSCONFIG 0x0010
95#define OMAP24XX_GPIO_SYSSTATUS 0x0014 95#define OMAP24XX_GPIO_SYSSTATUS 0x0014
96#define OMAP24XX_GPIO_IRQSTATUS1 0x0018 96#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
97#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
98#define OMAP24XX_GPIO_IRQENABLE2 0x002c
97#define OMAP24XX_GPIO_IRQENABLE1 0x001c 99#define OMAP24XX_GPIO_IRQENABLE1 0x001c
98#define OMAP24XX_GPIO_CTRL 0x0030 100#define OMAP24XX_GPIO_CTRL 0x0030
99#define OMAP24XX_GPIO_OE 0x0034 101#define OMAP24XX_GPIO_OE 0x0034
@@ -110,8 +112,6 @@
110#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 112#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
111#define OMAP24XX_GPIO_SETDATAOUT 0x0094 113#define OMAP24XX_GPIO_SETDATAOUT 0x0094
112 114
113#define OMAP_MPUIO_MASK (~OMAP_MAX_GPIO_LINES & 0xff)
114
115struct gpio_bank { 115struct gpio_bank {
116 void __iomem *base; 116 void __iomem *base;
117 u16 irq; 117 u16 irq;
@@ -216,11 +216,13 @@ static inline int gpio_valid(int gpio)
216{ 216{
217 if (gpio < 0) 217 if (gpio < 0)
218 return -1; 218 return -1;
219#ifndef CONFIG_ARCH_OMAP24XX
219 if (OMAP_GPIO_IS_MPUIO(gpio)) { 220 if (OMAP_GPIO_IS_MPUIO(gpio)) {
220 if ((gpio & OMAP_MPUIO_MASK) > 16) 221 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
221 return -1; 222 return -1;
222 return 0; 223 return 0;
223 } 224 }
225#endif
224#ifdef CONFIG_ARCH_OMAP15XX 226#ifdef CONFIG_ARCH_OMAP15XX
225 if (cpu_is_omap15xx() && gpio < 16) 227 if (cpu_is_omap15xx() && gpio < 16)
226 return 0; 228 return 0;
@@ -529,6 +531,10 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
529 return; 531 return;
530 } 532 }
531 __raw_writel(gpio_mask, reg); 533 __raw_writel(gpio_mask, reg);
534
535 /* Workaround for clearing DSP GPIO interrupts to allow retention */
536 if (cpu_is_omap2420())
537 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
532} 538}
533 539
534static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) 540static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
@@ -662,6 +668,14 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
662 } 668 }
663} 669}
664 670
671static void _reset_gpio(struct gpio_bank *bank, int gpio)
672{
673 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
674 _set_gpio_irqenable(bank, gpio, 0);
675 _clear_gpio_irqstatus(bank, gpio);
676 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
677}
678
665/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ 679/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
666static int gpio_wake_enable(unsigned int irq, unsigned int enable) 680static int gpio_wake_enable(unsigned int irq, unsigned int enable)
667{ 681{
@@ -672,9 +686,7 @@ static int gpio_wake_enable(unsigned int irq, unsigned int enable)
672 if (check_gpio(gpio) < 0) 686 if (check_gpio(gpio) < 0)
673 return -ENODEV; 687 return -ENODEV;
674 bank = get_gpio_bank(gpio); 688 bank = get_gpio_bank(gpio);
675 spin_lock(&bank->lock);
676 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable); 689 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
677 spin_unlock(&bank->lock);
678 690
679 return retval; 691 return retval;
680} 692}
@@ -696,7 +708,9 @@ int omap_request_gpio(int gpio)
696 } 708 }
697 bank->reserved_map |= (1 << get_gpio_index(gpio)); 709 bank->reserved_map |= (1 << get_gpio_index(gpio));
698 710
699 /* Set trigger to none. You need to enable the trigger after request_irq */ 711 /* Set trigger to none. You need to enable the desired trigger with
712 * request_irq() or set_irq_type().
713 */
700 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE); 714 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
701 715
702#ifdef CONFIG_ARCH_OMAP15XX 716#ifdef CONFIG_ARCH_OMAP15XX
@@ -756,9 +770,7 @@ void omap_free_gpio(int gpio)
756 } 770 }
757#endif 771#endif
758 bank->reserved_map &= ~(1 << get_gpio_index(gpio)); 772 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
759 _set_gpio_direction(bank, get_gpio_index(gpio), 1); 773 _reset_gpio(bank, gpio);
760 _set_gpio_irqenable(bank, gpio, 0);
761 _clear_gpio_irqstatus(bank, gpio);
762 spin_unlock(&bank->lock); 774 spin_unlock(&bank->lock);
763} 775}
764 776
@@ -898,6 +910,14 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
898 910
899} 911}
900 912
913static void gpio_irq_shutdown(unsigned int irq)
914{
915 unsigned int gpio = irq - IH_GPIO_BASE;
916 struct gpio_bank *bank = get_gpio_bank(gpio);
917
918 _reset_gpio(bank, gpio);
919}
920
901static void gpio_ack_irq(unsigned int irq) 921static void gpio_ack_irq(unsigned int irq)
902{ 922{
903 unsigned int gpio = irq - IH_GPIO_BASE; 923 unsigned int gpio = irq - IH_GPIO_BASE;
@@ -946,6 +966,7 @@ static void mpuio_unmask_irq(unsigned int irq)
946 966
947static struct irq_chip gpio_irq_chip = { 967static struct irq_chip gpio_irq_chip = {
948 .name = "GPIO", 968 .name = "GPIO",
969 .shutdown = gpio_irq_shutdown,
949 .ack = gpio_ack_irq, 970 .ack = gpio_ack_irq,
950 .mask = gpio_mask_irq, 971 .mask = gpio_mask_irq,
951 .unmask = gpio_unmask_irq, 972 .unmask = gpio_unmask_irq,
@@ -985,7 +1006,7 @@ static int __init _omap_gpio_init(void)
985 else 1006 else
986 clk_enable(gpio_ick); 1007 clk_enable(gpio_ick);
987 gpio_fck = clk_get(NULL, "gpios_fck"); 1008 gpio_fck = clk_get(NULL, "gpios_fck");
988 if (IS_ERR(gpio_ick)) 1009 if (IS_ERR(gpio_fck))
989 printk("Could not get gpios_fck\n"); 1010 printk("Could not get gpios_fck\n");
990 else 1011 else
991 clk_enable(gpio_fck); 1012 clk_enable(gpio_fck);
@@ -1144,8 +1165,8 @@ static int omap_gpio_resume(struct sys_device *dev)
1144 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1165 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1145 break; 1166 break;
1146 case METHOD_GPIO_24XX: 1167 case METHOD_GPIO_24XX:
1147 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; 1168 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1148 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1169 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1149 break; 1170 break;
1150 default: 1171 default:
1151 continue; 1172 continue;
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 196aac3ac329..ade9a0fa6ef6 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -75,8 +75,6 @@ static struct clk *mcbsp1_ick = 0;
75static struct clk *mcbsp1_fck = 0; 75static struct clk *mcbsp1_fck = 0;
76static struct clk *mcbsp2_ick = 0; 76static struct clk *mcbsp2_ick = 0;
77static struct clk *mcbsp2_fck = 0; 77static struct clk *mcbsp2_fck = 0;
78static struct clk *sys_ck = 0;
79static struct clk *sys_clkout = 0;
80#endif 78#endif
81 79
82static void omap_mcbsp_dump_reg(u8 id) 80static void omap_mcbsp_dump_reg(u8 id)
@@ -232,7 +230,6 @@ static void omap2_mcbsp2_mux_setup(void)
232 omap_cfg_reg(W15_24XX_MCBSP2_DR); 230 omap_cfg_reg(W15_24XX_MCBSP2_DR);
233 omap_cfg_reg(V15_24XX_MCBSP2_DX); 231 omap_cfg_reg(V15_24XX_MCBSP2_DX);
234 omap_cfg_reg(V14_24XX_GPIO117); 232 omap_cfg_reg(V14_24XX_GPIO117);
235 omap_cfg_reg(W14_24XX_SYS_CLKOUT);
236} 233}
237#endif 234#endif
238 235
@@ -984,13 +981,7 @@ static int __init omap_mcbsp_init(void)
984 if (cpu_is_omap24xx()) { 981 if (cpu_is_omap24xx()) {
985 mcbsp_info = mcbsp_24xx; 982 mcbsp_info = mcbsp_24xx;
986 mcbsp_count = ARRAY_SIZE(mcbsp_24xx); 983 mcbsp_count = ARRAY_SIZE(mcbsp_24xx);
987
988 /* REVISIT: where's the right place? */
989 omap2_mcbsp2_mux_setup(); 984 omap2_mcbsp2_mux_setup();
990 sys_ck = clk_get(0, "sys_ck");
991 sys_clkout = clk_get(0, "sys_clkout");
992 clk_set_parent(sys_clkout, sys_ck);
993 clk_enable(sys_clkout);
994 } 985 }
995#endif 986#endif
996 for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) { 987 for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
diff --git a/arch/arm/plat-omap/pm.c b/arch/arm/plat-omap/pm.c
deleted file mode 100644
index 04b4102727a8..000000000000
--- a/arch/arm/plat-omap/pm.c
+++ /dev/null
@@ -1,670 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/pm.c
3 *
4 * OMAP Power Management Routines
5 *
6 * Original code for the SA11x0:
7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
8 *
9 * Modified for the PXA250 by Nicolas Pitre:
10 * Copyright (c) 2002 Monta Vista Software, Inc.
11 *
12 * Modified for the OMAP1510 by David Singleton:
13 * Copyright (c) 2002 Monta Vista Software, Inc.
14 *
15 * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
16 *
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
21 *
22 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * You should have received a copy of the GNU General Public License along
34 * with this program; if not, write to the Free Software Foundation, Inc.,
35 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 */
37
38#include <linux/pm.h>
39#include <linux/sched.h>
40#include <linux/proc_fs.h>
41#include <linux/pm.h>
42#include <linux/interrupt.h>
43
44#include <asm/io.h>
45#include <asm/irq.h>
46#include <asm/mach/time.h>
47#include <asm/mach/irq.h>
48
49#include <asm/mach-types.h>
50#include <asm/arch/irqs.h>
51#include <asm/arch/tc.h>
52#include <asm/arch/pm.h>
53#include <asm/arch/mux.h>
54#include <asm/arch/tps65010.h>
55#include <asm/arch/dsp_common.h>
56
57#include <asm/arch/clock.h>
58#include <asm/arch/sram.h>
59
60static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
61static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
62static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
63static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
64static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
65
66static void (*omap_sram_idle)(void) = NULL;
67static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
68
69/*
70 * Let's power down on idle, but only if we are really
71 * idle, because once we start down the path of
72 * going idle we continue to do idle even if we get
73 * a clock tick interrupt . .
74 */
75void omap_pm_idle(void)
76{
77 unsigned int mask32 = 0;
78
79 /*
80 * If the DSP is being used let's just idle the CPU, the overhead
81 * to wake up from Big Sleep is big, milliseconds versus micro
82 * seconds for wait for interrupt.
83 */
84
85 local_irq_disable();
86 local_fiq_disable();
87 if (need_resched()) {
88 local_fiq_enable();
89 local_irq_enable();
90 return;
91 }
92 mask32 = omap_readl(ARM_SYSST);
93
94 /*
95 * Prevent the ULPD from entering low power state by setting
96 * POWER_CTRL_REG:4 = 0
97 */
98 omap_writew(omap_readw(ULPD_POWER_CTRL) &
99 ~ULPD_DEEP_SLEEP_TRANSITION_EN, ULPD_POWER_CTRL);
100
101 /*
102 * Since an interrupt may set up a timer, we don't want to
103 * reprogram the hardware timer with interrupts enabled.
104 * Re-enable interrupts only after returning from idle.
105 */
106 timer_dyn_reprogram();
107
108 if ((mask32 & DSP_IDLE) == 0) {
109 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4");
110 } else
111 omap_sram_idle();
112
113 local_fiq_enable();
114 local_irq_enable();
115}
116
117/*
118 * Configuration of the wakeup event is board specific. For the
119 * moment we put it into this helper function. Later it may move
120 * to board specific files.
121 */
122static void omap_pm_wakeup_setup(void)
123{
124 u32 level1_wake = 0;
125 u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
126
127 /*
128 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
129 * and the L2 wakeup interrupts: keypad and UART2. Note that the
130 * drivers must still separately call omap_set_gpio_wakeup() to
131 * wake up to a GPIO interrupt.
132 */
133 if (cpu_is_omap730())
134 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
135 OMAP_IRQ_BIT(INT_730_IH2_IRQ);
136 else if (cpu_is_omap1510())
137 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
138 OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
139 else if (cpu_is_omap16xx())
140 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
141 OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
142
143 omap_writel(~level1_wake, OMAP_IH1_MIR);
144
145 if (cpu_is_omap730()) {
146 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
147 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) | OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)), OMAP_IH2_1_MIR);
148 } else if (cpu_is_omap1510()) {
149 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
150 omap_writel(~level2_wake, OMAP_IH2_MIR);
151 } else if (cpu_is_omap16xx()) {
152 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
153 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
154
155 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
156 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ), OMAP_IH2_1_MIR);
157 omap_writel(~0x0, OMAP_IH2_2_MIR);
158 omap_writel(~0x0, OMAP_IH2_3_MIR);
159 }
160
161 /* New IRQ agreement, recalculate in cascade order */
162 omap_writel(1, OMAP_IH2_CONTROL);
163 omap_writel(1, OMAP_IH1_CONTROL);
164}
165
166void omap_pm_suspend(void)
167{
168 unsigned long arg0 = 0, arg1 = 0;
169
170 printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev);
171
172 omap_serial_wake_trigger(1);
173
174 if (machine_is_omap_osk()) {
175 /* Stop LED1 (D9) blink */
176 tps65010_set_led(LED1, OFF);
177 }
178
179 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
180
181 /*
182 * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
183 */
184
185 local_irq_disable();
186 local_fiq_disable();
187
188 /*
189 * Step 2: save registers
190 *
191 * The omap is a strange/beautiful device. The caches, memory
192 * and register state are preserved across power saves.
193 * We have to save and restore very little register state to
194 * idle the omap.
195 *
196 * Save interrupt, MPUI, ARM and UPLD control registers.
197 */
198
199 if (cpu_is_omap730()) {
200 MPUI730_SAVE(OMAP_IH1_MIR);
201 MPUI730_SAVE(OMAP_IH2_0_MIR);
202 MPUI730_SAVE(OMAP_IH2_1_MIR);
203 MPUI730_SAVE(MPUI_CTRL);
204 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
205 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
206 MPUI730_SAVE(EMIFS_CONFIG);
207 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
208
209 } else if (cpu_is_omap1510()) {
210 MPUI1510_SAVE(OMAP_IH1_MIR);
211 MPUI1510_SAVE(OMAP_IH2_MIR);
212 MPUI1510_SAVE(MPUI_CTRL);
213 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
214 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
215 MPUI1510_SAVE(EMIFS_CONFIG);
216 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
217 } else if (cpu_is_omap16xx()) {
218 MPUI1610_SAVE(OMAP_IH1_MIR);
219 MPUI1610_SAVE(OMAP_IH2_0_MIR);
220 MPUI1610_SAVE(OMAP_IH2_1_MIR);
221 MPUI1610_SAVE(OMAP_IH2_2_MIR);
222 MPUI1610_SAVE(OMAP_IH2_3_MIR);
223 MPUI1610_SAVE(MPUI_CTRL);
224 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
225 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
226 MPUI1610_SAVE(EMIFS_CONFIG);
227 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
228 }
229
230 ARM_SAVE(ARM_CKCTL);
231 ARM_SAVE(ARM_IDLECT1);
232 ARM_SAVE(ARM_IDLECT2);
233 if (!(cpu_is_omap1510()))
234 ARM_SAVE(ARM_IDLECT3);
235 ARM_SAVE(ARM_EWUPCT);
236 ARM_SAVE(ARM_RSTCT1);
237 ARM_SAVE(ARM_RSTCT2);
238 ARM_SAVE(ARM_SYSST);
239 ULPD_SAVE(ULPD_CLOCK_CTRL);
240 ULPD_SAVE(ULPD_STATUS_REQ);
241
242 /* (Step 3 removed - we now allow deep sleep by default) */
243
244 /*
245 * Step 4: OMAP DSP Shutdown
246 */
247
248
249 /*
250 * Step 5: Wakeup Event Setup
251 */
252
253 omap_pm_wakeup_setup();
254
255 /*
256 * Step 6: ARM and Traffic controller shutdown
257 */
258
259 /* disable ARM watchdog */
260 omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
261 omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
262
263 /*
264 * Step 6b: ARM and Traffic controller shutdown
265 *
266 * Step 6 continues here. Prepare jump to power management
267 * assembly code in internal SRAM.
268 *
269 * Since the omap_cpu_suspend routine has been copied to
270 * SRAM, we'll do an indirect procedure call to it and pass the
271 * contents of arm_idlect1 and arm_idlect2 so it can restore
272 * them when it wakes up and it will return.
273 */
274
275 arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
276 arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
277
278 /*
279 * Step 6c: ARM and Traffic controller shutdown
280 *
281 * Jump to assembly code. The processor will stay there
282 * until wake up.
283 */
284 omap_sram_suspend(arg0, arg1);
285
286 /*
287 * If we are here, processor is woken up!
288 */
289
290 /*
291 * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
292 */
293
294 if (!(cpu_is_omap1510()))
295 ARM_RESTORE(ARM_IDLECT3);
296 ARM_RESTORE(ARM_CKCTL);
297 ARM_RESTORE(ARM_EWUPCT);
298 ARM_RESTORE(ARM_RSTCT1);
299 ARM_RESTORE(ARM_RSTCT2);
300 ARM_RESTORE(ARM_SYSST);
301 ULPD_RESTORE(ULPD_CLOCK_CTRL);
302 ULPD_RESTORE(ULPD_STATUS_REQ);
303
304 if (cpu_is_omap730()) {
305 MPUI730_RESTORE(EMIFS_CONFIG);
306 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
307 MPUI730_RESTORE(OMAP_IH1_MIR);
308 MPUI730_RESTORE(OMAP_IH2_0_MIR);
309 MPUI730_RESTORE(OMAP_IH2_1_MIR);
310 } else if (cpu_is_omap1510()) {
311 MPUI1510_RESTORE(MPUI_CTRL);
312 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
313 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
314 MPUI1510_RESTORE(EMIFS_CONFIG);
315 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
316 MPUI1510_RESTORE(OMAP_IH1_MIR);
317 MPUI1510_RESTORE(OMAP_IH2_MIR);
318 } else if (cpu_is_omap16xx()) {
319 MPUI1610_RESTORE(MPUI_CTRL);
320 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
321 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
322 MPUI1610_RESTORE(EMIFS_CONFIG);
323 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
324
325 MPUI1610_RESTORE(OMAP_IH1_MIR);
326 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
327 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
328 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
329 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
330 }
331
332 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
333
334 /*
335 * Reenable interrupts
336 */
337
338 local_irq_enable();
339 local_fiq_enable();
340
341 omap_serial_wake_trigger(0);
342
343 printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev);
344
345 if (machine_is_omap_osk()) {
346 /* Let LED1 (D9) blink again */
347 tps65010_set_led(LED1, BLINK);
348 }
349}
350
351#if defined(DEBUG) && defined(CONFIG_PROC_FS)
352static int g_read_completed;
353
354/*
355 * Read system PM registers for debugging
356 */
357static int omap_pm_read_proc(
358 char *page_buffer,
359 char **my_first_byte,
360 off_t virtual_start,
361 int length,
362 int *eof,
363 void *data)
364{
365 int my_buffer_offset = 0;
366 char * const my_base = page_buffer;
367
368 ARM_SAVE(ARM_CKCTL);
369 ARM_SAVE(ARM_IDLECT1);
370 ARM_SAVE(ARM_IDLECT2);
371 if (!(cpu_is_omap1510()))
372 ARM_SAVE(ARM_IDLECT3);
373 ARM_SAVE(ARM_EWUPCT);
374 ARM_SAVE(ARM_RSTCT1);
375 ARM_SAVE(ARM_RSTCT2);
376 ARM_SAVE(ARM_SYSST);
377
378 ULPD_SAVE(ULPD_IT_STATUS);
379 ULPD_SAVE(ULPD_CLOCK_CTRL);
380 ULPD_SAVE(ULPD_SOFT_REQ);
381 ULPD_SAVE(ULPD_STATUS_REQ);
382 ULPD_SAVE(ULPD_DPLL_CTRL);
383 ULPD_SAVE(ULPD_POWER_CTRL);
384
385 if (cpu_is_omap730()) {
386 MPUI730_SAVE(MPUI_CTRL);
387 MPUI730_SAVE(MPUI_DSP_STATUS);
388 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
389 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
390 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
391 MPUI730_SAVE(EMIFS_CONFIG);
392 } else if (cpu_is_omap1510()) {
393 MPUI1510_SAVE(MPUI_CTRL);
394 MPUI1510_SAVE(MPUI_DSP_STATUS);
395 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
396 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
397 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
398 MPUI1510_SAVE(EMIFS_CONFIG);
399 } else if (cpu_is_omap16xx()) {
400 MPUI1610_SAVE(MPUI_CTRL);
401 MPUI1610_SAVE(MPUI_DSP_STATUS);
402 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
403 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
404 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
405 MPUI1610_SAVE(EMIFS_CONFIG);
406 }
407
408 if (virtual_start == 0) {
409 g_read_completed = 0;
410
411 my_buffer_offset += sprintf(my_base + my_buffer_offset,
412 "ARM_CKCTL_REG: 0x%-8x \n"
413 "ARM_IDLECT1_REG: 0x%-8x \n"
414 "ARM_IDLECT2_REG: 0x%-8x \n"
415 "ARM_IDLECT3_REG: 0x%-8x \n"
416 "ARM_EWUPCT_REG: 0x%-8x \n"
417 "ARM_RSTCT1_REG: 0x%-8x \n"
418 "ARM_RSTCT2_REG: 0x%-8x \n"
419 "ARM_SYSST_REG: 0x%-8x \n"
420 "ULPD_IT_STATUS_REG: 0x%-4x \n"
421 "ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
422 "ULPD_SOFT_REQ_REG: 0x%-4x \n"
423 "ULPD_DPLL_CTRL_REG: 0x%-4x \n"
424 "ULPD_STATUS_REQ_REG: 0x%-4x \n"
425 "ULPD_POWER_CTRL_REG: 0x%-4x \n",
426 ARM_SHOW(ARM_CKCTL),
427 ARM_SHOW(ARM_IDLECT1),
428 ARM_SHOW(ARM_IDLECT2),
429 ARM_SHOW(ARM_IDLECT3),
430 ARM_SHOW(ARM_EWUPCT),
431 ARM_SHOW(ARM_RSTCT1),
432 ARM_SHOW(ARM_RSTCT2),
433 ARM_SHOW(ARM_SYSST),
434 ULPD_SHOW(ULPD_IT_STATUS),
435 ULPD_SHOW(ULPD_CLOCK_CTRL),
436 ULPD_SHOW(ULPD_SOFT_REQ),
437 ULPD_SHOW(ULPD_DPLL_CTRL),
438 ULPD_SHOW(ULPD_STATUS_REQ),
439 ULPD_SHOW(ULPD_POWER_CTRL));
440
441 if (cpu_is_omap730()) {
442 my_buffer_offset += sprintf(my_base + my_buffer_offset,
443 "MPUI730_CTRL_REG 0x%-8x \n"
444 "MPUI730_DSP_STATUS_REG: 0x%-8x \n"
445 "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
446 "MPUI730_DSP_API_CONFIG_REG: 0x%-8x \n"
447 "MPUI730_SDRAM_CONFIG_REG: 0x%-8x \n"
448 "MPUI730_EMIFS_CONFIG_REG: 0x%-8x \n",
449 MPUI730_SHOW(MPUI_CTRL),
450 MPUI730_SHOW(MPUI_DSP_STATUS),
451 MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
452 MPUI730_SHOW(MPUI_DSP_API_CONFIG),
453 MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
454 MPUI730_SHOW(EMIFS_CONFIG));
455 } else if (cpu_is_omap1510()) {
456 my_buffer_offset += sprintf(my_base + my_buffer_offset,
457 "MPUI1510_CTRL_REG 0x%-8x \n"
458 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
459 "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
460 "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
461 "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
462 "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
463 MPUI1510_SHOW(MPUI_CTRL),
464 MPUI1510_SHOW(MPUI_DSP_STATUS),
465 MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
466 MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
467 MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
468 MPUI1510_SHOW(EMIFS_CONFIG));
469 } else if (cpu_is_omap16xx()) {
470 my_buffer_offset += sprintf(my_base + my_buffer_offset,
471 "MPUI1610_CTRL_REG 0x%-8x \n"
472 "MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
473 "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
474 "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
475 "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
476 "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
477 MPUI1610_SHOW(MPUI_CTRL),
478 MPUI1610_SHOW(MPUI_DSP_STATUS),
479 MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
480 MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
481 MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
482 MPUI1610_SHOW(EMIFS_CONFIG));
483 }
484
485 g_read_completed++;
486 } else if (g_read_completed >= 1) {
487 *eof = 1;
488 return 0;
489 }
490 g_read_completed++;
491
492 *my_first_byte = page_buffer;
493 return my_buffer_offset;
494}
495
496static void omap_pm_init_proc(void)
497{
498 struct proc_dir_entry *entry;
499
500 entry = create_proc_read_entry("driver/omap_pm",
501 S_IWUSR | S_IRUGO, NULL,
502 omap_pm_read_proc, NULL);
503}
504
505#endif /* DEBUG && CONFIG_PROC_FS */
506
507/*
508 * omap_pm_prepare - Do preliminary suspend work.
509 * @state: suspend state we're entering.
510 *
511 */
512//#include <asm/hardware.h>
513
514static int omap_pm_prepare(suspend_state_t state)
515{
516 int error = 0;
517
518 switch (state)
519 {
520 case PM_SUSPEND_STANDBY:
521 case PM_SUSPEND_MEM:
522 break;
523
524 case PM_SUSPEND_DISK:
525 return -ENOTSUPP;
526
527 default:
528 return -EINVAL;
529 }
530
531 return error;
532}
533
534
535/*
536 * omap_pm_enter - Actually enter a sleep state.
537 * @state: State we're entering.
538 *
539 */
540
541static int omap_pm_enter(suspend_state_t state)
542{
543 switch (state)
544 {
545 case PM_SUSPEND_STANDBY:
546 case PM_SUSPEND_MEM:
547 omap_pm_suspend();
548 break;
549
550 case PM_SUSPEND_DISK:
551 return -ENOTSUPP;
552
553 default:
554 return -EINVAL;
555 }
556
557 return 0;
558}
559
560
561/**
562 * omap_pm_finish - Finish up suspend sequence.
563 * @state: State we're coming out of.
564 *
565 * This is called after we wake back up (or if entering the sleep state
566 * failed).
567 */
568
569static int omap_pm_finish(suspend_state_t state)
570{
571 return 0;
572}
573
574
575static irqreturn_t omap_wakeup_interrupt(int irq, void * dev,
576 struct pt_regs * regs)
577{
578 return IRQ_HANDLED;
579}
580
581static struct irqaction omap_wakeup_irq = {
582 .name = "peripheral wakeup",
583 .flags = IRQF_DISABLED,
584 .handler = omap_wakeup_interrupt
585};
586
587
588
589static struct pm_ops omap_pm_ops ={
590 .pm_disk_mode = 0,
591 .prepare = omap_pm_prepare,
592 .enter = omap_pm_enter,
593 .finish = omap_pm_finish,
594};
595
596static int __init omap_pm_init(void)
597{
598 printk("Power Management for TI OMAP.\n");
599 /*
600 * We copy the assembler sleep/wakeup routines to SRAM.
601 * These routines need to be in SRAM as that's the only
602 * memory the MPU can see when it wakes up.
603 */
604 if (cpu_is_omap730()) {
605 omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend,
606 omap730_idle_loop_suspend_sz);
607 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
608 omap730_cpu_suspend_sz);
609 } else if (cpu_is_omap1510()) {
610 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend,
611 omap1510_idle_loop_suspend_sz);
612 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
613 omap1510_cpu_suspend_sz);
614 } else if (cpu_is_omap16xx()) {
615 omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend,
616 omap1610_idle_loop_suspend_sz);
617 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
618 omap1610_cpu_suspend_sz);
619 }
620
621 if (omap_sram_idle == NULL || omap_sram_suspend == NULL) {
622 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
623 return -ENODEV;
624 }
625
626 pm_idle = omap_pm_idle;
627
628 if (cpu_is_omap730())
629 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
630 else if (cpu_is_omap16xx())
631 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
632
633#if 0
634 /* --- BEGIN BOARD-DEPENDENT CODE --- */
635 /* Sleepx mask direction */
636 omap_writew((omap_readw(0xfffb5008) & ~2), 0xfffb5008);
637 /* Unmask sleepx signal */
638 omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
639 /* --- END BOARD-DEPENDENT CODE --- */
640#endif
641
642 /* Program new power ramp-up time
643 * (0 for most boards since we don't lower voltage when in deep sleep)
644 */
645 omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
646
647 /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
648 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
649
650 /* Configure IDLECT3 */
651 if (cpu_is_omap730())
652 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
653 else if (cpu_is_omap16xx())
654 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
655
656 pm_set_ops(&omap_pm_ops);
657
658#if defined(DEBUG) && defined(CONFIG_PROC_FS)
659 omap_pm_init_proc();
660#endif
661
662 if (cpu_is_omap16xx()) {
663 /* configure LOW_PWR pin */
664 omap_cfg_reg(T20_1610_LOW_PWR);
665 }
666
667 return 0;
668}
669__initcall(omap_pm_init);
670
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index e75718301b0f..19014b2ff4c6 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -174,10 +174,7 @@ void __init omap_map_sram(void)
174 if (cpu_is_omap24xx()) { 174 if (cpu_is_omap24xx()) {
175 omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA; 175 omap_sram_io_desc[0].virtual = OMAP2_SRAM_VA;
176 176
177 if (is_sram_locked()) 177 base = OMAP2_SRAM_PA;
178 base = OMAP2_SRAM_PUB_PA;
179 else
180 base = OMAP2_SRAM_PA;
181 base = ROUND_DOWN(base, PAGE_SIZE); 178 base = ROUND_DOWN(base, PAGE_SIZE);
182 omap_sram_io_desc[0].pfn = __phys_to_pfn(base); 179 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
183 } 180 }
diff --git a/arch/arm/plat-omap/timer32k.c b/arch/arm/plat-omap/timer32k.c
index 281ecc7fcdfc..cf6df3378d37 100644
--- a/arch/arm/plat-omap/timer32k.c
+++ b/arch/arm/plat-omap/timer32k.c
@@ -105,6 +105,8 @@ static inline unsigned long omap_32k_timer_read(int reg)
105 105
106static inline void omap_32k_timer_start(unsigned long load_val) 106static inline void omap_32k_timer_start(unsigned long load_val)
107{ 107{
108 if (!load_val)
109 load_val = 1;
108 omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR); 110 omap_32k_timer_write(load_val, OMAP1_32K_TIMER_TVR);
109 omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR); 111 omap_32k_timer_write(0x0f, OMAP1_32K_TIMER_CR);
110} 112}
@@ -192,14 +194,11 @@ unsigned long long sched_clock(void)
192 * issues with dynamic tick. In the dynamic tick case, we need to lock 194 * issues with dynamic tick. In the dynamic tick case, we need to lock
193 * with irqsave. 195 * with irqsave.
194 */ 196 */
195static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id, 197static inline irqreturn_t _omap_32k_timer_interrupt(int irq, void *dev_id,
196 struct pt_regs *regs) 198 struct pt_regs *regs)
197{ 199{
198 unsigned long flags;
199 unsigned long now; 200 unsigned long now;
200 201
201 write_seqlock_irqsave(&xtime_lock, flags);
202
203 omap_32k_timer_ack_irq(); 202 omap_32k_timer_ack_irq();
204 now = omap_32k_sync_timer_read(); 203 now = omap_32k_sync_timer_read();
205 204
@@ -215,6 +214,23 @@ static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
215 * continuous timer can be overridden from pm_idle to be longer. 214 * continuous timer can be overridden from pm_idle to be longer.
216 */ 215 */
217 omap_32k_timer_start(omap_32k_last_tick + OMAP_32K_TICKS_PER_HZ - now); 216 omap_32k_timer_start(omap_32k_last_tick + OMAP_32K_TICKS_PER_HZ - now);
217
218 return IRQ_HANDLED;
219}
220
221static irqreturn_t omap_32k_timer_handler(int irq, void *dev_id,
222 struct pt_regs *regs)
223{
224 return _omap_32k_timer_interrupt(irq, dev_id, regs);
225}
226
227static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
228 struct pt_regs *regs)
229{
230 unsigned long flags;
231
232 write_seqlock_irqsave(&xtime_lock, flags);
233 _omap_32k_timer_interrupt(irq, dev_id, regs);
218 write_sequnlock_irqrestore(&xtime_lock, flags); 234 write_sequnlock_irqrestore(&xtime_lock, flags);
219 235
220 return IRQ_HANDLED; 236 return IRQ_HANDLED;
@@ -230,7 +246,15 @@ static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
230 */ 246 */
231void omap_32k_timer_reprogram(unsigned long next_tick) 247void omap_32k_timer_reprogram(unsigned long next_tick)
232{ 248{
233 omap_32k_timer_start(JIFFIES_TO_HW_TICKS(next_tick, 32768) + 1); 249 unsigned long ticks = JIFFIES_TO_HW_TICKS(next_tick, 32768) + 1;
250 unsigned long now = omap_32k_sync_timer_read();
251 unsigned long idled = now - omap_32k_last_tick;
252
253 if (idled + 1 < ticks)
254 ticks -= idled;
255 else
256 ticks = 1;
257 omap_32k_timer_start(ticks);
234} 258}
235 259
236static struct irqaction omap_32k_timer_irq; 260static struct irqaction omap_32k_timer_irq;
@@ -252,7 +276,7 @@ static struct dyn_tick_timer omap_dyn_tick_timer = {
252 .enable = omap_32k_timer_enable_dyn_tick, 276 .enable = omap_32k_timer_enable_dyn_tick,
253 .disable = omap_32k_timer_disable_dyn_tick, 277 .disable = omap_32k_timer_disable_dyn_tick,
254 .reprogram = omap_32k_timer_reprogram, 278 .reprogram = omap_32k_timer_reprogram,
255 .handler = omap_32k_timer_interrupt, 279 .handler = omap_32k_timer_handler,
256}; 280};
257#endif /* CONFIG_NO_IDLE_HZ */ 281#endif /* CONFIG_NO_IDLE_HZ */
258 282
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-23 12:30:08 -0500