diff options
author | Dan Williams <dan.j.williams@intel.com> | 2007-06-06 12:51:21 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-07-12 06:11:55 -0400 |
commit | 51198ea9478b6e10759ab07cd0b9917663c8df7a (patch) | |
tree | bc744b8eaa771d583936b1227ab1613f94fa923d /arch/arm | |
parent | 7dcca30a32aadb0520417521b0c44f42d09fe05c (diff) |
[ARM] 4429/2: iop13xx: expose the 'iop' attribute versions of the tpmi control registers
The tpmi control registers can be accessed on the internal bus via an
address with PCI attributes or IOP attributes (i.e. read-only,
read-write... etc). The sas driver needs access to the iop-attribute
registers for initialization.
Changelog:
* use ARRAY_SIZE for num_resources, Russell King
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-iop13xx/tpmi.c | 32 |
1 files changed, 27 insertions, 5 deletions
diff --git a/arch/arm/mach-iop13xx/tpmi.c b/arch/arm/mach-iop13xx/tpmi.c index d3dc278213da..2476347ea62f 100644 --- a/arch/arm/mach-iop13xx/tpmi.c +++ b/arch/arm/mach-iop13xx/tpmi.c | |||
@@ -29,13 +29,15 @@ | |||
29 | #define IOP13XX_TPMI_MMR(dev) IOP13XX_REG_ADDR32_PHYS(0x48000 + (dev << 12)) | 29 | #define IOP13XX_TPMI_MMR(dev) IOP13XX_REG_ADDR32_PHYS(0x48000 + (dev << 12)) |
30 | #define IOP13XX_TPMI_MEM(dev) IOP13XX_REG_ADDR32_PHYS(0x60000 + (dev << 13)) | 30 | #define IOP13XX_TPMI_MEM(dev) IOP13XX_REG_ADDR32_PHYS(0x60000 + (dev << 13)) |
31 | #define IOP13XX_TPMI_CTRL(dev) IOP13XX_REG_ADDR32_PHYS(0x50000 + (dev << 10)) | 31 | #define IOP13XX_TPMI_CTRL(dev) IOP13XX_REG_ADDR32_PHYS(0x50000 + (dev << 10)) |
32 | #define IOP13XX_TPMI_IOP_CTRL(dev) (IOP13XX_TPMI_CTRL(dev) + 0x2000) | ||
32 | #define IOP13XX_TPMI_MMR_SIZE (SZ_4K - 1) | 33 | #define IOP13XX_TPMI_MMR_SIZE (SZ_4K - 1) |
33 | #define IOP13XX_TPMI_MEM_SIZE (255) | 34 | #define IOP13XX_TPMI_MEM_SIZE (255) |
34 | #define IOP13XX_TPMI_MEM_CTRL (SZ_1K - 1) | 35 | #define IOP13XX_TPMI_MEM_CTRL (SZ_1K - 1) |
35 | #define IOP13XX_TPMI_RESOURCE_MMR 0 | 36 | #define IOP13XX_TPMI_RESOURCE_MMR 0 |
36 | #define IOP13XX_TPMI_RESOURCE_MEM 1 | 37 | #define IOP13XX_TPMI_RESOURCE_MEM 1 |
37 | #define IOP13XX_TPMI_RESOURCE_CTRL 2 | 38 | #define IOP13XX_TPMI_RESOURCE_CTRL 2 |
38 | #define IOP13XX_TPMI_RESOURCE_IRQ 3 | 39 | #define IOP13XX_TPMI_RESOURCE_IOP_CTRL 3 |
40 | #define IOP13XX_TPMI_RESOURCE_IRQ 4 | ||
39 | 41 | ||
40 | static struct resource iop13xx_tpmi_0_resources[] = { | 42 | static struct resource iop13xx_tpmi_0_resources[] = { |
41 | [IOP13XX_TPMI_RESOURCE_MMR] = { | 43 | [IOP13XX_TPMI_RESOURCE_MMR] = { |
@@ -53,6 +55,11 @@ static struct resource iop13xx_tpmi_0_resources[] = { | |||
53 | .end = IOP13XX_TPMI_CTRL(0) + IOP13XX_TPMI_MEM_CTRL, | 55 | .end = IOP13XX_TPMI_CTRL(0) + IOP13XX_TPMI_MEM_CTRL, |
54 | .flags = IORESOURCE_MEM, | 56 | .flags = IORESOURCE_MEM, |
55 | }, | 57 | }, |
58 | [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = { | ||
59 | .start = IOP13XX_TPMI_IOP_CTRL(0), | ||
60 | .end = IOP13XX_TPMI_IOP_CTRL(0) + IOP13XX_TPMI_MEM_CTRL, | ||
61 | .flags = IORESOURCE_MEM, | ||
62 | }, | ||
56 | [IOP13XX_TPMI_RESOURCE_IRQ] = { | 63 | [IOP13XX_TPMI_RESOURCE_IRQ] = { |
57 | .start = IRQ_IOP13XX_TPMI0_OUT, | 64 | .start = IRQ_IOP13XX_TPMI0_OUT, |
58 | .end = IRQ_IOP13XX_TPMI0_OUT, | 65 | .end = IRQ_IOP13XX_TPMI0_OUT, |
@@ -76,6 +83,11 @@ static struct resource iop13xx_tpmi_1_resources[] = { | |||
76 | .end = IOP13XX_TPMI_CTRL(1) + IOP13XX_TPMI_MEM_CTRL, | 83 | .end = IOP13XX_TPMI_CTRL(1) + IOP13XX_TPMI_MEM_CTRL, |
77 | .flags = IORESOURCE_MEM, | 84 | .flags = IORESOURCE_MEM, |
78 | }, | 85 | }, |
86 | [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = { | ||
87 | .start = IOP13XX_TPMI_IOP_CTRL(1), | ||
88 | .end = IOP13XX_TPMI_IOP_CTRL(1) + IOP13XX_TPMI_MEM_CTRL, | ||
89 | .flags = IORESOURCE_MEM, | ||
90 | }, | ||
79 | [IOP13XX_TPMI_RESOURCE_IRQ] = { | 91 | [IOP13XX_TPMI_RESOURCE_IRQ] = { |
80 | .start = IRQ_IOP13XX_TPMI1_OUT, | 92 | .start = IRQ_IOP13XX_TPMI1_OUT, |
81 | .end = IRQ_IOP13XX_TPMI1_OUT, | 93 | .end = IRQ_IOP13XX_TPMI1_OUT, |
@@ -99,6 +111,11 @@ static struct resource iop13xx_tpmi_2_resources[] = { | |||
99 | .end = IOP13XX_TPMI_CTRL(2) + IOP13XX_TPMI_MEM_CTRL, | 111 | .end = IOP13XX_TPMI_CTRL(2) + IOP13XX_TPMI_MEM_CTRL, |
100 | .flags = IORESOURCE_MEM, | 112 | .flags = IORESOURCE_MEM, |
101 | }, | 113 | }, |
114 | [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = { | ||
115 | .start = IOP13XX_TPMI_IOP_CTRL(2), | ||
116 | .end = IOP13XX_TPMI_IOP_CTRL(2) + IOP13XX_TPMI_MEM_CTRL, | ||
117 | .flags = IORESOURCE_MEM, | ||
118 | }, | ||
102 | [IOP13XX_TPMI_RESOURCE_IRQ] = { | 119 | [IOP13XX_TPMI_RESOURCE_IRQ] = { |
103 | .start = IRQ_IOP13XX_TPMI2_OUT, | 120 | .start = IRQ_IOP13XX_TPMI2_OUT, |
104 | .end = IRQ_IOP13XX_TPMI2_OUT, | 121 | .end = IRQ_IOP13XX_TPMI2_OUT, |
@@ -122,6 +139,11 @@ static struct resource iop13xx_tpmi_3_resources[] = { | |||
122 | .end = IOP13XX_TPMI_CTRL(3) + IOP13XX_TPMI_MEM_CTRL, | 139 | .end = IOP13XX_TPMI_CTRL(3) + IOP13XX_TPMI_MEM_CTRL, |
123 | .flags = IORESOURCE_MEM, | 140 | .flags = IORESOURCE_MEM, |
124 | }, | 141 | }, |
142 | [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = { | ||
143 | .start = IOP13XX_TPMI_IOP_CTRL(3), | ||
144 | .end = IOP13XX_TPMI_IOP_CTRL(3) + IOP13XX_TPMI_MEM_CTRL, | ||
145 | .flags = IORESOURCE_MEM, | ||
146 | }, | ||
125 | [IOP13XX_TPMI_RESOURCE_IRQ] = { | 147 | [IOP13XX_TPMI_RESOURCE_IRQ] = { |
126 | .start = IRQ_IOP13XX_TPMI3_OUT, | 148 | .start = IRQ_IOP13XX_TPMI3_OUT, |
127 | .end = IRQ_IOP13XX_TPMI3_OUT, | 149 | .end = IRQ_IOP13XX_TPMI3_OUT, |
@@ -133,7 +155,7 @@ u64 iop13xx_tpmi_mask = DMA_64BIT_MASK; | |||
133 | static struct platform_device iop13xx_tpmi_0_device = { | 155 | static struct platform_device iop13xx_tpmi_0_device = { |
134 | .name = "iop-tpmi", | 156 | .name = "iop-tpmi", |
135 | .id = 0, | 157 | .id = 0, |
136 | .num_resources = 4, | 158 | .num_resources = ARRAY_SIZE(iop13xx_tpmi_0_resources), |
137 | .resource = iop13xx_tpmi_0_resources, | 159 | .resource = iop13xx_tpmi_0_resources, |
138 | .dev = { | 160 | .dev = { |
139 | .dma_mask = &iop13xx_tpmi_mask, | 161 | .dma_mask = &iop13xx_tpmi_mask, |
@@ -144,7 +166,7 @@ static struct platform_device iop13xx_tpmi_0_device = { | |||
144 | static struct platform_device iop13xx_tpmi_1_device = { | 166 | static struct platform_device iop13xx_tpmi_1_device = { |
145 | .name = "iop-tpmi", | 167 | .name = "iop-tpmi", |
146 | .id = 1, | 168 | .id = 1, |
147 | .num_resources = 4, | 169 | .num_resources = ARRAY_SIZE(iop13xx_tpmi_1_resources), |
148 | .resource = iop13xx_tpmi_1_resources, | 170 | .resource = iop13xx_tpmi_1_resources, |
149 | .dev = { | 171 | .dev = { |
150 | .dma_mask = &iop13xx_tpmi_mask, | 172 | .dma_mask = &iop13xx_tpmi_mask, |
@@ -155,7 +177,7 @@ static struct platform_device iop13xx_tpmi_1_device = { | |||
155 | static struct platform_device iop13xx_tpmi_2_device = { | 177 | static struct platform_device iop13xx_tpmi_2_device = { |
156 | .name = "iop-tpmi", | 178 | .name = "iop-tpmi", |
157 | .id = 2, | 179 | .id = 2, |
158 | .num_resources = 4, | 180 | .num_resources = ARRAY_SIZE(iop13xx_tpmi_2_resources), |
159 | .resource = iop13xx_tpmi_2_resources, | 181 | .resource = iop13xx_tpmi_2_resources, |
160 | .dev = { | 182 | .dev = { |
161 | .dma_mask = &iop13xx_tpmi_mask, | 183 | .dma_mask = &iop13xx_tpmi_mask, |
@@ -166,7 +188,7 @@ static struct platform_device iop13xx_tpmi_2_device = { | |||
166 | static struct platform_device iop13xx_tpmi_3_device = { | 188 | static struct platform_device iop13xx_tpmi_3_device = { |
167 | .name = "iop-tpmi", | 189 | .name = "iop-tpmi", |
168 | .id = 3, | 190 | .id = 3, |
169 | .num_resources = 4, | 191 | .num_resources = ARRAY_SIZE(iop13xx_tpmi_3_resources), |
170 | .resource = iop13xx_tpmi_3_resources, | 192 | .resource = iop13xx_tpmi_3_resources, |
171 | .dev = { | 193 | .dev = { |
172 | .dma_mask = &iop13xx_tpmi_mask, | 194 | .dma_mask = &iop13xx_tpmi_mask, |