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authorTimo Teras <timo.teras@solidboot.com>2006-12-06 20:13:52 -0500
committerTony Lindgren <tony@atomide.com>2007-03-02 04:47:09 -0500
commit681e9940da89633bd25a6d155118fa5340260bc5 (patch)
tree2359194e051aba9b86cd0c1825ffcb3b4332f155 /arch/arm
parent6f9c92f1b9930dd400c79872036d1d8636e6e4b9 (diff)
ARM: OMAP: Proper handling of DMA4_IRQSTATUS_L0
The register bits are reset by writing one. Remove the unneeded reads and fix writes to not clear too many bits. Signed-off-by: Timo Teras <timo.teras@solidboot.com> Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/plat-omap/dma.c14
1 files changed, 3 insertions, 11 deletions
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index bb045e5ddbd8..f3f84fbf8b87 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -557,7 +557,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
557 omap_enable_channel_irq(free_ch); 557 omap_enable_channel_irq(free_ch);
558 /* Clear the CSR register and IRQ status register */ 558 /* Clear the CSR register and IRQ status register */
559 OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK; 559 OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK;
560 omap_writel(~0x0, OMAP_DMA4_IRQSTATUS_L0); 560 omap_writel(1 << free_ch, OMAP_DMA4_IRQSTATUS_L0);
561 } 561 }
562 562
563 *dma_ch_out = free_ch; 563 *dma_ch_out = free_ch;
@@ -597,10 +597,7 @@ void omap_free_dma(int lch)
597 597
598 /* Clear the CSR register and IRQ status register */ 598 /* Clear the CSR register and IRQ status register */
599 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK; 599 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK;
600 600 omap_writel(1 << lch, OMAP_DMA4_IRQSTATUS_L0);
601 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
602 val |= 1 << lch;
603 omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
604 601
605 /* Disable all DMA interrupts for the channel. */ 602 /* Disable all DMA interrupts for the channel. */
606 OMAP_DMA_CICR_REG(lch) = 0; 603 OMAP_DMA_CICR_REG(lch) = 0;
@@ -927,7 +924,6 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
927static int omap2_dma_handle_ch(int ch) 924static int omap2_dma_handle_ch(int ch)
928{ 925{
929 u32 status = OMAP_DMA_CSR_REG(ch); 926 u32 status = OMAP_DMA_CSR_REG(ch);
930 u32 val;
931 927
932 if (!status) 928 if (!status)
933 return 0; 929 return 0;
@@ -948,11 +944,7 @@ static int omap2_dma_handle_ch(int ch)
948 dma_chan[ch].dev_id); 944 dma_chan[ch].dev_id);
949 945
950 OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK; 946 OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK;
951 947 omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0);
952 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0);
953 /* ch in this function is from 0-31 while in register it is 1-32 */
954 val = 1 << (ch);
955 omap_writel(val, OMAP_DMA4_IRQSTATUS_L0);
956 948
957 if (likely(dma_chan[ch].callback != NULL)) 949 if (likely(dma_chan[ch].callback != NULL))
958 dma_chan[ch].callback(ch, status, dma_chan[ch].data); 950 dma_chan[ch].callback(ch, status, dma_chan[ch].data);