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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2013-05-15 06:12:33 -0400
committerNicolas Ferre <nicolas.ferre@atmel.com>2013-05-15 06:37:45 -0400
commitb7a8ca5173ef9aa55fa039d7c216426ff0b25a12 (patch)
tree41010eebef7f8a1727af490561ced96205fdde5c /arch/arm
parent3f81127293284da449942a0144b9747c5db1e523 (diff)
ARM: at91: rm9200 fix time support
since commit 838a2ae80a6ab52139fb1bf0a93ea8c5eff94488 Author: Shawn Guo <shawn.guo@linaro.org> Date: Sat Jan 12 11:50:05 2013 +0000 ARM: use clockevents_config_and_register() where possible The timer is wrongly configured and result in a nice crash so revert it on rm9200 timer. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: stable <stable@vger.kernel.org> # 3.8+ Cc: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-at91/at91rm9200_time.c7
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 2acdff4c1dfe..180b3024bec3 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -174,6 +174,7 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
174static struct clock_event_device clkevt = { 174static struct clock_event_device clkevt = {
175 .name = "at91_tick", 175 .name = "at91_tick",
176 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 176 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
177 .shift = 32,
177 .rating = 150, 178 .rating = 150,
178 .set_next_event = clkevt32k_next_event, 179 .set_next_event = clkevt32k_next_event,
179 .set_mode = clkevt32k_mode, 180 .set_mode = clkevt32k_mode,
@@ -264,9 +265,11 @@ void __init at91rm9200_timer_init(void)
264 at91_st_write(AT91_ST_RTMR, 1); 265 at91_st_write(AT91_ST_RTMR, 1);
265 266
266 /* Setup timer clockevent, with minimum of two ticks (important!!) */ 267 /* Setup timer clockevent, with minimum of two ticks (important!!) */
268 clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
269 clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
270 clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
267 clkevt.cpumask = cpumask_of(0); 271 clkevt.cpumask = cpumask_of(0);
268 clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK, 272 clockevents_register_device(&clkevt);
269 2, AT91_ST_ALMV);
270 273
271 /* register clocksource */ 274 /* register clocksource */
272 clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK); 275 clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);