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authorShawn Guo <shawn.guo@linaro.org>2013-04-02 02:04:45 -0400
committerShawn Guo <shawn.guo@linaro.org>2013-04-09 10:53:38 -0400
commit9a8d6d55f6989961298b995e3ef91eb90e034cf2 (patch)
treeb5e947ef9ed09db0255cc53e0c41e40a78e7e41c /arch/arm
parent082d33d08fe4bc8f73854d7692384905ec1cfcff (diff)
ARM: dts: imx: add initial imx6dl-sabresd support
Add initial imx6dl-sabresd support based on the common stuff already in imx6qdl-sabresd.dtsi. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/imx6dl-sabresd.dts35
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi83
3 files changed, 119 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0254495b6a0f..38d19b005854 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -98,6 +98,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
98 imx53-mba53.dtb \ 98 imx53-mba53.dtb \
99 imx53-qsb.dtb \ 99 imx53-qsb.dtb \
100 imx53-smd.dtb \ 100 imx53-smd.dtb \
101 imx6dl-sabresd.dtb \
101 imx6q-arm2.dtb \ 102 imx6q-arm2.dtb \
102 imx6q-sabreauto.dtb \ 103 imx6q-sabreauto.dtb \
103 imx6q-sabrelite.dtb \ 104 imx6q-sabrelite.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts
new file mode 100644
index 000000000000..7efb05db4783
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-sabresd.dts
@@ -0,0 +1,35 @@
1/*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include "imx6dl.dtsi"
12#include "imx6qdl-sabresd.dtsi"
13
14/ {
15 model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
16 compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
17};
18
19&iomuxc {
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_hog>;
22
23 hog {
24 pinctrl_hog: hoggrp {
25 fsl,pins = <
26 MX6DL_PAD_GPIO_4__GPIO1_IO04 0x80000000
27 MX6DL_PAD_GPIO_5__GPIO1_IO05 0x80000000
28 MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
29 MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
30 MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
31 MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
32 >;
33 };
34 };
35};
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 3cd067798607..3e07f6e9095c 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -1,3 +1,4 @@
1
1/* 2/*
2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 4 *
@@ -8,6 +9,7 @@
8 */ 9 */
9 10
10#include "imx6qdl.dtsi" 11#include "imx6qdl.dtsi"
12#include "imx6dl-pinfunc.h"
11 13
12/ { 14/ {
13 cpus { 15 cpus {
@@ -29,6 +31,87 @@
29 31
30 soc { 32 soc {
31 aips1: aips-bus@02000000 { 33 aips1: aips-bus@02000000 {
34 iomuxc: iomuxc@020e0000 {
35 compatible = "fsl,imx6dl-iomuxc";
36 reg = <0x020e0000 0x4000>;
37
38 enet {
39 pinctrl_enet_1: enetgrp-1 {
40 fsl,pins = <
41 MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
42 MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
43 MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
44 MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
45 MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
46 MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
47 MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
48 MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
49 MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
50 MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
51 MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
52 MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
53 MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
54 MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
55 MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
56 MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
57 >;
58 };
59 };
60
61 uart1 {
62 pinctrl_uart1_1: uart1grp-1 {
63 fsl,pins = <
64 MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
65 MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
66 >;
67 };
68 };
69
70 usbotg {
71 pinctrl_usbotg_2: usbotggrp-2 {
72 fsl,pins = <
73 MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
74 >;
75 };
76 };
77
78 usdhc2 {
79 pinctrl_usdhc2_1: usdhc2grp-1 {
80 fsl,pins = <
81 MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
82 MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
83 MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
84 MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
85 MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
86 MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
87 MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
88 MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
89 MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
90 MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
91 >;
92 };
93 };
94
95 usdhc3 {
96 pinctrl_usdhc3_1: usdhc3grp-1 {
97 fsl,pins = <
98 MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
99 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
100 MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
101 MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
102 MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
103 MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
104 MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
105 MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
106 MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
107 MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
108 >;
109 };
110 };
111
112
113 };
114
32 pxp: pxp@020f0000 { 115 pxp: pxp@020f0000 {
33 reg = <0x020f0000 0x4000>; 116 reg = <0x020f0000 0x4000>;
34 interrupts = <0 98 0x04>; 117 interrupts = <0 98 0x04>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-26 09:42:00 -0500