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authorOlof Johansson <olof@lixom.net>2012-05-10 02:48:44 -0400
committerOlof Johansson <olof@lixom.net>2012-05-10 02:48:52 -0400
commit7a3252f8374749ae4b5cc60e02f9b9eba79311cc (patch)
tree4eaecb237905833cca0251329d9048dbbeebfefb /arch/arm
parentbd69e27304e754b18dd6be8d8575af37afbbd095 (diff)
parent8c6a3852f639736ca7cb0f5e7b3fd0f314b0fc6a (diff)
Merge branch 'for-3.5/tegra30-audio' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/drivers
By Stephen Warren (5) and Peter De Schrijver (1) via Stephen Warren * 'for-3.5/tegra30-audio' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: dt: tegra cardhu: basic audio support ARM: dt: tegra30.dtsi: Add audio-related nodes ARM: tegra: add AUXDATA required for audio ARM: tegra: set up audio clocks for tegra30 dt ARM: tegra: Initialize pll_p_out1 ARM: tegra: provide clock aliases for AHUB configlink Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/tegra-cardhu.dts63
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi41
-rw-r--r--arch/arm/mach-tegra/board-dt-tegra30.c10
-rw-r--r--arch/arm/mach-tegra/common.c12
-rw-r--r--arch/arm/mach-tegra/tegra30_clocks.c9
5 files changed, 135 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
index 0a9f34a2c3aa..ab8d901b5ab6 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -51,6 +51,15 @@
51 nvidia,pull = <2>; 51 nvidia,pull = <2>;
52 nvidia,tristate = <0>; 52 nvidia,tristate = <0>;
53 }; 53 };
54 dap2_fs_pa2 {
55 nvidia,pins = "dap2_fs_pa2",
56 "dap2_sclk_pa3",
57 "dap2_din_pa4",
58 "dap2_dout_pa5";
59 nvidia,function = "i2s1";
60 nvidia,pull = <0>;
61 nvidia,tristate = <0>;
62 };
54 }; 63 };
55 }; 64 };
56 65
@@ -92,6 +101,20 @@
92 101
93 i2c@7000d000 { 102 i2c@7000d000 {
94 clock-frequency = <100000>; 103 clock-frequency = <100000>;
104
105 wm8903: wm8903@1a {
106 compatible = "wlf,wm8903";
107 reg = <0x1a>;
108 interrupt-parent = <&gpio>;
109 interrupts = <179 0x04>; /* gpio PW3 */
110
111 gpio-controller;
112 #gpio-cells = <2>;
113
114 micdet-cfg = <0>;
115 micdet-delay = <100>;
116 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
117 };
95 }; 118 };
96 119
97 sdhci@78000000 { 120 sdhci@78000000 {
@@ -111,4 +134,44 @@
111 sdhci@78000400 { 134 sdhci@78000400 {
112 support-8bit; 135 support-8bit;
113 }; 136 };
137
138 ahub@70080000 {
139 i2s@70080300 {
140 status = "disable";
141 };
142
143 i2s@70080500 {
144 status = "disable";
145 };
146
147 i2s@70080600 {
148 status = "disable";
149 };
150
151 i2s@70080700 {
152 status = "disable";
153 };
154 };
155
156 sound {
157 compatible = "nvidia,tegra-audio-wm8903-cardhu",
158 "nvidia,tegra-audio-wm8903";
159 nvidia,model = "NVIDIA Tegra Cardhu";
160
161 nvidia,audio-routing =
162 "Headphone Jack", "HPOUTR",
163 "Headphone Jack", "HPOUTL",
164 "Int Spk", "ROP",
165 "Int Spk", "RON",
166 "Int Spk", "LOP",
167 "Int Spk", "LON",
168 "Mic Jack", "MICBIAS",
169 "IN1L", "Mic Jack";
170
171 nvidia,i2s-controller = <&tegra_i2s1>;
172 nvidia,audio-codec = <&wm8903>;
173
174 nvidia,spkr-en-gpios = <&wm8903 2 0>;
175 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
176 };
114}; 177};
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 62a7b39f1c9a..15200a949a81 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -183,4 +183,45 @@
183 reg = < 0x70000868 0xd0 /* Pad control registers */ 183 reg = < 0x70000868 0xd0 /* Pad control registers */
184 0x70003000 0x3e0 >; /* Mux registers */ 184 0x70003000 0x3e0 >; /* Mux registers */
185 }; 185 };
186
187 ahub {
188 compatible = "nvidia,tegra30-ahub";
189 reg = <0x70080000 0x200 0x70080200 0x100>;
190 interrupts = < 0 103 0x04 >;
191 nvidia,dma-request-selector = <&apbdma 1>;
192
193 ranges;
194 #address-cells = <1>;
195 #size-cells = <1>;
196
197 tegra_i2s0: i2s@70080300 {
198 compatible = "nvidia,tegra30-i2s";
199 reg = <0x70080300 0x100>;
200 nvidia,ahub-cif-ids = <4 4>;
201 };
202
203 tegra_i2s1: i2s@70080400 {
204 compatible = "nvidia,tegra30-i2s";
205 reg = <0x70080400 0x100>;
206 nvidia,ahub-cif-ids = <5 5>;
207 };
208
209 tegra_i2s2: i2s@70080500 {
210 compatible = "nvidia,tegra30-i2s";
211 reg = <0x70080500 0x100>;
212 nvidia,ahub-cif-ids = <6 6>;
213 };
214
215 tegra_i2s3: i2s@70080600 {
216 compatible = "nvidia,tegra30-i2s";
217 reg = <0x70080600 0x100>;
218 nvidia,ahub-cif-ids = <7 7>;
219 };
220
221 tegra_i2s4: i2s@70080700 {
222 compatible = "nvidia,tegra30-i2s";
223 reg = <0x70080700 0x100>;
224 nvidia,ahub-cif-ids = <8 8>;
225 };
226 };
186}; 227};
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 5f7c03e972f3..d96dae0b4aa7 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -51,12 +51,22 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
51 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL), 51 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL),
52 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL), 52 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL),
53 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL), 53 OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL),
54 OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),
54 {} 55 {}
55}; 56};
56 57
57static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { 58static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
58 /* name parent rate enabled */ 59 /* name parent rate enabled */
59 { "uarta", "pll_p", 408000000, true }, 60 { "uarta", "pll_p", 408000000, true },
61 { "pll_a", "pll_p_out1", 564480000, true },
62 { "pll_a_out0", "pll_a", 11289600, true },
63 { "extern1", "pll_a_out0", 0, true },
64 { "clk_out_1", "extern1", 0, true },
65 { "i2s0", "pll_a_out0", 11289600, false},
66 { "i2s1", "pll_a_out0", 11289600, false},
67 { "i2s2", "pll_a_out0", 11289600, false},
68 { "i2s3", "pll_a_out0", 11289600, false},
69 { "i2s4", "pll_a_out0", 11289600, false},
60 { NULL, NULL, 0, 0}, 70 { NULL, NULL, 0, 0},
61}; 71};
62 72
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index f18f615aa93a..2d80566b5383 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -95,6 +95,17 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = {
95}; 95};
96#endif 96#endif
97 97
98#ifdef CONFIG_ARCH_TEGRA_3x_SOC
99static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
100 /* name parent rate enabled */
101 { "clk_m", NULL, 0, true },
102 { "pll_p", "clk_m", 408000000, true },
103 { "pll_p_out1", "pll_p", 9600000, true },
104 { NULL, NULL, 0, 0},
105};
106#endif
107
108
98static void __init tegra_init_cache(u32 tag_latency, u32 data_latency) 109static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
99{ 110{
100#ifdef CONFIG_CACHE_L2X0 111#ifdef CONFIG_CACHE_L2X0
@@ -129,6 +140,7 @@ void __init tegra30_init_early(void)
129{ 140{
130 tegra_init_fuse(); 141 tegra_init_fuse();
131 tegra30_init_clocks(); 142 tegra30_init_clocks();
143 tegra_clk_init_from_table(tegra30_clk_init_table);
132 tegra_init_cache(0x441, 0x551); 144 tegra_init_cache(0x441, 0x551);
133 tegra_pmc_init(); 145 tegra_pmc_init();
134 tegra_powergate_init(); 146 tegra_powergate_init();
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index 6d08b53f92d2..e33fe4b14a2a 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -3015,6 +3015,15 @@ struct clk_duplicate tegra_clk_duplicates[] = {
3015 CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL), 3015 CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
3016 CLK_DUPLICATE("twd", "smp_twd", NULL), 3016 CLK_DUPLICATE("twd", "smp_twd", NULL),
3017 CLK_DUPLICATE("vcp", "nvavp", "vcp"), 3017 CLK_DUPLICATE("vcp", "nvavp", "vcp"),
3018 CLK_DUPLICATE("i2s0", NULL, "i2s0"),
3019 CLK_DUPLICATE("i2s1", NULL, "i2s1"),
3020 CLK_DUPLICATE("i2s2", NULL, "i2s2"),
3021 CLK_DUPLICATE("i2s3", NULL, "i2s3"),
3022 CLK_DUPLICATE("i2s4", NULL, "i2s4"),
3023 CLK_DUPLICATE("dam0", NULL, "dam0"),
3024 CLK_DUPLICATE("dam1", NULL, "dam1"),
3025 CLK_DUPLICATE("dam2", NULL, "dam2"),
3026 CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
3018}; 3027};
3019 3028
3020struct clk *tegra_ptr_clks[] = { 3029struct clk *tegra_ptr_clks[] = {