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authorArnd Bergmann <arnd@arndb.de>2013-06-19 19:00:15 -0400
committerArnd Bergmann <arnd@arndb.de>2013-06-19 19:00:15 -0400
commit596fd95ea606548adaa8310a7c05a6dcfec46f16 (patch)
tree2d1f5bb81dff7a40ab030a87d6c7fb5ae2bcf559 /arch/arm
parent99ff1830426ed59cc722091eadffd17736bdf148 (diff)
parentf55b2b56cd37fa8bcfcb75248c27094eaf09e04c (diff)
Merge tag 'integrator-pci-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/soc
From Linus Walleij: This is a patch series that: - Pulls the Integrator/AP PCI bridge driver into one file - Adds full device tree support for it - Keeps ATAG support around for the time being * tag 'integrator-pci-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: ARM: integrator: basic PCIv3 device tree support ARM: integrator: move static ioremapping into PCIv3 driver ARM: integrator: move VGA base assignment ARM: integrator: remap PCIv3 base dynamically ARM: integrator: move V3 register definitions into driver ARM: integrator: move PCI base address grab to probe ARM: integrator: grab PCI error IRQ in probe() ARM: integrator: convert PCIv3 bridge to platform device ARM: integrator: merge PCIv3 driver into one file ARM: pci: create pci_common_init_dev() Documentation/devicetree: add a small note on PCI Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/integratorap.dts41
-rw-r--r--arch/arm/include/asm/hardware/pci_v3.h186
-rw-r--r--arch/arm/include/asm/mach/pci.h17
-rw-r--r--arch/arm/kernel/bios32.c9
-rw-r--r--arch/arm/mach-integrator/Makefile2
-rw-r--r--arch/arm/mach-integrator/include/mach/platform.h23
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c31
-rw-r--r--arch/arm/mach-integrator/pci.c113
-rw-r--r--arch/arm/mach-integrator/pci_v3.c532
-rw-r--r--arch/arm/mach-integrator/pci_v3.h2
10 files changed, 550 insertions, 406 deletions
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts
index c9c3fa344647..03f23b7a0ab5 100644
--- a/arch/arm/boot/dts/integratorap.dts
+++ b/arch/arm/boot/dts/integratorap.dts
@@ -39,6 +39,47 @@
39 valid-mask = <0x003fffff>; 39 valid-mask = <0x003fffff>;
40 }; 40 };
41 41
42 pci: pciv3@62000000 {
43 compatible = "v3,v360epc-pci";
44 #interrupt-cells = <1>;
45 #size-cells = <2>;
46 #address-cells = <3>;
47 reg = <0x62000000 0x10000>;
48 interrupt-parent = <&pic>;
49 interrupts = <17>; /* Bus error IRQ */
50 ranges = <0x00000000 0 0x61000000 /* config space */
51 0x61000000 0 0x00100000 /* 16 MiB @ 61000000 */
52 0x01000000 0 0x60000000 /* I/O space */
53 0x60000000 0 0x00100000 /* 16 MiB @ 60000000 */
54 0x02000000 0 0x40000000 /* non-prefectable memory */
55 0x40000000 0 0x10000000 /* 256 MiB @ 40000000 */
56 0x42000000 0 0x50000000 /* prefetchable memory */
57 0x50000000 0 0x10000000>; /* 256 MiB @ 50000000 */
58 interrupt-map-mask = <0xf800 0 0 0x7>;
59 interrupt-map = <
60 /* IDSEL 9 */
61 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
62 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
63 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
64 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
65 /* IDSEL 10 */
66 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
67 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
68 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
69 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
70 /* IDSEL 11 */
71 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
72 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
73 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
74 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
75 /* IDSEL 12 */
76 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
77 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
78 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
79 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
80 >;
81 };
82
42 fpga { 83 fpga {
43 /* 84 /*
44 * The Integator/AP predates the idea to have magic numbers 85 * The Integator/AP predates the idea to have magic numbers
diff --git a/arch/arm/include/asm/hardware/pci_v3.h b/arch/arm/include/asm/hardware/pci_v3.h
deleted file mode 100644
index 2811c7e2cfdf..000000000000
--- a/arch/arm/include/asm/hardware/pci_v3.h
+++ /dev/null
@@ -1,186 +0,0 @@
1/*
2 * arch/arm/include/asm/hardware/pci_v3.h
3 *
4 * Internal header file PCI V3 chip
5 *
6 * Copyright (C) ARM Limited
7 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef ASM_ARM_HARDWARE_PCI_V3_H
24#define ASM_ARM_HARDWARE_PCI_V3_H
25
26/* -------------------------------------------------------------------------------
27 * V3 Local Bus to PCI Bridge definitions
28 * -------------------------------------------------------------------------------
29 * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
30 * All V3 register names are prefaced by V3_ to avoid clashing with any other
31 * PCI definitions. Their names match the user's manual.
32 *
33 * I'm assuming that I20 is disabled.
34 *
35 */
36#define V3_PCI_VENDOR 0x00000000
37#define V3_PCI_DEVICE 0x00000002
38#define V3_PCI_CMD 0x00000004
39#define V3_PCI_STAT 0x00000006
40#define V3_PCI_CC_REV 0x00000008
41#define V3_PCI_HDR_CFG 0x0000000C
42#define V3_PCI_IO_BASE 0x00000010
43#define V3_PCI_BASE0 0x00000014
44#define V3_PCI_BASE1 0x00000018
45#define V3_PCI_SUB_VENDOR 0x0000002C
46#define V3_PCI_SUB_ID 0x0000002E
47#define V3_PCI_ROM 0x00000030
48#define V3_PCI_BPARAM 0x0000003C
49#define V3_PCI_MAP0 0x00000040
50#define V3_PCI_MAP1 0x00000044
51#define V3_PCI_INT_STAT 0x00000048
52#define V3_PCI_INT_CFG 0x0000004C
53#define V3_LB_BASE0 0x00000054
54#define V3_LB_BASE1 0x00000058
55#define V3_LB_MAP0 0x0000005E
56#define V3_LB_MAP1 0x00000062
57#define V3_LB_BASE2 0x00000064
58#define V3_LB_MAP2 0x00000066
59#define V3_LB_SIZE 0x00000068
60#define V3_LB_IO_BASE 0x0000006E
61#define V3_FIFO_CFG 0x00000070
62#define V3_FIFO_PRIORITY 0x00000072
63#define V3_FIFO_STAT 0x00000074
64#define V3_LB_ISTAT 0x00000076
65#define V3_LB_IMASK 0x00000077
66#define V3_SYSTEM 0x00000078
67#define V3_LB_CFG 0x0000007A
68#define V3_PCI_CFG 0x0000007C
69#define V3_DMA_PCI_ADR0 0x00000080
70#define V3_DMA_PCI_ADR1 0x00000090
71#define V3_DMA_LOCAL_ADR0 0x00000084
72#define V3_DMA_LOCAL_ADR1 0x00000094
73#define V3_DMA_LENGTH0 0x00000088
74#define V3_DMA_LENGTH1 0x00000098
75#define V3_DMA_CSR0 0x0000008B
76#define V3_DMA_CSR1 0x0000009B
77#define V3_DMA_CTLB_ADR0 0x0000008C
78#define V3_DMA_CTLB_ADR1 0x0000009C
79#define V3_DMA_DELAY 0x000000E0
80#define V3_MAIL_DATA 0x000000C0
81#define V3_PCI_MAIL_IEWR 0x000000D0
82#define V3_PCI_MAIL_IERD 0x000000D2
83#define V3_LB_MAIL_IEWR 0x000000D4
84#define V3_LB_MAIL_IERD 0x000000D6
85#define V3_MAIL_WR_STAT 0x000000D8
86#define V3_MAIL_RD_STAT 0x000000DA
87#define V3_QBA_MAP 0x000000DC
88
89/* PCI COMMAND REGISTER bits
90 */
91#define V3_COMMAND_M_FBB_EN (1 << 9)
92#define V3_COMMAND_M_SERR_EN (1 << 8)
93#define V3_COMMAND_M_PAR_EN (1 << 6)
94#define V3_COMMAND_M_MASTER_EN (1 << 2)
95#define V3_COMMAND_M_MEM_EN (1 << 1)
96#define V3_COMMAND_M_IO_EN (1 << 0)
97
98/* SYSTEM REGISTER bits
99 */
100#define V3_SYSTEM_M_RST_OUT (1 << 15)
101#define V3_SYSTEM_M_LOCK (1 << 14)
102
103/* PCI_CFG bits
104 */
105#define V3_PCI_CFG_M_I2O_EN (1 << 15)
106#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14)
107#define V3_PCI_CFG_M_IO_DIS (1 << 13)
108#define V3_PCI_CFG_M_EN3V (1 << 12)
109#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
110#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
111#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
112
113/* PCI_BASE register bits (PCI -> Local Bus)
114 */
115#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
116#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
117#define V3_PCI_BASE_M_PREFETCH (1 << 3)
118#define V3_PCI_BASE_M_TYPE (3 << 1)
119#define V3_PCI_BASE_M_IO (1 << 0)
120
121/* PCI MAP register bits (PCI -> Local bus)
122 */
123#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
124#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
125#define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
126#define V3_PCI_MAP_M_SWAP (3 << 8)
127#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
128#define V3_PCI_MAP_M_REG_EN (1 << 1)
129#define V3_PCI_MAP_M_ENABLE (1 << 0)
130
131/*
132 * LB_BASE0,1 register bits (Local bus -> PCI)
133 */
134#define V3_LB_BASE_ADR_BASE 0xfff00000
135#define V3_LB_BASE_SWAP (3 << 8)
136#define V3_LB_BASE_ADR_SIZE (15 << 4)
137#define V3_LB_BASE_PREFETCH (1 << 3)
138#define V3_LB_BASE_ENABLE (1 << 0)
139
140#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
141#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
142#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
143#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
144#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
145#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
146#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
147#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
148#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
149#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
150#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
151#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
152
153#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
154
155/*
156 * LB_MAP0,1 register bits (Local bus -> PCI)
157 */
158#define V3_LB_MAP_MAP_ADR 0xfff0
159#define V3_LB_MAP_TYPE (7 << 1)
160#define V3_LB_MAP_AD_LOW_EN (1 << 0)
161
162#define V3_LB_MAP_TYPE_IACK (0 << 1)
163#define V3_LB_MAP_TYPE_IO (1 << 1)
164#define V3_LB_MAP_TYPE_MEM (3 << 1)
165#define V3_LB_MAP_TYPE_CONFIG (5 << 1)
166#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
167
168#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
169
170/*
171 * LB_BASE2 register bits (Local bus -> PCI IO)
172 */
173#define V3_LB_BASE2_ADR_BASE 0xff00
174#define V3_LB_BASE2_SWAP (3 << 6)
175#define V3_LB_BASE2_ENABLE (1 << 0)
176
177#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
178
179/*
180 * LB_MAP2 register bits (Local bus -> PCI IO)
181 */
182#define V3_LB_MAP2_MAP_ADR 0xff00
183
184#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
185
186#endif
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 7d2c3c843801..a1c90d7feb0e 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -16,6 +16,7 @@
16struct pci_sys_data; 16struct pci_sys_data;
17struct pci_ops; 17struct pci_ops;
18struct pci_bus; 18struct pci_bus;
19struct device;
19 20
20struct hw_pci { 21struct hw_pci {
21#ifdef CONFIG_PCI_DOMAINS 22#ifdef CONFIG_PCI_DOMAINS
@@ -68,7 +69,16 @@ struct pci_sys_data {
68/* 69/*
69 * Call this with your hw_pci struct to initialise the PCI system. 70 * Call this with your hw_pci struct to initialise the PCI system.
70 */ 71 */
71void pci_common_init(struct hw_pci *); 72void pci_common_init_dev(struct device *, struct hw_pci *);
73
74/*
75 * Compatibility wrapper for older platforms that do not care about
76 * passing the parent device.
77 */
78static inline void pci_common_init(struct hw_pci *hw)
79{
80 pci_common_init_dev(NULL, hw);
81}
72 82
73/* 83/*
74 * Setup early fixed I/O mapping. 84 * Setup early fixed I/O mapping.
@@ -96,9 +106,4 @@ extern struct pci_ops via82c505_ops;
96extern int via82c505_setup(int nr, struct pci_sys_data *); 106extern int via82c505_setup(int nr, struct pci_sys_data *);
97extern void via82c505_init(void *sysdata); 107extern void via82c505_init(void *sysdata);
98 108
99extern struct pci_ops pci_v3_ops;
100extern int pci_v3_setup(int nr, struct pci_sys_data *);
101extern void pci_v3_preinit(void);
102extern void pci_v3_postinit(void);
103
104#endif /* __ASM_MACH_PCI_H */ 109#endif /* __ASM_MACH_PCI_H */
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index b2ed73c45489..261fcc826169 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -445,7 +445,8 @@ static int pcibios_init_resources(int busnr, struct pci_sys_data *sys)
445 return 0; 445 return 0;
446} 446}
447 447
448static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head) 448static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
449 struct list_head *head)
449{ 450{
450 struct pci_sys_data *sys = NULL; 451 struct pci_sys_data *sys = NULL;
451 int ret; 452 int ret;
@@ -480,7 +481,7 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
480 if (hw->scan) 481 if (hw->scan)
481 sys->bus = hw->scan(nr, sys); 482 sys->bus = hw->scan(nr, sys);
482 else 483 else
483 sys->bus = pci_scan_root_bus(NULL, sys->busnr, 484 sys->bus = pci_scan_root_bus(parent, sys->busnr,
484 hw->ops, sys, &sys->resources); 485 hw->ops, sys, &sys->resources);
485 486
486 if (!sys->bus) 487 if (!sys->bus)
@@ -497,7 +498,7 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
497 } 498 }
498} 499}
499 500
500void pci_common_init(struct hw_pci *hw) 501void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
501{ 502{
502 struct pci_sys_data *sys; 503 struct pci_sys_data *sys;
503 LIST_HEAD(head); 504 LIST_HEAD(head);
@@ -505,7 +506,7 @@ void pci_common_init(struct hw_pci *hw)
505 pci_add_flags(PCI_REASSIGN_ALL_RSRC); 506 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
506 if (hw->preinit) 507 if (hw->preinit)
507 hw->preinit(); 508 hw->preinit();
508 pcibios_init_hw(hw, &head); 509 pcibios_init_hw(parent, hw, &head);
509 if (hw->postinit) 510 if (hw->postinit)
510 hw->postinit(); 511 hw->postinit();
511 512
diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index d14d6b76f4c2..ec759ded7b60 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -8,5 +8,5 @@ obj-y := core.o lm.o leds.o
8obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o 8obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o
9obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o 9obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o
10 10
11obj-$(CONFIG_PCI) += pci_v3.o pci.o 11obj-$(CONFIG_PCI) += pci_v3.o
12obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o 12obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
index be5859efe10e..306d025d9730 100644
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ b/arch/arm/mach-integrator/include/mach/platform.h
@@ -305,29 +305,6 @@
305/* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */ 305/* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */
306 306
307/* ------------------------------------------------------------------------ 307/* ------------------------------------------------------------------------
308 * Where in the memory map does PCI live?
309 * ------------------------------------------------------------------------
310 * This represents a fairly liberal usage of address space. Even though
311 * the V3 only has two windows (therefore we need to map stuff on the fly),
312 * we maintain the same addresses, even if they're not mapped.
313 *
314 */
315#define PHYS_PCI_MEM_BASE 0x40000000 /* 512M to xxx */
316/* unused 256M from A0000000-AFFFFFFF might be used for I2O ???
317 */
318#define PHYS_PCI_IO_BASE 0x60000000 /* 16M to xxx */
319/* unused (128-16)M from B1000000-B7FFFFFF
320 */
321#define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */
322/* unused ((128-16)M - 64K) from XXX
323 */
324#define PHYS_PCI_V3_BASE 0x62000000
325
326#define PCI_MEMORY_VADDR IOMEM(0xe8000000)
327#define PCI_CONFIG_VADDR IOMEM(0xec000000)
328#define PCI_V3_VADDR IOMEM(0xed000000)
329
330/* ------------------------------------------------------------------------
331 * Integrator Interrupt Controllers 308 * Integrator Interrupt Controllers
332 * ------------------------------------------------------------------------ 309 * ------------------------------------------------------------------------
333 * 310 *
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index b23c8e4f28e8..a5b15c4e8def 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -41,7 +41,6 @@
41#include <linux/stat.h> 41#include <linux/stat.h>
42#include <linux/sys_soc.h> 42#include <linux/sys_soc.h>
43#include <linux/termios.h> 43#include <linux/termios.h>
44#include <video/vga.h>
45 44
46#include <mach/hardware.h> 45#include <mach/hardware.h>
47#include <mach/platform.h> 46#include <mach/platform.h>
@@ -57,10 +56,10 @@
57#include <asm/mach/arch.h> 56#include <asm/mach/arch.h>
58#include <asm/mach/irq.h> 57#include <asm/mach/irq.h>
59#include <asm/mach/map.h> 58#include <asm/mach/map.h>
60#include <asm/mach/pci.h>
61#include <asm/mach/time.h> 59#include <asm/mach/time.h>
62 60
63#include "common.h" 61#include "common.h"
62#include "pci_v3.h"
64 63
65/* Base address to the AP system controller */ 64/* Base address to the AP system controller */
66void __iomem *ap_syscon_base; 65void __iomem *ap_syscon_base;
@@ -78,10 +77,6 @@ void __iomem *ap_syscon_base;
78 77
79/* 78/*
80 * Logical Physical 79 * Logical Physical
81 * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
82 * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
83 * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
84 * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
85 * ef000000 Cache flush 80 * ef000000 Cache flush
86 * f1000000 10000000 Core module registers 81 * f1000000 10000000 Core module registers
87 * f1100000 11000000 System controller registers 82 * f1100000 11000000 System controller registers
@@ -130,29 +125,13 @@ static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
130 .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE), 125 .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
131 .length = SZ_4K, 126 .length = SZ_4K,
132 .type = MT_DEVICE 127 .type = MT_DEVICE
133 }, {
134 .virtual = (unsigned long)PCI_MEMORY_VADDR,
135 .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
136 .length = SZ_16M,
137 .type = MT_DEVICE
138 }, {
139 .virtual = (unsigned long)PCI_CONFIG_VADDR,
140 .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
141 .length = SZ_16M,
142 .type = MT_DEVICE
143 }, {
144 .virtual = (unsigned long)PCI_V3_VADDR,
145 .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
146 .length = SZ_64K,
147 .type = MT_DEVICE
148 } 128 }
149}; 129};
150 130
151static void __init ap_map_io(void) 131static void __init ap_map_io(void)
152{ 132{
153 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc)); 133 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
154 vga_base = (unsigned long)PCI_MEMORY_VADDR; 134 pci_v3_early_init();
155 pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
156} 135}
157 136
158#ifdef CONFIG_PM 137#ifdef CONFIG_PM
@@ -615,6 +594,11 @@ static void __init ap_map_io_atag(void)
615 * for eventual deletion. 594 * for eventual deletion.
616 */ 595 */
617 596
597static struct platform_device pci_v3_device = {
598 .name = "pci-v3",
599 .id = 0,
600};
601
618static struct resource cfi_flash_resource = { 602static struct resource cfi_flash_resource = {
619 .start = INTEGRATOR_FLASH_BASE, 603 .start = INTEGRATOR_FLASH_BASE,
620 .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1, 604 .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
@@ -672,6 +656,7 @@ static void __init ap_init(void)
672 unsigned long sc_dec; 656 unsigned long sc_dec;
673 int i; 657 int i;
674 658
659 platform_device_register(&pci_v3_device);
675 platform_device_register(&cfi_flash_device); 660 platform_device_register(&cfi_flash_device);
676 661
677 ap_syscon_base = __io_address(INTEGRATOR_SC_BASE); 662 ap_syscon_base = __io_address(INTEGRATOR_SC_BASE);
diff --git a/arch/arm/mach-integrator/pci.c b/arch/arm/mach-integrator/pci.c
deleted file mode 100644
index 6c1667e728f5..000000000000
--- a/arch/arm/mach-integrator/pci.c
+++ /dev/null
@@ -1,113 +0,0 @@
1/*
2 * linux/arch/arm/mach-integrator/pci-integrator.c
3 *
4 * Copyright (C) 1999 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 *
22 * PCI functions for Integrator
23 */
24#include <linux/kernel.h>
25#include <linux/pci.h>
26#include <linux/interrupt.h>
27#include <linux/init.h>
28
29#include <asm/mach/pci.h>
30#include <asm/mach-types.h>
31
32#include <mach/irqs.h>
33
34/*
35 * A small note about bridges and interrupts. The DECchip 21050 (and
36 * later) adheres to the PCI-PCI bridge specification. This says that
37 * the interrupts on the other side of a bridge are swizzled in the
38 * following manner:
39 *
40 * Dev Interrupt Interrupt
41 * Pin on Pin on
42 * Device Connector
43 *
44 * 4 A A
45 * B B
46 * C C
47 * D D
48 *
49 * 5 A B
50 * B C
51 * C D
52 * D A
53 *
54 * 6 A C
55 * B D
56 * C A
57 * D B
58 *
59 * 7 A D
60 * B A
61 * C B
62 * D C
63 *
64 * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
65 * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
66 */
67
68/*
69 * This routine handles multiple bridges.
70 */
71static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp)
72{
73 if (*pinp == 0)
74 *pinp = 1;
75
76 return pci_common_swizzle(dev, pinp);
77}
78
79static int irq_tab[4] __initdata = {
80 IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
81};
82
83/*
84 * map the specified device/slot/pin to an IRQ. This works out such
85 * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
86 */
87static int __init integrator_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
88{
89 int intnr = ((slot - 9) + (pin - 1)) & 3;
90
91 return irq_tab[intnr];
92}
93
94extern void pci_v3_init(void *);
95
96static struct hw_pci integrator_pci __initdata = {
97 .swizzle = integrator_swizzle,
98 .map_irq = integrator_map_irq,
99 .setup = pci_v3_setup,
100 .nr_controllers = 1,
101 .ops = &pci_v3_ops,
102 .preinit = pci_v3_preinit,
103 .postinit = pci_v3_postinit,
104};
105
106static int __init integrator_pci_init(void)
107{
108 if (machine_is_integrator())
109 pci_common_init(&integrator_pci);
110 return 0;
111}
112
113subsys_initcall(integrator_pci_init);
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index e7fcea7f3300..a0e069d37e14 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -27,16 +27,198 @@
27#include <linux/spinlock.h> 27#include <linux/spinlock.h>
28#include <linux/init.h> 28#include <linux/init.h>
29#include <linux/io.h> 29#include <linux/io.h>
30#include <linux/platform_device.h>
31#include <linux/of.h>
32#include <linux/of_address.h>
33#include <linux/of_irq.h>
34#include <linux/of_pci.h>
35#include <video/vga.h>
30 36
31#include <mach/hardware.h> 37#include <mach/hardware.h>
32#include <mach/platform.h> 38#include <mach/platform.h>
33#include <mach/irqs.h> 39#include <mach/irqs.h>
34 40
41#include <asm/mach/map.h>
35#include <asm/signal.h> 42#include <asm/signal.h>
36#include <asm/mach/pci.h> 43#include <asm/mach/pci.h>
37#include <asm/irq_regs.h> 44#include <asm/irq_regs.h>
38 45
39#include <asm/hardware/pci_v3.h> 46#include "pci_v3.h"
47
48/*
49 * Where in the memory map does PCI live?
50 *
51 * This represents a fairly liberal usage of address space. Even though
52 * the V3 only has two windows (therefore we need to map stuff on the fly),
53 * we maintain the same addresses, even if they're not mapped.
54 */
55#define PHYS_PCI_MEM_BASE 0x40000000 /* 512M */
56#define PHYS_PCI_IO_BASE 0x60000000 /* 16M */
57#define PHYS_PCI_CONFIG_BASE 0x61000000 /* 16M */
58#define PHYS_PCI_V3_BASE 0x62000000 /* 64K */
59
60#define PCI_MEMORY_VADDR IOMEM(0xe8000000)
61#define PCI_CONFIG_VADDR IOMEM(0xec000000)
62
63/*
64 * V3 Local Bus to PCI Bridge definitions
65 *
66 * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
67 * All V3 register names are prefaced by V3_ to avoid clashing with any other
68 * PCI definitions. Their names match the user's manual.
69 *
70 * I'm assuming that I20 is disabled.
71 *
72 */
73#define V3_PCI_VENDOR 0x00000000
74#define V3_PCI_DEVICE 0x00000002
75#define V3_PCI_CMD 0x00000004
76#define V3_PCI_STAT 0x00000006
77#define V3_PCI_CC_REV 0x00000008
78#define V3_PCI_HDR_CFG 0x0000000C
79#define V3_PCI_IO_BASE 0x00000010
80#define V3_PCI_BASE0 0x00000014
81#define V3_PCI_BASE1 0x00000018
82#define V3_PCI_SUB_VENDOR 0x0000002C
83#define V3_PCI_SUB_ID 0x0000002E
84#define V3_PCI_ROM 0x00000030
85#define V3_PCI_BPARAM 0x0000003C
86#define V3_PCI_MAP0 0x00000040
87#define V3_PCI_MAP1 0x00000044
88#define V3_PCI_INT_STAT 0x00000048
89#define V3_PCI_INT_CFG 0x0000004C
90#define V3_LB_BASE0 0x00000054
91#define V3_LB_BASE1 0x00000058
92#define V3_LB_MAP0 0x0000005E
93#define V3_LB_MAP1 0x00000062
94#define V3_LB_BASE2 0x00000064
95#define V3_LB_MAP2 0x00000066
96#define V3_LB_SIZE 0x00000068
97#define V3_LB_IO_BASE 0x0000006E
98#define V3_FIFO_CFG 0x00000070
99#define V3_FIFO_PRIORITY 0x00000072
100#define V3_FIFO_STAT 0x00000074
101#define V3_LB_ISTAT 0x00000076
102#define V3_LB_IMASK 0x00000077
103#define V3_SYSTEM 0x00000078
104#define V3_LB_CFG 0x0000007A
105#define V3_PCI_CFG 0x0000007C
106#define V3_DMA_PCI_ADR0 0x00000080
107#define V3_DMA_PCI_ADR1 0x00000090
108#define V3_DMA_LOCAL_ADR0 0x00000084
109#define V3_DMA_LOCAL_ADR1 0x00000094
110#define V3_DMA_LENGTH0 0x00000088
111#define V3_DMA_LENGTH1 0x00000098
112#define V3_DMA_CSR0 0x0000008B
113#define V3_DMA_CSR1 0x0000009B
114#define V3_DMA_CTLB_ADR0 0x0000008C
115#define V3_DMA_CTLB_ADR1 0x0000009C
116#define V3_DMA_DELAY 0x000000E0
117#define V3_MAIL_DATA 0x000000C0
118#define V3_PCI_MAIL_IEWR 0x000000D0
119#define V3_PCI_MAIL_IERD 0x000000D2
120#define V3_LB_MAIL_IEWR 0x000000D4
121#define V3_LB_MAIL_IERD 0x000000D6
122#define V3_MAIL_WR_STAT 0x000000D8
123#define V3_MAIL_RD_STAT 0x000000DA
124#define V3_QBA_MAP 0x000000DC
125
126/* PCI COMMAND REGISTER bits
127 */
128#define V3_COMMAND_M_FBB_EN (1 << 9)
129#define V3_COMMAND_M_SERR_EN (1 << 8)
130#define V3_COMMAND_M_PAR_EN (1 << 6)
131#define V3_COMMAND_M_MASTER_EN (1 << 2)
132#define V3_COMMAND_M_MEM_EN (1 << 1)
133#define V3_COMMAND_M_IO_EN (1 << 0)
134
135/* SYSTEM REGISTER bits
136 */
137#define V3_SYSTEM_M_RST_OUT (1 << 15)
138#define V3_SYSTEM_M_LOCK (1 << 14)
139
140/* PCI_CFG bits
141 */
142#define V3_PCI_CFG_M_I2O_EN (1 << 15)
143#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14)
144#define V3_PCI_CFG_M_IO_DIS (1 << 13)
145#define V3_PCI_CFG_M_EN3V (1 << 12)
146#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
147#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
148#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
149
150/* PCI_BASE register bits (PCI -> Local Bus)
151 */
152#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
153#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
154#define V3_PCI_BASE_M_PREFETCH (1 << 3)
155#define V3_PCI_BASE_M_TYPE (3 << 1)
156#define V3_PCI_BASE_M_IO (1 << 0)
157
158/* PCI MAP register bits (PCI -> Local bus)
159 */
160#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
161#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
162#define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
163#define V3_PCI_MAP_M_SWAP (3 << 8)
164#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
165#define V3_PCI_MAP_M_REG_EN (1 << 1)
166#define V3_PCI_MAP_M_ENABLE (1 << 0)
167
168/*
169 * LB_BASE0,1 register bits (Local bus -> PCI)
170 */
171#define V3_LB_BASE_ADR_BASE 0xfff00000
172#define V3_LB_BASE_SWAP (3 << 8)
173#define V3_LB_BASE_ADR_SIZE (15 << 4)
174#define V3_LB_BASE_PREFETCH (1 << 3)
175#define V3_LB_BASE_ENABLE (1 << 0)
176
177#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
178#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
179#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
180#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
181#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
182#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
183#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
184#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
185#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
186#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
187#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
188#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
189
190#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
191
192/*
193 * LB_MAP0,1 register bits (Local bus -> PCI)
194 */
195#define V3_LB_MAP_MAP_ADR 0xfff0
196#define V3_LB_MAP_TYPE (7 << 1)
197#define V3_LB_MAP_AD_LOW_EN (1 << 0)
198
199#define V3_LB_MAP_TYPE_IACK (0 << 1)
200#define V3_LB_MAP_TYPE_IO (1 << 1)
201#define V3_LB_MAP_TYPE_MEM (3 << 1)
202#define V3_LB_MAP_TYPE_CONFIG (5 << 1)
203#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
204
205#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
206
207/*
208 * LB_BASE2 register bits (Local bus -> PCI IO)
209 */
210#define V3_LB_BASE2_ADR_BASE 0xff00
211#define V3_LB_BASE2_SWAP (3 << 6)
212#define V3_LB_BASE2_ENABLE (1 << 0)
213
214#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
215
216/*
217 * LB_MAP2 register bits (Local bus -> PCI IO)
218 */
219#define V3_LB_MAP2_MAP_ADR 0xff00
220
221#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
40 222
41/* 223/*
42 * The V3 PCI interface chip in Integrator provides several windows from 224 * The V3 PCI interface chip in Integrator provides several windows from
@@ -101,15 +283,22 @@
101 * the mappings into PCI memory. 283 * the mappings into PCI memory.
102 */ 284 */
103 285
286/* Filled in by probe */
287static void __iomem *pci_v3_base;
288static struct resource conf_mem; /* FIXME: remap this instead of static map */
289static struct resource io_mem;
290static struct resource non_mem;
291static struct resource pre_mem;
292
104// V3 access routines 293// V3 access routines
105#define v3_writeb(o,v) __raw_writeb(v, PCI_V3_VADDR + (unsigned int)(o)) 294#define v3_writeb(o,v) __raw_writeb(v, pci_v3_base + (unsigned int)(o))
106#define v3_readb(o) (__raw_readb(PCI_V3_VADDR + (unsigned int)(o))) 295#define v3_readb(o) (__raw_readb(pci_v3_base + (unsigned int)(o)))
107 296
108#define v3_writew(o,v) __raw_writew(v, PCI_V3_VADDR + (unsigned int)(o)) 297#define v3_writew(o,v) __raw_writew(v, pci_v3_base + (unsigned int)(o))
109#define v3_readw(o) (__raw_readw(PCI_V3_VADDR + (unsigned int)(o))) 298#define v3_readw(o) (__raw_readw(pci_v3_base + (unsigned int)(o)))
110 299
111#define v3_writel(o,v) __raw_writel(v, PCI_V3_VADDR + (unsigned int)(o)) 300#define v3_writel(o,v) __raw_writel(v, pci_v3_base + (unsigned int)(o))
112#define v3_readl(o) (__raw_readl(PCI_V3_VADDR + (unsigned int)(o))) 301#define v3_readl(o) (__raw_readl(pci_v3_base + (unsigned int)(o)))
113 302
114/*============================================================================ 303/*============================================================================
115 * 304 *
@@ -243,13 +432,13 @@ static void __iomem *v3_open_config_window(struct pci_bus *bus,
243 * prefetchable), this frees up base1 for re-use by 432 * prefetchable), this frees up base1 for re-use by
244 * configuration memory 433 * configuration memory
245 */ 434 */
246 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | 435 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
247 V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE); 436 V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
248 437
249 /* 438 /*
250 * Set up base1/map1 to point into configuration space. 439 * Set up base1/map1 to point into configuration space.
251 */ 440 */
252 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) | 441 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(conf_mem.start) |
253 V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE); 442 V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
254 v3_writew(V3_LB_MAP1, mapaddress); 443 v3_writew(V3_LB_MAP1, mapaddress);
255 444
@@ -261,7 +450,7 @@ static void v3_close_config_window(void)
261 /* 450 /*
262 * Reassign base1 for use by prefetchable PCI memory 451 * Reassign base1 for use by prefetchable PCI memory
263 */ 452 */
264 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | 453 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
265 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | 454 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
266 V3_LB_BASE_ENABLE); 455 V3_LB_BASE_ENABLE);
267 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | 456 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
@@ -270,7 +459,7 @@ static void v3_close_config_window(void)
270 /* 459 /*
271 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct) 460 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
272 */ 461 */
273 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | 462 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
274 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); 463 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
275} 464}
276 465
@@ -337,25 +526,11 @@ static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
337 return PCIBIOS_SUCCESSFUL; 526 return PCIBIOS_SUCCESSFUL;
338} 527}
339 528
340struct pci_ops pci_v3_ops = { 529static struct pci_ops pci_v3_ops = {
341 .read = v3_read_config, 530 .read = v3_read_config,
342 .write = v3_write_config, 531 .write = v3_write_config,
343}; 532};
344 533
345static struct resource non_mem = {
346 .name = "PCI non-prefetchable",
347 .start = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START,
348 .end = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE - 1,
349 .flags = IORESOURCE_MEM,
350};
351
352static struct resource pre_mem = {
353 .name = "PCI prefetchable",
354 .start = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START,
355 .end = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START + PCI_BUS_PREMEM_SIZE - 1,
356 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
357};
358
359static int __init pci_v3_setup_resources(struct pci_sys_data *sys) 534static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
360{ 535{
361 if (request_resource(&iomem_resource, &non_mem)) { 536 if (request_resource(&iomem_resource, &non_mem)) {
@@ -471,7 +646,7 @@ static irqreturn_t v3_irq(int dummy, void *devid)
471 return IRQ_HANDLED; 646 return IRQ_HANDLED;
472} 647}
473 648
474int __init pci_v3_setup(int nr, struct pci_sys_data *sys) 649static int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
475{ 650{
476 int ret = 0; 651 int ret = 0;
477 652
@@ -479,7 +654,7 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
479 return -EINVAL; 654 return -EINVAL;
480 655
481 if (nr == 0) { 656 if (nr == 0) {
482 sys->mem_offset = PHYS_PCI_MEM_BASE; 657 sys->mem_offset = non_mem.start;
483 ret = pci_v3_setup_resources(sys); 658 ret = pci_v3_setup_resources(sys);
484 } 659 }
485 660
@@ -490,18 +665,10 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
490 * V3_LB_BASE? - local bus address 665 * V3_LB_BASE? - local bus address
491 * V3_LB_MAP? - pci bus address 666 * V3_LB_MAP? - pci bus address
492 */ 667 */
493void __init pci_v3_preinit(void) 668static void __init pci_v3_preinit(void)
494{ 669{
495 unsigned long flags; 670 unsigned long flags;
496 unsigned int temp; 671 unsigned int temp;
497 int ret;
498
499 /* Remap the Integrator system controller */
500 ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
501 if (!ap_syscon_base) {
502 pr_err("unable to remap the AP syscon for PCIv3\n");
503 return;
504 }
505 672
506 pcibios_min_mem = 0x00100000; 673 pcibios_min_mem = 0x00100000;
507 674
@@ -525,7 +692,7 @@ void __init pci_v3_preinit(void)
525 * Setup window 0 - PCI non-prefetchable memory 692 * Setup window 0 - PCI non-prefetchable memory
526 * Local: 0x40000000 Bus: 0x00000000 Size: 256MB 693 * Local: 0x40000000 Bus: 0x00000000 Size: 256MB
527 */ 694 */
528 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) | 695 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(non_mem.start) |
529 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE); 696 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
530 v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) | 697 v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) |
531 V3_LB_MAP_TYPE_MEM); 698 V3_LB_MAP_TYPE_MEM);
@@ -534,7 +701,7 @@ void __init pci_v3_preinit(void)
534 * Setup window 1 - PCI prefetchable memory 701 * Setup window 1 - PCI prefetchable memory
535 * Local: 0x50000000 Bus: 0x10000000 Size: 256MB 702 * Local: 0x50000000 Bus: 0x10000000 Size: 256MB
536 */ 703 */
537 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) | 704 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(pre_mem.start) |
538 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH | 705 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
539 V3_LB_BASE_ENABLE); 706 V3_LB_BASE_ENABLE);
540 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) | 707 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
@@ -543,7 +710,7 @@ void __init pci_v3_preinit(void)
543 /* 710 /*
544 * Setup window 2 - PCI IO 711 * Setup window 2 - PCI IO
545 */ 712 */
546 v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(PHYS_PCI_IO_BASE) | 713 v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(io_mem.start) |
547 V3_LB_BASE_ENABLE); 714 V3_LB_BASE_ENABLE);
548 v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0)); 715 v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
549 716
@@ -578,18 +745,10 @@ void __init pci_v3_preinit(void)
578 v3_writeb(V3_LB_IMASK, 0x28); 745 v3_writeb(V3_LB_IMASK, 0x28);
579 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET); 746 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
580 747
581 /*
582 * Grab the PCI error interrupt.
583 */
584 ret = request_irq(IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
585 if (ret)
586 printk(KERN_ERR "PCI: unable to grab PCI error "
587 "interrupt: %d\n", ret);
588
589 raw_spin_unlock_irqrestore(&v3_lock, flags); 748 raw_spin_unlock_irqrestore(&v3_lock, flags);
590} 749}
591 750
592void __init pci_v3_postinit(void) 751static void __init pci_v3_postinit(void)
593{ 752{
594 unsigned int pci_cmd; 753 unsigned int pci_cmd;
595 754
@@ -608,5 +767,278 @@ void __init pci_v3_postinit(void)
608 "interrupt: %d\n", ret); 767 "interrupt: %d\n", ret);
609#endif 768#endif
610 769
611 register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0); 770 register_isa_ports(non_mem.start, io_mem.start, 0);
771}
772
773/*
774 * A small note about bridges and interrupts. The DECchip 21050 (and
775 * later) adheres to the PCI-PCI bridge specification. This says that
776 * the interrupts on the other side of a bridge are swizzled in the
777 * following manner:
778 *
779 * Dev Interrupt Interrupt
780 * Pin on Pin on
781 * Device Connector
782 *
783 * 4 A A
784 * B B
785 * C C
786 * D D
787 *
788 * 5 A B
789 * B C
790 * C D
791 * D A
792 *
793 * 6 A C
794 * B D
795 * C A
796 * D B
797 *
798 * 7 A D
799 * B A
800 * C B
801 * D C
802 *
803 * Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
804 * Thus, each swizzle is ((pin-1) + (device#-4)) % 4
805 */
806
807/*
808 * This routine handles multiple bridges.
809 */
810static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp)
811{
812 if (*pinp == 0)
813 *pinp = 1;
814
815 return pci_common_swizzle(dev, pinp);
816}
817
818static int irq_tab[4] __initdata = {
819 IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
820};
821
822/*
823 * map the specified device/slot/pin to an IRQ. This works out such
824 * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
825 */
826static int __init pci_v3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
827{
828 int intnr = ((slot - 9) + (pin - 1)) & 3;
829
830 return irq_tab[intnr];
831}
832
833static struct hw_pci pci_v3 __initdata = {
834 .swizzle = pci_v3_swizzle,
835 .setup = pci_v3_setup,
836 .nr_controllers = 1,
837 .ops = &pci_v3_ops,
838 .preinit = pci_v3_preinit,
839 .postinit = pci_v3_postinit,
840};
841
842#ifdef CONFIG_OF
843
844static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin)
845{
846 struct of_irq oirq;
847 int ret;
848
849 ret = of_irq_map_pci(dev, &oirq);
850 if (ret) {
851 dev_err(&dev->dev, "of_irq_map_pci() %d\n", ret);
852 /* Proper return code 0 == NO_IRQ */
853 return 0;
854 }
855
856 return irq_create_of_mapping(oirq.controller, oirq.specifier,
857 oirq.size);
858}
859
860static int __init pci_v3_dtprobe(struct platform_device *pdev,
861 struct device_node *np)
862{
863 struct of_pci_range_parser parser;
864 struct of_pci_range range;
865 struct resource *res;
866 int irq, ret;
867
868 if (of_pci_range_parser_init(&parser, np))
869 return -EINVAL;
870
871 /* Get base for bridge registers */
872 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
873 if (!res) {
874 dev_err(&pdev->dev, "unable to obtain PCIv3 base\n");
875 return -ENODEV;
876 }
877 pci_v3_base = devm_ioremap(&pdev->dev, res->start,
878 resource_size(res));
879 if (!pci_v3_base) {
880 dev_err(&pdev->dev, "unable to remap PCIv3 base\n");
881 return -ENODEV;
882 }
883
884 /* Get and request error IRQ resource */
885 irq = platform_get_irq(pdev, 0);
886 if (irq <= 0) {
887 dev_err(&pdev->dev, "unable to obtain PCIv3 error IRQ\n");
888 return -ENODEV;
889 }
890 ret = devm_request_irq(&pdev->dev, irq, v3_irq, 0,
891 "PCIv3 error", NULL);
892 if (ret < 0) {
893 dev_err(&pdev->dev, "unable to request PCIv3 error IRQ %d (%d)\n", irq, ret);
894 return ret;
895 }
896
897 for_each_of_pci_range(&parser, &range) {
898 if (!range.flags) {
899 of_pci_range_to_resource(&range, np, &conf_mem);
900 conf_mem.name = "PCIv3 config";
901 }
902 if (range.flags & IORESOURCE_IO) {
903 of_pci_range_to_resource(&range, np, &io_mem);
904 io_mem.name = "PCIv3 I/O";
905 }
906 if ((range.flags & IORESOURCE_MEM) &&
907 !(range.flags & IORESOURCE_PREFETCH)) {
908 of_pci_range_to_resource(&range, np, &non_mem);
909 non_mem.name = "PCIv3 non-prefetched mem";
910 }
911 if ((range.flags & IORESOURCE_MEM) &&
912 (range.flags & IORESOURCE_PREFETCH)) {
913 of_pci_range_to_resource(&range, np, &pre_mem);
914 pre_mem.name = "PCIv3 prefetched mem";
915 }
916 }
917
918 if (!conf_mem.start || !io_mem.start ||
919 !non_mem.start || !pre_mem.start) {
920 dev_err(&pdev->dev, "missing ranges in device node\n");
921 return -EINVAL;
922 }
923
924 pci_v3.map_irq = pci_v3_map_irq_dt;
925 pci_common_init_dev(&pdev->dev, &pci_v3);
926
927 return 0;
928}
929
930#else
931
932static inline int pci_v3_dtprobe(struct platform_device *pdev,
933 struct device_node *np)
934{
935 return -EINVAL;
936}
937
938#endif
939
940static int __init pci_v3_probe(struct platform_device *pdev)
941{
942 struct device_node *np = pdev->dev.of_node;
943 int ret;
944
945 /* Remap the Integrator system controller */
946 ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
947 if (!ap_syscon_base) {
948 dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n");
949 return -ENODEV;
950 }
951
952 /* Device tree probe path */
953 if (np)
954 return pci_v3_dtprobe(pdev, np);
955
956 pci_v3_base = devm_ioremap(&pdev->dev, PHYS_PCI_V3_BASE, SZ_64K);
957 if (!pci_v3_base) {
958 dev_err(&pdev->dev, "unable to remap PCIv3 base\n");
959 return -ENODEV;
960 }
961
962 ret = devm_request_irq(&pdev->dev, IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
963 if (ret) {
964 dev_err(&pdev->dev, "unable to grab PCI error interrupt: %d\n",
965 ret);
966 return -ENODEV;
967 }
968
969 conf_mem.name = "PCIv3 config";
970 conf_mem.start = PHYS_PCI_CONFIG_BASE;
971 conf_mem.end = PHYS_PCI_CONFIG_BASE + SZ_16M - 1;
972 conf_mem.flags = IORESOURCE_MEM;
973
974 io_mem.name = "PCIv3 I/O";
975 io_mem.start = PHYS_PCI_IO_BASE;
976 io_mem.end = PHYS_PCI_IO_BASE + SZ_16M - 1;
977 io_mem.flags = IORESOURCE_MEM;
978
979 non_mem.name = "PCIv3 non-prefetched mem";
980 non_mem.start = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START;
981 non_mem.end = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START +
982 PCI_BUS_NONMEM_SIZE - 1;
983 non_mem.flags = IORESOURCE_MEM;
984
985 pre_mem.name = "PCIv3 prefetched mem";
986 pre_mem.start = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START;
987 pre_mem.end = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START +
988 PCI_BUS_PREMEM_SIZE - 1;
989 pre_mem.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
990
991 pci_v3.map_irq = pci_v3_map_irq;
992
993 pci_common_init_dev(&pdev->dev, &pci_v3);
994
995 return 0;
996}
997
998static const struct of_device_id pci_ids[] = {
999 { .compatible = "v3,v360epc-pci", },
1000 {},
1001};
1002
1003static struct platform_driver pci_v3_driver = {
1004 .driver = {
1005 .name = "pci-v3",
1006 .of_match_table = pci_ids,
1007 },
1008};
1009
1010static int __init pci_v3_init(void)
1011{
1012 return platform_driver_probe(&pci_v3_driver, pci_v3_probe);
1013}
1014
1015subsys_initcall(pci_v3_init);
1016
1017/*
1018 * Static mappings for the PCIv3 bridge
1019 *
1020 * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
1021 * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
1022 * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
1023 */
1024static struct map_desc pci_v3_io_desc[] __initdata __maybe_unused = {
1025 {
1026 .virtual = (unsigned long)PCI_MEMORY_VADDR,
1027 .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
1028 .length = SZ_16M,
1029 .type = MT_DEVICE
1030 }, {
1031 .virtual = (unsigned long)PCI_CONFIG_VADDR,
1032 .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
1033 .length = SZ_16M,
1034 .type = MT_DEVICE
1035 }
1036};
1037
1038int __init pci_v3_early_init(void)
1039{
1040 iotable_init(pci_v3_io_desc, ARRAY_SIZE(pci_v3_io_desc));
1041 vga_base = (unsigned long)PCI_MEMORY_VADDR;
1042 pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
1043 return 0;
612} 1044}
diff --git a/arch/arm/mach-integrator/pci_v3.h b/arch/arm/mach-integrator/pci_v3.h
new file mode 100644
index 000000000000..755fd29fed4a
--- /dev/null
+++ b/arch/arm/mach-integrator/pci_v3.h
@@ -0,0 +1,2 @@
1/* Simple oneliner include to the PCIv3 early init */
2extern int pci_v3_early_init(void);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 13:06:32 -0500