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authorPaul Walmsley <paul@pwsan.com>2008-03-18 04:04:51 -0400
committerTony Lindgren <tony@atomide.com>2008-04-14 13:29:37 -0400
commit445959821f82846913fe09fee0573e0238415e8c (patch)
tree38d0ec8fd827017e21961a42a58a9bcaaede7c6e /arch/arm
parentc595713da76bc7cedddf5135072ea6037cc0befb (diff)
ARM: OMAP2: Change 24xx to use new register access
This patch changes 24xx to use new register access, except for clock framework. Clock framework register access will get updates in the next patch. Note that board-*.c files change GPMC (General Purpose Memory Controller) access to use gpmc_cs_write_reg() instead of accessing the registers directly. The code also uses gpmc_fck instead of it's parent clock core_l3_ck for GPMC clock. The H4 board file also adds h4_init_flash() function, which specify the flash start and end addresses. Also note that sleep.S removes some unused registers addresses. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c23
-rw-r--r--arch/arm/mach-omap2/board-apollon.c60
-rw-r--r--arch/arm/mach-omap2/board-h4.c111
-rw-r--r--arch/arm/mach-omap2/gpmc.c12
-rw-r--r--arch/arm/mach-omap2/memory.c26
-rw-r--r--arch/arm/mach-omap2/mux.c10
-rw-r--r--arch/arm/mach-omap2/prcm-regs.h14
-rw-r--r--arch/arm/mach-omap2/prcm.c14
-rw-r--r--arch/arm/mach-omap2/sleep.S23
-rw-r--r--arch/arm/mach-omap2/sram-fn.S42
-rw-r--r--arch/arm/plat-omap/common.c47
11 files changed, 282 insertions, 100 deletions
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 64235dee5614..1c12d7c6c7fc 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -33,7 +33,6 @@
33#include <asm/arch/board.h> 33#include <asm/arch/board.h>
34#include <asm/arch/common.h> 34#include <asm/arch/common.h>
35#include <asm/arch/gpmc.h> 35#include <asm/arch/gpmc.h>
36#include "prcm-regs.h"
37 36
38#include <asm/io.h> 37#include <asm/io.h>
39 38
@@ -125,15 +124,18 @@ static inline void __init sdp2430_init_smc91x(void)
125 int eth_cs; 124 int eth_cs;
126 unsigned long cs_mem_base; 125 unsigned long cs_mem_base;
127 unsigned int rate; 126 unsigned int rate;
128 struct clk *l3ck; 127 struct clk *gpmc_fck;
129 128
130 eth_cs = SDP2430_SMC91X_CS; 129 eth_cs = SDP2430_SMC91X_CS;
131 130
132 l3ck = clk_get(NULL, "core_l3_ck"); 131 gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
133 if (IS_ERR(l3ck)) 132 if (IS_ERR(gpmc_fck)) {
134 rate = 100000000; 133 WARN_ON(1);
135 else 134 return;
136 rate = clk_get_rate(l3ck); 135 }
136
137 clk_enable(gpmc_fck);
138 rate = clk_get_rate(gpmc_fck);
137 139
138 /* Make sure CS1 timings are correct, for 2430 always muxed */ 140 /* Make sure CS1 timings are correct, for 2430 always muxed */
139 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200); 141 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
@@ -160,7 +162,7 @@ static inline void __init sdp2430_init_smc91x(void)
160 162
161 if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) { 163 if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
162 printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); 164 printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
163 return; 165 goto out;
164 } 166 }
165 167
166 sdp2430_smc91x_resources[0].start = cs_mem_base + 0x300; 168 sdp2430_smc91x_resources[0].start = cs_mem_base + 0x300;
@@ -171,10 +173,13 @@ static inline void __init sdp2430_init_smc91x(void)
171 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", 173 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
172 OMAP24XX_ETHR_GPIO_IRQ); 174 OMAP24XX_ETHR_GPIO_IRQ);
173 gpmc_cs_free(eth_cs); 175 gpmc_cs_free(eth_cs);
174 return; 176 goto out;
175 } 177 }
176 omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1); 178 omap_set_gpio_direction(OMAP24XX_ETHR_GPIO_IRQ, 1);
177 179
180out:
181 clk_disable(gpmc_fck);
182 clk_put(gpmc_fck);
178} 183}
179 184
180static void __init omap_2430sdp_init_irq(void) 185static void __init omap_2430sdp_init_irq(void)
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 7846551f0575..a1e1e6765b5b 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -26,6 +26,8 @@
26#include <linux/interrupt.h> 26#include <linux/interrupt.h>
27#include <linux/delay.h> 27#include <linux/delay.h>
28#include <linux/leds.h> 28#include <linux/leds.h>
29#include <linux/err.h>
30#include <linux/clk.h>
29 31
30#include <asm/hardware.h> 32#include <asm/hardware.h>
31#include <asm/mach-types.h> 33#include <asm/mach-types.h>
@@ -39,7 +41,7 @@
39#include <asm/arch/board.h> 41#include <asm/arch/board.h>
40#include <asm/arch/common.h> 42#include <asm/arch/common.h>
41#include <asm/arch/gpmc.h> 43#include <asm/arch/gpmc.h>
42#include "prcm-regs.h" 44#include <asm/arch/control.h>
43 45
44/* LED & Switch macros */ 46/* LED & Switch macros */
45#define LED0_GPIO13 13 47#define LED0_GPIO13 13
@@ -187,17 +189,47 @@ static inline void __init apollon_init_smc91x(void)
187{ 189{
188 unsigned long base; 190 unsigned long base;
189 191
192 unsigned int rate;
193 struct clk *gpmc_fck;
194 int eth_cs;
195
196 gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
197 if (IS_ERR(gpmc_fck)) {
198 WARN_ON(1);
199 return;
200 }
201
202 clk_enable(gpmc_fck);
203 rate = clk_get_rate(gpmc_fck);
204
205 eth_cs = APOLLON_ETH_CS;
206
190 /* Make sure CS1 timings are correct */ 207 /* Make sure CS1 timings are correct */
191 GPMC_CONFIG1_1 = 0x00011203; 208 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200);
192 GPMC_CONFIG2_1 = 0x001f1f01; 209
193 GPMC_CONFIG3_1 = 0x00080803; 210 if (rate >= 160000000) {
194 GPMC_CONFIG4_1 = 0x1c091c09; 211 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
195 GPMC_CONFIG5_1 = 0x041f1f1f; 212 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
196 GPMC_CONFIG6_1 = 0x000004c4; 213 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
214 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
215 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
216 } else if (rate >= 130000000) {
217 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
218 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
219 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
220 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
221 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
222 } else {/* rate = 100000000 */
223 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
224 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
225 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
226 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
227 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
228 }
197 229
198 if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) { 230 if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) {
199 printk(KERN_ERR "Failed to request GPMC CS for smc91x\n"); 231 printk(KERN_ERR "Failed to request GPMC CS for smc91x\n");
200 return; 232 goto out;
201 } 233 }
202 apollon_smc91x_resources[0].start = base + 0x300; 234 apollon_smc91x_resources[0].start = base + 0x300;
203 apollon_smc91x_resources[0].end = base + 0x30f; 235 apollon_smc91x_resources[0].end = base + 0x30f;
@@ -208,9 +240,13 @@ static inline void __init apollon_init_smc91x(void)
208 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", 240 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
209 APOLLON_ETHR_GPIO_IRQ); 241 APOLLON_ETHR_GPIO_IRQ);
210 gpmc_cs_free(APOLLON_ETH_CS); 242 gpmc_cs_free(APOLLON_ETH_CS);
211 return; 243 goto out;
212 } 244 }
213 omap_set_gpio_direction(APOLLON_ETHR_GPIO_IRQ, 1); 245 omap_set_gpio_direction(APOLLON_ETHR_GPIO_IRQ, 1);
246
247out:
248 clk_disable(gpmc_fck);
249 clk_put(gpmc_fck);
214} 250}
215 251
216static void __init omap_apollon_init_irq(void) 252static void __init omap_apollon_init_irq(void)
@@ -330,6 +366,8 @@ static void __init apollon_usb_init(void)
330 366
331static void __init omap_apollon_init(void) 367static void __init omap_apollon_init(void)
332{ 368{
369 u32 v;
370
333 apollon_led_init(); 371 apollon_led_init();
334 apollon_sw_init(); 372 apollon_sw_init();
335 apollon_flash_init(); 373 apollon_flash_init();
@@ -339,7 +377,9 @@ static void __init omap_apollon_init(void)
339 omap_cfg_reg(W19_24XX_SYS_NIRQ); 377 omap_cfg_reg(W19_24XX_SYS_NIRQ);
340 378
341 /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */ 379 /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */
342 CONTROL_DEVCONF |= (1 << 24); 380 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
381 v |= (1 << 24);
382 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
343 383
344 /* 384 /*
345 * Make sure the serial ports are muxed on at this point. 385 * Make sure the serial ports are muxed on at this point.
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index f125f432cc3e..d1915f99a5fa 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -19,6 +19,8 @@
19#include <linux/delay.h> 19#include <linux/delay.h>
20#include <linux/workqueue.h> 20#include <linux/workqueue.h>
21#include <linux/input.h> 21#include <linux/input.h>
22#include <linux/err.h>
23#include <linux/clk.h>
22 24
23#include <asm/hardware.h> 25#include <asm/hardware.h>
24#include <asm/mach-types.h> 26#include <asm/mach-types.h>
@@ -26,6 +28,7 @@
26#include <asm/mach/map.h> 28#include <asm/mach/map.h>
27#include <asm/mach/flash.h> 29#include <asm/mach/flash.h>
28 30
31#include <asm/arch/control.h>
29#include <asm/arch/gpio.h> 32#include <asm/arch/gpio.h>
30#include <asm/arch/gpioexpander.h> 33#include <asm/arch/gpioexpander.h>
31#include <asm/arch/mux.h> 34#include <asm/arch/mux.h>
@@ -36,10 +39,13 @@
36#include <asm/arch/keypad.h> 39#include <asm/arch/keypad.h>
37#include <asm/arch/menelaus.h> 40#include <asm/arch/menelaus.h>
38#include <asm/arch/dma.h> 41#include <asm/arch/dma.h>
39#include "prcm-regs.h" 42#include <asm/arch/gpmc.h>
40 43
41#include <asm/io.h> 44#include <asm/io.h>
42 45
46#define H4_FLASH_CS 0
47#define H4_SMC91X_CS 1
48
43static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 }; 49static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 };
44static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 }; 50static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 };
45 51
@@ -116,8 +122,6 @@ static struct flash_platform_data h4_flash_data = {
116}; 122};
117 123
118static struct resource h4_flash_resource = { 124static struct resource h4_flash_resource = {
119 .start = H4_CS0_BASE,
120 .end = H4_CS0_BASE + SZ_64M - 1,
121 .flags = IORESOURCE_MEM, 125 .flags = IORESOURCE_MEM,
122}; 126};
123 127
@@ -253,21 +257,107 @@ static struct platform_device *h4_devices[] __initdata = {
253 &h4_lcd_device, 257 &h4_lcd_device,
254}; 258};
255 259
260/* 2420 Sysboot setup (2430 is different) */
261static u32 get_sysboot_value(void)
262{
263 return (omap_ctrl_readl(OMAP24XX_CONTROL_STATUS) &
264 (OMAP2_SYSBOOT_5_MASK | OMAP2_SYSBOOT_4_MASK |
265 OMAP2_SYSBOOT_3_MASK | OMAP2_SYSBOOT_2_MASK |
266 OMAP2_SYSBOOT_1_MASK | OMAP2_SYSBOOT_0_MASK));
267}
268
269/* H4-2420's always used muxed mode, H4-2422's always use non-muxed
270 *
271 * Note: OMAP-GIT doesn't correctly do is_cpu_omap2422 and is_cpu_omap2423
272 * correctly. The macro needs to look at production_id not just hawkeye.
273 */
274static u32 is_gpmc_muxed(void)
275{
276 u32 mux;
277 mux = get_sysboot_value();
278 if ((mux & 0xF) == 0xd)
279 return 1; /* NAND config (could be either) */
280 if (mux & 0x2) /* if mux'ed */
281 return 1;
282 else
283 return 0;
284}
285
256static inline void __init h4_init_debug(void) 286static inline void __init h4_init_debug(void)
257{ 287{
288 int eth_cs;
289 unsigned long cs_mem_base;
290 unsigned int muxed, rate;
291 struct clk *gpmc_fck;
292
293 eth_cs = H4_SMC91X_CS;
294
295 gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
296 if (IS_ERR(gpmc_fck)) {
297 WARN_ON(1);
298 return;
299 }
300
301 clk_enable(gpmc_fck);
302 rate = clk_get_rate(gpmc_fck);
303 clk_disable(gpmc_fck);
304 clk_put(gpmc_fck);
305
306 if (is_gpmc_muxed())
307 muxed = 0x200;
308 else
309 muxed = 0;
310
258 /* Make sure CS1 timings are correct */ 311 /* Make sure CS1 timings are correct */
259 GPMC_CONFIG1_1 = 0x00011200; 312 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1,
260 GPMC_CONFIG2_1 = 0x001f1f01; 313 0x00011000 | muxed);
261 GPMC_CONFIG3_1 = 0x00080803; 314
262 GPMC_CONFIG4_1 = 0x1c091c09; 315 if (rate >= 160000000) {
263 GPMC_CONFIG5_1 = 0x041f1f1f; 316 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01);
264 GPMC_CONFIG6_1 = 0x000004c4; 317 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803);
265 GPMC_CONFIG7_1 = 0x00000f40 | (0x08000000 >> 24); 318 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a);
319 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
320 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
321 } else if (rate >= 130000000) {
322 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
323 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
324 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
325 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F);
326 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4);
327 } else {/* rate = 100000000 */
328 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00);
329 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802);
330 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09);
331 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F);
332 gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2);
333 }
334
335 if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
336 printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
337 goto out;
338 }
339
266 udelay(100); 340 udelay(100);
267 341
268 omap_cfg_reg(M15_24XX_GPIO92); 342 omap_cfg_reg(M15_24XX_GPIO92);
269 if (debug_card_init(cs_mem_base, OMAP24XX_ETHR_GPIO_IRQ) < 0) 343 if (debug_card_init(cs_mem_base, OMAP24XX_ETHR_GPIO_IRQ) < 0)
270 gpmc_cs_free(eth_cs); 344 gpmc_cs_free(eth_cs);
345
346out:
347 clk_disable(gpmc_fck);
348 clk_put(gpmc_fck);
349}
350
351static void __init h4_init_flash(void)
352{
353 unsigned long base;
354
355 if (gpmc_cs_request(H4_FLASH_CS, SZ_64M, &base) < 0) {
356 printk("Can't request GPMC CS for flash\n");
357 return;
358 }
359 h4_flash_resource.start = base;
360 h4_flash_resource.end = base + SZ_64M - 1;
271} 361}
272 362
273static void __init omap_h4_init_irq(void) 363static void __init omap_h4_init_irq(void)
@@ -275,6 +365,7 @@ static void __init omap_h4_init_irq(void)
275 omap2_init_common_hw(); 365 omap2_init_common_hw();
276 omap_init_irq(); 366 omap_init_irq();
277 omap_gpio_init(); 367 omap_gpio_init();
368 h4_init_flash();
278} 369}
279 370
280static struct omap_uart_config h4_uart_config __initdata = { 371static struct omap_uart_config h4_uart_config __initdata = {
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 5a4cc2076a7d..02cede295e89 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -69,7 +69,7 @@ static void __iomem *gpmc_base =
69static void __iomem *gpmc_cs_base = 69static void __iomem *gpmc_cs_base =
70 (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0; 70 (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
71 71
72static struct clk *gpmc_l3_clk; 72static struct clk *gpmc_fck;
73 73
74static void gpmc_write_reg(int idx, u32 val) 74static void gpmc_write_reg(int idx, u32 val)
75{ 75{
@@ -94,11 +94,10 @@ u32 gpmc_cs_read_reg(int cs, int idx)
94 return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx); 94 return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
95} 95}
96 96
97/* TODO: Add support for gpmc_fck to clock framework and use it */
98unsigned long gpmc_get_fclk_period(void) 97unsigned long gpmc_get_fclk_period(void)
99{ 98{
100 /* In picoseconds */ 99 /* In picoseconds */
101 return 1000000000 / ((clk_get_rate(gpmc_l3_clk)) / 1000); 100 return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000);
102} 101}
103 102
104unsigned int gpmc_ns_to_ticks(unsigned int time_ns) 103unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
@@ -398,8 +397,11 @@ void __init gpmc_init(void)
398{ 397{
399 u32 l; 398 u32 l;
400 399
401 gpmc_l3_clk = clk_get(NULL, "core_l3_ck"); 400 gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */
402 BUG_ON(IS_ERR(gpmc_l3_clk)); 401 if (IS_ERR(gpmc_fck))
402 WARN_ON(1);
403 else
404 clk_enable(gpmc_fck);
403 405
404 l = gpmc_read_reg(GPMC_REVISION); 406 l = gpmc_read_reg(GPMC_REVISION);
405 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); 407 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index 3e5d8cd4ea4f..b56c1a082d92 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -27,11 +27,16 @@
27#include <asm/arch/clock.h> 27#include <asm/arch/clock.h>
28#include <asm/arch/sram.h> 28#include <asm/arch/sram.h>
29 29
30#include "prcm-regs.h" 30#include "prm.h"
31
31#include "memory.h" 32#include "memory.h"
33#include "sdrc.h"
32 34
35unsigned long omap2_sdrc_base;
36unsigned long omap2_sms_base;
33 37
34static struct memory_timings mem_timings; 38static struct memory_timings mem_timings;
39static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
35 40
36u32 omap2_memory_get_slow_dll_ctrl(void) 41u32 omap2_memory_get_slow_dll_ctrl(void)
37{ 42{
@@ -53,7 +58,7 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
53 unsigned long dll_cnt; 58 unsigned long dll_cnt;
54 u32 fast_dll = 0; 59 u32 fast_dll = 0;
55 60
56 mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */ 61 mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
57 62
58 /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others. 63 /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
59 * In the case of 2422, its ok to use CS1 instead of CS0. 64 * In the case of 2422, its ok to use CS1 instead of CS0.
@@ -73,11 +78,11 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
73 mem_timings.dll_mode = M_LOCK; 78 mem_timings.dll_mode = M_LOCK;
74 79
75 if (mem_timings.base_cs == 0) { 80 if (mem_timings.base_cs == 0) {
76 fast_dll = SDRC_DLLA_CTRL; 81 fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
77 dll_cnt = SDRC_DLLA_STATUS & 0xff00; 82 dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
78 } else { 83 } else {
79 fast_dll = SDRC_DLLB_CTRL; 84 fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
80 dll_cnt = SDRC_DLLB_STATUS & 0xff00; 85 dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
81 } 86 }
82 if (force_lock_to_unlock_mode) { 87 if (force_lock_to_unlock_mode) {
83 fast_dll &= ~0xff00; 88 fast_dll &= ~0xff00;
@@ -106,14 +111,13 @@ void __init omap2_init_memory(void)
106{ 111{
107 u32 l; 112 u32 l;
108 113
109 l = SMS_SYSCONFIG; 114 l = sms_read_reg(SMS_SYSCONFIG);
110 l &= ~(0x3 << 3); 115 l &= ~(0x3 << 3);
111 l |= (0x2 << 3); 116 l |= (0x2 << 3);
112 SMS_SYSCONFIG = l; 117 sms_write_reg(l, SMS_SYSCONFIG);
113 118
114 l = SDRC_SYSCONFIG; 119 l = sdrc_read_reg(SDRC_SYSCONFIG);
115 l &= ~(0x3 << 3); 120 l &= ~(0x3 << 3);
116 l |= (0x2 << 3); 121 l |= (0x2 << 3);
117 SDRC_SYSCONFIG = l; 122 sdrc_write_reg(l, SDRC_SYSCONFIG);
118
119} 123}
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 0cf7562ff88f..930770012a75 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -29,6 +29,7 @@
29#include <asm/io.h> 29#include <asm/io.h>
30#include <linux/spinlock.h> 30#include <linux/spinlock.h>
31 31
32#include <asm/arch/control.h>
32#include <asm/arch/mux.h> 33#include <asm/arch/mux.h>
33 34
34#ifdef CONFIG_OMAP_MUX 35#ifdef CONFIG_OMAP_MUX
@@ -218,18 +219,16 @@ MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1)
218#define OMAP24XX_PINS_SZ 0 219#define OMAP24XX_PINS_SZ 0
219#endif /* CONFIG_ARCH_OMAP24XX */ 220#endif /* CONFIG_ARCH_OMAP24XX */
220 221
221#define OMAP24XX_L4_BASE 0x48000000
222#define OMAP24XX_PULL_ENA (1 << 3) 222#define OMAP24XX_PULL_ENA (1 << 3)
223#define OMAP24XX_PULL_UP (1 << 4) 223#define OMAP24XX_PULL_UP (1 << 4)
224 224
225/* REVISIT: Convert this code to use ctrl_{read,write}_reg */
226#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) 225#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
227void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg) 226void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg)
228{ 227{
229 u16 orig; 228 u16 orig;
230 u8 warn = 0, debug = 0; 229 u8 warn = 0, debug = 0;
231 230
232 orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg); 231 orig = omap_ctrl_readb(cfg->mux_reg);
233 232
234#ifdef CONFIG_OMAP_MUX_DEBUG 233#ifdef CONFIG_OMAP_MUX_DEBUG
235 debug = cfg->debug; 234 debug = cfg->debug;
@@ -238,7 +237,8 @@ void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg)
238 if (debug || warn) 237 if (debug || warn)
239 printk(KERN_WARNING 238 printk(KERN_WARNING
240 "MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n", 239 "MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
241 cfg->name, omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg)); 240 cfg->name, omap_ctrl_base_get() + cfg->mux_reg,
241 orig, reg);
242} 242}
243#else 243#else
244#define omap2_cfg_debug(x, y) do {} while (0) 244#define omap2_cfg_debug(x, y) do {} while (0)
@@ -258,7 +258,7 @@ int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
258 if (cfg->pu_pd_val) 258 if (cfg->pu_pd_val)
259 reg |= OMAP24XX_PULL_UP; 259 reg |= OMAP24XX_PULL_UP;
260 omap2_cfg_debug(cfg, reg); 260 omap2_cfg_debug(cfg, reg);
261 omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg); 261 omap_ctrl_writeb(reg, cfg->mux_reg);
262 spin_unlock_irqrestore(&mux_spin_lock, flags); 262 spin_unlock_irqrestore(&mux_spin_lock, flags);
263 263
264 return 0; 264 return 0;
diff --git a/arch/arm/mach-omap2/prcm-regs.h b/arch/arm/mach-omap2/prcm-regs.h
index 5e1c4b53ee9d..c7f6cfa0b485 100644
--- a/arch/arm/mach-omap2/prcm-regs.h
+++ b/arch/arm/mach-omap2/prcm-regs.h
@@ -23,6 +23,20 @@
23#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_H 23#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_H
24#define __ARCH_ARM_MACH_OMAP2_PRCM_H 24#define __ARCH_ARM_MACH_OMAP2_PRCM_H
25 25
26#ifdef CONFIG_ARCH_OMAP2420
27#define OMAP24XX_32KSYNCT_BASE (L4_24XX_BASE + 0x4000)
28#define OMAP24XX_PRCM_BASE (L4_24XX_BASE + 0x8000)
29#define OMAP24XX_SDRC_BASE (L3_24XX_BASE + 0x9000)
30#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8)
31#endif
32
33#ifdef CONFIG_ARCH_OMAP2430
34#define OMAP24XX_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
35#define OMAP24XX_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
36#define OMAP24XX_SDRC_BASE (0x6D000000)
37#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8)
38#endif
39
26/* SET_PERFORMANCE_LEVEL PARAMETERS */ 40/* SET_PERFORMANCE_LEVEL PARAMETERS */
27#define PRCM_HALF_SPEED 1 41#define PRCM_HALF_SPEED 1
28#define PRCM_FULL_SPEED 2 42#define PRCM_FULL_SPEED 2
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 90f530540c65..b12f423b8595 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -17,19 +17,27 @@
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/clk.h> 18#include <linux/clk.h>
19 19
20#include "prcm-regs.h" 20#include <asm/io.h>
21
22#include "prm.h"
23#include "prm-regbits-24xx.h"
21 24
22extern void omap2_clk_prepare_for_reboot(void); 25extern void omap2_clk_prepare_for_reboot(void);
23 26
24u32 omap_prcm_get_reset_sources(void) 27u32 omap_prcm_get_reset_sources(void)
25{ 28{
26 return RM_RSTST_WKUP & 0x7f; 29 return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f;
27} 30}
28EXPORT_SYMBOL(omap_prcm_get_reset_sources); 31EXPORT_SYMBOL(omap_prcm_get_reset_sources);
29 32
30/* Resets clock rates and reboots the system. Only called from system.h */ 33/* Resets clock rates and reboots the system. Only called from system.h */
31void omap_prcm_arch_reset(char mode) 34void omap_prcm_arch_reset(char mode)
32{ 35{
36 u32 wkup;
33 omap2_clk_prepare_for_reboot(); 37 omap2_clk_prepare_for_reboot();
34 RM_RSTCTRL_WKUP |= 2; 38
39 if (cpu_is_omap24xx()) {
40 wkup = prm_read_mod_reg(WKUP_MOD, RM_RSTCTRL) | OMAP_RST_DPLL3;
41 prm_write_mod_reg(wkup, WKUP_MOD, RM_RSTCTRL);
42 }
35} 43}
diff --git a/arch/arm/mach-omap2/sleep.S b/arch/arm/mach-omap2/sleep.S
index 16247d557853..46ccb9b8b583 100644
--- a/arch/arm/mach-omap2/sleep.S
+++ b/arch/arm/mach-omap2/sleep.S
@@ -26,19 +26,10 @@
26#include <asm/arch/io.h> 26#include <asm/arch/io.h>
27#include <asm/arch/pm.h> 27#include <asm/arch/pm.h>
28 28
29#define A_32KSYNC_CR_V IO_ADDRESS(OMAP_TIMER32K_BASE+0x10) 29#include "sdrc.h"
30#define A_PRCM_VOLTCTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x50)
31#define A_PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x80)
32#define A_CM_CLKEN_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x500)
33#define A_CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x520)
34#define A_CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x540)
35#define A_CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE+0x544)
36 30
37#define A_SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0x60) 31/* First address of reserved address space? apparently valid for OMAP2 & 3 */
38#define A_SDRC_POWER_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0x70)
39#define A_SDRC_RFR_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA4)
40#define A_SDRC0_V (0xC0000000) 32#define A_SDRC0_V (0xC0000000)
41#define A_SDRC_MANUAL_V IO_ADDRESS(OMAP24XX_SDRC_BASE+0xA8)
42 33
43 .text 34 .text
44 35
@@ -126,17 +117,11 @@ loop2:
126 ldmfd sp!, {r0 - r12, pc} @ restore regs and return 117 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
127 118
128A_SDRC_POWER: 119A_SDRC_POWER:
129 .word A_SDRC_POWER_V 120 .word OMAP242X_SDRC_REGADDR(SDRC_POWER)
130A_SDRC0: 121A_SDRC0:
131 .word A_SDRC0_V 122 .word A_SDRC0_V
132A_CM_CLKSEL2_PLL_S:
133 .word A_CM_CLKSEL2_PLL_V
134A_CM_CLKEN_PLL:
135 .word A_CM_CLKEN_PLL_V
136A_SDRC_DLLA_CTRL_S: 123A_SDRC_DLLA_CTRL_S:
137 .word A_SDRC_DLLA_CTRL_V 124 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
138A_SDRC_MANUAL_S:
139 .word A_SDRC_MANUAL_V
140 125
141ENTRY(omap24xx_cpu_suspend_sz) 126ENTRY(omap24xx_cpu_suspend_sz)
142 .word . - omap24xx_cpu_suspend 127 .word . - omap24xx_cpu_suspend
diff --git a/arch/arm/mach-omap2/sram-fn.S b/arch/arm/mach-omap2/sram-fn.S
index b27576690f8d..4a9e49140716 100644
--- a/arch/arm/mach-omap2/sram-fn.S
+++ b/arch/arm/mach-omap2/sram-fn.S
@@ -27,19 +27,11 @@
27#include <asm/arch/io.h> 27#include <asm/arch/io.h>
28#include <asm/hardware.h> 28#include <asm/hardware.h>
29 29
30#include "prcm-regs.h" 30#include "sdrc.h"
31#include "prm.h"
32#include "cm.h"
31 33
32#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP24XX_32KSYNCT_BASE + 0x010) 34#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
33
34#define CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x544)
35#define PRCM_VOLTCTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x050)
36#define PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x080)
37#define CM_CLKEN_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x500)
38#define CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x520)
39#define CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x540)
40
41#define SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x060)
42#define SDRC_RFR_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x0a4)
43 35
44 .text 36 .text
45 37
@@ -131,11 +123,11 @@ volt_delay:
131 123
132/* relative load constants */ 124/* relative load constants */
133cm_clksel2_pll: 125cm_clksel2_pll:
134 .word CM_CLKSEL2_PLL_V 126 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
135sdrc_dlla_ctrl: 127sdrc_dlla_ctrl:
136 .word SDRC_DLLA_CTRL_V 128 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
137prcm_voltctrl: 129prcm_voltctrl:
138 .word PRCM_VOLTCTRL_V 130 .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50)
139prcm_mask_val: 131prcm_mask_val:
140 .word 0xFFFF3FFC 132 .word 0xFFFF3FFC
141timer_32ksynct_cr: 133timer_32ksynct_cr:
@@ -225,13 +217,13 @@ volt_delay_c:
225 mov pc, lr @ back to caller 217 mov pc, lr @ back to caller
226 218
227ddr_cm_clksel2_pll: 219ddr_cm_clksel2_pll:
228 .word CM_CLKSEL2_PLL_V 220 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
229ddr_sdrc_dlla_ctrl: 221ddr_sdrc_dlla_ctrl:
230 .word SDRC_DLLA_CTRL_V 222 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
231ddr_sdrc_rfr_ctrl: 223ddr_sdrc_rfr_ctrl:
232 .word SDRC_RFR_CTRL_V 224 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
233ddr_prcm_voltctrl: 225ddr_prcm_voltctrl:
234 .word PRCM_VOLTCTRL_V 226 .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50)
235ddr_prcm_mask_val: 227ddr_prcm_mask_val:
236 .word 0xFFFF3FFC 228 .word 0xFFFF3FFC
237ddr_timer_32ksynct: 229ddr_timer_32ksynct:
@@ -316,17 +308,17 @@ wait_dll_lock:
316 ldmfd sp!, {r0-r12, pc} @ restore regs and return 308 ldmfd sp!, {r0-r12, pc} @ restore regs and return
317 309
318set_config: 310set_config:
319 .word PRCM_CLKCFG_CTRL_V 311 .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x80)
320pll_ctl: 312pll_ctl:
321 .word CM_CLKEN_PLL_V 313 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_FCLKEN1)
322pll_stat: 314pll_stat:
323 .word CM_IDLEST_CKGEN_V 315 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST1)
324pll_div: 316pll_div:
325 .word CM_CLKSEL1_PLL_V 317 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL)
326sdrc_rfr: 318sdrc_rfr:
327 .word SDRC_RFR_CTRL_V 319 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
328dlla_ctrl: 320dlla_ctrl:
329 .word SDRC_DLLA_CTRL_V 321 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
330 322
331ENTRY(sram_set_prcm_sz) 323ENTRY(sram_set_prcm_sz)
332 .word . - sram_set_prcm 324 .word . - sram_set_prcm
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 7f1cae16cfad..bd1cef2c3c14 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -27,11 +27,16 @@
27#include <asm/setup.h> 27#include <asm/setup.h>
28 28
29#include <asm/arch/board.h> 29#include <asm/arch/board.h>
30#include <asm/arch/control.h>
30#include <asm/arch/mux.h> 31#include <asm/arch/mux.h>
31#include <asm/arch/fpga.h> 32#include <asm/arch/fpga.h>
32 33
33#include <asm/arch/clock.h> 34#include <asm/arch/clock.h>
34 35
36#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
37# include "../mach-omap2/sdrc.h"
38#endif
39
35#define NO_LENGTH_CHECK 0xffffffff 40#define NO_LENGTH_CHECK 0xffffffff
36 41
37unsigned char omap_bootloader_tag[512]; 42unsigned char omap_bootloader_tag[512];
@@ -171,8 +176,8 @@ console_initcall(omap_add_serial_console);
171 176
172#if defined(CONFIG_ARCH_OMAP16XX) 177#if defined(CONFIG_ARCH_OMAP16XX)
173#define TIMER_32K_SYNCHRONIZED 0xfffbc410 178#define TIMER_32K_SYNCHRONIZED 0xfffbc410
174#elif defined(CONFIG_ARCH_OMAP24XX) 179#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
175#define TIMER_32K_SYNCHRONIZED (OMAP24XX_32KSYNCT_BASE + 0x10) 180#define TIMER_32K_SYNCHRONIZED (OMAP2_32KSYNCT_BASE + 0x10)
176#endif 181#endif
177 182
178#ifdef TIMER_32K_SYNCHRONIZED 183#ifdef TIMER_32K_SYNCHRONIZED
@@ -215,7 +220,13 @@ static int __init omap_init_clocksource_32k(void)
215 static char err[] __initdata = KERN_ERR 220 static char err[] __initdata = KERN_ERR
216 "%s: can't register clocksource!\n"; 221 "%s: can't register clocksource!\n";
217 222
218 if (cpu_is_omap16xx() || cpu_is_omap24xx()) { 223 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
224 struct clk *sync_32k_ick;
225
226 sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
227 if (sync_32k_ick)
228 clk_enable(sync_32k_ick);
229
219 clocksource_32k.mult = clocksource_hz2mult(32768, 230 clocksource_32k.mult = clocksource_hz2mult(32768,
220 clocksource_32k.shift); 231 clocksource_32k.shift);
221 232
@@ -227,3 +238,33 @@ static int __init omap_init_clocksource_32k(void)
227arch_initcall(omap_init_clocksource_32k); 238arch_initcall(omap_init_clocksource_32k);
228 239
229#endif /* TIMER_32K_SYNCHRONIZED */ 240#endif /* TIMER_32K_SYNCHRONIZED */
241
242/* Global address base setup code */
243
244#if defined(CONFIG_ARCH_OMAP2420)
245void __init omap2_set_globals_242x(void)
246{
247 omap2_sdrc_base = OMAP2420_SDRC_BASE;
248 omap2_sms_base = OMAP2420_SMS_BASE;
249 omap_ctrl_base_set(OMAP2420_CTRL_BASE);
250}
251#endif
252
253#if defined(CONFIG_ARCH_OMAP2430)
254void __init omap2_set_globals_243x(void)
255{
256 omap2_sdrc_base = OMAP243X_SDRC_BASE;
257 omap2_sms_base = OMAP243X_SMS_BASE;
258 omap_ctrl_base_set(OMAP243X_CTRL_BASE);
259}
260#endif
261
262#if defined(CONFIG_ARCH_OMAP3430)
263void __init omap2_set_globals_343x(void)
264{
265 omap2_sdrc_base = OMAP343X_SDRC_BASE;
266 omap2_sms_base = OMAP343X_SMS_BASE;
267 omap_ctrl_base_set(OMAP343X_CTRL_BASE);
268}
269#endif
270