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authorJoseph Lo <josephl@nvidia.com>2013-07-03 05:50:41 -0400
committerStephen Warren <swarren@nvidia.com>2013-07-19 12:08:07 -0400
commit3f1be81eef0de7193aae389663f50d38df3a3788 (patch)
tree3bff078600186eb439d7deb1c5b32590ed10443c /arch/arm
parentccea4bc654a9d5330c4488acadc3abfa4ea7ebbf (diff)
ARM: tegra: shut off the CPU rail when the last CPU in suspend
When the last CPU core in suspend, the CPU power rail can be turned off by setting flags to flow controller. Then the flow controller will inform PMC to turn off the CPU rail when the last CPU goes into suspend. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-tegra/flowctrl.h5
-rw-r--r--arch/arm/mach-tegra/pmc.c16
2 files changed, 20 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index de0acb9ee323..c89aac60a143 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -35,6 +35,11 @@
35#define FLOW_CTRL_CPU0_CSR 0x8 35#define FLOW_CTRL_CPU0_CSR 0x8
36#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15) 36#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15)
37#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14) 37#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14)
38#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13)
39#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12)
40#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
41 FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
42 FLOW_CTRL_CSR_ENABLE_EXT_CRAIL)
38#define FLOW_CTRL_CSR_ENABLE (1 << 0) 43#define FLOW_CTRL_CSR_ENABLE (1 << 0)
39#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 44#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
40#define FLOW_CTRL_CPU1_CSR 0x18 45#define FLOW_CTRL_CPU1_CSR 0x18
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index eb3fa4aee0e4..8345fcdcc9d5 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -21,6 +21,7 @@
21#include <linux/of.h> 21#include <linux/of.h>
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23 23
24#include "flowctrl.h"
24#include "fuse.h" 25#include "fuse.h"
25#include "pm.h" 26#include "pm.h"
26#include "pmc.h" 27#include "pmc.h"
@@ -195,13 +196,26 @@ enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
195 196
196void tegra_pmc_pm_set(enum tegra_suspend_mode mode) 197void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
197{ 198{
198 u32 reg; 199 u32 reg, csr_reg;
199 unsigned long rate = 0; 200 unsigned long rate = 0;
200 201
201 reg = tegra_pmc_readl(PMC_CTRL); 202 reg = tegra_pmc_readl(PMC_CTRL);
202 reg |= TEGRA_POWER_CPU_PWRREQ_OE; 203 reg |= TEGRA_POWER_CPU_PWRREQ_OE;
203 reg &= ~TEGRA_POWER_EFFECT_LP0; 204 reg &= ~TEGRA_POWER_EFFECT_LP0;
204 205
206 switch (tegra_chip_id) {
207 case TEGRA20:
208 case TEGRA30:
209 break;
210 default:
211 /* Turn off CRAIL */
212 csr_reg = flowctrl_read_cpu_csr(0);
213 csr_reg &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
214 csr_reg |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
215 flowctrl_write_cpu_csr(0, csr_reg);
216 break;
217 }
218
205 switch (mode) { 219 switch (mode) {
206 case TEGRA_SUSPEND_LP2: 220 case TEGRA_SUSPEND_LP2:
207 rate = clk_get_rate(tegra_pclk); 221 rate = clk_get_rate(tegra_pclk);