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authorOlof Johansson <olof@lixom.net>2012-09-22 17:09:21 -0400
committerOlof Johansson <olof@lixom.net>2012-09-22 17:22:47 -0400
commit0d601f613b8557cf6489f06251ae5dc383b811d0 (patch)
tree05f3a4d054e0bddc308af479918ce67cd02e8eba /arch/arm
parentd7ffa2234c186ce040e79b43639628c1c482b115 (diff)
parent5b40baee4a39d96d4d6a48a2b2383982912c429b (diff)
Merge branch 'kirkwood/addr_decode' of git://git.infradead.org/users/jcooper/linux into late/kirkwood
* 'kirkwood/addr_decode' of git://git.infradead.org/users/jcooper/linux: arm: mvebu: add address decoding controller to the DT arm: mvebu: add basic address decoding support to Armada 370/XP arm: plat-orion: make bridge_virt_base non-const to support DT use case arm: plat-orion: introduce PLAT_ORION_LEGACY hidden config option arm: plat-orion: use void __iomem pointers for addr-map functions arm: plat-orion: use void __iomem pointers for time functions arm: plat-orion: use void __iomem pointers for MPP functions arm: plat-orion: use void __iomem pointers for UART registration functions arm: mach-mvebu: use IOMEM() for base address definitions arm: mach-orion5x: use IOMEM() for base address definitions arm: mach-mv78xx0: use IOMEM() for base address definitions arm: mach-kirkwood: use IOMEM() for base address definitions arm: mach-dove: use IOMEM() for base address definitions arm: mach-orion5x: use plus instead of or for address definitions arm: mach-mv78xx0: use plus instead of or for address definitions arm: mach-kirkwood: use plus instead of or for address definitions arm: mach-dove: use plus instead of or for address definitions This branch had quite a few conflicts, in particular with the PCI static map rework from Rob Herring, and a few other context conflicts due to changes in Kconfig, etc. I fixed up conflicts in: arch/arm/Kconfig arch/arm/mach-dove/common.c arch/arm/mach-dove/include/mach/dove.h arch/arm/mach-kirkwood/common.c arch/arm/mach-kirkwood/include/mach/kirkwood.h arch/arm/mach-mv78xx0/common.c arch/arm/mach-mv78xx0/include/mach/mv78xx0.h arch/arm/mach-orion5x/common.c arch/arm/mach-orion5x/include/mach/orion5x.h Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig12
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi5
-rw-r--r--arch/arm/mach-dove/common.c4
-rw-r--r--arch/arm/mach-dove/include/mach/bridge-regs.h16
-rw-r--r--arch/arm/mach-dove/include/mach/dove.h126
-rw-r--r--arch/arm/mach-dove/irq.c10
-rw-r--r--arch/arm/mach-dove/pcie.c6
-rw-r--r--arch/arm/mach-kirkwood/addr-map.c3
-rw-r--r--arch/arm/mach-kirkwood/common.c8
-rw-r--r--arch/arm/mach-kirkwood/include/mach/bridge-regs.h20
-rw-r--r--arch/arm/mach-kirkwood/include/mach/kirkwood.h112
-rw-r--r--arch/arm/mach-kirkwood/irq.c9
-rw-r--r--arch/arm/mach-kirkwood/pcie.c12
-rw-r--r--arch/arm/mach-kirkwood/ts41x-setup.c3
-rw-r--r--arch/arm/mach-mv78xx0/addr-map.c6
-rw-r--r--arch/arm/mach-mv78xx0/common.c4
-rw-r--r--arch/arm/mach-mv78xx0/include/mach/bridge-regs.h12
-rw-r--r--arch/arm/mach-mv78xx0/include/mach/mv78xx0.h86
-rw-r--r--arch/arm/mach-mv78xx0/irq.c9
-rw-r--r--arch/arm/mach-mv78xx0/pcie.c12
-rw-r--r--arch/arm/mach-mvebu/Makefile2
-rw-r--r--arch/arm/mach-mvebu/addr-map.c134
-rw-r--r--arch/arm/mach-mvebu/armada-370-xp.c2
-rw-r--r--arch/arm/mach-mvebu/armada-370-xp.h2
-rw-r--r--arch/arm/mach-orion5x/addr-map.c3
-rw-r--r--arch/arm/mach-orion5x/common.c4
-rw-r--r--arch/arm/mach-orion5x/dns323-setup.c2
-rw-r--r--arch/arm/mach-orion5x/include/mach/bridge-regs.h20
-rw-r--r--arch/arm/mach-orion5x/include/mach/orion5x.h56
-rw-r--r--arch/arm/mach-orion5x/irq.c5
-rw-r--r--arch/arm/mach-orion5x/pci.c6
-rw-r--r--arch/arm/plat-orion/Makefile9
-rw-r--r--arch/arm/plat-orion/addr-map.c11
-rw-r--r--arch/arm/plat-orion/common.c12
-rw-r--r--arch/arm/plat-orion/include/plat/addr-map.h4
-rw-r--r--arch/arm/plat-orion/include/plat/common.h8
-rw-r--r--arch/arm/plat-orion/include/plat/mpp.h2
-rw-r--r--arch/arm/plat-orion/include/plat/time.h4
-rw-r--r--arch/arm/plat-orion/mpp.c6
-rw-r--r--arch/arm/plat-orion/time.c8
40 files changed, 459 insertions, 316 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5876aef72dfe..70505d8f85c5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -540,7 +540,7 @@ config ARCH_DOVE
540 select ARCH_REQUIRE_GPIOLIB 540 select ARCH_REQUIRE_GPIOLIB
541 select GENERIC_CLOCKEVENTS 541 select GENERIC_CLOCKEVENTS
542 select MIGHT_HAVE_PCI 542 select MIGHT_HAVE_PCI
543 select PLAT_ORION 543 select PLAT_ORION_LEGACY
544 select USB_ARCH_HAS_EHCI 544 select USB_ARCH_HAS_EHCI
545 help 545 help
546 Support for the Marvell Dove SoC 88AP510 546 Support for the Marvell Dove SoC 88AP510
@@ -551,7 +551,7 @@ config ARCH_KIRKWOOD
551 select PCI 551 select PCI
552 select ARCH_REQUIRE_GPIOLIB 552 select ARCH_REQUIRE_GPIOLIB
553 select GENERIC_CLOCKEVENTS 553 select GENERIC_CLOCKEVENTS
554 select PLAT_ORION 554 select PLAT_ORION_LEGACY
555 help 555 help
556 Support for the following Marvell Kirkwood series SoCs: 556 Support for the following Marvell Kirkwood series SoCs:
557 88F6180, 88F6192 and 88F6281. 557 88F6180, 88F6192 and 88F6281.
@@ -577,7 +577,7 @@ config ARCH_MV78XX0
577 select PCI 577 select PCI
578 select ARCH_REQUIRE_GPIOLIB 578 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS 579 select GENERIC_CLOCKEVENTS
580 select PLAT_ORION 580 select PLAT_ORION_LEGACY
581 help 581 help
582 Support for the following Marvell MV78xx0 series SoCs: 582 Support for the following Marvell MV78xx0 series SoCs:
583 MV781x0, MV782x0. 583 MV781x0, MV782x0.
@@ -589,7 +589,7 @@ config ARCH_ORION5X
589 select PCI 589 select PCI
590 select ARCH_REQUIRE_GPIOLIB 590 select ARCH_REQUIRE_GPIOLIB
591 select GENERIC_CLOCKEVENTS 591 select GENERIC_CLOCKEVENTS
592 select PLAT_ORION 592 select PLAT_ORION_LEGACY
593 help 593 help
594 Support for the following Marvell Orion 5x series SoCs: 594 Support for the following Marvell Orion 5x series SoCs:
595 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182), 595 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
@@ -1146,6 +1146,10 @@ config PLAT_ORION
1146 select IRQ_DOMAIN 1146 select IRQ_DOMAIN
1147 select COMMON_CLK 1147 select COMMON_CLK
1148 1148
1149config PLAT_ORION_LEGACY
1150 bool
1151 select PLAT_ORION
1152
1149config PLAT_PXA 1153config PLAT_PXA
1150 bool 1154 bool
1151 1155
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 6b6b932a5a7d..16cc82cdaa81 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -63,6 +63,11 @@
63 reg = <0xd0020300 0x30>; 63 reg = <0xd0020300 0x30>;
64 interrupts = <37>, <38>, <39>, <40>; 64 interrupts = <37>, <38>, <39>, <40>;
65 }; 65 };
66
67 addr-decoding@d0020000 {
68 compatible = "marvell,armada-addr-decoding-controller";
69 reg = <0xd0020000 0x258>;
70 };
66 }; 71 };
67}; 72};
68 73
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 28475bb7d36f..b37bef1d5ffa 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -41,12 +41,12 @@
41 ****************************************************************************/ 41 ****************************************************************************/
42static struct map_desc dove_io_desc[] __initdata = { 42static struct map_desc dove_io_desc[] __initdata = {
43 { 43 {
44 .virtual = DOVE_SB_REGS_VIRT_BASE, 44 .virtual = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
45 .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE), 45 .pfn = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
46 .length = DOVE_SB_REGS_SIZE, 46 .length = DOVE_SB_REGS_SIZE,
47 .type = MT_DEVICE, 47 .type = MT_DEVICE,
48 }, { 48 }, {
49 .virtual = DOVE_NB_REGS_VIRT_BASE, 49 .virtual = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
50 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE), 50 .pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
51 .length = DOVE_NB_REGS_SIZE, 51 .length = DOVE_NB_REGS_SIZE,
52 .type = MT_DEVICE, 52 .type = MT_DEVICE,
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h
index f953bb54aa9d..99f259e8cf33 100644
--- a/arch/arm/mach-dove/include/mach/bridge-regs.h
+++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -13,22 +13,22 @@
13 13
14#include <mach/dove.h> 14#include <mach/dove.h>
15 15
16#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0000) 16#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000)
17 17
18#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) 18#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
19#define CPU_CTRL_PCIE0_LINK 0x00000001 19#define CPU_CTRL_PCIE0_LINK 0x00000001
20#define CPU_RESET 0x00000002 20#define CPU_RESET 0x00000002
21#define CPU_CTRL_PCIE1_LINK 0x00000008 21#define CPU_CTRL_PCIE1_LINK 0x00000008
22 22
23#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) 23#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
24#define SOFT_RESET_OUT_EN 0x00000004 24#define SOFT_RESET_OUT_EN 0x00000004
25 25
26#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) 26#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
27#define SOFT_RESET 0x00000001 27#define SOFT_RESET 0x00000001
28 28
29#define BRIDGE_INT_TIMER1_CLR (~0x0004) 29#define BRIDGE_INT_TIMER1_CLR (~0x0004)
30 30
31#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) 31#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
32#define IRQ_CAUSE_LOW_OFF 0x0000 32#define IRQ_CAUSE_LOW_OFF 0x0000
33#define IRQ_MASK_LOW_OFF 0x0004 33#define IRQ_MASK_LOW_OFF 0x0004
34#define FIQ_MASK_LOW_OFF 0x0008 34#define FIQ_MASK_LOW_OFF 0x0008
@@ -47,9 +47,9 @@
47#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF) 47#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
48#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF) 48#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
49 49
50#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE | 0x011c) 50#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c)
51 51
52#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) 52#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
53#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) 53#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
54 54
55#endif 55#endif
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index c91e3004a47b..661725e3115a 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -25,7 +25,7 @@
25 */ 25 */
26 26
27#define DOVE_CESA_PHYS_BASE 0xc8000000 27#define DOVE_CESA_PHYS_BASE 0xc8000000
28#define DOVE_CESA_VIRT_BASE 0xfdb00000 28#define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000)
29#define DOVE_CESA_SIZE SZ_1M 29#define DOVE_CESA_SIZE SZ_1M
30 30
31#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000 31#define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000
@@ -38,15 +38,15 @@
38#define DOVE_BOOTROM_SIZE SZ_128M 38#define DOVE_BOOTROM_SIZE SZ_128M
39 39
40#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000 40#define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000
41#define DOVE_SCRATCHPAD_VIRT_BASE 0xfdd00000 41#define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000)
42#define DOVE_SCRATCHPAD_SIZE SZ_1M 42#define DOVE_SCRATCHPAD_SIZE SZ_1M
43 43
44#define DOVE_SB_REGS_PHYS_BASE 0xf1000000 44#define DOVE_SB_REGS_PHYS_BASE 0xf1000000
45#define DOVE_SB_REGS_VIRT_BASE 0xfde00000 45#define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfde00000)
46#define DOVE_SB_REGS_SIZE SZ_8M 46#define DOVE_SB_REGS_SIZE SZ_8M
47 47
48#define DOVE_NB_REGS_PHYS_BASE 0xf1800000 48#define DOVE_NB_REGS_PHYS_BASE 0xf1800000
49#define DOVE_NB_REGS_VIRT_BASE 0xfe600000 49#define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe600000)
50#define DOVE_NB_REGS_SIZE SZ_8M 50#define DOVE_NB_REGS_SIZE SZ_8M
51 51
52#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 52#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000
@@ -62,75 +62,75 @@
62 */ 62 */
63 63
64/* SPI, I2C, UART */ 64/* SPI, I2C, UART */
65#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x11000) 65#define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x11000)
66#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12000) 66#define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12000)
67#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12000) 67#define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12000)
68#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12100) 68#define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12100)
69#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12100) 69#define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12100)
70#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12200) 70#define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12200)
71#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12200) 71#define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12200)
72#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x12300) 72#define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12300)
73#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x12300) 73#define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12300)
74#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x10600) 74#define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x10600)
75#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x14600) 75#define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x14600)
76 76
77/* North-South Bridge */ 77/* North-South Bridge */
78#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x20000) 78#define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000)
79#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x20000) 79#define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000)
80 80
81/* Cryptographic Engine */ 81/* Cryptographic Engine */
82#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x30000) 82#define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000)
83 83
84/* PCIe 0 */ 84/* PCIe 0 */
85#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x40000) 85#define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x40000)
86 86
87/* USB */ 87/* USB */
88#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x50000) 88#define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x50000)
89#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x51000) 89#define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x51000)
90 90
91/* XOR 0 Engine */ 91/* XOR 0 Engine */
92#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60800) 92#define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60800)
93#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60800) 93#define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60800)
94#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60A00) 94#define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60A00)
95#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60A00) 95#define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60A00)
96 96
97/* XOR 1 Engine */ 97/* XOR 1 Engine */
98#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60900) 98#define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60900)
99#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60900) 99#define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60900)
100#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x60B00) 100#define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60B00)
101#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x60B00) 101#define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60B00)
102 102
103/* Gigabit Ethernet */ 103/* Gigabit Ethernet */
104#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x70000) 104#define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x70000)
105 105
106/* PCIe 1 */ 106/* PCIe 1 */
107#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0x80000) 107#define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x80000)
108 108
109/* CAFE */ 109/* CAFE */
110#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x92000) 110#define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x92000)
111#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x90000) 111#define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x90000)
112#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x94000) 112#define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x94000)
113#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x98000) 113#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000)
114 114
115/* SATA */ 115/* SATA */
116#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xa0000) 116#define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xa0000)
117 117
118/* I2S/SPDIF */ 118/* I2S/SPDIF */
119#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb0000) 119#define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb0000)
120#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xb4000) 120#define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb4000)
121 121
122/* NAND Flash Controller */ 122/* NAND Flash Controller */
123#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xc0000) 123#define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xc0000)
124 124
125/* MPP, GPIO, Reset Sampling */ 125/* MPP, GPIO, Reset Sampling */
126#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200) 126#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
127#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) 127#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
128#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE | 0x014) 128#define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE + 0x014)
129#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE | 0x018) 129#define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE + 0x018)
130#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400) 130#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
131#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0420) 131#define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0420)
132#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe8400) 132#define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe8400)
133#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c) 133#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
134#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) 134#define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1)
135#define DOVE_NAND_GPIO_EN (1 << 0) 135#define DOVE_NAND_GPIO_EN (1 << 0)
136#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) 136#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
@@ -142,44 +142,44 @@
142#define DOVE_SD0_GPIO_SEL (1 << 0) 142#define DOVE_SD0_GPIO_SEL (1 << 0)
143 143
144/* Power Management */ 144/* Power Management */
145#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0000) 145#define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0000)
146#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c) 146#define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c)
147 147
148/* Real Time Clock */ 148/* Real Time Clock */
149#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xd8500) 149#define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xd8500)
150 150
151/* AC97 */ 151/* AC97 */
152#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe0000) 152#define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe0000)
153#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe0000) 153#define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe0000)
154 154
155/* Peripheral DMA */ 155/* Peripheral DMA */
156#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xe4000) 156#define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe4000)
157#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe4000) 157#define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe4000)
158 158
159#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C) 159#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
160#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7) 160#define DOVE_TWSI_ENABLE_OPTION1 (1 << 7)
161#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030) 161#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
162#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20) 162#define DOVE_TWSI_ENABLE_OPTION2 (1 << 20)
163#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21) 163#define DOVE_TWSI_ENABLE_OPTION3 (1 << 21)
164#define DOVE_TWSI_OPTION3_GPIO (1 << 22) 164#define DOVE_TWSI_OPTION3_GPIO (1 << 22)
165#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0xec000) 165#define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xec000)
166#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034) 166#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
167#define DOVE_SSP_ON_AU1 (1 << 0) 167#define DOVE_SSP_ON_AU1 (1 << 0)
168#define DOVE_SSP_CLOCK_ENABLE (1 << 1) 168#define DOVE_SSP_CLOCK_ENABLE (1 << 1)
169#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11) 169#define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11)
170/* Memory Controller */ 170/* Memory Controller */
171#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE | 0x00000) 171#define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000)
172 172
173/* LCD Controller */ 173/* LCD Controller */
174#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000) 174#define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
175#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x20000) 175#define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x20000)
176#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x10000) 176#define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000)
177#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x30000) 177#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000)
178 178
179/* Graphic Engine */ 179/* Graphic Engine */
180#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x40000) 180#define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x40000)
181 181
182/* Video Engine */ 182/* Video Engine */
183#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x400000) 183#define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x400000)
184 184
185#endif 185#endif
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index 186357f3b4db..087711524e8a 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -100,19 +100,19 @@ void __init dove_init_irq(void)
100{ 100{
101 int i; 101 int i;
102 102
103 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); 103 orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
104 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); 104 orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
105 105
106 /* 106 /*
107 * Initialize gpiolib for GPIOs 0-71. 107 * Initialize gpiolib for GPIOs 0-71.
108 */ 108 */
109 orion_gpio_init(NULL, 0, 32, (void __iomem *)DOVE_GPIO_LO_VIRT_BASE, 0, 109 orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
110 IRQ_DOVE_GPIO_START, gpio0_irqs); 110 IRQ_DOVE_GPIO_START, gpio0_irqs);
111 111
112 orion_gpio_init(NULL, 32, 32, (void __iomem *)DOVE_GPIO_HI_VIRT_BASE, 0, 112 orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
113 IRQ_DOVE_GPIO_START + 32, gpio1_irqs); 113 IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
114 114
115 orion_gpio_init(NULL, 64, 8, (void __iomem *)DOVE_GPIO2_VIRT_BASE, 0, 115 orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
116 IRQ_DOVE_GPIO_START + 64, gpio2_irqs); 116 IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
117 117
118 /* 118 /*
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index 355332d502cb..bb15b26041cb 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -182,18 +182,18 @@ static struct hw_pci dove_pci __initdata = {
182 .map_irq = dove_pcie_map_irq, 182 .map_irq = dove_pcie_map_irq,
183}; 183};
184 184
185static void __init add_pcie_port(int index, unsigned long base) 185static void __init add_pcie_port(int index, void __iomem *base)
186{ 186{
187 printk(KERN_INFO "Dove PCIe port %d: ", index); 187 printk(KERN_INFO "Dove PCIe port %d: ", index);
188 188
189 if (orion_pcie_link_up((void __iomem *)base)) { 189 if (orion_pcie_link_up(base)) {
190 struct pcie_port *pp = &pcie_port[num_pcie_ports++]; 190 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
191 191
192 printk(KERN_INFO "link up\n"); 192 printk(KERN_INFO "link up\n");
193 193
194 pp->index = index; 194 pp->index = index;
195 pp->root_bus_nr = -1; 195 pp->root_bus_nr = -1;
196 pp->base = (void __iomem *)base; 196 pp->base = base;
197 spin_lock_init(&pp->conf_lock); 197 spin_lock_init(&pp->conf_lock);
198 memset(&pp->res, 0, sizeof(pp->res)); 198 memset(&pp->res, 0, sizeof(pp->res));
199 } else { 199 } else {
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index e9a7180863d9..8f0d162a1e1d 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -86,5 +86,6 @@ void __init kirkwood_setup_cpu_mbus(void)
86 /* 86 /*
87 * Setup MBUS dram target info. 87 * Setup MBUS dram target info.
88 */ 88 */
89 orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE); 89 orion_setup_cpu_mbus_target(&addr_map_cfg,
90 (void __iomem *) DDR_WINDOW_CPU_BASE);
90} 91}
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 5c38c94b79a2..3991077f58a2 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -42,7 +42,7 @@
42 ****************************************************************************/ 42 ****************************************************************************/
43static struct map_desc kirkwood_io_desc[] __initdata = { 43static struct map_desc kirkwood_io_desc[] __initdata = {
44 { 44 {
45 .virtual = KIRKWOOD_REGS_VIRT_BASE, 45 .virtual = (unsigned long) KIRKWOOD_REGS_VIRT_BASE,
46 .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE), 46 .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
47 .length = KIRKWOOD_REGS_SIZE, 47 .length = KIRKWOOD_REGS_SIZE,
48 .type = MT_DEVICE, 48 .type = MT_DEVICE,
@@ -205,8 +205,7 @@ static struct clk *tclk;
205 205
206static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx) 206static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
207{ 207{
208 return clk_register_gate(NULL, name, "tclk", 0, 208 return clk_register_gate(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
209 (void __iomem *)CLOCK_GATING_CTRL,
210 bit_idx, 0, &gating_lock); 209 bit_idx, 0, &gating_lock);
211} 210}
212 211
@@ -215,8 +214,7 @@ static struct clk __init *kirkwood_register_gate_fn(const char *name,
215 void (*fn_en)(void), 214 void (*fn_en)(void),
216 void (*fn_dis)(void)) 215 void (*fn_dis)(void))
217{ 216{
218 return clk_register_gate_fn(NULL, name, "tclk", 0, 217 return clk_register_gate_fn(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
219 (void __iomem *)CLOCK_GATING_CTRL,
220 bit_idx, 0, &gating_lock, fn_en, fn_dis); 218 bit_idx, 0, &gating_lock, fn_en, fn_dis);
221} 219}
222 220
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index a115142f8690..5c82b7dce4e2 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -13,37 +13,37 @@
13 13
14#include <mach/kirkwood.h> 14#include <mach/kirkwood.h>
15 15
16#define CPU_CONFIG (BRIDGE_VIRT_BASE | 0x0100) 16#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0100)
17#define CPU_CONFIG_ERROR_PROP 0x00000004 17#define CPU_CONFIG_ERROR_PROP 0x00000004
18 18
19#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) 19#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
20#define CPU_RESET 0x00000002 20#define CPU_RESET 0x00000002
21 21
22#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) 22#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
23#define WDT_RESET_OUT_EN 0x00000002 23#define WDT_RESET_OUT_EN 0x00000002
24#define SOFT_RESET_OUT_EN 0x00000004 24#define SOFT_RESET_OUT_EN 0x00000004
25 25
26#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) 26#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
27#define SOFT_RESET 0x00000001 27#define SOFT_RESET 0x00000001
28 28
29#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110) 29#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110)
30#define WDT_INT_REQ 0x0008 30#define WDT_INT_REQ 0x0008
31 31
32#define BRIDGE_INT_TIMER1_CLR (~0x0004) 32#define BRIDGE_INT_TIMER1_CLR (~0x0004)
33 33
34#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) 34#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
35#define IRQ_CAUSE_LOW_OFF 0x0000 35#define IRQ_CAUSE_LOW_OFF 0x0000
36#define IRQ_MASK_LOW_OFF 0x0004 36#define IRQ_MASK_LOW_OFF 0x0004
37#define IRQ_CAUSE_HIGH_OFF 0x0010 37#define IRQ_CAUSE_HIGH_OFF 0x0010
38#define IRQ_MASK_HIGH_OFF 0x0014 38#define IRQ_MASK_HIGH_OFF 0x0014
39 39
40#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) 40#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
41#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) 41#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
42 42
43#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128) 43#define L2_CONFIG_REG (BRIDGE_VIRT_BASE + 0x0128)
44#define L2_WRITETHROUGH 0x00000010 44#define L2_WRITETHROUGH 0x00000010
45 45
46#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE | 0x11c) 46#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE + 0x11c)
47#define CGC_BIT_GE0 (0) 47#define CGC_BIT_GE0 (0)
48#define CGC_BIT_PEX0 (2) 48#define CGC_BIT_PEX0 (2)
49#define CGC_BIT_USB0 (3) 49#define CGC_BIT_USB0 (3)
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index af4f0000dcef..041653a04a9c 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -45,7 +45,7 @@
45#define KIRKWOOD_PCIE_IO_SIZE SZ_64K 45#define KIRKWOOD_PCIE_IO_SIZE SZ_64K
46 46
47#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000 47#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
48#define KIRKWOOD_REGS_VIRT_BASE 0xfed00000 48#define KIRKWOOD_REGS_VIRT_BASE IOMEM(0xfed00000)
49#define KIRKWOOD_REGS_SIZE SZ_1M 49#define KIRKWOOD_REGS_SIZE SZ_1M
50 50
51#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000 51#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
@@ -59,61 +59,61 @@
59/* 59/*
60 * Register Map 60 * Register Map
61 */ 61 */
62#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000) 62#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x00000)
63#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500) 63#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE + 0x1500)
64#define DDR_OPERATION_BASE (DDR_VIRT_BASE | 0x1418) 64#define DDR_OPERATION_BASE (DDR_VIRT_BASE + 0x1418)
65 65
66#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000) 66#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x10000)
67#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000) 67#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x10000)
68#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030) 68#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE + 0x0030)
69#define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034) 69#define DEVICE_ID (DEV_BUS_VIRT_BASE + 0x0034)
70#define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100) 70#define GPIO_LOW_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100)
71#define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0140) 71#define GPIO_HIGH_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0140)
72#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300) 72#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0300)
73#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600) 73#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x0600)
74#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) 74#define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000)
75#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) 75#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000)
76#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) 76#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000)
77#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) 77#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100)
78#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) 78#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100)
79 79
80#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000) 80#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x20000)
81#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x20000) 81#define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
82 82
83#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x30000) 83#define CRYPTO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x30000)
84 84
85#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000) 85#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x40000)
86#define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70) 86#define PCIE_LINK_CTRL (PCIE_VIRT_BASE + 0x70)
87#define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04) 87#define PCIE_STATUS (PCIE_VIRT_BASE + 0x1a04)
88#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x44000) 88#define PCIE1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x44000)
89#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE | 0x70) 89#define PCIE1_LINK_CTRL (PCIE1_VIRT_BASE + 0x70)
90#define PCIE1_STATUS (PCIE1_VIRT_BASE | 0x1a04) 90#define PCIE1_STATUS (PCIE1_VIRT_BASE + 0x1a04)
91 91
92#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000) 92#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x50000)
93 93
94#define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60800) 94#define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60800)
95#define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60800) 95#define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60800)
96#define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60900) 96#define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60900)
97#define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60900) 97#define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60900)
98#define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60A00) 98#define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60A00)
99#define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60A00) 99#define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60A00)
100#define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60B00) 100#define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x60B00)
101#define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60B00) 101#define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x60B00)
102 102
103#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x70000) 103#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x70000)
104#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000) 104#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x74000)
105 105
106#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000) 106#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x80000)
107#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x80000) 107#define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0x80000)
108#define SATA0_IF_CTRL (SATA_VIRT_BASE | 0x2050) 108#define SATA0_IF_CTRL (SATA_VIRT_BASE + 0x2050)
109#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE | 0x2330) 109#define SATA0_PHY_MODE_2 (SATA_VIRT_BASE + 0x2330)
110#define SATA1_IF_CTRL (SATA_VIRT_BASE | 0x4050) 110#define SATA1_IF_CTRL (SATA_VIRT_BASE + 0x4050)
111#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE | 0x4330) 111#define SATA1_PHY_MODE_2 (SATA_VIRT_BASE + 0x4330)
112 112
113#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000) 113#define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x90000)
114 114
115#define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0xA0000) 115#define AUDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0xA0000)
116#define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0xA0000) 116#define AUDIO_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE + 0xA0000)
117 117
118/* 118/*
119 * Supported devices and revisions. 119 * Supported devices and revisions.
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
index 20149a7fd280..884703535a0a 100644
--- a/arch/arm/mach-kirkwood/irq.c
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -10,6 +10,7 @@
10#include <linux/gpio.h> 10#include <linux/gpio.h>
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/irq.h> 12#include <linux/irq.h>
13#include <linux/io.h>
13#include <mach/bridge-regs.h> 14#include <mach/bridge-regs.h>
14#include <plat/orion-gpio.h> 15#include <plat/orion-gpio.h>
15#include <plat/irq.h> 16#include <plat/irq.h>
@@ -30,14 +31,14 @@ static int __initdata gpio1_irqs[4] = {
30 31
31void __init kirkwood_init_irq(void) 32void __init kirkwood_init_irq(void)
32{ 33{
33 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); 34 orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
34 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); 35 orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
35 36
36 /* 37 /*
37 * Initialize gpiolib for GPIOs 0-49. 38 * Initialize gpiolib for GPIOs 0-49.
38 */ 39 */
39 orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_LOW_VIRT_BASE, 0, 40 orion_gpio_init(NULL, 0, 32, GPIO_LOW_VIRT_BASE, 0,
40 IRQ_KIRKWOOD_GPIO_START, gpio0_irqs); 41 IRQ_KIRKWOOD_GPIO_START, gpio0_irqs);
41 orion_gpio_init(NULL, 32, 18, (void __iomem *)GPIO_HIGH_VIRT_BASE, 0, 42 orion_gpio_init(NULL, 32, 18, GPIO_HIGH_VIRT_BASE, 0,
42 IRQ_KIRKWOOD_GPIO_START + 32, gpio1_irqs); 43 IRQ_KIRKWOOD_GPIO_START + 32, gpio1_irqs);
43} 44}
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 532d8acb38f9..ec544918b12c 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -47,8 +47,8 @@ void kirkwood_enable_pcie(void)
47void kirkwood_pcie_id(u32 *dev, u32 *rev) 47void kirkwood_pcie_id(u32 *dev, u32 *rev)
48{ 48{
49 kirkwood_enable_pcie(); 49 kirkwood_enable_pcie();
50 *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE); 50 *dev = orion_pcie_dev_id(PCIE_VIRT_BASE);
51 *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE); 51 *rev = orion_pcie_rev(PCIE_VIRT_BASE);
52} 52}
53 53
54struct pcie_port { 54struct pcie_port {
@@ -133,7 +133,7 @@ static struct pci_ops pcie_ops = {
133 133
134static void __init pcie0_ioresources_init(struct pcie_port *pp) 134static void __init pcie0_ioresources_init(struct pcie_port *pp)
135{ 135{
136 pp->base = (void __iomem *)PCIE_VIRT_BASE; 136 pp->base = PCIE_VIRT_BASE;
137 pp->irq = IRQ_KIRKWOOD_PCIE; 137 pp->irq = IRQ_KIRKWOOD_PCIE;
138 138
139 /* 139 /*
@@ -147,7 +147,7 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp)
147 147
148static void __init pcie1_ioresources_init(struct pcie_port *pp) 148static void __init pcie1_ioresources_init(struct pcie_port *pp)
149{ 149{
150 pp->base = (void __iomem *)PCIE1_VIRT_BASE; 150 pp->base = PCIE1_VIRT_BASE;
151 pp->irq = IRQ_KIRKWOOD_PCIE1; 151 pp->irq = IRQ_KIRKWOOD_PCIE1;
152 152
153 /* 153 /*
@@ -255,11 +255,11 @@ static struct hw_pci kirkwood_pci __initdata = {
255 .map_irq = kirkwood_pcie_map_irq, 255 .map_irq = kirkwood_pcie_map_irq,
256}; 256};
257 257
258static void __init add_pcie_port(int index, unsigned long base) 258static void __init add_pcie_port(int index, void __iomem *base)
259{ 259{
260 printk(KERN_INFO "Kirkwood PCIe port %d: ", index); 260 printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
261 261
262 if (orion_pcie_link_up((void __iomem *)base)) { 262 if (orion_pcie_link_up(base)) {
263 printk(KERN_INFO "link up\n"); 263 printk(KERN_INFO "link up\n");
264 pcie_port_map[num_pcie_ports++] = index; 264 pcie_port_map[num_pcie_ports++] = index;
265 } else 265 } else
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index 5bbca2680442..367a9400f532 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -20,6 +20,7 @@
20#include <linux/gpio.h> 20#include <linux/gpio.h>
21#include <linux/gpio_keys.h> 21#include <linux/gpio_keys.h>
22#include <linux/input.h> 22#include <linux/input.h>
23#include <linux/io.h>
23#include <asm/mach-types.h> 24#include <asm/mach-types.h>
24#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
25#include <mach/kirkwood.h> 26#include <mach/kirkwood.h>
@@ -161,7 +162,7 @@ static int __init ts41x_pci_init(void)
161 * (Marvell 88sx7042/sata_mv) is known to stop working 162 * (Marvell 88sx7042/sata_mv) is known to stop working
162 * after a few minutes. 163 * after a few minutes.
163 */ 164 */
164 orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE); 165 orion_pcie_reset(PCIE_VIRT_BASE);
165 166
166 kirkwood_pcie_id(&dev, &rev); 167 kirkwood_pcie_id(&dev, &rev);
167 if (dev == MV88F6282_DEV_ID) 168 if (dev == MV88F6282_DEV_ID)
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index 137e479d15a0..343c435b4176 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -48,7 +48,7 @@ static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, i
48 * so we don't need to take that into account here. 48 * so we don't need to take that into account here.
49 */ 49 */
50 50
51 return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win)); 51 return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win);
52} 52}
53 53
54/* 54/*
@@ -72,10 +72,10 @@ void __init mv78xx0_setup_cpu_mbus(void)
72 */ 72 */
73 if (mv78xx0_core_index() == 0) 73 if (mv78xx0_core_index() == 0)
74 orion_setup_cpu_mbus_target(&addr_map_cfg, 74 orion_setup_cpu_mbus_target(&addr_map_cfg,
75 DDR_WINDOW_CPU0_BASE); 75 (void __iomem *) DDR_WINDOW_CPU0_BASE);
76 else 76 else
77 orion_setup_cpu_mbus_target(&addr_map_cfg, 77 orion_setup_cpu_mbus_target(&addr_map_cfg,
78 DDR_WINDOW_CPU1_BASE); 78 (void __iomem *) DDR_WINDOW_CPU1_BASE);
79} 79}
80 80
81void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, 81void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index a6f3cd21e8c2..131cd4883f3d 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -130,12 +130,12 @@ static int get_tclk(void)
130 ****************************************************************************/ 130 ****************************************************************************/
131static struct map_desc mv78xx0_io_desc[] __initdata = { 131static struct map_desc mv78xx0_io_desc[] __initdata = {
132 { 132 {
133 .virtual = MV78XX0_CORE_REGS_VIRT_BASE, 133 .virtual = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
134 .pfn = 0, 134 .pfn = 0,
135 .length = MV78XX0_CORE_REGS_SIZE, 135 .length = MV78XX0_CORE_REGS_SIZE,
136 .type = MT_DEVICE, 136 .type = MT_DEVICE,
137 }, { 137 }, {
138 .virtual = MV78XX0_REGS_VIRT_BASE, 138 .virtual = (unsigned long) MV78XX0_REGS_VIRT_BASE,
139 .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE), 139 .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
140 .length = MV78XX0_REGS_SIZE, 140 .length = MV78XX0_REGS_SIZE,
141 .type = MT_DEVICE, 141 .type = MT_DEVICE,
diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
index eb187e0e059b..5f03484584d4 100644
--- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
+++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
@@ -11,18 +11,18 @@
11 11
12#include <mach/mv78xx0.h> 12#include <mach/mv78xx0.h>
13 13
14#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104) 14#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
15#define L2_WRITETHROUGH 0x00020000 15#define L2_WRITETHROUGH 0x00020000
16 16
17#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108) 17#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
18#define SOFT_RESET_OUT_EN 0x00000004 18#define SOFT_RESET_OUT_EN 0x00000004
19 19
20#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c) 20#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
21#define SOFT_RESET 0x00000001 21#define SOFT_RESET 0x00000001
22 22
23#define BRIDGE_INT_TIMER1_CLR (~0x0004) 23#define BRIDGE_INT_TIMER1_CLR (~0x0004)
24 24
25#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200) 25#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
26#define IRQ_CAUSE_ERR_OFF 0x0000 26#define IRQ_CAUSE_ERR_OFF 0x0000
27#define IRQ_CAUSE_LOW_OFF 0x0004 27#define IRQ_CAUSE_LOW_OFF 0x0004
28#define IRQ_CAUSE_HIGH_OFF 0x0008 28#define IRQ_CAUSE_HIGH_OFF 0x0008
@@ -30,7 +30,7 @@
30#define IRQ_MASK_LOW_OFF 0x0010 30#define IRQ_MASK_LOW_OFF 0x0010
31#define IRQ_MASK_HIGH_OFF 0x0014 31#define IRQ_MASK_HIGH_OFF 0x0014
32 32
33#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) 33#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
34#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE | 0x0300) 34#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
35 35
36#endif 36#endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index bd03fed1128e..46200a183cf2 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -41,7 +41,7 @@
41 */ 41 */
42#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000 42#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
43#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000 43#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
44#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000 44#define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
45#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000 45#define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
46#define MV78XX0_CORE_REGS_SIZE SZ_16K 46#define MV78XX0_CORE_REGS_SIZE SZ_16K
47 47
@@ -49,7 +49,7 @@
49#define MV78XX0_PCIE_IO_SIZE SZ_1M 49#define MV78XX0_PCIE_IO_SIZE SZ_1M
50 50
51#define MV78XX0_REGS_PHYS_BASE 0xf1000000 51#define MV78XX0_REGS_PHYS_BASE 0xf1000000
52#define MV78XX0_REGS_VIRT_BASE 0xfd000000 52#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfd000000)
53#define MV78XX0_REGS_SIZE SZ_1M 53#define MV78XX0_REGS_SIZE SZ_1M
54 54
55#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000 55#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
@@ -64,47 +64,47 @@
64/* 64/*
65 * Register Map 65 * Register Map
66 */ 66 */
67#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) 67#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x00000)
68#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500) 68#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE + 0x1500)
69#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1570) 69#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE + 0x1570)
70 70
71#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000) 71#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x10000)
72#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) 72#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x10000)
73#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) 73#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE + 0x0030)
74#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) 74#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE + 0x0034)
75#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x0100) 75#define GPIO_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x0100)
76#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) 76#define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1000)
77#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100) 77#define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x1100)
78#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) 78#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2000)
79#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) 79#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2000)
80#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) 80#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2100)
81#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100) 81#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2100)
82#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200) 82#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2200)
83#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200) 83#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2200)
84#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300) 84#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE + 0x2300)
85#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300) 85#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE + 0x2300)
86 86
87#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000) 87#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x30000)
88#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000) 88#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x34000)
89 89
90#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000) 90#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x40000)
91#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000) 91#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x44000)
92#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000) 92#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x48000)
93#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000) 93#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x4c000)
94 94
95#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000) 95#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x50000)
96#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000) 96#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000)
97#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000) 97#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000)
98 98
99#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000) 99#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000)
100#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000) 100#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000)
101 101
102#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000) 102#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x80000)
103#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000) 103#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x84000)
104#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000) 104#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000)
105#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000) 105#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000)
106 106
107#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000) 107#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000)
108 108
109/* 109/*
110 * Supported devices and revisions. 110 * Supported devices and revisions.
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index 4d720f2aedba..32073444024b 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -10,6 +10,7 @@
10#include <linux/gpio.h> 10#include <linux/gpio.h>
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/irq.h> 12#include <linux/irq.h>
13#include <linux/io.h>
13#include <mach/bridge-regs.h> 14#include <mach/bridge-regs.h>
14#include <plat/orion-gpio.h> 15#include <plat/orion-gpio.h>
15#include <plat/irq.h> 16#include <plat/irq.h>
@@ -24,16 +25,16 @@ static int __initdata gpio0_irqs[4] = {
24 25
25void __init mv78xx0_init_irq(void) 26void __init mv78xx0_init_irq(void)
26{ 27{
27 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); 28 orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
28 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); 29 orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
29 orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF)); 30 orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);
30 31
31 /* 32 /*
32 * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask 33 * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask
33 * registers for core #1 are at an offset of 0x18 from those of 34 * registers for core #1 are at an offset of 0x18 from those of
34 * core #0.) 35 * core #0.)
35 */ 36 */
36 orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE, 37 orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE,
37 mv78xx0_core_index() ? 0x18 : 0, 38 mv78xx0_core_index() ? 0x18 : 0,
38 IRQ_MV78XX0_GPIO_START, gpio0_irqs); 39 IRQ_MV78XX0_GPIO_START, gpio0_irqs);
39} 40}
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index 26a059b4f472..a9a154a646dd 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -34,8 +34,8 @@ static struct resource pcie_io_space;
34 34
35void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) 35void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
36{ 36{
37 *dev = orion_pcie_dev_id((void __iomem *)PCIE00_VIRT_BASE); 37 *dev = orion_pcie_dev_id(PCIE00_VIRT_BASE);
38 *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE); 38 *rev = orion_pcie_rev(PCIE00_VIRT_BASE);
39} 39}
40 40
41u32 pcie_port_size[8] = { 41u32 pcie_port_size[8] = {
@@ -223,11 +223,11 @@ static struct hw_pci mv78xx0_pci __initdata = {
223 .map_irq = mv78xx0_pcie_map_irq, 223 .map_irq = mv78xx0_pcie_map_irq,
224}; 224};
225 225
226static void __init add_pcie_port(int maj, int min, unsigned long base) 226static void __init add_pcie_port(int maj, int min, void __iomem *base)
227{ 227{
228 printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min); 228 printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
229 229
230 if (orion_pcie_link_up((void __iomem *)base)) { 230 if (orion_pcie_link_up(base)) {
231 struct pcie_port *pp = &pcie_port[num_pcie_ports++]; 231 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
232 232
233 printk("link up\n"); 233 printk("link up\n");
@@ -235,7 +235,7 @@ static void __init add_pcie_port(int maj, int min, unsigned long base)
235 pp->maj = maj; 235 pp->maj = maj;
236 pp->min = min; 236 pp->min = min;
237 pp->root_bus_nr = -1; 237 pp->root_bus_nr = -1;
238 pp->base = (void __iomem *)base; 238 pp->base = base;
239 spin_lock_init(&pp->conf_lock); 239 spin_lock_init(&pp->conf_lock);
240 memset(&pp->res, 0, sizeof(pp->res)); 240 memset(&pp->res, 0, sizeof(pp->res));
241 } else { 241 } else {
@@ -249,7 +249,7 @@ void __init mv78xx0_pcie_init(int init_port0, int init_port1)
249 249
250 if (init_port0) { 250 if (init_port0) {
251 add_pcie_port(0, 0, PCIE00_VIRT_BASE); 251 add_pcie_port(0, 0, PCIE00_VIRT_BASE);
252 if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) { 252 if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) {
253 add_pcie_port(0, 1, PCIE01_VIRT_BASE); 253 add_pcie_port(0, 1, PCIE01_VIRT_BASE);
254 add_pcie_port(0, 2, PCIE02_VIRT_BASE); 254 add_pcie_port(0, 2, PCIE02_VIRT_BASE);
255 add_pcie_port(0, 3, PCIE03_VIRT_BASE); 255 add_pcie_port(0, 3, PCIE03_VIRT_BASE);
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 6ea8998ab8f1..cbe566443063 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1,4 +1,4 @@
1ccflags-$(ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include 1ccflags-$(ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
2 2
3obj-y += system-controller.o 3obj-y += system-controller.o
4obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o 4obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o
diff --git a/arch/arm/mach-mvebu/addr-map.c b/arch/arm/mach-mvebu/addr-map.c
new file mode 100644
index 000000000000..fe454a4430be
--- /dev/null
+++ b/arch/arm/mach-mvebu/addr-map.c
@@ -0,0 +1,134 @@
1/*
2 * Address map functions for Marvell 370 / XP SoCs
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/mbus.h>
16#include <linux/io.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <plat/addr-map.h>
20
21/*
22 * Generic Address Decode Windows bit settings
23 */
24#define ARMADA_XP_TARGET_DEV_BUS 1
25#define ARMADA_XP_ATTR_DEV_BOOTROM 0x1D
26#define ARMADA_XP_TARGET_ETH1 3
27#define ARMADA_XP_TARGET_PCIE_0_2 4
28#define ARMADA_XP_TARGET_ETH0 7
29#define ARMADA_XP_TARGET_PCIE_1_3 8
30
31#define ARMADA_370_TARGET_DEV_BUS 1
32#define ARMADA_370_ATTR_DEV_BOOTROM 0x1D
33#define ARMADA_370_TARGET_PCIE_0 4
34#define ARMADA_370_TARGET_PCIE_1 8
35
36#define ARMADA_WINDOW_8_PLUS_OFFSET 0x90
37#define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180
38
39static const struct __initdata orion_addr_map_info
40armada_xp_addr_map_info[] = {
41 /*
42 * Window for the BootROM, needed for SMP on Armada XP
43 */
44 { 0, 0xfff00000, SZ_1M, ARMADA_XP_TARGET_DEV_BUS,
45 ARMADA_XP_ATTR_DEV_BOOTROM, -1 },
46 /* End marker */
47 { -1, 0, 0, 0, 0, 0 },
48};
49
50static const struct __initdata orion_addr_map_info
51armada_370_addr_map_info[] = {
52 /* End marker */
53 { -1, 0, 0, 0, 0, 0 },
54};
55
56static struct of_device_id of_addr_decoding_controller_table[] = {
57 { .compatible = "marvell,armada-addr-decoding-controller" },
58 { /* end of list */ },
59};
60
61static void __iomem *
62armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
63{
64 unsigned int offset;
65
66 /* The register layout is a bit annoying and the below code
67 * tries to cope with it.
68 * - At offset 0x0, there are the registers for the first 8
69 * windows, with 4 registers of 32 bits per window (ctrl,
70 * base, remap low, remap high)
71 * - Then at offset 0x80, there is a hole of 0x10 bytes for
72 * the internal registers base address and internal units
73 * sync barrier register.
74 * - Then at offset 0x90, there the registers for 12
75 * windows, with only 2 registers of 32 bits per window
76 * (ctrl, base).
77 */
78 if (win < 8)
79 offset = (win << 4);
80 else
81 offset = ARMADA_WINDOW_8_PLUS_OFFSET + (win << 3);
82
83 return cfg->bridge_virt_base + offset;
84}
85
86static struct __initdata orion_addr_map_cfg addr_map_cfg = {
87 .num_wins = 20,
88 .remappable_wins = 8,
89 .win_cfg_base = armada_cfg_base,
90};
91
92static int __init armada_setup_cpu_mbus(void)
93{
94 struct device_node *np;
95 void __iomem *mbus_unit_addr_decoding_base;
96 void __iomem *sdram_addr_decoding_base;
97
98 np = of_find_matching_node(NULL, of_addr_decoding_controller_table);
99 if (!np)
100 return -ENODEV;
101
102 mbus_unit_addr_decoding_base = of_iomap(np, 0);
103 BUG_ON(!mbus_unit_addr_decoding_base);
104
105 sdram_addr_decoding_base =
106 mbus_unit_addr_decoding_base +
107 ARMADA_SDRAM_ADDR_DECODING_OFFSET;
108
109 addr_map_cfg.bridge_virt_base = mbus_unit_addr_decoding_base;
110
111 /*
112 * Disable, clear and configure windows.
113 */
114 if (of_machine_is_compatible("marvell,armadaxp"))
115 orion_config_wins(&addr_map_cfg, armada_xp_addr_map_info);
116 else if (of_machine_is_compatible("marvell,armada370"))
117 orion_config_wins(&addr_map_cfg, armada_370_addr_map_info);
118 else {
119 pr_err("Unsupported SoC\n");
120 return -EINVAL;
121 }
122
123 /*
124 * Setup MBUS dram target info.
125 */
126 orion_setup_cpu_mbus_target(&addr_map_cfg,
127 sdram_addr_decoding_base);
128 return 0;
129}
130
131/* Using a early_initcall is needed so that this initialization gets
132 * done before the SMP initialization, which requires the BootROM to
133 * be remapped. */
134early_initcall(armada_setup_cpu_mbus);
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index b46418a8b352..49d791548ad6 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -25,7 +25,7 @@
25 25
26static struct map_desc armada_370_xp_io_desc[] __initdata = { 26static struct map_desc armada_370_xp_io_desc[] __initdata = {
27 { 27 {
28 .virtual = ARMADA_370_XP_REGS_VIRT_BASE, 28 .virtual = (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE,
29 .pfn = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE), 29 .pfn = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
30 .length = ARMADA_370_XP_REGS_SIZE, 30 .length = ARMADA_370_XP_REGS_SIZE,
31 .type = MT_DEVICE, 31 .type = MT_DEVICE,
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index 25f0ca8d7820..aac9bebc6b03 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -16,7 +16,7 @@
16#define __MACH_ARMADA_370_XP_H 16#define __MACH_ARMADA_370_XP_H
17 17
18#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000 18#define ARMADA_370_XP_REGS_PHYS_BASE 0xd0000000
19#define ARMADA_370_XP_REGS_VIRT_BASE 0xfeb00000 19#define ARMADA_370_XP_REGS_VIRT_BASE IOMEM(0xfeb00000)
20#define ARMADA_370_XP_REGS_SIZE SZ_1M 20#define ARMADA_370_XP_REGS_SIZE SZ_1M
21 21
22#endif /* __MACH_ARMADA_370_XP_H */ 22#endif /* __MACH_ARMADA_370_XP_H */
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index eaac83d1df6f..b5efc0fd31cb 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -113,7 +113,8 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
113 /* 113 /*
114 * Setup MBUS dram target info. 114 * Setup MBUS dram target info.
115 */ 115 */
116 orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE); 116 orion_setup_cpu_mbus_target(&addr_map_cfg,
117 (void __iomem *) ORION5X_DDR_WINDOW_CPU_BASE);
117} 118}
118 119
119void __init orion5x_setup_dev_boot_win(u32 base, u32 size) 120void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 5387fdfcaf3f..3e07f52f2127 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -42,12 +42,12 @@
42 ****************************************************************************/ 42 ****************************************************************************/
43static struct map_desc orion5x_io_desc[] __initdata = { 43static struct map_desc orion5x_io_desc[] __initdata = {
44 { 44 {
45 .virtual = ORION5X_REGS_VIRT_BASE, 45 .virtual = (unsigned long) ORION5X_REGS_VIRT_BASE,
46 .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), 46 .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
47 .length = ORION5X_REGS_SIZE, 47 .length = ORION5X_REGS_SIZE,
48 .type = MT_DEVICE, 48 .type = MT_DEVICE,
49 }, { 49 }, {
50 .virtual = ORION5X_PCIE_WA_VIRT_BASE, 50 .virtual = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE,
51 .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), 51 .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
52 .length = ORION5X_PCIE_WA_SIZE, 52 .length = ORION5X_PCIE_WA_SIZE,
53 .type = MT_DEVICE, 53 .type = MT_DEVICE,
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 0e19db69f5c4..e533588880ff 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -701,7 +701,7 @@ static void __init dns323_init(void)
701 * Note: AFAIK, rev B1 needs the same treatement but I'll let 701 * Note: AFAIK, rev B1 needs the same treatement but I'll let
702 * somebody else test it. 702 * somebody else test it.
703 */ 703 */
704 writel(0x5, ORION5X_SATA_VIRT_BASE | 0x2c); 704 writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c);
705 break; 705 break;
706 } 706 }
707} 707}
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
index 11a3c1e9801f..461fd69a10ae 100644
--- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h
+++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
@@ -13,27 +13,27 @@
13 13
14#include <mach/orion5x.h> 14#include <mach/orion5x.h>
15 15
16#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE | 0x100) 16#define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
17 17
18#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE | 0x104) 18#define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
19 19
20#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x108) 20#define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
21#define WDT_RESET_OUT_EN 0x0002 21#define WDT_RESET_OUT_EN 0x0002
22 22
23#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE | 0x10c) 23#define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
24 24
25#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x110) 25#define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
26 26
27#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE | 0x11C) 27#define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
28 28
29#define WDT_INT_REQ 0x0008 29#define WDT_INT_REQ 0x0008
30 30
31#define BRIDGE_INT_TIMER1_CLR (~0x0004) 31#define BRIDGE_INT_TIMER1_CLR (~0x0004)
32 32
33#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE | 0x200) 33#define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
34 34
35#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE | 0x204) 35#define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
36 36
37#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE | 0x300) 37#define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300)
38#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE | 0x300) 38#define TIMER_PHYS_BASE (ORION5X_BRIDGE_PHYS_BASE + 0x300)
39#endif 39#endif
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 1b60131b7f60..d265f5484a8e 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -37,7 +37,7 @@
37 * fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only) 37 * fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only)
38 ****************************************************************************/ 38 ****************************************************************************/
39#define ORION5X_REGS_PHYS_BASE 0xf1000000 39#define ORION5X_REGS_PHYS_BASE 0xf1000000
40#define ORION5X_REGS_VIRT_BASE 0xfe000000 40#define ORION5X_REGS_VIRT_BASE IOMEM(0xfe000000)
41#define ORION5X_REGS_SIZE SZ_1M 41#define ORION5X_REGS_SIZE SZ_1M
42 42
43#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 43#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
@@ -53,7 +53,7 @@
53 53
54/* Relevant only for Orion-1/Orion-NAS */ 54/* Relevant only for Orion-1/Orion-NAS */
55#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 55#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
56#define ORION5X_PCIE_WA_VIRT_BASE 0xfd000000 56#define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
57#define ORION5X_PCIE_WA_SIZE SZ_16M 57#define ORION5X_PCIE_WA_SIZE SZ_16M
58 58
59#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 59#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
@@ -66,42 +66,42 @@
66 * Orion Registers Map 66 * Orion Registers Map
67 ******************************************************************************/ 67 ******************************************************************************/
68 68
69#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x00000) 69#define ORION5X_DDR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x00000)
70#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE | 0x1500) 70#define ORION5X_DDR_WINDOW_CPU_BASE (ORION5X_DDR_VIRT_BASE + 0x1500)
71#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x10000) 71#define ORION5X_DEV_BUS_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x10000)
72#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x10000) 72#define ORION5X_DEV_BUS_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x10000)
73#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE | (x)) 73#define ORION5X_DEV_BUS_REG(x) (ORION5X_DEV_BUS_VIRT_BASE + (x))
74#define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100) 74#define GPIO_VIRT_BASE ORION5X_DEV_BUS_REG(0x0100)
75#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x0600) 75#define SPI_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x0600)
76#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x1000) 76#define I2C_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x1000)
77#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2000) 77#define UART0_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2000)
78#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2000) 78#define UART0_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2000)
79#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE | 0x2100) 79#define UART1_PHYS_BASE (ORION5X_DEV_BUS_PHYS_BASE + 0x2100)
80#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE | 0x2100) 80#define UART1_VIRT_BASE (ORION5X_DEV_BUS_VIRT_BASE + 0x2100)
81 81
82#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x20000) 82#define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000)
83#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x20000) 83#define ORION5X_BRIDGE_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x20000)
84 84
85#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x30000) 85#define ORION5X_PCI_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x30000)
86 86
87#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x40000) 87#define ORION5X_PCIE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x40000)
88 88
89#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x50000) 89#define ORION5X_USB0_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x50000)
90#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x50000) 90#define ORION5X_USB0_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x50000)
91 91
92#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x60900) 92#define ORION5X_XOR_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x60900)
93#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x60900) 93#define ORION5X_XOR_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x60900)
94 94
95#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x70000) 95#define ORION5X_ETH_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x70000)
96#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x70000) 96#define ORION5X_ETH_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x70000)
97 97
98#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x80000) 98#define ORION5X_SATA_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x80000)
99#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0x80000) 99#define ORION5X_SATA_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x80000)
100 100
101#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0x90000) 101#define ORION5X_CRYPTO_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0x90000)
102 102
103#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE | 0xa0000) 103#define ORION5X_USB1_PHYS_BASE (ORION5X_REGS_PHYS_BASE + 0xa0000)
104#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE | 0xa0000) 104#define ORION5X_USB1_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0xa0000)
105 105
106/******************************************************************************* 106/*******************************************************************************
107 * Device Bus Registers 107 * Device Bus Registers
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index e152641cdb0e..30a192b9c517 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -12,6 +12,7 @@
12#include <linux/gpio.h> 12#include <linux/gpio.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/irq.h> 14#include <linux/irq.h>
15#include <linux/io.h>
15#include <mach/bridge-regs.h> 16#include <mach/bridge-regs.h>
16#include <plat/orion-gpio.h> 17#include <plat/orion-gpio.h>
17#include <plat/irq.h> 18#include <plat/irq.h>
@@ -25,11 +26,11 @@ static int __initdata gpio0_irqs[4] = {
25 26
26void __init orion5x_init_irq(void) 27void __init orion5x_init_irq(void)
27{ 28{
28 orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK); 29 orion_irq_init(0, MAIN_IRQ_MASK);
29 30
30 /* 31 /*
31 * Initialize gpiolib for GPIOs 0-31. 32 * Initialize gpiolib for GPIOs 0-31.
32 */ 33 */
33 orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE, 0, 34 orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, 0,
34 IRQ_ORION5X_GPIO_START, gpio0_irqs); 35 IRQ_ORION5X_GPIO_START, gpio0_irqs);
35} 36}
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 6921d49b988d..cd50e328db2a 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -38,7 +38,7 @@
38/***************************************************************************** 38/*****************************************************************************
39 * PCIe controller 39 * PCIe controller
40 ****************************************************************************/ 40 ****************************************************************************/
41#define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE) 41#define PCIE_BASE (ORION5X_PCIE_VIRT_BASE)
42 42
43void __init orion5x_pcie_id(u32 *dev, u32 *rev) 43void __init orion5x_pcie_id(u32 *dev, u32 *rev)
44{ 44{
@@ -111,7 +111,7 @@ static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
111 return PCIBIOS_DEVICE_NOT_FOUND; 111 return PCIBIOS_DEVICE_NOT_FOUND;
112 } 112 }
113 113
114 ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE, 114 ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE,
115 bus, devfn, where, size, val); 115 bus, devfn, where, size, val);
116 116
117 return ret; 117 return ret;
@@ -188,7 +188,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
188/***************************************************************************** 188/*****************************************************************************
189 * PCI controller 189 * PCI controller
190 ****************************************************************************/ 190 ****************************************************************************/
191#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE | (x)) 191#define ORION5X_PCI_REG(x) (ORION5X_PCI_VIRT_BASE + (x))
192#define PCI_MODE ORION5X_PCI_REG(0xd00) 192#define PCI_MODE ORION5X_PCI_REG(0xd00)
193#define PCI_CMD ORION5X_PCI_REG(0xc00) 193#define PCI_CMD ORION5X_PCI_REG(0xc00)
194#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14) 194#define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index c20ce0f5ce33..1251e5bd41c5 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -2,9 +2,8 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y := irq.o pcie.o time.o common.o mpp.o addr-map.o 5obj-y += addr-map.o
6obj-m :=
7obj-n :=
8obj- :=
9 6
10obj-$(CONFIG_GENERIC_GPIO) += gpio.o 7orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
8obj-$(CONFIG_PLAT_ORION_LEGACY) += irq.o pcie.o time.o common.o mpp.o
9obj-$(CONFIG_PLAT_ORION_LEGACY) += $(orion-gpio-y)
diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c
index 367ca89ac403..a7b8060c293a 100644
--- a/arch/arm/plat-orion/addr-map.c
+++ b/arch/arm/plat-orion/addr-map.c
@@ -48,7 +48,7 @@ EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
48static void __init __iomem * 48static void __init __iomem *
49orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win) 49orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
50{ 50{
51 return (void __iomem *)(cfg->bridge_virt_base + (win << 4)); 51 return cfg->bridge_virt_base + (win << 4);
52} 52}
53 53
54/* 54/*
@@ -143,19 +143,16 @@ void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
143 * Setup MBUS dram target info. 143 * Setup MBUS dram target info.
144 */ 144 */
145void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, 145void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
146 const u32 ddr_window_cpu_base) 146 const void __iomem *ddr_window_cpu_base)
147{ 147{
148 void __iomem *addr;
149 int i; 148 int i;
150 int cs; 149 int cs;
151 150
152 orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; 151 orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
153 152
154 addr = (void __iomem *)ddr_window_cpu_base;
155
156 for (i = 0, cs = 0; i < 4; i++) { 153 for (i = 0, cs = 0; i < 4; i++) {
157 u32 base = readl(addr + DDR_BASE_CS_OFF(i)); 154 u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i));
158 u32 size = readl(addr + DDR_SIZE_CS_OFF(i)); 155 u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i));
159 156
160 /* 157 /*
161 * Chip select enabled? 158 * Chip select enabled?
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index 87f53caef655..b8a688cad4c2 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -86,13 +86,13 @@ static void __init uart_complete(
86 struct platform_device *orion_uart, 86 struct platform_device *orion_uart,
87 struct plat_serial8250_port *data, 87 struct plat_serial8250_port *data,
88 struct resource *resources, 88 struct resource *resources,
89 unsigned int membase, 89 void __iomem *membase,
90 resource_size_t mapbase, 90 resource_size_t mapbase,
91 unsigned int irq, 91 unsigned int irq,
92 struct clk *clk) 92 struct clk *clk)
93{ 93{
94 data->mapbase = mapbase; 94 data->mapbase = mapbase;
95 data->membase = (void __iomem *)membase; 95 data->membase = membase;
96 data->irq = irq; 96 data->irq = irq;
97 data->uartclk = uart_get_clk_rate(clk); 97 data->uartclk = uart_get_clk_rate(clk);
98 orion_uart->dev.platform_data = data; 98 orion_uart->dev.platform_data = data;
@@ -120,7 +120,7 @@ static struct platform_device orion_uart0 = {
120 .id = PLAT8250_DEV_PLATFORM, 120 .id = PLAT8250_DEV_PLATFORM,
121}; 121};
122 122
123void __init orion_uart0_init(unsigned int membase, 123void __init orion_uart0_init(void __iomem *membase,
124 resource_size_t mapbase, 124 resource_size_t mapbase,
125 unsigned int irq, 125 unsigned int irq,
126 struct clk *clk) 126 struct clk *clk)
@@ -148,7 +148,7 @@ static struct platform_device orion_uart1 = {
148 .id = PLAT8250_DEV_PLATFORM1, 148 .id = PLAT8250_DEV_PLATFORM1,
149}; 149};
150 150
151void __init orion_uart1_init(unsigned int membase, 151void __init orion_uart1_init(void __iomem *membase,
152 resource_size_t mapbase, 152 resource_size_t mapbase,
153 unsigned int irq, 153 unsigned int irq,
154 struct clk *clk) 154 struct clk *clk)
@@ -176,7 +176,7 @@ static struct platform_device orion_uart2 = {
176 .id = PLAT8250_DEV_PLATFORM2, 176 .id = PLAT8250_DEV_PLATFORM2,
177}; 177};
178 178
179void __init orion_uart2_init(unsigned int membase, 179void __init orion_uart2_init(void __iomem *membase,
180 resource_size_t mapbase, 180 resource_size_t mapbase,
181 unsigned int irq, 181 unsigned int irq,
182 struct clk *clk) 182 struct clk *clk)
@@ -204,7 +204,7 @@ static struct platform_device orion_uart3 = {
204 .id = 3, 204 .id = 3,
205}; 205};
206 206
207void __init orion_uart3_init(unsigned int membase, 207void __init orion_uart3_init(void __iomem *membase,
208 resource_size_t mapbase, 208 resource_size_t mapbase,
209 unsigned int irq, 209 unsigned int irq,
210 struct clk *clk) 210 struct clk *clk)
diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h
index fd556f77562c..ec63e4a627d0 100644
--- a/arch/arm/plat-orion/include/plat/addr-map.h
+++ b/arch/arm/plat-orion/include/plat/addr-map.h
@@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info;
16struct orion_addr_map_cfg { 16struct orion_addr_map_cfg {
17 const int num_wins; /* Total number of windows */ 17 const int num_wins; /* Total number of windows */
18 const int remappable_wins; 18 const int remappable_wins;
19 const u32 bridge_virt_base; 19 void __iomem *bridge_virt_base;
20 20
21 /* If NULL, the default cpu_win_can_remap will be used, using 21 /* If NULL, the default cpu_win_can_remap will be used, using
22 the value in remappable_wins */ 22 the value in remappable_wins */
@@ -49,5 +49,5 @@ void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
49 const u8 attr, const int remap); 49 const u8 attr, const int remap);
50 50
51void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg, 51void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
52 const u32 ddr_window_cpu_base); 52 const void __iomem *ddr_window_cpu_base);
53#endif 53#endif
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
index ae2377ef63e5..6bbc3fe5f58e 100644
--- a/arch/arm/plat-orion/include/plat/common.h
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -13,22 +13,22 @@
13 13
14struct dsa_platform_data; 14struct dsa_platform_data;
15 15
16void __init orion_uart0_init(unsigned int membase, 16void __init orion_uart0_init(void __iomem *membase,
17 resource_size_t mapbase, 17 resource_size_t mapbase,
18 unsigned int irq, 18 unsigned int irq,
19 struct clk *clk); 19 struct clk *clk);
20 20
21void __init orion_uart1_init(unsigned int membase, 21void __init orion_uart1_init(void __iomem *membase,
22 resource_size_t mapbase, 22 resource_size_t mapbase,
23 unsigned int irq, 23 unsigned int irq,
24 struct clk *clk); 24 struct clk *clk);
25 25
26void __init orion_uart2_init(unsigned int membase, 26void __init orion_uart2_init(void __iomem *membase,
27 resource_size_t mapbase, 27 resource_size_t mapbase,
28 unsigned int irq, 28 unsigned int irq,
29 struct clk *clk); 29 struct clk *clk);
30 30
31void __init orion_uart3_init(unsigned int membase, 31void __init orion_uart3_init(void __iomem *membase,
32 resource_size_t mapbase, 32 resource_size_t mapbase,
33 unsigned int irq, 33 unsigned int irq,
34 struct clk *clk); 34 struct clk *clk);
diff --git a/arch/arm/plat-orion/include/plat/mpp.h b/arch/arm/plat-orion/include/plat/mpp.h
index 723adce99f41..254552fee889 100644
--- a/arch/arm/plat-orion/include/plat/mpp.h
+++ b/arch/arm/plat-orion/include/plat/mpp.h
@@ -29,6 +29,6 @@
29#define MPP_OUTPUT_MASK GENERIC_MPP(0, 0x0, 0, 1) 29#define MPP_OUTPUT_MASK GENERIC_MPP(0, 0x0, 0, 1)
30 30
31void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, 31void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
32 unsigned int mpp_max, unsigned int dev_bus); 32 unsigned int mpp_max, void __iomem *dev_bus);
33 33
34#endif 34#endif
diff --git a/arch/arm/plat-orion/include/plat/time.h b/arch/arm/plat-orion/include/plat/time.h
index 4d5f1f6e18df..07527e417c62 100644
--- a/arch/arm/plat-orion/include/plat/time.h
+++ b/arch/arm/plat-orion/include/plat/time.h
@@ -11,9 +11,9 @@
11#ifndef __PLAT_TIME_H 11#ifndef __PLAT_TIME_H
12#define __PLAT_TIME_H 12#define __PLAT_TIME_H
13 13
14void orion_time_set_base(u32 timer_base); 14void orion_time_set_base(void __iomem *timer_base);
15 15
16void orion_time_init(u32 bridge_base, u32 bridge_timer1_clr_mask, 16void orion_time_init(void __iomem *bridge_base, u32 bridge_timer1_clr_mask,
17 unsigned int irq, unsigned int tclk); 17 unsigned int irq, unsigned int tclk);
18 18
19 19
diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c
index 7740bb31d662..e686fe76a96b 100644
--- a/arch/arm/plat-orion/mpp.c
+++ b/arch/arm/plat-orion/mpp.c
@@ -18,15 +18,15 @@
18#include <plat/mpp.h> 18#include <plat/mpp.h>
19 19
20/* Address of the ith MPP control register */ 20/* Address of the ith MPP control register */
21static __init unsigned long mpp_ctrl_addr(unsigned int i, 21static __init void __iomem *mpp_ctrl_addr(unsigned int i,
22 unsigned long dev_bus) 22 void __iomem *dev_bus)
23{ 23{
24 return dev_bus + (i) * 4; 24 return dev_bus + (i) * 4;
25} 25}
26 26
27 27
28void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask, 28void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
29 unsigned int mpp_max, unsigned int dev_bus) 29 unsigned int mpp_max, void __iomem *dev_bus)
30{ 30{
31 unsigned int mpp_nr_regs = (1 + mpp_max/8); 31 unsigned int mpp_nr_regs = (1 + mpp_max/8);
32 u32 mpp_ctrl[mpp_nr_regs]; 32 u32 mpp_ctrl[mpp_nr_regs];
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 1ed8d1397fcf..0f4fa863dd55 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -180,13 +180,13 @@ static struct irqaction orion_timer_irq = {
180}; 180};
181 181
182void __init 182void __init
183orion_time_set_base(u32 _timer_base) 183orion_time_set_base(void __iomem *_timer_base)
184{ 184{
185 timer_base = (void __iomem *)_timer_base; 185 timer_base = _timer_base;
186} 186}
187 187
188void __init 188void __init
189orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask, 189orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
190 unsigned int irq, unsigned int tclk) 190 unsigned int irq, unsigned int tclk)
191{ 191{
192 u32 u; 192 u32 u;
@@ -194,7 +194,7 @@ orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
194 /* 194 /*
195 * Set SoC-specific data. 195 * Set SoC-specific data.
196 */ 196 */
197 bridge_base = (void __iomem *)_bridge_base; 197 bridge_base = _bridge_base;
198 bridge_timer1_clr_mask = _bridge_timer1_clr_mask; 198 bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
199 199
200 ticks_per_jiffy = (tclk + HZ/2) / HZ; 200 ticks_per_jiffy = (tclk + HZ/2) / HZ;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 14:38:32 -0500