diff options
author | Pavel Pisa <ppisa@pikron.com> | 2007-03-07 17:56:16 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-03-12 12:49:35 -0400 |
commit | b3c6b76ffb1a8c8d1f12e838a25c1a86f5316e2c (patch) | |
tree | 7e68897d90f93ea62b890128408cfbf2d0b57c86 /arch/arm | |
parent | 83b84c4e8c7cf00e26610f03ee59e9be010f527c (diff) |
[ARM] 4255/1: i.MX/MX1 Correct MPU PLL reference clock value.
Only System PLL clock source is selectable by CSCR_SYSTEM_SEL
bit. MPU PLL is driven by 512*CLK32 for each case.
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-imx/cpufreq.c | 6 | ||||
-rw-r--r-- | arch/arm/mach-imx/generic.c | 9 |
2 files changed, 8 insertions, 7 deletions
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c index 43525ee504d5..7e70e0b0b989 100644 --- a/arch/arm/mach-imx/cpufreq.c +++ b/arch/arm/mach-imx/cpufreq.c | |||
@@ -83,13 +83,13 @@ static void imx_set_mpctl0(u32 mpctl0) | |||
83 | * imx_compute_mpctl - compute new PLL parameters | 83 | * imx_compute_mpctl - compute new PLL parameters |
84 | * @new_mpctl: pointer to location assigned by new PLL control register value | 84 | * @new_mpctl: pointer to location assigned by new PLL control register value |
85 | * @cur_mpctl: current PLL control register parameters | 85 | * @cur_mpctl: current PLL control register parameters |
86 | * @f_ref: reference source frequency Hz | ||
86 | * @freq: required frequency in Hz | 87 | * @freq: required frequency in Hz |
87 | * @relation: is one of %CPUFREQ_RELATION_L (supremum) | 88 | * @relation: is one of %CPUFREQ_RELATION_L (supremum) |
88 | * and %CPUFREQ_RELATION_H (infimum) | 89 | * and %CPUFREQ_RELATION_H (infimum) |
89 | */ | 90 | */ |
90 | long imx_compute_mpctl(u32 *new_mpctl, u32 cur_mpctl, unsigned long freq, int relation) | 91 | long imx_compute_mpctl(u32 *new_mpctl, u32 cur_mpctl, u32 f_ref, unsigned long freq, int relation) |
91 | { | 92 | { |
92 | u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512); | ||
93 | u32 mfi; | 93 | u32 mfi; |
94 | u32 mfn; | 94 | u32 mfn; |
95 | u32 mfd; | 95 | u32 mfd; |
@@ -204,7 +204,7 @@ static int imx_set_target(struct cpufreq_policy *policy, | |||
204 | sysclk = imx_get_system_clk(); | 204 | sysclk = imx_get_system_clk(); |
205 | 205 | ||
206 | if (freq > sysclk / bclk_div_at_boot + 1000000) { | 206 | if (freq > sysclk / bclk_div_at_boot + 1000000) { |
207 | freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, freq, relation); | 207 | freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, CLK32 * 512, freq, relation); |
208 | if (freq < 0) { | 208 | if (freq < 0) { |
209 | printk(KERN_WARNING "imx: target frequency %ld Hz cannot be set\n", freq); | 209 | printk(KERN_WARNING "imx: target frequency %ld Hz cannot be set\n", freq); |
210 | return -EINVAL; | 210 | return -EINVAL; |
diff --git a/arch/arm/mach-imx/generic.c b/arch/arm/mach-imx/generic.c index b5aa49d00ca3..7a7fa51ec62c 100644 --- a/arch/arm/mach-imx/generic.c +++ b/arch/arm/mach-imx/generic.c | |||
@@ -102,7 +102,7 @@ EXPORT_SYMBOL(imx_gpio_mode); | |||
102 | * f = 2 * f_ref * -------------------- | 102 | * f = 2 * f_ref * -------------------- |
103 | * pd + 1 | 103 | * pd + 1 |
104 | */ | 104 | */ |
105 | static unsigned int imx_decode_pll(unsigned int pll) | 105 | static unsigned int imx_decode_pll(unsigned int pll, u32 f_ref) |
106 | { | 106 | { |
107 | unsigned long long ll; | 107 | unsigned long long ll; |
108 | unsigned long quot; | 108 | unsigned long quot; |
@@ -111,7 +111,6 @@ static unsigned int imx_decode_pll(unsigned int pll) | |||
111 | u32 mfn = pll & 0x3ff; | 111 | u32 mfn = pll & 0x3ff; |
112 | u32 mfd = (pll >> 16) & 0x3ff; | 112 | u32 mfd = (pll >> 16) & 0x3ff; |
113 | u32 pd = (pll >> 26) & 0xf; | 113 | u32 pd = (pll >> 26) & 0xf; |
114 | u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512); | ||
115 | 114 | ||
116 | mfi = mfi <= 5 ? 5 : mfi; | 115 | mfi = mfi <= 5 ? 5 : mfi; |
117 | 116 | ||
@@ -124,13 +123,15 @@ static unsigned int imx_decode_pll(unsigned int pll) | |||
124 | 123 | ||
125 | unsigned int imx_get_system_clk(void) | 124 | unsigned int imx_get_system_clk(void) |
126 | { | 125 | { |
127 | return imx_decode_pll(SPCTL0); | 126 | u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512); |
127 | |||
128 | return imx_decode_pll(SPCTL0, f_ref); | ||
128 | } | 129 | } |
129 | EXPORT_SYMBOL(imx_get_system_clk); | 130 | EXPORT_SYMBOL(imx_get_system_clk); |
130 | 131 | ||
131 | unsigned int imx_get_mcu_clk(void) | 132 | unsigned int imx_get_mcu_clk(void) |
132 | { | 133 | { |
133 | return imx_decode_pll(MPCTL0); | 134 | return imx_decode_pll(MPCTL0, CLK32 * 512); |
134 | } | 135 | } |
135 | EXPORT_SYMBOL(imx_get_mcu_clk); | 136 | EXPORT_SYMBOL(imx_get_mcu_clk); |
136 | 137 | ||