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authorLinus Torvalds <torvalds@linux-foundation.org>2010-10-21 19:42:32 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-10-21 19:42:32 -0400
commitb5153163ed580e00c67bdfecb02b2e3843817b3e (patch)
treeb8c878601f07f5df8f694435857a5f3dcfd75482 /arch/arm
parenta8cbf22559ceefdcdfac00701e8e6da7518b7e8e (diff)
parent6451d7783ba5ff24eb1a544eaa6665b890f30466 (diff)
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (278 commits) arm: remove machine_desc.io_pg_offst and .phys_io arm: use addruart macro to establish debug mappings arm: return both physical and virtual addresses from addruart arm/debug: consolidate addruart macros for CONFIG_DEBUG_ICEDCC ARM: make struct machine_desc definition coherent with its comment eukrea_mbimxsd-baseboard: Pass the correct GPIO to gpio_free cpuimx27: fix compile when ULPI is selected mach-pcm037_eet: fix compile errors Fixing ethernet driver compilation error for i.MX31 ADS board cpuimx51: update board support mx5: add cpuimx51sd module and its baseboard iomux-mx51: fix GPIO_1_xx 's IOMUX configuration imx-esdhc: update devices registration mx51: add resources for SD/MMC on i.MX51 iomux-mx51: fix SD1 and SD2's iomux configuration clock-mx51: rename CLOCK1 to CLOCK_CCGR for better readability clock-mx51: factorize clk_set_parent and clk_get_rate eukrea_mbimxsd: add support for DVI displays cpuimx25 & cpuimx35: fix OTG port registration in host mode i.MX31 and i.MX35 : fix errate TLSbo65953 and ENGcm09472 ...
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig76
-rw-r--r--arch/arm/Kconfig.debug19
-rw-r--r--arch/arm/Makefile11
-rw-r--r--arch/arm/common/gic.c14
-rw-r--r--arch/arm/common/pl330.c7
-rw-r--r--arch/arm/common/sa1111.c2
-rw-r--r--arch/arm/configs/at91sam9g20ek_defconfig1
-rw-r--r--arch/arm/configs/kirkwood_defconfig1
-rw-r--r--arch/arm/configs/mx27_defconfig15
-rw-r--r--arch/arm/configs/mx31pdk_defconfig44
-rw-r--r--arch/arm/configs/mx3_defconfig2
-rw-r--r--arch/arm/configs/mx51_defconfig9
-rw-r--r--arch/arm/configs/realview-smp_defconfig15
-rw-r--r--arch/arm/configs/realview_defconfig15
-rw-r--r--arch/arm/configs/s5p64x0_defconfig (renamed from arch/arm/configs/s5p6440_defconfig)3
-rw-r--r--arch/arm/configs/u300_defconfig37
-rw-r--r--arch/arm/include/asm/assembler.h27
-rw-r--r--arch/arm/include/asm/cacheflush.h65
-rw-r--r--arch/arm/include/asm/cachetype.h8
-rw-r--r--arch/arm/include/asm/elf.h4
-rw-r--r--arch/arm/include/asm/ftrace.h20
-rw-r--r--arch/arm/include/asm/hardware/coresight.h34
-rw-r--r--arch/arm/include/asm/hw_breakpoint.h133
-rw-r--r--arch/arm/include/asm/io.h1
-rw-r--r--arch/arm/include/asm/mach/arch.h9
-rw-r--r--arch/arm/include/asm/mmu_context.h29
-rw-r--r--arch/arm/include/asm/module.h31
-rw-r--r--arch/arm/include/asm/pgtable.h26
-rw-r--r--arch/arm/include/asm/processor.h4
-rw-r--r--arch/arm/include/asm/ptrace.h2
-rw-r--r--arch/arm/include/asm/seccomp.h11
-rw-r--r--arch/arm/include/asm/smp_mpidr.h17
-rw-r--r--arch/arm/include/asm/smp_plat.h25
-rw-r--r--arch/arm/include/asm/system.h6
-rw-r--r--arch/arm/include/asm/thread_info.h2
-rw-r--r--arch/arm/include/asm/tlbflush.h36
-rw-r--r--arch/arm/kernel/Makefile1
-rw-r--r--arch/arm/kernel/armksyms.c2
-rw-r--r--arch/arm/kernel/asm-offsets.c2
-rw-r--r--arch/arm/kernel/debug.S35
-rw-r--r--arch/arm/kernel/entry-armv.S11
-rw-r--r--arch/arm/kernel/entry-common.S78
-rw-r--r--arch/arm/kernel/etm.c15
-rw-r--r--arch/arm/kernel/ftrace.c188
-rw-r--r--arch/arm/kernel/head-common.S305
-rw-r--r--arch/arm/kernel/head-nommu.S5
-rw-r--r--arch/arm/kernel/head.S323
-rw-r--r--arch/arm/kernel/hw_breakpoint.c849
-rw-r--r--arch/arm/kernel/module.c68
-rw-r--r--arch/arm/kernel/process.c45
-rw-r--r--arch/arm/kernel/ptrace.c239
-rw-r--r--arch/arm/kernel/setup.c46
-rw-r--r--arch/arm/kernel/smp.c66
-rw-r--r--arch/arm/kernel/unwind.c2
-rw-r--r--arch/arm/kernel/vmlinux.lds.S39
-rw-r--r--arch/arm/mach-aaec2000/aaed2000.c2
-rw-r--r--arch/arm/mach-aaec2000/include/mach/debug-macro.S10
-rw-r--r--arch/arm/mach-aaec2000/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-at91/Kconfig15
-rw-r--r--arch/arm/mach-at91/Makefile4
-rw-r--r--arch/arm/mach-at91/board-1arm.c2
-rw-r--r--arch/arm/mach-at91/board-afeb-9260v1.c2
-rw-r--r--arch/arm/mach-at91/board-at572d940hf_ek.c4
-rw-r--r--arch/arm/mach-at91/board-cam60.c2
-rw-r--r--arch/arm/mach-at91/board-cap9adk.c2
-rw-r--r--arch/arm/mach-at91/board-carmeva.c2
-rw-r--r--arch/arm/mach-at91/board-cpu9krea.c2
-rw-r--r--arch/arm/mach-at91/board-cpuat91.c2
-rw-r--r--arch/arm/mach-at91/board-csb337.c2
-rw-r--r--arch/arm/mach-at91/board-csb637.c2
-rw-r--r--arch/arm/mach-at91/board-dk.c2
-rw-r--r--arch/arm/mach-at91/board-eb9200.c2
-rw-r--r--arch/arm/mach-at91/board-ecbat91.c2
-rw-r--r--arch/arm/mach-at91/board-eco920.c2
-rw-r--r--arch/arm/mach-at91/board-ek.c2
-rw-r--r--arch/arm/mach-at91/board-flexibity.c162
-rw-r--r--arch/arm/mach-at91/board-kafa.c2
-rw-r--r--arch/arm/mach-at91/board-kb9202.c2
-rw-r--r--arch/arm/mach-at91/board-neocore926.c2
-rw-r--r--arch/arm/mach-at91/board-picotux200.c2
-rw-r--r--arch/arm/mach-at91/board-qil-a9260.c2
-rw-r--r--arch/arm/mach-at91/board-sam9-l9260.c2
-rw-r--r--arch/arm/mach-at91/board-sam9260ek.c2
-rw-r--r--arch/arm/mach-at91/board-sam9261ek.c2
-rw-r--r--arch/arm/mach-at91/board-sam9263ek.c2
-rw-r--r--arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c329
-rw-r--r--arch/arm/mach-at91/board-sam9g20ek.c74
-rw-r--r--arch/arm/mach-at91/board-sam9m10g45ek.c6
-rw-r--r--arch/arm/mach-at91/board-sam9rlek.c2
-rw-r--r--arch/arm/mach-at91/board-snapper9260.c2
-rw-r--r--arch/arm/mach-at91/board-stamp9g20.c4
-rw-r--r--arch/arm/mach-at91/board-usb-a9260.c2
-rw-r--r--arch/arm/mach-at91/board-usb-a9263.c2
-rw-r--r--arch/arm/mach-at91/board-yl-9200.c2
-rw-r--r--arch/arm/mach-at91/include/mach/at91x40.h6
-rw-r--r--arch/arm/mach-at91/include/mach/debug-macro.S8
-rw-r--r--arch/arm/mach-at91/include/mach/system.h4
-rw-r--r--arch/arm/mach-bcmring/arch.c2
-rw-r--r--arch/arm/mach-bcmring/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-clps711x/autcpu12.c2
-rw-r--r--arch/arm/mach-clps711x/cdb89712.c2
-rw-r--r--arch/arm/mach-clps711x/ceiva.c2
-rw-r--r--arch/arm/mach-clps711x/clep7312.c2
-rw-r--r--arch/arm/mach-clps711x/edb7211-arch.c2
-rw-r--r--arch/arm/mach-clps711x/fortunet.c2
-rw-r--r--arch/arm/mach-clps711x/include/mach/debug-macro.S12
-rw-r--r--arch/arm/mach-clps711x/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-clps711x/p720t.c2
-rw-r--r--arch/arm/mach-cns3xxx/cns3420vb.c2
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/debug-macro.S10
-rw-r--r--arch/arm/mach-davinci/board-da830-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-da850-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-dm355-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-dm355-leopard.c2
-rw-r--r--arch/arm/mach-davinci/board-dm365-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-dm644x-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c4
-rw-r--r--arch/arm/mach-davinci/board-neuros-osd2.c2
-rw-r--r--arch/arm/mach-davinci/board-sffsdr.c2
-rw-r--r--arch/arm/mach-davinci/board-tnetv107x-evm.c2
-rw-r--r--arch/arm/mach-davinci/include/mach/debug-macro.S46
-rw-r--r--arch/arm/mach-dove/dove-db-setup.c2
-rw-r--r--arch/arm/mach-dove/include/mach/debug-macro.S11
-rw-r--r--arch/arm/mach-ebsa110/core.c2
-rw-r--r--arch/arm/mach-ebsa110/include/mach/debug-macro.S7
-rw-r--r--arch/arm/mach-ebsa110/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-ep93xx/adssphere.c2
-rw-r--r--arch/arm/mach-ep93xx/edb93xx.c16
-rw-r--r--arch/arm/mach-ep93xx/gesbc9312.c2
-rw-r--r--arch/arm/mach-ep93xx/include/mach/debug-macro.S11
-rw-r--r--arch/arm/mach-ep93xx/micro9.c8
-rw-r--r--arch/arm/mach-ep93xx/simone.c2
-rw-r--r--arch/arm/mach-ep93xx/snappercl15.c2
-rw-r--r--arch/arm/mach-ep93xx/ts72xx.c2
-rw-r--r--arch/arm/mach-footbridge/cats-hw.c2
-rw-r--r--arch/arm/mach-footbridge/ebsa285.c2
-rw-r--r--arch/arm/mach-footbridge/include/mach/debug-macro.S22
-rw-r--r--arch/arm/mach-footbridge/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-footbridge/netwinder-hw.c2
-rw-r--r--arch/arm/mach-footbridge/personal.c2
-rw-r--r--arch/arm/mach-gemini/board-nas4220b.c2
-rw-r--r--arch/arm/mach-gemini/board-rut1xx.c2
-rw-r--r--arch/arm/mach-gemini/board-wbd111.c2
-rw-r--r--arch/arm/mach-gemini/board-wbd222.c2
-rw-r--r--arch/arm/mach-gemini/include/mach/debug-macro.S8
-rw-r--r--arch/arm/mach-h720x/h7201-eval.c2
-rw-r--r--arch/arm/mach-h720x/h7202-eval.c2
-rw-r--r--arch/arm/mach-h720x/include/mach/debug-macro.S10
-rw-r--r--arch/arm/mach-h720x/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-imx/Kconfig14
-rw-r--r--arch/arm/mach-imx/Makefile1
-rw-r--r--arch/arm/mach-imx/clock-imx1.c2
-rw-r--r--arch/arm/mach-imx/clock-imx21.c6
-rw-r--r--arch/arm/mach-imx/clock-imx27.c48
-rw-r--r--arch/arm/mach-imx/devices-imx1.h14
-rw-r--r--arch/arm/mach-imx/devices-imx21.h36
-rw-r--r--arch/arm/mach-imx/devices-imx27.h51
-rw-r--r--arch/arm/mach-imx/devices.c56
-rw-r--r--arch/arm/mach-imx/devices.h3
-rw-r--r--arch/arm/mach-imx/eukrea_mbimx27-baseboard.c8
-rw-r--r--arch/arm/mach-imx/mach-cpuimx27.c8
-rw-r--r--arch/arm/mach-imx/mach-imx27_visstrim_m10.c261
-rw-r--r--arch/arm/mach-imx/mach-imx27lite.c10
-rw-r--r--arch/arm/mach-imx/mach-mx1ads.c8
-rw-r--r--arch/arm/mach-imx/mach-mx21ads.c4
-rw-r--r--arch/arm/mach-imx/mach-mx27_3ds.c10
-rw-r--r--arch/arm/mach-imx/mach-mx27ads.c8
-rw-r--r--arch/arm/mach-imx/mach-mxt_td60.c15
-rw-r--r--arch/arm/mach-imx/mach-pca100.c17
-rw-r--r--arch/arm/mach-imx/mach-pcm038.c10
-rw-r--r--arch/arm/mach-imx/mach-scb9328.c4
-rw-r--r--arch/arm/mach-imx/pcm970-baseboard.c4
-rw-r--r--arch/arm/mach-integrator/include/mach/debug-macro.S10
-rw-r--r--arch/arm/mach-integrator/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c2
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c2
-rw-r--r--arch/arm/mach-iop13xx/include/mach/debug-macro.S16
-rw-r--r--arch/arm/mach-iop13xx/iq81340mc.c2
-rw-r--r--arch/arm/mach-iop13xx/iq81340sc.c2
-rw-r--r--arch/arm/mach-iop32x/em7210.c2
-rw-r--r--arch/arm/mach-iop32x/glantank.c2
-rw-r--r--arch/arm/mach-iop32x/include/mach/debug-macro.S7
-rw-r--r--arch/arm/mach-iop32x/iq31244.c4
-rw-r--r--arch/arm/mach-iop32x/iq80321.c2
-rw-r--r--arch/arm/mach-iop32x/n2100.c2
-rw-r--r--arch/arm/mach-iop33x/include/mach/debug-macro.S12
-rw-r--r--arch/arm/mach-iop33x/iq80331.c2
-rw-r--r--arch/arm/mach-iop33x/iq80332.c2
-rw-r--r--arch/arm/mach-ixp2000/enp2611.c2
-rw-r--r--arch/arm/mach-ixp2000/include/mach/debug-macro.S14
-rw-r--r--arch/arm/mach-ixp2000/ixdp2400.c2
-rw-r--r--arch/arm/mach-ixp2000/ixdp2800.c2
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x01.c6
-rw-r--r--arch/arm/mach-ixp23xx/espresso.c2
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/debug-macro.S11
-rw-r--r--arch/arm/mach-ixp23xx/ixdp2351.c2
-rw-r--r--arch/arm/mach-ixp23xx/roadrunner.c2
-rw-r--r--arch/arm/mach-ixp4xx/avila-setup.c4
-rw-r--r--arch/arm/mach-ixp4xx/coyote-setup.c4
-rw-r--r--arch/arm/mach-ixp4xx/dsmg600-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/fsg-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/gateway7001-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/goramo_mlr.c2
-rw-r--r--arch/arm/mach-ixp4xx/gtwx5715-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/debug-macro.S16
-rw-r--r--arch/arm/mach-ixp4xx/ixdp425-setup.c8
-rw-r--r--arch/arm/mach-ixp4xx/nas100d-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/nslu2-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/vulcan-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/wg302v2-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/Kconfig12
-rw-r--r--arch/arm/mach-kirkwood/Makefile12
-rw-r--r--arch/arm/mach-kirkwood/d2net_v2-setup.c229
-rw-r--r--arch/arm/mach-kirkwood/db88f6281-bp-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/dockstar-setup.c110
-rw-r--r--arch/arm/mach-kirkwood/guruplug-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/include/mach/debug-macro.S11
-rw-r--r--arch/arm/mach-kirkwood/include/mach/leds-netxbig.h55
-rw-r--r--arch/arm/mach-kirkwood/lacie_v2-common.c127
-rw-r--r--arch/arm/mach-kirkwood/lacie_v2-common.h18
-rw-r--r--arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/netspace_v2-setup.c128
-rw-r--r--arch/arm/mach-kirkwood/netxbig_v2-setup.c273
-rw-r--r--arch/arm/mach-kirkwood/openrd-setup.c107
-rw-r--r--arch/arm/mach-kirkwood/rd88f6192-nas-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/rd88f6281-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/sheevaplug-setup.c4
-rw-r--r--arch/arm/mach-kirkwood/t5325-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/ts219-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/ts41x-setup.c2
-rw-r--r--arch/arm/mach-ks8695/board-acs5k.c2
-rw-r--r--arch/arm/mach-ks8695/board-dsm320.c2
-rw-r--r--arch/arm/mach-ks8695/board-micrel.c2
-rw-r--r--arch/arm/mach-ks8695/include/mach/debug-macro.S8
-rw-r--r--arch/arm/mach-l7200/include/mach/debug-macro.S38
-rw-r--r--arch/arm/mach-lh7a40x/arch-kev7a400.c2
-rw-r--r--arch/arm/mach-lh7a40x/arch-lpd7a40x.c4
-rw-r--r--arch/arm/mach-lh7a40x/include/mach/debug-macro.S10
-rw-r--r--arch/arm/mach-loki/include/mach/debug-macro.S11
-rw-r--r--arch/arm/mach-loki/lb88rc8480-setup.c2
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/debug-macro.S8
-rw-r--r--arch/arm/mach-lpc32xx/phy3250.c2
-rw-r--r--arch/arm/mach-mmp/Kconfig7
-rw-r--r--arch/arm/mach-mmp/Makefile1
-rw-r--r--arch/arm/mach-mmp/aspenite.c94
-rw-r--r--arch/arm/mach-mmp/avengers_lite.c2
-rw-r--r--arch/arm/mach-mmp/common.c10
-rw-r--r--arch/arm/mach-mmp/flint.c6
-rw-r--r--arch/arm/mach-mmp/include/mach/cputype.h49
-rw-r--r--arch/arm/mach-mmp/include/mach/debug-macro.S11
-rw-r--r--arch/arm/mach-mmp/include/mach/irqs.h4
-rw-r--r--arch/arm/mach-mmp/include/mach/mfp-pxa168.h7
-rw-r--r--arch/arm/mach-mmp/include/mach/pxa168.h20
-rw-r--r--arch/arm/mach-mmp/include/mach/regs-apmu.h12
-rw-r--r--arch/arm/mach-mmp/include/mach/teton_bga.h27
-rw-r--r--arch/arm/mach-mmp/jasper.c7
-rw-r--r--arch/arm/mach-mmp/pxa168.c16
-rw-r--r--arch/arm/mach-mmp/tavorevb.c2
-rw-r--r--arch/arm/mach-mmp/teton_bga.c89
-rw-r--r--arch/arm/mach-mmp/ttc_dkb.c6
-rw-r--r--arch/arm/mach-msm/Kconfig55
-rw-r--r--arch/arm/mach-msm/Makefile21
-rw-r--r--arch/arm/mach-msm/board-halibut.c2
-rw-r--r--arch/arm/mach-msm/board-mahimahi.c2
-rw-r--r--arch/arm/mach-msm/board-msm7x27.c8
-rw-r--r--arch/arm/mach-msm/board-msm7x30.c28
-rw-r--r--arch/arm/mach-msm/board-msm8x60.c100
-rw-r--r--arch/arm/mach-msm/board-qsd8x50.c50
-rw-r--r--arch/arm/mach-msm/board-sapphire.c2
-rw-r--r--arch/arm/mach-msm/board-trout.c2
-rw-r--r--arch/arm/mach-msm/clock-dummy.c54
-rw-r--r--arch/arm/mach-msm/devices-msm7x30.c5
-rw-r--r--arch/arm/mach-msm/devices-msm8x60-iommu.c883
-rw-r--r--arch/arm/mach-msm/devices-qsd8x50.c5
-rw-r--r--arch/arm/mach-msm/gpio.c409
-rw-r--r--arch/arm/mach-msm/gpio_hw.h278
-rw-r--r--arch/arm/mach-msm/gpiomux-7x30.c38
-rw-r--r--arch/arm/mach-msm/gpiomux-8x50.c28
-rw-r--r--arch/arm/mach-msm/gpiomux-8x60.c19
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-rw-r--r--arch/arm/mach-s5p64x0/dma.c (renamed from arch/arm/mach-s5p6440/dma.c)86
-rw-r--r--arch/arm/mach-s5p64x0/gpio.c (renamed from arch/arm/mach-s5p6440/gpio.c)104
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-rw-r--r--arch/arm/mach-s5p64x0/include/mach/dma.h (renamed from arch/arm/mach-s5p6440/include/mach/dma.h)0
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/entry-macro.S (renamed from arch/arm/mach-s5p6440/include/mach/entry-macro.S)8
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-rw-r--r--arch/arm/mach-s5p64x0/include/mach/hardware.h (renamed from arch/arm/mach-s5p6440/include/mach/hardware.h)8
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-rw-r--r--arch/arm/mm/proc-v6.S49
-rw-r--r--arch/arm/mm/proc-v7.S47
-rw-r--r--arch/arm/mm/proc-xsc3.S2
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-rw-r--r--arch/arm/mm/tlb-v7.S33
-rw-r--r--arch/arm/plat-mxc/Kconfig16
-rw-r--r--arch/arm/plat-mxc/Makefile2
-rw-r--r--arch/arm/plat-mxc/audmux-v2.c8
-rw-r--r--arch/arm/plat-mxc/devices/Kconfig10
-rw-r--r--arch/arm/plat-mxc/devices/Makefile9
-rw-r--r--arch/arm/plat-mxc/devices/platform-esdhc.c71
-rw-r--r--arch/arm/plat-mxc/devices/platform-fec.c58
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-dma.c129
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-i2c.c85
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-ssi.c107
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-uart.c137
-rw-r--r--arch/arm/plat-mxc/devices/platform-mxc_nand.c85
-rw-r--r--arch/arm/plat-mxc/devices/platform-spi_imx.c89
-rw-r--r--arch/arm/plat-mxc/ehci.c4
-rw-r--r--arch/arm/plat-mxc/epit.c242
-rw-r--r--arch/arm/plat-mxc/gpio.c2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31ads.h33
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-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S8
-rw-r--r--arch/arm/plat-mxc/include/mach/devices-common.h112
-rw-r--r--arch/arm/plat-mxc/include/mach/esdhc.h16
-rw-r--r--arch/arm/plat-mxc/include/mach/eukrea-baseboards.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx51.h120
-rw-r--r--arch/arm/plat-mxc/include/mach/iram.h41
-rw-r--r--arch/arm/plat-mxc/include/mach/mx21.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h17
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/mx31.h11
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h38
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3x.h23
-rw-r--r--arch/arm/plat-mxc/include/mach/mx51.h657
-rw-r--r--arch/arm/plat-mxc/include/mach/system.h32
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h1
-rw-r--r--arch/arm/plat-mxc/iram_alloc.c73
-rw-r--r--arch/arm/plat-nomadik/gpio.c74
-rw-r--r--arch/arm/plat-nomadik/include/plat/gpio.h2
-rw-r--r--arch/arm/plat-nomadik/include/plat/pincfg.h36
-rw-r--r--arch/arm/plat-omap/include/plat/smp.h12
-rw-r--r--arch/arm/plat-pxa/include/plat/pxa27x_keypad.h (renamed from arch/arm/mach-pxa/include/mach/pxa27x_keypad.h)10
-rw-r--r--arch/arm/plat-s5p/Kconfig9
-rw-r--r--arch/arm/plat-s5p/Makefile1
-rw-r--r--arch/arm/plat-s5p/clock.c19
-rw-r--r--arch/arm/plat-s5p/cpu.c34
-rw-r--r--arch/arm/plat-s5p/dev-onenand.c (renamed from arch/arm/mach-s5pv210/dev-onenand.c)28
-rw-r--r--arch/arm/plat-s5p/dev-uart.c58
-rw-r--r--arch/arm/plat-s5p/include/plat/pll.h7
-rw-r--r--arch/arm/plat-s5p/include/plat/s5p-clock.h8
-rw-r--r--arch/arm/plat-s5p/include/plat/s5p6440.h7
-rw-r--r--arch/arm/plat-s5p/include/plat/s5p6450.h36
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h7
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h20
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c64xx-spi.h2
-rw-r--r--arch/arm/plat-spear/include/plat/debug-macro.S8
-rw-r--r--arch/arm/plat-stmp3xxx/include/mach/debug-macro.S11
-rw-r--r--arch/arm/plat-tcc/Kconfig20
-rw-r--r--arch/arm/plat-tcc/Makefile3
-rw-r--r--arch/arm/plat-tcc/clock.c179
-rw-r--r--arch/arm/plat-tcc/include/mach/clkdev.h7
-rw-r--r--arch/arm/plat-tcc/include/mach/clock.h48
-rw-r--r--arch/arm/plat-tcc/include/mach/debug-macro.S32
-rw-r--r--arch/arm/plat-tcc/include/mach/entry-macro.S68
-rw-r--r--arch/arm/plat-tcc/include/mach/hardware.h43
-rw-r--r--arch/arm/plat-tcc/include/mach/io.h23
-rw-r--r--arch/arm/plat-tcc/include/mach/irqs.h83
-rw-r--r--arch/arm/plat-tcc/include/mach/memory.h18
-rw-r--r--arch/arm/plat-tcc/include/mach/system.h31
-rw-r--r--arch/arm/plat-tcc/include/mach/tcc8k-regs.h807
-rw-r--r--arch/arm/plat-tcc/include/mach/timex.h5
-rw-r--r--arch/arm/plat-tcc/include/mach/uncompress.h34
-rw-r--r--arch/arm/plat-tcc/include/mach/vmalloc.h10
-rw-r--r--arch/arm/plat-tcc/system.c25
814 files changed, 24047 insertions, 6582 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9103904b3dab..3849887157e7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -19,6 +19,8 @@ config ARM
19 select HAVE_KPROBES if (!XIP_KERNEL) 19 select HAVE_KPROBES if (!XIP_KERNEL)
20 select HAVE_KRETPROBES if (HAVE_KPROBES) 20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
22 select HAVE_GENERIC_DMA_COHERENT 24 select HAVE_GENERIC_DMA_COHERENT
23 select HAVE_KERNEL_GZIP 25 select HAVE_KERNEL_GZIP
24 select HAVE_KERNEL_LZO 26 select HAVE_KERNEL_LZO
@@ -27,6 +29,7 @@ config ARM
27 select HAVE_PERF_EVENTS 29 select HAVE_PERF_EVENTS
28 select PERF_USE_VMALLOC 30 select PERF_USE_VMALLOC
29 select HAVE_REGS_AND_STACK_ACCESS_API 31 select HAVE_REGS_AND_STACK_ACCESS_API
32 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
30 help 33 help
31 The ARM series is a line of low-power-consumption RISC chip designs 34 The ARM series is a line of low-power-consumption RISC chip designs
32 licensed by ARM Ltd and targeted at embedded applications and 35 licensed by ARM Ltd and targeted at embedded applications and
@@ -146,6 +149,9 @@ config ARCH_HAS_CPUFREQ
146 and that the relevant menu configurations are displayed for 149 and that the relevant menu configurations are displayed for
147 it. 150 it.
148 151
152config ARCH_HAS_CPU_IDLE_WAIT
153 def_bool y
154
149config GENERIC_HWEIGHT 155config GENERIC_HWEIGHT
150 bool 156 bool
151 default y 157 default y
@@ -511,6 +517,7 @@ config ARCH_MMP
511 select GENERIC_CLOCKEVENTS 517 select GENERIC_CLOCKEVENTS
512 select TICK_ONESHOT 518 select TICK_ONESHOT
513 select PLAT_PXA 519 select PLAT_PXA
520 select SPARSE_IRQ
514 help 521 help
515 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line. 522 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
516 523
@@ -588,6 +595,7 @@ config ARCH_PXA
588 select GENERIC_CLOCKEVENTS 595 select GENERIC_CLOCKEVENTS
589 select TICK_ONESHOT 596 select TICK_ONESHOT
590 select PLAT_PXA 597 select PLAT_PXA
598 select SPARSE_IRQ
591 help 599 help
592 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 600 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
593 601
@@ -679,8 +687,8 @@ config ARCH_S3C64XX
679 help 687 help
680 Samsung S3C64XX series based systems 688 Samsung S3C64XX series based systems
681 689
682config ARCH_S5P6440 690config ARCH_S5P64X0
683 bool "Samsung S5P6440" 691 bool "Samsung S5P6440 S5P6450"
684 select CPU_V6 692 select CPU_V6
685 select GENERIC_GPIO 693 select GENERIC_GPIO
686 select HAVE_CLK 694 select HAVE_CLK
@@ -689,7 +697,8 @@ config ARCH_S5P6440
689 select HAVE_S3C2410_I2C 697 select HAVE_S3C2410_I2C
690 select HAVE_S3C_RTC 698 select HAVE_S3C_RTC
691 help 699 help
692 Samsung S5P6440 CPU based systems 700 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
701 SMDK6450.
693 702
694config ARCH_S5P6442 703config ARCH_S5P6442
695 bool "Samsung S5P6442" 704 bool "Samsung S5P6442"
@@ -748,6 +757,15 @@ config ARCH_SHARK
748 Support for the StrongARM based Digital DNARD machine, also known 757 Support for the StrongARM based Digital DNARD machine, also known
749 as "Shark" (<http://www.shark-linux.de/shark.html>). 758 as "Shark" (<http://www.shark-linux.de/shark.html>).
750 759
760config ARCH_TCC_926
761 bool "Telechips TCC ARM926-based systems"
762 select CPU_ARM926T
763 select HAVE_CLK
764 select COMMON_CLKDEV
765 select GENERIC_CLOCKEVENTS
766 help
767 Support for Telechips TCC ARM926-based systems.
768
751config ARCH_LH7A40X 769config ARCH_LH7A40X
752 bool "Sharp LH7A40X" 770 bool "Sharp LH7A40X"
753 select CPU_ARM922T 771 select CPU_ARM922T
@@ -916,6 +934,8 @@ source "arch/arm/plat-s5p/Kconfig"
916 934
917source "arch/arm/plat-spear/Kconfig" 935source "arch/arm/plat-spear/Kconfig"
918 936
937source "arch/arm/plat-tcc/Kconfig"
938
919if ARCH_S3C2410 939if ARCH_S3C2410
920source "arch/arm/mach-s3c2400/Kconfig" 940source "arch/arm/mach-s3c2400/Kconfig"
921source "arch/arm/mach-s3c2410/Kconfig" 941source "arch/arm/mach-s3c2410/Kconfig"
@@ -929,7 +949,7 @@ if ARCH_S3C64XX
929source "arch/arm/mach-s3c64xx/Kconfig" 949source "arch/arm/mach-s3c64xx/Kconfig"
930endif 950endif
931 951
932source "arch/arm/mach-s5p6440/Kconfig" 952source "arch/arm/mach-s5p64x0/Kconfig"
933 953
934source "arch/arm/mach-s5p6442/Kconfig" 954source "arch/arm/mach-s5p6442/Kconfig"
935 955
@@ -1003,7 +1023,7 @@ endif
1003 1023
1004config ARM_ERRATA_411920 1024config ARM_ERRATA_411920
1005 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 1025 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1006 depends on CPU_V6 && !SMP 1026 depends on CPU_V6
1007 help 1027 help
1008 Invalidation of the Instruction Cache operation can 1028 Invalidation of the Instruction Cache operation can
1009 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 1029 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
@@ -1182,13 +1202,13 @@ source "kernel/time/Kconfig"
1182 1202
1183config SMP 1203config SMP
1184 bool "Symmetric Multi-Processing (EXPERIMENTAL)" 1204 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1185 depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\ 1205 depends on EXPERIMENTAL
1186 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\
1187 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
1188 depends on GENERIC_CLOCKEVENTS 1206 depends on GENERIC_CLOCKEVENTS
1207 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1208 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\
1209 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
1189 select USE_GENERIC_SMP_HELPERS 1210 select USE_GENERIC_SMP_HELPERS
1190 select HAVE_ARM_SCU if ARCH_REALVIEW || ARCH_OMAP4 || ARCH_S5PV310 ||\ 1211 select HAVE_ARM_SCU
1191 ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
1192 help 1212 help
1193 This enables support for systems with more than one CPU. If you have 1213 This enables support for systems with more than one CPU. If you have
1194 a system with only one CPU, like most personal computers, say N. If 1214 a system with only one CPU, like most personal computers, say N. If
@@ -1206,6 +1226,19 @@ config SMP
1206 1226
1207 If you don't know what to do here, say N. 1227 If you don't know what to do here, say N.
1208 1228
1229config SMP_ON_UP
1230 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1231 depends on EXPERIMENTAL
1232 depends on SMP && !XIP && !THUMB2_KERNEL
1233 default y
1234 help
1235 SMP kernels contain instructions which fail on non-SMP processors.
1236 Enabling this option allows the kernel to modify itself to make
1237 these instructions safe. Disabling it allows about 1K of space
1238 savings.
1239
1240 If you don't know what to do here, say Y.
1241
1209config HAVE_ARM_SCU 1242config HAVE_ARM_SCU
1210 bool 1243 bool
1211 depends on SMP 1244 depends on SMP
@@ -1256,12 +1289,9 @@ config HOTPLUG_CPU
1256 1289
1257config LOCAL_TIMERS 1290config LOCAL_TIMERS
1258 bool "Use local timer interrupts" 1291 bool "Use local timer interrupts"
1259 depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \ 1292 depends on SMP
1260 REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1261 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
1262 default y 1293 default y
1263 select HAVE_ARM_TWD if ARCH_REALVIEW || ARCH_OMAP4 || ARCH_S5PV310 || \ 1294 select HAVE_ARM_TWD
1264 ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS
1265 help 1295 help
1266 Enable support for local timers on SMP platforms, rather then the 1296 Enable support for local timers on SMP platforms, rather then the
1267 legacy IPI broadcast method. Local timers allows the system 1297 legacy IPI broadcast method. Local timers allows the system
@@ -1272,7 +1302,7 @@ source kernel/Kconfig.preempt
1272 1302
1273config HZ 1303config HZ
1274 int 1304 int
1275 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || \ 1305 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1276 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310 1306 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
1277 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER 1307 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1278 default AT91_TIMER_HZ if ARCH_AT91 1308 default AT91_TIMER_HZ if ARCH_AT91
@@ -1478,6 +1508,20 @@ config UACCESS_WITH_MEMCPY
1478 However, if the CPU data cache is using a write-allocate mode, 1508 However, if the CPU data cache is using a write-allocate mode,
1479 this option is unlikely to provide any performance gain. 1509 this option is unlikely to provide any performance gain.
1480 1510
1511config SECCOMP
1512 bool
1513 prompt "Enable seccomp to safely compute untrusted bytecode"
1514 ---help---
1515 This kernel feature is useful for number crunching applications
1516 that may need to compute untrusted bytecode during their
1517 execution. By using pipes or other transports made available to
1518 the process as file descriptors supporting the read/write
1519 syscalls, it's possible to isolate those applications in
1520 their own address space using seccomp. Once seccomp is
1521 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1522 and the task is only allowed to execute a few safe syscalls
1523 defined by each seccomp mode.
1524
1481config CC_STACKPROTECTOR 1525config CC_STACKPROTECTOR
1482 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)" 1526 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1483 help 1527 help
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 91344af75f39..2fd0b99afc4b 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -2,6 +2,20 @@ menu "Kernel hacking"
2 2
3source "lib/Kconfig.debug" 3source "lib/Kconfig.debug"
4 4
5config STRICT_DEVMEM
6 bool "Filter access to /dev/mem"
7 depends on MMU
8 ---help---
9 If this option is disabled, you allow userspace (root) access to all
10 of memory, including kernel and userspace memory. Accidental
11 access to this is obviously disastrous, but specific access can
12 be used by people debugging the kernel.
13
14 If this option is switched on, the /dev/mem file only allows
15 userspace access to memory mapped peripherals.
16
17 If in doubt, say Y.
18
5# RMK wants arm kernels compiled with frame pointers or stack unwinding. 19# RMK wants arm kernels compiled with frame pointers or stack unwinding.
6# If you know what you are doing and are willing to live without stack 20# If you know what you are doing and are willing to live without stack
7# traces, you can get a slightly smaller kernel by setting this option to 21# traces, you can get a slightly smaller kernel by setting this option to
@@ -27,6 +41,11 @@ config ARM_UNWIND
27 the performance is not affected. Currently, this feature 41 the performance is not affected. Currently, this feature
28 only works with EABI compilers. If unsure say Y. 42 only works with EABI compilers. If unsure say Y.
29 43
44config OLD_MCOUNT
45 bool
46 depends on FUNCTION_TRACER && FRAME_POINTER
47 default y
48
30config DEBUG_USER 49config DEBUG_USER
31 bool "Verbose user fault messages" 50 bool "Verbose user fault messages"
32 help 51 help
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 59c1ce858fc8..b87aed028eef 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -173,7 +173,7 @@ machine-$(CONFIG_ARCH_RPC) := rpc
173machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443 173machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443
174machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 174machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
175machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx 175machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx
176machine-$(CONFIG_ARCH_S5P6440) := s5p6440 176machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
177machine-$(CONFIG_ARCH_S5P6442) := s5p6442 177machine-$(CONFIG_ARCH_S5P6442) := s5p6442
178machine-$(CONFIG_ARCH_S5PC100) := s5pc100 178machine-$(CONFIG_ARCH_S5PC100) := s5pc100
179machine-$(CONFIG_ARCH_S5PV210) := s5pv210 179machine-$(CONFIG_ARCH_S5PV210) := s5pv210
@@ -183,6 +183,7 @@ machine-$(CONFIG_ARCH_SHARK) := shark
183machine-$(CONFIG_ARCH_SHMOBILE) := shmobile 183machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
184machine-$(CONFIG_ARCH_STMP378X) := stmp378x 184machine-$(CONFIG_ARCH_STMP378X) := stmp378x
185machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx 185machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx
186machine-$(CONFIG_ARCH_TCC8K) := tcc8k
186machine-$(CONFIG_ARCH_TEGRA) := tegra 187machine-$(CONFIG_ARCH_TEGRA) := tegra
187machine-$(CONFIG_ARCH_U300) := u300 188machine-$(CONFIG_ARCH_U300) := u300
188machine-$(CONFIG_ARCH_U8500) := ux500 189machine-$(CONFIG_ARCH_U8500) := ux500
@@ -202,6 +203,7 @@ plat-$(CONFIG_ARCH_MXC) := mxc
202plat-$(CONFIG_ARCH_OMAP) := omap 203plat-$(CONFIG_ARCH_OMAP) := omap
203plat-$(CONFIG_ARCH_S3C64XX) := samsung 204plat-$(CONFIG_ARCH_S3C64XX) := samsung
204plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx 205plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx
206plat-$(CONFIG_ARCH_TCC_926) := tcc
205plat-$(CONFIG_PLAT_IOP) := iop 207plat-$(CONFIG_PLAT_IOP) := iop
206plat-$(CONFIG_PLAT_NOMADIK) := nomadik 208plat-$(CONFIG_PLAT_NOMADIK) := nomadik
207plat-$(CONFIG_PLAT_ORION) := orion 209plat-$(CONFIG_PLAT_ORION) := orion
@@ -245,13 +247,14 @@ ifeq ($(FASTFPE),$(wildcard $(FASTFPE)))
245FASTFPE_OBJ :=$(FASTFPE)/ 247FASTFPE_OBJ :=$(FASTFPE)/
246endif 248endif
247 249
248# If we have a machine-specific directory, then include it in the build.
249core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
250core-y += $(machdirs) $(platdirs)
251core-$(CONFIG_FPE_NWFPE) += arch/arm/nwfpe/ 250core-$(CONFIG_FPE_NWFPE) += arch/arm/nwfpe/
252core-$(CONFIG_FPE_FASTFPE) += $(FASTFPE_OBJ) 251core-$(CONFIG_FPE_FASTFPE) += $(FASTFPE_OBJ)
253core-$(CONFIG_VFP) += arch/arm/vfp/ 252core-$(CONFIG_VFP) += arch/arm/vfp/
254 253
254# If we have a machine-specific directory, then include it in the build.
255core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
256core-y += $(machdirs) $(platdirs)
257
255drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/ 258drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/
256 259
257libs-y := arch/arm/lib/ $(libs-y) 260libs-y := arch/arm/lib/ $(libs-y)
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 7dfa9a85bc0c..ada6359160eb 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -67,25 +67,11 @@ static inline unsigned int gic_irq(unsigned int irq)
67 67
68/* 68/*
69 * Routines to acknowledge, disable and enable interrupts 69 * Routines to acknowledge, disable and enable interrupts
70 *
71 * Linux assumes that when we're done with an interrupt we need to
72 * unmask it, in the same way we need to unmask an interrupt when
73 * we first enable it.
74 *
75 * The GIC has a separate notion of "end of interrupt" to re-enable
76 * an interrupt after handling, in order to support hardware
77 * prioritisation.
78 *
79 * We can make the GIC behave in the way that Linux expects by making
80 * our "acknowledge" routine disable the interrupt, then mark it as
81 * complete.
82 */ 70 */
83static void gic_ack_irq(unsigned int irq) 71static void gic_ack_irq(unsigned int irq)
84{ 72{
85 u32 mask = 1 << (irq % 32);
86 73
87 spin_lock(&irq_controller_lock); 74 spin_lock(&irq_controller_lock);
88 writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
89 writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI); 75 writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI);
90 spin_unlock(&irq_controller_lock); 76 spin_unlock(&irq_controller_lock);
91} 77}
diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c
index 5ebbab6242a7..8f0f86db3602 100644
--- a/arch/arm/common/pl330.c
+++ b/arch/arm/common/pl330.c
@@ -146,8 +146,7 @@
146#define DESIGNER 0x41 146#define DESIGNER 0x41
147#define REVISION 0x0 147#define REVISION 0x0
148#define INTEG_CFG 0x0 148#define INTEG_CFG 0x0
149#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12) \ 149#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
150 | (REVISION << 20) | (INTEG_CFG << 24))
151 150
152#define PCELL_ID_VAL 0xb105f00d 151#define PCELL_ID_VAL 0xb105f00d
153 152
@@ -1859,10 +1858,10 @@ int pl330_add(struct pl330_info *pi)
1859 regs = pi->base; 1858 regs = pi->base;
1860 1859
1861 /* Check if we can handle this DMAC */ 1860 /* Check if we can handle this DMAC */
1862 if (get_id(pi, PERIPH_ID) != PERIPH_ID_VAL 1861 if ((get_id(pi, PERIPH_ID) & 0xfffff) != PERIPH_ID_VAL
1863 || get_id(pi, PCELL_ID) != PCELL_ID_VAL) { 1862 || get_id(pi, PCELL_ID) != PCELL_ID_VAL) {
1864 dev_err(pi->dev, "PERIPH_ID 0x%x, PCELL_ID 0x%x !\n", 1863 dev_err(pi->dev, "PERIPH_ID 0x%x, PCELL_ID 0x%x !\n",
1865 readl(regs + PERIPH_ID), readl(regs + PCELL_ID)); 1864 get_id(pi, PERIPH_ID), get_id(pi, PCELL_ID));
1866 return -EINVAL; 1865 return -EINVAL;
1867 } 1866 }
1868 1867
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index 517d50ddbeb3..c0258a8c103b 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -678,7 +678,7 @@ out:
678 * %-EBUSY physical address already marked in-use. 678 * %-EBUSY physical address already marked in-use.
679 * %0 successful. 679 * %0 successful.
680 */ 680 */
681static int 681static int __devinit
682__sa1111_probe(struct device *me, struct resource *mem, int irq) 682__sa1111_probe(struct device *me, struct resource *mem, int irq)
683{ 683{
684 struct sa1111 *sachip; 684 struct sa1111 *sachip;
diff --git a/arch/arm/configs/at91sam9g20ek_defconfig b/arch/arm/configs/at91sam9g20ek_defconfig
index f1bac70d6ce9..9e90e6d79297 100644
--- a/arch/arm/configs/at91sam9g20ek_defconfig
+++ b/arch/arm/configs/at91sam9g20ek_defconfig
@@ -13,6 +13,7 @@ CONFIG_MODULE_UNLOAD=y
13CONFIG_ARCH_AT91=y 13CONFIG_ARCH_AT91=y
14CONFIG_ARCH_AT91SAM9G20=y 14CONFIG_ARCH_AT91SAM9G20=y
15CONFIG_MACH_AT91SAM9G20EK=y 15CONFIG_MACH_AT91SAM9G20EK=y
16CONFIG_MACH_AT91SAM9G20EK_2MMC=y
16CONFIG_AT91_PROGRAMMABLE_CLOCKS=y 17CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
17# CONFIG_ARM_THUMB is not set 18# CONFIG_ARM_THUMB is not set
18CONFIG_AEABI=y 19CONFIG_AEABI=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index ccc9c9959b82..2f7042813765 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -15,6 +15,7 @@ CONFIG_MACH_MV88F6281GTW_GE=y
15CONFIG_MACH_SHEEVAPLUG=y 15CONFIG_MACH_SHEEVAPLUG=y
16CONFIG_MACH_ESATA_SHEEVAPLUG=y 16CONFIG_MACH_ESATA_SHEEVAPLUG=y
17CONFIG_MACH_GURUPLUG=y 17CONFIG_MACH_GURUPLUG=y
18CONFIG_MACH_DOCKSTAR=y
18CONFIG_MACH_TS219=y 19CONFIG_MACH_TS219=y
19CONFIG_MACH_TS41X=y 20CONFIG_MACH_TS41X=y
20CONFIG_MACH_OPENRD_BASE=y 21CONFIG_MACH_OPENRD_BASE=y
diff --git a/arch/arm/configs/mx27_defconfig b/arch/arm/configs/mx27_defconfig
index b2038b0e266f..813cfb366c18 100644
--- a/arch/arm/configs/mx27_defconfig
+++ b/arch/arm/configs/mx27_defconfig
@@ -21,8 +21,14 @@ CONFIG_ARCH_MX2=y
21CONFIG_MACH_MX27=y 21CONFIG_MACH_MX27=y
22CONFIG_MACH_MX27ADS=y 22CONFIG_MACH_MX27ADS=y
23CONFIG_MACH_PCM038=y 23CONFIG_MACH_PCM038=y
24CONFIG_MACH_CPUIMX27=y
25CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y
26CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y
24CONFIG_MACH_MX27_3DS=y 27CONFIG_MACH_MX27_3DS=y
28CONFIG_MACH_IMX27_VISSTRIM_M10=y
25CONFIG_MACH_IMX27LITE=y 29CONFIG_MACH_IMX27LITE=y
30CONFIG_MACH_PCA100=y
31CONFIG_MACH_MXT_TD60=y
26CONFIG_MXC_IRQ_PRIOR=y 32CONFIG_MXC_IRQ_PRIOR=y
27CONFIG_MXC_PWM=y 33CONFIG_MXC_PWM=y
28CONFIG_NO_HZ=y 34CONFIG_NO_HZ=y
@@ -76,7 +82,9 @@ CONFIG_INPUT_EVDEV=y
76# CONFIG_INPUT_KEYBOARD is not set 82# CONFIG_INPUT_KEYBOARD is not set
77# CONFIG_INPUT_MOUSE is not set 83# CONFIG_INPUT_MOUSE is not set
78CONFIG_INPUT_TOUCHSCREEN=y 84CONFIG_INPUT_TOUCHSCREEN=y
85CONFIG_TOUCHSCREEN_ADS7846=m
79# CONFIG_SERIO is not set 86# CONFIG_SERIO is not set
87CONFIG_SERIAL_8250=m
80CONFIG_SERIAL_IMX=y 88CONFIG_SERIAL_IMX=y
81CONFIG_SERIAL_IMX_CONSOLE=y 89CONFIG_SERIAL_IMX_CONSOLE=y
82# CONFIG_LEGACY_PTYS is not set 90# CONFIG_LEGACY_PTYS is not set
@@ -85,19 +93,20 @@ CONFIG_I2C=y
85CONFIG_I2C_CHARDEV=y 93CONFIG_I2C_CHARDEV=y
86CONFIG_I2C_IMX=y 94CONFIG_I2C_IMX=y
87CONFIG_SPI=y 95CONFIG_SPI=y
88CONFIG_SPI_BITBANG=y 96CONFIG_SPI_IMX=y
89CONFIG_W1=y 97CONFIG_W1=y
90CONFIG_W1_MASTER_MXC=y 98CONFIG_W1_MASTER_MXC=y
91CONFIG_W1_SLAVE_THERM=y 99CONFIG_W1_SLAVE_THERM=y
92# CONFIG_HWMON is not set 100# CONFIG_HWMON is not set
93CONFIG_FB=y 101CONFIG_FB=y
94CONFIG_FB_IMX=y 102CONFIG_FB_IMX=y
95# CONFIG_VGA_CONSOLE is not set
96CONFIG_FRAMEBUFFER_CONSOLE=y 103CONFIG_FRAMEBUFFER_CONSOLE=y
97CONFIG_FONTS=y 104CONFIG_FONTS=y
98CONFIG_FONT_8x8=y 105CONFIG_FONT_8x8=y
99# CONFIG_HID_SUPPORT is not set 106# CONFIG_HID_SUPPORT is not set
100# CONFIG_USB_SUPPORT is not set 107CONFIG_USB=m
108# CONFIG_USB_DEVICE_CLASS is not set
109CONFIG_USB_ULPI=y
101CONFIG_MMC=y 110CONFIG_MMC=y
102CONFIG_MMC_MXC=y 111CONFIG_MMC_MXC=y
103CONFIG_RTC_CLASS=y 112CONFIG_RTC_CLASS=y
diff --git a/arch/arm/configs/mx31pdk_defconfig b/arch/arm/configs/mx31pdk_defconfig
deleted file mode 100644
index 2d29329749e4..000000000000
--- a/arch/arm/configs/mx31pdk_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
1# CONFIG_LOCALVERSION_AUTO is not set
2# CONFIG_SWAP is not set
3# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
4# CONFIG_COMPAT_BRK is not set
5# CONFIG_IOSCHED_DEADLINE is not set
6# CONFIG_IOSCHED_CFQ is not set
7CONFIG_ARCH_MXC=y
8# CONFIG_MACH_MX31ADS is not set
9CONFIG_MACH_MX31_3DS=y
10CONFIG_AEABI=y
11CONFIG_NET=y
12CONFIG_PACKET=y
13CONFIG_UNIX=y
14CONFIG_NET_KEY=y
15CONFIG_INET=y
16CONFIG_IP_PNP=y
17CONFIG_IP_PNP_DHCP=y
18# CONFIG_INET_LRO is not set
19CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
20# CONFIG_PREVENT_FIRMWARE_BUILD is not set
21# CONFIG_FIRMWARE_IN_KERNEL is not set
22# CONFIG_BLK_DEV is not set
23# CONFIG_MISC_DEVICES is not set
24CONFIG_NETDEVICES=y
25CONFIG_NET_ETHERNET=y
26# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
27# CONFIG_INPUT_KEYBOARD is not set
28# CONFIG_INPUT_MOUSE is not set
29# CONFIG_SERIO is not set
30# CONFIG_DEVKMEM is not set
31CONFIG_SERIAL_IMX=y
32CONFIG_SERIAL_IMX_CONSOLE=y
33# CONFIG_LEGACY_PTYS is not set
34# CONFIG_HW_RANDOM is not set
35# CONFIG_HWMON is not set
36# CONFIG_VGA_CONSOLE is not set
37# CONFIG_HID_SUPPORT is not set
38# CONFIG_USB_SUPPORT is not set
39# CONFIG_DNOTIFY is not set
40# CONFIG_ENABLE_WARN_DEPRECATED is not set
41# CONFIG_ENABLE_MUST_CHECK is not set
42# CONFIG_RCU_CPU_STALL_DETECTOR is not set
43# CONFIG_CRYPTO_ANSI_CPRNG is not set
44# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig
index 161f907b611f..f0c339fd5d21 100644
--- a/arch/arm/configs/mx3_defconfig
+++ b/arch/arm/configs/mx3_defconfig
@@ -24,6 +24,7 @@ CONFIG_MACH_PCM043=y
24CONFIG_MACH_ARMADILLO5X0=y 24CONFIG_MACH_ARMADILLO5X0=y
25CONFIG_MACH_MX35_3DS=y 25CONFIG_MACH_MX35_3DS=y
26CONFIG_MACH_KZM_ARM11_01=y 26CONFIG_MACH_KZM_ARM11_01=y
27CONFIG_MACH_EUKREA_CPUIMX35=y
27CONFIG_MXC_IRQ_PRIOR=y 28CONFIG_MXC_IRQ_PRIOR=y
28CONFIG_MXC_PWM=y 29CONFIG_MXC_PWM=y
29CONFIG_NO_HZ=y 30CONFIG_NO_HZ=y
@@ -108,7 +109,6 @@ CONFIG_MMC=y
108CONFIG_MMC_MXC=y 109CONFIG_MMC_MXC=y
109CONFIG_DMADEVICES=y 110CONFIG_DMADEVICES=y
110# CONFIG_DNOTIFY is not set 111# CONFIG_DNOTIFY is not set
111CONFIG_INOTIFY=y
112CONFIG_TMPFS=y 112CONFIG_TMPFS=y
113CONFIG_JFFS2_FS=y 113CONFIG_JFFS2_FS=y
114CONFIG_UBIFS_FS=y 114CONFIG_UBIFS_FS=y
diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig
index a665ecbbe2bc..163cfee7644c 100644
--- a/arch/arm/configs/mx51_defconfig
+++ b/arch/arm/configs/mx51_defconfig
@@ -15,6 +15,8 @@ CONFIG_MODULE_SRCVERSION_ALL=y
15CONFIG_ARCH_MXC=y 15CONFIG_ARCH_MXC=y
16CONFIG_ARCH_MX5=y 16CONFIG_ARCH_MX5=y
17CONFIG_MACH_MX51_BABBAGE=y 17CONFIG_MACH_MX51_BABBAGE=y
18CONFIG_MACH_MX51_3DS=y
19CONFIG_MACH_EUKREA_CPUIMX51=y
18CONFIG_NO_HZ=y 20CONFIG_NO_HZ=y
19CONFIG_HIGH_RES_TIMERS=y 21CONFIG_HIGH_RES_TIMERS=y
20CONFIG_PREEMPT_VOLUNTARY=y 22CONFIG_PREEMPT_VOLUNTARY=y
@@ -69,7 +71,6 @@ CONFIG_REALTEK_PHY=y
69CONFIG_NATIONAL_PHY=y 71CONFIG_NATIONAL_PHY=y
70CONFIG_STE10XP=y 72CONFIG_STE10XP=y
71CONFIG_LSI_ET1011C_PHY=y 73CONFIG_LSI_ET1011C_PHY=y
72CONFIG_FIXED_PHY=y
73CONFIG_MDIO_BITBANG=y 74CONFIG_MDIO_BITBANG=y
74CONFIG_MDIO_GPIO=y 75CONFIG_MDIO_GPIO=y
75CONFIG_NET_ETHERNET=y 76CONFIG_NET_ETHERNET=y
@@ -100,7 +101,6 @@ CONFIG_I2C_ALGOPCF=m
100CONFIG_I2C_ALGOPCA=m 101CONFIG_I2C_ALGOPCA=m
101CONFIG_GPIO_SYSFS=y 102CONFIG_GPIO_SYSFS=y
102# CONFIG_HWMON is not set 103# CONFIG_HWMON is not set
103# CONFIG_VGA_CONSOLE is not set
104# CONFIG_HID_SUPPORT is not set 104# CONFIG_HID_SUPPORT is not set
105CONFIG_USB=y 105CONFIG_USB=y
106CONFIG_USB_EHCI_HCD=y 106CONFIG_USB_EHCI_HCD=y
@@ -117,13 +117,11 @@ CONFIG_EXT2_FS_XATTR=y
117CONFIG_EXT2_FS_POSIX_ACL=y 117CONFIG_EXT2_FS_POSIX_ACL=y
118CONFIG_EXT2_FS_SECURITY=y 118CONFIG_EXT2_FS_SECURITY=y
119CONFIG_EXT3_FS=y 119CONFIG_EXT3_FS=y
120CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
121CONFIG_EXT3_FS_POSIX_ACL=y 120CONFIG_EXT3_FS_POSIX_ACL=y
122CONFIG_EXT3_FS_SECURITY=y 121CONFIG_EXT3_FS_SECURITY=y
123CONFIG_EXT4_FS=y 122CONFIG_EXT4_FS=y
124CONFIG_EXT4_FS_POSIX_ACL=y 123CONFIG_EXT4_FS_POSIX_ACL=y
125CONFIG_EXT4_FS_SECURITY=y 124CONFIG_EXT4_FS_SECURITY=y
126CONFIG_INOTIFY=y
127CONFIG_QUOTA=y 125CONFIG_QUOTA=y
128CONFIG_QUOTA_NETLINK_INTERFACE=y 126CONFIG_QUOTA_NETLINK_INTERFACE=y
129# CONFIG_PRINT_QUOTA_WARNING is not set 127# CONFIG_PRINT_QUOTA_WARNING is not set
@@ -136,6 +134,7 @@ CONFIG_ZISOFS=y
136CONFIG_UDF_FS=m 134CONFIG_UDF_FS=m
137CONFIG_MSDOS_FS=m 135CONFIG_MSDOS_FS=m
138CONFIG_VFAT_FS=y 136CONFIG_VFAT_FS=y
137CONFIG_TMPFS=y
139CONFIG_CONFIGFS_FS=m 138CONFIG_CONFIGFS_FS=m
140CONFIG_NFS_FS=y 139CONFIG_NFS_FS=y
141CONFIG_NFS_V3=y 140CONFIG_NFS_V3=y
@@ -151,7 +150,6 @@ CONFIG_NLS_UTF8=y
151CONFIG_MAGIC_SYSRQ=y 150CONFIG_MAGIC_SYSRQ=y
152CONFIG_DEBUG_FS=y 151CONFIG_DEBUG_FS=y
153CONFIG_DEBUG_KERNEL=y 152CONFIG_DEBUG_KERNEL=y
154# CONFIG_DETECT_SOFTLOCKUP is not set
155# CONFIG_SCHED_DEBUG is not set 153# CONFIG_SCHED_DEBUG is not set
156# CONFIG_DEBUG_BUGVERBOSE is not set 154# CONFIG_DEBUG_BUGVERBOSE is not set
157# CONFIG_RCU_CPU_STALL_DETECTOR is not set 155# CONFIG_RCU_CPU_STALL_DETECTOR is not set
@@ -159,7 +157,6 @@ CONFIG_DEBUG_KERNEL=y
159# CONFIG_ARM_UNWIND is not set 157# CONFIG_ARM_UNWIND is not set
160CONFIG_DEBUG_LL=y 158CONFIG_DEBUG_LL=y
161CONFIG_EARLY_PRINTK=y 159CONFIG_EARLY_PRINTK=y
162CONFIG_KEYS=y
163CONFIG_SECURITYFS=y 160CONFIG_SECURITYFS=y
164CONFIG_CRYPTO_DEFLATE=y 161CONFIG_CRYPTO_DEFLATE=y
165CONFIG_CRYPTO_LZO=y 162CONFIG_CRYPTO_LZO=y
diff --git a/arch/arm/configs/realview-smp_defconfig b/arch/arm/configs/realview-smp_defconfig
index 9312ef9f9bf4..5ca7a61f7c01 100644
--- a/arch/arm/configs/realview-smp_defconfig
+++ b/arch/arm/configs/realview-smp_defconfig
@@ -39,6 +39,7 @@ CONFIG_MTD_CFI=y
39CONFIG_MTD_CFI_INTELEXT=y 39CONFIG_MTD_CFI_INTELEXT=y
40CONFIG_MTD_CFI_AMDSTD=y 40CONFIG_MTD_CFI_AMDSTD=y
41CONFIG_MTD_ARM_INTEGRATOR=y 41CONFIG_MTD_ARM_INTEGRATOR=y
42CONFIG_ARM_CHARLCD=y
42CONFIG_NETDEVICES=y 43CONFIG_NETDEVICES=y
43CONFIG_SMSC_PHY=y 44CONFIG_SMSC_PHY=y
44CONFIG_NET_ETHERNET=y 45CONFIG_NET_ETHERNET=y
@@ -52,10 +53,13 @@ CONFIG_SERIAL_AMBA_PL011=y
52CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 53CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
53CONFIG_LEGACY_PTY_COUNT=16 54CONFIG_LEGACY_PTY_COUNT=16
54# CONFIG_HW_RANDOM is not set 55# CONFIG_HW_RANDOM is not set
56CONFIG_I2C=y
57CONFIG_I2C_VERSATILE=y
58CONFIG_SPI=y
59CONFIG_GPIOLIB=y
55# CONFIG_HWMON is not set 60# CONFIG_HWMON is not set
56CONFIG_FB=y 61CONFIG_FB=y
57CONFIG_FB_ARMCLCD=y 62CONFIG_FB_ARMCLCD=y
58# CONFIG_VGA_CONSOLE is not set
59CONFIG_FRAMEBUFFER_CONSOLE=y 63CONFIG_FRAMEBUFFER_CONSOLE=y
60CONFIG_LOGO=y 64CONFIG_LOGO=y
61# CONFIG_LOGO_LINUX_MONO is not set 65# CONFIG_LOGO_LINUX_MONO is not set
@@ -70,7 +74,13 @@ CONFIG_SND_ARMAACI=y
70# CONFIG_USB_SUPPORT is not set 74# CONFIG_USB_SUPPORT is not set
71CONFIG_MMC=y 75CONFIG_MMC=y
72CONFIG_MMC_ARMMMCI=y 76CONFIG_MMC_ARMMMCI=y
73CONFIG_INOTIFY=y 77CONFIG_NEW_LEDS=y
78CONFIG_LEDS_CLASS=y
79CONFIG_LEDS_TRIGGERS=y
80CONFIG_LEDS_TRIGGER_HEARTBEAT=y
81CONFIG_RTC_CLASS=y
82CONFIG_RTC_DRV_DS1307=y
83CONFIG_RTC_DRV_PL031=y
74CONFIG_VFAT_FS=y 84CONFIG_VFAT_FS=y
75CONFIG_TMPFS=y 85CONFIG_TMPFS=y
76CONFIG_CRAMFS=y 86CONFIG_CRAMFS=y
@@ -80,6 +90,7 @@ CONFIG_ROOT_NFS=y
80CONFIG_NLS_CODEPAGE_437=y 90CONFIG_NLS_CODEPAGE_437=y
81CONFIG_NLS_ISO8859_1=y 91CONFIG_NLS_ISO8859_1=y
82CONFIG_MAGIC_SYSRQ=y 92CONFIG_MAGIC_SYSRQ=y
93CONFIG_DEBUG_FS=y
83CONFIG_DEBUG_KERNEL=y 94CONFIG_DEBUG_KERNEL=y
84# CONFIG_SCHED_DEBUG is not set 95# CONFIG_SCHED_DEBUG is not set
85# CONFIG_RCU_CPU_STALL_DETECTOR is not set 96# CONFIG_RCU_CPU_STALL_DETECTOR is not set
diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig
index fb75192ee7e5..fcaa60328051 100644
--- a/arch/arm/configs/realview_defconfig
+++ b/arch/arm/configs/realview_defconfig
@@ -38,6 +38,7 @@ CONFIG_MTD_CFI=y
38CONFIG_MTD_CFI_INTELEXT=y 38CONFIG_MTD_CFI_INTELEXT=y
39CONFIG_MTD_CFI_AMDSTD=y 39CONFIG_MTD_CFI_AMDSTD=y
40CONFIG_MTD_ARM_INTEGRATOR=y 40CONFIG_MTD_ARM_INTEGRATOR=y
41CONFIG_ARM_CHARLCD=y
41CONFIG_NETDEVICES=y 42CONFIG_NETDEVICES=y
42CONFIG_SMSC_PHY=y 43CONFIG_SMSC_PHY=y
43CONFIG_NET_ETHERNET=y 44CONFIG_NET_ETHERNET=y
@@ -51,10 +52,13 @@ CONFIG_SERIAL_AMBA_PL011=y
51CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 52CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
52CONFIG_LEGACY_PTY_COUNT=16 53CONFIG_LEGACY_PTY_COUNT=16
53# CONFIG_HW_RANDOM is not set 54# CONFIG_HW_RANDOM is not set
55CONFIG_I2C=y
56CONFIG_I2C_VERSATILE=y
57CONFIG_SPI=y
58CONFIG_GPIOLIB=y
54# CONFIG_HWMON is not set 59# CONFIG_HWMON is not set
55CONFIG_FB=y 60CONFIG_FB=y
56CONFIG_FB_ARMCLCD=y 61CONFIG_FB_ARMCLCD=y
57# CONFIG_VGA_CONSOLE is not set
58CONFIG_FRAMEBUFFER_CONSOLE=y 62CONFIG_FRAMEBUFFER_CONSOLE=y
59CONFIG_LOGO=y 63CONFIG_LOGO=y
60# CONFIG_LOGO_LINUX_MONO is not set 64# CONFIG_LOGO_LINUX_MONO is not set
@@ -69,7 +73,13 @@ CONFIG_SND_ARMAACI=y
69# CONFIG_USB_SUPPORT is not set 73# CONFIG_USB_SUPPORT is not set
70CONFIG_MMC=y 74CONFIG_MMC=y
71CONFIG_MMC_ARMMMCI=y 75CONFIG_MMC_ARMMMCI=y
72CONFIG_INOTIFY=y 76CONFIG_NEW_LEDS=y
77CONFIG_LEDS_CLASS=y
78CONFIG_LEDS_TRIGGERS=y
79CONFIG_LEDS_TRIGGER_HEARTBEAT=y
80CONFIG_RTC_CLASS=y
81CONFIG_RTC_DRV_DS1307=y
82CONFIG_RTC_DRV_PL031=y
73CONFIG_VFAT_FS=y 83CONFIG_VFAT_FS=y
74CONFIG_TMPFS=y 84CONFIG_TMPFS=y
75CONFIG_CRAMFS=y 85CONFIG_CRAMFS=y
@@ -79,6 +89,7 @@ CONFIG_ROOT_NFS=y
79CONFIG_NLS_CODEPAGE_437=y 89CONFIG_NLS_CODEPAGE_437=y
80CONFIG_NLS_ISO8859_1=y 90CONFIG_NLS_ISO8859_1=y
81CONFIG_MAGIC_SYSRQ=y 91CONFIG_MAGIC_SYSRQ=y
92CONFIG_DEBUG_FS=y
82CONFIG_DEBUG_KERNEL=y 93CONFIG_DEBUG_KERNEL=y
83# CONFIG_SCHED_DEBUG is not set 94# CONFIG_SCHED_DEBUG is not set
84# CONFIG_RCU_CPU_STALL_DETECTOR is not set 95# CONFIG_RCU_CPU_STALL_DETECTOR is not set
diff --git a/arch/arm/configs/s5p6440_defconfig b/arch/arm/configs/s5p64x0_defconfig
index 0b0266c6d326..2993ecd35145 100644
--- a/arch/arm/configs/s5p6440_defconfig
+++ b/arch/arm/configs/s5p64x0_defconfig
@@ -5,10 +5,11 @@ CONFIG_KALLSYMS_ALL=y
5CONFIG_MODULES=y 5CONFIG_MODULES=y
6CONFIG_MODULE_UNLOAD=y 6CONFIG_MODULE_UNLOAD=y
7# CONFIG_BLK_DEV_BSG is not set 7# CONFIG_BLK_DEV_BSG is not set
8CONFIG_ARCH_S5P6440=y 8CONFIG_ARCH_S5P64X0=y
9CONFIG_S3C_BOOT_ERROR_RESET=y 9CONFIG_S3C_BOOT_ERROR_RESET=y
10CONFIG_S3C_LOWLEVEL_UART_PORT=1 10CONFIG_S3C_LOWLEVEL_UART_PORT=1
11CONFIG_MACH_SMDK6440=y 11CONFIG_MACH_SMDK6440=y
12CONFIG_MACH_SMDK6450=y
12CONFIG_CPU_32v6K=y 13CONFIG_CPU_32v6K=y
13CONFIG_AEABI=y 14CONFIG_AEABI=y
14CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc" 15CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
index 46e5e0747269..c1c252cdca60 100644
--- a/arch/arm/configs/u300_defconfig
+++ b/arch/arm/configs/u300_defconfig
@@ -28,26 +28,9 @@ CONFIG_CPU_IDLE=y
28CONFIG_FPE_NWFPE=y 28CONFIG_FPE_NWFPE=y
29CONFIG_PM=y 29CONFIG_PM=y
30# CONFIG_SUSPEND is not set 30# CONFIG_SUSPEND is not set
31CONFIG_NET=y
32CONFIG_PACKET=y
33CONFIG_UNIX=y
34CONFIG_INET=y
35# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
36# CONFIG_INET_XFRM_MODE_TUNNEL is not set
37# CONFIG_INET_XFRM_MODE_BEET is not set
38# CONFIG_INET_LRO is not set
39# CONFIG_INET_DIAG is not set
40# CONFIG_IPV6 is not set
41# CONFIG_WIRELESS is not set
42CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 31CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
43# CONFIG_PREVENT_FIRMWARE_BUILD is not set 32# CONFIG_PREVENT_FIRMWARE_BUILD is not set
44CONFIG_MTD=y 33# CONFIG_MISC_DEVICES is not set
45CONFIG_MTD_PARTITIONS=y
46CONFIG_MTD_CMDLINE_PARTS=y
47CONFIG_MTD_CHAR=y
48CONFIG_MTD_BLOCK=y
49CONFIG_MTD_NAND=y
50CONFIG_MTD_NAND_ECC_SMC=y
51# CONFIG_INPUT_MOUSEDEV is not set 34# CONFIG_INPUT_MOUSEDEV is not set
52CONFIG_INPUT_EVDEV=y 35CONFIG_INPUT_EVDEV=y
53# CONFIG_KEYBOARD_ATKBD is not set 36# CONFIG_KEYBOARD_ATKBD is not set
@@ -58,7 +41,6 @@ CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
58CONFIG_LEGACY_PTY_COUNT=16 41CONFIG_LEGACY_PTY_COUNT=16
59# CONFIG_HW_RANDOM is not set 42# CONFIG_HW_RANDOM is not set
60CONFIG_I2C=y 43CONFIG_I2C=y
61CONFIG_POWER_SUPPLY=y
62# CONFIG_HWMON is not set 44# CONFIG_HWMON is not set
63CONFIG_WATCHDOG=y 45CONFIG_WATCHDOG=y
64CONFIG_REGULATOR=y 46CONFIG_REGULATOR=y
@@ -66,24 +48,10 @@ CONFIG_FB=y
66CONFIG_BACKLIGHT_LCD_SUPPORT=y 48CONFIG_BACKLIGHT_LCD_SUPPORT=y
67# CONFIG_LCD_CLASS_DEVICE is not set 49# CONFIG_LCD_CLASS_DEVICE is not set
68CONFIG_BACKLIGHT_CLASS_DEVICE=y 50CONFIG_BACKLIGHT_CLASS_DEVICE=y
69# CONFIG_VGA_CONSOLE is not set
70CONFIG_SOUND=y
71CONFIG_SND=y
72# CONFIG_SND_SUPPORT_OLD_API is not set
73# CONFIG_SND_VERBOSE_PROCFS is not set
74# CONFIG_SND_DRIVERS is not set
75# CONFIG_SND_ARM is not set
76# CONFIG_SND_SPI is not set
77CONFIG_SND_SOC=y
78# CONFIG_HID_SUPPORT is not set 51# CONFIG_HID_SUPPORT is not set
79# CONFIG_USB_SUPPORT is not set 52# CONFIG_USB_SUPPORT is not set
80CONFIG_MMC=y 53CONFIG_MMC=y
81CONFIG_MMC_DEBUG=y
82CONFIG_MMC_ARMMMCI=y 54CONFIG_MMC_ARMMMCI=y
83CONFIG_NEW_LEDS=y
84CONFIG_LEDS_CLASS=y
85CONFIG_LEDS_TRIGGERS=y
86CONFIG_LEDS_TRIGGER_BACKLIGHT=y
87CONFIG_RTC_CLASS=y 55CONFIG_RTC_CLASS=y
88# CONFIG_RTC_HCTOSYS is not set 56# CONFIG_RTC_HCTOSYS is not set
89CONFIG_RTC_DRV_COH901331=y 57CONFIG_RTC_DRV_COH901331=y
@@ -93,12 +61,11 @@ CONFIG_COH901318=y
93CONFIG_FUSE_FS=y 61CONFIG_FUSE_FS=y
94CONFIG_VFAT_FS=y 62CONFIG_VFAT_FS=y
95CONFIG_TMPFS=y 63CONFIG_TMPFS=y
96# CONFIG_NETWORK_FILESYSTEMS is not set
97CONFIG_NLS_CODEPAGE_437=y 64CONFIG_NLS_CODEPAGE_437=y
98CONFIG_NLS_ISO8859_1=y 65CONFIG_NLS_ISO8859_1=y
99CONFIG_PRINTK_TIME=y 66CONFIG_PRINTK_TIME=y
67CONFIG_DEBUG_FS=y
100CONFIG_DEBUG_KERNEL=y 68CONFIG_DEBUG_KERNEL=y
101# CONFIG_DETECT_SOFTLOCKUP is not set
102# CONFIG_SCHED_DEBUG is not set 69# CONFIG_SCHED_DEBUG is not set
103CONFIG_TIMER_STATS=y 70CONFIG_TIMER_STATS=y
104# CONFIG_DEBUG_PREEMPT is not set 71# CONFIG_DEBUG_PREEMPT is not set
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 6e8f05c8a1c8..062b58c029ab 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -154,16 +154,39 @@
154 .long 9999b,9001f; \ 154 .long 9999b,9001f; \
155 .popsection 155 .popsection
156 156
157#ifdef CONFIG_SMP
158#define ALT_SMP(instr...) \
1599998: instr
160#define ALT_UP(instr...) \
161 .pushsection ".alt.smp.init", "a" ;\
162 .long 9998b ;\
163 instr ;\
164 .popsection
165#define ALT_UP_B(label) \
166 .equ up_b_offset, label - 9998b ;\
167 .pushsection ".alt.smp.init", "a" ;\
168 .long 9998b ;\
169 b . + up_b_offset ;\
170 .popsection
171#else
172#define ALT_SMP(instr...)
173#define ALT_UP(instr...) instr
174#define ALT_UP_B(label) b label
175#endif
176
157/* 177/*
158 * SMP data memory barrier 178 * SMP data memory barrier
159 */ 179 */
160 .macro smp_dmb 180 .macro smp_dmb
161#ifdef CONFIG_SMP 181#ifdef CONFIG_SMP
162#if __LINUX_ARM_ARCH__ >= 7 182#if __LINUX_ARM_ARCH__ >= 7
163 dmb 183 ALT_SMP(dmb)
164#elif __LINUX_ARM_ARCH__ == 6 184#elif __LINUX_ARM_ARCH__ == 6
165 mcr p15, 0, r0, c7, c10, 5 @ dmb 185 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
186#else
187#error Incompatible SMP platform
166#endif 188#endif
189 ALT_UP(nop)
167#endif 190#endif
168 .endm 191 .endm
169 192
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 4656a24058d2..3acd8fa25e34 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -137,10 +137,10 @@
137#endif 137#endif
138 138
139/* 139/*
140 * This flag is used to indicate that the page pointed to by a pte 140 * This flag is used to indicate that the page pointed to by a pte is clean
141 * is dirty and requires cleaning before returning it to the user. 141 * and does not require cleaning before returning it to the user.
142 */ 142 */
143#define PG_dcache_dirty PG_arch_1 143#define PG_dcache_clean PG_arch_1
144 144
145/* 145/*
146 * MM Cache Management 146 * MM Cache Management
@@ -156,6 +156,12 @@
156 * Please note that the implementation of these, and the required 156 * Please note that the implementation of these, and the required
157 * effects are cache-type (VIVT/VIPT/PIPT) specific. 157 * effects are cache-type (VIVT/VIPT/PIPT) specific.
158 * 158 *
159 * flush_icache_all()
160 *
161 * Unconditionally clean and invalidate the entire icache.
162 * Currently only needed for cache-v6.S and cache-v7.S, see
163 * __flush_icache_all for the generic implementation.
164 *
159 * flush_kern_all() 165 * flush_kern_all()
160 * 166 *
161 * Unconditionally clean and invalidate the entire cache. 167 * Unconditionally clean and invalidate the entire cache.
@@ -206,6 +212,7 @@
206 */ 212 */
207 213
208struct cpu_cache_fns { 214struct cpu_cache_fns {
215 void (*flush_icache_all)(void);
209 void (*flush_kern_all)(void); 216 void (*flush_kern_all)(void);
210 void (*flush_user_all)(void); 217 void (*flush_user_all)(void);
211 void (*flush_user_range)(unsigned long, unsigned long, unsigned int); 218 void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
@@ -227,6 +234,7 @@ struct cpu_cache_fns {
227 234
228extern struct cpu_cache_fns cpu_cache; 235extern struct cpu_cache_fns cpu_cache;
229 236
237#define __cpuc_flush_icache_all cpu_cache.flush_icache_all
230#define __cpuc_flush_kern_all cpu_cache.flush_kern_all 238#define __cpuc_flush_kern_all cpu_cache.flush_kern_all
231#define __cpuc_flush_user_all cpu_cache.flush_user_all 239#define __cpuc_flush_user_all cpu_cache.flush_user_all
232#define __cpuc_flush_user_range cpu_cache.flush_user_range 240#define __cpuc_flush_user_range cpu_cache.flush_user_range
@@ -246,6 +254,7 @@ extern struct cpu_cache_fns cpu_cache;
246 254
247#else 255#else
248 256
257#define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all)
249#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all) 258#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
250#define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all) 259#define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all)
251#define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range) 260#define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
@@ -253,6 +262,7 @@ extern struct cpu_cache_fns cpu_cache;
253#define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range) 262#define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
254#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area) 263#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
255 264
265extern void __cpuc_flush_icache_all(void);
256extern void __cpuc_flush_kern_all(void); 266extern void __cpuc_flush_kern_all(void);
257extern void __cpuc_flush_user_all(void); 267extern void __cpuc_flush_user_all(void);
258extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int); 268extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
@@ -291,6 +301,37 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
291/* 301/*
292 * Convert calls to our calling convention. 302 * Convert calls to our calling convention.
293 */ 303 */
304
305/* Invalidate I-cache */
306#define __flush_icache_all_generic() \
307 asm("mcr p15, 0, %0, c7, c5, 0" \
308 : : "r" (0));
309
310/* Invalidate I-cache inner shareable */
311#define __flush_icache_all_v7_smp() \
312 asm("mcr p15, 0, %0, c7, c1, 0" \
313 : : "r" (0));
314
315/*
316 * Optimized __flush_icache_all for the common cases. Note that UP ARMv7
317 * will fall through to use __flush_icache_all_generic.
318 */
319#if (defined(CONFIG_CPU_V7) && defined(CONFIG_CPU_V6)) || \
320 defined(CONFIG_SMP_ON_UP)
321#define __flush_icache_preferred __cpuc_flush_icache_all
322#elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
323#define __flush_icache_preferred __flush_icache_all_v7_smp
324#elif __LINUX_ARM_ARCH__ == 6 && defined(CONFIG_ARM_ERRATA_411920)
325#define __flush_icache_preferred __cpuc_flush_icache_all
326#else
327#define __flush_icache_preferred __flush_icache_all_generic
328#endif
329
330static inline void __flush_icache_all(void)
331{
332 __flush_icache_preferred();
333}
334
294#define flush_cache_all() __cpuc_flush_kern_all() 335#define flush_cache_all() __cpuc_flush_kern_all()
295 336
296static inline void vivt_flush_cache_mm(struct mm_struct *mm) 337static inline void vivt_flush_cache_mm(struct mm_struct *mm)
@@ -366,21 +407,6 @@ extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr
366#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 407#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
367extern void flush_dcache_page(struct page *); 408extern void flush_dcache_page(struct page *);
368 409
369static inline void __flush_icache_all(void)
370{
371#ifdef CONFIG_ARM_ERRATA_411920
372 extern void v6_icache_inval_all(void);
373 v6_icache_inval_all();
374#elif defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ >= 7
375 asm("mcr p15, 0, %0, c7, c1, 0 @ invalidate I-cache inner shareable\n"
376 :
377 : "r" (0));
378#else
379 asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n"
380 :
381 : "r" (0));
382#endif
383}
384static inline void flush_kernel_vmap_range(void *addr, int size) 410static inline void flush_kernel_vmap_range(void *addr, int size)
385{ 411{
386 if ((cache_is_vivt() || cache_is_vipt_aliasing())) 412 if ((cache_is_vivt() || cache_is_vipt_aliasing()))
@@ -405,9 +431,6 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
405#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE 431#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
406static inline void flush_kernel_dcache_page(struct page *page) 432static inline void flush_kernel_dcache_page(struct page *page)
407{ 433{
408 /* highmem pages are always flushed upon kunmap already */
409 if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page))
410 __cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
411} 434}
412 435
413#define flush_dcache_mmap_lock(mapping) \ 436#define flush_dcache_mmap_lock(mapping) \
diff --git a/arch/arm/include/asm/cachetype.h b/arch/arm/include/asm/cachetype.h
index d3a4c2cb9f2f..c023db09fcc1 100644
--- a/arch/arm/include/asm/cachetype.h
+++ b/arch/arm/include/asm/cachetype.h
@@ -6,6 +6,7 @@
6#define CACHEID_VIPT_ALIASING (1 << 2) 6#define CACHEID_VIPT_ALIASING (1 << 2)
7#define CACHEID_VIPT (CACHEID_VIPT_ALIASING|CACHEID_VIPT_NONALIASING) 7#define CACHEID_VIPT (CACHEID_VIPT_ALIASING|CACHEID_VIPT_NONALIASING)
8#define CACHEID_ASID_TAGGED (1 << 3) 8#define CACHEID_ASID_TAGGED (1 << 3)
9#define CACHEID_VIPT_I_ALIASING (1 << 4)
9 10
10extern unsigned int cacheid; 11extern unsigned int cacheid;
11 12
@@ -14,15 +15,18 @@ extern unsigned int cacheid;
14#define cache_is_vipt_nonaliasing() cacheid_is(CACHEID_VIPT_NONALIASING) 15#define cache_is_vipt_nonaliasing() cacheid_is(CACHEID_VIPT_NONALIASING)
15#define cache_is_vipt_aliasing() cacheid_is(CACHEID_VIPT_ALIASING) 16#define cache_is_vipt_aliasing() cacheid_is(CACHEID_VIPT_ALIASING)
16#define icache_is_vivt_asid_tagged() cacheid_is(CACHEID_ASID_TAGGED) 17#define icache_is_vivt_asid_tagged() cacheid_is(CACHEID_ASID_TAGGED)
18#define icache_is_vipt_aliasing() cacheid_is(CACHEID_VIPT_I_ALIASING)
17 19
18/* 20/*
19 * __LINUX_ARM_ARCH__ is the minimum supported CPU architecture 21 * __LINUX_ARM_ARCH__ is the minimum supported CPU architecture
20 * Mask out support which will never be present on newer CPUs. 22 * Mask out support which will never be present on newer CPUs.
21 * - v6+ is never VIVT 23 * - v6+ is never VIVT
22 * - v7+ VIPT never aliases 24 * - v7+ VIPT never aliases on D-side
23 */ 25 */
24#if __LINUX_ARM_ARCH__ >= 7 26#if __LINUX_ARM_ARCH__ >= 7
25#define __CACHEID_ARCH_MIN (CACHEID_VIPT_NONALIASING | CACHEID_ASID_TAGGED) 27#define __CACHEID_ARCH_MIN (CACHEID_VIPT_NONALIASING |\
28 CACHEID_ASID_TAGGED |\
29 CACHEID_VIPT_I_ALIASING)
26#elif __LINUX_ARM_ARCH__ >= 6 30#elif __LINUX_ARM_ARCH__ >= 6
27#define __CACHEID_ARCH_MIN (~CACHEID_VIVT) 31#define __CACHEID_ARCH_MIN (~CACHEID_VIVT)
28#else 32#else
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 5747a8baa413..8bb66bca2e3e 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -127,4 +127,8 @@ struct mm_struct;
127extern unsigned long arch_randomize_brk(struct mm_struct *mm); 127extern unsigned long arch_randomize_brk(struct mm_struct *mm);
128#define arch_randomize_brk arch_randomize_brk 128#define arch_randomize_brk arch_randomize_brk
129 129
130extern int vectors_user_mapping(void);
131#define arch_setup_additional_pages(bprm, uses_interp) vectors_user_mapping()
132#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
133
130#endif 134#endif
diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h
index 103f7ee97313..f89515adac60 100644
--- a/arch/arm/include/asm/ftrace.h
+++ b/arch/arm/include/asm/ftrace.h
@@ -2,12 +2,30 @@
2#define _ASM_ARM_FTRACE 2#define _ASM_ARM_FTRACE
3 3
4#ifdef CONFIG_FUNCTION_TRACER 4#ifdef CONFIG_FUNCTION_TRACER
5#define MCOUNT_ADDR ((long)(mcount)) 5#define MCOUNT_ADDR ((unsigned long)(__gnu_mcount_nc))
6#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */ 6#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
7 7
8#ifndef __ASSEMBLY__ 8#ifndef __ASSEMBLY__
9extern void mcount(void); 9extern void mcount(void);
10extern void __gnu_mcount_nc(void); 10extern void __gnu_mcount_nc(void);
11
12#ifdef CONFIG_DYNAMIC_FTRACE
13struct dyn_arch_ftrace {
14#ifdef CONFIG_OLD_MCOUNT
15 bool old_mcount;
16#endif
17};
18
19static inline unsigned long ftrace_call_adjust(unsigned long addr)
20{
21 /* With Thumb-2, the recorded addresses have the lsb set */
22 return addr & ~1;
23}
24
25extern void ftrace_caller_old(void);
26extern void ftrace_call_old(void);
27#endif
28
11#endif 29#endif
12 30
13#endif 31#endif
diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h
index 212e47828c79..7ecd793b8f5a 100644
--- a/arch/arm/include/asm/hardware/coresight.h
+++ b/arch/arm/include/asm/hardware/coresight.h
@@ -21,18 +21,6 @@
21#define TRACER_RUNNING BIT(TRACER_RUNNING_BIT) 21#define TRACER_RUNNING BIT(TRACER_RUNNING_BIT)
22#define TRACER_CYCLE_ACC BIT(TRACER_CYCLE_ACC_BIT) 22#define TRACER_CYCLE_ACC BIT(TRACER_CYCLE_ACC_BIT)
23 23
24struct tracectx {
25 unsigned int etb_bufsz;
26 void __iomem *etb_regs;
27 void __iomem *etm_regs;
28 unsigned long flags;
29 int ncmppairs;
30 int etm_portsz;
31 struct device *dev;
32 struct clk *emu_clk;
33 struct mutex mutex;
34};
35
36#define TRACER_TIMEOUT 10000 24#define TRACER_TIMEOUT 10000
37 25
38#define etm_writel(t, v, x) \ 26#define etm_writel(t, v, x) \
@@ -112,10 +100,10 @@ struct tracectx {
112 100
113/* ETM status register, "ETM Architecture", 3.3.2 */ 101/* ETM status register, "ETM Architecture", 3.3.2 */
114#define ETMR_STATUS (0x10) 102#define ETMR_STATUS (0x10)
115#define ETMST_OVERFLOW (1 << 0) 103#define ETMST_OVERFLOW BIT(0)
116#define ETMST_PROGBIT (1 << 1) 104#define ETMST_PROGBIT BIT(1)
117#define ETMST_STARTSTOP (1 << 2) 105#define ETMST_STARTSTOP BIT(2)
118#define ETMST_TRIGGER (1 << 3) 106#define ETMST_TRIGGER BIT(3)
119 107
120#define etm_progbit(t) (etm_readl((t), ETMR_STATUS) & ETMST_PROGBIT) 108#define etm_progbit(t) (etm_readl((t), ETMR_STATUS) & ETMST_PROGBIT)
121#define etm_started(t) (etm_readl((t), ETMR_STATUS) & ETMST_STARTSTOP) 109#define etm_started(t) (etm_readl((t), ETMR_STATUS) & ETMST_STARTSTOP)
@@ -123,7 +111,7 @@ struct tracectx {
123 111
124#define ETMR_TRACEENCTRL2 0x1c 112#define ETMR_TRACEENCTRL2 0x1c
125#define ETMR_TRACEENCTRL 0x24 113#define ETMR_TRACEENCTRL 0x24
126#define ETMTE_INCLEXCL (1 << 24) 114#define ETMTE_INCLEXCL BIT(24)
127#define ETMR_TRACEENEVT 0x20 115#define ETMR_TRACEENEVT 0x20
128#define ETMCTRL_OPTS (ETMCTRL_DO_CPRT | \ 116#define ETMCTRL_OPTS (ETMCTRL_DO_CPRT | \
129 ETMCTRL_DATA_DO_ADDR | \ 117 ETMCTRL_DATA_DO_ADDR | \
@@ -146,12 +134,12 @@ struct tracectx {
146#define ETBR_CTRL 0x20 134#define ETBR_CTRL 0x20
147#define ETBR_FORMATTERCTRL 0x304 135#define ETBR_FORMATTERCTRL 0x304
148#define ETBFF_ENFTC 1 136#define ETBFF_ENFTC 1
149#define ETBFF_ENFCONT (1 << 1) 137#define ETBFF_ENFCONT BIT(1)
150#define ETBFF_FONFLIN (1 << 4) 138#define ETBFF_FONFLIN BIT(4)
151#define ETBFF_MANUAL_FLUSH (1 << 6) 139#define ETBFF_MANUAL_FLUSH BIT(6)
152#define ETBFF_TRIGIN (1 << 8) 140#define ETBFF_TRIGIN BIT(8)
153#define ETBFF_TRIGEVT (1 << 9) 141#define ETBFF_TRIGEVT BIT(9)
154#define ETBFF_TRIGFL (1 << 10) 142#define ETBFF_TRIGFL BIT(10)
155 143
156#define etb_writel(t, v, x) \ 144#define etb_writel(t, v, x) \
157 (__raw_writel((v), (t)->etb_regs + (x))) 145 (__raw_writel((v), (t)->etb_regs + (x)))
diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h
new file mode 100644
index 000000000000..4d8ae9d67abe
--- /dev/null
+++ b/arch/arm/include/asm/hw_breakpoint.h
@@ -0,0 +1,133 @@
1#ifndef _ARM_HW_BREAKPOINT_H
2#define _ARM_HW_BREAKPOINT_H
3
4#ifdef __KERNEL__
5
6struct task_struct;
7
8#ifdef CONFIG_HAVE_HW_BREAKPOINT
9
10struct arch_hw_breakpoint_ctrl {
11 u32 __reserved : 9,
12 mismatch : 1,
13 : 9,
14 len : 8,
15 type : 2,
16 privilege : 2,
17 enabled : 1;
18};
19
20struct arch_hw_breakpoint {
21 u32 address;
22 u32 trigger;
23 struct perf_event *suspended_wp;
24 struct arch_hw_breakpoint_ctrl ctrl;
25};
26
27static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
28{
29 return (ctrl.mismatch << 22) | (ctrl.len << 5) | (ctrl.type << 3) |
30 (ctrl.privilege << 1) | ctrl.enabled;
31}
32
33static inline void decode_ctrl_reg(u32 reg,
34 struct arch_hw_breakpoint_ctrl *ctrl)
35{
36 ctrl->enabled = reg & 0x1;
37 reg >>= 1;
38 ctrl->privilege = reg & 0x3;
39 reg >>= 2;
40 ctrl->type = reg & 0x3;
41 reg >>= 2;
42 ctrl->len = reg & 0xff;
43 reg >>= 17;
44 ctrl->mismatch = reg & 0x1;
45}
46
47/* Debug architecture numbers. */
48#define ARM_DEBUG_ARCH_RESERVED 0 /* In case of ptrace ABI updates. */
49#define ARM_DEBUG_ARCH_V6 1
50#define ARM_DEBUG_ARCH_V6_1 2
51#define ARM_DEBUG_ARCH_V7_ECP14 3
52#define ARM_DEBUG_ARCH_V7_MM 4
53
54/* Breakpoint */
55#define ARM_BREAKPOINT_EXECUTE 0
56
57/* Watchpoints */
58#define ARM_BREAKPOINT_LOAD 1
59#define ARM_BREAKPOINT_STORE 2
60
61/* Privilege Levels */
62#define ARM_BREAKPOINT_PRIV 1
63#define ARM_BREAKPOINT_USER 2
64
65/* Lengths */
66#define ARM_BREAKPOINT_LEN_1 0x1
67#define ARM_BREAKPOINT_LEN_2 0x3
68#define ARM_BREAKPOINT_LEN_4 0xf
69#define ARM_BREAKPOINT_LEN_8 0xff
70
71/* Limits */
72#define ARM_MAX_BRP 16
73#define ARM_MAX_WRP 16
74#define ARM_MAX_HBP_SLOTS (ARM_MAX_BRP + ARM_MAX_WRP)
75
76/* DSCR method of entry bits. */
77#define ARM_DSCR_MOE(x) ((x >> 2) & 0xf)
78#define ARM_ENTRY_BREAKPOINT 0x1
79#define ARM_ENTRY_ASYNC_WATCHPOINT 0x2
80#define ARM_ENTRY_SYNC_WATCHPOINT 0xa
81
82/* DSCR monitor/halting bits. */
83#define ARM_DSCR_HDBGEN (1 << 14)
84#define ARM_DSCR_MDBGEN (1 << 15)
85
86/* opcode2 numbers for the co-processor instructions. */
87#define ARM_OP2_BVR 4
88#define ARM_OP2_BCR 5
89#define ARM_OP2_WVR 6
90#define ARM_OP2_WCR 7
91
92/* Base register numbers for the debug registers. */
93#define ARM_BASE_BVR 64
94#define ARM_BASE_BCR 80
95#define ARM_BASE_WVR 96
96#define ARM_BASE_WCR 112
97
98/* Accessor macros for the debug registers. */
99#define ARM_DBG_READ(M, OP2, VAL) do {\
100 asm volatile("mrc p14, 0, %0, c0," #M ", " #OP2 : "=r" (VAL));\
101} while (0)
102
103#define ARM_DBG_WRITE(M, OP2, VAL) do {\
104 asm volatile("mcr p14, 0, %0, c0," #M ", " #OP2 : : "r" (VAL));\
105} while (0)
106
107struct notifier_block;
108struct perf_event;
109struct pmu;
110
111extern struct pmu perf_ops_bp;
112extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
113 int *gen_len, int *gen_type);
114extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
115extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
116extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
117 unsigned long val, void *data);
118
119extern u8 arch_get_debug_arch(void);
120extern u8 arch_get_max_wp_len(void);
121extern void clear_ptrace_hw_breakpoint(struct task_struct *tsk);
122
123int arch_install_hw_breakpoint(struct perf_event *bp);
124void arch_uninstall_hw_breakpoint(struct perf_event *bp);
125void hw_breakpoint_pmu_read(struct perf_event *bp);
126int hw_breakpoint_slots(int type);
127
128#else
129static inline void clear_ptrace_hw_breakpoint(struct task_struct *tsk) {}
130
131#endif /* CONFIG_HAVE_HW_BREAKPOINT */
132#endif /* __KERNEL__ */
133#endif /* _ARM_HW_BREAKPOINT_H */
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 1261b1f928d9..815efa2d4e07 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -294,6 +294,7 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
294#define ARCH_HAS_VALID_PHYS_ADDR_RANGE 294#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
295extern int valid_phys_addr_range(unsigned long addr, size_t size); 295extern int valid_phys_addr_range(unsigned long addr, size_t size);
296extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); 296extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
297extern int devmem_is_allowed(unsigned long pfn);
297#endif 298#endif
298 299
299/* 300/*
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 8a0dd18ba642..d97a964207fa 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -16,18 +16,15 @@ struct sys_timer;
16 16
17struct machine_desc { 17struct machine_desc {
18 /* 18 /*
19 * Note! The first four elements are used 19 * Note! The first two elements are used
20 * by assembler code in head.S, head-common.S 20 * by assembler code in head.S, head-common.S
21 */ 21 */
22 unsigned int nr; /* architecture number */ 22 unsigned int nr; /* architecture number */
23 unsigned int nr_irqs; /* number of IRQs */
24 unsigned int phys_io; /* start of physical io */
25 unsigned int io_pg_offst; /* byte offset for io
26 * page tabe entry */
27
28 const char *name; /* architecture name */ 23 const char *name; /* architecture name */
29 unsigned long boot_params; /* tagged list */ 24 unsigned long boot_params; /* tagged list */
30 25
26 unsigned int nr_irqs; /* number of IRQs */
27
31 unsigned int video_start; /* start of video RAM */ 28 unsigned int video_start; /* start of video RAM */
32 unsigned int video_end; /* end of video RAM */ 29 unsigned int video_end; /* end of video RAM */
33 30
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index a0b3cac0547c..71605d9f8e42 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -18,7 +18,6 @@
18#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
19#include <asm/cachetype.h> 19#include <asm/cachetype.h>
20#include <asm/proc-fns.h> 20#include <asm/proc-fns.h>
21#include <asm-generic/mm_hooks.h>
22 21
23void __check_kvm_seq(struct mm_struct *mm); 22void __check_kvm_seq(struct mm_struct *mm);
24 23
@@ -134,4 +133,32 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
134#define deactivate_mm(tsk,mm) do { } while (0) 133#define deactivate_mm(tsk,mm) do { } while (0)
135#define activate_mm(prev,next) switch_mm(prev, next, NULL) 134#define activate_mm(prev,next) switch_mm(prev, next, NULL)
136 135
136/*
137 * We are inserting a "fake" vma for the user-accessible vector page so
138 * gdb and friends can get to it through ptrace and /proc/<pid>/mem.
139 * But we also want to remove it before the generic code gets to see it
140 * during process exit or the unmapping of it would cause total havoc.
141 * (the macro is used as remove_vma() is static to mm/mmap.c)
142 */
143#define arch_exit_mmap(mm) \
144do { \
145 struct vm_area_struct *high_vma = find_vma(mm, 0xffff0000); \
146 if (high_vma) { \
147 BUG_ON(high_vma->vm_next); /* it should be last */ \
148 if (high_vma->vm_prev) \
149 high_vma->vm_prev->vm_next = NULL; \
150 else \
151 mm->mmap = NULL; \
152 rb_erase(&high_vma->vm_rb, &mm->mm_rb); \
153 mm->mmap_cache = NULL; \
154 mm->map_count--; \
155 remove_vma(high_vma); \
156 } \
157} while (0)
158
159static inline void arch_dup_mmap(struct mm_struct *oldmm,
160 struct mm_struct *mm)
161{
162}
163
137#endif 164#endif
diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h
index e4dfa69abb68..cbb0bc295d2b 100644
--- a/arch/arm/include/asm/module.h
+++ b/arch/arm/include/asm/module.h
@@ -7,20 +7,27 @@
7 7
8struct unwind_table; 8struct unwind_table;
9 9
10struct mod_arch_specific
11{
12#ifdef CONFIG_ARM_UNWIND 10#ifdef CONFIG_ARM_UNWIND
13 Elf_Shdr *unw_sec_init; 11struct arm_unwind_mapping {
14 Elf_Shdr *unw_sec_devinit; 12 Elf_Shdr *unw_sec;
15 Elf_Shdr *unw_sec_core; 13 Elf_Shdr *sec_text;
16 Elf_Shdr *sec_init_text; 14 struct unwind_table *unwind;
17 Elf_Shdr *sec_devinit_text; 15};
18 Elf_Shdr *sec_core_text; 16enum {
19 struct unwind_table *unwind_init; 17 ARM_SEC_INIT,
20 struct unwind_table *unwind_devinit; 18 ARM_SEC_DEVINIT,
21 struct unwind_table *unwind_core; 19 ARM_SEC_CORE,
22#endif 20 ARM_SEC_EXIT,
21 ARM_SEC_DEVEXIT,
22 ARM_SEC_MAX,
23};
24struct mod_arch_specific {
25 struct arm_unwind_mapping map[ARM_SEC_MAX];
23}; 26};
27#else
28struct mod_arch_specific {
29};
30#endif
24 31
25/* 32/*
26 * Include the ARM architecture version. 33 * Include the ARM architecture version.
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index e90b167ea848..a9672e8406a3 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -278,9 +278,24 @@ extern struct page *empty_zero_page;
278 278
279#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext) 279#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
280 280
281#define set_pte_at(mm,addr,ptep,pteval) do { \ 281#if __LINUX_ARM_ARCH__ < 6
282 set_pte_ext(ptep, pteval, (addr) >= TASK_SIZE ? 0 : PTE_EXT_NG); \ 282static inline void __sync_icache_dcache(pte_t pteval)
283 } while (0) 283{
284}
285#else
286extern void __sync_icache_dcache(pte_t pteval);
287#endif
288
289static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
290 pte_t *ptep, pte_t pteval)
291{
292 if (addr >= TASK_SIZE)
293 set_pte_ext(ptep, pteval, 0);
294 else {
295 __sync_icache_dcache(pteval);
296 set_pte_ext(ptep, pteval, PTE_EXT_NG);
297 }
298}
284 299
285/* 300/*
286 * The following only work if pte_present() is true. 301 * The following only work if pte_present() is true.
@@ -290,8 +305,13 @@ extern struct page *empty_zero_page;
290#define pte_write(pte) (pte_val(pte) & L_PTE_WRITE) 305#define pte_write(pte) (pte_val(pte) & L_PTE_WRITE)
291#define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY) 306#define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY)
292#define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG) 307#define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG)
308#define pte_exec(pte) (pte_val(pte) & L_PTE_EXEC)
293#define pte_special(pte) (0) 309#define pte_special(pte) (0)
294 310
311#define pte_present_user(pte) \
312 ((pte_val(pte) & (L_PTE_PRESENT | L_PTE_USER)) == \
313 (L_PTE_PRESENT | L_PTE_USER))
314
295#define PTE_BIT_FUNC(fn,op) \ 315#define PTE_BIT_FUNC(fn,op) \
296static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; } 316static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
297 317
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 7bed3daf83b8..67357baaeeeb 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -19,6 +19,7 @@
19 19
20#ifdef __KERNEL__ 20#ifdef __KERNEL__
21 21
22#include <asm/hw_breakpoint.h>
22#include <asm/ptrace.h> 23#include <asm/ptrace.h>
23#include <asm/types.h> 24#include <asm/types.h>
24 25
@@ -41,6 +42,9 @@ struct debug_entry {
41struct debug_info { 42struct debug_info {
42 int nsaved; 43 int nsaved;
43 struct debug_entry bp[2]; 44 struct debug_entry bp[2];
45#ifdef CONFIG_HAVE_HW_BREAKPOINT
46 struct perf_event *hbp[ARM_MAX_HBP_SLOTS];
47#endif
44}; 48};
45 49
46struct thread_struct { 50struct thread_struct {
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 7ce15eb15f72..783d50f32618 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -29,6 +29,8 @@
29#define PTRACE_SETCRUNCHREGS 26 29#define PTRACE_SETCRUNCHREGS 26
30#define PTRACE_GETVFPREGS 27 30#define PTRACE_GETVFPREGS 27
31#define PTRACE_SETVFPREGS 28 31#define PTRACE_SETVFPREGS 28
32#define PTRACE_GETHBPREGS 29
33#define PTRACE_SETHBPREGS 30
32 34
33/* 35/*
34 * PSR bits 36 * PSR bits
diff --git a/arch/arm/include/asm/seccomp.h b/arch/arm/include/asm/seccomp.h
new file mode 100644
index 000000000000..52b156b341f5
--- /dev/null
+++ b/arch/arm/include/asm/seccomp.h
@@ -0,0 +1,11 @@
1#ifndef _ASM_ARM_SECCOMP_H
2#define _ASM_ARM_SECCOMP_H
3
4#include <linux/unistd.h>
5
6#define __NR_seccomp_read __NR_read
7#define __NR_seccomp_write __NR_write
8#define __NR_seccomp_exit __NR_exit
9#define __NR_seccomp_sigreturn __NR_rt_sigreturn
10
11#endif /* _ASM_ARM_SECCOMP_H */
diff --git a/arch/arm/include/asm/smp_mpidr.h b/arch/arm/include/asm/smp_mpidr.h
new file mode 100644
index 000000000000..6a9307d64900
--- /dev/null
+++ b/arch/arm/include/asm/smp_mpidr.h
@@ -0,0 +1,17 @@
1#ifndef ASMARM_SMP_MIDR_H
2#define ASMARM_SMP_MIDR_H
3
4#define hard_smp_processor_id() \
5 ({ \
6 unsigned int cpunum; \
7 __asm__("\n" \
8 "1: mrc p15, 0, %0, c0, c0, 5\n" \
9 " .pushsection \".alt.smp.init\", \"a\"\n"\
10 " .long 1b\n" \
11 " mov %0, #0\n" \
12 " .popsection" \
13 : "=r" (cpunum)); \
14 cpunum &= 0x0F; \
15 })
16
17#endif
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index e6215305544a..f24c1b9e211d 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -7,15 +7,40 @@
7 7
8#include <asm/cputype.h> 8#include <asm/cputype.h>
9 9
10/*
11 * Return true if we are running on a SMP platform
12 */
13static inline bool is_smp(void)
14{
15#ifndef CONFIG_SMP
16 return false;
17#elif defined(CONFIG_SMP_ON_UP)
18 extern unsigned int smp_on_up;
19 return !!smp_on_up;
20#else
21 return true;
22#endif
23}
24
10/* all SMP configurations have the extended CPUID registers */ 25/* all SMP configurations have the extended CPUID registers */
11static inline int tlb_ops_need_broadcast(void) 26static inline int tlb_ops_need_broadcast(void)
12{ 27{
28 if (!is_smp())
29 return 0;
30
13 return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2; 31 return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
14} 32}
15 33
34#if !defined(CONFIG_SMP) || __LINUX_ARM_ARCH__ >= 7
35#define cache_ops_need_broadcast() 0
36#else
16static inline int cache_ops_need_broadcast(void) 37static inline int cache_ops_need_broadcast(void)
17{ 38{
39 if (!is_smp())
40 return 0;
41
18 return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1; 42 return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
19} 43}
44#endif
20 45
21#endif 46#endif
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 8ba1ccf82a02..1120f18a6b17 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -85,6 +85,10 @@ void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
85 struct pt_regs *), 85 struct pt_regs *),
86 int sig, int code, const char *name); 86 int sig, int code, const char *name);
87 87
88void hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int,
89 struct pt_regs *),
90 int sig, int code, const char *name);
91
88#define xchg(ptr,x) \ 92#define xchg(ptr,x) \
89 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) 93 ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
90 94
@@ -325,6 +329,8 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
325extern void disable_hlt(void); 329extern void disable_hlt(void);
326extern void enable_hlt(void); 330extern void enable_hlt(void);
327 331
332void cpu_idle_wait(void);
333
328#include <asm-generic/cmpxchg-local.h> 334#include <asm-generic/cmpxchg-local.h>
329 335
330#if __LINUX_ARM_ARCH__ < 6 336#if __LINUX_ARM_ARCH__ < 6
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 763e29fa8530..7b5cc8dae06e 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -144,6 +144,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
144#define TIF_MEMDIE 18 /* is terminating due to OOM killer */ 144#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
145#define TIF_FREEZE 19 145#define TIF_FREEZE 19
146#define TIF_RESTORE_SIGMASK 20 146#define TIF_RESTORE_SIGMASK 20
147#define TIF_SECCOMP 21
147 148
148#define _TIF_SIGPENDING (1 << TIF_SIGPENDING) 149#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
149#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) 150#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
@@ -153,6 +154,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
153#define _TIF_USING_IWMMXT (1 << TIF_USING_IWMMXT) 154#define _TIF_USING_IWMMXT (1 << TIF_USING_IWMMXT)
154#define _TIF_FREEZE (1 << TIF_FREEZE) 155#define _TIF_FREEZE (1 << TIF_FREEZE)
155#define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK) 156#define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK)
157#define _TIF_SECCOMP (1 << TIF_SECCOMP)
156 158
157/* 159/*
158 * Change these and you break ASM code in entry-common.S 160 * Change these and you break ASM code in entry-common.S
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 33b546ae72d4..ce7378ea15a2 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -70,6 +70,10 @@
70#undef _TLB 70#undef _TLB
71#undef MULTI_TLB 71#undef MULTI_TLB
72 72
73#ifdef CONFIG_SMP_ON_UP
74#define MULTI_TLB 1
75#endif
76
73#define v3_tlb_flags (TLB_V3_FULL | TLB_V3_PAGE) 77#define v3_tlb_flags (TLB_V3_FULL | TLB_V3_PAGE)
74 78
75#ifdef CONFIG_CPU_TLB_V3 79#ifdef CONFIG_CPU_TLB_V3
@@ -185,17 +189,23 @@
185# define v6wbi_always_flags (-1UL) 189# define v6wbi_always_flags (-1UL)
186#endif 190#endif
187 191
188#ifdef CONFIG_SMP 192#define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
189#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_V7_IS_BTB | \
190 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID) 193 TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | TLB_V7_UIS_ASID)
191#else 194#define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BTB | \
192#define v7wbi_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_BTB | \
193 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID) 195 TLB_V6_U_FULL | TLB_V6_U_PAGE | TLB_V6_U_ASID)
194#endif
195 196
196#ifdef CONFIG_CPU_TLB_V7 197#ifdef CONFIG_CPU_TLB_V7
197# define v7wbi_possible_flags v7wbi_tlb_flags 198
198# define v7wbi_always_flags v7wbi_tlb_flags 199# ifdef CONFIG_SMP_ON_UP
200# define v7wbi_possible_flags (v7wbi_tlb_flags_smp | v7wbi_tlb_flags_up)
201# define v7wbi_always_flags (v7wbi_tlb_flags_smp & v7wbi_tlb_flags_up)
202# elif defined(CONFIG_SMP)
203# define v7wbi_possible_flags v7wbi_tlb_flags_smp
204# define v7wbi_always_flags v7wbi_tlb_flags_smp
205# else
206# define v7wbi_possible_flags v7wbi_tlb_flags_up
207# define v7wbi_always_flags v7wbi_tlb_flags_up
208# endif
199# ifdef _TLB 209# ifdef _TLB
200# define MULTI_TLB 1 210# define MULTI_TLB 1
201# else 211# else
@@ -560,12 +570,20 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
560#endif 570#endif
561 571
562/* 572/*
563 * if PG_dcache_dirty is set for the page, we need to ensure that any 573 * If PG_dcache_clean is not set for the page, we need to ensure that any
564 * cache entries for the kernels virtual memory range are written 574 * cache entries for the kernels virtual memory range are written
565 * back to the page. 575 * back to the page. On ARMv6 and later, the cache coherency is handled via
576 * the set_pte_at() function.
566 */ 577 */
578#if __LINUX_ARM_ARCH__ < 6
567extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, 579extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
568 pte_t *ptep); 580 pte_t *ptep);
581#else
582static inline void update_mmu_cache(struct vm_area_struct *vma,
583 unsigned long addr, pte_t *ptep)
584{
585}
586#endif
569 587
570#endif 588#endif
571 589
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 980b78e31328..5b9b268f4fbb 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_KGDB) += kgdb.o
42obj-$(CONFIG_ARM_UNWIND) += unwind.o 42obj-$(CONFIG_ARM_UNWIND) += unwind.o
43obj-$(CONFIG_HAVE_TCM) += tcm.o 43obj-$(CONFIG_HAVE_TCM) += tcm.o
44obj-$(CONFIG_CRASH_DUMP) += crash_dump.o 44obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
45obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
45 46
46obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o 47obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o
47AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 48AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index 8214bfebfaca..e5e1e5387678 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -165,6 +165,8 @@ EXPORT_SYMBOL(_find_next_bit_be);
165#endif 165#endif
166 166
167#ifdef CONFIG_FUNCTION_TRACER 167#ifdef CONFIG_FUNCTION_TRACER
168#ifdef CONFIG_OLD_MCOUNT
168EXPORT_SYMBOL(mcount); 169EXPORT_SYMBOL(mcount);
170#endif
169EXPORT_SYMBOL(__gnu_mcount_nc); 171EXPORT_SYMBOL(__gnu_mcount_nc);
170#endif 172#endif
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 85f2a019f77b..82da66172132 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -102,8 +102,6 @@ int main(void)
102 DEFINE(SIZEOF_MACHINE_DESC, sizeof(struct machine_desc)); 102 DEFINE(SIZEOF_MACHINE_DESC, sizeof(struct machine_desc));
103 DEFINE(MACHINFO_TYPE, offsetof(struct machine_desc, nr)); 103 DEFINE(MACHINFO_TYPE, offsetof(struct machine_desc, nr));
104 DEFINE(MACHINFO_NAME, offsetof(struct machine_desc, name)); 104 DEFINE(MACHINFO_NAME, offsetof(struct machine_desc, name));
105 DEFINE(MACHINFO_PHYSIO, offsetof(struct machine_desc, phys_io));
106 DEFINE(MACHINFO_PGOFFIO, offsetof(struct machine_desc, io_pg_offst));
107 BLANK(); 105 BLANK();
108 DEFINE(PROC_INFO_SZ, sizeof(struct proc_info_list)); 106 DEFINE(PROC_INFO_SZ, sizeof(struct proc_info_list));
109 DEFINE(PROCINFO_INITFUNC, offsetof(struct proc_info_list, __cpu_flush)); 107 DEFINE(PROCINFO_INITFUNC, offsetof(struct proc_info_list, __cpu_flush));
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index a38b4879441d..a0f07521ca8a 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -22,11 +22,11 @@
22#if defined(CONFIG_DEBUG_ICEDCC) 22#if defined(CONFIG_DEBUG_ICEDCC)
23 @@ debug using ARM EmbeddedICE DCC channel 23 @@ debug using ARM EmbeddedICE DCC channel
24 24
25#if defined(CONFIG_CPU_V6) 25 .macro addruart, rp, rv
26
27 .macro addruart, rx, tmp
28 .endm 26 .endm
29 27
28#if defined(CONFIG_CPU_V6)
29
30 .macro senduart, rd, rx 30 .macro senduart, rd, rx
31 mcr p14, 0, \rd, c0, c5, 0 31 mcr p14, 0, \rd, c0, c5, 0
32 .endm 32 .endm
@@ -51,9 +51,6 @@
51 51
52#elif defined(CONFIG_CPU_V7) 52#elif defined(CONFIG_CPU_V7)
53 53
54 .macro addruart, rx, tmp
55 .endm
56
57 .macro senduart, rd, rx 54 .macro senduart, rd, rx
58 mcr p14, 0, \rd, c0, c5, 0 55 mcr p14, 0, \rd, c0, c5, 0
59 .endm 56 .endm
@@ -71,9 +68,6 @@ wait: mrc p14, 0, pc, c0, c1, 0
71 68
72#elif defined(CONFIG_CPU_XSCALE) 69#elif defined(CONFIG_CPU_XSCALE)
73 70
74 .macro addruart, rx, tmp
75 .endm
76
77 .macro senduart, rd, rx 71 .macro senduart, rd, rx
78 mcr p14, 0, \rd, c8, c0, 0 72 mcr p14, 0, \rd, c8, c0, 0
79 .endm 73 .endm
@@ -98,9 +92,6 @@ wait: mrc p14, 0, pc, c0, c1, 0
98 92
99#else 93#else
100 94
101 .macro addruart, rx, tmp
102 .endm
103
104 .macro senduart, rd, rx 95 .macro senduart, rd, rx
105 mcr p14, 0, \rd, c1, c0, 0 96 mcr p14, 0, \rd, c1, c0, 0
106 .endm 97 .endm
@@ -130,6 +121,22 @@ wait: mrc p14, 0, pc, c0, c1, 0
130#include <mach/debug-macro.S> 121#include <mach/debug-macro.S>
131#endif /* CONFIG_DEBUG_ICEDCC */ 122#endif /* CONFIG_DEBUG_ICEDCC */
132 123
124#ifdef CONFIG_MMU
125 .macro addruart_current, rx, tmp1, tmp2
126 addruart \tmp1, \tmp2
127 mrc p15, 0, \rx, c1, c0
128 tst \rx, #1
129 moveq \rx, \tmp1
130 movne \rx, \tmp2
131 .endm
132
133#else /* !CONFIG_MMU */
134 .macro addruart_current, rx, tmp1, tmp2
135 addruart \rx, \tmp1
136 .endm
137
138#endif /* CONFIG_MMU */
139
133/* 140/*
134 * Useful debugging routines 141 * Useful debugging routines
135 */ 142 */
@@ -164,7 +171,7 @@ ENDPROC(printhex2)
164 .ltorg 171 .ltorg
165 172
166ENTRY(printascii) 173ENTRY(printascii)
167 addruart r3, r1 174 addruart_current r3, r1, r2
168 b 2f 175 b 2f
1691: waituart r2, r3 1761: waituart r2, r3
170 senduart r1, r3 177 senduart r1, r3
@@ -180,7 +187,7 @@ ENTRY(printascii)
180ENDPROC(printascii) 187ENDPROC(printascii)
181 188
182ENTRY(printch) 189ENTRY(printch)
183 addruart r3, r1 190 addruart_current r3, r1, r2
184 mov r1, r0 191 mov r1, r0
185 mov r0, #0 192 mov r0, #0
186 b 1b 193 b 1b
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bb8e93a76407..c09e3573c5de 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -46,7 +46,8 @@
46 * this macro assumes that irqstat (r6) and base (r5) are 46 * this macro assumes that irqstat (r6) and base (r5) are
47 * preserved from get_irqnr_and_base above 47 * preserved from get_irqnr_and_base above
48 */ 48 */
49 test_for_ipi r0, r6, r5, lr 49 ALT_SMP(test_for_ipi r0, r6, r5, lr)
50 ALT_UP_B(9997f)
50 movne r0, sp 51 movne r0, sp
51 adrne lr, BSYM(1b) 52 adrne lr, BSYM(1b)
52 bne do_IPI 53 bne do_IPI
@@ -57,6 +58,7 @@
57 adrne lr, BSYM(1b) 58 adrne lr, BSYM(1b)
58 bne do_local_timer 59 bne do_local_timer
59#endif 60#endif
619997:
60#endif 62#endif
61 63
62 .endm 64 .endm
@@ -965,11 +967,8 @@ kuser_cmpxchg_fixup:
965 beq 1b 967 beq 1b
966 rsbs r0, r3, #0 968 rsbs r0, r3, #0
967 /* beware -- each __kuser slot must be 8 instructions max */ 969 /* beware -- each __kuser slot must be 8 instructions max */
968#ifdef CONFIG_SMP 970 ALT_SMP(b __kuser_memory_barrier)
969 b __kuser_memory_barrier 971 ALT_UP(usr_ret lr)
970#else
971 usr_ret lr
972#endif
973 972
974#endif 973#endif
975 974
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 7885722bdf4e..8bfa98757cd2 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -129,30 +129,58 @@ ENDPROC(ret_from_fork)
129 * clobber the ip register. This is OK because the ARM calling convention 129 * clobber the ip register. This is OK because the ARM calling convention
130 * allows it to be clobbered in subroutines and doesn't use it to hold 130 * allows it to be clobbered in subroutines and doesn't use it to hold
131 * parameters.) 131 * parameters.)
132 *
133 * When using dynamic ftrace, we patch out the mcount call by a "mov r0, r0"
134 * for the mcount case, and a "pop {lr}" for the __gnu_mcount_nc case (see
135 * arch/arm/kernel/ftrace.c).
132 */ 136 */
137
138#ifndef CONFIG_OLD_MCOUNT
139#if (__GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 4))
140#error Ftrace requires CONFIG_FRAME_POINTER=y with GCC older than 4.4.0.
141#endif
142#endif
143
133#ifdef CONFIG_DYNAMIC_FTRACE 144#ifdef CONFIG_DYNAMIC_FTRACE
134ENTRY(mcount) 145ENTRY(__gnu_mcount_nc)
146 mov ip, lr
147 ldmia sp!, {lr}
148 mov pc, ip
149ENDPROC(__gnu_mcount_nc)
150
151ENTRY(ftrace_caller)
135 stmdb sp!, {r0-r3, lr} 152 stmdb sp!, {r0-r3, lr}
136 mov r0, lr 153 mov r0, lr
137 sub r0, r0, #MCOUNT_INSN_SIZE 154 sub r0, r0, #MCOUNT_INSN_SIZE
155 ldr r1, [sp, #20]
138 156
139 .globl mcount_call 157 .global ftrace_call
140mcount_call: 158ftrace_call:
141 bl ftrace_stub 159 bl ftrace_stub
142 ldr lr, [fp, #-4] @ restore lr 160 ldmia sp!, {r0-r3, ip, lr}
143 ldmia sp!, {r0-r3, pc} 161 mov pc, ip
162ENDPROC(ftrace_caller)
144 163
145ENTRY(ftrace_caller) 164#ifdef CONFIG_OLD_MCOUNT
165ENTRY(mcount)
166 stmdb sp!, {lr}
167 ldr lr, [fp, #-4]
168 ldmia sp!, {pc}
169ENDPROC(mcount)
170
171ENTRY(ftrace_caller_old)
146 stmdb sp!, {r0-r3, lr} 172 stmdb sp!, {r0-r3, lr}
147 ldr r1, [fp, #-4] 173 ldr r1, [fp, #-4]
148 mov r0, lr 174 mov r0, lr
149 sub r0, r0, #MCOUNT_INSN_SIZE 175 sub r0, r0, #MCOUNT_INSN_SIZE
150 176
151 .globl ftrace_call 177 .globl ftrace_call_old
152ftrace_call: 178ftrace_call_old:
153 bl ftrace_stub 179 bl ftrace_stub
154 ldr lr, [fp, #-4] @ restore lr 180 ldr lr, [fp, #-4] @ restore lr
155 ldmia sp!, {r0-r3, pc} 181 ldmia sp!, {r0-r3, pc}
182ENDPROC(ftrace_caller_old)
183#endif
156 184
157#else 185#else
158 186
@@ -160,7 +188,7 @@ ENTRY(__gnu_mcount_nc)
160 stmdb sp!, {r0-r3, lr} 188 stmdb sp!, {r0-r3, lr}
161 ldr r0, =ftrace_trace_function 189 ldr r0, =ftrace_trace_function
162 ldr r2, [r0] 190 ldr r2, [r0]
163 adr r0, ftrace_stub 191 adr r0, .Lftrace_stub
164 cmp r0, r2 192 cmp r0, r2
165 bne gnu_trace 193 bne gnu_trace
166 ldmia sp!, {r0-r3, ip, lr} 194 ldmia sp!, {r0-r3, ip, lr}
@@ -170,11 +198,19 @@ gnu_trace:
170 ldr r1, [sp, #20] @ lr of instrumented routine 198 ldr r1, [sp, #20] @ lr of instrumented routine
171 mov r0, lr 199 mov r0, lr
172 sub r0, r0, #MCOUNT_INSN_SIZE 200 sub r0, r0, #MCOUNT_INSN_SIZE
173 mov lr, pc 201 adr lr, BSYM(1f)
174 mov pc, r2 202 mov pc, r2
2031:
175 ldmia sp!, {r0-r3, ip, lr} 204 ldmia sp!, {r0-r3, ip, lr}
176 mov pc, ip 205 mov pc, ip
206ENDPROC(__gnu_mcount_nc)
177 207
208#ifdef CONFIG_OLD_MCOUNT
209/*
210 * This is under an ifdef in order to force link-time errors for people trying
211 * to build with !FRAME_POINTER with a GCC which doesn't use the new-style
212 * mcount.
213 */
178ENTRY(mcount) 214ENTRY(mcount)
179 stmdb sp!, {r0-r3, lr} 215 stmdb sp!, {r0-r3, lr}
180 ldr r0, =ftrace_trace_function 216 ldr r0, =ftrace_trace_function
@@ -193,12 +229,15 @@ trace:
193 mov pc, r2 229 mov pc, r2
194 ldr lr, [fp, #-4] @ restore lr 230 ldr lr, [fp, #-4] @ restore lr
195 ldmia sp!, {r0-r3, pc} 231 ldmia sp!, {r0-r3, pc}
232ENDPROC(mcount)
233#endif
196 234
197#endif /* CONFIG_DYNAMIC_FTRACE */ 235#endif /* CONFIG_DYNAMIC_FTRACE */
198 236
199 .globl ftrace_stub 237ENTRY(ftrace_stub)
200ftrace_stub: 238.Lftrace_stub:
201 mov pc, lr 239 mov pc, lr
240ENDPROC(ftrace_stub)
202 241
203#endif /* CONFIG_FUNCTION_TRACER */ 242#endif /* CONFIG_FUNCTION_TRACER */
204 243
@@ -295,7 +334,6 @@ ENTRY(vector_swi)
295 334
296 get_thread_info tsk 335 get_thread_info tsk
297 adr tbl, sys_call_table @ load syscall table pointer 336 adr tbl, sys_call_table @ load syscall table pointer
298 ldr ip, [tsk, #TI_FLAGS] @ check for syscall tracing
299 337
300#if defined(CONFIG_OABI_COMPAT) 338#if defined(CONFIG_OABI_COMPAT)
301 /* 339 /*
@@ -312,8 +350,20 @@ ENTRY(vector_swi)
312 eor scno, scno, #__NR_SYSCALL_BASE @ check OS number 350 eor scno, scno, #__NR_SYSCALL_BASE @ check OS number
313#endif 351#endif
314 352
353 ldr r10, [tsk, #TI_FLAGS] @ check for syscall tracing
315 stmdb sp!, {r4, r5} @ push fifth and sixth args 354 stmdb sp!, {r4, r5} @ push fifth and sixth args
316 tst ip, #_TIF_SYSCALL_TRACE @ are we tracing syscalls? 355
356#ifdef CONFIG_SECCOMP
357 tst r10, #_TIF_SECCOMP
358 beq 1f
359 mov r0, scno
360 bl __secure_computing
361 add r0, sp, #S_R0 + S_OFF @ pointer to regs
362 ldmia r0, {r0 - r3} @ have to reload r0 - r3
3631:
364#endif
365
366 tst r10, #_TIF_SYSCALL_TRACE @ are we tracing syscalls?
317 bne __sys_trace 367 bne __sys_trace
318 368
319 cmp scno, #NR_syscalls @ check upper syscall limit 369 cmp scno, #NR_syscalls @ check upper syscall limit
diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c
index 33c7077174db..a48d51257988 100644
--- a/arch/arm/kernel/etm.c
+++ b/arch/arm/kernel/etm.c
@@ -30,6 +30,21 @@
30MODULE_LICENSE("GPL"); 30MODULE_LICENSE("GPL");
31MODULE_AUTHOR("Alexander Shishkin"); 31MODULE_AUTHOR("Alexander Shishkin");
32 32
33/*
34 * ETM tracer state
35 */
36struct tracectx {
37 unsigned int etb_bufsz;
38 void __iomem *etb_regs;
39 void __iomem *etm_regs;
40 unsigned long flags;
41 int ncmppairs;
42 int etm_portsz;
43 struct device *dev;
44 struct clk *emu_clk;
45 struct mutex mutex;
46};
47
33static struct tracectx tracer; 48static struct tracectx tracer;
34 49
35static inline bool trace_isrunning(struct tracectx *t) 50static inline bool trace_isrunning(struct tracectx *t)
diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c
index 0298286ad4ad..971ac8c36ea7 100644
--- a/arch/arm/kernel/ftrace.c
+++ b/arch/arm/kernel/ftrace.c
@@ -2,102 +2,194 @@
2 * Dynamic function tracing support. 2 * Dynamic function tracing support.
3 * 3 *
4 * Copyright (C) 2008 Abhishek Sagar <sagar.abhishek@gmail.com> 4 * Copyright (C) 2008 Abhishek Sagar <sagar.abhishek@gmail.com>
5 * Copyright (C) 2010 Rabin Vincent <rabin@rab.in>
5 * 6 *
6 * For licencing details, see COPYING. 7 * For licencing details, see COPYING.
7 * 8 *
8 * Defines low-level handling of mcount calls when the kernel 9 * Defines low-level handling of mcount calls when the kernel
9 * is compiled with the -pg flag. When using dynamic ftrace, the 10 * is compiled with the -pg flag. When using dynamic ftrace, the
10 * mcount call-sites get patched lazily with NOP till they are 11 * mcount call-sites get patched with NOP till they are enabled.
11 * enabled. All code mutation routines here take effect atomically. 12 * All code mutation routines here are called under stop_machine().
12 */ 13 */
13 14
14#include <linux/ftrace.h> 15#include <linux/ftrace.h>
16#include <linux/uaccess.h>
15 17
16#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
17#include <asm/ftrace.h> 19#include <asm/ftrace.h>
18 20
19#define PC_OFFSET 8 21#ifdef CONFIG_THUMB2_KERNEL
20#define BL_OPCODE 0xeb000000 22#define NOP 0xeb04f85d /* pop.w {lr} */
21#define BL_OFFSET_MASK 0x00ffffff 23#else
24#define NOP 0xe8bd4000 /* pop {lr} */
25#endif
22 26
23static unsigned long bl_insn; 27#ifdef CONFIG_OLD_MCOUNT
24static const unsigned long NOP = 0xe1a00000; /* mov r0, r0 */ 28#define OLD_MCOUNT_ADDR ((unsigned long) mcount)
29#define OLD_FTRACE_ADDR ((unsigned long) ftrace_caller_old)
25 30
26unsigned char *ftrace_nop_replace(void) 31#define OLD_NOP 0xe1a00000 /* mov r0, r0 */
32
33static unsigned long ftrace_nop_replace(struct dyn_ftrace *rec)
27{ 34{
28 return (char *)&NOP; 35 return rec->arch.old_mcount ? OLD_NOP : NOP;
29} 36}
30 37
38static unsigned long adjust_address(struct dyn_ftrace *rec, unsigned long addr)
39{
40 if (!rec->arch.old_mcount)
41 return addr;
42
43 if (addr == MCOUNT_ADDR)
44 addr = OLD_MCOUNT_ADDR;
45 else if (addr == FTRACE_ADDR)
46 addr = OLD_FTRACE_ADDR;
47
48 return addr;
49}
50#else
51static unsigned long ftrace_nop_replace(struct dyn_ftrace *rec)
52{
53 return NOP;
54}
55
56static unsigned long adjust_address(struct dyn_ftrace *rec, unsigned long addr)
57{
58 return addr;
59}
60#endif
61
31/* construct a branch (BL) instruction to addr */ 62/* construct a branch (BL) instruction to addr */
32unsigned char *ftrace_call_replace(unsigned long pc, unsigned long addr) 63#ifdef CONFIG_THUMB2_KERNEL
64static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr)
33{ 65{
66 unsigned long s, j1, j2, i1, i2, imm10, imm11;
67 unsigned long first, second;
34 long offset; 68 long offset;
35 69
36 offset = (long)addr - (long)(pc + PC_OFFSET); 70 offset = (long)addr - (long)(pc + 4);
71 if (offset < -16777216 || offset > 16777214) {
72 WARN_ON_ONCE(1);
73 return 0;
74 }
75
76 s = (offset >> 24) & 0x1;
77 i1 = (offset >> 23) & 0x1;
78 i2 = (offset >> 22) & 0x1;
79 imm10 = (offset >> 12) & 0x3ff;
80 imm11 = (offset >> 1) & 0x7ff;
81
82 j1 = (!i1) ^ s;
83 j2 = (!i2) ^ s;
84
85 first = 0xf000 | (s << 10) | imm10;
86 second = 0xd000 | (j1 << 13) | (j2 << 11) | imm11;
87
88 return (second << 16) | first;
89}
90#else
91static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr)
92{
93 long offset;
94
95 offset = (long)addr - (long)(pc + 8);
37 if (unlikely(offset < -33554432 || offset > 33554428)) { 96 if (unlikely(offset < -33554432 || offset > 33554428)) {
38 /* Can't generate branches that far (from ARM ARM). Ftrace 97 /* Can't generate branches that far (from ARM ARM). Ftrace
39 * doesn't generate branches outside of kernel text. 98 * doesn't generate branches outside of kernel text.
40 */ 99 */
41 WARN_ON_ONCE(1); 100 WARN_ON_ONCE(1);
42 return NULL; 101 return 0;
43 } 102 }
44 offset = (offset >> 2) & BL_OFFSET_MASK;
45 bl_insn = BL_OPCODE | offset;
46 return (unsigned char *)&bl_insn;
47}
48 103
49int ftrace_modify_code(unsigned long pc, unsigned char *old_code, 104 offset = (offset >> 2) & 0x00ffffff;
50 unsigned char *new_code)
51{
52 unsigned long err = 0, replaced = 0, old, new;
53 105
54 old = *(unsigned long *)old_code; 106 return 0xeb000000 | offset;
55 new = *(unsigned long *)new_code; 107}
108#endif
56 109
57 __asm__ __volatile__ ( 110static int ftrace_modify_code(unsigned long pc, unsigned long old,
58 "1: ldr %1, [%2] \n" 111 unsigned long new)
59 " cmp %1, %4 \n" 112{
60 "2: streq %3, [%2] \n" 113 unsigned long replaced;
61 " cmpne %1, %3 \n"
62 " movne %0, #2 \n"
63 "3:\n"
64 114
65 ".pushsection .fixup, \"ax\"\n" 115 if (probe_kernel_read(&replaced, (void *)pc, MCOUNT_INSN_SIZE))
66 "4: mov %0, #1 \n" 116 return -EFAULT;
67 " b 3b \n"
68 ".popsection\n"
69 117
70 ".pushsection __ex_table, \"a\"\n" 118 if (replaced != old)
71 " .long 1b, 4b \n" 119 return -EINVAL;
72 " .long 2b, 4b \n"
73 ".popsection\n"
74 120
75 : "=r"(err), "=r"(replaced) 121 if (probe_kernel_write((void *)pc, &new, MCOUNT_INSN_SIZE))
76 : "r"(pc), "r"(new), "r"(old), "0"(err), "1"(replaced) 122 return -EPERM;
77 : "memory");
78 123
79 if (!err && (replaced == old)) 124 flush_icache_range(pc, pc + MCOUNT_INSN_SIZE);
80 flush_icache_range(pc, pc + MCOUNT_INSN_SIZE);
81 125
82 return err; 126 return 0;
83} 127}
84 128
85int ftrace_update_ftrace_func(ftrace_func_t func) 129int ftrace_update_ftrace_func(ftrace_func_t func)
86{ 130{
87 int ret;
88 unsigned long pc, old; 131 unsigned long pc, old;
89 unsigned char *new; 132 unsigned long new;
133 int ret;
90 134
91 pc = (unsigned long)&ftrace_call; 135 pc = (unsigned long)&ftrace_call;
92 memcpy(&old, &ftrace_call, MCOUNT_INSN_SIZE); 136 memcpy(&old, &ftrace_call, MCOUNT_INSN_SIZE);
93 new = ftrace_call_replace(pc, (unsigned long)func); 137 new = ftrace_call_replace(pc, (unsigned long)func);
94 ret = ftrace_modify_code(pc, (unsigned char *)&old, new); 138
139 ret = ftrace_modify_code(pc, old, new);
140
141#ifdef CONFIG_OLD_MCOUNT
142 if (!ret) {
143 pc = (unsigned long)&ftrace_call_old;
144 memcpy(&old, &ftrace_call_old, MCOUNT_INSN_SIZE);
145 new = ftrace_call_replace(pc, (unsigned long)func);
146
147 ret = ftrace_modify_code(pc, old, new);
148 }
149#endif
150
151 return ret;
152}
153
154int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
155{
156 unsigned long new, old;
157 unsigned long ip = rec->ip;
158
159 old = ftrace_nop_replace(rec);
160 new = ftrace_call_replace(ip, adjust_address(rec, addr));
161
162 return ftrace_modify_code(rec->ip, old, new);
163}
164
165int ftrace_make_nop(struct module *mod,
166 struct dyn_ftrace *rec, unsigned long addr)
167{
168 unsigned long ip = rec->ip;
169 unsigned long old;
170 unsigned long new;
171 int ret;
172
173 old = ftrace_call_replace(ip, adjust_address(rec, addr));
174 new = ftrace_nop_replace(rec);
175 ret = ftrace_modify_code(ip, old, new);
176
177#ifdef CONFIG_OLD_MCOUNT
178 if (ret == -EINVAL && addr == MCOUNT_ADDR) {
179 rec->arch.old_mcount = true;
180
181 old = ftrace_call_replace(ip, adjust_address(rec, addr));
182 new = ftrace_nop_replace(rec);
183 ret = ftrace_modify_code(ip, old, new);
184 }
185#endif
186
95 return ret; 187 return ret;
96} 188}
97 189
98/* run from ftrace_init with irqs disabled */
99int __init ftrace_dyn_arch_init(void *data) 190int __init ftrace_dyn_arch_init(void *data)
100{ 191{
101 ftrace_mcount_set(data); 192 *(unsigned long *)data = 0;
193
102 return 0; 194 return 0;
103} 195}
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index b9505aa267c0..bbecaac1e013 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -15,55 +15,6 @@
15#define ATAG_CORE_SIZE ((2*4 + 3*4) >> 2) 15#define ATAG_CORE_SIZE ((2*4 + 3*4) >> 2)
16#define ATAG_CORE_SIZE_EMPTY ((2*4) >> 2) 16#define ATAG_CORE_SIZE_EMPTY ((2*4) >> 2)
17 17
18 .align 2
19 .type __switch_data, %object
20__switch_data:
21 .long __mmap_switched
22 .long __data_loc @ r4
23 .long _data @ r5
24 .long __bss_start @ r6
25 .long _end @ r7
26 .long processor_id @ r4
27 .long __machine_arch_type @ r5
28 .long __atags_pointer @ r6
29 .long cr_alignment @ r7
30 .long init_thread_union + THREAD_START_SP @ sp
31
32/*
33 * The following fragment of code is executed with the MMU on in MMU mode,
34 * and uses absolute addresses; this is not position independent.
35 *
36 * r0 = cp#15 control register
37 * r1 = machine ID
38 * r2 = atags pointer
39 * r9 = processor ID
40 */
41__mmap_switched:
42 adr r3, __switch_data + 4
43
44 ldmia r3!, {r4, r5, r6, r7}
45 cmp r4, r5 @ Copy data segment if needed
461: cmpne r5, r6
47 ldrne fp, [r4], #4
48 strne fp, [r5], #4
49 bne 1b
50
51 mov fp, #0 @ Clear BSS (and zero fp)
521: cmp r6, r7
53 strcc fp, [r6],#4
54 bcc 1b
55
56 ARM( ldmia r3, {r4, r5, r6, r7, sp})
57 THUMB( ldmia r3, {r4, r5, r6, r7} )
58 THUMB( ldr sp, [r3, #16] )
59 str r9, [r4] @ Save processor ID
60 str r1, [r5] @ Save machine type
61 str r2, [r6] @ Save atags pointer
62 bic r4, r0, #CR_A @ Clear 'A' bit
63 stmia r7, {r0, r4} @ Save control register values
64 b start_kernel
65ENDPROC(__mmap_switched)
66
67/* 18/*
68 * Exception handling. Something went wrong and we can't proceed. We 19 * Exception handling. Something went wrong and we can't proceed. We
69 * ought to tell the user, but since we don't have any guarantee that 20 * ought to tell the user, but since we don't have any guarantee that
@@ -73,21 +24,7 @@ ENDPROC(__mmap_switched)
73 * and hope for the best (useful if bootloader fails to pass a proper 24 * and hope for the best (useful if bootloader fails to pass a proper
74 * machine ID for example). 25 * machine ID for example).
75 */ 26 */
76__error_p: 27 __HEAD
77#ifdef CONFIG_DEBUG_LL
78 adr r0, str_p1
79 bl printascii
80 mov r0, r9
81 bl printhex8
82 adr r0, str_p2
83 bl printascii
84 b __error
85str_p1: .asciz "\nError: unrecognized/unsupported processor variant (0x"
86str_p2: .asciz ").\n"
87 .align
88#endif
89ENDPROC(__error_p)
90
91__error_a: 28__error_a:
92#ifdef CONFIG_DEBUG_LL 29#ifdef CONFIG_DEBUG_LL
93 mov r4, r1 @ preserve machine ID 30 mov r4, r1 @ preserve machine ID
@@ -97,7 +34,7 @@ __error_a:
97 bl printhex8 34 bl printhex8
98 adr r0, str_a2 35 adr r0, str_a2
99 bl printascii 36 bl printascii
100 adr r3, 4f 37 adr r3, __lookup_machine_type_data
101 ldmia r3, {r4, r5, r6} @ get machine desc list 38 ldmia r3, {r4, r5, r6} @ get machine desc list
102 sub r4, r3, r4 @ get offset between virt&phys 39 sub r4, r3, r4 @ get offset between virt&phys
103 add r5, r5, r4 @ convert virt addresses to 40 add r5, r5, r4 @ convert virt addresses to
@@ -125,78 +62,6 @@ str_a3: .asciz "\nPlease check your kernel config and/or bootloader.\n"
125 .align 62 .align
126#endif 63#endif
127 64
128__error:
129#ifdef CONFIG_ARCH_RPC
130/*
131 * Turn the screen red on a error - RiscPC only.
132 */
133 mov r0, #0x02000000
134 mov r3, #0x11
135 orr r3, r3, r3, lsl #8
136 orr r3, r3, r3, lsl #16
137 str r3, [r0], #4
138 str r3, [r0], #4
139 str r3, [r0], #4
140 str r3, [r0], #4
141#endif
1421: mov r0, r0
143 b 1b
144ENDPROC(__error)
145
146
147/*
148 * Read processor ID register (CP#15, CR0), and look up in the linker-built
149 * supported processor list. Note that we can't use the absolute addresses
150 * for the __proc_info lists since we aren't running with the MMU on
151 * (and therefore, we are not in the correct address space). We have to
152 * calculate the offset.
153 *
154 * r9 = cpuid
155 * Returns:
156 * r3, r4, r6 corrupted
157 * r5 = proc_info pointer in physical address space
158 * r9 = cpuid (preserved)
159 */
160__lookup_processor_type:
161 adr r3, 3f
162 ldmia r3, {r5 - r7}
163 add r3, r3, #8
164 sub r3, r3, r7 @ get offset between virt&phys
165 add r5, r5, r3 @ convert virt addresses to
166 add r6, r6, r3 @ physical address space
1671: ldmia r5, {r3, r4} @ value, mask
168 and r4, r4, r9 @ mask wanted bits
169 teq r3, r4
170 beq 2f
171 add r5, r5, #PROC_INFO_SZ @ sizeof(proc_info_list)
172 cmp r5, r6
173 blo 1b
174 mov r5, #0 @ unknown processor
1752: mov pc, lr
176ENDPROC(__lookup_processor_type)
177
178/*
179 * This provides a C-API version of the above function.
180 */
181ENTRY(lookup_processor_type)
182 stmfd sp!, {r4 - r7, r9, lr}
183 mov r9, r0
184 bl __lookup_processor_type
185 mov r0, r5
186 ldmfd sp!, {r4 - r7, r9, pc}
187ENDPROC(lookup_processor_type)
188
189/*
190 * Look in <asm/procinfo.h> and arch/arm/kernel/arch.[ch] for
191 * more information about the __proc_info and __arch_info structures.
192 */
193 .align 2
1943: .long __proc_info_begin
195 .long __proc_info_end
1964: .long .
197 .long __arch_info_begin
198 .long __arch_info_end
199
200/* 65/*
201 * Lookup machine architecture in the linker-build list of architectures. 66 * Lookup machine architecture in the linker-build list of architectures.
202 * Note that we can't use the absolute addresses for the __arch_info 67 * Note that we can't use the absolute addresses for the __arch_info
@@ -209,7 +74,7 @@ ENDPROC(lookup_processor_type)
209 * r5 = mach_info pointer in physical address space 74 * r5 = mach_info pointer in physical address space
210 */ 75 */
211__lookup_machine_type: 76__lookup_machine_type:
212 adr r3, 4b 77 adr r3, __lookup_machine_type_data
213 ldmia r3, {r4, r5, r6} 78 ldmia r3, {r4, r5, r6}
214 sub r3, r3, r4 @ get offset between virt&phys 79 sub r3, r3, r4 @ get offset between virt&phys
215 add r5, r5, r3 @ convert virt addresses to 80 add r5, r5, r3 @ convert virt addresses to
@@ -225,15 +90,16 @@ __lookup_machine_type:
225ENDPROC(__lookup_machine_type) 90ENDPROC(__lookup_machine_type)
226 91
227/* 92/*
228 * This provides a C-API version of the above function. 93 * Look in arch/arm/kernel/arch.[ch] for information about the
94 * __arch_info structures.
229 */ 95 */
230ENTRY(lookup_machine_type) 96 .align 2
231 stmfd sp!, {r4 - r6, lr} 97 .type __lookup_machine_type_data, %object
232 mov r1, r0 98__lookup_machine_type_data:
233 bl __lookup_machine_type 99 .long .
234 mov r0, r5 100 .long __arch_info_begin
235 ldmfd sp!, {r4 - r6, pc} 101 .long __arch_info_end
236ENDPROC(lookup_machine_type) 102 .size __lookup_machine_type_data, . - __lookup_machine_type_data
237 103
238/* Determine validity of the r2 atags pointer. The heuristic requires 104/* Determine validity of the r2 atags pointer. The heuristic requires
239 * that the pointer be aligned, in the first 16k of physical RAM and 105 * that the pointer be aligned, in the first 16k of physical RAM and
@@ -265,3 +131,150 @@ __vet_atags:
2651: mov r2, #0 1311: mov r2, #0
266 mov pc, lr 132 mov pc, lr
267ENDPROC(__vet_atags) 133ENDPROC(__vet_atags)
134
135/*
136 * The following fragment of code is executed with the MMU on in MMU mode,
137 * and uses absolute addresses; this is not position independent.
138 *
139 * r0 = cp#15 control register
140 * r1 = machine ID
141 * r2 = atags pointer
142 * r9 = processor ID
143 */
144 __INIT
145__mmap_switched:
146 adr r3, __mmap_switched_data
147
148 ldmia r3!, {r4, r5, r6, r7}
149 cmp r4, r5 @ Copy data segment if needed
1501: cmpne r5, r6
151 ldrne fp, [r4], #4
152 strne fp, [r5], #4
153 bne 1b
154
155 mov fp, #0 @ Clear BSS (and zero fp)
1561: cmp r6, r7
157 strcc fp, [r6],#4
158 bcc 1b
159
160 ARM( ldmia r3, {r4, r5, r6, r7, sp})
161 THUMB( ldmia r3, {r4, r5, r6, r7} )
162 THUMB( ldr sp, [r3, #16] )
163 str r9, [r4] @ Save processor ID
164 str r1, [r5] @ Save machine type
165 str r2, [r6] @ Save atags pointer
166 bic r4, r0, #CR_A @ Clear 'A' bit
167 stmia r7, {r0, r4} @ Save control register values
168 b start_kernel
169ENDPROC(__mmap_switched)
170
171 .align 2
172 .type __mmap_switched_data, %object
173__mmap_switched_data:
174 .long __data_loc @ r4
175 .long _sdata @ r5
176 .long __bss_start @ r6
177 .long _end @ r7
178 .long processor_id @ r4
179 .long __machine_arch_type @ r5
180 .long __atags_pointer @ r6
181 .long cr_alignment @ r7
182 .long init_thread_union + THREAD_START_SP @ sp
183 .size __mmap_switched_data, . - __mmap_switched_data
184
185/*
186 * This provides a C-API version of __lookup_machine_type
187 */
188ENTRY(lookup_machine_type)
189 stmfd sp!, {r4 - r6, lr}
190 mov r1, r0
191 bl __lookup_machine_type
192 mov r0, r5
193 ldmfd sp!, {r4 - r6, pc}
194ENDPROC(lookup_machine_type)
195
196/*
197 * This provides a C-API version of __lookup_processor_type
198 */
199ENTRY(lookup_processor_type)
200 stmfd sp!, {r4 - r6, r9, lr}
201 mov r9, r0
202 bl __lookup_processor_type
203 mov r0, r5
204 ldmfd sp!, {r4 - r6, r9, pc}
205ENDPROC(lookup_processor_type)
206
207/*
208 * Read processor ID register (CP#15, CR0), and look up in the linker-built
209 * supported processor list. Note that we can't use the absolute addresses
210 * for the __proc_info lists since we aren't running with the MMU on
211 * (and therefore, we are not in the correct address space). We have to
212 * calculate the offset.
213 *
214 * r9 = cpuid
215 * Returns:
216 * r3, r4, r6 corrupted
217 * r5 = proc_info pointer in physical address space
218 * r9 = cpuid (preserved)
219 */
220 __CPUINIT
221__lookup_processor_type:
222 adr r3, __lookup_processor_type_data
223 ldmia r3, {r4 - r6}
224 sub r3, r3, r4 @ get offset between virt&phys
225 add r5, r5, r3 @ convert virt addresses to
226 add r6, r6, r3 @ physical address space
2271: ldmia r5, {r3, r4} @ value, mask
228 and r4, r4, r9 @ mask wanted bits
229 teq r3, r4
230 beq 2f
231 add r5, r5, #PROC_INFO_SZ @ sizeof(proc_info_list)
232 cmp r5, r6
233 blo 1b
234 mov r5, #0 @ unknown processor
2352: mov pc, lr
236ENDPROC(__lookup_processor_type)
237
238/*
239 * Look in <asm/procinfo.h> for information about the __proc_info structure.
240 */
241 .align 2
242 .type __lookup_processor_type_data, %object
243__lookup_processor_type_data:
244 .long .
245 .long __proc_info_begin
246 .long __proc_info_end
247 .size __lookup_processor_type_data, . - __lookup_processor_type_data
248
249__error_p:
250#ifdef CONFIG_DEBUG_LL
251 adr r0, str_p1
252 bl printascii
253 mov r0, r9
254 bl printhex8
255 adr r0, str_p2
256 bl printascii
257 b __error
258str_p1: .asciz "\nError: unrecognized/unsupported processor variant (0x"
259str_p2: .asciz ").\n"
260 .align
261#endif
262ENDPROC(__error_p)
263
264__error:
265#ifdef CONFIG_ARCH_RPC
266/*
267 * Turn the screen red on a error - RiscPC only.
268 */
269 mov r0, #0x02000000
270 mov r3, #0x11
271 orr r3, r3, r3, lsl #8
272 orr r3, r3, r3, lsl #16
273 str r3, [r0], #4
274 str r3, [r0], #4
275 str r3, [r0], #4
276 str r3, [r0], #4
277#endif
2781: mov r0, r0
279 b 1b
280ENDPROC(__error)
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index 573b803dc6bf..814ce1a73270 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -48,8 +48,6 @@ ENTRY(stext)
48 movs r8, r5 @ invalid machine (r5=0)? 48 movs r8, r5 @ invalid machine (r5=0)?
49 beq __error_a @ yes, error 'a' 49 beq __error_a @ yes, error 'a'
50 50
51 ldr r13, __switch_data @ address to jump to after
52 @ the initialization is done
53 adr lr, BSYM(__after_proc_init) @ return (PIC) address 51 adr lr, BSYM(__after_proc_init) @ return (PIC) address
54 ARM( add pc, r10, #PROCINFO_INITFUNC ) 52 ARM( add pc, r10, #PROCINFO_INITFUNC )
55 THUMB( add r12, r10, #PROCINFO_INITFUNC ) 53 THUMB( add r12, r10, #PROCINFO_INITFUNC )
@@ -87,8 +85,7 @@ __after_proc_init:
87 mcr p15, 0, r0, c1, c0, 0 @ write control reg 85 mcr p15, 0, r0, c1, c0, 0 @ write control reg
88#endif /* CONFIG_CPU_CP15 */ 86#endif /* CONFIG_CPU_CP15 */
89 87
90 mov r3, r13 88 b __mmap_switched @ clear the BSS and jump
91 mov pc, r3 @ clear the BSS and jump
92 @ to start_kernel 89 @ to start_kernel
93ENDPROC(__after_proc_init) 90ENDPROC(__after_proc_init)
94 .ltorg 91 .ltorg
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf947212..dd6b369ac69c 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -22,6 +22,10 @@
22#include <asm/thread_info.h> 22#include <asm/thread_info.h>
23#include <asm/system.h> 23#include <asm/system.h>
24 24
25#ifdef CONFIG_DEBUG_LL
26#include <mach/debug-macro.S>
27#endif
28
25#if (PHYS_OFFSET & 0x001fffff) 29#if (PHYS_OFFSET & 0x001fffff)
26#error "PHYS_OFFSET must be at an even 2MiB boundary!" 30#error "PHYS_OFFSET must be at an even 2MiB boundary!"
27#endif 31#endif
@@ -86,6 +90,9 @@ ENTRY(stext)
86 movs r8, r5 @ invalid machine (r5=0)? 90 movs r8, r5 @ invalid machine (r5=0)?
87 beq __error_a @ yes, error 'a' 91 beq __error_a @ yes, error 'a'
88 bl __vet_atags 92 bl __vet_atags
93#ifdef CONFIG_SMP_ON_UP
94 bl __fixup_smp
95#endif
89 bl __create_page_tables 96 bl __create_page_tables
90 97
91 /* 98 /*
@@ -95,113 +102,15 @@ ENTRY(stext)
95 * above. On return, the CPU will be ready for the MMU to be 102 * above. On return, the CPU will be ready for the MMU to be
96 * turned on, and r0 will hold the CPU control register value. 103 * turned on, and r0 will hold the CPU control register value.
97 */ 104 */
98 ldr r13, __switch_data @ address to jump to after 105 ldr r13, =__mmap_switched @ address to jump to after
99 @ mmu has been enabled 106 @ mmu has been enabled
100 adr lr, BSYM(__enable_mmu) @ return (PIC) address 107 adr lr, BSYM(1f) @ return (PIC) address
101 ARM( add pc, r10, #PROCINFO_INITFUNC ) 108 ARM( add pc, r10, #PROCINFO_INITFUNC )
102 THUMB( add r12, r10, #PROCINFO_INITFUNC ) 109 THUMB( add r12, r10, #PROCINFO_INITFUNC )
103 THUMB( mov pc, r12 ) 110 THUMB( mov pc, r12 )
1111: b __enable_mmu
104ENDPROC(stext) 112ENDPROC(stext)
105 113 .ltorg
106#if defined(CONFIG_SMP)
107ENTRY(secondary_startup)
108 /*
109 * Common entry point for secondary CPUs.
110 *
111 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
112 * the processor type - there is no need to check the machine type
113 * as it has already been validated by the primary processor.
114 */
115 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
116 mrc p15, 0, r9, c0, c0 @ get processor id
117 bl __lookup_processor_type
118 movs r10, r5 @ invalid processor?
119 moveq r0, #'p' @ yes, error 'p'
120 beq __error
121
122 /*
123 * Use the page tables supplied from __cpu_up.
124 */
125 adr r4, __secondary_data
126 ldmia r4, {r5, r7, r12} @ address to jump to after
127 sub r4, r4, r5 @ mmu has been enabled
128 ldr r4, [r7, r4] @ get secondary_data.pgdir
129 adr lr, BSYM(__enable_mmu) @ return address
130 mov r13, r12 @ __secondary_switched address
131 ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor
132 @ (return control reg)
133 THUMB( add r12, r10, #PROCINFO_INITFUNC )
134 THUMB( mov pc, r12 )
135ENDPROC(secondary_startup)
136
137 /*
138 * r6 = &secondary_data
139 */
140ENTRY(__secondary_switched)
141 ldr sp, [r7, #4] @ get secondary_data.stack
142 mov fp, #0
143 b secondary_start_kernel
144ENDPROC(__secondary_switched)
145
146 .type __secondary_data, %object
147__secondary_data:
148 .long .
149 .long secondary_data
150 .long __secondary_switched
151#endif /* defined(CONFIG_SMP) */
152
153
154
155/*
156 * Setup common bits before finally enabling the MMU. Essentially
157 * this is just loading the page table pointer and domain access
158 * registers.
159 */
160__enable_mmu:
161#ifdef CONFIG_ALIGNMENT_TRAP
162 orr r0, r0, #CR_A
163#else
164 bic r0, r0, #CR_A
165#endif
166#ifdef CONFIG_CPU_DCACHE_DISABLE
167 bic r0, r0, #CR_C
168#endif
169#ifdef CONFIG_CPU_BPREDICT_DISABLE
170 bic r0, r0, #CR_Z
171#endif
172#ifdef CONFIG_CPU_ICACHE_DISABLE
173 bic r0, r0, #CR_I
174#endif
175 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
176 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
177 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
178 domain_val(DOMAIN_IO, DOMAIN_CLIENT))
179 mcr p15, 0, r5, c3, c0, 0 @ load domain access register
180 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
181 b __turn_mmu_on
182ENDPROC(__enable_mmu)
183
184/*
185 * Enable the MMU. This completely changes the structure of the visible
186 * memory space. You will not be able to trace execution through this.
187 * If you have an enquiry about this, *please* check the linux-arm-kernel
188 * mailing list archives BEFORE sending another post to the list.
189 *
190 * r0 = cp#15 control register
191 * r13 = *virtual* address to jump to upon completion
192 *
193 * other registers depend on the function called upon completion
194 */
195 .align 5
196__turn_mmu_on:
197 mov r0, r0
198 mcr p15, 0, r0, c1, c0, 0 @ write control reg
199 mrc p15, 0, r3, c0, c0, 0 @ read id reg
200 mov r3, r3
201 mov r3, r13
202 mov pc, r3
203ENDPROC(__turn_mmu_on)
204
205 114
206/* 115/*
207 * Setup the initial page tables. We only setup the barest 116 * Setup the initial page tables. We only setup the barest
@@ -213,7 +122,7 @@ ENDPROC(__turn_mmu_on)
213 * r10 = procinfo 122 * r10 = procinfo
214 * 123 *
215 * Returns: 124 * Returns:
216 * r0, r3, r6, r7 corrupted 125 * r0, r3, r5-r7 corrupted
217 * r4 = physical page table address 126 * r4 = physical page table address
218 */ 127 */
219__create_page_tables: 128__create_page_tables:
@@ -235,20 +144,30 @@ __create_page_tables:
235 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags 144 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
236 145
237 /* 146 /*
238 * Create identity mapping for first MB of kernel to 147 * Create identity mapping to cater for __enable_mmu.
239 * cater for the MMU enable. This identity mapping 148 * This identity mapping will be removed by paging_init().
240 * will be removed by paging_init(). We use our current program
241 * counter to determine corresponding section base address.
242 */ 149 */
243 mov r6, pc 150 adr r0, __enable_mmu_loc
244 mov r6, r6, lsr #20 @ start of kernel section 151 ldmia r0, {r3, r5, r6}
245 orr r3, r7, r6, lsl #20 @ flags + kernel base 152 sub r0, r0, r3 @ virt->phys offset
246 str r3, [r4, r6, lsl #2] @ identity mapping 153 add r5, r5, r0 @ phys __enable_mmu
154 add r6, r6, r0 @ phys __enable_mmu_end
155 mov r5, r5, lsr #20
156 mov r6, r6, lsr #20
157
1581: orr r3, r7, r5, lsl #20 @ flags + kernel base
159 str r3, [r4, r5, lsl #2] @ identity mapping
160 teq r5, r6
161 addne r5, r5, #1 @ next section
162 bne 1b
247 163
248 /* 164 /*
249 * Now setup the pagetables for our kernel direct 165 * Now setup the pagetables for our kernel direct
250 * mapped region. 166 * mapped region.
251 */ 167 */
168 mov r3, pc
169 mov r3, r3, lsr #20
170 orr r3, r7, r3, lsl #20
252 add r0, r4, #(KERNEL_START & 0xff000000) >> 18 171 add r0, r4, #(KERNEL_START & 0xff000000) >> 18
253 str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]! 172 str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]!
254 ldr r6, =(KERNEL_END - 1) 173 ldr r6, =(KERNEL_END - 1)
@@ -289,24 +208,35 @@ __create_page_tables:
289 str r6, [r0] 208 str r6, [r0]
290 209
291#ifdef CONFIG_DEBUG_LL 210#ifdef CONFIG_DEBUG_LL
292 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 211#ifndef CONFIG_DEBUG_ICEDCC
293 /* 212 /*
294 * Map in IO space for serial debugging. 213 * Map in IO space for serial debugging.
295 * This allows debug messages to be output 214 * This allows debug messages to be output
296 * via a serial console before paging_init. 215 * via a serial console before paging_init.
297 */ 216 */
298 ldr r3, [r8, #MACHINFO_PGOFFIO] 217 addruart r7, r3
218
219 mov r3, r3, lsr #20
220 mov r3, r3, lsl #2
221
299 add r0, r4, r3 222 add r0, r4, r3
300 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) 223 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
301 cmp r3, #0x0800 @ limit to 512MB 224 cmp r3, #0x0800 @ limit to 512MB
302 movhi r3, #0x0800 225 movhi r3, #0x0800
303 add r6, r0, r3 226 add r6, r0, r3
304 ldr r3, [r8, #MACHINFO_PHYSIO] 227 mov r3, r7, lsr #20
305 orr r3, r3, r7 228 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
229 orr r3, r7, r3, lsl #20
3061: str r3, [r0], #4 2301: str r3, [r0], #4
307 add r3, r3, #1 << 20 231 add r3, r3, #1 << 20
308 teq r0, r6 232 teq r0, r6
309 bne 1b 233 bne 1b
234
235#else /* CONFIG_DEBUG_ICEDCC */
236 /* we don't need any serial debugging mappings for ICEDCC */
237 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
238#endif /* !CONFIG_DEBUG_ICEDCC */
239
310#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) 240#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
311 /* 241 /*
312 * If we're using the NetWinder or CATS, we also need to map 242 * If we're using the NetWinder or CATS, we also need to map
@@ -332,5 +262,168 @@ __create_page_tables:
332 mov pc, lr 262 mov pc, lr
333ENDPROC(__create_page_tables) 263ENDPROC(__create_page_tables)
334 .ltorg 264 .ltorg
265__enable_mmu_loc:
266 .long .
267 .long __enable_mmu
268 .long __enable_mmu_end
269
270#if defined(CONFIG_SMP)
271 __CPUINIT
272ENTRY(secondary_startup)
273 /*
274 * Common entry point for secondary CPUs.
275 *
276 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
277 * the processor type - there is no need to check the machine type
278 * as it has already been validated by the primary processor.
279 */
280 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
281 mrc p15, 0, r9, c0, c0 @ get processor id
282 bl __lookup_processor_type
283 movs r10, r5 @ invalid processor?
284 moveq r0, #'p' @ yes, error 'p'
285 beq __error_p
286
287 /*
288 * Use the page tables supplied from __cpu_up.
289 */
290 adr r4, __secondary_data
291 ldmia r4, {r5, r7, r12} @ address to jump to after
292 sub r4, r4, r5 @ mmu has been enabled
293 ldr r4, [r7, r4] @ get secondary_data.pgdir
294 adr lr, BSYM(__enable_mmu) @ return address
295 mov r13, r12 @ __secondary_switched address
296 ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor
297 @ (return control reg)
298 THUMB( add r12, r10, #PROCINFO_INITFUNC )
299 THUMB( mov pc, r12 )
300ENDPROC(secondary_startup)
301
302 /*
303 * r6 = &secondary_data
304 */
305ENTRY(__secondary_switched)
306 ldr sp, [r7, #4] @ get secondary_data.stack
307 mov fp, #0
308 b secondary_start_kernel
309ENDPROC(__secondary_switched)
310
311 .type __secondary_data, %object
312__secondary_data:
313 .long .
314 .long secondary_data
315 .long __secondary_switched
316#endif /* defined(CONFIG_SMP) */
317
318
319
320/*
321 * Setup common bits before finally enabling the MMU. Essentially
322 * this is just loading the page table pointer and domain access
323 * registers.
324 *
325 * r0 = cp#15 control register
326 * r1 = machine ID
327 * r2 = atags pointer
328 * r4 = page table pointer
329 * r9 = processor ID
330 * r13 = *virtual* address to jump to upon completion
331 */
332__enable_mmu:
333#ifdef CONFIG_ALIGNMENT_TRAP
334 orr r0, r0, #CR_A
335#else
336 bic r0, r0, #CR_A
337#endif
338#ifdef CONFIG_CPU_DCACHE_DISABLE
339 bic r0, r0, #CR_C
340#endif
341#ifdef CONFIG_CPU_BPREDICT_DISABLE
342 bic r0, r0, #CR_Z
343#endif
344#ifdef CONFIG_CPU_ICACHE_DISABLE
345 bic r0, r0, #CR_I
346#endif
347 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
348 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
349 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
350 domain_val(DOMAIN_IO, DOMAIN_CLIENT))
351 mcr p15, 0, r5, c3, c0, 0 @ load domain access register
352 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
353 b __turn_mmu_on
354ENDPROC(__enable_mmu)
355
356/*
357 * Enable the MMU. This completely changes the structure of the visible
358 * memory space. You will not be able to trace execution through this.
359 * If you have an enquiry about this, *please* check the linux-arm-kernel
360 * mailing list archives BEFORE sending another post to the list.
361 *
362 * r0 = cp#15 control register
363 * r1 = machine ID
364 * r2 = atags pointer
365 * r9 = processor ID
366 * r13 = *virtual* address to jump to upon completion
367 *
368 * other registers depend on the function called upon completion
369 */
370 .align 5
371__turn_mmu_on:
372 mov r0, r0
373 mcr p15, 0, r0, c1, c0, 0 @ write control reg
374 mrc p15, 0, r3, c0, c0, 0 @ read id reg
375 mov r3, r3
376 mov r3, r13
377 mov pc, r3
378__enable_mmu_end:
379ENDPROC(__turn_mmu_on)
380
381
382#ifdef CONFIG_SMP_ON_UP
383__fixup_smp:
384 mov r7, #0x00070000
385 orr r6, r7, #0xff000000 @ mask 0xff070000
386 orr r7, r7, #0x41000000 @ val 0x41070000
387 and r0, r9, r6
388 teq r0, r7 @ ARM CPU and ARMv6/v7?
389 bne __fixup_smp_on_up @ no, assume UP
390
391 orr r6, r6, #0x0000ff00
392 orr r6, r6, #0x000000f0 @ mask 0xff07fff0
393 orr r7, r7, #0x0000b000
394 orr r7, r7, #0x00000020 @ val 0x4107b020
395 and r0, r9, r6
396 teq r0, r7 @ ARM 11MPCore?
397 moveq pc, lr @ yes, assume SMP
398
399 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
400 tst r0, #1 << 31
401 movne pc, lr @ bit 31 => SMP
402
403__fixup_smp_on_up:
404 adr r0, 1f
405 ldmia r0, {r3, r6, r7}
406 sub r3, r0, r3
407 add r6, r6, r3
408 add r7, r7, r3
4092: cmp r6, r7
410 ldmia r6!, {r0, r4}
411 strlo r4, [r0, r3]
412 blo 2b
413 mov pc, lr
414ENDPROC(__fixup_smp)
415
4161: .word .
417 .word __smpalt_begin
418 .word __smpalt_end
419
420 .pushsection .data
421 .globl smp_on_up
422smp_on_up:
423 ALT_SMP(.long 1)
424 ALT_UP(.long 0)
425 .popsection
426
427#endif
335 428
336#include "head-common.S" 429#include "head-common.S"
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
new file mode 100644
index 000000000000..54593b0c241b
--- /dev/null
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -0,0 +1,849 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2009, 2010 ARM Limited
16 *
17 * Author: Will Deacon <will.deacon@arm.com>
18 */
19
20/*
21 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
22 * using the CPU's debug registers.
23 */
24#define pr_fmt(fmt) "hw-breakpoint: " fmt
25
26#include <linux/errno.h>
27#include <linux/perf_event.h>
28#include <linux/hw_breakpoint.h>
29#include <linux/smp.h>
30
31#include <asm/cacheflush.h>
32#include <asm/cputype.h>
33#include <asm/current.h>
34#include <asm/hw_breakpoint.h>
35#include <asm/kdebug.h>
36#include <asm/system.h>
37#include <asm/traps.h>
38
39/* Breakpoint currently in use for each BRP. */
40static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
41
42/* Watchpoint currently in use for each WRP. */
43static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
44
45/* Number of BRP/WRP registers on this CPU. */
46static int core_num_brps;
47static int core_num_wrps;
48
49/* Debug architecture version. */
50static u8 debug_arch;
51
52/* Maximum supported watchpoint length. */
53static u8 max_watchpoint_len;
54
55/* Determine number of BRP registers available. */
56static int get_num_brps(void)
57{
58 u32 didr;
59 ARM_DBG_READ(c0, 0, didr);
60 return ((didr >> 24) & 0xf) + 1;
61}
62
63/* Determine number of WRP registers available. */
64static int get_num_wrps(void)
65{
66 /*
67 * FIXME: When a watchpoint fires, the only way to work out which
68 * watchpoint it was is by disassembling the faulting instruction
69 * and working out the address of the memory access.
70 *
71 * Furthermore, we can only do this if the watchpoint was precise
72 * since imprecise watchpoints prevent us from calculating register
73 * based addresses.
74 *
75 * For the time being, we only report 1 watchpoint register so we
76 * always know which watchpoint fired. In the future we can either
77 * add a disassembler and address generation emulator, or we can
78 * insert a check to see if the DFAR is set on watchpoint exception
79 * entry [the ARM ARM states that the DFAR is UNKNOWN, but
80 * experience shows that it is set on some implementations].
81 */
82
83#if 0
84 u32 didr, wrps;
85 ARM_DBG_READ(c0, 0, didr);
86 return ((didr >> 28) & 0xf) + 1;
87#endif
88
89 return 1;
90}
91
92int hw_breakpoint_slots(int type)
93{
94 /*
95 * We can be called early, so don't rely on
96 * our static variables being initialised.
97 */
98 switch (type) {
99 case TYPE_INST:
100 return get_num_brps();
101 case TYPE_DATA:
102 return get_num_wrps();
103 default:
104 pr_warning("unknown slot type: %d\n", type);
105 return 0;
106 }
107}
108
109/* Determine debug architecture. */
110static u8 get_debug_arch(void)
111{
112 u32 didr;
113
114 /* Do we implement the extended CPUID interface? */
115 if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
116 pr_warning("CPUID feature registers not supported. "
117 "Assuming v6 debug is present.\n");
118 return ARM_DEBUG_ARCH_V6;
119 }
120
121 ARM_DBG_READ(c0, 0, didr);
122 return (didr >> 16) & 0xf;
123}
124
125/* Does this core support mismatch breakpoints? */
126static int core_has_mismatch_bps(void)
127{
128 return debug_arch >= ARM_DEBUG_ARCH_V7_ECP14 && core_num_brps > 1;
129}
130
131u8 arch_get_debug_arch(void)
132{
133 return debug_arch;
134}
135
136#define READ_WB_REG_CASE(OP2, M, VAL) \
137 case ((OP2 << 4) + M): \
138 ARM_DBG_READ(c ## M, OP2, VAL); \
139 break
140
141#define WRITE_WB_REG_CASE(OP2, M, VAL) \
142 case ((OP2 << 4) + M): \
143 ARM_DBG_WRITE(c ## M, OP2, VAL);\
144 break
145
146#define GEN_READ_WB_REG_CASES(OP2, VAL) \
147 READ_WB_REG_CASE(OP2, 0, VAL); \
148 READ_WB_REG_CASE(OP2, 1, VAL); \
149 READ_WB_REG_CASE(OP2, 2, VAL); \
150 READ_WB_REG_CASE(OP2, 3, VAL); \
151 READ_WB_REG_CASE(OP2, 4, VAL); \
152 READ_WB_REG_CASE(OP2, 5, VAL); \
153 READ_WB_REG_CASE(OP2, 6, VAL); \
154 READ_WB_REG_CASE(OP2, 7, VAL); \
155 READ_WB_REG_CASE(OP2, 8, VAL); \
156 READ_WB_REG_CASE(OP2, 9, VAL); \
157 READ_WB_REG_CASE(OP2, 10, VAL); \
158 READ_WB_REG_CASE(OP2, 11, VAL); \
159 READ_WB_REG_CASE(OP2, 12, VAL); \
160 READ_WB_REG_CASE(OP2, 13, VAL); \
161 READ_WB_REG_CASE(OP2, 14, VAL); \
162 READ_WB_REG_CASE(OP2, 15, VAL)
163
164#define GEN_WRITE_WB_REG_CASES(OP2, VAL) \
165 WRITE_WB_REG_CASE(OP2, 0, VAL); \
166 WRITE_WB_REG_CASE(OP2, 1, VAL); \
167 WRITE_WB_REG_CASE(OP2, 2, VAL); \
168 WRITE_WB_REG_CASE(OP2, 3, VAL); \
169 WRITE_WB_REG_CASE(OP2, 4, VAL); \
170 WRITE_WB_REG_CASE(OP2, 5, VAL); \
171 WRITE_WB_REG_CASE(OP2, 6, VAL); \
172 WRITE_WB_REG_CASE(OP2, 7, VAL); \
173 WRITE_WB_REG_CASE(OP2, 8, VAL); \
174 WRITE_WB_REG_CASE(OP2, 9, VAL); \
175 WRITE_WB_REG_CASE(OP2, 10, VAL); \
176 WRITE_WB_REG_CASE(OP2, 11, VAL); \
177 WRITE_WB_REG_CASE(OP2, 12, VAL); \
178 WRITE_WB_REG_CASE(OP2, 13, VAL); \
179 WRITE_WB_REG_CASE(OP2, 14, VAL); \
180 WRITE_WB_REG_CASE(OP2, 15, VAL)
181
182static u32 read_wb_reg(int n)
183{
184 u32 val = 0;
185
186 switch (n) {
187 GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val);
188 GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val);
189 GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val);
190 GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val);
191 default:
192 pr_warning("attempt to read from unknown breakpoint "
193 "register %d\n", n);
194 }
195
196 return val;
197}
198
199static void write_wb_reg(int n, u32 val)
200{
201 switch (n) {
202 GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val);
203 GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val);
204 GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val);
205 GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val);
206 default:
207 pr_warning("attempt to write to unknown breakpoint "
208 "register %d\n", n);
209 }
210 isb();
211}
212
213/*
214 * In order to access the breakpoint/watchpoint control registers,
215 * we must be running in debug monitor mode. Unfortunately, we can
216 * be put into halting debug mode at any time by an external debugger
217 * but there is nothing we can do to prevent that.
218 */
219static int enable_monitor_mode(void)
220{
221 u32 dscr;
222 int ret = 0;
223
224 ARM_DBG_READ(c1, 0, dscr);
225
226 /* Ensure that halting mode is disabled. */
227 if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN, "halting debug mode enabled."
228 "Unable to access hardware resources.")) {
229 ret = -EPERM;
230 goto out;
231 }
232
233 /* Write to the corresponding DSCR. */
234 switch (debug_arch) {
235 case ARM_DEBUG_ARCH_V6:
236 case ARM_DEBUG_ARCH_V6_1:
237 ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN));
238 break;
239 case ARM_DEBUG_ARCH_V7_ECP14:
240 ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN));
241 break;
242 default:
243 ret = -ENODEV;
244 goto out;
245 }
246
247 /* Check that the write made it through. */
248 ARM_DBG_READ(c1, 0, dscr);
249 if (WARN_ONCE(!(dscr & ARM_DSCR_MDBGEN),
250 "failed to enable monitor mode.")) {
251 ret = -EPERM;
252 }
253
254out:
255 return ret;
256}
257
258/*
259 * Check if 8-bit byte-address select is available.
260 * This clobbers WRP 0.
261 */
262static u8 get_max_wp_len(void)
263{
264 u32 ctrl_reg;
265 struct arch_hw_breakpoint_ctrl ctrl;
266 u8 size = 4;
267
268 if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14)
269 goto out;
270
271 if (enable_monitor_mode())
272 goto out;
273
274 memset(&ctrl, 0, sizeof(ctrl));
275 ctrl.len = ARM_BREAKPOINT_LEN_8;
276 ctrl_reg = encode_ctrl_reg(ctrl);
277
278 write_wb_reg(ARM_BASE_WVR, 0);
279 write_wb_reg(ARM_BASE_WCR, ctrl_reg);
280 if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg)
281 size = 8;
282
283out:
284 return size;
285}
286
287u8 arch_get_max_wp_len(void)
288{
289 return max_watchpoint_len;
290}
291
292/*
293 * Handler for reactivating a suspended watchpoint when the single
294 * step `mismatch' breakpoint is triggered.
295 */
296static void wp_single_step_handler(struct perf_event *bp, int unused,
297 struct perf_sample_data *data,
298 struct pt_regs *regs)
299{
300 perf_event_enable(counter_arch_bp(bp)->suspended_wp);
301 unregister_hw_breakpoint(bp);
302}
303
304static int bp_is_single_step(struct perf_event *bp)
305{
306 return bp->overflow_handler == wp_single_step_handler;
307}
308
309/*
310 * Install a perf counter breakpoint.
311 */
312int arch_install_hw_breakpoint(struct perf_event *bp)
313{
314 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
315 struct perf_event **slot, **slots;
316 int i, max_slots, ctrl_base, val_base, ret = 0;
317
318 /* Ensure that we are in monitor mode and halting mode is disabled. */
319 ret = enable_monitor_mode();
320 if (ret)
321 goto out;
322
323 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
324 /* Breakpoint */
325 ctrl_base = ARM_BASE_BCR;
326 val_base = ARM_BASE_BVR;
327 slots = __get_cpu_var(bp_on_reg);
328 max_slots = core_num_brps - 1;
329
330 if (bp_is_single_step(bp)) {
331 info->ctrl.mismatch = 1;
332 i = max_slots;
333 slots[i] = bp;
334 goto setup;
335 }
336 } else {
337 /* Watchpoint */
338 ctrl_base = ARM_BASE_WCR;
339 val_base = ARM_BASE_WVR;
340 slots = __get_cpu_var(wp_on_reg);
341 max_slots = core_num_wrps;
342 }
343
344 for (i = 0; i < max_slots; ++i) {
345 slot = &slots[i];
346
347 if (!*slot) {
348 *slot = bp;
349 break;
350 }
351 }
352
353 if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot")) {
354 ret = -EBUSY;
355 goto out;
356 }
357
358setup:
359 /* Setup the address register. */
360 write_wb_reg(val_base + i, info->address);
361
362 /* Setup the control register. */
363 write_wb_reg(ctrl_base + i, encode_ctrl_reg(info->ctrl) | 0x1);
364
365out:
366 return ret;
367}
368
369void arch_uninstall_hw_breakpoint(struct perf_event *bp)
370{
371 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
372 struct perf_event **slot, **slots;
373 int i, max_slots, base;
374
375 if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
376 /* Breakpoint */
377 base = ARM_BASE_BCR;
378 slots = __get_cpu_var(bp_on_reg);
379 max_slots = core_num_brps - 1;
380
381 if (bp_is_single_step(bp)) {
382 i = max_slots;
383 slots[i] = NULL;
384 goto reset;
385 }
386 } else {
387 /* Watchpoint */
388 base = ARM_BASE_WCR;
389 slots = __get_cpu_var(wp_on_reg);
390 max_slots = core_num_wrps;
391 }
392
393 /* Remove the breakpoint. */
394 for (i = 0; i < max_slots; ++i) {
395 slot = &slots[i];
396
397 if (*slot == bp) {
398 *slot = NULL;
399 break;
400 }
401 }
402
403 if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot"))
404 return;
405
406reset:
407 /* Reset the control register. */
408 write_wb_reg(base + i, 0);
409}
410
411static int get_hbp_len(u8 hbp_len)
412{
413 unsigned int len_in_bytes = 0;
414
415 switch (hbp_len) {
416 case ARM_BREAKPOINT_LEN_1:
417 len_in_bytes = 1;
418 break;
419 case ARM_BREAKPOINT_LEN_2:
420 len_in_bytes = 2;
421 break;
422 case ARM_BREAKPOINT_LEN_4:
423 len_in_bytes = 4;
424 break;
425 case ARM_BREAKPOINT_LEN_8:
426 len_in_bytes = 8;
427 break;
428 }
429
430 return len_in_bytes;
431}
432
433/*
434 * Check whether bp virtual address is in kernel space.
435 */
436int arch_check_bp_in_kernelspace(struct perf_event *bp)
437{
438 unsigned int len;
439 unsigned long va;
440 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
441
442 va = info->address;
443 len = get_hbp_len(info->ctrl.len);
444
445 return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
446}
447
448/*
449 * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
450 * Hopefully this will disappear when ptrace can bypass the conversion
451 * to generic breakpoint descriptions.
452 */
453int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
454 int *gen_len, int *gen_type)
455{
456 /* Type */
457 switch (ctrl.type) {
458 case ARM_BREAKPOINT_EXECUTE:
459 *gen_type = HW_BREAKPOINT_X;
460 break;
461 case ARM_BREAKPOINT_LOAD:
462 *gen_type = HW_BREAKPOINT_R;
463 break;
464 case ARM_BREAKPOINT_STORE:
465 *gen_type = HW_BREAKPOINT_W;
466 break;
467 case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
468 *gen_type = HW_BREAKPOINT_RW;
469 break;
470 default:
471 return -EINVAL;
472 }
473
474 /* Len */
475 switch (ctrl.len) {
476 case ARM_BREAKPOINT_LEN_1:
477 *gen_len = HW_BREAKPOINT_LEN_1;
478 break;
479 case ARM_BREAKPOINT_LEN_2:
480 *gen_len = HW_BREAKPOINT_LEN_2;
481 break;
482 case ARM_BREAKPOINT_LEN_4:
483 *gen_len = HW_BREAKPOINT_LEN_4;
484 break;
485 case ARM_BREAKPOINT_LEN_8:
486 *gen_len = HW_BREAKPOINT_LEN_8;
487 break;
488 default:
489 return -EINVAL;
490 }
491
492 return 0;
493}
494
495/*
496 * Construct an arch_hw_breakpoint from a perf_event.
497 */
498static int arch_build_bp_info(struct perf_event *bp)
499{
500 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
501
502 /* Type */
503 switch (bp->attr.bp_type) {
504 case HW_BREAKPOINT_X:
505 info->ctrl.type = ARM_BREAKPOINT_EXECUTE;
506 break;
507 case HW_BREAKPOINT_R:
508 info->ctrl.type = ARM_BREAKPOINT_LOAD;
509 break;
510 case HW_BREAKPOINT_W:
511 info->ctrl.type = ARM_BREAKPOINT_STORE;
512 break;
513 case HW_BREAKPOINT_RW:
514 info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
515 break;
516 default:
517 return -EINVAL;
518 }
519
520 /* Len */
521 switch (bp->attr.bp_len) {
522 case HW_BREAKPOINT_LEN_1:
523 info->ctrl.len = ARM_BREAKPOINT_LEN_1;
524 break;
525 case HW_BREAKPOINT_LEN_2:
526 info->ctrl.len = ARM_BREAKPOINT_LEN_2;
527 break;
528 case HW_BREAKPOINT_LEN_4:
529 info->ctrl.len = ARM_BREAKPOINT_LEN_4;
530 break;
531 case HW_BREAKPOINT_LEN_8:
532 info->ctrl.len = ARM_BREAKPOINT_LEN_8;
533 if ((info->ctrl.type != ARM_BREAKPOINT_EXECUTE)
534 && max_watchpoint_len >= 8)
535 break;
536 default:
537 return -EINVAL;
538 }
539
540 /* Address */
541 info->address = bp->attr.bp_addr;
542
543 /* Privilege */
544 info->ctrl.privilege = ARM_BREAKPOINT_USER;
545 if (arch_check_bp_in_kernelspace(bp) && !bp_is_single_step(bp))
546 info->ctrl.privilege |= ARM_BREAKPOINT_PRIV;
547
548 /* Enabled? */
549 info->ctrl.enabled = !bp->attr.disabled;
550
551 /* Mismatch */
552 info->ctrl.mismatch = 0;
553
554 return 0;
555}
556
557/*
558 * Validate the arch-specific HW Breakpoint register settings.
559 */
560int arch_validate_hwbkpt_settings(struct perf_event *bp)
561{
562 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
563 int ret = 0;
564 u32 bytelen, max_len, offset, alignment_mask = 0x3;
565
566 /* Build the arch_hw_breakpoint. */
567 ret = arch_build_bp_info(bp);
568 if (ret)
569 goto out;
570
571 /* Check address alignment. */
572 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
573 alignment_mask = 0x7;
574 if (info->address & alignment_mask) {
575 /*
576 * Try to fix the alignment. This may result in a length
577 * that is too large, so we must check for that.
578 */
579 bytelen = get_hbp_len(info->ctrl.len);
580 max_len = info->ctrl.type == ARM_BREAKPOINT_EXECUTE ? 4 :
581 max_watchpoint_len;
582
583 if (max_len >= 8)
584 offset = info->address & 0x7;
585 else
586 offset = info->address & 0x3;
587
588 if (bytelen > (1 << ((max_len - (offset + 1)) >> 1))) {
589 ret = -EFBIG;
590 goto out;
591 }
592
593 info->ctrl.len <<= offset;
594 info->address &= ~offset;
595
596 pr_debug("breakpoint alignment fixup: length = 0x%x, "
597 "address = 0x%x\n", info->ctrl.len, info->address);
598 }
599
600 /*
601 * Currently we rely on an overflow handler to take
602 * care of single-stepping the breakpoint when it fires.
603 * In the case of userspace breakpoints on a core with V7 debug,
604 * we can use the mismatch feature as a poor-man's hardware single-step.
605 */
606 if (WARN_ONCE(!bp->overflow_handler &&
607 (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_bps()),
608 "overflow handler required but none found")) {
609 ret = -EINVAL;
610 goto out;
611 }
612out:
613 return ret;
614}
615
616static void update_mismatch_flag(int idx, int flag)
617{
618 struct perf_event *bp = __get_cpu_var(bp_on_reg[idx]);
619 struct arch_hw_breakpoint *info;
620
621 if (bp == NULL)
622 return;
623
624 info = counter_arch_bp(bp);
625
626 /* Update the mismatch field to enter/exit `single-step' mode */
627 if (!bp->overflow_handler && info->ctrl.mismatch != flag) {
628 info->ctrl.mismatch = flag;
629 write_wb_reg(ARM_BASE_BCR + idx, encode_ctrl_reg(info->ctrl) | 0x1);
630 }
631}
632
633static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs)
634{
635 int i;
636 struct perf_event *bp, **slots = __get_cpu_var(wp_on_reg);
637 struct arch_hw_breakpoint *info;
638 struct perf_event_attr attr;
639
640 /* Without a disassembler, we can only handle 1 watchpoint. */
641 BUG_ON(core_num_wrps > 1);
642
643 hw_breakpoint_init(&attr);
644 attr.bp_addr = regs->ARM_pc & ~0x3;
645 attr.bp_len = HW_BREAKPOINT_LEN_4;
646 attr.bp_type = HW_BREAKPOINT_X;
647
648 for (i = 0; i < core_num_wrps; ++i) {
649 rcu_read_lock();
650
651 if (slots[i] == NULL) {
652 rcu_read_unlock();
653 continue;
654 }
655
656 /*
657 * The DFAR is an unknown value. Since we only allow a
658 * single watchpoint, we can set the trigger to the lowest
659 * possible faulting address.
660 */
661 info = counter_arch_bp(slots[i]);
662 info->trigger = slots[i]->attr.bp_addr;
663 pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
664 perf_bp_event(slots[i], regs);
665
666 /*
667 * If no overflow handler is present, insert a temporary
668 * mismatch breakpoint so we can single-step over the
669 * watchpoint trigger.
670 */
671 if (!slots[i]->overflow_handler) {
672 bp = register_user_hw_breakpoint(&attr,
673 wp_single_step_handler,
674 current);
675 counter_arch_bp(bp)->suspended_wp = slots[i];
676 perf_event_disable(slots[i]);
677 }
678
679 rcu_read_unlock();
680 }
681}
682
683static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs)
684{
685 int i;
686 int mismatch;
687 u32 ctrl_reg, val, addr;
688 struct perf_event *bp, **slots = __get_cpu_var(bp_on_reg);
689 struct arch_hw_breakpoint *info;
690 struct arch_hw_breakpoint_ctrl ctrl;
691
692 /* The exception entry code places the amended lr in the PC. */
693 addr = regs->ARM_pc;
694
695 for (i = 0; i < core_num_brps; ++i) {
696 rcu_read_lock();
697
698 bp = slots[i];
699
700 if (bp == NULL) {
701 rcu_read_unlock();
702 continue;
703 }
704
705 mismatch = 0;
706
707 /* Check if the breakpoint value matches. */
708 val = read_wb_reg(ARM_BASE_BVR + i);
709 if (val != (addr & ~0x3))
710 goto unlock;
711
712 /* Possible match, check the byte address select to confirm. */
713 ctrl_reg = read_wb_reg(ARM_BASE_BCR + i);
714 decode_ctrl_reg(ctrl_reg, &ctrl);
715 if ((1 << (addr & 0x3)) & ctrl.len) {
716 mismatch = 1;
717 info = counter_arch_bp(bp);
718 info->trigger = addr;
719 }
720
721unlock:
722 if ((mismatch && !info->ctrl.mismatch) || bp_is_single_step(bp)) {
723 pr_debug("breakpoint fired: address = 0x%x\n", addr);
724 perf_bp_event(bp, regs);
725 }
726
727 update_mismatch_flag(i, mismatch);
728 rcu_read_unlock();
729 }
730}
731
732/*
733 * Called from either the Data Abort Handler [watchpoint] or the
734 * Prefetch Abort Handler [breakpoint].
735 */
736static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
737 struct pt_regs *regs)
738{
739 int ret = 1; /* Unhandled fault. */
740 u32 dscr;
741
742 /* We only handle watchpoints and hardware breakpoints. */
743 ARM_DBG_READ(c1, 0, dscr);
744
745 /* Perform perf callbacks. */
746 switch (ARM_DSCR_MOE(dscr)) {
747 case ARM_ENTRY_BREAKPOINT:
748 breakpoint_handler(addr, regs);
749 break;
750 case ARM_ENTRY_ASYNC_WATCHPOINT:
751 WARN_ON("Asynchronous watchpoint exception taken. "
752 "Debugging results may be unreliable");
753 case ARM_ENTRY_SYNC_WATCHPOINT:
754 watchpoint_handler(addr, regs);
755 break;
756 default:
757 goto out;
758 }
759
760 ret = 0;
761out:
762 return ret;
763}
764
765/*
766 * One-time initialisation.
767 */
768static void __init reset_ctrl_regs(void *unused)
769{
770 int i;
771
772 if (enable_monitor_mode())
773 return;
774
775 for (i = 0; i < core_num_brps; ++i) {
776 write_wb_reg(ARM_BASE_BCR + i, 0UL);
777 write_wb_reg(ARM_BASE_BVR + i, 0UL);
778 }
779
780 for (i = 0; i < core_num_wrps; ++i) {
781 write_wb_reg(ARM_BASE_WCR + i, 0UL);
782 write_wb_reg(ARM_BASE_WVR + i, 0UL);
783 }
784}
785
786static int __init arch_hw_breakpoint_init(void)
787{
788 int ret = 0;
789 u32 dscr;
790
791 debug_arch = get_debug_arch();
792
793 if (debug_arch > ARM_DEBUG_ARCH_V7_ECP14) {
794 pr_info("debug architecture 0x%x unsupported.\n", debug_arch);
795 ret = -ENODEV;
796 goto out;
797 }
798
799 /* Determine how many BRPs/WRPs are available. */
800 core_num_brps = get_num_brps();
801 core_num_wrps = get_num_wrps();
802
803 pr_info("found %d breakpoint and %d watchpoint registers.\n",
804 core_num_brps, core_num_wrps);
805
806 if (core_has_mismatch_bps())
807 pr_info("1 breakpoint reserved for watchpoint single-step.\n");
808
809 ARM_DBG_READ(c1, 0, dscr);
810 if (dscr & ARM_DSCR_HDBGEN) {
811 pr_warning("halting debug mode enabled. Assuming maximum "
812 "watchpoint size of 4 bytes.");
813 } else {
814 /* Work out the maximum supported watchpoint length. */
815 max_watchpoint_len = get_max_wp_len();
816 pr_info("maximum watchpoint size is %u bytes.\n",
817 max_watchpoint_len);
818
819 /*
820 * Reset the breakpoint resources. We assume that a halting
821 * debugger will leave the world in a nice state for us.
822 */
823 smp_call_function(reset_ctrl_regs, NULL, 1);
824 reset_ctrl_regs(NULL);
825 }
826
827 /* Register debug fault handler. */
828 hook_fault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT,
829 "watchpoint debug exception");
830 hook_ifault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT,
831 "breakpoint debug exception");
832
833out:
834 return ret;
835}
836arch_initcall(arch_hw_breakpoint_init);
837
838void hw_breakpoint_pmu_read(struct perf_event *bp)
839{
840}
841
842/*
843 * Dummy function to register with die_notifier.
844 */
845int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
846 unsigned long val, void *data)
847{
848 return NOTIFY_DONE;
849}
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index 6b4605893f1e..d9bd786ce23d 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -69,20 +69,31 @@ int module_frob_arch_sections(Elf_Ehdr *hdr,
69{ 69{
70#ifdef CONFIG_ARM_UNWIND 70#ifdef CONFIG_ARM_UNWIND
71 Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum; 71 Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum;
72 struct arm_unwind_mapping *maps = mod->arch.map;
72 73
73 for (s = sechdrs; s < sechdrs_end; s++) { 74 for (s = sechdrs; s < sechdrs_end; s++) {
74 if (strcmp(".ARM.exidx.init.text", secstrings + s->sh_name) == 0) 75 char const *secname = secstrings + s->sh_name;
75 mod->arch.unw_sec_init = s; 76
76 else if (strcmp(".ARM.exidx.devinit.text", secstrings + s->sh_name) == 0) 77 if (strcmp(".ARM.exidx.init.text", secname) == 0)
77 mod->arch.unw_sec_devinit = s; 78 maps[ARM_SEC_INIT].unw_sec = s;
78 else if (strcmp(".ARM.exidx", secstrings + s->sh_name) == 0) 79 else if (strcmp(".ARM.exidx.devinit.text", secname) == 0)
79 mod->arch.unw_sec_core = s; 80 maps[ARM_SEC_DEVINIT].unw_sec = s;
80 else if (strcmp(".init.text", secstrings + s->sh_name) == 0) 81 else if (strcmp(".ARM.exidx", secname) == 0)
81 mod->arch.sec_init_text = s; 82 maps[ARM_SEC_CORE].unw_sec = s;
82 else if (strcmp(".devinit.text", secstrings + s->sh_name) == 0) 83 else if (strcmp(".ARM.exidx.exit.text", secname) == 0)
83 mod->arch.sec_devinit_text = s; 84 maps[ARM_SEC_EXIT].unw_sec = s;
84 else if (strcmp(".text", secstrings + s->sh_name) == 0) 85 else if (strcmp(".ARM.exidx.devexit.text", secname) == 0)
85 mod->arch.sec_core_text = s; 86 maps[ARM_SEC_DEVEXIT].unw_sec = s;
87 else if (strcmp(".init.text", secname) == 0)
88 maps[ARM_SEC_INIT].sec_text = s;
89 else if (strcmp(".devinit.text", secname) == 0)
90 maps[ARM_SEC_DEVINIT].sec_text = s;
91 else if (strcmp(".text", secname) == 0)
92 maps[ARM_SEC_CORE].sec_text = s;
93 else if (strcmp(".exit.text", secname) == 0)
94 maps[ARM_SEC_EXIT].sec_text = s;
95 else if (strcmp(".devexit.text", secname) == 0)
96 maps[ARM_SEC_DEVEXIT].sec_text = s;
86 } 97 }
87#endif 98#endif
88 return 0; 99 return 0;
@@ -292,31 +303,22 @@ apply_relocate_add(Elf32_Shdr *sechdrs, const char *strtab,
292#ifdef CONFIG_ARM_UNWIND 303#ifdef CONFIG_ARM_UNWIND
293static void register_unwind_tables(struct module *mod) 304static void register_unwind_tables(struct module *mod)
294{ 305{
295 if (mod->arch.unw_sec_init && mod->arch.sec_init_text) 306 int i;
296 mod->arch.unwind_init = 307 for (i = 0; i < ARM_SEC_MAX; ++i) {
297 unwind_table_add(mod->arch.unw_sec_init->sh_addr, 308 struct arm_unwind_mapping *map = &mod->arch.map[i];
298 mod->arch.unw_sec_init->sh_size, 309 if (map->unw_sec && map->sec_text)
299 mod->arch.sec_init_text->sh_addr, 310 map->unwind = unwind_table_add(map->unw_sec->sh_addr,
300 mod->arch.sec_init_text->sh_size); 311 map->unw_sec->sh_size,
301 if (mod->arch.unw_sec_devinit && mod->arch.sec_devinit_text) 312 map->sec_text->sh_addr,
302 mod->arch.unwind_devinit = 313 map->sec_text->sh_size);
303 unwind_table_add(mod->arch.unw_sec_devinit->sh_addr, 314 }
304 mod->arch.unw_sec_devinit->sh_size,
305 mod->arch.sec_devinit_text->sh_addr,
306 mod->arch.sec_devinit_text->sh_size);
307 if (mod->arch.unw_sec_core && mod->arch.sec_core_text)
308 mod->arch.unwind_core =
309 unwind_table_add(mod->arch.unw_sec_core->sh_addr,
310 mod->arch.unw_sec_core->sh_size,
311 mod->arch.sec_core_text->sh_addr,
312 mod->arch.sec_core_text->sh_size);
313} 315}
314 316
315static void unregister_unwind_tables(struct module *mod) 317static void unregister_unwind_tables(struct module *mod)
316{ 318{
317 unwind_table_del(mod->arch.unwind_init); 319 int i = ARM_SEC_MAX;
318 unwind_table_del(mod->arch.unwind_devinit); 320 while (--i >= 0)
319 unwind_table_del(mod->arch.unwind_core); 321 unwind_table_del(mod->arch.map[i].unwind);
320} 322}
321#else 323#else
322static inline void register_unwind_tables(struct module *mod) { } 324static inline void register_unwind_tables(struct module *mod) { }
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 401e38be1f78..e76fcaadce03 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -29,6 +29,7 @@
29#include <linux/utsname.h> 29#include <linux/utsname.h>
30#include <linux/uaccess.h> 30#include <linux/uaccess.h>
31#include <linux/random.h> 31#include <linux/random.h>
32#include <linux/hw_breakpoint.h>
32 33
33#include <asm/cacheflush.h> 34#include <asm/cacheflush.h>
34#include <asm/leds.h> 35#include <asm/leds.h>
@@ -135,6 +136,25 @@ EXPORT_SYMBOL(pm_power_off);
135void (*arm_pm_restart)(char str, const char *cmd) = arm_machine_restart; 136void (*arm_pm_restart)(char str, const char *cmd) = arm_machine_restart;
136EXPORT_SYMBOL_GPL(arm_pm_restart); 137EXPORT_SYMBOL_GPL(arm_pm_restart);
137 138
139static void do_nothing(void *unused)
140{
141}
142
143/*
144 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
145 * pm_idle and update to new pm_idle value. Required while changing pm_idle
146 * handler on SMP systems.
147 *
148 * Caller must have changed pm_idle to the new value before the call. Old
149 * pm_idle value will not be used by any CPU after the return of this function.
150 */
151void cpu_idle_wait(void)
152{
153 smp_mb();
154 /* kick all the CPUs so that they exit out of pm_idle */
155 smp_call_function(do_nothing, NULL, 1);
156}
157EXPORT_SYMBOL_GPL(cpu_idle_wait);
138 158
139/* 159/*
140 * This is our default idle handler. We need to disable 160 * This is our default idle handler. We need to disable
@@ -317,6 +337,8 @@ void flush_thread(void)
317 struct thread_info *thread = current_thread_info(); 337 struct thread_info *thread = current_thread_info();
318 struct task_struct *tsk = current; 338 struct task_struct *tsk = current;
319 339
340 flush_ptrace_hw_breakpoint(tsk);
341
320 memset(thread->used_cp, 0, sizeof(thread->used_cp)); 342 memset(thread->used_cp, 0, sizeof(thread->used_cp));
321 memset(&tsk->thread.debug, 0, sizeof(struct debug_info)); 343 memset(&tsk->thread.debug, 0, sizeof(struct debug_info));
322 memset(&thread->fpstate, 0, sizeof(union fp_state)); 344 memset(&thread->fpstate, 0, sizeof(union fp_state));
@@ -345,6 +367,8 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
345 thread->cpu_context.sp = (unsigned long)childregs; 367 thread->cpu_context.sp = (unsigned long)childregs;
346 thread->cpu_context.pc = (unsigned long)ret_from_fork; 368 thread->cpu_context.pc = (unsigned long)ret_from_fork;
347 369
370 clear_ptrace_hw_breakpoint(p);
371
348 if (clone_flags & CLONE_SETTLS) 372 if (clone_flags & CLONE_SETTLS)
349 thread->tp_value = regs->ARM_r3; 373 thread->tp_value = regs->ARM_r3;
350 374
@@ -458,3 +482,24 @@ unsigned long arch_randomize_brk(struct mm_struct *mm)
458 unsigned long range_end = mm->brk + 0x02000000; 482 unsigned long range_end = mm->brk + 0x02000000;
459 return randomize_range(mm->brk, range_end, 0) ? : mm->brk; 483 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
460} 484}
485
486/*
487 * The vectors page is always readable from user space for the
488 * atomic helpers and the signal restart code. Let's declare a mapping
489 * for it so it is visible through ptrace and /proc/<pid>/mem.
490 */
491
492int vectors_user_mapping(void)
493{
494 struct mm_struct *mm = current->mm;
495 return install_special_mapping(mm, 0xffff0000, PAGE_SIZE,
496 VM_READ | VM_EXEC |
497 VM_MAYREAD | VM_MAYEXEC |
498 VM_ALWAYSDUMP | VM_RESERVED,
499 NULL);
500}
501
502const char *arch_vma_name(struct vm_area_struct *vma)
503{
504 return (vma->vm_start == 0xffff0000) ? "[vectors]" : NULL;
505}
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index f99d489822d5..e0cb6370ed14 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -19,6 +19,8 @@
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/signal.h> 20#include <linux/signal.h>
21#include <linux/uaccess.h> 21#include <linux/uaccess.h>
22#include <linux/perf_event.h>
23#include <linux/hw_breakpoint.h>
22 24
23#include <asm/pgtable.h> 25#include <asm/pgtable.h>
24#include <asm/system.h> 26#include <asm/system.h>
@@ -847,6 +849,232 @@ static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data)
847} 849}
848#endif 850#endif
849 851
852#ifdef CONFIG_HAVE_HW_BREAKPOINT
853/*
854 * Convert a virtual register number into an index for a thread_info
855 * breakpoint array. Breakpoints are identified using positive numbers
856 * whilst watchpoints are negative. The registers are laid out as pairs
857 * of (address, control), each pair mapping to a unique hw_breakpoint struct.
858 * Register 0 is reserved for describing resource information.
859 */
860static int ptrace_hbp_num_to_idx(long num)
861{
862 if (num < 0)
863 num = (ARM_MAX_BRP << 1) - num;
864 return (num - 1) >> 1;
865}
866
867/*
868 * Returns the virtual register number for the address of the
869 * breakpoint at index idx.
870 */
871static long ptrace_hbp_idx_to_num(int idx)
872{
873 long mid = ARM_MAX_BRP << 1;
874 long num = (idx << 1) + 1;
875 return num > mid ? mid - num : num;
876}
877
878/*
879 * Handle hitting a HW-breakpoint.
880 */
881static void ptrace_hbptriggered(struct perf_event *bp, int unused,
882 struct perf_sample_data *data,
883 struct pt_regs *regs)
884{
885 struct arch_hw_breakpoint *bkpt = counter_arch_bp(bp);
886 long num;
887 int i;
888 siginfo_t info;
889
890 for (i = 0; i < ARM_MAX_HBP_SLOTS; ++i)
891 if (current->thread.debug.hbp[i] == bp)
892 break;
893
894 num = (i == ARM_MAX_HBP_SLOTS) ? 0 : ptrace_hbp_idx_to_num(i);
895
896 info.si_signo = SIGTRAP;
897 info.si_errno = (int)num;
898 info.si_code = TRAP_HWBKPT;
899 info.si_addr = (void __user *)(bkpt->trigger);
900
901 force_sig_info(SIGTRAP, &info, current);
902}
903
904/*
905 * Set ptrace breakpoint pointers to zero for this task.
906 * This is required in order to prevent child processes from unregistering
907 * breakpoints held by their parent.
908 */
909void clear_ptrace_hw_breakpoint(struct task_struct *tsk)
910{
911 memset(tsk->thread.debug.hbp, 0, sizeof(tsk->thread.debug.hbp));
912}
913
914/*
915 * Unregister breakpoints from this task and reset the pointers in
916 * the thread_struct.
917 */
918void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
919{
920 int i;
921 struct thread_struct *t = &tsk->thread;
922
923 for (i = 0; i < ARM_MAX_HBP_SLOTS; i++) {
924 if (t->debug.hbp[i]) {
925 unregister_hw_breakpoint(t->debug.hbp[i]);
926 t->debug.hbp[i] = NULL;
927 }
928 }
929}
930
931static u32 ptrace_get_hbp_resource_info(void)
932{
933 u8 num_brps, num_wrps, debug_arch, wp_len;
934 u32 reg = 0;
935
936 num_brps = hw_breakpoint_slots(TYPE_INST);
937 num_wrps = hw_breakpoint_slots(TYPE_DATA);
938 debug_arch = arch_get_debug_arch();
939 wp_len = arch_get_max_wp_len();
940
941 reg |= debug_arch;
942 reg <<= 8;
943 reg |= wp_len;
944 reg <<= 8;
945 reg |= num_wrps;
946 reg <<= 8;
947 reg |= num_brps;
948
949 return reg;
950}
951
952static struct perf_event *ptrace_hbp_create(struct task_struct *tsk, int type)
953{
954 struct perf_event_attr attr;
955
956 ptrace_breakpoint_init(&attr);
957
958 /* Initialise fields to sane defaults. */
959 attr.bp_addr = 0;
960 attr.bp_len = HW_BREAKPOINT_LEN_4;
961 attr.bp_type = type;
962 attr.disabled = 1;
963
964 return register_user_hw_breakpoint(&attr, ptrace_hbptriggered, tsk);
965}
966
967static int ptrace_gethbpregs(struct task_struct *tsk, long num,
968 unsigned long __user *data)
969{
970 u32 reg;
971 int idx, ret = 0;
972 struct perf_event *bp;
973 struct arch_hw_breakpoint_ctrl arch_ctrl;
974
975 if (num == 0) {
976 reg = ptrace_get_hbp_resource_info();
977 } else {
978 idx = ptrace_hbp_num_to_idx(num);
979 if (idx < 0 || idx >= ARM_MAX_HBP_SLOTS) {
980 ret = -EINVAL;
981 goto out;
982 }
983
984 bp = tsk->thread.debug.hbp[idx];
985 if (!bp) {
986 reg = 0;
987 goto put;
988 }
989
990 arch_ctrl = counter_arch_bp(bp)->ctrl;
991
992 /*
993 * Fix up the len because we may have adjusted it
994 * to compensate for an unaligned address.
995 */
996 while (!(arch_ctrl.len & 0x1))
997 arch_ctrl.len >>= 1;
998
999 if (idx & 0x1)
1000 reg = encode_ctrl_reg(arch_ctrl);
1001 else
1002 reg = bp->attr.bp_addr;
1003 }
1004
1005put:
1006 if (put_user(reg, data))
1007 ret = -EFAULT;
1008
1009out:
1010 return ret;
1011}
1012
1013static int ptrace_sethbpregs(struct task_struct *tsk, long num,
1014 unsigned long __user *data)
1015{
1016 int idx, gen_len, gen_type, implied_type, ret = 0;
1017 u32 user_val;
1018 struct perf_event *bp;
1019 struct arch_hw_breakpoint_ctrl ctrl;
1020 struct perf_event_attr attr;
1021
1022 if (num == 0)
1023 goto out;
1024 else if (num < 0)
1025 implied_type = HW_BREAKPOINT_RW;
1026 else
1027 implied_type = HW_BREAKPOINT_X;
1028
1029 idx = ptrace_hbp_num_to_idx(num);
1030 if (idx < 0 || idx >= ARM_MAX_HBP_SLOTS) {
1031 ret = -EINVAL;
1032 goto out;
1033 }
1034
1035 if (get_user(user_val, data)) {
1036 ret = -EFAULT;
1037 goto out;
1038 }
1039
1040 bp = tsk->thread.debug.hbp[idx];
1041 if (!bp) {
1042 bp = ptrace_hbp_create(tsk, implied_type);
1043 if (IS_ERR(bp)) {
1044 ret = PTR_ERR(bp);
1045 goto out;
1046 }
1047 tsk->thread.debug.hbp[idx] = bp;
1048 }
1049
1050 attr = bp->attr;
1051
1052 if (num & 0x1) {
1053 /* Address */
1054 attr.bp_addr = user_val;
1055 } else {
1056 /* Control */
1057 decode_ctrl_reg(user_val, &ctrl);
1058 ret = arch_bp_generic_fields(ctrl, &gen_len, &gen_type);
1059 if (ret)
1060 goto out;
1061
1062 if ((gen_type & implied_type) != gen_type) {
1063 ret = -EINVAL;
1064 goto out;
1065 }
1066
1067 attr.bp_len = gen_len;
1068 attr.bp_type = gen_type;
1069 attr.disabled = !ctrl.enabled;
1070 }
1071
1072 ret = modify_user_hw_breakpoint(bp, &attr);
1073out:
1074 return ret;
1075}
1076#endif
1077
850long arch_ptrace(struct task_struct *child, long request, long addr, long data) 1078long arch_ptrace(struct task_struct *child, long request, long addr, long data)
851{ 1079{
852 int ret; 1080 int ret;
@@ -916,6 +1144,17 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
916 break; 1144 break;
917#endif 1145#endif
918 1146
1147#ifdef CONFIG_HAVE_HW_BREAKPOINT
1148 case PTRACE_GETHBPREGS:
1149 ret = ptrace_gethbpregs(child, addr,
1150 (unsigned long __user *)data);
1151 break;
1152 case PTRACE_SETHBPREGS:
1153 ret = ptrace_sethbpregs(child, addr,
1154 (unsigned long __user *)data);
1155 break;
1156#endif
1157
919 default: 1158 default:
920 ret = ptrace_request(child, request, addr, data); 1159 ret = ptrace_request(child, request, addr, data);
921 break; 1160 break;
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index d5231ae7355a..336f14e0e5c2 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -36,6 +36,7 @@
36#include <asm/procinfo.h> 36#include <asm/procinfo.h>
37#include <asm/sections.h> 37#include <asm/sections.h>
38#include <asm/setup.h> 38#include <asm/setup.h>
39#include <asm/smp_plat.h>
39#include <asm/mach-types.h> 40#include <asm/mach-types.h>
40#include <asm/cacheflush.h> 41#include <asm/cacheflush.h>
41#include <asm/cachetype.h> 42#include <asm/cachetype.h>
@@ -238,6 +239,35 @@ int cpu_architecture(void)
238 return cpu_arch; 239 return cpu_arch;
239} 240}
240 241
242static int cpu_has_aliasing_icache(unsigned int arch)
243{
244 int aliasing_icache;
245 unsigned int id_reg, num_sets, line_size;
246
247 /* arch specifies the register format */
248 switch (arch) {
249 case CPU_ARCH_ARMv7:
250 asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR"
251 : /* No output operands */
252 : "r" (1));
253 isb();
254 asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR"
255 : "=r" (id_reg));
256 line_size = 4 << ((id_reg & 0x7) + 2);
257 num_sets = ((id_reg >> 13) & 0x7fff) + 1;
258 aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
259 break;
260 case CPU_ARCH_ARMv6:
261 aliasing_icache = read_cpuid_cachetype() & (1 << 11);
262 break;
263 default:
264 /* I-cache aliases will be handled by D-cache aliasing code */
265 aliasing_icache = 0;
266 }
267
268 return aliasing_icache;
269}
270
241static void __init cacheid_init(void) 271static void __init cacheid_init(void)
242{ 272{
243 unsigned int cachetype = read_cpuid_cachetype(); 273 unsigned int cachetype = read_cpuid_cachetype();
@@ -249,10 +279,15 @@ static void __init cacheid_init(void)
249 cacheid = CACHEID_VIPT_NONALIASING; 279 cacheid = CACHEID_VIPT_NONALIASING;
250 if ((cachetype & (3 << 14)) == 1 << 14) 280 if ((cachetype & (3 << 14)) == 1 << 14)
251 cacheid |= CACHEID_ASID_TAGGED; 281 cacheid |= CACHEID_ASID_TAGGED;
252 } else if (cachetype & (1 << 23)) 282 else if (cpu_has_aliasing_icache(CPU_ARCH_ARMv7))
283 cacheid |= CACHEID_VIPT_I_ALIASING;
284 } else if (cachetype & (1 << 23)) {
253 cacheid = CACHEID_VIPT_ALIASING; 285 cacheid = CACHEID_VIPT_ALIASING;
254 else 286 } else {
255 cacheid = CACHEID_VIPT_NONALIASING; 287 cacheid = CACHEID_VIPT_NONALIASING;
288 if (cpu_has_aliasing_icache(CPU_ARCH_ARMv6))
289 cacheid |= CACHEID_VIPT_I_ALIASING;
290 }
256 } else { 291 } else {
257 cacheid = CACHEID_VIVT; 292 cacheid = CACHEID_VIVT;
258 } 293 }
@@ -263,7 +298,7 @@ static void __init cacheid_init(void)
263 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown", 298 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown",
264 cache_is_vivt() ? "VIVT" : 299 cache_is_vivt() ? "VIVT" :
265 icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" : 300 icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" :
266 cache_is_vipt_aliasing() ? "VIPT aliasing" : 301 icache_is_vipt_aliasing() ? "VIPT aliasing" :
267 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown"); 302 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown");
268} 303}
269 304
@@ -490,7 +525,7 @@ request_standard_resources(struct meminfo *mi, struct machine_desc *mdesc)
490 525
491 kernel_code.start = virt_to_phys(_text); 526 kernel_code.start = virt_to_phys(_text);
492 kernel_code.end = virt_to_phys(_etext - 1); 527 kernel_code.end = virt_to_phys(_etext - 1);
493 kernel_data.start = virt_to_phys(_data); 528 kernel_data.start = virt_to_phys(_sdata);
494 kernel_data.end = virt_to_phys(_end - 1); 529 kernel_data.end = virt_to_phys(_end - 1);
495 530
496 for (i = 0; i < mi->nr_banks; i++) { 531 for (i = 0; i < mi->nr_banks; i++) {
@@ -825,7 +860,8 @@ void __init setup_arch(char **cmdline_p)
825 request_standard_resources(&meminfo, mdesc); 860 request_standard_resources(&meminfo, mdesc);
826 861
827#ifdef CONFIG_SMP 862#ifdef CONFIG_SMP
828 smp_init_cpus(); 863 if (is_smp())
864 smp_init_cpus();
829#endif 865#endif
830 reserve_crashkernel(); 866 reserve_crashkernel();
831 867
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 40dc74f2b27f..8c1959590252 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -33,6 +33,7 @@
33#include <asm/pgtable.h> 33#include <asm/pgtable.h>
34#include <asm/pgalloc.h> 34#include <asm/pgalloc.h>
35#include <asm/processor.h> 35#include <asm/processor.h>
36#include <asm/sections.h>
36#include <asm/tlbflush.h> 37#include <asm/tlbflush.h>
37#include <asm/ptrace.h> 38#include <asm/ptrace.h>
38#include <asm/localtimer.h> 39#include <asm/localtimer.h>
@@ -67,12 +68,47 @@ enum ipi_msg_type {
67 IPI_CPU_STOP, 68 IPI_CPU_STOP,
68}; 69};
69 70
71static inline void identity_mapping_add(pgd_t *pgd, unsigned long start,
72 unsigned long end)
73{
74 unsigned long addr, prot;
75 pmd_t *pmd;
76
77 prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE;
78 if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
79 prot |= PMD_BIT4;
80
81 for (addr = start & PGDIR_MASK; addr < end;) {
82 pmd = pmd_offset(pgd + pgd_index(addr), addr);
83 pmd[0] = __pmd(addr | prot);
84 addr += SECTION_SIZE;
85 pmd[1] = __pmd(addr | prot);
86 addr += SECTION_SIZE;
87 flush_pmd_entry(pmd);
88 outer_clean_range(__pa(pmd), __pa(pmd + 1));
89 }
90}
91
92static inline void identity_mapping_del(pgd_t *pgd, unsigned long start,
93 unsigned long end)
94{
95 unsigned long addr;
96 pmd_t *pmd;
97
98 for (addr = start & PGDIR_MASK; addr < end; addr += PGDIR_SIZE) {
99 pmd = pmd_offset(pgd + pgd_index(addr), addr);
100 pmd[0] = __pmd(0);
101 pmd[1] = __pmd(0);
102 clean_pmd_entry(pmd);
103 outer_clean_range(__pa(pmd), __pa(pmd + 1));
104 }
105}
106
70int __cpuinit __cpu_up(unsigned int cpu) 107int __cpuinit __cpu_up(unsigned int cpu)
71{ 108{
72 struct cpuinfo_arm *ci = &per_cpu(cpu_data, cpu); 109 struct cpuinfo_arm *ci = &per_cpu(cpu_data, cpu);
73 struct task_struct *idle = ci->idle; 110 struct task_struct *idle = ci->idle;
74 pgd_t *pgd; 111 pgd_t *pgd;
75 pmd_t *pmd;
76 int ret; 112 int ret;
77 113
78 /* 114 /*
@@ -101,11 +137,16 @@ int __cpuinit __cpu_up(unsigned int cpu)
101 * a 1:1 mapping for the physical address of the kernel. 137 * a 1:1 mapping for the physical address of the kernel.
102 */ 138 */
103 pgd = pgd_alloc(&init_mm); 139 pgd = pgd_alloc(&init_mm);
104 pmd = pmd_offset(pgd + pgd_index(PHYS_OFFSET), PHYS_OFFSET); 140 if (!pgd)
105 *pmd = __pmd((PHYS_OFFSET & PGDIR_MASK) | 141 return -ENOMEM;
106 PMD_TYPE_SECT | PMD_SECT_AP_WRITE); 142
107 flush_pmd_entry(pmd); 143 if (PHYS_OFFSET != PAGE_OFFSET) {
108 outer_clean_range(__pa(pmd), __pa(pmd + 1)); 144#ifndef CONFIG_HOTPLUG_CPU
145 identity_mapping_add(pgd, __pa(__init_begin), __pa(__init_end));
146#endif
147 identity_mapping_add(pgd, __pa(_stext), __pa(_etext));
148 identity_mapping_add(pgd, __pa(_sdata), __pa(_edata));
149 }
109 150
110 /* 151 /*
111 * We need to tell the secondary core where to find 152 * We need to tell the secondary core where to find
@@ -143,8 +184,14 @@ int __cpuinit __cpu_up(unsigned int cpu)
143 secondary_data.stack = NULL; 184 secondary_data.stack = NULL;
144 secondary_data.pgdir = 0; 185 secondary_data.pgdir = 0;
145 186
146 *pmd = __pmd(0); 187 if (PHYS_OFFSET != PAGE_OFFSET) {
147 clean_pmd_entry(pmd); 188#ifndef CONFIG_HOTPLUG_CPU
189 identity_mapping_del(pgd, __pa(__init_begin), __pa(__init_end));
190#endif
191 identity_mapping_del(pgd, __pa(_stext), __pa(_etext));
192 identity_mapping_del(pgd, __pa(_sdata), __pa(_edata));
193 }
194
148 pgd_free(&init_mm, pgd); 195 pgd_free(&init_mm, pgd);
149 196
150 if (ret) { 197 if (ret) {
@@ -567,7 +614,8 @@ void smp_send_stop(void)
567{ 614{
568 cpumask_t mask = cpu_online_map; 615 cpumask_t mask = cpu_online_map;
569 cpu_clear(smp_processor_id(), mask); 616 cpu_clear(smp_processor_id(), mask);
570 send_ipi_message(&mask, IPI_CPU_STOP); 617 if (!cpus_empty(mask))
618 send_ipi_message(&mask, IPI_CPU_STOP);
571} 619}
572 620
573/* 621/*
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
index dd81a918c106..2a161765f6d5 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -146,6 +146,8 @@ static struct unwind_idx *unwind_find_idx(unsigned long addr)
146 addr < table->end_addr) { 146 addr < table->end_addr) {
147 idx = search_index(addr, table->start, 147 idx = search_index(addr, table->start,
148 table->stop - 1); 148 table->stop - 1);
149 /* Move-to-front to exploit common traces */
150 list_move(&table->list, &unwind_tables);
149 break; 151 break;
150 } 152 }
151 } 153 }
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b16c07914b55..1953e3d21abf 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -8,6 +8,19 @@
8#include <asm/memory.h> 8#include <asm/memory.h>
9#include <asm/page.h> 9#include <asm/page.h>
10 10
11#define PROC_INFO \
12 VMLINUX_SYMBOL(__proc_info_begin) = .; \
13 *(.proc.info.init) \
14 VMLINUX_SYMBOL(__proc_info_end) = .;
15
16#ifdef CONFIG_HOTPLUG_CPU
17#define ARM_CPU_DISCARD(x)
18#define ARM_CPU_KEEP(x) x
19#else
20#define ARM_CPU_DISCARD(x) x
21#define ARM_CPU_KEEP(x)
22#endif
23
11OUTPUT_ARCH(arm) 24OUTPUT_ARCH(arm)
12ENTRY(stext) 25ENTRY(stext)
13 26
@@ -31,15 +44,18 @@ SECTIONS
31 HEAD_TEXT 44 HEAD_TEXT
32 INIT_TEXT 45 INIT_TEXT
33 _einittext = .; 46 _einittext = .;
34 __proc_info_begin = .; 47 ARM_CPU_DISCARD(PROC_INFO)
35 *(.proc.info.init)
36 __proc_info_end = .;
37 __arch_info_begin = .; 48 __arch_info_begin = .;
38 *(.arch.info.init) 49 *(.arch.info.init)
39 __arch_info_end = .; 50 __arch_info_end = .;
40 __tagtable_begin = .; 51 __tagtable_begin = .;
41 *(.taglist.init) 52 *(.taglist.init)
42 __tagtable_end = .; 53 __tagtable_end = .;
54#ifdef CONFIG_SMP_ON_UP
55 __smpalt_begin = .;
56 *(.alt.smp.init)
57 __smpalt_end = .;
58#endif
43 59
44 INIT_SETUP(16) 60 INIT_SETUP(16)
45 61
@@ -68,10 +84,8 @@ SECTIONS
68 /DISCARD/ : { 84 /DISCARD/ : {
69 *(.ARM.exidx.exit.text) 85 *(.ARM.exidx.exit.text)
70 *(.ARM.extab.exit.text) 86 *(.ARM.extab.exit.text)
71#ifndef CONFIG_HOTPLUG_CPU 87 ARM_CPU_DISCARD(*(.ARM.exidx.cpuexit.text))
72 *(.ARM.exidx.cpuexit.text) 88 ARM_CPU_DISCARD(*(.ARM.extab.cpuexit.text))
73 *(.ARM.extab.cpuexit.text)
74#endif
75#ifndef CONFIG_HOTPLUG 89#ifndef CONFIG_HOTPLUG
76 *(.ARM.exidx.devexit.text) 90 *(.ARM.exidx.devexit.text)
77 *(.ARM.extab.devexit.text) 91 *(.ARM.extab.devexit.text)
@@ -100,12 +114,11 @@ SECTIONS
100 *(.glue_7) 114 *(.glue_7)
101 *(.glue_7t) 115 *(.glue_7t)
102 *(.got) /* Global offset table */ 116 *(.got) /* Global offset table */
117 ARM_CPU_KEEP(PROC_INFO)
103 } 118 }
104 119
105 RO_DATA(PAGE_SIZE) 120 RO_DATA(PAGE_SIZE)
106 121
107 _etext = .; /* End of text and rodata section */
108
109#ifdef CONFIG_ARM_UNWIND 122#ifdef CONFIG_ARM_UNWIND
110 /* 123 /*
111 * Stack unwinding tables 124 * Stack unwinding tables
@@ -123,6 +136,8 @@ SECTIONS
123 } 136 }
124#endif 137#endif
125 138
139 _etext = .; /* End of text and rodata section */
140
126#ifdef CONFIG_XIP_KERNEL 141#ifdef CONFIG_XIP_KERNEL
127 __data_loc = ALIGN(4); /* location in binary */ 142 __data_loc = ALIGN(4); /* location in binary */
128 . = PAGE_OFFSET + TEXT_OFFSET; 143 . = PAGE_OFFSET + TEXT_OFFSET;
@@ -237,6 +252,12 @@ SECTIONS
237 252
238 /* Default discards */ 253 /* Default discards */
239 DISCARDS 254 DISCARDS
255
256#ifndef CONFIG_SMP_ON_UP
257 /DISCARD/ : {
258 *(.alt.smp.init)
259 }
260#endif
240} 261}
241 262
242/* 263/*
diff --git a/arch/arm/mach-aaec2000/aaed2000.c b/arch/arm/mach-aaec2000/aaed2000.c
index 81a3ecc0d104..0eb3e3e5b2d1 100644
--- a/arch/arm/mach-aaec2000/aaed2000.c
+++ b/arch/arm/mach-aaec2000/aaed2000.c
@@ -95,8 +95,6 @@ static void __init aaed2000_map_io(void)
95 95
96MACHINE_START(AAED2000, "Agilent AAED-2000 Development Platform") 96MACHINE_START(AAED2000, "Agilent AAED-2000 Development Platform")
97 /* Maintainer: Nicolas Bellido Y Ortega */ 97 /* Maintainer: Nicolas Bellido Y Ortega */
98 .phys_io = PIO_BASE,
99 .io_pg_offst = ((VIO_BASE) >> 18) & 0xfffc,
100 .map_io = aaed2000_map_io, 98 .map_io = aaed2000_map_io,
101 .init_irq = aaed2000_init_irq, 99 .init_irq = aaed2000_init_irq,
102 .timer = &aaec2000_timer, 100 .timer = &aaec2000_timer,
diff --git a/arch/arm/mach-aaec2000/include/mach/debug-macro.S b/arch/arm/mach-aaec2000/include/mach/debug-macro.S
index a9cac368bfe6..bc7ad5561c4c 100644
--- a/arch/arm/mach-aaec2000/include/mach/debug-macro.S
+++ b/arch/arm/mach-aaec2000/include/mach/debug-macro.S
@@ -10,12 +10,10 @@
10 */ 10 */
11 11
12#include "hardware.h" 12#include "hardware.h"
13 .macro addruart, rx, tmp 13 .macro addruart, rp, rv
14 mrc p15, 0, \rx, c1, c0 14 mov \rp, 0x00000800
15 tst \rx, #1 @ MMU enabled? 15 orr \rv, \rp, #io_p2v(0x80000000) @ virtual
16 moveq \rx, #0x80000000 @ physical 16 orr \rp, \rp, #0x80000000 @ physical
17 movne \rx, #io_p2v(0x80000000) @ virtual
18 orr \rx, \rx, #0x00000800
19 .endm 17 .endm
20 18
21 .macro senduart,rd,rx 19 .macro senduart,rd,rx
diff --git a/arch/arm/mach-aaec2000/include/mach/vmalloc.h b/arch/arm/mach-aaec2000/include/mach/vmalloc.h
index 551f68f666bf..cff4e0a996ce 100644
--- a/arch/arm/mach-aaec2000/include/mach/vmalloc.h
+++ b/arch/arm/mach-aaec2000/include/mach/vmalloc.h
@@ -11,6 +11,6 @@
11#ifndef __ASM_ARCH_VMALLOC_H 11#ifndef __ASM_ARCH_VMALLOC_H
12#define __ASM_ARCH_VMALLOC_H 12#define __ASM_ARCH_VMALLOC_H
13 13
14#define VMALLOC_END (PAGE_OFFSET + 0x10000000) 14#define VMALLOC_END 0xd0000000
15 15
16#endif /* __ASM_ARCH_VMALLOC_H */ 16#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 939bccd70569..851e8139ef9d 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -33,6 +33,7 @@ config ARCH_AT91SAM9260
33 select HAVE_AT91_USART3 33 select HAVE_AT91_USART3
34 select HAVE_AT91_USART4 34 select HAVE_AT91_USART4
35 select HAVE_AT91_USART5 35 select HAVE_AT91_USART5
36 select HAVE_NET_MACB
36 37
37config ARCH_AT91SAM9261 38config ARCH_AT91SAM9261
38 bool "AT91SAM9261" 39 bool "AT91SAM9261"
@@ -51,6 +52,7 @@ config ARCH_AT91SAM9263
51 select CPU_ARM926T 52 select CPU_ARM926T
52 select GENERIC_CLOCKEVENTS 53 select GENERIC_CLOCKEVENTS
53 select HAVE_FB_ATMEL 54 select HAVE_FB_ATMEL
55 select HAVE_NET_MACB
54 56
55config ARCH_AT91SAM9RL 57config ARCH_AT91SAM9RL
56 bool "AT91SAM9RL" 58 bool "AT91SAM9RL"
@@ -66,6 +68,7 @@ config ARCH_AT91SAM9G20
66 select HAVE_AT91_USART3 68 select HAVE_AT91_USART3
67 select HAVE_AT91_USART4 69 select HAVE_AT91_USART4
68 select HAVE_AT91_USART5 70 select HAVE_AT91_USART5
71 select HAVE_NET_MACB
69 72
70config ARCH_AT91SAM9G45 73config ARCH_AT91SAM9G45
71 bool "AT91SAM9G45" 74 bool "AT91SAM9G45"
@@ -73,6 +76,7 @@ config ARCH_AT91SAM9G45
73 select GENERIC_CLOCKEVENTS 76 select GENERIC_CLOCKEVENTS
74 select HAVE_AT91_USART3 77 select HAVE_AT91_USART3
75 select HAVE_FB_ATMEL 78 select HAVE_FB_ATMEL
79 select HAVE_NET_MACB
76 80
77config ARCH_AT91CAP9 81config ARCH_AT91CAP9
78 bool "AT91CAP9" 82 bool "AT91CAP9"
@@ -248,6 +252,12 @@ config MACH_CPU9260
248 Select this if you are using a Eukrea Electromatique's 252 Select this if you are using a Eukrea Electromatique's
249 CPU9260 Board <http://www.eukrea.com/> 253 CPU9260 Board <http://www.eukrea.com/>
250 254
255config MACH_FLEXIBITY
256 bool "Flexibity Connect board"
257 help
258 Select this if you are using Flexibity Connect board
259 <http://www.flexibity.com>
260
251endif 261endif
252 262
253# ---------------------------------------------------------- 263# ----------------------------------------------------------
@@ -338,6 +348,7 @@ config MACH_AT91SAM9G20EK
338 that embeds only one SD/MMC slot. 348 that embeds only one SD/MMC slot.
339 349
340config MACH_AT91SAM9G20EK_2MMC 350config MACH_AT91SAM9G20EK_2MMC
351 depends on MACH_AT91SAM9G20EK
341 bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots" 352 bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots"
342 select HAVE_NAND_ATMEL_BUSWIDTH_16 353 select HAVE_NAND_ATMEL_BUSWIDTH_16
343 help 354 help
@@ -383,8 +394,8 @@ if ARCH_AT91SAM9G45
383 394
384comment "AT91SAM9G45 Board Type" 395comment "AT91SAM9G45 Board Type"
385 396
386config MACH_AT91SAM9G45EKES 397config MACH_AT91SAM9M10G45EK
387 bool "Atmel AT91SAM9G45-EKES Evaluation Kit" 398 bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
388 select HAVE_NAND_ATMEL_BUSWIDTH_16 399 select HAVE_NAND_ATMEL_BUSWIDTH_16
389 help 400 help
390 Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit. 401 Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit.
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index ca2ac003f41f..412b3a471a4b 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_MACH_USB_A9260) += board-usb-a9260.o
46obj-$(CONFIG_MACH_QIL_A9260) += board-qil-a9260.o 46obj-$(CONFIG_MACH_QIL_A9260) += board-qil-a9260.o
47obj-$(CONFIG_MACH_AFEB9260) += board-afeb-9260v1.o 47obj-$(CONFIG_MACH_AFEB9260) += board-afeb-9260v1.o
48obj-$(CONFIG_MACH_CPU9260) += board-cpu9krea.o 48obj-$(CONFIG_MACH_CPU9260) += board-cpu9krea.o
49obj-$(CONFIG_MACH_FLEXIBITY) += board-flexibity.o
49 50
50# AT91SAM9261 board-specific support 51# AT91SAM9261 board-specific support
51obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o 52obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
@@ -61,7 +62,6 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
61 62
62# AT91SAM9G20 board-specific support 63# AT91SAM9G20 board-specific support
63obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o 64obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
64obj-$(CONFIG_MACH_AT91SAM9G20EK_2MMC) += board-sam9g20ek-2slot-mmc.o
65obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o 65obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o
66obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o 66obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o
67obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o 67obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o
@@ -70,7 +70,7 @@ obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o
70obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o 70obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
71 71
72# AT91SAM9G45 board-specific support 72# AT91SAM9G45 board-specific support
73obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o 73obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
74 74
75# AT91CAP9 board-specific support 75# AT91CAP9 board-specific support
76obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o 76obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 9b27d167bff0..46bdc82d3fbf 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -92,8 +92,6 @@ static void __init onearm_board_init(void)
92 92
93MACHINE_START(ONEARM, "Ajeco 1ARM single board computer") 93MACHINE_START(ONEARM, "Ajeco 1ARM single board computer")
94 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 94 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
95 .phys_io = AT91_BASE_SYS,
96 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
97 .boot_params = AT91_SDRAM_BASE + 0x100, 95 .boot_params = AT91_SDRAM_BASE + 0x100,
98 .timer = &at91rm9200_timer, 96 .timer = &at91rm9200_timer,
99 .map_io = onearm_map_io, 97 .map_io = onearm_map_io,
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index 50667bed7cc9..cba7f7771fee 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -218,8 +218,6 @@ static void __init afeb9260_board_init(void)
218 218
219MACHINE_START(AFEB9260, "Custom afeb9260 board") 219MACHINE_START(AFEB9260, "Custom afeb9260 board")
220 /* Maintainer: Sergey Lapin <slapin@ossfans.org> */ 220 /* Maintainer: Sergey Lapin <slapin@ossfans.org> */
221 .phys_io = AT91_BASE_SYS,
222 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
223 .boot_params = AT91_SDRAM_BASE + 0x100, 221 .boot_params = AT91_SDRAM_BASE + 0x100,
224 .timer = &at91sam926x_timer, 222 .timer = &at91sam926x_timer,
225 .map_io = afeb9260_map_io, 223 .map_io = afeb9260_map_io,
diff --git a/arch/arm/mach-at91/board-at572d940hf_ek.c b/arch/arm/mach-at91/board-at572d940hf_ek.c
index 5daff277f53e..3929f1c9e4e5 100644
--- a/arch/arm/mach-at91/board-at572d940hf_ek.c
+++ b/arch/arm/mach-at91/board-at572d940hf_ek.c
@@ -216,7 +216,7 @@ static struct atmel_nand_data __initdata eb_nand_data = {
216/* .rdy_pin = AT91_PIN_PC16, */ 216/* .rdy_pin = AT91_PIN_PC16, */
217 .enable_pin = AT91_PIN_PA15, 217 .enable_pin = AT91_PIN_PA15,
218 .partition_info = nand_partitions, 218 .partition_info = nand_partitions,
219#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16) 219#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
220 .bus_width_16 = 1, 220 .bus_width_16 = 1,
221#else 221#else
222 .bus_width_16 = 0, 222 .bus_width_16 = 0,
@@ -318,8 +318,6 @@ static void __init eb_board_init(void)
318 318
319MACHINE_START(AT572D940HFEB, "Atmel AT91D940HF-EB") 319MACHINE_START(AT572D940HFEB, "Atmel AT91D940HF-EB")
320 /* Maintainer: Atmel <costa.antonior@gmail.com> */ 320 /* Maintainer: Atmel <costa.antonior@gmail.com> */
321 .phys_io = AT91_BASE_SYS,
322 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
323 .boot_params = AT91_SDRAM_BASE + 0x100, 321 .boot_params = AT91_SDRAM_BASE + 0x100,
324 .timer = &at91sam926x_timer, 322 .timer = &at91sam926x_timer,
325 .map_io = eb_map_io, 323 .map_io = eb_map_io,
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index 44eb9f764938..b54e3e6fceb6 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -198,8 +198,6 @@ static void __init cam60_board_init(void)
198 198
199MACHINE_START(CAM60, "KwikByte CAM60") 199MACHINE_START(CAM60, "KwikByte CAM60")
200 /* Maintainer: KwikByte */ 200 /* Maintainer: KwikByte */
201 .phys_io = AT91_BASE_SYS,
202 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
203 .boot_params = AT91_SDRAM_BASE + 0x100, 201 .boot_params = AT91_SDRAM_BASE + 0x100,
204 .timer = &at91sam926x_timer, 202 .timer = &at91sam926x_timer,
205 .map_io = cam60_map_io, 203 .map_io = cam60_map_io,
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
index d6940870e403..e7274440ead9 100644
--- a/arch/arm/mach-at91/board-cap9adk.c
+++ b/arch/arm/mach-at91/board-cap9adk.c
@@ -399,8 +399,6 @@ static void __init cap9adk_board_init(void)
399 399
400MACHINE_START(AT91CAP9ADK, "Atmel AT91CAP9A-DK") 400MACHINE_START(AT91CAP9ADK, "Atmel AT91CAP9A-DK")
401 /* Maintainer: Stelian Pop <stelian.pop@leadtechdesign.com> */ 401 /* Maintainer: Stelian Pop <stelian.pop@leadtechdesign.com> */
402 .phys_io = AT91_BASE_SYS,
403 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
404 .boot_params = AT91_SDRAM_BASE + 0x100, 402 .boot_params = AT91_SDRAM_BASE + 0x100,
405 .timer = &at91sam926x_timer, 403 .timer = &at91sam926x_timer,
406 .map_io = cap9adk_map_io, 404 .map_io = cap9adk_map_io,
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index db1f9544d2e0..2e74a19874d1 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -162,8 +162,6 @@ static void __init carmeva_board_init(void)
162 162
163MACHINE_START(CARMEVA, "Carmeva") 163MACHINE_START(CARMEVA, "Carmeva")
164 /* Maintainer: Conitec Datasystems */ 164 /* Maintainer: Conitec Datasystems */
165 .phys_io = AT91_BASE_SYS,
166 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
167 .boot_params = AT91_SDRAM_BASE + 0x100, 165 .boot_params = AT91_SDRAM_BASE + 0x100,
168 .timer = &at91rm9200_timer, 166 .timer = &at91rm9200_timer,
169 .map_io = carmeva_map_io, 167 .map_io = carmeva_map_io,
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 4bc2e9f6ebb5..3838594578f3 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -375,8 +375,6 @@ MACHINE_START(CPUAT9260, "Eukrea CPU9260")
375MACHINE_START(CPUAT9G20, "Eukrea CPU9G20") 375MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
376#endif 376#endif
377 /* Maintainer: Eric Benard - EUKREA Electromatique */ 377 /* Maintainer: Eric Benard - EUKREA Electromatique */
378 .phys_io = AT91_BASE_SYS,
379 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
380 .boot_params = AT91_SDRAM_BASE + 0x100, 378 .boot_params = AT91_SDRAM_BASE + 0x100,
381 .timer = &at91sam926x_timer, 379 .timer = &at91sam926x_timer,
382 .map_io = cpu9krea_map_io, 380 .map_io = cpu9krea_map_io,
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index a28d99656190..2f4dd8cdd484 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -175,8 +175,6 @@ static void __init cpuat91_board_init(void)
175 175
176MACHINE_START(CPUAT91, "Eukrea") 176MACHINE_START(CPUAT91, "Eukrea")
177 /* Maintainer: Eric Benard - EUKREA Electromatique */ 177 /* Maintainer: Eric Benard - EUKREA Electromatique */
178 .phys_io = AT91_BASE_SYS,
179 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
180 .boot_params = AT91_SDRAM_BASE + 0x100, 178 .boot_params = AT91_SDRAM_BASE + 0x100,
181 .timer = &at91rm9200_timer, 179 .timer = &at91rm9200_timer,
182 .map_io = cpuat91_map_io, 180 .map_io = cpuat91_map_io,
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index fea2529ebcf9..464839dc39bd 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -257,8 +257,6 @@ static void __init csb337_board_init(void)
257 257
258MACHINE_START(CSB337, "Cogent CSB337") 258MACHINE_START(CSB337, "Cogent CSB337")
259 /* Maintainer: Bill Gatliff */ 259 /* Maintainer: Bill Gatliff */
260 .phys_io = AT91_BASE_SYS,
261 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
262 .boot_params = AT91_SDRAM_BASE + 0x100, 260 .boot_params = AT91_SDRAM_BASE + 0x100,
263 .timer = &at91rm9200_timer, 261 .timer = &at91rm9200_timer,
264 .map_io = csb337_map_io, 262 .map_io = csb337_map_io,
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index cfa3f04b2205..431688c61412 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -138,8 +138,6 @@ static void __init csb637_board_init(void)
138 138
139MACHINE_START(CSB637, "Cogent CSB637") 139MACHINE_START(CSB637, "Cogent CSB637")
140 /* Maintainer: Bill Gatliff */ 140 /* Maintainer: Bill Gatliff */
141 .phys_io = AT91_BASE_SYS,
142 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
143 .boot_params = AT91_SDRAM_BASE + 0x100, 141 .boot_params = AT91_SDRAM_BASE + 0x100,
144 .timer = &at91rm9200_timer, 142 .timer = &at91rm9200_timer,
145 .map_io = csb637_map_io, 143 .map_io = csb637_map_io,
diff --git a/arch/arm/mach-at91/board-dk.c b/arch/arm/mach-at91/board-dk.c
index 0fd0f5bc77ea..e14f0e165680 100644
--- a/arch/arm/mach-at91/board-dk.c
+++ b/arch/arm/mach-at91/board-dk.c
@@ -225,8 +225,6 @@ static void __init dk_board_init(void)
225 225
226MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK") 226MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK")
227 /* Maintainer: SAN People/Atmel */ 227 /* Maintainer: SAN People/Atmel */
228 .phys_io = AT91_BASE_SYS,
229 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
230 .boot_params = AT91_SDRAM_BASE + 0x100, 228 .boot_params = AT91_SDRAM_BASE + 0x100,
231 .timer = &at91rm9200_timer, 229 .timer = &at91rm9200_timer,
232 .map_io = dk_map_io, 230 .map_io = dk_map_io,
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index 528656761ff7..6cf6566ae346 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -120,8 +120,6 @@ static void __init eb9200_board_init(void)
120} 120}
121 121
122MACHINE_START(ATEB9200, "Embest ATEB9200") 122MACHINE_START(ATEB9200, "Embest ATEB9200")
123 .phys_io = AT91_BASE_SYS,
124 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
125 .boot_params = AT91_SDRAM_BASE + 0x100, 123 .boot_params = AT91_SDRAM_BASE + 0x100,
126 .timer = &at91rm9200_timer, 124 .timer = &at91rm9200_timer,
127 .map_io = eb9200_map_io, 125 .map_io = eb9200_map_io,
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index 1d69908617f0..7b58c948a957 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -168,8 +168,6 @@ static void __init ecb_at91board_init(void)
168 168
169MACHINE_START(ECBAT91, "emQbit's ECB_AT91") 169MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
170 /* Maintainer: emQbit.com */ 170 /* Maintainer: emQbit.com */
171 .phys_io = AT91_BASE_SYS,
172 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
173 .boot_params = AT91_SDRAM_BASE + 0x100, 171 .boot_params = AT91_SDRAM_BASE + 0x100,
174 .timer = &at91rm9200_timer, 172 .timer = &at91rm9200_timer,
175 .map_io = ecb_at91map_io, 173 .map_io = ecb_at91map_io,
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 295a96609e71..a158a0ce458f 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -148,8 +148,6 @@ static void __init eco920_board_init(void)
148 148
149MACHINE_START(ECO920, "eco920") 149MACHINE_START(ECO920, "eco920")
150 /* Maintainer: Sascha Hauer */ 150 /* Maintainer: Sascha Hauer */
151 .phys_io = AT91_BASE_SYS,
152 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
153 .boot_params = AT91_SDRAM_BASE + 0x100, 151 .boot_params = AT91_SDRAM_BASE + 0x100,
154 .timer = &at91rm9200_timer, 152 .timer = &at91rm9200_timer,
155 .map_io = eco920_map_io, 153 .map_io = eco920_map_io,
diff --git a/arch/arm/mach-at91/board-ek.c b/arch/arm/mach-at91/board-ek.c
index 4cdfaac8e590..56e92c4bbc2a 100644
--- a/arch/arm/mach-at91/board-ek.c
+++ b/arch/arm/mach-at91/board-ek.c
@@ -191,8 +191,6 @@ static void __init ek_board_init(void)
191 191
192MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK") 192MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
193 /* Maintainer: SAN People/Atmel */ 193 /* Maintainer: SAN People/Atmel */
194 .phys_io = AT91_BASE_SYS,
195 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
196 .boot_params = AT91_SDRAM_BASE + 0x100, 194 .boot_params = AT91_SDRAM_BASE + 0x100,
197 .timer = &at91rm9200_timer, 195 .timer = &at91rm9200_timer,
198 .map_io = ek_map_io, 196 .map_io = ek_map_io,
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
new file mode 100644
index 000000000000..c8a62dc8fa65
--- /dev/null
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -0,0 +1,162 @@
1/*
2 * linux/arch/arm/mach-at91/board-flexibity.c
3 *
4 * Copyright (C) 2010 Flexibity
5 * Copyright (C) 2005 SAN People
6 * Copyright (C) 2006 Atmel
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/init.h>
24#include <linux/platform_device.h>
25#include <linux/spi/spi.h>
26#include <linux/input.h>
27#include <linux/gpio.h>
28
29#include <asm/mach-types.h>
30
31#include <asm/mach/arch.h>
32#include <asm/mach/map.h>
33#include <asm/mach/irq.h>
34
35#include <mach/hardware.h>
36#include <mach/board.h>
37
38#include "generic.h"
39
40static void __init flexibity_map_io(void)
41{
42 /* Initialize processor: 18.432 MHz crystal */
43 at91sam9260_initialize(18432000);
44
45 /* DBGU on ttyS0. (Rx & Tx only) */
46 at91_register_uart(0, 0, 0);
47
48 /* set serial console to ttyS0 (ie, DBGU) */
49 at91_set_serial_console(0);
50}
51
52static void __init flexibity_init_irq(void)
53{
54 at91sam9260_init_interrupts(NULL);
55}
56
57/* USB Host port */
58static struct at91_usbh_data __initdata flexibity_usbh_data = {
59 .ports = 2,
60};
61
62/* USB Device port */
63static struct at91_udc_data __initdata flexibity_udc_data = {
64 .vbus_pin = AT91_PIN_PC5,
65 .pullup_pin = 0, /* pull-up driven by UDC */
66};
67
68/* SPI devices */
69static struct spi_board_info flexibity_spi_devices[] = {
70 { /* DataFlash chip */
71 .modalias = "mtd_dataflash",
72 .chip_select = 1,
73 .max_speed_hz = 15 * 1000 * 1000,
74 .bus_num = 0,
75 },
76};
77
78/* MCI (SD/MMC) */
79static struct at91_mmc_data __initdata flexibity_mmc_data = {
80 .slot_b = 0,
81 .wire4 = 1,
82 .det_pin = AT91_PIN_PC9,
83 .wp_pin = AT91_PIN_PC4,
84};
85
86/* LEDs */
87static struct gpio_led flexibity_leds[] = {
88 {
89 .name = "usb1:green",
90 .gpio = AT91_PIN_PA12,
91 .active_low = 1,
92 .default_trigger = "default-on",
93 },
94 {
95 .name = "usb1:red",
96 .gpio = AT91_PIN_PA13,
97 .active_low = 1,
98 .default_trigger = "default-on",
99 },
100 {
101 .name = "usb2:green",
102 .gpio = AT91_PIN_PB26,
103 .active_low = 1,
104 .default_trigger = "default-on",
105 },
106 {
107 .name = "usb2:red",
108 .gpio = AT91_PIN_PB27,
109 .active_low = 1,
110 .default_trigger = "default-on",
111 },
112 {
113 .name = "usb3:green",
114 .gpio = AT91_PIN_PC8,
115 .active_low = 1,
116 .default_trigger = "default-on",
117 },
118 {
119 .name = "usb3:red",
120 .gpio = AT91_PIN_PC6,
121 .active_low = 1,
122 .default_trigger = "default-on",
123 },
124 {
125 .name = "usb4:green",
126 .gpio = AT91_PIN_PB4,
127 .active_low = 1,
128 .default_trigger = "default-on",
129 },
130 {
131 .name = "usb4:red",
132 .gpio = AT91_PIN_PB5,
133 .active_low = 1,
134 .default_trigger = "default-on",
135 }
136};
137
138static void __init flexibity_board_init(void)
139{
140 /* Serial */
141 at91_add_device_serial();
142 /* USB Host */
143 at91_add_device_usbh(&flexibity_usbh_data);
144 /* USB Device */
145 at91_add_device_udc(&flexibity_udc_data);
146 /* SPI */
147 at91_add_device_spi(flexibity_spi_devices,
148 ARRAY_SIZE(flexibity_spi_devices));
149 /* MMC */
150 at91_add_device_mmc(0, &flexibity_mmc_data);
151 /* LEDs */
152 at91_gpio_leds(flexibity_leds, ARRAY_SIZE(flexibity_leds));
153}
154
155MACHINE_START(FLEXIBITY, "Flexibity Connect")
156 /* Maintainer: Maxim Osipov */
157 .boot_params = AT91_SDRAM_BASE + 0x100,
158 .timer = &at91sam926x_timer,
159 .map_io = flexibity_map_io,
160 .init_irq = flexibity_init_irq,
161 .init_machine = flexibity_board_init,
162MACHINE_END
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index a87956c0a74f..c0ce79d431a0 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -99,8 +99,6 @@ static void __init kafa_board_init(void)
99 99
100MACHINE_START(KAFA, "Sperry-Sun KAFA") 100MACHINE_START(KAFA, "Sperry-Sun KAFA")
101 /* Maintainer: Sergei Sharonov */ 101 /* Maintainer: Sergei Sharonov */
102 .phys_io = AT91_BASE_SYS,
103 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
104 .boot_params = AT91_SDRAM_BASE + 0x100, 102 .boot_params = AT91_SDRAM_BASE + 0x100,
105 .timer = &at91rm9200_timer, 103 .timer = &at91rm9200_timer,
106 .map_io = kafa_map_io, 104 .map_io = kafa_map_io,
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index fe9b9913fa3c..a13d2063faff 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -136,8 +136,6 @@ static void __init kb9202_board_init(void)
136 136
137MACHINE_START(KB9200, "KB920x") 137MACHINE_START(KB9200, "KB920x")
138 /* Maintainer: KwikByte, Inc. */ 138 /* Maintainer: KwikByte, Inc. */
139 .phys_io = AT91_BASE_SYS,
140 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
141 .boot_params = AT91_SDRAM_BASE + 0x100, 139 .boot_params = AT91_SDRAM_BASE + 0x100,
142 .timer = &at91rm9200_timer, 140 .timer = &at91rm9200_timer,
143 .map_io = kb9202_map_io, 141 .map_io = kb9202_map_io,
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
index 7c1e382330fb..fe5f1d47e6e2 100644
--- a/arch/arm/mach-at91/board-neocore926.c
+++ b/arch/arm/mach-at91/board-neocore926.c
@@ -387,8 +387,6 @@ static void __init neocore926_board_init(void)
387 387
388MACHINE_START(NEOCORE926, "ADENEO NEOCORE 926") 388MACHINE_START(NEOCORE926, "ADENEO NEOCORE 926")
389 /* Maintainer: ADENEO */ 389 /* Maintainer: ADENEO */
390 .phys_io = AT91_BASE_SYS,
391 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
392 .boot_params = AT91_SDRAM_BASE + 0x100, 390 .boot_params = AT91_SDRAM_BASE + 0x100,
393 .timer = &at91sam926x_timer, 391 .timer = &at91sam926x_timer,
394 .map_io = neocore926_map_io, 392 .map_io = neocore926_map_io,
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index 859727e7ea30..9d833bbc592d 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -156,8 +156,6 @@ static void __init picotux200_board_init(void)
156 156
157MACHINE_START(PICOTUX2XX, "picotux 200") 157MACHINE_START(PICOTUX2XX, "picotux 200")
158 /* Maintainer: Kleinhenz Elektronik GmbH */ 158 /* Maintainer: Kleinhenz Elektronik GmbH */
159 .phys_io = AT91_BASE_SYS,
160 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
161 .boot_params = AT91_SDRAM_BASE + 0x100, 159 .boot_params = AT91_SDRAM_BASE + 0x100,
162 .timer = &at91rm9200_timer, 160 .timer = &at91rm9200_timer,
163 .map_io = picotux200_map_io, 161 .map_io = picotux200_map_io,
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index 664938e8f661..69d15a875b66 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -268,8 +268,6 @@ static void __init ek_board_init(void)
268 268
269MACHINE_START(QIL_A9260, "CALAO QIL_A9260") 269MACHINE_START(QIL_A9260, "CALAO QIL_A9260")
270 /* Maintainer: calao-systems */ 270 /* Maintainer: calao-systems */
271 .phys_io = AT91_BASE_SYS,
272 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
273 .boot_params = AT91_SDRAM_BASE + 0x100, 271 .boot_params = AT91_SDRAM_BASE + 0x100,
274 .timer = &at91sam926x_timer, 272 .timer = &at91sam926x_timer,
275 .map_io = ek_map_io, 273 .map_io = ek_map_io,
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index b48346977534..25a26beaa728 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -212,8 +212,6 @@ static void __init ek_board_init(void)
212 212
213MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260") 213MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
214 /* Maintainer: Olimex */ 214 /* Maintainer: Olimex */
215 .phys_io = AT91_BASE_SYS,
216 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
217 .boot_params = AT91_SDRAM_BASE + 0x100, 215 .boot_params = AT91_SDRAM_BASE + 0x100,
218 .timer = &at91sam926x_timer, 216 .timer = &at91sam926x_timer,
219 .map_io = ek_map_io, 217 .map_io = ek_map_io,
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index ba9d501b5c50..de1816e0e1d9 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -356,8 +356,6 @@ static void __init ek_board_init(void)
356 356
357MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK") 357MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
358 /* Maintainer: Atmel */ 358 /* Maintainer: Atmel */
359 .phys_io = AT91_BASE_SYS,
360 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
361 .boot_params = AT91_SDRAM_BASE + 0x100, 359 .boot_params = AT91_SDRAM_BASE + 0x100,
362 .timer = &at91sam926x_timer, 360 .timer = &at91sam926x_timer,
363 .map_io = ek_map_io, 361 .map_io = ek_map_io,
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 65eb0943194f..14acc901e24c 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -623,8 +623,6 @@ MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
623MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK") 623MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
624#endif 624#endif
625 /* Maintainer: Atmel */ 625 /* Maintainer: Atmel */
626 .phys_io = AT91_BASE_SYS,
627 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
628 .boot_params = AT91_SDRAM_BASE + 0x100, 626 .boot_params = AT91_SDRAM_BASE + 0x100,
629 .timer = &at91sam926x_timer, 627 .timer = &at91sam926x_timer,
630 .map_io = ek_map_io, 628 .map_io = ek_map_io,
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 2d867fb0630f..bfe490df58be 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -454,8 +454,6 @@ static void __init ek_board_init(void)
454 454
455MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK") 455MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
456 /* Maintainer: Atmel */ 456 /* Maintainer: Atmel */
457 .phys_io = AT91_BASE_SYS,
458 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
459 .boot_params = AT91_SDRAM_BASE + 0x100, 457 .boot_params = AT91_SDRAM_BASE + 0x100,
460 .timer = &at91sam926x_timer, 458 .timer = &at91sam926x_timer,
461 .map_io = ek_map_io, 459 .map_io = ek_map_io,
diff --git a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c b/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
deleted file mode 100644
index c49f5c003ee1..000000000000
--- a/arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
+++ /dev/null
@@ -1,329 +0,0 @@
1/*
2 * Copyright (C) 2005 SAN People
3 * Copyright (C) 2008 Atmel
4 * Copyright (C) 2009 Rob Emanuele
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/types.h>
22#include <linux/init.h>
23#include <linux/mm.h>
24#include <linux/module.h>
25#include <linux/platform_device.h>
26#include <linux/spi/spi.h>
27#include <linux/spi/at73c213.h>
28#include <linux/clk.h>
29#include <linux/regulator/machine.h>
30#include <linux/regulator/fixed.h>
31#include <linux/regulator/consumer.h>
32
33#include <mach/hardware.h>
34#include <asm/setup.h>
35#include <asm/mach-types.h>
36#include <asm/irq.h>
37
38#include <asm/mach/arch.h>
39#include <asm/mach/map.h>
40#include <asm/mach/irq.h>
41
42#include <mach/board.h>
43#include <mach/gpio.h>
44#include <mach/at91sam9_smc.h>
45
46#include "sam9_smc.h"
47#include "generic.h"
48
49
50static void __init ek_map_io(void)
51{
52 /* Initialize processor: 18.432 MHz crystal */
53 at91sam9260_initialize(18432000);
54
55 /* DGBU on ttyS0. (Rx & Tx only) */
56 at91_register_uart(0, 0, 0);
57
58 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
59 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
60 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
61 | ATMEL_UART_RI);
62
63 /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
64 at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
65
66 /* set serial console to ttyS0 (ie, DBGU) */
67 at91_set_serial_console(0);
68}
69
70static void __init ek_init_irq(void)
71{
72 at91sam9260_init_interrupts(NULL);
73}
74
75
76/*
77 * USB Host port
78 */
79static struct at91_usbh_data __initdata ek_usbh_data = {
80 .ports = 2,
81};
82
83/*
84 * USB Device port
85 */
86static struct at91_udc_data __initdata ek_udc_data = {
87 .vbus_pin = AT91_PIN_PC5,
88 .pullup_pin = 0, /* pull-up driven by UDC */
89};
90
91
92/*
93 * SPI devices.
94 */
95static struct spi_board_info ek_spi_devices[] = {
96#if !(defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_AT91))
97 { /* DataFlash chip */
98 .modalias = "mtd_dataflash",
99 .chip_select = 1,
100 .max_speed_hz = 15 * 1000 * 1000,
101 .bus_num = 0,
102 },
103#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
104 { /* DataFlash card */
105 .modalias = "mtd_dataflash",
106 .chip_select = 0,
107 .max_speed_hz = 15 * 1000 * 1000,
108 .bus_num = 0,
109 },
110#endif
111#endif
112};
113
114
115/*
116 * MACB Ethernet device
117 */
118static struct at91_eth_data __initdata ek_macb_data = {
119 .phy_irq_pin = AT91_PIN_PB0,
120 .is_rmii = 1,
121};
122
123
124/*
125 * NAND flash
126 */
127static struct mtd_partition __initdata ek_nand_partition[] = {
128 {
129 .name = "Bootstrap",
130 .offset = 0,
131 .size = 4 * SZ_1M,
132 },
133 {
134 .name = "Partition 1",
135 .offset = MTDPART_OFS_NXTBLK,
136 .size = 60 * SZ_1M,
137 },
138 {
139 .name = "Partition 2",
140 .offset = MTDPART_OFS_NXTBLK,
141 .size = MTDPART_SIZ_FULL,
142 },
143};
144
145static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
146{
147 *num_partitions = ARRAY_SIZE(ek_nand_partition);
148 return ek_nand_partition;
149}
150
151/* det_pin is not connected */
152static struct atmel_nand_data __initdata ek_nand_data = {
153 .ale = 21,
154 .cle = 22,
155 .rdy_pin = AT91_PIN_PC13,
156 .enable_pin = AT91_PIN_PC14,
157 .partition_info = nand_partitions,
158#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
159 .bus_width_16 = 1,
160#else
161 .bus_width_16 = 0,
162#endif
163};
164
165static struct sam9_smc_config __initdata ek_nand_smc_config = {
166 .ncs_read_setup = 0,
167 .nrd_setup = 2,
168 .ncs_write_setup = 0,
169 .nwe_setup = 2,
170
171 .ncs_read_pulse = 4,
172 .nrd_pulse = 4,
173 .ncs_write_pulse = 4,
174 .nwe_pulse = 4,
175
176 .read_cycle = 7,
177 .write_cycle = 7,
178
179 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
180 .tdf_cycles = 3,
181};
182
183static void __init ek_add_device_nand(void)
184{
185 /* setup bus-width (8 or 16) */
186 if (ek_nand_data.bus_width_16)
187 ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
188 else
189 ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
190
191 /* configure chip-select 3 (NAND) */
192 sam9_smc_configure(3, &ek_nand_smc_config);
193
194 at91_add_device_nand(&ek_nand_data);
195}
196
197
198/*
199 * MCI (SD/MMC)
200 * wp_pin is not connected
201 */
202#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
203static struct mci_platform_data __initdata ek_mmc_data = {
204 .slot[0] = {
205 .bus_width = 4,
206 .detect_pin = AT91_PIN_PC2,
207 .wp_pin = -ENODEV,
208 },
209 .slot[1] = {
210 .bus_width = 4,
211 .detect_pin = AT91_PIN_PC9,
212 .wp_pin = -ENODEV,
213 },
214
215};
216#else
217static struct at91_mmc_data __initdata ek_mmc_data = {
218 .slot_b = 1, /* Only one slot so use slot B */
219 .wire4 = 1,
220 .det_pin = AT91_PIN_PC9,
221};
222#endif
223
224/*
225 * LEDs
226 */
227static struct gpio_led ek_leds[] = {
228 { /* "bottom" led, green, userled1 to be defined */
229 .name = "ds5",
230 .gpio = AT91_PIN_PB8,
231 .active_low = 1,
232 .default_trigger = "none",
233 },
234 { /* "power" led, yellow */
235 .name = "ds1",
236 .gpio = AT91_PIN_PB9,
237 .default_trigger = "heartbeat",
238 }
239};
240
241#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
242static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
243 REGULATOR_SUPPLY("AVDD", "0-001b"),
244 REGULATOR_SUPPLY("HPVDD", "0-001b"),
245 REGULATOR_SUPPLY("DBVDD", "0-001b"),
246 REGULATOR_SUPPLY("DCVDD", "0-001b"),
247};
248
249static struct regulator_init_data ek_avdd_reg_init_data = {
250 .constraints = {
251 .name = "3V3",
252 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
253 },
254 .consumer_supplies = ek_audio_consumer_supplies,
255 .num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
256};
257
258static struct fixed_voltage_config ek_vdd_pdata = {
259 .supply_name = "board-3V3",
260 .microvolts = 3300000,
261 .gpio = -EINVAL,
262 .enabled_at_boot = 0,
263 .init_data = &ek_avdd_reg_init_data,
264};
265static struct platform_device ek_voltage_regulator = {
266 .name = "reg-fixed-voltage",
267 .id = -1,
268 .num_resources = 0,
269 .dev = {
270 .platform_data = &ek_vdd_pdata,
271 },
272};
273static void __init ek_add_regulators(void)
274{
275 platform_device_register(&ek_voltage_regulator);
276}
277#else
278static void __init ek_add_regulators(void) {}
279#endif
280
281static struct i2c_board_info __initdata ek_i2c_devices[] = {
282 {
283 I2C_BOARD_INFO("24c512", 0x50),
284 },
285};
286
287
288static void __init ek_board_init(void)
289{
290 /* Serial */
291 at91_add_device_serial();
292 /* USB Host */
293 at91_add_device_usbh(&ek_usbh_data);
294 /* USB Device */
295 at91_add_device_udc(&ek_udc_data);
296 /* SPI */
297 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
298 /* NAND */
299 ek_add_device_nand();
300 /* Ethernet */
301 at91_add_device_eth(&ek_macb_data);
302 /* Regulators */
303 ek_add_regulators();
304 /* MMC */
305#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
306 at91_add_device_mci(0, &ek_mmc_data);
307#else
308 at91_add_device_mmc(0, &ek_mmc_data);
309#endif
310 /* I2C */
311 at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
312 /* LEDs */
313 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
314 /* PCK0 provides MCLK to the WM8731 */
315 at91_set_B_periph(AT91_PIN_PC1, 0);
316 /* SSC (for WM8731) */
317 at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
318}
319
320MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
321 /* Maintainer: Rob Emanuele */
322 .phys_io = AT91_BASE_SYS,
323 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
324 .boot_params = AT91_SDRAM_BASE + 0x100,
325 .timer = &at91sam926x_timer,
326 .map_io = ek_map_io,
327 .init_irq = ek_init_irq,
328 .init_machine = ek_board_init,
329MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 6ea9808b8868..ca8198b3c168 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -47,6 +47,18 @@
47#include "sam9_smc.h" 47#include "sam9_smc.h"
48#include "generic.h" 48#include "generic.h"
49 49
50/*
51 * board revision encoding
52 * bit 0:
53 * 0 => 1 sd/mmc slot
54 * 1 => 2 sd/mmc slots connectors (board from revision C)
55 */
56#define HAVE_2MMC (1 << 0)
57static int inline ek_have_2mmc(void)
58{
59 return machine_is_at91sam9g20ek_2mmc() || (system_rev & HAVE_2MMC);
60}
61
50 62
51static void __init ek_map_io(void) 63static void __init ek_map_io(void)
52{ 64{
@@ -94,7 +106,7 @@ static struct at91_udc_data __initdata ek_udc_data = {
94 * SPI devices. 106 * SPI devices.
95 */ 107 */
96static struct spi_board_info ek_spi_devices[] = { 108static struct spi_board_info ek_spi_devices[] = {
97#if !defined(CONFIG_MMC_AT91) 109#if !(defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_AT91))
98 { /* DataFlash chip */ 110 { /* DataFlash chip */
99 .modalias = "mtd_dataflash", 111 .modalias = "mtd_dataflash",
100 .chip_select = 1, 112 .chip_select = 1,
@@ -121,6 +133,13 @@ static struct at91_eth_data __initdata ek_macb_data = {
121 .is_rmii = 1, 133 .is_rmii = 1,
122}; 134};
123 135
136static void __init ek_add_device_macb(void)
137{
138 if (ek_have_2mmc())
139 ek_macb_data.phy_irq_pin = AT91_PIN_PB0;
140
141 at91_add_device_eth(&ek_macb_data);
142}
124 143
125/* 144/*
126 * NAND flash 145 * NAND flash
@@ -198,13 +217,36 @@ static void __init ek_add_device_nand(void)
198 217
199/* 218/*
200 * MCI (SD/MMC) 219 * MCI (SD/MMC)
201 * det_pin, wp_pin and vcc_pin are not connected 220 * wp_pin and vcc_pin are not connected
202 */ 221 */
222#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
223static struct mci_platform_data __initdata ek_mmc_data = {
224 .slot[1] = {
225 .bus_width = 4,
226 .detect_pin = AT91_PIN_PC9,
227 },
228
229};
230#else
203static struct at91_mmc_data __initdata ek_mmc_data = { 231static struct at91_mmc_data __initdata ek_mmc_data = {
204 .slot_b = 1, 232 .slot_b = 1, /* Only one slot so use slot B */
205 .wire4 = 1, 233 .wire4 = 1,
234 .det_pin = AT91_PIN_PC9,
206}; 235};
236#endif
207 237
238static void __init ek_add_device_mmc(void)
239{
240#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
241 if (ek_have_2mmc()) {
242 ek_mmc_data.slot[0].bus_width = 4;
243 ek_mmc_data.slot[0].detect_pin = AT91_PIN_PC2;
244 }
245 at91_add_device_mci(0, &ek_mmc_data);
246#else
247 at91_add_device_mmc(0, &ek_mmc_data);
248#endif
249}
208 250
209/* 251/*
210 * LEDs 252 * LEDs
@@ -223,6 +265,15 @@ static struct gpio_led ek_leds[] = {
223 } 265 }
224}; 266};
225 267
268static void __init ek_add_device_gpio_leds(void)
269{
270 if (ek_have_2mmc()) {
271 ek_leds[0].gpio = AT91_PIN_PB8;
272 ek_leds[1].gpio = AT91_PIN_PB9;
273 }
274
275 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
276}
226 277
227/* 278/*
228 * GPIO Buttons 279 * GPIO Buttons
@@ -336,15 +387,15 @@ static void __init ek_board_init(void)
336 /* NAND */ 387 /* NAND */
337 ek_add_device_nand(); 388 ek_add_device_nand();
338 /* Ethernet */ 389 /* Ethernet */
339 at91_add_device_eth(&ek_macb_data); 390 ek_add_device_macb();
340 /* Regulators */ 391 /* Regulators */
341 ek_add_regulators(); 392 ek_add_regulators();
342 /* MMC */ 393 /* MMC */
343 at91_add_device_mmc(0, &ek_mmc_data); 394 ek_add_device_mmc();
344 /* I2C */ 395 /* I2C */
345 at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices)); 396 at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
346 /* LEDs */ 397 /* LEDs */
347 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); 398 ek_add_device_gpio_leds();
348 /* Push Buttons */ 399 /* Push Buttons */
349 ek_add_device_buttons(); 400 ek_add_device_buttons();
350 /* PCK0 provides MCLK to the WM8731 */ 401 /* PCK0 provides MCLK to the WM8731 */
@@ -355,8 +406,15 @@ static void __init ek_board_init(void)
355 406
356MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK") 407MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
357 /* Maintainer: Atmel */ 408 /* Maintainer: Atmel */
358 .phys_io = AT91_BASE_SYS, 409 .boot_params = AT91_SDRAM_BASE + 0x100,
359 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, 410 .timer = &at91sam926x_timer,
411 .map_io = ek_map_io,
412 .init_irq = ek_init_irq,
413 .init_machine = ek_board_init,
414MACHINE_END
415
416MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
417 /* Maintainer: Atmel */
360 .boot_params = AT91_SDRAM_BASE + 0x100, 418 .boot_params = AT91_SDRAM_BASE + 0x100,
361 .timer = &at91sam926x_timer, 419 .timer = &at91sam926x_timer,
362 .map_io = ek_map_io, 420 .map_io = ek_map_io,
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index ee800595594d..7913984f6de9 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -135,7 +135,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
135 .rdy_pin = AT91_PIN_PC8, 135 .rdy_pin = AT91_PIN_PC8,
136 .enable_pin = AT91_PIN_PC14, 136 .enable_pin = AT91_PIN_PC14,
137 .partition_info = nand_partitions, 137 .partition_info = nand_partitions,
138#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16) 138#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
139 .bus_width_16 = 1, 139 .bus_width_16 = 1,
140#else 140#else
141 .bus_width_16 = 0, 141 .bus_width_16 = 0,
@@ -399,10 +399,8 @@ static void __init ek_board_init(void)
399 at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led)); 399 at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led));
400} 400}
401 401
402MACHINE_START(AT91SAM9G45EKES, "Atmel AT91SAM9G45-EKES") 402MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
403 /* Maintainer: Atmel */ 403 /* Maintainer: Atmel */
404 .phys_io = AT91_BASE_SYS,
405 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
406 .boot_params = AT91_SDRAM_BASE + 0x100, 404 .boot_params = AT91_SDRAM_BASE + 0x100,
407 .timer = &at91sam926x_timer, 405 .timer = &at91sam926x_timer,
408 .map_io = ek_map_io, 406 .map_io = ek_map_io,
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index 7ac20f3a2067..3bf3408e94c1 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -329,8 +329,6 @@ static void __init ek_board_init(void)
329 329
330MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK") 330MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
331 /* Maintainer: Atmel */ 331 /* Maintainer: Atmel */
332 .phys_io = AT91_BASE_SYS,
333 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
334 .boot_params = AT91_SDRAM_BASE + 0x100, 332 .boot_params = AT91_SDRAM_BASE + 0x100,
335 .timer = &at91sam926x_timer, 333 .timer = &at91sam926x_timer,
336 .map_io = ek_map_io, 334 .map_io = ek_map_io,
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 2c08ae4ad3a1..0a99b3cedd7a 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -177,8 +177,6 @@ static void __init snapper9260_board_init(void)
177} 177}
178 178
179MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module") 179MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
180 .phys_io = AT91_BASE_SYS,
181 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
182 .boot_params = AT91_SDRAM_BASE + 0x100, 180 .boot_params = AT91_SDRAM_BASE + 0x100,
183 .timer = &at91sam926x_timer, 181 .timer = &at91sam926x_timer,
184 .map_io = snapper9260_map_io, 182 .map_io = snapper9260_map_io,
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 87958274290f..5206eef4a67e 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -294,8 +294,6 @@ static void __init stamp9g20_board_init(void)
294 294
295MACHINE_START(PORTUXG20, "taskit PortuxG20") 295MACHINE_START(PORTUXG20, "taskit PortuxG20")
296 /* Maintainer: taskit GmbH */ 296 /* Maintainer: taskit GmbH */
297 .phys_io = AT91_BASE_SYS,
298 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
299 .boot_params = AT91_SDRAM_BASE + 0x100, 297 .boot_params = AT91_SDRAM_BASE + 0x100,
300 .timer = &at91sam926x_timer, 298 .timer = &at91sam926x_timer,
301 .map_io = portuxg20_map_io, 299 .map_io = portuxg20_map_io,
@@ -305,8 +303,6 @@ MACHINE_END
305 303
306MACHINE_START(STAMP9G20, "taskit Stamp9G20") 304MACHINE_START(STAMP9G20, "taskit Stamp9G20")
307 /* Maintainer: taskit GmbH */ 305 /* Maintainer: taskit GmbH */
308 .phys_io = AT91_BASE_SYS,
309 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
310 .boot_params = AT91_SDRAM_BASE + 0x100, 306 .boot_params = AT91_SDRAM_BASE + 0x100,
311 .timer = &at91sam926x_timer, 307 .timer = &at91sam926x_timer,
312 .map_io = stamp9g20_map_io, 308 .map_io = stamp9g20_map_io,
diff --git a/arch/arm/mach-at91/board-usb-a9260.c b/arch/arm/mach-at91/board-usb-a9260.c
index 905d6ef76807..07784baeae84 100644
--- a/arch/arm/mach-at91/board-usb-a9260.c
+++ b/arch/arm/mach-at91/board-usb-a9260.c
@@ -228,8 +228,6 @@ static void __init ek_board_init(void)
228 228
229MACHINE_START(USB_A9260, "CALAO USB_A9260") 229MACHINE_START(USB_A9260, "CALAO USB_A9260")
230 /* Maintainer: calao-systems */ 230 /* Maintainer: calao-systems */
231 .phys_io = AT91_BASE_SYS,
232 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
233 .boot_params = AT91_SDRAM_BASE + 0x100, 231 .boot_params = AT91_SDRAM_BASE + 0x100,
234 .timer = &at91sam926x_timer, 232 .timer = &at91sam926x_timer,
235 .map_io = ek_map_io, 233 .map_io = ek_map_io,
diff --git a/arch/arm/mach-at91/board-usb-a9263.c b/arch/arm/mach-at91/board-usb-a9263.c
index b6a3480383e5..b614508931fd 100644
--- a/arch/arm/mach-at91/board-usb-a9263.c
+++ b/arch/arm/mach-at91/board-usb-a9263.c
@@ -244,8 +244,6 @@ static void __init ek_board_init(void)
244 244
245MACHINE_START(USB_A9263, "CALAO USB_A9263") 245MACHINE_START(USB_A9263, "CALAO USB_A9263")
246 /* Maintainer: calao-systems */ 246 /* Maintainer: calao-systems */
247 .phys_io = AT91_BASE_SYS,
248 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
249 .boot_params = AT91_SDRAM_BASE + 0x100, 247 .boot_params = AT91_SDRAM_BASE + 0x100,
250 .timer = &at91sam926x_timer, 248 .timer = &at91sam926x_timer,
251 .map_io = ek_map_io, 249 .map_io = ek_map_io,
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index e22bf051f835..89df00a9d2f7 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -594,8 +594,6 @@ static void __init yl9200_board_init(void)
594 594
595MACHINE_START(YL9200, "uCdragon YL-9200") 595MACHINE_START(YL9200, "uCdragon YL-9200")
596 /* Maintainer: S.Birtles */ 596 /* Maintainer: S.Birtles */
597 .phys_io = AT91_BASE_SYS,
598 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
599 .boot_params = AT91_SDRAM_BASE + 0x100, 597 .boot_params = AT91_SDRAM_BASE + 0x100,
600 .timer = &at91rm9200_timer, 598 .timer = &at91rm9200_timer,
601 .map_io = yl9200_map_io, 599 .map_io = yl9200_map_io,
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
index d34cdb8abdca..063ac44a0204 100644
--- a/arch/arm/mach-at91/include/mach/at91x40.h
+++ b/arch/arm/mach-at91/include/mach/at91x40.h
@@ -52,4 +52,10 @@
52#define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */ 52#define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */
53#define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */ 53#define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */
54 54
55/*
56 * Support defines for the simple Power Controller module.
57 */
58#define AT91_PS_CR (AT91_PS + 0) /* PS Control register */
59#define AT91_PS_CR_CPU (1 << 0) /* CPU clock disable bit */
60
55#endif /* AT91X40_H */ 61#endif /* AT91X40_H */
diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S
index 9e750a1c1b5a..0f959faf74a9 100644
--- a/arch/arm/mach-at91/include/mach/debug-macro.S
+++ b/arch/arm/mach-at91/include/mach/debug-macro.S
@@ -14,11 +14,9 @@
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <mach/at91_dbgu.h> 15#include <mach/at91_dbgu.h>
16 16
17 .macro addruart, rx, tmp 17 .macro addruart, rp, rv
18 mrc p15, 0, \rx, c1, c0 18 ldr \rp, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address)
19 tst \rx, #1 @ MMU enabled? 19 ldr \rv, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address)
20 ldreq \rx, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address)
21 ldrne \rx, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address)
22 .endm 20 .endm
23 21
24 .macro senduart,rd,rx 22 .macro senduart,rd,rx
diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h
index ee8db152592e..36af14bc13bb 100644
--- a/arch/arm/mach-at91/include/mach/system.h
+++ b/arch/arm/mach-at91/include/mach/system.h
@@ -32,7 +32,11 @@ static inline void arch_idle(void)
32 * Disable the processor clock. The processor will be automatically 32 * Disable the processor clock. The processor will be automatically
33 * re-enabled by an interrupt or by a reset. 33 * re-enabled by an interrupt or by a reset.
34 */ 34 */
35#ifdef AT91_PS
36 at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
37#else
35 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK); 38 at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
39#endif
36#ifndef CONFIG_CPU_ARM920T 40#ifndef CONFIG_CPU_ARM920T
37 /* 41 /*
38 * Set the processor (CP15) into 'Wait for Interrupt' mode. 42 * Set the processor (CP15) into 'Wait for Interrupt' mode.
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
index 2f139196d63d..73eb066d2329 100644
--- a/arch/arm/mach-bcmring/arch.c
+++ b/arch/arm/mach-bcmring/arch.c
@@ -167,8 +167,6 @@ static void __init bcmring_fixup(struct machine_desc *desc,
167 167
168MACHINE_START(BCMRING, "BCMRING") 168MACHINE_START(BCMRING, "BCMRING")
169 /* Maintainer: Broadcom Corporation */ 169 /* Maintainer: Broadcom Corporation */
170 .phys_io = MM_IO_START,
171 .io_pg_offst = (MM_IO_BASE >> 18) & 0xfffc,
172 .fixup = bcmring_fixup, 170 .fixup = bcmring_fixup,
173 .map_io = bcmring_map_io, 171 .map_io = bcmring_map_io,
174 .init_irq = bcmring_init_irq, 172 .init_irq = bcmring_init_irq,
diff --git a/arch/arm/mach-bcmring/include/mach/vmalloc.h b/arch/arm/mach-bcmring/include/mach/vmalloc.h
index 35e2ead8395c..3db3a09fd398 100644
--- a/arch/arm/mach-bcmring/include/mach/vmalloc.h
+++ b/arch/arm/mach-bcmring/include/mach/vmalloc.h
@@ -22,4 +22,4 @@
22 * 0xe0000000 to 0xefffffff. This gives us 256 MB of vm space and handles 22 * 0xe0000000 to 0xefffffff. This gives us 256 MB of vm space and handles
23 * larger physical memory designs better. 23 * larger physical memory designs better.
24 */ 24 */
25#define VMALLOC_END (PAGE_OFFSET + 0x30000000) 25#define VMALLOC_END 0xf0000000
diff --git a/arch/arm/mach-clps711x/autcpu12.c b/arch/arm/mach-clps711x/autcpu12.c
index 5f18eccdc725..4a74b2c959bd 100644
--- a/arch/arm/mach-clps711x/autcpu12.c
+++ b/arch/arm/mach-clps711x/autcpu12.c
@@ -64,8 +64,6 @@ void __init autcpu12_map_io(void)
64 64
65MACHINE_START(AUTCPU12, "autronix autcpu12") 65MACHINE_START(AUTCPU12, "autronix autcpu12")
66 /* Maintainer: Thomas Gleixner */ 66 /* Maintainer: Thomas Gleixner */
67 .phys_io = 0x80000000,
68 .io_pg_offst = ((0xff000000) >> 18) & 0xfffc,
69 .boot_params = 0xc0020000, 67 .boot_params = 0xc0020000,
70 .map_io = autcpu12_map_io, 68 .map_io = autcpu12_map_io,
71 .init_irq = clps711x_init_irq, 69 .init_irq = clps711x_init_irq,
diff --git a/arch/arm/mach-clps711x/cdb89712.c b/arch/arm/mach-clps711x/cdb89712.c
index 71a80b5b8ad6..5a1689d48793 100644
--- a/arch/arm/mach-clps711x/cdb89712.c
+++ b/arch/arm/mach-clps711x/cdb89712.c
@@ -55,8 +55,6 @@ static void __init cdb89712_map_io(void)
55 55
56MACHINE_START(CDB89712, "Cirrus-CDB89712") 56MACHINE_START(CDB89712, "Cirrus-CDB89712")
57 /* Maintainer: Ray Lehtiniemi */ 57 /* Maintainer: Ray Lehtiniemi */
58 .phys_io = 0x80000000,
59 .io_pg_offst = ((0xff000000) >> 18) & 0xfffc,
60 .boot_params = 0xc0000100, 58 .boot_params = 0xc0000100,
61 .map_io = cdb89712_map_io, 59 .map_io = cdb89712_map_io,
62 .init_irq = clps711x_init_irq, 60 .init_irq = clps711x_init_irq,
diff --git a/arch/arm/mach-clps711x/ceiva.c b/arch/arm/mach-clps711x/ceiva.c
index 8ada20184978..16481cf3e931 100644
--- a/arch/arm/mach-clps711x/ceiva.c
+++ b/arch/arm/mach-clps711x/ceiva.c
@@ -56,8 +56,6 @@ static void __init ceiva_map_io(void)
56 56
57MACHINE_START(CEIVA, "CEIVA/Polaroid Photo MAX Digital Picture Frame") 57MACHINE_START(CEIVA, "CEIVA/Polaroid Photo MAX Digital Picture Frame")
58 /* Maintainer: Rob Scott */ 58 /* Maintainer: Rob Scott */
59 .phys_io = 0x80000000,
60 .io_pg_offst = ((0xff000000) >> 18) & 0xfffc,
61 .boot_params = 0xc0000100, 59 .boot_params = 0xc0000100,
62 .map_io = ceiva_map_io, 60 .map_io = ceiva_map_io,
63 .init_irq = clps711x_init_irq, 61 .init_irq = clps711x_init_irq,
diff --git a/arch/arm/mach-clps711x/clep7312.c b/arch/arm/mach-clps711x/clep7312.c
index 3c3bf45039ff..67b5abb4a60a 100644
--- a/arch/arm/mach-clps711x/clep7312.c
+++ b/arch/arm/mach-clps711x/clep7312.c
@@ -37,8 +37,6 @@ fixup_clep7312(struct machine_desc *desc, struct tag *tags,
37 37
38MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312") 38MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
39 /* Maintainer: Nobody */ 39 /* Maintainer: Nobody */
40 .phys_io = 0x80000000,
41 .io_pg_offst = ((0xff000000) >> 18) & 0xfffc,
42 .boot_params = 0xc0000100, 40 .boot_params = 0xc0000100,
43 .fixup = fixup_clep7312, 41 .fixup = fixup_clep7312,
44 .map_io = clps711x_map_io, 42 .map_io = clps711x_map_io,
diff --git a/arch/arm/mach-clps711x/edb7211-arch.c b/arch/arm/mach-clps711x/edb7211-arch.c
index 4a7a2322979a..98ca5b2e940d 100644
--- a/arch/arm/mach-clps711x/edb7211-arch.c
+++ b/arch/arm/mach-clps711x/edb7211-arch.c
@@ -57,8 +57,6 @@ fixup_edb7211(struct machine_desc *desc, struct tag *tags,
57 57
58MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)") 58MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
59 /* Maintainer: Jon McClintock */ 59 /* Maintainer: Jon McClintock */
60 .phys_io = 0x80000000,
61 .io_pg_offst = ((0xff000000) >> 18) & 0xfffc,
62 .boot_params = 0xc0020100, /* 0xc0000000 - 0xc001ffff can be video RAM */ 60 .boot_params = 0xc0020100, /* 0xc0000000 - 0xc001ffff can be video RAM */
63 .fixup = fixup_edb7211, 61 .fixup = fixup_edb7211,
64 .map_io = edb7211_map_io, 62 .map_io = edb7211_map_io,
diff --git a/arch/arm/mach-clps711x/fortunet.c b/arch/arm/mach-clps711x/fortunet.c
index a696099aa4f8..b1cb479e71e9 100644
--- a/arch/arm/mach-clps711x/fortunet.c
+++ b/arch/arm/mach-clps711x/fortunet.c
@@ -75,8 +75,6 @@ fortunet_fixup(struct machine_desc *desc, struct tag *tags,
75 75
76MACHINE_START(FORTUNET, "ARM-FortuNet") 76MACHINE_START(FORTUNET, "ARM-FortuNet")
77 /* Maintainer: FortuNet Inc. */ 77 /* Maintainer: FortuNet Inc. */
78 .phys_io = 0x80000000,
79 .io_pg_offst = ((0xf0000000) >> 18) & 0xfffc,
80 .boot_params = 0x00000000, 78 .boot_params = 0x00000000,
81 .fixup = fortunet_fixup, 79 .fixup = fortunet_fixup,
82 .map_io = clps711x_map_io, 80 .map_io = clps711x_map_io,
diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S
index 072cc6b61ba3..507c6873b7ee 100644
--- a/arch/arm/mach-clps711x/include/mach/debug-macro.S
+++ b/arch/arm/mach-clps711x/include/mach/debug-macro.S
@@ -14,16 +14,14 @@
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <asm/hardware/clps7111.h> 15#include <asm/hardware/clps7111.h>
16 16
17 .macro addruart, rx, tmp 17 .macro addruart, rp, rv
18 mrc p15, 0, \rx, c1, c0
19 tst \rx, #1 @ MMU enabled?
20 moveq \rx, #CLPS7111_PHYS_BASE
21 movne \rx, #CLPS7111_VIRT_BASE
22#ifndef CONFIG_DEBUG_CLPS711X_UART2 18#ifndef CONFIG_DEBUG_CLPS711X_UART2
23 add \rx, \rx, #0x0000 @ UART1 19 mov \rp, #0x0000 @ UART1
24#else 20#else
25 add \rx, \rx, #0x1000 @ UART2 21 mov \rp, #0x1000 @ UART2
26#endif 22#endif
23 orr \rv, \rp, #CLPS7111_VIRT_BASE
24 orr \rp, \rp, #CLPS7111_PHYS_BASE
27 .endm 25 .endm
28 26
29 .macro senduart,rd,rx 27 .macro senduart,rd,rx
diff --git a/arch/arm/mach-clps711x/include/mach/vmalloc.h b/arch/arm/mach-clps711x/include/mach/vmalloc.h
index ea6cc7beff28..30b3a287ed88 100644
--- a/arch/arm/mach-clps711x/include/mach/vmalloc.h
+++ b/arch/arm/mach-clps711x/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20#define VMALLOC_END (PAGE_OFFSET + 0x10000000) 20#define VMALLOC_END 0xd0000000
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c
index 0d94a30fd6fc..cefbce0480b9 100644
--- a/arch/arm/mach-clps711x/p720t.c
+++ b/arch/arm/mach-clps711x/p720t.c
@@ -89,8 +89,6 @@ static void __init p720t_map_io(void)
89 89
90MACHINE_START(P720T, "ARM-Prospector720T") 90MACHINE_START(P720T, "ARM-Prospector720T")
91 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 91 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
92 .phys_io = 0x80000000,
93 .io_pg_offst = ((0xff000000) >> 18) & 0xfffc,
94 .boot_params = 0xc0000100, 92 .boot_params = 0xc0000100,
95 .fixup = fixup_p720t, 93 .fixup = fixup_p720t,
96 .map_io = p720t_map_io, 94 .map_io = p720t_map_io,
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 9df8391fd78a..90fe9ab8591d 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -142,8 +142,6 @@ static void __init cns3420_map_io(void)
142} 142}
143 143
144MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board") 144MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
145 .phys_io = CNS3XXX_UART0_BASE,
146 .io_pg_offst = (CNS3XXX_UART0_BASE_VIRT >> 18) & 0xfffc,
147 .boot_params = 0x00000100, 145 .boot_params = 0x00000100,
148 .map_io = cns3420_map_io, 146 .map_io = cns3420_map_io,
149 .init_irq = cns3xxx_init_irq, 147 .init_irq = cns3xxx_init_irq,
diff --git a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S b/arch/arm/mach-cns3xxx/include/mach/debug-macro.S
index d16ce7eb00e9..56d828634db5 100644
--- a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S
+++ b/arch/arm/mach-cns3xxx/include/mach/debug-macro.S
@@ -10,12 +10,10 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12 12
13 .macro addruart,rx 13 .macro addruart,rp,rv
14 mrc p15, 0, \rx, c1, c0 14 mov \rp, #0x00009000
15 tst \rx, #1 @ MMU enabled? 15 orr \rv, \rp, #0xf0000000 @ virtual base
16 moveq \rx, #0x10000000 16 orr \rp, \rp, #0x10000000
17 movne \rx, #0xf0000000 @ virtual base
18 orr \rx, \rx, #0x00009000
19 .endm 17 .endm
20 18
21#include <asm/hardware/debug-pl01x.S> 19#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index c3994f341e49..7f3cdbfc0fbb 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -597,8 +597,6 @@ static void __init da830_evm_map_io(void)
597} 597}
598 598
599MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137 EVM") 599MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137 EVM")
600 .phys_io = IO_PHYS,
601 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
602 .boot_params = (DA8XX_DDR_BASE + 0x100), 600 .boot_params = (DA8XX_DDR_BASE + 0x100),
603 .map_io = da830_evm_map_io, 601 .map_io = da830_evm_map_io,
604 .init_irq = cp_intc_init, 602 .init_irq = cp_intc_init,
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index fdc2cc500fc6..b26f5cbfce3e 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -817,8 +817,6 @@ static void __init da850_evm_map_io(void)
817} 817}
818 818
819MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM") 819MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138 EVM")
820 .phys_io = IO_PHYS,
821 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
822 .boot_params = (DA8XX_DDR_BASE + 0x100), 820 .boot_params = (DA8XX_DDR_BASE + 0x100),
823 .map_io = da850_evm_map_io, 821 .map_io = da850_evm_map_io,
824 .init_irq = cp_intc_init, 822 .init_irq = cp_intc_init,
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index a3191015efee..6e7cad13352c 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -351,8 +351,6 @@ static __init void dm355_evm_init(void)
351} 351}
352 352
353MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM") 353MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
354 .phys_io = IO_PHYS,
355 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
356 .boot_params = (0x80000100), 354 .boot_params = (0x80000100),
357 .map_io = dm355_evm_map_io, 355 .map_io = dm355_evm_map_io,
358 .init_irq = davinci_irq_init, 356 .init_irq = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index f1d8132cf0c3..543f9911b281 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -270,8 +270,6 @@ static __init void dm355_leopard_init(void)
270} 270}
271 271
272MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard") 272MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
273 .phys_io = IO_PHYS,
274 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
275 .boot_params = (0x80000100), 273 .boot_params = (0x80000100),
276 .map_io = dm355_leopard_map_io, 274 .map_io = dm355_leopard_map_io,
277 .init_irq = davinci_irq_init, 275 .init_irq = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 84acef1d0b3d..944a0cbaf5cb 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -613,8 +613,6 @@ static __init void dm365_evm_init(void)
613} 613}
614 614
615MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM") 615MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
616 .phys_io = IO_PHYS,
617 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
618 .boot_params = (0x80000100), 616 .boot_params = (0x80000100),
619 .map_io = dm365_evm_map_io, 617 .map_io = dm365_evm_map_io,
620 .init_irq = davinci_irq_init, 618 .init_irq = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 34c8b418cd72..d59fba15ba8d 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -706,8 +706,6 @@ static __init void davinci_evm_init(void)
706 706
707MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM") 707MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
708 /* Maintainer: MontaVista Software <source@mvista.com> */ 708 /* Maintainer: MontaVista Software <source@mvista.com> */
709 .phys_io = IO_PHYS,
710 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
711 .boot_params = (DAVINCI_DDR_BASE + 0x100), 709 .boot_params = (DAVINCI_DDR_BASE + 0x100),
712 .map_io = davinci_evm_map_io, 710 .map_io = davinci_evm_map_io,
713 .init_irq = davinci_irq_init, 711 .init_irq = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 4502f346b2b0..6890488fb92b 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -786,8 +786,6 @@ void __init dm646x_board_setup_refclk(struct clk *clk)
786} 786}
787 787
788MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM") 788MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
789 .phys_io = IO_PHYS,
790 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
791 .boot_params = (0x80000100), 789 .boot_params = (0x80000100),
792 .map_io = davinci_map_io, 790 .map_io = davinci_map_io,
793 .init_irq = davinci_irq_init, 791 .init_irq = davinci_irq_init,
@@ -796,8 +794,6 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
796MACHINE_END 794MACHINE_END
797 795
798MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM") 796MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
799 .phys_io = IO_PHYS,
800 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
801 .boot_params = (0x80000100), 797 .boot_params = (0x80000100),
802 .map_io = davinci_map_io, 798 .map_io = davinci_map_io,
803 .init_irq = davinci_irq_init, 799 .init_irq = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 4c30e929bbf9..a4def889275c 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -275,8 +275,6 @@ static __init void davinci_ntosd2_init(void)
275 275
276MACHINE_START(NEUROS_OSD2, "Neuros OSD2") 276MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
277 /* Maintainer: Neuros Technologies <neuros@groups.google.com> */ 277 /* Maintainer: Neuros Technologies <neuros@groups.google.com> */
278 .phys_io = IO_PHYS,
279 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
280 .boot_params = (DAVINCI_DDR_BASE + 0x100), 278 .boot_params = (DAVINCI_DDR_BASE + 0x100),
281 .map_io = davinci_ntosd2_map_io, 279 .map_io = davinci_ntosd2_map_io,
282 .init_irq = davinci_irq_init, 280 .init_irq = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 23e664a1a802..9bdf8aafcc84 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -154,8 +154,6 @@ static __init void davinci_sffsdr_init(void)
154 154
155MACHINE_START(SFFSDR, "Lyrtech SFFSDR") 155MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
156 /* Maintainer: Hugo Villeneuve hugo.villeneuve@lyrtech.com */ 156 /* Maintainer: Hugo Villeneuve hugo.villeneuve@lyrtech.com */
157 .phys_io = IO_PHYS,
158 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
159 .boot_params = (DAVINCI_DDR_BASE + 0x100), 157 .boot_params = (DAVINCI_DDR_BASE + 0x100),
160 .map_io = davinci_sffsdr_map_io, 158 .map_io = davinci_sffsdr_map_io,
161 .init_irq = davinci_irq_init, 159 .init_irq = davinci_irq_init,
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index fe2a9d9c8bb7..b4de35b78904 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -164,8 +164,6 @@ console_initcall(tnetv107x_evm_console_init);
164#endif 164#endif
165 165
166MACHINE_START(TNETV107X, "TNETV107X EVM") 166MACHINE_START(TNETV107X, "TNETV107X EVM")
167 .phys_io = TNETV107X_IO_BASE,
168 .io_pg_offst = (TNETV107X_IO_VIRT >> 18) & 0xfffc,
169 .boot_params = (TNETV107X_DDR_BASE + 0x100), 167 .boot_params = (TNETV107X_DDR_BASE + 0x100),
170 .map_io = tnetv107x_init, 168 .map_io = tnetv107x_init,
171 .init_irq = cp_intc_init, 169 .init_irq = cp_intc_init,
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index f761dfdb8689..9f1befc5ac38 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -29,35 +29,39 @@ davinci_uart_phys: .word 0
29davinci_uart_virt: .word 0 29davinci_uart_virt: .word 0
30 .popsection 30 .popsection
31 31
32 .macro addruart, rx, tmp 32 .macro addruart, rp, rv
33 33
34 /* Use davinci_uart_phys/virt if already configured */ 34 /* Use davinci_uart_phys/virt if already configured */
3510: mrc p15, 0, \rx, c1, c0 3510: mrc p15, 0, \rp, c1, c0
36 tst \rx, #1 @ MMU enabled? 36 tst \rp, #1 @ MMU enabled?
37 ldreq \rx, =__virt_to_phys(davinci_uart_phys) 37 ldreq \rp, =__virt_to_phys(davinci_uart_phys)
38 ldrne \rx, =davinci_uart_virt 38 ldrne \rp, =davinci_uart_phys
39 ldr \rx, [\rx] 39 add \rv, \rp, #4 @ davinci_uart_virt
40 cmp \rx, #0 @ is port configured? 40 ldr \rp, [\rp, #0]
41 ldr \rv, [\rv, #0]
42 cmp \rp, #0 @ is port configured?
43 cmpne \rv, #0
41 bne 99f @ already configured 44 bne 99f @ already configured
42 45
43 mrc p15, 0, \rx, c1, c0 46 /* Check the debug UART address set in uncompress.h */
44 tst \rx, #1 @ MMU enabled? 47 mrc p15, 0, \rp, c1, c0
48 tst \rp, #1 @ MMU enabled?
45 49
46 /* Copy uart phys address from decompressor uart info */ 50 /* Copy uart phys address from decompressor uart info */
47 ldreq \tmp, =__virt_to_phys(davinci_uart_phys) 51 ldreq \rv, =__virt_to_phys(davinci_uart_phys)
48 ldrne \tmp, =davinci_uart_phys 52 ldrne \rv, =davinci_uart_phys
49 ldreq \rx, =DAVINCI_UART_INFO 53 ldreq \rp, =DAVINCI_UART_INFO
50 ldrne \rx, =__phys_to_virt(DAVINCI_UART_INFO) 54 ldrne \rp, =__phys_to_virt(DAVINCI_UART_INFO)
51 ldr \rx, [\rx, #0] 55 ldr \rp, [\rp, #0]
52 str \rx, [\tmp] 56 str \rp, [\rv]
53 57
54 /* Copy uart virt address from decompressor uart info */ 58 /* Copy uart virt address from decompressor uart info */
55 ldreq \tmp, =__virt_to_phys(davinci_uart_virt) 59 ldreq \rv, =__virt_to_phys(davinci_uart_virt)
56 ldrne \tmp, =davinci_uart_virt 60 ldrne \rv, =davinci_uart_virt
57 ldreq \rx, =DAVINCI_UART_INFO 61 ldreq \rp, =DAVINCI_UART_INFO
58 ldrne \rx, =__phys_to_virt(DAVINCI_UART_INFO) 62 ldrne \rp, =__phys_to_virt(DAVINCI_UART_INFO)
59 ldr \rx, [\rx, #4] 63 ldr \rp, [\rp, #4]
60 str \rx, [\tmp] 64 str \rp, [\rv]
61 65
62 b 10b 66 b 10b
6399: 6799:
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index bef70460fbc6..95925aa76dd9 100644
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -94,8 +94,6 @@ static void __init dove_db_init(void)
94} 94}
95 95
96MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board") 96MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
97 .phys_io = DOVE_SB_REGS_PHYS_BASE,
98 .io_pg_offst = ((DOVE_SB_REGS_VIRT_BASE) >> 18) & 0xfffc,
99 .boot_params = 0x00000100, 97 .boot_params = 0x00000100,
100 .init_machine = dove_db_init, 98 .init_machine = dove_db_init,
101 .map_io = dove_map_io, 99 .map_io = dove_map_io,
diff --git a/arch/arm/mach-dove/include/mach/debug-macro.S b/arch/arm/mach-dove/include/mach/debug-macro.S
index 1521d13f1d14..da8bf2bad3b1 100644
--- a/arch/arm/mach-dove/include/mach/debug-macro.S
+++ b/arch/arm/mach-dove/include/mach/debug-macro.S
@@ -8,12 +8,11 @@
8 8
9#include <mach/bridge-regs.h> 9#include <mach/bridge-regs.h>
10 10
11 .macro addruart, rx, tmp 11 .macro addruart, rp, rv
12 mrc p15, 0, \rx, c1, c0 12 ldr \rp, =DOVE_SB_REGS_PHYS_BASE
13 tst \rx, #1 @ MMU enabled? 13 ldr \rv, =DOVE_SB_REGS_VIRT_BASE
14 ldreq \rx, =DOVE_SB_REGS_PHYS_BASE 14 orr \rp, \rp, #0x00012000
15 ldrne \rx, =DOVE_SB_REGS_VIRT_BASE 15 orr \rv, \rv, #0x00012000
16 orr \rx, \rx, #0x00012000
17 .endm 16 .endm
18 17
19#define UART_SHIFT 2 18#define UART_SHIFT 2
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index c7bc7fbb11a6..5df4099fc14f 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -280,8 +280,6 @@ arch_initcall(ebsa110_init);
280 280
281MACHINE_START(EBSA110, "EBSA110") 281MACHINE_START(EBSA110, "EBSA110")
282 /* Maintainer: Russell King */ 282 /* Maintainer: Russell King */
283 .phys_io = 0xe0000000,
284 .io_pg_offst = ((0xe0000000) >> 18) & 0xfffc,
285 .boot_params = 0x00000400, 283 .boot_params = 0x00000400,
286 .reserve_lp0 = 1, 284 .reserve_lp0 = 1,
287 .reserve_lp2 = 1, 285 .reserve_lp2 = 1,
diff --git a/arch/arm/mach-ebsa110/include/mach/debug-macro.S b/arch/arm/mach-ebsa110/include/mach/debug-macro.S
index ebbd89f0e6c0..7ef5690fd08c 100644
--- a/arch/arm/mach-ebsa110/include/mach/debug-macro.S
+++ b/arch/arm/mach-ebsa110/include/mach/debug-macro.S
@@ -11,9 +11,10 @@
11 * 11 *
12**/ 12**/
13 13
14 .macro addruart, rx, tmp 14 .macro addruart, rp, rv
15 mov \rx, #0xf0000000 15 mov \rp, #0xf0000000
16 orr \rx, \rx, #0x00000be0 16 orr \rp, \rp, #0x00000be0
17 mov \rp, \rv
17 .endm 18 .endm
18 19
19#define UART_SHIFT 2 20#define UART_SHIFT 2
diff --git a/arch/arm/mach-ebsa110/include/mach/vmalloc.h b/arch/arm/mach-ebsa110/include/mach/vmalloc.h
index 9b44c19e95ec..60bde56fba4c 100644
--- a/arch/arm/mach-ebsa110/include/mach/vmalloc.h
+++ b/arch/arm/mach-ebsa110/include/mach/vmalloc.h
@@ -7,4 +7,4 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10#define VMALLOC_END (PAGE_OFFSET + 0x1f000000) 10#define VMALLOC_END 0xdf000000
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index f744f676783f..61b98ce4b673 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -33,8 +33,6 @@ static void __init adssphere_init_machine(void)
33 33
34MACHINE_START(ADSSPHERE, "ADS Sphere board") 34MACHINE_START(ADSSPHERE, "ADS Sphere board")
35 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 35 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
36 .phys_io = EP93XX_APB_PHYS_BASE,
37 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
38 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 36 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
39 .map_io = ep93xx_map_io, 37 .map_io = ep93xx_map_io,
40 .init_irq = ep93xx_init_irq, 38 .init_irq = ep93xx_init_irq,
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index c2ce9034ba87..4b0431652131 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -124,8 +124,6 @@ static void __init edb93xx_init_machine(void)
124#ifdef CONFIG_MACH_EDB9301 124#ifdef CONFIG_MACH_EDB9301
125MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board") 125MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board")
126 /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */ 126 /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
127 .phys_io = EP93XX_APB_PHYS_BASE,
128 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
129 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 127 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
130 .map_io = ep93xx_map_io, 128 .map_io = ep93xx_map_io,
131 .init_irq = ep93xx_init_irq, 129 .init_irq = ep93xx_init_irq,
@@ -137,8 +135,6 @@ MACHINE_END
137#ifdef CONFIG_MACH_EDB9302 135#ifdef CONFIG_MACH_EDB9302
138MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board") 136MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
139 /* Maintainer: George Kashperko <george@chas.com.ua> */ 137 /* Maintainer: George Kashperko <george@chas.com.ua> */
140 .phys_io = EP93XX_APB_PHYS_BASE,
141 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
142 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 138 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
143 .map_io = ep93xx_map_io, 139 .map_io = ep93xx_map_io,
144 .init_irq = ep93xx_init_irq, 140 .init_irq = ep93xx_init_irq,
@@ -150,8 +146,6 @@ MACHINE_END
150#ifdef CONFIG_MACH_EDB9302A 146#ifdef CONFIG_MACH_EDB9302A
151MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board") 147MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
152 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 148 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
153 .phys_io = EP93XX_APB_PHYS_BASE,
154 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
155 .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, 149 .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100,
156 .map_io = ep93xx_map_io, 150 .map_io = ep93xx_map_io,
157 .init_irq = ep93xx_init_irq, 151 .init_irq = ep93xx_init_irq,
@@ -163,8 +157,6 @@ MACHINE_END
163#ifdef CONFIG_MACH_EDB9307 157#ifdef CONFIG_MACH_EDB9307
164MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board") 158MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board")
165 /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */ 159 /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
166 .phys_io = EP93XX_APB_PHYS_BASE,
167 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
168 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 160 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
169 .map_io = ep93xx_map_io, 161 .map_io = ep93xx_map_io,
170 .init_irq = ep93xx_init_irq, 162 .init_irq = ep93xx_init_irq,
@@ -176,8 +168,6 @@ MACHINE_END
176#ifdef CONFIG_MACH_EDB9307A 168#ifdef CONFIG_MACH_EDB9307A
177MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board") 169MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board")
178 /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */ 170 /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
179 .phys_io = EP93XX_APB_PHYS_BASE,
180 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
181 .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, 171 .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100,
182 .map_io = ep93xx_map_io, 172 .map_io = ep93xx_map_io,
183 .init_irq = ep93xx_init_irq, 173 .init_irq = ep93xx_init_irq,
@@ -189,8 +179,6 @@ MACHINE_END
189#ifdef CONFIG_MACH_EDB9312 179#ifdef CONFIG_MACH_EDB9312
190MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board") 180MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board")
191 /* Maintainer: Toufeeq Hussain <toufeeq_hussain@infosys.com> */ 181 /* Maintainer: Toufeeq Hussain <toufeeq_hussain@infosys.com> */
192 .phys_io = EP93XX_APB_PHYS_BASE,
193 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
194 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 182 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
195 .map_io = ep93xx_map_io, 183 .map_io = ep93xx_map_io,
196 .init_irq = ep93xx_init_irq, 184 .init_irq = ep93xx_init_irq,
@@ -202,8 +190,6 @@ MACHINE_END
202#ifdef CONFIG_MACH_EDB9315 190#ifdef CONFIG_MACH_EDB9315
203MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board") 191MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board")
204 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 192 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
205 .phys_io = EP93XX_APB_PHYS_BASE,
206 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
207 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 193 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
208 .map_io = ep93xx_map_io, 194 .map_io = ep93xx_map_io,
209 .init_irq = ep93xx_init_irq, 195 .init_irq = ep93xx_init_irq,
@@ -215,8 +201,6 @@ MACHINE_END
215#ifdef CONFIG_MACH_EDB9315A 201#ifdef CONFIG_MACH_EDB9315A
216MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board") 202MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
217 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 203 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
218 .phys_io = EP93XX_APB_PHYS_BASE,
219 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
220 .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, 204 .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100,
221 .map_io = ep93xx_map_io, 205 .map_io = ep93xx_map_io,
222 .init_irq = ep93xx_init_irq, 206 .init_irq = ep93xx_init_irq,
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index d97168c0ba33..9bd3152bff9a 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -33,8 +33,6 @@ static void __init gesbc9312_init_machine(void)
33 33
34MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx") 34MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx")
35 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 35 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
36 .phys_io = EP93XX_APB_PHYS_BASE,
37 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
38 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 36 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
39 .map_io = ep93xx_map_io, 37 .map_io = ep93xx_map_io,
40 .init_irq = ep93xx_init_irq, 38 .init_irq = ep93xx_init_irq,
diff --git a/arch/arm/mach-ep93xx/include/mach/debug-macro.S b/arch/arm/mach-ep93xx/include/mach/debug-macro.S
index 5cd22444e223..b25bc9076367 100644
--- a/arch/arm/mach-ep93xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ep93xx/include/mach/debug-macro.S
@@ -11,12 +11,11 @@
11 */ 11 */
12#include <mach/ep93xx-regs.h> 12#include <mach/ep93xx-regs.h>
13 13
14 .macro addruart, rx, tmp 14 .macro addruart, rp, rv
15 mrc p15, 0, \rx, c1, c0 15 ldr \rp, =EP93XX_APB_PHYS_BASE @ Physical base
16 tst \rx, #1 @ MMU enabled? 16 ldr \rv, =EP93XX_APB_VIRT_BASE @ virtual base
17 ldreq \rx, =EP93XX_APB_PHYS_BASE @ Physical base 17 orr \rp, \rp, #0x000c0000
18 ldrne \rx, =EP93XX_APB_VIRT_BASE @ virtual base 18 orr \rv, \rv, #0x000c0000
19 orr \rx, \rx, #0x000c0000
20 .endm 19 .endm
21 20
22#include <asm/hardware/debug-pl01x.S> 21#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index 2ba776320a82..7adea6258efe 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -77,8 +77,6 @@ static void __init micro9_init_machine(void)
77#ifdef CONFIG_MACH_MICRO9H 77#ifdef CONFIG_MACH_MICRO9H
78MACHINE_START(MICRO9, "Contec Micro9-High") 78MACHINE_START(MICRO9, "Contec Micro9-High")
79 /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */ 79 /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
80 .phys_io = EP93XX_APB_PHYS_BASE,
81 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
82 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 80 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
83 .map_io = ep93xx_map_io, 81 .map_io = ep93xx_map_io,
84 .init_irq = ep93xx_init_irq, 82 .init_irq = ep93xx_init_irq,
@@ -90,8 +88,6 @@ MACHINE_END
90#ifdef CONFIG_MACH_MICRO9M 88#ifdef CONFIG_MACH_MICRO9M
91MACHINE_START(MICRO9M, "Contec Micro9-Mid") 89MACHINE_START(MICRO9M, "Contec Micro9-Mid")
92 /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */ 90 /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
93 .phys_io = EP93XX_APB_PHYS_BASE,
94 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
95 .boot_params = EP93XX_SDCE3_PHYS_BASE_ASYNC + 0x100, 91 .boot_params = EP93XX_SDCE3_PHYS_BASE_ASYNC + 0x100,
96 .map_io = ep93xx_map_io, 92 .map_io = ep93xx_map_io,
97 .init_irq = ep93xx_init_irq, 93 .init_irq = ep93xx_init_irq,
@@ -103,8 +99,6 @@ MACHINE_END
103#ifdef CONFIG_MACH_MICRO9L 99#ifdef CONFIG_MACH_MICRO9L
104MACHINE_START(MICRO9L, "Contec Micro9-Lite") 100MACHINE_START(MICRO9L, "Contec Micro9-Lite")
105 /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */ 101 /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
106 .phys_io = EP93XX_APB_PHYS_BASE,
107 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
108 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 102 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
109 .map_io = ep93xx_map_io, 103 .map_io = ep93xx_map_io,
110 .init_irq = ep93xx_init_irq, 104 .init_irq = ep93xx_init_irq,
@@ -116,8 +110,6 @@ MACHINE_END
116#ifdef CONFIG_MACH_MICRO9S 110#ifdef CONFIG_MACH_MICRO9S
117MACHINE_START(MICRO9S, "Contec Micro9-Slim") 111MACHINE_START(MICRO9S, "Contec Micro9-Slim")
118 /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */ 112 /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
119 .phys_io = EP93XX_APB_PHYS_BASE,
120 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
121 .boot_params = EP93XX_SDCE3_PHYS_BASE_ASYNC + 0x100, 113 .boot_params = EP93XX_SDCE3_PHYS_BASE_ASYNC + 0x100,
122 .map_io = ep93xx_map_io, 114 .map_io = ep93xx_map_io,
123 .init_irq = ep93xx_init_irq, 115 .init_irq = ep93xx_init_irq,
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index 5dded5884133..f22ce8db7947 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -65,8 +65,6 @@ static void __init simone_init_machine(void)
65 65
66MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board") 66MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board")
67/* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */ 67/* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */
68 .phys_io = EP93XX_APB_PHYS_BASE,
69 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
70 .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, 68 .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100,
71 .map_io = ep93xx_map_io, 69 .map_io = ep93xx_map_io,
72 .init_irq = ep93xx_init_irq, 70 .init_irq = ep93xx_init_irq,
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index a12c89301297..ac601fe2b448 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -163,8 +163,6 @@ static void __init snappercl15_init_machine(void)
163 163
164MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15") 164MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
165 /* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */ 165 /* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */
166 .phys_io = EP93XX_APB_PHYS_BASE,
167 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
168 .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, 166 .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100,
169 .map_io = ep93xx_map_io, 167 .map_io = ep93xx_map_io,
170 .init_irq = ep93xx_init_irq, 168 .init_irq = ep93xx_init_irq,
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 93aeab8af705..c2d2cf40ead9 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -257,8 +257,6 @@ static void __init ts72xx_init_machine(void)
257 257
258MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC") 258MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
259 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 259 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
260 .phys_io = EP93XX_APB_PHYS_BASE,
261 .io_pg_offst = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
262 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 260 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100,
263 .map_io = ts72xx_map_io, 261 .map_io = ts72xx_map_io,
264 .init_irq = ep93xx_init_irq, 262 .init_irq = ep93xx_init_irq,
diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c
index 1b996b26d2e0..5b1a8db779be 100644
--- a/arch/arm/mach-footbridge/cats-hw.c
+++ b/arch/arm/mach-footbridge/cats-hw.c
@@ -86,8 +86,6 @@ fixup_cats(struct machine_desc *desc, struct tag *tags,
86 86
87MACHINE_START(CATS, "Chalice-CATS") 87MACHINE_START(CATS, "Chalice-CATS")
88 /* Maintainer: Philip Blundell */ 88 /* Maintainer: Philip Blundell */
89 .phys_io = DC21285_ARMCSR_BASE,
90 .io_pg_offst = ((0xfe000000) >> 18) & 0xfffc,
91 .boot_params = 0x00000100, 89 .boot_params = 0x00000100,
92 .soft_reboot = 1, 90 .soft_reboot = 1,
93 .fixup = fixup_cats, 91 .fixup = fixup_cats,
diff --git a/arch/arm/mach-footbridge/ebsa285.c b/arch/arm/mach-footbridge/ebsa285.c
index 30040fd588cc..2ef69ff44ba8 100644
--- a/arch/arm/mach-footbridge/ebsa285.c
+++ b/arch/arm/mach-footbridge/ebsa285.c
@@ -15,8 +15,6 @@
15 15
16MACHINE_START(EBSA285, "EBSA285") 16MACHINE_START(EBSA285, "EBSA285")
17 /* Maintainer: Russell King */ 17 /* Maintainer: Russell King */
18 .phys_io = DC21285_ARMCSR_BASE,
19 .io_pg_offst = ((0xfe000000) >> 18) & 0xfffc,
20 .boot_params = 0x00000100, 18 .boot_params = 0x00000100,
21 .video_start = 0x000a0000, 19 .video_start = 0x000a0000,
22 .video_end = 0x000bffff, 20 .video_end = 0x000bffff,
diff --git a/arch/arm/mach-footbridge/include/mach/debug-macro.S b/arch/arm/mach-footbridge/include/mach/debug-macro.S
index 60dda1318f22..3c9e0c40c679 100644
--- a/arch/arm/mach-footbridge/include/mach/debug-macro.S
+++ b/arch/arm/mach-footbridge/include/mach/debug-macro.S
@@ -15,12 +15,10 @@
15 15
16#ifndef CONFIG_DEBUG_DC21285_PORT 16#ifndef CONFIG_DEBUG_DC21285_PORT
17 /* For NetWinder debugging */ 17 /* For NetWinder debugging */
18 .macro addruart, rx, tmp 18 .macro addruart, rp, rv
19 mrc p15, 0, \rx, c1, c0 19 mov \rp, #0x000003f8
20 tst \rx, #1 @ MMU enabled? 20 orr \rv, \rp, #0x7c000000 @ physical
21 moveq \rx, #0x7c000000 @ physical 21 orr \rp, \rp, #0xff000000 @ virtual
22 movne \rx, #0xff000000 @ virtual
23 orr \rx, \rx, #0x000003f8
24 .endm 22 .endm
25 23
26#define UART_SHIFT 0 24#define UART_SHIFT 0
@@ -32,14 +30,14 @@
32 .equ dc21285_high, ARMCSR_BASE & 0xff000000 30 .equ dc21285_high, ARMCSR_BASE & 0xff000000
33 .equ dc21285_low, ARMCSR_BASE & 0x00ffffff 31 .equ dc21285_low, ARMCSR_BASE & 0x00ffffff
34 32
35 .macro addruart, rx, tmp 33 .macro addruart, rp, rv
36 mrc p15, 0, \rx, c1, c0
37 tst \rx, #1 @ MMU enabled?
38 moveq \rx, #0x42000000
39 movne \rx, #dc21285_high
40 .if dc21285_low 34 .if dc21285_low
41 orrne \rx, \rx, #dc21285_low 35 mov \rp, #dc21285_low
36 .else
37 mov \rp, #0
42 .endif 38 .endif
39 orr \rv, \rp, #0x42000000
40 orr \rp, \rp, #dc21285_high
43 .endm 41 .endm
44 42
45 .macro senduart,rd,rx 43 .macro senduart,rd,rx
diff --git a/arch/arm/mach-footbridge/include/mach/vmalloc.h b/arch/arm/mach-footbridge/include/mach/vmalloc.h
index d0958d860a3c..0ffbb7c85e59 100644
--- a/arch/arm/mach-footbridge/include/mach/vmalloc.h
+++ b/arch/arm/mach-footbridge/include/mach/vmalloc.h
@@ -7,4 +7,4 @@
7 */ 7 */
8 8
9 9
10#define VMALLOC_END (PAGE_OFFSET + 0x30000000) 10#define VMALLOC_END 0xf0000000
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index ac7ffa6fc413..06e514f372d0 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -648,8 +648,6 @@ fixup_netwinder(struct machine_desc *desc, struct tag *tags,
648 648
649MACHINE_START(NETWINDER, "Rebel-NetWinder") 649MACHINE_START(NETWINDER, "Rebel-NetWinder")
650 /* Maintainer: Russell King/Rebel.com */ 650 /* Maintainer: Russell King/Rebel.com */
651 .phys_io = DC21285_ARMCSR_BASE,
652 .io_pg_offst = ((0xfe000000) >> 18) & 0xfffc,
653 .boot_params = 0x00000100, 651 .boot_params = 0x00000100,
654 .video_start = 0x000a0000, 652 .video_start = 0x000a0000,
655 .video_end = 0x000bffff, 653 .video_end = 0x000bffff,
diff --git a/arch/arm/mach-footbridge/personal.c b/arch/arm/mach-footbridge/personal.c
index e2c9f0690b16..3285e91ca8c1 100644
--- a/arch/arm/mach-footbridge/personal.c
+++ b/arch/arm/mach-footbridge/personal.c
@@ -15,8 +15,6 @@
15 15
16MACHINE_START(PERSONAL_SERVER, "Compaq-PersonalServer") 16MACHINE_START(PERSONAL_SERVER, "Compaq-PersonalServer")
17 /* Maintainer: Jamey Hicks / George France */ 17 /* Maintainer: Jamey Hicks / George France */
18 .phys_io = DC21285_ARMCSR_BASE,
19 .io_pg_offst = ((0xfe000000) >> 18) & 0xfffc,
20 .boot_params = 0x00000100, 18 .boot_params = 0x00000100,
21 .map_io = footbridge_map_io, 19 .map_io = footbridge_map_io,
22 .init_irq = footbridge_init_irq, 20 .init_irq = footbridge_init_irq,
diff --git a/arch/arm/mach-gemini/board-nas4220b.c b/arch/arm/mach-gemini/board-nas4220b.c
index 01f1d6daab44..2ba096de0034 100644
--- a/arch/arm/mach-gemini/board-nas4220b.c
+++ b/arch/arm/mach-gemini/board-nas4220b.c
@@ -101,8 +101,6 @@ static void __init ib4220b_init(void)
101} 101}
102 102
103MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B") 103MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
104 .phys_io = 0x7fffc000,
105 .io_pg_offst = ((0xffffc000) >> 18) & 0xfffc,
106 .boot_params = 0x100, 104 .boot_params = 0x100,
107 .map_io = gemini_map_io, 105 .map_io = gemini_map_io,
108 .init_irq = gemini_init_irq, 106 .init_irq = gemini_init_irq,
diff --git a/arch/arm/mach-gemini/board-rut1xx.c b/arch/arm/mach-gemini/board-rut1xx.c
index e0de968e32a6..a9a0d8b01942 100644
--- a/arch/arm/mach-gemini/board-rut1xx.c
+++ b/arch/arm/mach-gemini/board-rut1xx.c
@@ -85,8 +85,6 @@ static void __init rut1xx_init(void)
85} 85}
86 86
87MACHINE_START(RUT100, "Teltonika RUT100") 87MACHINE_START(RUT100, "Teltonika RUT100")
88 .phys_io = 0x7fffc000,
89 .io_pg_offst = ((0xffffc000) >> 18) & 0xfffc,
90 .boot_params = 0x100, 88 .boot_params = 0x100,
91 .map_io = gemini_map_io, 89 .map_io = gemini_map_io,
92 .init_irq = gemini_init_irq, 90 .init_irq = gemini_init_irq,
diff --git a/arch/arm/mach-gemini/board-wbd111.c b/arch/arm/mach-gemini/board-wbd111.c
index 36538c15b3c4..8b88d50d4337 100644
--- a/arch/arm/mach-gemini/board-wbd111.c
+++ b/arch/arm/mach-gemini/board-wbd111.c
@@ -133,8 +133,6 @@ static void __init wbd111_init(void)
133} 133}
134 134
135MACHINE_START(WBD111, "Wiliboard WBD-111") 135MACHINE_START(WBD111, "Wiliboard WBD-111")
136 .phys_io = 0x7fffc000,
137 .io_pg_offst = ((0xffffc000) >> 18) & 0xfffc,
138 .boot_params = 0x100, 136 .boot_params = 0x100,
139 .map_io = gemini_map_io, 137 .map_io = gemini_map_io,
140 .init_irq = gemini_init_irq, 138 .init_irq = gemini_init_irq,
diff --git a/arch/arm/mach-gemini/board-wbd222.c b/arch/arm/mach-gemini/board-wbd222.c
index ece8b4c65110..1eebcecd1c33 100644
--- a/arch/arm/mach-gemini/board-wbd222.c
+++ b/arch/arm/mach-gemini/board-wbd222.c
@@ -133,8 +133,6 @@ static void __init wbd222_init(void)
133} 133}
134 134
135MACHINE_START(WBD222, "Wiliboard WBD-222") 135MACHINE_START(WBD222, "Wiliboard WBD-222")
136 .phys_io = 0x7fffc000,
137 .io_pg_offst = ((0xffffc000) >> 18) & 0xfffc,
138 .boot_params = 0x100, 136 .boot_params = 0x100,
139 .map_io = gemini_map_io, 137 .map_io = gemini_map_io,
140 .init_irq = gemini_init_irq, 138 .init_irq = gemini_init_irq,
diff --git a/arch/arm/mach-gemini/include/mach/debug-macro.S b/arch/arm/mach-gemini/include/mach/debug-macro.S
index ad477047069d..f40e006d296e 100644
--- a/arch/arm/mach-gemini/include/mach/debug-macro.S
+++ b/arch/arm/mach-gemini/include/mach/debug-macro.S
@@ -11,11 +11,9 @@
11 */ 11 */
12#include <mach/hardware.h> 12#include <mach/hardware.h>
13 13
14 .macro addruart, rx, tmp 14 .macro addruart, rp, rv
15 mrc p15, 0, \rx, c1, c0 15 ldr \rp, =GEMINI_UART_BASE @ physical
16 tst \rx, #1 @ MMU enabled? 16 ldr \rv, =IO_ADDRESS(GEMINI_UART_BASE) @ virtual
17 ldreq \rx, =GEMINI_UART_BASE @ physical
18 ldrne \rx, =IO_ADDRESS(GEMINI_UART_BASE) @ virtual
19 .endm 17 .endm
20 18
21#define UART_SHIFT 2 19#define UART_SHIFT 2
diff --git a/arch/arm/mach-h720x/h7201-eval.c b/arch/arm/mach-h720x/h7201-eval.c
index 78be457dc324..79f0b896e446 100644
--- a/arch/arm/mach-h720x/h7201-eval.c
+++ b/arch/arm/mach-h720x/h7201-eval.c
@@ -30,8 +30,6 @@
30 30
31MACHINE_START(H7201, "Hynix GMS30C7201") 31MACHINE_START(H7201, "Hynix GMS30C7201")
32 /* Maintainer: Robert Schwebel, Pengutronix */ 32 /* Maintainer: Robert Schwebel, Pengutronix */
33 .phys_io = 0x80000000,
34 .io_pg_offst = ((0xf0000000) >> 18) & 0xfffc,
35 .boot_params = 0xc0001000, 33 .boot_params = 0xc0001000,
36 .map_io = h720x_map_io, 34 .map_io = h720x_map_io,
37 .init_irq = h720x_init_irq, 35 .init_irq = h720x_init_irq,
diff --git a/arch/arm/mach-h720x/h7202-eval.c b/arch/arm/mach-h720x/h7202-eval.c
index 8c0ba99d683f..cc28b1efe047 100644
--- a/arch/arm/mach-h720x/h7202-eval.c
+++ b/arch/arm/mach-h720x/h7202-eval.c
@@ -72,8 +72,6 @@ static void __init init_eval_h7202(void)
72 72
73MACHINE_START(H7202, "Hynix HMS30C7202") 73MACHINE_START(H7202, "Hynix HMS30C7202")
74 /* Maintainer: Robert Schwebel, Pengutronix */ 74 /* Maintainer: Robert Schwebel, Pengutronix */
75 .phys_io = 0x80000000,
76 .io_pg_offst = ((0xf0000000) >> 18) & 0xfffc,
77 .boot_params = 0x40000100, 75 .boot_params = 0x40000100,
78 .map_io = h720x_map_io, 76 .map_io = h720x_map_io,
79 .init_irq = h7202_init_irq, 77 .init_irq = h7202_init_irq,
diff --git a/arch/arm/mach-h720x/include/mach/debug-macro.S b/arch/arm/mach-h720x/include/mach/debug-macro.S
index 27cafd12f033..c2093e835720 100644
--- a/arch/arm/mach-h720x/include/mach/debug-macro.S
+++ b/arch/arm/mach-h720x/include/mach/debug-macro.S
@@ -16,12 +16,10 @@
16 .equ io_virt, IO_VIRT 16 .equ io_virt, IO_VIRT
17 .equ io_phys, IO_PHYS 17 .equ io_phys, IO_PHYS
18 18
19 .macro addruart, rx, tmp 19 .macro addruart, rp, rv
20 mrc p15, 0, \rx, c1, c0 20 mov \rp, #0x00020000 @ UART1
21 tst \rx, #1 @ MMU enabled? 21 add \rv, \rp, #io_virt @ virtual address
22 moveq \rx, #io_phys @ physical base address 22 add \rp, \rp, #io_phys @ physical base address
23 movne \rx, #io_virt @ virtual address
24 add \rx, \rx, #0x00020000 @ UART1
25 .endm 23 .endm
26 24
27 .macro senduart,rd,rx 25 .macro senduart,rd,rx
diff --git a/arch/arm/mach-h720x/include/mach/vmalloc.h b/arch/arm/mach-h720x/include/mach/vmalloc.h
index ff1460d6841b..a45915b88756 100644
--- a/arch/arm/mach-h720x/include/mach/vmalloc.h
+++ b/arch/arm/mach-h720x/include/mach/vmalloc.h
@@ -5,6 +5,6 @@
5#ifndef __ARCH_ARM_VMALLOC_H 5#ifndef __ARCH_ARM_VMALLOC_H
6#define __ARCH_ARM_VMALLOC_H 6#define __ARCH_ARM_VMALLOC_H
7 7
8#define VMALLOC_END (PAGE_OFFSET + 0x10000000) 8#define VMALLOC_END 0xd0000000
9 9
10#endif 10#endif
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 2f7e2728970d..197f9e241cff 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -147,8 +147,8 @@ choice
147 default MACH_EUKREA_MBIMX27_BASEBOARD 147 default MACH_EUKREA_MBIMX27_BASEBOARD
148 148
149config MACH_EUKREA_MBIMX27_BASEBOARD 149config MACH_EUKREA_MBIMX27_BASEBOARD
150 prompt "Eukrea MBIMX27 development board" 150 bool "Eukrea MBIMX27 development board"
151 bool 151 select IMX_HAVE_PLATFORM_IMX_SSI
152 select IMX_HAVE_PLATFORM_IMX_UART 152 select IMX_HAVE_PLATFORM_IMX_UART
153 select IMX_HAVE_PLATFORM_SPI_IMX 153 select IMX_HAVE_PLATFORM_SPI_IMX
154 help 154 help
@@ -164,6 +164,15 @@ config MACH_MX27_3DS
164 Include support for MX27PDK platform. This includes specific 164 Include support for MX27PDK platform. This includes specific
165 configurations for the board and its peripherals. 165 configurations for the board and its peripherals.
166 166
167config MACH_IMX27_VISSTRIM_M10
168 bool "Vista Silicon i.MX27 Visstrim_m10"
169 select IMX_HAVE_PLATFORM_IMX_I2C
170 select IMX_HAVE_PLATFORM_IMX_UART
171 help
172 Include support for Visstrim_m10 platform and its different variants.
173 This includes specific configurations for the board and its
174 peripherals.
175
167config MACH_IMX27LITE 176config MACH_IMX27LITE
168 bool "LogicPD MX27 LITEKIT platform" 177 bool "LogicPD MX27 LITEKIT platform"
169 select IMX_HAVE_PLATFORM_IMX_UART 178 select IMX_HAVE_PLATFORM_IMX_UART
@@ -174,6 +183,7 @@ config MACH_IMX27LITE
174config MACH_PCA100 183config MACH_PCA100
175 bool "Phytec phyCARD-s (pca100)" 184 bool "Phytec phyCARD-s (pca100)"
176 select IMX_HAVE_PLATFORM_IMX_I2C 185 select IMX_HAVE_PLATFORM_IMX_I2C
186 select IMX_HAVE_PLATFORM_IMX_SSI
177 select IMX_HAVE_PLATFORM_IMX_UART 187 select IMX_HAVE_PLATFORM_IMX_UART
178 select IMX_HAVE_PLATFORM_MXC_NAND 188 select IMX_HAVE_PLATFORM_MXC_NAND
179 select IMX_HAVE_PLATFORM_SPI_IMX 189 select IMX_HAVE_PLATFORM_SPI_IMX
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 46a9fdfbbd15..5582692bb176 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
27obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o 27obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
28obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o 28obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
29obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o 29obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o
30obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o
30obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o 31obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
31obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o 32obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
32obj-$(CONFIG_MACH_PCA100) += mach-pca100.o 33obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
diff --git a/arch/arm/mach-imx/clock-imx1.c b/arch/arm/mach-imx/clock-imx1.c
index c05096c38301..daca30b2d5b1 100644
--- a/arch/arm/mach-imx/clock-imx1.c
+++ b/arch/arm/mach-imx/clock-imx1.c
@@ -592,7 +592,7 @@ static struct clk_lookup lookups[] __initdata = {
592 _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk) 592 _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk)
593 _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk) 593 _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
594 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) 594 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
595 _REGISTER_CLOCK("spi_imx.0", NULL, spi_clk) 595 _REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk)
596 _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk) 596 _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
597 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) 597 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
598 _REGISTER_CLOCK(NULL, "mshc", mshc_clk) 598 _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
diff --git a/arch/arm/mach-imx/clock-imx21.c b/arch/arm/mach-imx/clock-imx21.c
index bb419ef4d133..cf15ea516a72 100644
--- a/arch/arm/mach-imx/clock-imx21.c
+++ b/arch/arm/mach-imx/clock-imx21.c
@@ -1172,9 +1172,9 @@ static struct clk_lookup lookups[] = {
1172 _REGISTER_CLOCK(NULL, "pwm", pwm_clk[0]) 1172 _REGISTER_CLOCK(NULL, "pwm", pwm_clk[0])
1173 _REGISTER_CLOCK(NULL, "sdhc1", sdhc_clk[0]) 1173 _REGISTER_CLOCK(NULL, "sdhc1", sdhc_clk[0])
1174 _REGISTER_CLOCK(NULL, "sdhc2", sdhc_clk[1]) 1174 _REGISTER_CLOCK(NULL, "sdhc2", sdhc_clk[1])
1175 _REGISTER_CLOCK(NULL, "cspi1", cspi_clk[0]) 1175 _REGISTER_CLOCK("imx21-cspi.0", NULL, cspi_clk[0])
1176 _REGISTER_CLOCK(NULL, "cspi2", cspi_clk[1]) 1176 _REGISTER_CLOCK("imx21-cspi.1", NULL, cspi_clk[1])
1177 _REGISTER_CLOCK(NULL, "cspi3", cspi_clk[2]) 1177 _REGISTER_CLOCK("imx21-cspi.2", NULL, cspi_clk[2])
1178 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0]) 1178 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0])
1179 _REGISTER_CLOCK(NULL, "csi", csi_clk[0]) 1179 _REGISTER_CLOCK(NULL, "csi", csi_clk[0])
1180 _REGISTER_CLOCK("imx21-hcd.0", NULL, usb_clk[0]) 1180 _REGISTER_CLOCK("imx21-hcd.0", NULL, usb_clk[0])
diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c
index 5a1aa15c8a16..98a25bada783 100644
--- a/arch/arm/mach-imx/clock-imx27.c
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -594,27 +594,27 @@ DEFINE_CLOCK(uart2_clk1, 0, PCCR1, 30, NULL, NULL, &ipg_clk);
594DEFINE_CLOCK(uart1_clk1, 0, PCCR1, 31, NULL, NULL, &ipg_clk); 594DEFINE_CLOCK(uart1_clk1, 0, PCCR1, 31, NULL, NULL, &ipg_clk);
595 595
596/* Clocks we cannot directly gate, but drivers need their rates */ 596/* Clocks we cannot directly gate, but drivers need their rates */
597DEFINE_CLOCK(cspi1_clk, 0, 0, 0, NULL, &cspi1_clk1, &per2_clk); 597DEFINE_CLOCK(cspi1_clk, 0, NULL, 0, NULL, &cspi1_clk1, &per2_clk);
598DEFINE_CLOCK(cspi2_clk, 1, 0, 0, NULL, &cspi2_clk1, &per2_clk); 598DEFINE_CLOCK(cspi2_clk, 1, NULL, 0, NULL, &cspi2_clk1, &per2_clk);
599DEFINE_CLOCK(cspi3_clk, 2, 0, 0, NULL, &cspi13_clk1, &per2_clk); 599DEFINE_CLOCK(cspi3_clk, 2, NULL, 0, NULL, &cspi13_clk1, &per2_clk);
600DEFINE_CLOCK(sdhc1_clk, 0, 0, 0, NULL, &sdhc1_clk1, &per2_clk); 600DEFINE_CLOCK(sdhc1_clk, 0, NULL, 0, NULL, &sdhc1_clk1, &per2_clk);
601DEFINE_CLOCK(sdhc2_clk, 1, 0, 0, NULL, &sdhc2_clk1, &per2_clk); 601DEFINE_CLOCK(sdhc2_clk, 1, NULL, 0, NULL, &sdhc2_clk1, &per2_clk);
602DEFINE_CLOCK(sdhc3_clk, 2, 0, 0, NULL, &sdhc3_clk1, &per2_clk); 602DEFINE_CLOCK(sdhc3_clk, 2, NULL, 0, NULL, &sdhc3_clk1, &per2_clk);
603DEFINE_CLOCK(pwm_clk, 0, 0, 0, NULL, &pwm_clk1, &per1_clk); 603DEFINE_CLOCK(pwm_clk, 0, NULL, 0, NULL, &pwm_clk1, &per1_clk);
604DEFINE_CLOCK(gpt1_clk, 0, 0, 0, NULL, &gpt1_clk1, &per1_clk); 604DEFINE_CLOCK(gpt1_clk, 0, NULL, 0, NULL, &gpt1_clk1, &per1_clk);
605DEFINE_CLOCK(gpt2_clk, 1, 0, 0, NULL, &gpt2_clk1, &per1_clk); 605DEFINE_CLOCK(gpt2_clk, 1, NULL, 0, NULL, &gpt2_clk1, &per1_clk);
606DEFINE_CLOCK(gpt3_clk, 2, 0, 0, NULL, &gpt3_clk1, &per1_clk); 606DEFINE_CLOCK(gpt3_clk, 2, NULL, 0, NULL, &gpt3_clk1, &per1_clk);
607DEFINE_CLOCK(gpt4_clk, 3, 0, 0, NULL, &gpt4_clk1, &per1_clk); 607DEFINE_CLOCK(gpt4_clk, 3, NULL, 0, NULL, &gpt4_clk1, &per1_clk);
608DEFINE_CLOCK(gpt5_clk, 4, 0, 0, NULL, &gpt5_clk1, &per1_clk); 608DEFINE_CLOCK(gpt5_clk, 4, NULL, 0, NULL, &gpt5_clk1, &per1_clk);
609DEFINE_CLOCK(gpt6_clk, 5, 0, 0, NULL, &gpt6_clk1, &per1_clk); 609DEFINE_CLOCK(gpt6_clk, 5, NULL, 0, NULL, &gpt6_clk1, &per1_clk);
610DEFINE_CLOCK(uart1_clk, 0, 0, 0, NULL, &uart1_clk1, &per1_clk); 610DEFINE_CLOCK(uart1_clk, 0, NULL, 0, NULL, &uart1_clk1, &per1_clk);
611DEFINE_CLOCK(uart2_clk, 1, 0, 0, NULL, &uart2_clk1, &per1_clk); 611DEFINE_CLOCK(uart2_clk, 1, NULL, 0, NULL, &uart2_clk1, &per1_clk);
612DEFINE_CLOCK(uart3_clk, 2, 0, 0, NULL, &uart3_clk1, &per1_clk); 612DEFINE_CLOCK(uart3_clk, 2, NULL, 0, NULL, &uart3_clk1, &per1_clk);
613DEFINE_CLOCK(uart4_clk, 3, 0, 0, NULL, &uart4_clk1, &per1_clk); 613DEFINE_CLOCK(uart4_clk, 3, NULL, 0, NULL, &uart4_clk1, &per1_clk);
614DEFINE_CLOCK(uart5_clk, 4, 0, 0, NULL, &uart5_clk1, &per1_clk); 614DEFINE_CLOCK(uart5_clk, 4, NULL, 0, NULL, &uart5_clk1, &per1_clk);
615DEFINE_CLOCK(uart6_clk, 5, 0, 0, NULL, &uart6_clk1, &per1_clk); 615DEFINE_CLOCK(uart6_clk, 5, NULL, 0, NULL, &uart6_clk1, &per1_clk);
616DEFINE_CLOCK1(lcdc_clk, 0, 0, 0, parent, &lcdc_clk1, &per3_clk); 616DEFINE_CLOCK1(lcdc_clk, 0, NULL, 0, parent, &lcdc_clk1, &per3_clk);
617DEFINE_CLOCK1(csi_clk, 0, 0, 0, parent, &csi_clk1, &per4_clk); 617DEFINE_CLOCK1(csi_clk, 0, NULL, 0, parent, &csi_clk1, &per4_clk);
618 618
619#define _REGISTER_CLOCK(d, n, c) \ 619#define _REGISTER_CLOCK(d, n, c) \
620 { \ 620 { \
@@ -640,9 +640,9 @@ static struct clk_lookup lookups[] = {
640 _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk) 640 _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
641 _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk) 641 _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
642 _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk) 642 _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk)
643 _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) 643 _REGISTER_CLOCK("imx27-cspi.0", NULL, cspi1_clk)
644 _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) 644 _REGISTER_CLOCK("imx27-cspi.1", NULL, cspi2_clk)
645 _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk) 645 _REGISTER_CLOCK("imx27-cspi.2", NULL, cspi3_clk)
646 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) 646 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
647 _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk) 647 _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
648 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk) 648 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
index a8d94f078196..81979486218e 100644
--- a/arch/arm/mach-imx/devices-imx1.h
+++ b/arch/arm/mach-imx/devices-imx1.h
@@ -9,10 +9,12 @@
9#include <mach/mx1.h> 9#include <mach/mx1.h>
10#include <mach/devices-common.h> 10#include <mach/devices-common.h>
11 11
12#define imx1_add_i2c_imx(pdata) \ 12extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst;
13 imx_add_imx_i2c(0, MX1_I2C_BASE_ADDR, SZ_4K, MX1_INT_I2C, pdata) 13#define imx1_add_imx_i2c(pdata) \
14 imx_add_imx_i2c(&imx1_imx_i2c_data, pdata)
14 15
15#define imx1_add_imx_uart0(pdata) \ 16extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst;
16 imx_add_imx_uart_3irq(0, MX1_UART1_BASE_ADDR, 0xd0, MX1_INT_UART1RX, MX1_INT_UART1TX, MX1_INT_UART1RTS, pdata) 17#define imx1_add_imx_uart(id, pdata) \
17#define imx1_add_imx_uart1(pdata) \ 18 imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata)
18 imx_add_imx_uart_3irq(0, MX1_UART2_BASE_ADDR, 0xd0, MX1_INT_UART2RX, MX1_INT_UART2TX, MX1_INT_UART2RTS, pdata) 19#define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata)
20#define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata)
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
index 42788e99d127..d189039749b0 100644
--- a/arch/arm/mach-imx/devices-imx21.h
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -9,22 +9,28 @@
9#include <mach/mx21.h> 9#include <mach/mx21.h>
10#include <mach/devices-common.h> 10#include <mach/devices-common.h>
11 11
12#define imx21_add_i2c_imx(pdata) \ 12extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst;
13 imx_add_imx_i2c(0, MX2x_I2C_BASE_ADDR, SZ_4K, MX2x_INT_I2C, pdata) 13#define imx21_add_imx_i2c(pdata) \
14 imx_add_imx_i2c(&imx21_imx_i2c_data, pdata)
14 15
15#define imx21_add_imx_uart0(pdata) \ 16extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst;
16 imx_add_imx_uart_1irq(0, MX21_UART1_BASE_ADDR, SZ_4K, MX21_INT_UART1, pdata) 17#define imx21_add_imx_ssi(id, pdata) \
17#define imx21_add_imx_uart1(pdata) \ 18 imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata)
18 imx_add_imx_uart_1irq(1, MX21_UART2_BASE_ADDR, SZ_4K, MX21_INT_UART2, pdata)
19#define imx21_add_imx_uart2(pdata) \
20 imx_add_imx_uart_1irq(2, MX21_UART3_BASE_ADDR, SZ_4K, MX21_INT_UART3, pdata)
21#define imx21_add_imx_uart3(pdata) \
22 imx_add_imx_uart_1irq(3, MX21_UART4_BASE_ADDR, SZ_4K, MX21_INT_UART4, pdata)
23 19
20extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst;
21#define imx21_add_imx_uart(id, pdata) \
22 imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata)
23#define imx21_add_imx_uart0(pdata) imx21_add_imx_uart(0, pdata)
24#define imx21_add_imx_uart1(pdata) imx21_add_imx_uart(1, pdata)
25#define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata)
26#define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata)
27
28extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst;
24#define imx21_add_mxc_nand(pdata) \ 29#define imx21_add_mxc_nand(pdata) \
25 imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata) 30 imx_add_mxc_nand(&imx21_mxc_nand_data, pdata)
26 31
27#define imx21_add_spi_imx0(pdata) \ 32extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst;
28 imx_add_spi_imx(0, MX21_CSPI1_BASE_ADDR, SZ_4K, MX21_INT_CSPI1, pdata) 33#define imx21_add_cspi(id, pdata) \
29#define imx21_add_spi_imx1(pdata) \ 34 imx_add_spi_imx(&imx21_cspi_data[id], pdata)
30 imx_add_spi_imx(1, MX21_CSPI2_BASE_ADDR, SZ_4K, MX21_INT_CSPI2, pdata) 35#define imx21_add_spi_imx0(pdata) imx21_add_cspi(0, pdata)
36#define imx21_add_spi_imx1(pdata) imx21_add_cspi(1, pdata)
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 65e7bb7ec2e8..7011690364f2 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -9,30 +9,35 @@
9#include <mach/mx27.h> 9#include <mach/mx27.h>
10#include <mach/devices-common.h> 10#include <mach/devices-common.h>
11 11
12#define imx27_add_i2c_imx0(pdata) \ 12extern const struct imx_fec_data imx27_fec_data __initconst;
13 imx_add_imx_i2c(0, MX27_I2C1_BASE_ADDR, SZ_4K, MX27_INT_I2C1, pdata) 13#define imx27_add_fec(pdata) \
14#define imx27_add_i2c_imx1(pdata) \ 14 imx_add_fec(&imx27_fec_data, pdata)
15 imx_add_imx_i2c(1, MX27_I2C2_BASE_ADDR, SZ_4K, MX27_INT_I2C2, pdata)
16 15
17#define imx27_add_imx_uart0(pdata) \ 16extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst;
18 imx_add_imx_uart_1irq(0, MX27_UART1_BASE_ADDR, SZ_4K, MX27_INT_UART1, pdata) 17#define imx27_add_imx_i2c(id, pdata) \
19#define imx27_add_imx_uart1(pdata) \ 18 imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata)
20 imx_add_imx_uart_1irq(1, MX27_UART2_BASE_ADDR, SZ_4K, MX27_INT_UART2, pdata)
21#define imx27_add_imx_uart2(pdata) \
22 imx_add_imx_uart_1irq(2, MX27_UART3_BASE_ADDR, SZ_4K, MX27_INT_UART3, pdata)
23#define imx27_add_imx_uart3(pdata) \
24 imx_add_imx_uart_1irq(3, MX27_UART4_BASE_ADDR, SZ_4K, MX27_INT_UART4, pdata)
25#define imx27_add_imx_uart4(pdata) \
26 imx_add_imx_uart_1irq(4, MX27_UART5_BASE_ADDR, SZ_4K, MX27_INT_UART5, pdata)
27#define imx27_add_imx_uart5(pdata) \
28 imx_add_imx_uart_1irq(5, MX27_UART6_BASE_ADDR, SZ_4K, MX27_INT_UART6, pdata)
29 19
20extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst;
21#define imx27_add_imx_ssi(id, pdata) \
22 imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata)
23
24extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst;
25#define imx27_add_imx_uart(id, pdata) \
26 imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata)
27#define imx27_add_imx_uart0(pdata) imx27_add_imx_uart(0, pdata)
28#define imx27_add_imx_uart1(pdata) imx27_add_imx_uart(1, pdata)
29#define imx27_add_imx_uart2(pdata) imx27_add_imx_uart(2, pdata)
30#define imx27_add_imx_uart3(pdata) imx27_add_imx_uart(3, pdata)
31#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata)
32#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata)
33
34extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst;
30#define imx27_add_mxc_nand(pdata) \ 35#define imx27_add_mxc_nand(pdata) \
31 imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata) 36 imx_add_mxc_nand(&imx27_mxc_nand_data, pdata)
32 37
33#define imx27_add_spi_imx0(pdata) \ 38extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst;
34 imx_add_spi_imx(0, MX27_CSPI1_BASE_ADDR, SZ_4K, MX27_INT_CSPI1, pdata) 39#define imx27_add_cspi(id, pdata) \
35#define imx27_add_spi_imx1(pdata) \ 40 imx_add_spi_imx(&imx27_cspi_data[id], pdata)
36 imx_add_spi_imx(1, MX27_CSPI2_BASE_ADDR, SZ_4K, MX27_INT_CSPI2, pdata) 41#define imx27_add_spi_imx0(pdata) imx27_add_cspi(0, pdata)
37#define imx27_add_spi_imx2(pdata) \ 42#define imx27_add_spi_imx1(pdata) imx27_add_cspi(1, pdata)
38 imx_add_spi_imx(2, MX27_CSPI3_BASE_ADDR, SZ_4K, MX27_INT_CSPI3, pdata) 43#define imx27_add_spi_imx2(pdata) imx27_add_cspi(2, pdata)
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index 9c271a752b84..fba5047de8b1 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -314,27 +314,6 @@ struct platform_device mxc_fb_device = {
314 }, 314 },
315}; 315};
316 316
317#ifdef CONFIG_MACH_MX27
318static struct resource mxc_fec_resources[] = {
319 {
320 .start = MX27_FEC_BASE_ADDR,
321 .end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
322 .flags = IORESOURCE_MEM,
323 }, {
324 .start = MX27_INT_FEC,
325 .end = MX27_INT_FEC,
326 .flags = IORESOURCE_IRQ,
327 },
328};
329
330struct platform_device mxc_fec_device = {
331 .name = "fec",
332 .id = 0,
333 .num_resources = ARRAY_SIZE(mxc_fec_resources),
334 .resource = mxc_fec_resources,
335};
336#endif
337
338static struct resource mxc_pwm_resources[] = { 317static struct resource mxc_pwm_resources[] = {
339 { 318 {
340 .start = MX2x_PWM_BASE_ADDR, 319 .start = MX2x_PWM_BASE_ADDR,
@@ -480,41 +459,6 @@ struct platform_device mxc_usbh2 = {
480}; 459};
481#endif 460#endif
482 461
483#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
484 { \
485 .name = _name, \
486 .start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
487 .end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
488 .flags = IORESOURCE_DMA, \
489 }
490
491#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
492 static struct resource imx_ssi_resources ## n[] = { \
493 { \
494 .start = MX2x_SSI ## ssin ## _BASE_ADDR, \
495 .end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
496 .flags = IORESOURCE_MEM, \
497 }, { \
498 .start = MX2x_INT_SSI1, \
499 .end = MX2x_INT_SSI1, \
500 .flags = IORESOURCE_IRQ, \
501 }, \
502 DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
503 DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
504 DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
505 DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
506 }; \
507 \
508 struct platform_device imx_ssi_device ## n = { \
509 .name = "imx-ssi", \
510 .id = n, \
511 .num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
512 .resource = imx_ssi_resources ## n, \
513 }
514
515DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
516DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
517
518/* GPIO port description */ 462/* GPIO port description */
519#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \ 463#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
520 { \ 464 { \
diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h
index efd4527506a5..807f02a031c9 100644
--- a/arch/arm/mach-imx/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -16,7 +16,6 @@ extern struct platform_device mxc_gpt5;
16extern struct platform_device mxc_wdt; 16extern struct platform_device mxc_wdt;
17extern struct platform_device mxc_w1_master_device; 17extern struct platform_device mxc_w1_master_device;
18extern struct platform_device mxc_fb_device; 18extern struct platform_device mxc_fb_device;
19extern struct platform_device mxc_fec_device;
20extern struct platform_device mxc_pwm_device; 19extern struct platform_device mxc_pwm_device;
21extern struct platform_device mxc_sdhc_device0; 20extern struct platform_device mxc_sdhc_device0;
22extern struct platform_device mxc_sdhc_device1; 21extern struct platform_device mxc_sdhc_device1;
@@ -26,7 +25,5 @@ extern struct platform_device mxc_otg_host;
26extern struct platform_device mxc_usbh1; 25extern struct platform_device mxc_usbh1;
27extern struct platform_device mxc_usbh2; 26extern struct platform_device mxc_usbh2;
28extern struct platform_device mx21_usbhc_device; 27extern struct platform_device mx21_usbhc_device;
29extern struct platform_device imx_ssi_device0;
30extern struct platform_device imx_ssi_device1;
31extern struct platform_device imx_kpp_device; 28extern struct platform_device imx_kpp_device;
32#endif 29#endif
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 4edc5f439201..026263c665ca 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -36,13 +36,12 @@
36#include <mach/hardware.h> 36#include <mach/hardware.h>
37#include <mach/mmc.h> 37#include <mach/mmc.h>
38#include <mach/spi.h> 38#include <mach/spi.h>
39#include <mach/ssi.h>
40#include <mach/audmux.h> 39#include <mach/audmux.h>
41 40
42#include "devices-imx27.h" 41#include "devices-imx27.h"
43#include "devices.h" 42#include "devices.h"
44 43
45static int eukrea_mbimx27_pins[] = { 44static const int eukrea_mbimx27_pins[] __initconst = {
46 /* UART2 */ 45 /* UART2 */
47 PE3_PF_UART2_CTS, 46 PE3_PF_UART2_CTS,
48 PE4_PF_UART2_RTS, 47 PE4_PF_UART2_RTS,
@@ -311,7 +310,8 @@ static struct imxmmc_platform_data sdhc_pdata = {
311 .dat3_card_detect = 1, 310 .dat3_card_detect = 1,
312}; 311};
313 312
314struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata = { 313static const
314struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata __initconst = {
315 .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE, 315 .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE,
316}; 316};
317 317
@@ -357,7 +357,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
357 i2c_register_board_info(0, eukrea_mbimx27_i2c_devices, 357 i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
358 ARRAY_SIZE(eukrea_mbimx27_i2c_devices)); 358 ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
359 359
360 mxc_register_device(&imx_ssi_device0, &eukrea_mbimx27_ssi_pdata); 360 imx27_add_imx_ssi(0, &eukrea_mbimx27_ssi_pdata);
361 361
362#if defined(CONFIG_TOUCHSCREEN_ADS7846) \ 362#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
363 || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) 363 || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 6830afd1d2ba..745ee60fb068 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -46,7 +46,7 @@
46#include "devices-imx27.h" 46#include "devices-imx27.h"
47#include "devices.h" 47#include "devices.h"
48 48
49static int eukrea_cpuimx27_pins[] = { 49static const int eukrea_cpuimx27_pins[] __initconst = {
50 /* UART1 */ 50 /* UART1 */
51 PE12_PF_UART1_TXD, 51 PE12_PF_UART1_TXD,
52 PE13_PF_UART1_RXD, 52 PE13_PF_UART1_RXD,
@@ -157,7 +157,6 @@ cpuimx27_nand_board_info __initconst = {
157 157
158static struct platform_device *platform_devices[] __initdata = { 158static struct platform_device *platform_devices[] __initdata = {
159 &eukrea_cpuimx27_nor_mtd_device, 159 &eukrea_cpuimx27_nor_mtd_device,
160 &mxc_fec_device,
161 &mxc_wdt, 160 &mxc_wdt,
162 &mxc_w1_master_device, 161 &mxc_w1_master_device,
163}; 162};
@@ -259,8 +258,9 @@ static void __init eukrea_cpuimx27_init(void)
259 i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices, 258 i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
260 ARRAY_SIZE(eukrea_cpuimx27_i2c_devices)); 259 ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
261 260
262 imx27_add_i2c_imx0(&cpuimx27_i2c1_data); 261 imx27_add_imx_i2c(0, &cpuimx27_i2c1_data);
263 262
263 imx27_add_fec(NULL);
264 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 264 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
265 265
266#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) 266#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
@@ -307,8 +307,6 @@ static struct sys_timer eukrea_cpuimx27_timer = {
307}; 307};
308 308
309MACHINE_START(CPUIMX27, "EUKREA CPUIMX27") 309MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
310 .phys_io = MX27_AIPI_BASE_ADDR,
311 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
312 .boot_params = MX27_PHYS_OFFSET + 0x100, 310 .boot_params = MX27_PHYS_OFFSET + 0x100,
313 .map_io = mx27_map_io, 311 .map_io = mx27_map_io,
314 .init_irq = mx27_init_irq, 312 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
new file mode 100644
index 000000000000..59716fab586d
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -0,0 +1,261 @@
1/*
2 * mach-imx27_visstrim_m10.c
3 *
4 * Copyright 2010 Javier Martin <javier.martin@vista-silicon.com>
5 *
6 * Based on mach-pcm038.c, mach-pca100.c, mach-mx27ads.c and others.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
21 * MA 02110-1301, USA.
22 */
23
24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26#include <linux/platform_device.h>
27#include <linux/mtd/physmap.h>
28#include <linux/i2c.h>
29#include <linux/i2c/pca953x.h>
30#include <linux/gpio_keys.h>
31#include <linux/input.h>
32#include <linux/gpio.h>
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/time.h>
36#include <mach/common.h>
37#include <mach/mmc.h>
38#include <mach/iomux.h>
39#include <mach/mxc_ehci.h>
40
41#include "devices-imx27.h"
42#include "devices.h"
43
44#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
45#define SDHC1_IRQ IRQ_GPIOB(25)
46
47static const int visstrim_m10_pins[] __initconst = {
48 /* UART1 (console) */
49 PE12_PF_UART1_TXD,
50 PE13_PF_UART1_RXD,
51 PE14_PF_UART1_CTS,
52 PE15_PF_UART1_RTS,
53 /* FEC */
54 PD0_AIN_FEC_TXD0,
55 PD1_AIN_FEC_TXD1,
56 PD2_AIN_FEC_TXD2,
57 PD3_AIN_FEC_TXD3,
58 PD4_AOUT_FEC_RX_ER,
59 PD5_AOUT_FEC_RXD1,
60 PD6_AOUT_FEC_RXD2,
61 PD7_AOUT_FEC_RXD3,
62 PD8_AF_FEC_MDIO,
63 PD9_AIN_FEC_MDC,
64 PD10_AOUT_FEC_CRS,
65 PD11_AOUT_FEC_TX_CLK,
66 PD12_AOUT_FEC_RXD0,
67 PD13_AOUT_FEC_RX_DV,
68 PD14_AOUT_FEC_RX_CLK,
69 PD15_AOUT_FEC_COL,
70 PD16_AIN_FEC_TX_ER,
71 PF23_AIN_FEC_TX_EN,
72 /* SDHC1 */
73 PE18_PF_SD1_D0,
74 PE19_PF_SD1_D1,
75 PE20_PF_SD1_D2,
76 PE21_PF_SD1_D3,
77 PE22_PF_SD1_CMD,
78 PE23_PF_SD1_CLK,
79 /* Both I2Cs */
80 PD17_PF_I2C_DATA,
81 PD18_PF_I2C_CLK,
82 PC5_PF_I2C2_SDA,
83 PC6_PF_I2C2_SCL,
84 /* USB OTG */
85 OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
86 PC9_PF_USBOTG_DATA0,
87 PC11_PF_USBOTG_DATA1,
88 PC10_PF_USBOTG_DATA2,
89 PC13_PF_USBOTG_DATA3,
90 PC12_PF_USBOTG_DATA4,
91 PC7_PF_USBOTG_DATA5,
92 PC8_PF_USBOTG_DATA6,
93 PE25_PF_USBOTG_DATA7,
94 PE24_PF_USBOTG_CLK,
95 PE2_PF_USBOTG_DIR,
96 PE0_PF_USBOTG_NXT,
97 PE1_PF_USBOTG_STP,
98 PB23_PF_USB_PWR,
99 PB24_PF_USB_OC,
100};
101
102/* GPIOs used as events for applications */
103static struct gpio_keys_button visstrim_gpio_keys[] = {
104 {
105 .type = EV_KEY,
106 .code = KEY_RESTART,
107 .gpio = (GPIO_PORTC + 15),
108 .desc = "Default config",
109 .active_low = 0,
110 .wakeup = 1,
111 },
112 {
113 .type = EV_KEY,
114 .code = KEY_RECORD,
115 .gpio = (GPIO_PORTF + 14),
116 .desc = "Record",
117 .active_low = 0,
118 .wakeup = 1,
119 },
120 {
121 .type = EV_KEY,
122 .code = KEY_STOP,
123 .gpio = (GPIO_PORTF + 13),
124 .desc = "Stop",
125 .active_low = 0,
126 .wakeup = 1,
127 }
128};
129
130static struct gpio_keys_platform_data visstrim_gpio_keys_platform_data = {
131 .buttons = visstrim_gpio_keys,
132 .nbuttons = ARRAY_SIZE(visstrim_gpio_keys),
133};
134
135static struct platform_device visstrim_gpio_keys_device = {
136 .name = "gpio-keys",
137 .id = -1,
138 .dev = {
139 .platform_data = &visstrim_gpio_keys_platform_data,
140 },
141};
142
143/* Visstrim_SM10 has a microSD slot connected to sdhc1 */
144static int visstrim_m10_sdhc1_init(struct device *dev,
145 irq_handler_t detect_irq, void *data)
146{
147 int ret;
148
149 ret = request_irq(SDHC1_IRQ, detect_irq, IRQF_TRIGGER_FALLING,
150 "mmc-detect", data);
151 return ret;
152}
153
154static void visstrim_m10_sdhc1_exit(struct device *dev, void *data)
155{
156 free_irq(SDHC1_IRQ, data);
157}
158
159static struct imxmmc_platform_data visstrim_m10_sdhc_pdata = {
160 .init = visstrim_m10_sdhc1_init,
161 .exit = visstrim_m10_sdhc1_exit,
162};
163
164/* Visstrim_SM10 NOR flash */
165static struct physmap_flash_data visstrim_m10_flash_data = {
166 .width = 2,
167};
168
169static struct resource visstrim_m10_flash_resource = {
170 .start = 0xc0000000,
171 .end = 0xc0000000 + SZ_64M - 1,
172 .flags = IORESOURCE_MEM,
173};
174
175static struct platform_device visstrim_m10_nor_mtd_device = {
176 .name = "physmap-flash",
177 .id = 0,
178 .dev = {
179 .platform_data = &visstrim_m10_flash_data,
180 },
181 .num_resources = 1,
182 .resource = &visstrim_m10_flash_resource,
183};
184
185static struct platform_device *platform_devices[] __initdata = {
186 &visstrim_gpio_keys_device,
187 &visstrim_m10_nor_mtd_device,
188};
189
190/* Visstrim_M10 uses UART0 as console */
191static const struct imxuart_platform_data uart_pdata __initconst = {
192 .flags = IMXUART_HAVE_RTSCTS,
193};
194
195/* I2C */
196static const struct imxi2c_platform_data visstrim_m10_i2c_data __initconst = {
197 .bitrate = 100000,
198};
199
200static struct pca953x_platform_data visstrim_m10_pca9555_pdata = {
201 .gpio_base = 240, /* After MX27 internal GPIOs */
202 .invert = 0,
203};
204
205static struct i2c_board_info visstrim_m10_i2c_devices[] = {
206 {
207 I2C_BOARD_INFO("pca9555", 0x20),
208 .platform_data = &visstrim_m10_pca9555_pdata,
209 },
210};
211
212/* USB OTG */
213static int otg_phy_init(struct platform_device *pdev)
214{
215 gpio_set_value(OTG_PHY_CS_GPIO, 0);
216 return 0;
217}
218
219static struct mxc_usbh_platform_data visstrim_m10_usbotg_pdata = {
220 .init = otg_phy_init,
221 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
222 .flags = MXC_EHCI_POWER_PINS_ENABLED,
223};
224
225static void __init visstrim_m10_board_init(void)
226{
227 int ret;
228
229 ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins,
230 ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10");
231 if (ret)
232 pr_err("Failed to setup pins (%d)\n", ret);
233
234 imx27_add_imx_uart0(&uart_pdata);
235
236 i2c_register_board_info(0, visstrim_m10_i2c_devices,
237 ARRAY_SIZE(visstrim_m10_i2c_devices));
238 imx27_add_imx_i2c(0, &visstrim_m10_i2c_data);
239 imx27_add_imx_i2c(1, &visstrim_m10_i2c_data);
240 mxc_register_device(&mxc_sdhc_device0, &visstrim_m10_sdhc_pdata);
241 mxc_register_device(&mxc_otg_host, &visstrim_m10_usbotg_pdata);
242 imx27_add_fec(NULL);
243 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
244}
245
246static void __init visstrim_m10_timer_init(void)
247{
248 mx27_clocks_init((unsigned long)25000000);
249}
250
251static struct sys_timer visstrim_m10_timer = {
252 .init = visstrim_m10_timer_init,
253};
254
255MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
256 .boot_params = MX27_PHYS_OFFSET + 0x100,
257 .map_io = mx27_map_io,
258 .init_irq = mx27_init_irq,
259 .init_machine = visstrim_m10_board_init,
260 .timer = &visstrim_m10_timer,
261MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index 22a2b5d91213..bbdbc75127d3 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -27,7 +27,7 @@
27#include "devices-imx27.h" 27#include "devices-imx27.h"
28#include "devices.h" 28#include "devices.h"
29 29
30static unsigned int mx27lite_pins[] = { 30static const int mx27lite_pins[] __initconst = {
31 /* UART1 */ 31 /* UART1 */
32 PE12_PF_UART1_TXD, 32 PE12_PF_UART1_TXD,
33 PE13_PF_UART1_RXD, 33 PE13_PF_UART1_RXD,
@@ -58,16 +58,12 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
58 .flags = IMXUART_HAVE_RTSCTS, 58 .flags = IMXUART_HAVE_RTSCTS,
59}; 59};
60 60
61static struct platform_device *platform_devices[] __initdata = {
62 &mxc_fec_device,
63};
64
65static void __init mx27lite_init(void) 61static void __init mx27lite_init(void)
66{ 62{
67 mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins), 63 mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
68 "imx27lite"); 64 "imx27lite");
69 imx27_add_imx_uart0(&uart_pdata); 65 imx27_add_imx_uart0(&uart_pdata);
70 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 66 imx27_add_fec(NULL);
71} 67}
72 68
73static void __init mx27lite_timer_init(void) 69static void __init mx27lite_timer_init(void)
@@ -80,8 +76,6 @@ static struct sys_timer mx27lite_timer = {
80}; 76};
81 77
82MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") 78MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
83 .phys_io = MX27_AIPI_BASE_ADDR,
84 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
85 .boot_params = MX27_PHYS_OFFSET + 0x100, 79 .boot_params = MX27_PHYS_OFFSET + 0x100,
86 .map_io = mx27_map_io, 80 .map_io = mx27_map_io,
87 .init_irq = mx27_init_irq, 81 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 77a760cfadc0..6187ce9ba7d5 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -32,7 +32,7 @@
32#include "devices-imx1.h" 32#include "devices-imx1.h"
33#include "devices.h" 33#include "devices.h"
34 34
35static int mx1ads_pins[] = { 35static const int mx1ads_pins[] __initconst = {
36 /* UART1 */ 36 /* UART1 */
37 PC9_PF_UART1_CTS, 37 PC9_PF_UART1_CTS,
38 PC10_PF_UART1_RTS, 38 PC10_PF_UART1_RTS,
@@ -131,7 +131,7 @@ static void __init mx1ads_init(void)
131 i2c_register_board_info(0, mx1ads_i2c_devices, 131 i2c_register_board_info(0, mx1ads_i2c_devices,
132 ARRAY_SIZE(mx1ads_i2c_devices)); 132 ARRAY_SIZE(mx1ads_i2c_devices));
133 133
134 imx1_add_i2c_imx(&mx1ads_i2c_data); 134 imx1_add_imx_i2c(&mx1ads_i2c_data);
135} 135}
136 136
137static void __init mx1ads_timer_init(void) 137static void __init mx1ads_timer_init(void)
@@ -145,8 +145,6 @@ struct sys_timer mx1ads_timer = {
145 145
146MACHINE_START(MX1ADS, "Freescale MX1ADS") 146MACHINE_START(MX1ADS, "Freescale MX1ADS")
147 /* Maintainer: Sascha Hauer, Pengutronix */ 147 /* Maintainer: Sascha Hauer, Pengutronix */
148 .phys_io = MX1_IO_BASE_ADDR,
149 .io_pg_offst = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
150 .boot_params = MX1_PHYS_OFFSET + 0x100, 148 .boot_params = MX1_PHYS_OFFSET + 0x100,
151 .map_io = mx1_map_io, 149 .map_io = mx1_map_io,
152 .init_irq = mx1_init_irq, 150 .init_irq = mx1_init_irq,
@@ -155,8 +153,6 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
155MACHINE_END 153MACHINE_END
156 154
157MACHINE_START(MXLADS, "Freescale MXLADS") 155MACHINE_START(MXLADS, "Freescale MXLADS")
158 .phys_io = MX1_IO_BASE_ADDR,
159 .io_pg_offst = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
160 .boot_params = MX1_PHYS_OFFSET + 0x100, 156 .boot_params = MX1_PHYS_OFFSET + 0x100,
161 .map_io = mx1_map_io, 157 .map_io = mx1_map_io,
162 .init_irq = mx1_init_irq, 158 .init_irq = mx1_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 96d7f8189f32..e1282e9f50ff 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -67,7 +67,7 @@
67#define MX21ADS_IO_LED4_ON 0x4000 67#define MX21ADS_IO_LED4_ON 0x4000
68#define MX21ADS_IO_LED3_ON 0x8000 68#define MX21ADS_IO_LED3_ON 0x8000
69 69
70static unsigned int mx21ads_pins[] = { 70static const int mx21ads_pins[] __initconst = {
71 71
72 /* CS8900A */ 72 /* CS8900A */
73 (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11), 73 (GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11),
@@ -314,8 +314,6 @@ static struct sys_timer mx21ads_timer = {
314 314
315MACHINE_START(MX21ADS, "Freescale i.MX21ADS") 315MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
316 /* maintainer: Freescale Semiconductor, Inc. */ 316 /* maintainer: Freescale Semiconductor, Inc. */
317 .phys_io = MX21_AIPI_BASE_ADDR,
318 .io_pg_offst = ((MX21_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
319 .boot_params = MX21_PHYS_OFFSET + 0x100, 317 .boot_params = MX21_PHYS_OFFSET + 0x100,
320 .map_io = mx21ads_map_io, 318 .map_io = mx21ads_map_io,
321 .init_irq = mx21_init_irq, 319 .init_irq = mx21_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index e66ffaa1c26c..b8bbd31aa850 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -33,7 +33,7 @@
33#include "devices-imx27.h" 33#include "devices-imx27.h"
34#include "devices.h" 34#include "devices.h"
35 35
36static unsigned int mx27pdk_pins[] = { 36static const int mx27pdk_pins[] __initconst = {
37 /* UART1 */ 37 /* UART1 */
38 PE12_PF_UART1_TXD, 38 PE12_PF_UART1_TXD,
39 PE13_PF_UART1_RXD, 39 PE13_PF_UART1_RXD,
@@ -64,10 +64,6 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
64 .flags = IMXUART_HAVE_RTSCTS, 64 .flags = IMXUART_HAVE_RTSCTS,
65}; 65};
66 66
67static struct platform_device *platform_devices[] __initdata = {
68 &mxc_fec_device,
69};
70
71/* 67/*
72 * Matrix keyboard 68 * Matrix keyboard
73 */ 69 */
@@ -94,7 +90,7 @@ static void __init mx27pdk_init(void)
94 mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins), 90 mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
95 "mx27pdk"); 91 "mx27pdk");
96 imx27_add_imx_uart0(&uart_pdata); 92 imx27_add_imx_uart0(&uart_pdata);
97 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 93 imx27_add_fec(NULL);
98 mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data); 94 mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data);
99} 95}
100 96
@@ -109,8 +105,6 @@ static struct sys_timer mx27pdk_timer = {
109 105
110MACHINE_START(MX27_3DS, "Freescale MX27PDK") 106MACHINE_START(MX27_3DS, "Freescale MX27PDK")
111 /* maintainer: Freescale Semiconductor, Inc. */ 107 /* maintainer: Freescale Semiconductor, Inc. */
112 .phys_io = MX27_AIPI_BASE_ADDR,
113 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
114 .boot_params = MX27_PHYS_OFFSET + 0x100, 108 .boot_params = MX27_PHYS_OFFSET + 0x100,
115 .map_io = mx27_map_io, 109 .map_io = mx27_map_io,
116 .init_irq = mx27_init_irq, 110 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 9c77da98a10e..a1e4bc573afc 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -66,7 +66,7 @@
66/* to determine the correct external crystal reference */ 66/* to determine the correct external crystal reference */
67#define CKIH_27MHZ_BIT_SET (1 << 3) 67#define CKIH_27MHZ_BIT_SET (1 << 3)
68 68
69static unsigned int mx27ads_pins[] = { 69static const int mx27ads_pins[] __initconst = {
70 /* UART0 */ 70 /* UART0 */
71 PE12_PF_UART1_TXD, 71 PE12_PF_UART1_TXD,
72 PE13_PF_UART1_RXD, 72 PE13_PF_UART1_RXD,
@@ -284,7 +284,6 @@ static struct imxmmc_platform_data sdhc2_pdata = {
284 284
285static struct platform_device *platform_devices[] __initdata = { 285static struct platform_device *platform_devices[] __initdata = {
286 &mx27ads_nor_mtd_device, 286 &mx27ads_nor_mtd_device,
287 &mxc_fec_device,
288 &mxc_w1_master_device, 287 &mxc_w1_master_device,
289}; 288};
290 289
@@ -308,11 +307,12 @@ static void __init mx27ads_board_init(void)
308 /* only the i2c master 1 is used on this CPU card */ 307 /* only the i2c master 1 is used on this CPU card */
309 i2c_register_board_info(1, mx27ads_i2c_devices, 308 i2c_register_board_info(1, mx27ads_i2c_devices,
310 ARRAY_SIZE(mx27ads_i2c_devices)); 309 ARRAY_SIZE(mx27ads_i2c_devices));
311 imx27_add_i2c_imx1(&mx27ads_i2c1_data); 310 imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
312 mxc_register_device(&mxc_fb_device, &mx27ads_fb_data); 311 mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
313 mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); 312 mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
314 mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata); 313 mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
315 314
315 imx27_add_fec(NULL);
316 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 316 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
317} 317}
318 318
@@ -347,8 +347,6 @@ static void __init mx27ads_map_io(void)
347 347
348MACHINE_START(MX27ADS, "Freescale i.MX27ADS") 348MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
349 /* maintainer: Freescale Semiconductor, Inc. */ 349 /* maintainer: Freescale Semiconductor, Inc. */
350 .phys_io = MX27_AIPI_BASE_ADDR,
351 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
352 .boot_params = MX27_PHYS_OFFSET + 0x100, 350 .boot_params = MX27_PHYS_OFFSET + 0x100,
353 .map_io = mx27ads_map_io, 351 .map_io = mx27ads_map_io,
354 .init_irq = mx27_init_irq, 352 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index a3a1e452d4c5..38d3a4ae17c7 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -37,7 +37,7 @@
37#include "devices-imx27.h" 37#include "devices-imx27.h"
38#include "devices.h" 38#include "devices.h"
39 39
40static unsigned int mxt_td60_pins[] __initdata = { 40static const int mxt_td60_pins[] __initconst = {
41 /* UART0 */ 41 /* UART0 */
42 PE12_PF_UART1_TXD, 42 PE12_PF_UART1_TXD,
43 PE13_PF_UART1_RXD, 43 PE13_PF_UART1_RXD,
@@ -231,10 +231,6 @@ static struct imxmmc_platform_data sdhc1_pdata = {
231 .exit = mxt_td60_sdhc1_exit, 231 .exit = mxt_td60_sdhc1_exit,
232}; 232};
233 233
234static struct platform_device *platform_devices[] __initdata = {
235 &mxc_fec_device,
236};
237
238static const struct imxuart_platform_data uart_pdata __initconst = { 234static const struct imxuart_platform_data uart_pdata __initconst = {
239 .flags = IMXUART_HAVE_RTSCTS, 235 .flags = IMXUART_HAVE_RTSCTS,
240}; 236};
@@ -255,12 +251,11 @@ static void __init mxt_td60_board_init(void)
255 i2c_register_board_info(1, mxt_td60_i2c2_devices, 251 i2c_register_board_info(1, mxt_td60_i2c2_devices,
256 ARRAY_SIZE(mxt_td60_i2c2_devices)); 252 ARRAY_SIZE(mxt_td60_i2c2_devices));
257 253
258 imx27_add_i2c_imx0(&mxt_td60_i2c0_data); 254 imx27_add_imx_i2c(0, &mxt_td60_i2c0_data);
259 imx27_add_i2c_imx1(&mxt_td60_i2c1_data); 255 imx27_add_imx_i2c(1, &mxt_td60_i2c1_data);
260 mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data); 256 mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data);
261 mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); 257 mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
262 258 imx27_add_fec(NULL);
263 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
264} 259}
265 260
266static void __init mxt_td60_timer_init(void) 261static void __init mxt_td60_timer_init(void)
@@ -274,8 +269,6 @@ static struct sys_timer mxt_td60_timer = {
274 269
275MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") 270MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
276 /* maintainer: Maxtrack Industrial */ 271 /* maintainer: Maxtrack Industrial */
277 .phys_io = MX27_AIPI_BASE_ADDR,
278 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
279 .boot_params = MX27_PHYS_OFFSET + 0x100, 272 .boot_params = MX27_PHYS_OFFSET + 0x100,
280 .map_io = mx27_map_io, 273 .map_io = mx27_map_io,
281 .init_irq = mx27_init_irq, 274 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 23c9e1f37b9c..8c720d44602a 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -38,7 +38,6 @@
38#include <mach/iomux-mx27.h> 38#include <mach/iomux-mx27.h>
39#include <asm/mach/time.h> 39#include <asm/mach/time.h>
40#include <mach/audmux.h> 40#include <mach/audmux.h>
41#include <mach/ssi.h>
42#include <mach/mxc_nand.h> 41#include <mach/mxc_nand.h>
43#include <mach/irqs.h> 42#include <mach/irqs.h>
44#include <mach/mmc.h> 43#include <mach/mmc.h>
@@ -55,7 +54,7 @@
55#define SPI1_SS1 (GPIO_PORTD + 27) 54#define SPI1_SS1 (GPIO_PORTD + 27)
56#define SD2_CD (GPIO_PORTC + 29) 55#define SD2_CD (GPIO_PORTC + 29)
57 56
58static int pca100_pins[] = { 57static const int pca100_pins[] __initconst = {
59 /* UART1 */ 58 /* UART1 */
60 PE12_PF_UART1_TXD, 59 PE12_PF_UART1_TXD,
61 PE13_PF_UART1_RXD, 60 PE13_PF_UART1_RXD,
@@ -174,7 +173,6 @@ pca100_nand_board_info __initconst = {
174 173
175static struct platform_device *platform_devices[] __initdata = { 174static struct platform_device *platform_devices[] __initdata = {
176 &mxc_w1_master_device, 175 &mxc_w1_master_device,
177 &mxc_fec_device,
178 &mxc_wdt, 176 &mxc_wdt,
179}; 177};
180 178
@@ -193,11 +191,9 @@ static struct i2c_board_info pca100_i2c_devices[] = {
193 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ 191 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
194 .platform_data = &board_eeprom, 192 .platform_data = &board_eeprom,
195 }, { 193 }, {
196 I2C_BOARD_INFO("rtc-pcf8563", 0x51), 194 I2C_BOARD_INFO("pcf8563", 0x51),
197 .type = "pcf8563"
198 }, { 195 }, {
199 I2C_BOARD_INFO("lm75", 0x4a), 196 I2C_BOARD_INFO("lm75", 0x4a),
200 .type = "lm75"
201 } 197 }
202}; 198};
203 199
@@ -252,7 +248,7 @@ static void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
252 msleep(2); 248 msleep(2);
253} 249}
254 250
255static struct imx_ssi_platform_data pca100_ssi_pdata = { 251static const struct imx_ssi_platform_data pca100_ssi_pdata __initconst = {
256 .ac97_reset = pca100_ac97_cold_reset, 252 .ac97_reset = pca100_ac97_cold_reset,
257 .ac97_warm_reset = pca100_ac97_warm_reset, 253 .ac97_warm_reset = pca100_ac97_warm_reset,
258 .flags = IMX_SSI_USE_AC97, 254 .flags = IMX_SSI_USE_AC97,
@@ -389,7 +385,7 @@ static void __init pca100_init(void)
389 if (ret) 385 if (ret)
390 printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret); 386 printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);
391 387
392 mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata); 388 imx27_add_imx_ssi(0, &pca100_ssi_pdata);
393 389
394 imx27_add_imx_uart0(&uart_pdata); 390 imx27_add_imx_uart0(&uart_pdata);
395 391
@@ -401,7 +397,7 @@ static void __init pca100_init(void)
401 i2c_register_board_info(1, pca100_i2c_devices, 397 i2c_register_board_info(1, pca100_i2c_devices,
402 ARRAY_SIZE(pca100_i2c_devices)); 398 ARRAY_SIZE(pca100_i2c_devices));
403 399
404 imx27_add_i2c_imx1(&pca100_i2c1_data); 400 imx27_add_imx_i2c(1, &pca100_i2c1_data);
405 401
406#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) 402#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
407 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN); 403 mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
@@ -436,6 +432,7 @@ static void __init pca100_init(void)
436 432
437 mxc_register_device(&mxc_fb_device, &pca100_fb_data); 433 mxc_register_device(&mxc_fb_device, &pca100_fb_data);
438 434
435 imx27_add_fec(NULL);
439 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 436 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
440} 437}
441 438
@@ -449,8 +446,6 @@ static struct sys_timer pca100_timer = {
449}; 446};
450 447
451MACHINE_START(PCA100, "phyCARD-i.MX27") 448MACHINE_START(PCA100, "phyCARD-i.MX27")
452 .phys_io = MX27_AIPI_BASE_ADDR,
453 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
454 .boot_params = MX27_PHYS_OFFSET + 0x100, 449 .boot_params = MX27_PHYS_OFFSET + 0x100,
455 .map_io = mx27_map_io, 450 .map_io = mx27_map_io,
456 .init_irq = mx27_init_irq, 451 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 9212e8f37001..49a97ce07426 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -43,7 +43,7 @@
43#include "devices-imx27.h" 43#include "devices-imx27.h"
44#include "devices.h" 44#include "devices.h"
45 45
46static int pcm038_pins[] = { 46static const int pcm038_pins[] __initconst = {
47 /* UART1 */ 47 /* UART1 */
48 PE12_PF_UART1_TXD, 48 PE12_PF_UART1_TXD,
49 PE13_PF_UART1_RXD, 49 PE13_PF_UART1_RXD,
@@ -173,7 +173,6 @@ pcm038_nand_board_info __initconst = {
173static struct platform_device *platform_devices[] __initdata = { 173static struct platform_device *platform_devices[] __initdata = {
174 &pcm038_nor_mtd_device, 174 &pcm038_nor_mtd_device,
175 &mxc_w1_master_device, 175 &mxc_w1_master_device,
176 &mxc_fec_device,
177 &pcm038_sram_mtd_device, 176 &pcm038_sram_mtd_device,
178 &mxc_wdt, 177 &mxc_wdt,
179}; 178};
@@ -257,7 +256,7 @@ static struct regulator_init_data cam_data = {
257 .consumer_supplies = cam_consumers, 256 .consumer_supplies = cam_consumers,
258}; 257};
259 258
260struct mc13783_regulator_init_data pcm038_regulators[] = { 259static struct mc13783_regulator_init_data pcm038_regulators[] = {
261 { 260 {
262 .id = MC13783_REGU_VCAM, 261 .id = MC13783_REGU_VCAM,
263 .init_data = &cam_data, 262 .init_data = &cam_data,
@@ -309,7 +308,7 @@ static void __init pcm038_init(void)
309 i2c_register_board_info(1, pcm038_i2c_devices, 308 i2c_register_board_info(1, pcm038_i2c_devices,
310 ARRAY_SIZE(pcm038_i2c_devices)); 309 ARRAY_SIZE(pcm038_i2c_devices));
311 310
312 imx27_add_i2c_imx1(&pcm038_i2c1_data); 311 imx27_add_imx_i2c(1, &pcm038_i2c1_data);
313 312
314 /* PE18 for user-LED D40 */ 313 /* PE18 for user-LED D40 */
315 mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT); 314 mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
@@ -325,6 +324,7 @@ static void __init pcm038_init(void)
325 324
326 mxc_register_device(&mxc_usbh2, &usbh2_pdata); 325 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
327 326
327 imx27_add_fec(NULL);
328 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 328 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
329 329
330#ifdef CONFIG_MACH_PCM970_BASEBOARD 330#ifdef CONFIG_MACH_PCM970_BASEBOARD
@@ -342,8 +342,6 @@ static struct sys_timer pcm038_timer = {
342}; 342};
343 343
344MACHINE_START(PCM038, "phyCORE-i.MX27") 344MACHINE_START(PCM038, "phyCORE-i.MX27")
345 .phys_io = MX27_AIPI_BASE_ADDR,
346 .io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
347 .boot_params = MX27_PHYS_OFFSET + 0x100, 345 .boot_params = MX27_PHYS_OFFSET + 0x100,
348 .map_io = mx27_map_io, 346 .map_io = mx27_map_io,
349 .init_irq = mx27_init_irq, 347 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index 88bf0d1e26e6..1fbdd3faa7ab 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -95,7 +95,7 @@ static struct platform_device dm9000x_device = {
95 } 95 }
96}; 96};
97 97
98static int mxc_uart1_pins[] = { 98static const int mxc_uart1_pins[] = {
99 PC9_PF_UART1_CTS, 99 PC9_PF_UART1_CTS,
100 PC10_PF_UART1_RTS, 100 PC10_PF_UART1_RTS,
101 PC11_PF_UART1_TXD, 101 PC11_PF_UART1_TXD,
@@ -147,8 +147,6 @@ static struct sys_timer scb9328_timer = {
147 147
148MACHINE_START(SCB9328, "Synertronixx scb9328") 148MACHINE_START(SCB9328, "Synertronixx scb9328")
149 /* Sascha Hauer */ 149 /* Sascha Hauer */
150 .phys_io = 0x00200000,
151 .io_pg_offst = ((0xe0200000) >> 18) & 0xfffc,
152 .boot_params = 0x08000100, 150 .boot_params = 0x08000100,
153 .map_io = mx1_map_io, 151 .map_io = mx1_map_io,
154 .init_irq = mx1_init_irq, 152 .init_irq = mx1_init_irq,
diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
index f490a406d57e..9110d9cca7a2 100644
--- a/arch/arm/mach-imx/pcm970-baseboard.c
+++ b/arch/arm/mach-imx/pcm970-baseboard.c
@@ -31,7 +31,7 @@
31 31
32#include "devices.h" 32#include "devices.h"
33 33
34static int pcm970_pins[] = { 34static const int pcm970_pins[] __initconst = {
35 /* SDHC */ 35 /* SDHC */
36 PB4_PF_SD2_D0, 36 PB4_PF_SD2_D0,
37 PB5_PF_SD2_D1, 37 PB5_PF_SD2_D1,
@@ -200,7 +200,7 @@ static struct resource pcm970_sja1000_resources[] = {
200 }, 200 },
201}; 201};
202 202
203struct sja1000_platform_data pcm970_sja1000_platform_data = { 203static struct sja1000_platform_data pcm970_sja1000_platform_data = {
204 .osc_freq = 16000000, 204 .osc_freq = 16000000,
205 .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL, 205 .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
206 .cdr = CDR_CBP, 206 .cdr = CDR_CBP,
diff --git a/arch/arm/mach-integrator/include/mach/debug-macro.S b/arch/arm/mach-integrator/include/mach/debug-macro.S
index 87a6888ae011..a1f598fd3a56 100644
--- a/arch/arm/mach-integrator/include/mach/debug-macro.S
+++ b/arch/arm/mach-integrator/include/mach/debug-macro.S
@@ -11,12 +11,10 @@
11 * 11 *
12*/ 12*/
13 13
14 .macro addruart, rx, tmp 14 .macro addruart, rp, rv
15 mrc p15, 0, \rx, c1, c0 15 mov \rp, #0x16000000 @ physical base address
16 tst \rx, #1 @ MMU enabled? 16 mov \rv, #0xf0000000 @ virtual base
17 moveq \rx, #0x16000000 @ physical base address 17 add \rv, \rv, #0x16000000 >> 4
18 movne \rx, #0xf0000000 @ virtual base
19 addne \rx, \rx, #0x16000000 >> 4
20 .endm 18 .endm
21 19
22#include <asm/hardware/debug-pl01x.S> 20#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-integrator/include/mach/vmalloc.h b/arch/arm/mach-integrator/include/mach/vmalloc.h
index e87ab0b37bdd..e056e7cf5645 100644
--- a/arch/arm/mach-integrator/include/mach/vmalloc.h
+++ b/arch/arm/mach-integrator/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20#define VMALLOC_END (PAGE_OFFSET + 0x10000000) 20#define VMALLOC_END 0xd0000000
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 6ab5a03ab9d8..548208f11179 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -500,8 +500,6 @@ static struct sys_timer ap_timer = {
500 500
501MACHINE_START(INTEGRATOR, "ARM-Integrator") 501MACHINE_START(INTEGRATOR, "ARM-Integrator")
502 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 502 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
503 .phys_io = 0x16000000,
504 .io_pg_offst = ((0xf1600000) >> 18) & 0xfffc,
505 .boot_params = 0x00000100, 503 .boot_params = 0x00000100,
506 .map_io = ap_map_io, 504 .map_io = ap_map_io,
507 .reserve = integrator_reserve, 505 .reserve = integrator_reserve,
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 05db40e3c4f7..6258c90d020c 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -599,8 +599,6 @@ static struct sys_timer cp_timer = {
599 599
600MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") 600MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
601 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 601 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
602 .phys_io = 0x16000000,
603 .io_pg_offst = ((0xf1600000) >> 18) & 0xfffc,
604 .boot_params = 0x00000100, 602 .boot_params = 0x00000100,
605 .map_io = intcp_map_io, 603 .map_io = intcp_map_io,
606 .reserve = integrator_reserve, 604 .reserve = integrator_reserve,
diff --git a/arch/arm/mach-iop13xx/include/mach/debug-macro.S b/arch/arm/mach-iop13xx/include/mach/debug-macro.S
index c9d6ba46963d..e664466d51bf 100644
--- a/arch/arm/mach-iop13xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-iop13xx/include/mach/debug-macro.S
@@ -11,15 +11,13 @@
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13 13
14 .macro addruart, rx, tmp 14 .macro addruart, rp, rv
15 mrc p15, 0, \rx, c1, c0 15 mov \rp, #0x00002300
16 tst \rx, #1 @ mmu enabled? 16 orr \rp, \rp, #0x00000040
17 moveq \rx, #0xff000000 @ physical 17 orr \rv, \rp, #0xfe000000 @ virtual
18 orreq \rx, \rx, #0x00d80000 18 orr \rv, \rv, #0x00e80000
19 movne \rx, #0xfe000000 @ virtual 19 orr \rp, \rp, #0xff000000 @ physical
20 orrne \rx, \rx, #0x00e80000 20 orr \rp, \rp, #0x00d80000
21 orr \rx, \rx, #0x00002300
22 orr \rx, \rx, #0x00000040
23 .endm 21 .endm
24 22
25#define UART_SHIFT 2 23#define UART_SHIFT 2
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
index f91f3154577d..9b5a63f5d07d 100644
--- a/arch/arm/mach-iop13xx/iq81340mc.c
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -91,8 +91,6 @@ static struct sys_timer iq81340mc_timer = {
91 91
92MACHINE_START(IQ81340MC, "Intel IQ81340MC") 92MACHINE_START(IQ81340MC, "Intel IQ81340MC")
93 /* Maintainer: Dan Williams <dan.j.williams@intel.com> */ 93 /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
94 .phys_io = IOP13XX_PMMR_PHYS_MEM_BASE,
95 .io_pg_offst = (IOP13XX_PMMR_VIRT_MEM_BASE >> 18) & 0xfffc,
96 .boot_params = 0x00000100, 94 .boot_params = 0x00000100,
97 .map_io = iop13xx_map_io, 95 .map_io = iop13xx_map_io,
98 .init_irq = iop13xx_init_irq, 96 .init_irq = iop13xx_init_irq,
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
index ddb7a3435de9..df3492a9c280 100644
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -93,8 +93,6 @@ static struct sys_timer iq81340sc_timer = {
93 93
94MACHINE_START(IQ81340SC, "Intel IQ81340SC") 94MACHINE_START(IQ81340SC, "Intel IQ81340SC")
95 /* Maintainer: Dan Williams <dan.j.williams@intel.com> */ 95 /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
96 .phys_io = IOP13XX_PMMR_PHYS_MEM_BASE,
97 .io_pg_offst = (IOP13XX_PMMR_VIRT_MEM_BASE >> 18) & 0xfffc,
98 .boot_params = 0x00000100, 96 .boot_params = 0x00000100,
99 .map_io = iop13xx_map_io, 97 .map_io = iop13xx_map_io,
100 .init_irq = iop13xx_init_irq, 98 .init_irq = iop13xx_init_irq,
diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c
index 2bef9b6e1cc9..779f924af302 100644
--- a/arch/arm/mach-iop32x/em7210.c
+++ b/arch/arm/mach-iop32x/em7210.c
@@ -203,8 +203,6 @@ static void __init em7210_init_machine(void)
203} 203}
204 204
205MACHINE_START(EM7210, "Lanner EM7210") 205MACHINE_START(EM7210, "Lanner EM7210")
206 .phys_io = IQ31244_UART,
207 .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
208 .boot_params = 0xa0000100, 206 .boot_params = 0xa0000100,
209 .map_io = em7210_map_io, 207 .map_io = em7210_map_io,
210 .init_irq = iop32x_init_irq, 208 .init_irq = iop32x_init_irq,
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
index 10384fc37cb2..c6b6f9c5650d 100644
--- a/arch/arm/mach-iop32x/glantank.c
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -207,8 +207,6 @@ static void __init glantank_init_machine(void)
207 207
208MACHINE_START(GLANTANK, "GLAN Tank") 208MACHINE_START(GLANTANK, "GLAN Tank")
209 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 209 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
210 .phys_io = GLANTANK_UART,
211 .io_pg_offst = ((GLANTANK_UART) >> 18) & 0xfffc,
212 .boot_params = 0xa0000100, 210 .boot_params = 0xa0000100,
213 .map_io = glantank_map_io, 211 .map_io = glantank_map_io,
214 .init_irq = iop32x_init_irq, 212 .init_irq = iop32x_init_irq,
diff --git a/arch/arm/mach-iop32x/include/mach/debug-macro.S b/arch/arm/mach-iop32x/include/mach/debug-macro.S
index 736afe1edd1f..ff9e76c09f35 100644
--- a/arch/arm/mach-iop32x/include/mach/debug-macro.S
+++ b/arch/arm/mach-iop32x/include/mach/debug-macro.S
@@ -11,9 +11,10 @@
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13 13
14 .macro addruart, rx, tmp 14 .macro addruart, rp, rv
15 mov \rx, #0xfe000000 @ physical as well as virtual 15 mov \rp, #0xfe000000 @ physical as well as virtual
16 orr \rx, \rx, #0x00800000 @ location of the UART 16 orr \rp, \rp, #0x00800000 @ location of the UART
17 mov \rv, \rp
17 .endm 18 .endm
18 19
19#define UART_SHIFT 0 20#define UART_SHIFT 0
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index d6ac85ff109d..fde962c057f0 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -313,8 +313,6 @@ __setup("force_ep80219", force_ep80219_setup);
313 313
314MACHINE_START(IQ31244, "Intel IQ31244") 314MACHINE_START(IQ31244, "Intel IQ31244")
315 /* Maintainer: Intel Corp. */ 315 /* Maintainer: Intel Corp. */
316 .phys_io = IQ31244_UART,
317 .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
318 .boot_params = 0xa0000100, 316 .boot_params = 0xa0000100,
319 .map_io = iq31244_map_io, 317 .map_io = iq31244_map_io,
320 .init_irq = iop32x_init_irq, 318 .init_irq = iop32x_init_irq,
@@ -329,8 +327,6 @@ MACHINE_END
329 */ 327 */
330MACHINE_START(EP80219, "Intel EP80219") 328MACHINE_START(EP80219, "Intel EP80219")
331 /* Maintainer: Intel Corp. */ 329 /* Maintainer: Intel Corp. */
332 .phys_io = IQ31244_UART,
333 .io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
334 .boot_params = 0xa0000100, 330 .boot_params = 0xa0000100,
335 .map_io = iq31244_map_io, 331 .map_io = iq31244_map_io,
336 .init_irq = iop32x_init_irq, 332 .init_irq = iop32x_init_irq,
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index c6a0e4ee9d91..3a95950e8737 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -186,8 +186,6 @@ static void __init iq80321_init_machine(void)
186 186
187MACHINE_START(IQ80321, "Intel IQ80321") 187MACHINE_START(IQ80321, "Intel IQ80321")
188 /* Maintainer: Intel Corp. */ 188 /* Maintainer: Intel Corp. */
189 .phys_io = IQ80321_UART,
190 .io_pg_offst = ((IQ80321_UART) >> 18) & 0xfffc,
191 .boot_params = 0xa0000100, 189 .boot_params = 0xa0000100,
192 .map_io = iq80321_map_io, 190 .map_io = iq80321_map_io,
193 .init_irq = iop32x_init_irq, 191 .init_irq = iop32x_init_irq,
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index f108a31afc2b..626aa375915d 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -327,8 +327,6 @@ static void __init n2100_init_machine(void)
327 327
328MACHINE_START(N2100, "Thecus N2100") 328MACHINE_START(N2100, "Thecus N2100")
329 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 329 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
330 .phys_io = N2100_UART,
331 .io_pg_offst = ((N2100_UART) >> 18) & 0xfffc,
332 .boot_params = 0xa0000100, 330 .boot_params = 0xa0000100,
333 .map_io = n2100_map_io, 331 .map_io = n2100_map_io,
334 .init_irq = iop32x_init_irq, 332 .init_irq = iop32x_init_irq,
diff --git a/arch/arm/mach-iop33x/include/mach/debug-macro.S b/arch/arm/mach-iop33x/include/mach/debug-macro.S
index addb2da78422..40c500dd1fac 100644
--- a/arch/arm/mach-iop33x/include/mach/debug-macro.S
+++ b/arch/arm/mach-iop33x/include/mach/debug-macro.S
@@ -11,13 +11,11 @@
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13 13
14 .macro addruart, rx, tmp 14 .macro addruart, rp, rv
15 mrc p15, 0, \rx, c1, c0 15 mov \rp, #0x00ff0000
16 tst \rx, #1 @ mmu enabled? 16 orr \rp, \rp, #0x0000f700
17 moveq \rx, #0xff000000 @ physical 17 orr \rv, #0xfe000000 @ virtual
18 movne \rx, #0xfe000000 @ virtual 18 orr \rp, #0xff000000 @ physical
19 orr \rx, \rx, #0x00ff0000
20 orr \rx, \rx, #0x0000f700
21 .endm 19 .endm
22 20
23#define UART_SHIFT 2 21#define UART_SHIFT 2
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index c6ff5523b380..c565f8d1e3a4 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -141,8 +141,6 @@ static void __init iq80331_init_machine(void)
141 141
142MACHINE_START(IQ80331, "Intel IQ80331") 142MACHINE_START(IQ80331, "Intel IQ80331")
143 /* Maintainer: Intel Corp. */ 143 /* Maintainer: Intel Corp. */
144 .phys_io = 0xfefff000,
145 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc,
146 .boot_params = 0x00000100, 144 .boot_params = 0x00000100,
147 .map_io = iop3xx_map_io, 145 .map_io = iop3xx_map_io,
148 .init_irq = iop33x_init_irq, 146 .init_irq = iop33x_init_irq,
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index fbf551409394..36a9efb254c2 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -141,8 +141,6 @@ static void __init iq80332_init_machine(void)
141 141
142MACHINE_START(IQ80332, "Intel IQ80332") 142MACHINE_START(IQ80332, "Intel IQ80332")
143 /* Maintainer: Intel Corp. */ 143 /* Maintainer: Intel Corp. */
144 .phys_io = 0xfefff000,
145 .io_pg_offst = ((0xfffff000) >> 18) & 0xfffc,
146 .boot_params = 0x00000100, 144 .boot_params = 0x00000100,
147 .map_io = iop3xx_map_io, 145 .map_io = iop3xx_map_io,
148 .init_irq = iop33x_init_irq, 146 .init_irq = iop33x_init_irq,
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
index 1a557e0d055b..88663ab1d2ad 100644
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ b/arch/arm/mach-ixp2000/enp2611.c
@@ -253,8 +253,6 @@ static void __init enp2611_init_machine(void)
253 253
254MACHINE_START(ENP2611, "Radisys ENP-2611 PCI network processor board") 254MACHINE_START(ENP2611, "Radisys ENP-2611 PCI network processor board")
255 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 255 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
256 .phys_io = IXP2000_UART_PHYS_BASE,
257 .io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
258 .boot_params = 0x00000100, 256 .boot_params = 0x00000100,
259 .map_io = enp2611_map_io, 257 .map_io = enp2611_map_io,
260 .init_irq = ixp2000_init_irq, 258 .init_irq = ixp2000_init_irq,
diff --git a/arch/arm/mach-ixp2000/include/mach/debug-macro.S b/arch/arm/mach-ixp2000/include/mach/debug-macro.S
index 6a827681680f..0ef533b20972 100644
--- a/arch/arm/mach-ixp2000/include/mach/debug-macro.S
+++ b/arch/arm/mach-ixp2000/include/mach/debug-macro.S
@@ -11,16 +11,14 @@
11 * 11 *
12*/ 12*/
13 13
14 .macro addruart, rx, tmp 14 .macro addruart, rp, rv
15 mrc p15, 0, \rx, c1, c0 15 mov \rp, #0x00030000
16 tst \rx, #1 @ MMU enabled?
17 moveq \rx, #0xc0000000 @ Physical base
18 movne \rx, #0xfe000000 @ virtual base
19 orrne \rx, \rx, #0x00f00000
20 orr \rx, \rx, #0x00030000
21#ifdef __ARMEB__ 16#ifdef __ARMEB__
22 orr \rx, \rx, #0x00000003 17 orr \rp, \rp, #0x00000003
23#endif 18#endif
19 orr \rv, \rp, #0xfe000000 @ virtual base
20 orr \rv, \rv, #0x00f00000
21 orr \rp, \rp, #0xc0000000 @ Physical base
24 .endm 22 .endm
25 23
26#define UART_SHIFT 2 24#define UART_SHIFT 2
diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c
index 55e5c69352ad..dfffc1e817fa 100644
--- a/arch/arm/mach-ixp2000/ixdp2400.c
+++ b/arch/arm/mach-ixp2000/ixdp2400.c
@@ -170,8 +170,6 @@ void __init ixdp2400_init_irq(void)
170 170
171MACHINE_START(IXDP2400, "Intel IXDP2400 Development Platform") 171MACHINE_START(IXDP2400, "Intel IXDP2400 Development Platform")
172 /* Maintainer: MontaVista Software, Inc. */ 172 /* Maintainer: MontaVista Software, Inc. */
173 .phys_io = IXP2000_UART_PHYS_BASE,
174 .io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
175 .boot_params = 0x00000100, 173 .boot_params = 0x00000100,
176 .map_io = ixdp2x00_map_io, 174 .map_io = ixdp2x00_map_io,
177 .init_irq = ixdp2400_init_irq, 175 .init_irq = ixdp2400_init_irq,
diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c
index 237b61a85e9a..cd4c9bcff2b5 100644
--- a/arch/arm/mach-ixp2000/ixdp2800.c
+++ b/arch/arm/mach-ixp2000/ixdp2800.c
@@ -285,8 +285,6 @@ void __init ixdp2800_init_irq(void)
285 285
286MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform") 286MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform")
287 /* Maintainer: MontaVista Software, Inc. */ 287 /* Maintainer: MontaVista Software, Inc. */
288 .phys_io = IXP2000_UART_PHYS_BASE,
289 .io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
290 .boot_params = 0x00000100, 288 .boot_params = 0x00000100,
291 .map_io = ixdp2x00_map_io, 289 .map_io = ixdp2x00_map_io,
292 .init_irq = ixdp2800_init_irq, 290 .init_irq = ixdp2800_init_irq,
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index 0369ec4242a6..6c121bdbe311 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -416,8 +416,6 @@ static void __init ixdp2x01_init_machine(void)
416#ifdef CONFIG_ARCH_IXDP2401 416#ifdef CONFIG_ARCH_IXDP2401
417MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform") 417MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform")
418 /* Maintainer: MontaVista Software, Inc. */ 418 /* Maintainer: MontaVista Software, Inc. */
419 .phys_io = IXP2000_UART_PHYS_BASE,
420 .io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
421 .boot_params = 0x00000100, 419 .boot_params = 0x00000100,
422 .map_io = ixdp2x01_map_io, 420 .map_io = ixdp2x01_map_io,
423 .init_irq = ixdp2x01_init_irq, 421 .init_irq = ixdp2x01_init_irq,
@@ -429,8 +427,6 @@ MACHINE_END
429#ifdef CONFIG_ARCH_IXDP2801 427#ifdef CONFIG_ARCH_IXDP2801
430MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform") 428MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform")
431 /* Maintainer: MontaVista Software, Inc. */ 429 /* Maintainer: MontaVista Software, Inc. */
432 .phys_io = IXP2000_UART_PHYS_BASE,
433 .io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
434 .boot_params = 0x00000100, 430 .boot_params = 0x00000100,
435 .map_io = ixdp2x01_map_io, 431 .map_io = ixdp2x01_map_io,
436 .init_irq = ixdp2x01_init_irq, 432 .init_irq = ixdp2x01_init_irq,
@@ -444,8 +440,6 @@ MACHINE_END
444 */ 440 */
445MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform") 441MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform")
446 /* Maintainer: MontaVista Software, Inc. */ 442 /* Maintainer: MontaVista Software, Inc. */
447 .phys_io = IXP2000_UART_PHYS_BASE,
448 .io_pg_offst = ((IXP2000_UART_VIRT_BASE) >> 18) & 0xfffc,
449 .boot_params = 0x00000100, 443 .boot_params = 0x00000100,
450 .map_io = ixdp2x01_map_io, 444 .map_io = ixdp2x01_map_io,
451 .init_irq = ixdp2x01_init_irq, 445 .init_irq = ixdp2x01_init_irq,
diff --git a/arch/arm/mach-ixp23xx/espresso.c b/arch/arm/mach-ixp23xx/espresso.c
index 1c06bfc5a7ef..e25e5fe183ba 100644
--- a/arch/arm/mach-ixp23xx/espresso.c
+++ b/arch/arm/mach-ixp23xx/espresso.c
@@ -85,8 +85,6 @@ static void __init espresso_init(void)
85 85
86MACHINE_START(ESPRESSO, "IP Fabrics Double Espresso") 86MACHINE_START(ESPRESSO, "IP Fabrics Double Espresso")
87 /* Maintainer: Lennert Buytenhek */ 87 /* Maintainer: Lennert Buytenhek */
88 .phys_io = IXP23XX_PERIPHERAL_PHYS,
89 .io_pg_offst = ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
90 .map_io = ixp23xx_map_io, 88 .map_io = ixp23xx_map_io,
91 .init_irq = ixp23xx_init_irq, 89 .init_irq = ixp23xx_init_irq,
92 .timer = &ixp23xx_timer, 90 .timer = &ixp23xx_timer,
diff --git a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
index a82e375465e2..f7c6eef7fa22 100644
--- a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
@@ -12,13 +12,12 @@
12 */ 12 */
13#include <mach/ixp23xx.h> 13#include <mach/ixp23xx.h>
14 14
15 .macro addruart, rx, tmp 15 .macro addruart, rp, rv
16 mrc p15, 0, \rx, c1, c0 16 ldr \rp, =IXP23XX_PERIPHERAL_PHYS @ physical
17 tst \rx, #1 @ mmu enabled? 17 ldr \rv, =IXP23XX_PERIPHERAL_VIRT @ virtual
18 ldreq \rx, =IXP23XX_PERIPHERAL_PHYS @ physical
19 ldrne \rx, =IXP23XX_PERIPHERAL_VIRT @ virtual
20#ifdef __ARMEB__ 18#ifdef __ARMEB__
21 orr \rx, \rx, #0x00000003 19 orr \rp, \rp, #0x00000003
20 orr \rv, \rv, #0x00000003
22#endif 21#endif
23 .endm 22 .endm
24 23
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
index f1b124a709ab..664e39c2a903 100644
--- a/arch/arm/mach-ixp23xx/ixdp2351.c
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -328,8 +328,6 @@ static void __init ixdp2351_init(void)
328 328
329MACHINE_START(IXDP2351, "Intel IXDP2351 Development Platform") 329MACHINE_START(IXDP2351, "Intel IXDP2351 Development Platform")
330 /* Maintainer: MontaVista Software, Inc. */ 330 /* Maintainer: MontaVista Software, Inc. */
331 .phys_io = IXP23XX_PERIPHERAL_PHYS,
332 .io_pg_offst = ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
333 .map_io = ixdp2351_map_io, 331 .map_io = ixdp2351_map_io,
334 .init_irq = ixdp2351_init_irq, 332 .init_irq = ixdp2351_init_irq,
335 .timer = &ixp23xx_timer, 333 .timer = &ixp23xx_timer,
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c
index 6d38d769761c..76c61ba73218 100644
--- a/arch/arm/mach-ixp23xx/roadrunner.c
+++ b/arch/arm/mach-ixp23xx/roadrunner.c
@@ -171,8 +171,6 @@ static void __init roadrunner_init(void)
171 171
172MACHINE_START(ROADRUNNER, "ADI Engineering RoadRunner Development Platform") 172MACHINE_START(ROADRUNNER, "ADI Engineering RoadRunner Development Platform")
173 /* Maintainer: Deepak Saxena */ 173 /* Maintainer: Deepak Saxena */
174 .phys_io = IXP23XX_PERIPHERAL_PHYS,
175 .io_pg_offst = ((IXP23XX_PERIPHERAL_VIRT >> 18)) & 0xfffc,
176 .map_io = ixp23xx_map_io, 174 .map_io = ixp23xx_map_io,
177 .init_irq = ixp23xx_init_irq, 175 .init_irq = ixp23xx_init_irq,
178 .timer = &ixp23xx_timer, 176 .timer = &ixp23xx_timer,
diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c
index d8bc86d76f1d..73745ff102d5 100644
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -164,8 +164,6 @@ static void __init avila_init(void)
164 164
165MACHINE_START(AVILA, "Gateworks Avila Network Platform") 165MACHINE_START(AVILA, "Gateworks Avila Network Platform")
166 /* Maintainer: Deepak Saxena <dsaxena@plexity.net> */ 166 /* Maintainer: Deepak Saxena <dsaxena@plexity.net> */
167 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
168 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
169 .map_io = ixp4xx_map_io, 167 .map_io = ixp4xx_map_io,
170 .init_irq = ixp4xx_init_irq, 168 .init_irq = ixp4xx_init_irq,
171 .timer = &ixp4xx_timer, 169 .timer = &ixp4xx_timer,
@@ -181,8 +179,6 @@ MACHINE_END
181#ifdef CONFIG_MACH_LOFT 179#ifdef CONFIG_MACH_LOFT
182MACHINE_START(LOFT, "Giant Shoulder Inc Loft board") 180MACHINE_START(LOFT, "Giant Shoulder Inc Loft board")
183 /* Maintainer: Tom Billman <kernel@giantshoulderinc.com> */ 181 /* Maintainer: Tom Billman <kernel@giantshoulderinc.com> */
184 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
185 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
186 .map_io = ixp4xx_map_io, 182 .map_io = ixp4xx_map_io,
187 .init_irq = ixp4xx_init_irq, 183 .init_irq = ixp4xx_init_irq,
188 .timer = &ixp4xx_timer, 184 .timer = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c
index 31a47f6a8939..355e3de38733 100644
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -109,8 +109,6 @@ static void __init coyote_init(void)
109#ifdef CONFIG_ARCH_ADI_COYOTE 109#ifdef CONFIG_ARCH_ADI_COYOTE
110MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote") 110MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote")
111 /* Maintainer: MontaVista Software, Inc. */ 111 /* Maintainer: MontaVista Software, Inc. */
112 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
113 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
114 .map_io = ixp4xx_map_io, 112 .map_io = ixp4xx_map_io,
115 .init_irq = ixp4xx_init_irq, 113 .init_irq = ixp4xx_init_irq,
116 .timer = &ixp4xx_timer, 114 .timer = &ixp4xx_timer,
@@ -126,8 +124,6 @@ MACHINE_END
126#ifdef CONFIG_MACH_IXDPG425 124#ifdef CONFIG_MACH_IXDPG425
127MACHINE_START(IXDPG425, "Intel IXDPG425") 125MACHINE_START(IXDPG425, "Intel IXDPG425")
128 /* Maintainer: MontaVista Software, Inc. */ 126 /* Maintainer: MontaVista Software, Inc. */
129 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
130 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
131 .map_io = ixp4xx_map_io, 127 .map_io = ixp4xx_map_io,
132 .init_irq = ixp4xx_init_irq, 128 .init_irq = ixp4xx_init_irq,
133 .timer = &ixp4xx_timer, 129 .timer = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 7c1fa54a6145..d398229cfaa5 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -279,8 +279,6 @@ static void __init dsmg600_init(void)
279 279
280MACHINE_START(DSMG600, "D-Link DSM-G600 RevA") 280MACHINE_START(DSMG600, "D-Link DSM-G600 RevA")
281 /* Maintainer: www.nslu2-linux.org */ 281 /* Maintainer: www.nslu2-linux.org */
282 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
283 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
284 .boot_params = 0x00000100, 282 .boot_params = 0x00000100,
285 .map_io = ixp4xx_map_io, 283 .map_io = ixp4xx_map_io,
286 .init_irq = ixp4xx_init_irq, 284 .init_irq = ixp4xx_init_irq,
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
index e7f4befba422..727ee39ce11c 100644
--- a/arch/arm/mach-ixp4xx/fsg-setup.c
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -270,8 +270,6 @@ static void __init fsg_init(void)
270 270
271MACHINE_START(FSG, "Freecom FSG-3") 271MACHINE_START(FSG, "Freecom FSG-3")
272 /* Maintainer: www.nslu2-linux.org */ 272 /* Maintainer: www.nslu2-linux.org */
273 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
274 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
275 .map_io = ixp4xx_map_io, 273 .map_io = ixp4xx_map_io,
276 .init_irq = ixp4xx_init_irq, 274 .init_irq = ixp4xx_init_irq,
277 .timer = &ixp4xx_timer, 275 .timer = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/gateway7001-setup.c b/arch/arm/mach-ixp4xx/gateway7001-setup.c
index 2583b2a13174..9dc0b4eaa65a 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-setup.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c
@@ -96,8 +96,6 @@ static void __init gateway7001_init(void)
96#ifdef CONFIG_MACH_GATEWAY7001 96#ifdef CONFIG_MACH_GATEWAY7001
97MACHINE_START(GATEWAY7001, "Gateway 7001 AP") 97MACHINE_START(GATEWAY7001, "Gateway 7001 AP")
98 /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */ 98 /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
99 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
100 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
101 .map_io = ixp4xx_map_io, 99 .map_io = ixp4xx_map_io,
102 .init_irq = ixp4xx_init_irq, 100 .init_irq = ixp4xx_init_irq,
103 .timer = &ixp4xx_timer, 101 .timer = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
index 1c28048209c1..d0e4861ac03d 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -496,8 +496,6 @@ subsys_initcall(gmlr_pci_init);
496 496
497MACHINE_START(GORAMO_MLR, "MultiLink") 497MACHINE_START(GORAMO_MLR, "MultiLink")
498 /* Maintainer: Krzysztof Halasa */ 498 /* Maintainer: Krzysztof Halasa */
499 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
500 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
501 .map_io = ixp4xx_map_io, 499 .map_io = ixp4xx_map_io,
502 .init_irq = ixp4xx_init_irq, 500 .init_irq = ixp4xx_init_irq,
503 .timer = &ixp4xx_timer, 501 .timer = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index c67586b79400..77abead36227 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -164,8 +164,6 @@ static void __init gtwx5715_init(void)
164 164
165MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)") 165MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)")
166 /* Maintainer: George Joseph */ 166 /* Maintainer: George Joseph */
167 .phys_io = IXP4XX_UART2_BASE_PHYS,
168 .io_pg_offst = ((IXP4XX_UART2_BASE_VIRT) >> 18) & 0xfffc,
169 .map_io = ixp4xx_map_io, 167 .map_io = ixp4xx_map_io,
170 .init_irq = ixp4xx_init_irq, 168 .init_irq = ixp4xx_init_irq,
171 .timer = &ixp4xx_timer, 169 .timer = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
index 3fc66d6d00a0..b974a49c0aff 100644
--- a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
@@ -10,16 +10,16 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13 .macro addruart, rx, tmp 13 .macro addruart, rp, rv
14 mrc p15, 0, \rx, c1, c0
15 tst \rx, #1 @ MMU enabled?
16 moveq \rx, #0xc8000000
17 movne \rx, #0xff000000
18 orrne \rx, \rx, #0x00b00000
19#ifdef __ARMEB__ 14#ifdef __ARMEB__
20 add \rx,\rx,#3 @ Uart regs are at off set of 3 if 15 mov \rp, #3 @ Uart regs are at off set of 3 if
21 @ byte writes used - Big Endian. 16 @ byte writes used - Big Endian.
17#else
18 mov \rp, #0
22#endif 19#endif
20 orr \rv, \rp, #0xff000000 @ virtual
21 orr \rv, \rv, #0x00b00000
22 orr \rp, \rp, #0xc8000000 @ physical
23 .endm 23 .endm
24 24
25#define UART_SHIFT 2 25#define UART_SHIFT 2
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index ea9ee4ed0a3e..140783386785 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -257,8 +257,6 @@ static void __init ixdp425_init(void)
257#ifdef CONFIG_ARCH_IXDP425 257#ifdef CONFIG_ARCH_IXDP425
258MACHINE_START(IXDP425, "Intel IXDP425 Development Platform") 258MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
259 /* Maintainer: MontaVista Software, Inc. */ 259 /* Maintainer: MontaVista Software, Inc. */
260 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
261 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
262 .map_io = ixp4xx_map_io, 260 .map_io = ixp4xx_map_io,
263 .init_irq = ixp4xx_init_irq, 261 .init_irq = ixp4xx_init_irq,
264 .timer = &ixp4xx_timer, 262 .timer = &ixp4xx_timer,
@@ -270,8 +268,6 @@ MACHINE_END
270#ifdef CONFIG_MACH_IXDP465 268#ifdef CONFIG_MACH_IXDP465
271MACHINE_START(IXDP465, "Intel IXDP465 Development Platform") 269MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
272 /* Maintainer: MontaVista Software, Inc. */ 270 /* Maintainer: MontaVista Software, Inc. */
273 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
274 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
275 .map_io = ixp4xx_map_io, 271 .map_io = ixp4xx_map_io,
276 .init_irq = ixp4xx_init_irq, 272 .init_irq = ixp4xx_init_irq,
277 .timer = &ixp4xx_timer, 273 .timer = &ixp4xx_timer,
@@ -283,8 +279,6 @@ MACHINE_END
283#ifdef CONFIG_ARCH_PRPMC1100 279#ifdef CONFIG_ARCH_PRPMC1100
284MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform") 280MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
285 /* Maintainer: MontaVista Software, Inc. */ 281 /* Maintainer: MontaVista Software, Inc. */
286 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
287 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
288 .map_io = ixp4xx_map_io, 282 .map_io = ixp4xx_map_io,
289 .init_irq = ixp4xx_init_irq, 283 .init_irq = ixp4xx_init_irq,
290 .timer = &ixp4xx_timer, 284 .timer = &ixp4xx_timer,
@@ -296,8 +290,6 @@ MACHINE_END
296#ifdef CONFIG_MACH_KIXRP435 290#ifdef CONFIG_MACH_KIXRP435
297MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform") 291MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
298 /* Maintainer: MontaVista Software, Inc. */ 292 /* Maintainer: MontaVista Software, Inc. */
299 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
300 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
301 .map_io = ixp4xx_map_io, 293 .map_io = ixp4xx_map_io,
302 .init_irq = ixp4xx_init_irq, 294 .init_irq = ixp4xx_init_irq,
303 .timer = &ixp4xx_timer, 295 .timer = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
index e3ee880aa1e6..f18fee748878 100644
--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
@@ -314,8 +314,6 @@ static void __init nas100d_init(void)
314 314
315MACHINE_START(NAS100D, "Iomega NAS 100d") 315MACHINE_START(NAS100D, "Iomega NAS 100d")
316 /* Maintainer: www.nslu2-linux.org */ 316 /* Maintainer: www.nslu2-linux.org */
317 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
318 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
319 .boot_params = 0x00000100, 317 .boot_params = 0x00000100,
320 .map_io = ixp4xx_map_io, 318 .map_io = ixp4xx_map_io,
321 .init_irq = ixp4xx_init_irq, 319 .init_irq = ixp4xx_init_irq,
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
index c14e0034be4b..f79b62eb7614 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -300,8 +300,6 @@ static void __init nslu2_init(void)
300 300
301MACHINE_START(NSLU2, "Linksys NSLU2") 301MACHINE_START(NSLU2, "Linksys NSLU2")
302 /* Maintainer: www.nslu2-linux.org */ 302 /* Maintainer: www.nslu2-linux.org */
303 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
304 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
305 .boot_params = 0x00000100, 303 .boot_params = 0x00000100,
306 .map_io = ixp4xx_map_io, 304 .map_io = ixp4xx_map_io,
307 .init_irq = ixp4xx_init_irq, 305 .init_irq = ixp4xx_init_irq,
diff --git a/arch/arm/mach-ixp4xx/vulcan-setup.c b/arch/arm/mach-ixp4xx/vulcan-setup.c
index 465cc5cce687..4e72cfdd3c46 100644
--- a/arch/arm/mach-ixp4xx/vulcan-setup.c
+++ b/arch/arm/mach-ixp4xx/vulcan-setup.c
@@ -236,8 +236,6 @@ static void __init vulcan_init(void)
236 236
237MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan") 237MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan")
238 /* Maintainer: Marc Zyngier <maz@misterjones.org> */ 238 /* Maintainer: Marc Zyngier <maz@misterjones.org> */
239 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
240 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
241 .map_io = ixp4xx_map_io, 239 .map_io = ixp4xx_map_io,
242 .init_irq = ixp4xx_init_irq, 240 .init_irq = ixp4xx_init_irq,
243 .timer = &ixp4xx_timer, 241 .timer = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/wg302v2-setup.c b/arch/arm/mach-ixp4xx/wg302v2-setup.c
index 4dd74863daa9..5d148c7bc4fb 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-setup.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c
@@ -97,8 +97,6 @@ static void __init wg302v2_init(void)
97#ifdef CONFIG_MACH_WG302V2 97#ifdef CONFIG_MACH_WG302V2
98MACHINE_START(WG302V2, "Netgear WG302 v2 / WAG302 v2") 98MACHINE_START(WG302V2, "Netgear WG302 v2 / WAG302 v2")
99 /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */ 99 /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
100 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
101 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
102 .map_io = ixp4xx_map_io, 100 .map_io = ixp4xx_map_io,
103 .init_irq = ixp4xx_init_irq, 101 .init_irq = ixp4xx_init_irq,
104 .timer = &ixp4xx_timer, 102 .timer = &ixp4xx_timer,
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index cc25501b57fa..34106335c728 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -58,6 +58,12 @@ config MACH_TS41X
58 QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS 58 QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS
59 devices. 59 devices.
60 60
61config MACH_DOCKSTAR
62 bool "Seagate FreeAgent DockStar"
63 help
64 Say 'Y' here if you want your kernel to support the
65 Seagate FreeAgent DockStar.
66
61config MACH_OPENRD 67config MACH_OPENRD
62 bool 68 bool
63 69
@@ -100,6 +106,12 @@ config MACH_NETSPACE_MAX_V2
100 Say 'Y' here if you want your kernel to support the 106 Say 'Y' here if you want your kernel to support the
101 LaCie Network Space Max v2 NAS. 107 LaCie Network Space Max v2 NAS.
102 108
109config MACH_D2NET_V2
110 bool "LaCie d2 Network v2 NAS Board"
111 help
112 Say 'Y' here if you want your kernel to support the
113 LaCie d2 Network v2 NAS.
114
103config MACH_NET2BIG_V2 115config MACH_NET2BIG_V2
104 bool "LaCie 2Big Network v2 NAS Board" 116 bool "LaCie 2Big Network v2 NAS Board"
105 help 117 help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 295d7baa6ae1..5dcaa81a2ec3 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -7,14 +7,16 @@ obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o
7obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o 7obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o
8obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG) += sheevaplug-setup.o 8obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG) += sheevaplug-setup.o
9obj-$(CONFIG_MACH_GURUPLUG) += guruplug-setup.o 9obj-$(CONFIG_MACH_GURUPLUG) += guruplug-setup.o
10obj-$(CONFIG_MACH_DOCKSTAR) += dockstar-setup.o
10obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o 11obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o
11obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o 12obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o
12obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o 13obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o
13obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o 14obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o lacie_v2-common.o
14obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o 15obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o lacie_v2-common.o
15obj-$(CONFIG_MACH_NETSPACE_MAX_V2) += netspace_v2-setup.o 16obj-$(CONFIG_MACH_NETSPACE_MAX_V2) += netspace_v2-setup.o lacie_v2-common.o
16obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o 17obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o
17obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o 18obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o
19obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o
18obj-$(CONFIG_MACH_T5325) += t5325-setup.o 20obj-$(CONFIG_MACH_T5325) += t5325-setup.o
19 21
20obj-$(CONFIG_CPU_IDLE) += cpuidle.o 22obj-$(CONFIG_CPU_IDLE) += cpuidle.o
diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c
new file mode 100644
index 000000000000..4aa86e4a152c
--- /dev/null
+++ b/arch/arm/mach-kirkwood/d2net_v2-setup.c
@@ -0,0 +1,229 @@
1/*
2 * arch/arm/mach-kirkwood/d2net_v2-setup.c
3 *
4 * LaCie d2 Network Space v2 Board Setup
5 *
6 * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/platform_device.h>
26#include <linux/ata_platform.h>
27#include <linux/mv643xx_eth.h>
28#include <linux/input.h>
29#include <linux/gpio.h>
30#include <linux/gpio_keys.h>
31#include <linux/leds.h>
32#include <asm/mach-types.h>
33#include <asm/mach/arch.h>
34#include <mach/kirkwood.h>
35#include <mach/leds-ns2.h>
36#include "common.h"
37#include "mpp.h"
38#include "lacie_v2-common.h"
39
40/*****************************************************************************
41 * Ethernet
42 ****************************************************************************/
43
44static struct mv643xx_eth_platform_data d2net_v2_ge00_data = {
45 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
46};
47
48/*****************************************************************************
49 * SATA
50 ****************************************************************************/
51
52static struct mv_sata_platform_data d2net_v2_sata_data = {
53 .n_ports = 2,
54};
55
56/*****************************************************************************
57 * GPIO keys
58 ****************************************************************************/
59
60#define D2NET_V2_GPIO_PUSH_BUTTON 34
61#define D2NET_V2_GPIO_POWER_SWITCH_ON 13
62#define D2NET_V2_GPIO_POWER_SWITCH_OFF 15
63
64#define D2NET_V2_SWITCH_POWER_ON 0x1
65#define D2NET_V2_SWITCH_POWER_OFF 0x2
66
67static struct gpio_keys_button d2net_v2_buttons[] = {
68 [0] = {
69 .type = EV_SW,
70 .code = D2NET_V2_SWITCH_POWER_ON,
71 .gpio = D2NET_V2_GPIO_POWER_SWITCH_ON,
72 .desc = "Back power switch (on|auto)",
73 .active_low = 0,
74 },
75 [1] = {
76 .type = EV_SW,
77 .code = D2NET_V2_SWITCH_POWER_OFF,
78 .gpio = D2NET_V2_GPIO_POWER_SWITCH_OFF,
79 .desc = "Back power switch (auto|off)",
80 .active_low = 0,
81 },
82 [2] = {
83 .code = KEY_POWER,
84 .gpio = D2NET_V2_GPIO_PUSH_BUTTON,
85 .desc = "Front Push Button",
86 .active_low = 1,
87 },
88};
89
90static struct gpio_keys_platform_data d2net_v2_button_data = {
91 .buttons = d2net_v2_buttons,
92 .nbuttons = ARRAY_SIZE(d2net_v2_buttons),
93};
94
95static struct platform_device d2net_v2_gpio_buttons = {
96 .name = "gpio-keys",
97 .id = -1,
98 .dev = {
99 .platform_data = &d2net_v2_button_data,
100 },
101};
102
103/*****************************************************************************
104 * GPIO LEDs
105 ****************************************************************************/
106
107#define D2NET_V2_GPIO_RED_LED 12
108
109static struct gpio_led d2net_v2_gpio_led_pins[] = {
110 {
111 .name = "d2net_v2:red:fail",
112 .gpio = D2NET_V2_GPIO_RED_LED,
113 },
114};
115
116static struct gpio_led_platform_data d2net_v2_gpio_leds_data = {
117 .num_leds = ARRAY_SIZE(d2net_v2_gpio_led_pins),
118 .leds = d2net_v2_gpio_led_pins,
119};
120
121static struct platform_device d2net_v2_gpio_leds = {
122 .name = "leds-gpio",
123 .id = -1,
124 .dev = {
125 .platform_data = &d2net_v2_gpio_leds_data,
126 },
127};
128
129/*****************************************************************************
130 * Dual-GPIO CPLD LEDs
131 ****************************************************************************/
132
133#define D2NET_V2_GPIO_BLUE_LED_SLOW 29
134#define D2NET_V2_GPIO_BLUE_LED_CMD 30
135
136static struct ns2_led d2net_v2_led_pins[] = {
137 {
138 .name = "d2net_v2:blue:sata",
139 .cmd = D2NET_V2_GPIO_BLUE_LED_CMD,
140 .slow = D2NET_V2_GPIO_BLUE_LED_SLOW,
141 },
142};
143
144static struct ns2_led_platform_data d2net_v2_leds_data = {
145 .num_leds = ARRAY_SIZE(d2net_v2_led_pins),
146 .leds = d2net_v2_led_pins,
147};
148
149static struct platform_device d2net_v2_leds = {
150 .name = "leds-ns2",
151 .id = -1,
152 .dev = {
153 .platform_data = &d2net_v2_leds_data,
154 },
155};
156
157/*****************************************************************************
158 * General Setup
159 ****************************************************************************/
160
161static unsigned int d2net_v2_mpp_config[] __initdata = {
162 MPP0_SPI_SCn,
163 MPP1_SPI_MOSI,
164 MPP2_SPI_SCK,
165 MPP3_SPI_MISO,
166 MPP6_SYSRST_OUTn,
167 MPP7_GPO, /* Request power-off */
168 MPP8_TW0_SDA,
169 MPP9_TW0_SCK,
170 MPP10_UART0_TXD,
171 MPP11_UART0_RXD,
172 MPP12_GPO, /* Red led */
173 MPP13_GPIO, /* Rear power switch (on|auto) */
174 MPP14_GPIO, /* USB fuse */
175 MPP15_GPIO, /* Rear power switch (auto|off) */
176 MPP16_GPIO, /* SATA 0 power */
177 MPP21_SATA0_ACTn,
178 MPP24_GPIO, /* USB mode select */
179 MPP26_GPIO, /* USB device vbus */
180 MPP28_GPIO, /* USB enable host vbus */
181 MPP29_GPIO, /* Blue led (slow register) */
182 MPP30_GPIO, /* Blue led (command register) */
183 MPP34_GPIO, /* Power button (1 = Released, 0 = Pushed) */
184 MPP35_GPIO, /* Inhibit power-off */
185 0
186};
187
188#define D2NET_V2_GPIO_POWER_OFF 7
189
190static void d2net_v2_power_off(void)
191{
192 gpio_set_value(D2NET_V2_GPIO_POWER_OFF, 1);
193}
194
195static void __init d2net_v2_init(void)
196{
197 /*
198 * Basic setup. Needs to be called early.
199 */
200 kirkwood_init();
201 kirkwood_mpp_conf(d2net_v2_mpp_config);
202
203 lacie_v2_hdd_power_init(1);
204
205 kirkwood_ehci_init();
206 kirkwood_ge00_init(&d2net_v2_ge00_data);
207 kirkwood_sata_init(&d2net_v2_sata_data);
208 kirkwood_uart0_init();
209 lacie_v2_register_flash();
210 lacie_v2_register_i2c_devices();
211
212 platform_device_register(&d2net_v2_leds);
213 platform_device_register(&d2net_v2_gpio_leds);
214 platform_device_register(&d2net_v2_gpio_buttons);
215
216 if (gpio_request(D2NET_V2_GPIO_POWER_OFF, "power-off") == 0 &&
217 gpio_direction_output(D2NET_V2_GPIO_POWER_OFF, 0) == 0)
218 pm_power_off = d2net_v2_power_off;
219 else
220 pr_err("d2net_v2: failed to configure power-off GPIO\n");
221}
222
223MACHINE_START(D2NET_V2, "LaCie d2 Network v2")
224 .boot_params = 0x00000100,
225 .init_machine = d2net_v2_init,
226 .map_io = kirkwood_map_io,
227 .init_irq = kirkwood_init_irq,
228 .timer = &lacie_v2_timer,
229MACHINE_END
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 16f6691e7c68..9ea71182d31a 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -97,8 +97,6 @@ subsys_initcall(db88f6281_pci_init);
97 97
98MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board") 98MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
99 /* Maintainer: Saeed Bishara <saeed@marvell.com> */ 99 /* Maintainer: Saeed Bishara <saeed@marvell.com> */
100 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
101 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
102 .boot_params = 0x00000100, 100 .boot_params = 0x00000100,
103 .init_machine = db88f6281_init, 101 .init_machine = db88f6281_init,
104 .map_io = kirkwood_map_io, 102 .map_io = kirkwood_map_io,
diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c
new file mode 100644
index 000000000000..433ea368c060
--- /dev/null
+++ b/arch/arm/mach-kirkwood/dockstar-setup.c
@@ -0,0 +1,110 @@
1/*
2 * arch/arm/mach-kirkwood/dockstar-setup.c
3 *
4 * Seagate FreeAgent DockStar Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/ata_platform.h>
15#include <linux/mtd/partitions.h>
16#include <linux/mv643xx_eth.h>
17#include <linux/gpio.h>
18#include <linux/leds.h>
19#include <asm/mach-types.h>
20#include <asm/mach/arch.h>
21#include <mach/kirkwood.h>
22#include <plat/mvsdio.h>
23#include "common.h"
24#include "mpp.h"
25
26static struct mtd_partition dockstar_nand_parts[] = {
27 {
28 .name = "u-boot",
29 .offset = 0,
30 .size = SZ_1M
31 }, {
32 .name = "uImage",
33 .offset = MTDPART_OFS_NXTBLK,
34 .size = SZ_4M
35 }, {
36 .name = "root",
37 .offset = MTDPART_OFS_NXTBLK,
38 .size = MTDPART_SIZ_FULL
39 },
40};
41
42static struct mv643xx_eth_platform_data dockstar_ge00_data = {
43 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
44};
45
46static struct gpio_led dockstar_led_pins[] = {
47 {
48 .name = "dockstar:green:health",
49 .default_trigger = "default-on",
50 .gpio = 46,
51 .active_low = 1,
52 },
53 {
54 .name = "dockstar:orange:misc",
55 .default_trigger = "none",
56 .gpio = 47,
57 .active_low = 1,
58 },
59};
60
61static struct gpio_led_platform_data dockstar_led_data = {
62 .leds = dockstar_led_pins,
63 .num_leds = ARRAY_SIZE(dockstar_led_pins),
64};
65
66static struct platform_device dockstar_leds = {
67 .name = "leds-gpio",
68 .id = -1,
69 .dev = {
70 .platform_data = &dockstar_led_data,
71 }
72};
73
74static unsigned int dockstar_mpp_config[] __initdata = {
75 MPP29_GPIO, /* USB Power Enable */
76 MPP46_GPIO, /* LED green */
77 MPP47_GPIO, /* LED orange */
78 0
79};
80
81static void __init dockstar_init(void)
82{
83 /*
84 * Basic setup. Needs to be called early.
85 */
86 kirkwood_init();
87
88 /* setup gpio pin select */
89 kirkwood_mpp_conf(dockstar_mpp_config);
90
91 kirkwood_uart0_init();
92 kirkwood_nand_init(ARRAY_AND_SIZE(dockstar_nand_parts), 25);
93
94 if (gpio_request(29, "USB Power Enable") != 0 ||
95 gpio_direction_output(29, 1) != 0)
96 printk(KERN_ERR "can't set up GPIO 29 (USB Power Enable)\n");
97 kirkwood_ehci_init();
98
99 kirkwood_ge00_init(&dockstar_ge00_data);
100
101 platform_device_register(&dockstar_leds);
102}
103
104MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar")
105 .boot_params = 0x00000100,
106 .init_machine = dockstar_init,
107 .map_io = kirkwood_map_io,
108 .init_irq = kirkwood_init_irq,
109 .timer = &kirkwood_timer,
110MACHINE_END
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
index 54d07c89d4ff..8f47dc0a2fef 100644
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -121,8 +121,6 @@ static void __init guruplug_init(void)
121 121
122MACHINE_START(GURUPLUG, "Marvell GuruPlug Reference Board") 122MACHINE_START(GURUPLUG, "Marvell GuruPlug Reference Board")
123 /* Maintainer: Siddarth Gore <gores@marvell.com> */ 123 /* Maintainer: Siddarth Gore <gores@marvell.com> */
124 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
125 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
126 .boot_params = 0x00000100, 124 .boot_params = 0x00000100,
127 .init_machine = guruplug_init, 125 .init_machine = guruplug_init,
128 .map_io = kirkwood_map_io, 126 .map_io = kirkwood_map_io,
diff --git a/arch/arm/mach-kirkwood/include/mach/debug-macro.S b/arch/arm/mach-kirkwood/include/mach/debug-macro.S
index d0606774dea7..db06ae437d08 100644
--- a/arch/arm/mach-kirkwood/include/mach/debug-macro.S
+++ b/arch/arm/mach-kirkwood/include/mach/debug-macro.S
@@ -8,12 +8,11 @@
8 8
9#include <mach/bridge-regs.h> 9#include <mach/bridge-regs.h>
10 10
11 .macro addruart, rx, tmp 11 .macro addruart, rp, rv
12 mrc p15, 0, \rx, c1, c0 12 ldr \rp, =KIRKWOOD_REGS_PHYS_BASE
13 tst \rx, #1 @ MMU enabled? 13 ldr \rv, =KIRKWOOD_REGS_VIRT_BASE
14 ldreq \rx, =KIRKWOOD_REGS_PHYS_BASE 14 orr \rp, \rp, #0x00012000
15 ldrne \rx, =KIRKWOOD_REGS_VIRT_BASE 15 orr \rv, \rv, #0x00012000
16 orr \rx, \rx, #0x00012000
17 .endm 16 .endm
18 17
19#define UART_SHIFT 2 18#define UART_SHIFT 2
diff --git a/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h b/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h
new file mode 100644
index 000000000000..24b536ebdf13
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/leds-netxbig.h
@@ -0,0 +1,55 @@
1/*
2 * arch/arm/mach-kirkwood/include/mach/leds-netxbig.h
3 *
4 * Platform data structure for netxbig LED driver
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __MACH_LEDS_NETXBIG_H
12#define __MACH_LEDS_NETXBIG_H
13
14struct netxbig_gpio_ext {
15 unsigned *addr;
16 int num_addr;
17 unsigned *data;
18 int num_data;
19 unsigned enable;
20};
21
22enum netxbig_led_mode {
23 NETXBIG_LED_OFF,
24 NETXBIG_LED_ON,
25 NETXBIG_LED_SATA,
26 NETXBIG_LED_TIMER1,
27 NETXBIG_LED_TIMER2,
28 NETXBIG_LED_MODE_NUM,
29};
30
31#define NETXBIG_LED_INVALID_MODE NETXBIG_LED_MODE_NUM
32
33struct netxbig_led_timer {
34 unsigned long delay_on;
35 unsigned long delay_off;
36 enum netxbig_led_mode mode;
37};
38
39struct netxbig_led {
40 const char *name;
41 const char *default_trigger;
42 int mode_addr;
43 int *mode_val;
44 int bright_addr;
45};
46
47struct netxbig_led_platform_data {
48 struct netxbig_gpio_ext *gpio_ext;
49 struct netxbig_led_timer *timer;
50 int num_timer;
51 struct netxbig_led *leds;
52 int num_leds;
53};
54
55#endif /* __MACH_LEDS_NETXBIG_H */
diff --git a/arch/arm/mach-kirkwood/lacie_v2-common.c b/arch/arm/mach-kirkwood/lacie_v2-common.c
new file mode 100644
index 000000000000..d3ea1b6c8a02
--- /dev/null
+++ b/arch/arm/mach-kirkwood/lacie_v2-common.c
@@ -0,0 +1,127 @@
1/*
2 * arch/arm/mach-kirkwood/lacie_v2-common.c
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <linux/kernel.h>
10#include <linux/init.h>
11#include <linux/mtd/physmap.h>
12#include <linux/spi/flash.h>
13#include <linux/spi/spi.h>
14#include <linux/i2c.h>
15#include <linux/i2c/at24.h>
16#include <linux/gpio.h>
17#include <asm/mach/time.h>
18#include <mach/kirkwood.h>
19#include <mach/irqs.h>
20#include <plat/time.h>
21#include "common.h"
22
23/*****************************************************************************
24 * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
25 ****************************************************************************/
26
27static struct mtd_partition lacie_v2_flash_parts[] = {
28 {
29 .name = "u-boot",
30 .size = MTDPART_SIZ_FULL,
31 .offset = 0,
32 .mask_flags = MTD_WRITEABLE, /* force read-only */
33 },
34};
35
36static const struct flash_platform_data lacie_v2_flash = {
37 .type = "mx25l4005a",
38 .name = "spi_flash",
39 .parts = lacie_v2_flash_parts,
40 .nr_parts = ARRAY_SIZE(lacie_v2_flash_parts),
41};
42
43static struct spi_board_info __initdata lacie_v2_spi_slave_info[] = {
44 {
45 .modalias = "m25p80",
46 .platform_data = &lacie_v2_flash,
47 .irq = -1,
48 .max_speed_hz = 20000000,
49 .bus_num = 0,
50 .chip_select = 0,
51 },
52};
53
54void __init lacie_v2_register_flash(void)
55{
56 spi_register_board_info(lacie_v2_spi_slave_info,
57 ARRAY_SIZE(lacie_v2_spi_slave_info));
58 kirkwood_spi_init();
59}
60
61/*****************************************************************************
62 * I2C devices
63 ****************************************************************************/
64
65static struct at24_platform_data at24c04 = {
66 .byte_len = SZ_4K / 8,
67 .page_size = 16,
68};
69
70/*
71 * i2c addr | chip | description
72 * 0x50 | HT24LC04 | eeprom (512B)
73 */
74
75static struct i2c_board_info __initdata lacie_v2_i2c_info[] = {
76 {
77 I2C_BOARD_INFO("24c04", 0x50),
78 .platform_data = &at24c04,
79 }
80};
81
82void __init lacie_v2_register_i2c_devices(void)
83{
84 kirkwood_i2c_init();
85 i2c_register_board_info(0, lacie_v2_i2c_info,
86 ARRAY_SIZE(lacie_v2_i2c_info));
87}
88
89/*****************************************************************************
90 * Hard Disk power
91 ****************************************************************************/
92
93static int __initdata lacie_v2_gpio_hdd_power[] = { 16, 17, 41, 42, 43 };
94
95void __init lacie_v2_hdd_power_init(int hdd_num)
96{
97 int i;
98 int err;
99
100 /* Power up all hard disks. */
101 for (i = 0; i < hdd_num; i++) {
102 err = gpio_request(lacie_v2_gpio_hdd_power[i], NULL);
103 if (err == 0) {
104 err = gpio_direction_output(
105 lacie_v2_gpio_hdd_power[i], 1);
106 /* Free the HDD power GPIOs. This allow user-space to
107 * configure them via the gpiolib sysfs interface. */
108 gpio_free(lacie_v2_gpio_hdd_power[i]);
109 }
110 if (err)
111 pr_err("Failed to power up HDD%d\n", i + 1);
112 }
113}
114
115/*****************************************************************************
116 * Timer
117 ****************************************************************************/
118
119static void lacie_v2_timer_init(void)
120{
121 kirkwood_tclk = 166666667;
122 orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
123}
124
125struct sys_timer lacie_v2_timer = {
126 .init = lacie_v2_timer_init,
127};
diff --git a/arch/arm/mach-kirkwood/lacie_v2-common.h b/arch/arm/mach-kirkwood/lacie_v2-common.h
new file mode 100644
index 000000000000..af521315b87b
--- /dev/null
+++ b/arch/arm/mach-kirkwood/lacie_v2-common.h
@@ -0,0 +1,18 @@
1/*
2 * arch/arm/mach-kirkwood/lacie_v2-common.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ARCH_KIRKWOOD_LACIE_V2_COMMON_H
10#define __ARCH_KIRKWOOD_LACIE_V2_COMMON_H
11
12void lacie_v2_register_flash(void);
13void lacie_v2_register_i2c_devices(void);
14void lacie_v2_hdd_power_init(int hdd_num);
15
16extern struct sys_timer lacie_v2_timer;
17
18#endif
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index c6b92b42eb4e..1e5266f57e2a 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -163,8 +163,6 @@ subsys_initcall(mv88f6281gtw_ge_pci_init);
163 163
164MACHINE_START(MV88F6281GTW_GE, "Marvell 88F6281 GTW GE Board") 164MACHINE_START(MV88F6281GTW_GE, "Marvell 88F6281 GTW GE Board")
165 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ 165 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
166 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
167 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
168 .boot_params = 0x00000100, 166 .boot_params = 0x00000100,
169 .init_machine = mv88f6281gtw_ge_init, 167 .init_machine = mv88f6281gtw_ge_init,
170 .map_io = kirkwood_map_io, 168 .map_io = kirkwood_map_io,
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index d26bf324738b..5e286441b8f4 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -24,56 +24,19 @@
24#include <linux/kernel.h> 24#include <linux/kernel.h>
25#include <linux/init.h> 25#include <linux/init.h>
26#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27#include <linux/mtd/physmap.h>
28#include <linux/spi/flash.h>
29#include <linux/spi/spi.h>
30#include <linux/ata_platform.h> 27#include <linux/ata_platform.h>
31#include <linux/mv643xx_eth.h> 28#include <linux/mv643xx_eth.h>
32#include <linux/i2c.h>
33#include <linux/i2c/at24.h>
34#include <linux/input.h> 29#include <linux/input.h>
35#include <linux/gpio.h> 30#include <linux/gpio.h>
36#include <linux/gpio_keys.h> 31#include <linux/gpio_keys.h>
37#include <linux/leds.h> 32#include <linux/leds.h>
38#include <asm/mach-types.h> 33#include <asm/mach-types.h>
39#include <asm/mach/arch.h> 34#include <asm/mach/arch.h>
40#include <asm/mach/time.h>
41#include <mach/kirkwood.h> 35#include <mach/kirkwood.h>
42#include <mach/leds-ns2.h> 36#include <mach/leds-ns2.h>
43#include <plat/time.h>
44#include "common.h" 37#include "common.h"
45#include "mpp.h" 38#include "mpp.h"
46 39#include "lacie_v2-common.h"
47/*****************************************************************************
48 * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
49 ****************************************************************************/
50
51static struct mtd_partition netspace_v2_flash_parts[] = {
52 {
53 .name = "u-boot",
54 .size = MTDPART_SIZ_FULL,
55 .offset = 0,
56 .mask_flags = MTD_WRITEABLE, /* force read-only */
57 },
58};
59
60static const struct flash_platform_data netspace_v2_flash = {
61 .type = "mx25l4005a",
62 .name = "spi_flash",
63 .parts = netspace_v2_flash_parts,
64 .nr_parts = ARRAY_SIZE(netspace_v2_flash_parts),
65};
66
67static struct spi_board_info __initdata netspace_v2_spi_slave_info[] = {
68 {
69 .modalias = "m25p80",
70 .platform_data = &netspace_v2_flash,
71 .irq = -1,
72 .max_speed_hz = 20000000,
73 .bus_num = 0,
74 .chip_select = 0,
75 },
76};
77 40
78/***************************************************************************** 41/*****************************************************************************
79 * Ethernet 42 * Ethernet
@@ -84,27 +47,6 @@ static struct mv643xx_eth_platform_data netspace_v2_ge00_data = {
84}; 47};
85 48
86/***************************************************************************** 49/*****************************************************************************
87 * I2C devices
88 ****************************************************************************/
89
90static struct at24_platform_data at24c04 = {
91 .byte_len = SZ_4K / 8,
92 .page_size = 16,
93};
94
95/*
96 * i2c addr | chip | description
97 * 0x50 | HT24LC04 | eeprom (512B)
98 */
99
100static struct i2c_board_info __initdata netspace_v2_i2c_info[] = {
101 {
102 I2C_BOARD_INFO("24c04", 0x50),
103 .platform_data = &at24c04,
104 }
105};
106
107/*****************************************************************************
108 * SATA 50 * SATA
109 ****************************************************************************/ 51 ****************************************************************************/
110 52
@@ -112,35 +54,6 @@ static struct mv_sata_platform_data netspace_v2_sata_data = {
112 .n_ports = 2, 54 .n_ports = 2,
113}; 55};
114 56
115#define NETSPACE_V2_GPIO_SATA0_POWER 16
116#define NETSPACE_V2_GPIO_SATA1_POWER 17
117
118static void __init netspace_v2_sata_power_init(void)
119{
120 int err;
121
122 err = gpio_request(NETSPACE_V2_GPIO_SATA0_POWER, "SATA0 power");
123 if (err == 0) {
124 err = gpio_direction_output(NETSPACE_V2_GPIO_SATA0_POWER, 1);
125 if (err)
126 gpio_free(NETSPACE_V2_GPIO_SATA0_POWER);
127 }
128 if (err)
129 pr_err("netspace_v2: failed to setup SATA0 power\n");
130
131 if (machine_is_netspace_max_v2()) {
132 err = gpio_request(NETSPACE_V2_GPIO_SATA1_POWER, "SATA1 power");
133 if (err == 0) {
134 err = gpio_direction_output(
135 NETSPACE_V2_GPIO_SATA1_POWER, 1);
136 if (err)
137 gpio_free(NETSPACE_V2_GPIO_SATA1_POWER);
138 }
139 if (err)
140 pr_err("netspace_v2: failed to setup SATA1 power\n");
141 }
142}
143
144/***************************************************************************** 57/*****************************************************************************
145 * GPIO keys 58 * GPIO keys
146 ****************************************************************************/ 59 ****************************************************************************/
@@ -224,20 +137,6 @@ static struct platform_device netspace_v2_leds = {
224}; 137};
225 138
226/***************************************************************************** 139/*****************************************************************************
227 * Timer
228 ****************************************************************************/
229
230static void netspace_v2_timer_init(void)
231{
232 kirkwood_tclk = 166666667;
233 orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
234}
235
236struct sys_timer netspace_v2_timer = {
237 .init = netspace_v2_timer_init,
238};
239
240/*****************************************************************************
241 * General Setup 140 * General Setup
242 ****************************************************************************/ 141 ****************************************************************************/
243 142
@@ -291,18 +190,17 @@ static void __init netspace_v2_init(void)
291 kirkwood_init(); 190 kirkwood_init();
292 kirkwood_mpp_conf(netspace_v2_mpp_config); 191 kirkwood_mpp_conf(netspace_v2_mpp_config);
293 192
294 netspace_v2_sata_power_init(); 193 if (machine_is_netspace_max_v2())
194 lacie_v2_hdd_power_init(2);
195 else
196 lacie_v2_hdd_power_init(1);
295 197
296 kirkwood_ehci_init(); 198 kirkwood_ehci_init();
297 kirkwood_ge00_init(&netspace_v2_ge00_data); 199 kirkwood_ge00_init(&netspace_v2_ge00_data);
298 kirkwood_sata_init(&netspace_v2_sata_data); 200 kirkwood_sata_init(&netspace_v2_sata_data);
299 kirkwood_uart0_init(); 201 kirkwood_uart0_init();
300 spi_register_board_info(netspace_v2_spi_slave_info, 202 lacie_v2_register_flash();
301 ARRAY_SIZE(netspace_v2_spi_slave_info)); 203 lacie_v2_register_i2c_devices();
302 kirkwood_spi_init();
303 kirkwood_i2c_init();
304 i2c_register_board_info(0, netspace_v2_i2c_info,
305 ARRAY_SIZE(netspace_v2_i2c_info));
306 204
307 platform_device_register(&netspace_v2_leds); 205 platform_device_register(&netspace_v2_leds);
308 platform_device_register(&netspace_v2_gpio_leds); 206 platform_device_register(&netspace_v2_gpio_leds);
@@ -317,36 +215,30 @@ static void __init netspace_v2_init(void)
317 215
318#ifdef CONFIG_MACH_NETSPACE_V2 216#ifdef CONFIG_MACH_NETSPACE_V2
319MACHINE_START(NETSPACE_V2, "LaCie Network Space v2") 217MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
320 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
321 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
322 .boot_params = 0x00000100, 218 .boot_params = 0x00000100,
323 .init_machine = netspace_v2_init, 219 .init_machine = netspace_v2_init,
324 .map_io = kirkwood_map_io, 220 .map_io = kirkwood_map_io,
325 .init_irq = kirkwood_init_irq, 221 .init_irq = kirkwood_init_irq,
326 .timer = &netspace_v2_timer, 222 .timer = &lacie_v2_timer,
327MACHINE_END 223MACHINE_END
328#endif 224#endif
329 225
330#ifdef CONFIG_MACH_INETSPACE_V2 226#ifdef CONFIG_MACH_INETSPACE_V2
331MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2") 227MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
332 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
333 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
334 .boot_params = 0x00000100, 228 .boot_params = 0x00000100,
335 .init_machine = netspace_v2_init, 229 .init_machine = netspace_v2_init,
336 .map_io = kirkwood_map_io, 230 .map_io = kirkwood_map_io,
337 .init_irq = kirkwood_init_irq, 231 .init_irq = kirkwood_init_irq,
338 .timer = &netspace_v2_timer, 232 .timer = &lacie_v2_timer,
339MACHINE_END 233MACHINE_END
340#endif 234#endif
341 235
342#ifdef CONFIG_MACH_NETSPACE_MAX_V2 236#ifdef CONFIG_MACH_NETSPACE_MAX_V2
343MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2") 237MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
344 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
345 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
346 .boot_params = 0x00000100, 238 .boot_params = 0x00000100,
347 .init_machine = netspace_v2_init, 239 .init_machine = netspace_v2_init,
348 .map_io = kirkwood_map_io, 240 .map_io = kirkwood_map_io,
349 .init_irq = kirkwood_init_irq, 241 .init_irq = kirkwood_init_irq,
350 .timer = &netspace_v2_timer, 242 .timer = &lacie_v2_timer,
351MACHINE_END 243MACHINE_END
352#endif 244#endif
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 2bd14c5079de..a1b45d501aef 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -23,55 +23,19 @@
23#include <linux/kernel.h> 23#include <linux/kernel.h>
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <linux/mtd/physmap.h>
27#include <linux/spi/flash.h>
28#include <linux/spi/spi.h>
29#include <linux/ata_platform.h> 26#include <linux/ata_platform.h>
30#include <linux/mv643xx_eth.h> 27#include <linux/mv643xx_eth.h>
31#include <linux/i2c.h>
32#include <linux/i2c/at24.h>
33#include <linux/input.h> 28#include <linux/input.h>
34#include <linux/gpio.h> 29#include <linux/gpio.h>
35#include <linux/gpio_keys.h> 30#include <linux/gpio_keys.h>
36#include <linux/leds.h> 31#include <linux/leds.h>
37#include <asm/mach-types.h> 32#include <asm/mach-types.h>
38#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
39#include <asm/mach/time.h>
40#include <mach/kirkwood.h> 34#include <mach/kirkwood.h>
41#include <plat/time.h> 35#include <mach/leds-netxbig.h>
42#include "common.h" 36#include "common.h"
43#include "mpp.h" 37#include "mpp.h"
44 38#include "lacie_v2-common.h"
45/*****************************************************************************
46 * 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
47 ****************************************************************************/
48
49static struct mtd_partition netxbig_v2_flash_parts[] = {
50 {
51 .name = "u-boot",
52 .size = MTDPART_SIZ_FULL,
53 .offset = 0,
54 .mask_flags = MTD_WRITEABLE, /* force read-only */
55 },
56};
57
58static const struct flash_platform_data netxbig_v2_flash = {
59 .type = "mx25l4005a",
60 .name = "spi_flash",
61 .parts = netxbig_v2_flash_parts,
62 .nr_parts = ARRAY_SIZE(netxbig_v2_flash_parts),
63};
64
65static struct spi_board_info __initdata netxbig_v2_spi_slave_info[] = {
66 {
67 .modalias = "m25p80",
68 .platform_data = &netxbig_v2_flash,
69 .irq = -1,
70 .max_speed_hz = 20000000,
71 .bus_num = 0,
72 .chip_select = 0,
73 },
74};
75 39
76/***************************************************************************** 40/*****************************************************************************
77 * Ethernet 41 * Ethernet
@@ -86,27 +50,6 @@ static struct mv643xx_eth_platform_data netxbig_v2_ge01_data = {
86}; 50};
87 51
88/***************************************************************************** 52/*****************************************************************************
89 * I2C devices
90 ****************************************************************************/
91
92static struct at24_platform_data at24c04 = {
93 .byte_len = SZ_4K / 8,
94 .page_size = 16,
95};
96
97/*
98 * i2c addr | chip | description
99 * 0x50 | HT24LC04 | eeprom (512B)
100 */
101
102static struct i2c_board_info __initdata netxbig_v2_i2c_info[] = {
103 {
104 I2C_BOARD_INFO("24c04", 0x50),
105 .platform_data = &at24c04,
106 }
107};
108
109/*****************************************************************************
110 * SATA 53 * SATA
111 ****************************************************************************/ 54 ****************************************************************************/
112 55
@@ -114,34 +57,6 @@ static struct mv_sata_platform_data netxbig_v2_sata_data = {
114 .n_ports = 2, 57 .n_ports = 2,
115}; 58};
116 59
117static int __initdata netxbig_v2_gpio_hdd_power[] = { 16, 17, 41, 42, 43 };
118
119static void __init netxbig_v2_sata_power_init(void)
120{
121 int i;
122 int err;
123 int hdd_nb;
124
125 if (machine_is_net2big_v2())
126 hdd_nb = 2;
127 else
128 hdd_nb = 5;
129
130 /* Power up all hard disks. */
131 for (i = 0; i < hdd_nb; i++) {
132 err = gpio_request(netxbig_v2_gpio_hdd_power[i], NULL);
133 if (err == 0) {
134 err = gpio_direction_output(
135 netxbig_v2_gpio_hdd_power[i], 1);
136 /* Free the HDD power GPIOs. This allow user-space to
137 * configure them via the gpiolib sysfs interface. */
138 gpio_free(netxbig_v2_gpio_hdd_power[i]);
139 }
140 if (err)
141 pr_err("netxbig_v2: failed to power up HDD%d\n", i + 1);
142 }
143}
144
145/***************************************************************************** 60/*****************************************************************************
146 * GPIO keys 61 * GPIO keys
147 ****************************************************************************/ 62 ****************************************************************************/
@@ -190,7 +105,7 @@ static struct platform_device netxbig_v2_gpio_buttons = {
190}; 105};
191 106
192/***************************************************************************** 107/*****************************************************************************
193 * GPIO LEDs 108 * GPIO extension LEDs
194 ****************************************************************************/ 109 ****************************************************************************/
195 110
196/* 111/*
@@ -200,19 +115,32 @@ static struct platform_device netxbig_v2_gpio_buttons = {
200 * - address register : bit [0-2] -> GPIO [47-49] 115 * - address register : bit [0-2] -> GPIO [47-49]
201 * - data register : bit [0-2] -> GPIO [44-46] 116 * - data register : bit [0-2] -> GPIO [44-46]
202 * - enable register : GPIO 29 117 * - enable register : GPIO 29
203 * 118 */
119
120static int netxbig_v2_gpio_ext_addr[] = { 47, 48, 49 };
121static int netxbig_v2_gpio_ext_data[] = { 44, 45, 46 };
122
123static struct netxbig_gpio_ext netxbig_v2_gpio_ext = {
124 .addr = netxbig_v2_gpio_ext_addr,
125 .num_addr = ARRAY_SIZE(netxbig_v2_gpio_ext_addr),
126 .data = netxbig_v2_gpio_ext_data,
127 .num_data = ARRAY_SIZE(netxbig_v2_gpio_ext_data),
128 .enable = 29,
129};
130
131/*
204 * Address register selection: 132 * Address register selection:
205 * 133 *
206 * addr | register 134 * addr | register
207 * ---------------------------- 135 * ----------------------------
208 * 0 | front LED 136 * 0 | front LED
209 * 1 | front LED brightness 137 * 1 | front LED brightness
210 * 2 | HDD LED brightness 138 * 2 | SATA LED brightness
211 * 3 | HDD1 LED 139 * 3 | SATA0 LED
212 * 4 | HDD2 LED 140 * 4 | SATA1 LED
213 * 5 | HDD3 LED 141 * 5 | SATA2 LED
214 * 6 | HDD4 LED 142 * 6 | SATA3 LED
215 * 7 | HDD5 LED 143 * 7 | SATA4 LED
216 * 144 *
217 * Data register configuration: 145 * Data register configuration:
218 * 146 *
@@ -233,30 +161,107 @@ static struct platform_device netxbig_v2_gpio_buttons = {
233 * 6 | blink blue on=1 sec and red on=1 sec 161 * 6 | blink blue on=1 sec and red on=1 sec
234 * 7 | blink blue on=0.5 sec and blue off=2.5 sec 162 * 7 | blink blue on=0.5 sec and blue off=2.5 sec
235 * 163 *
236 * data | HDD LED mode 164 * data | SATA LED mode
237 * ------------------------------------------------- 165 * -------------------------------------------------
238 * 0 | fix blue on 166 * 0 | fix off
239 * 1 | SATA activity blink 167 * 1 | SATA activity blink
240 * 2 | fix red on 168 * 2 | fix red on
241 * 3 | blink blue on=1 sec and blue off=1 sec 169 * 3 | blink blue on=1 sec and blue off=1 sec
242 * 4 | blink red on=1 sec and red off=1 sec 170 * 4 | blink red on=1 sec and red off=1 sec
243 * 5 | blink blue on=2.5 sec and red on=0.5 sec 171 * 5 | blink blue on=2.5 sec and red on=0.5 sec
244 * 6 | blink blue on=1 sec and red on=1 sec 172 * 6 | blink blue on=1 sec and red on=1 sec
245 * 7 | blink blue on=0.5 sec and blue off=2.5 sec 173 * 7 | fix blue on
246 */ 174 */
247 175
248/***************************************************************************** 176static int netxbig_v2_red_mled[NETXBIG_LED_MODE_NUM] = {
249 * Timer 177 [NETXBIG_LED_OFF] = 0,
250 ****************************************************************************/ 178 [NETXBIG_LED_ON] = 2,
179 [NETXBIG_LED_SATA] = NETXBIG_LED_INVALID_MODE,
180 [NETXBIG_LED_TIMER1] = 4,
181 [NETXBIG_LED_TIMER2] = NETXBIG_LED_INVALID_MODE,
182};
251 183
252static void netxbig_v2_timer_init(void) 184static int netxbig_v2_blue_pwr_mled[NETXBIG_LED_MODE_NUM] = {
253{ 185 [NETXBIG_LED_OFF] = 0,
254 kirkwood_tclk = 166666667; 186 [NETXBIG_LED_ON] = 1,
255 orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk); 187 [NETXBIG_LED_SATA] = NETXBIG_LED_INVALID_MODE,
256} 188 [NETXBIG_LED_TIMER1] = 3,
189 [NETXBIG_LED_TIMER2] = 7,
190};
191
192static int netxbig_v2_blue_sata_mled[NETXBIG_LED_MODE_NUM] = {
193 [NETXBIG_LED_OFF] = 0,
194 [NETXBIG_LED_ON] = 7,
195 [NETXBIG_LED_SATA] = 1,
196 [NETXBIG_LED_TIMER1] = 3,
197 [NETXBIG_LED_TIMER2] = NETXBIG_LED_INVALID_MODE,
198};
199
200static struct netxbig_led_timer netxbig_v2_led_timer[] = {
201 [0] = {
202 .delay_on = 500,
203 .delay_off = 500,
204 .mode = NETXBIG_LED_TIMER1,
205 },
206 [1] = {
207 .delay_on = 500,
208 .delay_off = 1000,
209 .mode = NETXBIG_LED_TIMER2,
210 },
211};
212
213#define NETXBIG_LED(_name, maddr, mval, baddr) \
214 { .name = _name, \
215 .mode_addr = maddr, \
216 .mode_val = mval, \
217 .bright_addr = baddr }
218
219static struct netxbig_led net2big_v2_leds_ctrl[] = {
220 NETXBIG_LED("net2big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled, 1),
221 NETXBIG_LED("net2big-v2:red:power", 0, netxbig_v2_red_mled, 1),
222 NETXBIG_LED("net2big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2),
223 NETXBIG_LED("net2big-v2:red:sata0", 3, netxbig_v2_red_mled, 2),
224 NETXBIG_LED("net2big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2),
225 NETXBIG_LED("net2big-v2:red:sata1", 4, netxbig_v2_red_mled, 2),
226};
227
228static struct netxbig_led_platform_data net2big_v2_leds_data = {
229 .gpio_ext = &netxbig_v2_gpio_ext,
230 .timer = netxbig_v2_led_timer,
231 .num_timer = ARRAY_SIZE(netxbig_v2_led_timer),
232 .leds = net2big_v2_leds_ctrl,
233 .num_leds = ARRAY_SIZE(net2big_v2_leds_ctrl),
234};
235
236static struct netxbig_led net5big_v2_leds_ctrl[] = {
237 NETXBIG_LED("net5big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled, 1),
238 NETXBIG_LED("net5big-v2:red:power", 0, netxbig_v2_red_mled, 1),
239 NETXBIG_LED("net5big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2),
240 NETXBIG_LED("net5big-v2:red:sata0", 3, netxbig_v2_red_mled, 2),
241 NETXBIG_LED("net5big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2),
242 NETXBIG_LED("net5big-v2:red:sata1", 4, netxbig_v2_red_mled, 2),
243 NETXBIG_LED("net5big-v2:blue:sata2", 5, netxbig_v2_blue_sata_mled, 2),
244 NETXBIG_LED("net5big-v2:red:sata2", 5, netxbig_v2_red_mled, 2),
245 NETXBIG_LED("net5big-v2:blue:sata3", 6, netxbig_v2_blue_sata_mled, 2),
246 NETXBIG_LED("net5big-v2:red:sata3", 6, netxbig_v2_red_mled, 2),
247 NETXBIG_LED("net5big-v2:blue:sata4", 7, netxbig_v2_blue_sata_mled, 2),
248 NETXBIG_LED("net5big-v2:red:sata5", 7, netxbig_v2_red_mled, 2),
249};
257 250
258struct sys_timer netxbig_v2_timer = { 251static struct netxbig_led_platform_data net5big_v2_leds_data = {
259 .init = netxbig_v2_timer_init, 252 .gpio_ext = &netxbig_v2_gpio_ext,
253 .timer = netxbig_v2_led_timer,
254 .num_timer = ARRAY_SIZE(netxbig_v2_led_timer),
255 .leds = net5big_v2_leds_ctrl,
256 .num_leds = ARRAY_SIZE(net5big_v2_leds_ctrl),
257};
258
259static struct platform_device netxbig_v2_leds = {
260 .name = "leds-netxbig",
261 .id = -1,
262 .dev = {
263 .platform_data = &net2big_v2_leds_data,
264 },
260}; 265};
261 266
262/***************************************************************************** 267/*****************************************************************************
@@ -284,18 +289,18 @@ static unsigned int net2big_v2_mpp_config[] __initdata = {
284 MPP24_GPIO, /* USB mode select */ 289 MPP24_GPIO, /* USB mode select */
285 MPP26_GPIO, /* USB device vbus */ 290 MPP26_GPIO, /* USB device vbus */
286 MPP28_GPIO, /* USB enable host vbus */ 291 MPP28_GPIO, /* USB enable host vbus */
287 MPP29_GPIO, /* CPLD extension ALE */ 292 MPP29_GPIO, /* GPIO extension ALE */
288 MPP34_GPIO, /* Rear Push button */ 293 MPP34_GPIO, /* Rear Push button */
289 MPP35_GPIO, /* Inhibit switch power-off */ 294 MPP35_GPIO, /* Inhibit switch power-off */
290 MPP36_GPIO, /* SATA HDD1 presence */ 295 MPP36_GPIO, /* SATA HDD1 presence */
291 MPP37_GPIO, /* SATA HDD2 presence */ 296 MPP37_GPIO, /* SATA HDD2 presence */
292 MPP40_GPIO, /* eSATA presence */ 297 MPP40_GPIO, /* eSATA presence */
293 MPP44_GPIO, /* CPLD extension (data 0) */ 298 MPP44_GPIO, /* GPIO extension (data 0) */
294 MPP45_GPIO, /* CPLD extension (data 1) */ 299 MPP45_GPIO, /* GPIO extension (data 1) */
295 MPP46_GPIO, /* CPLD extension (data 2) */ 300 MPP46_GPIO, /* GPIO extension (data 2) */
296 MPP47_GPIO, /* CPLD extension (addr 0) */ 301 MPP47_GPIO, /* GPIO extension (addr 0) */
297 MPP48_GPIO, /* CPLD extension (addr 1) */ 302 MPP48_GPIO, /* GPIO extension (addr 1) */
298 MPP49_GPIO, /* CPLD extension (addr 2) */ 303 MPP49_GPIO, /* GPIO extension (addr 2) */
299 0 304 0
300}; 305};
301 306
@@ -324,7 +329,7 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
324 MPP26_GE1_RXD2, 329 MPP26_GE1_RXD2,
325 MPP27_GE1_RXD3, 330 MPP27_GE1_RXD3,
326 MPP28_GPIO, /* USB enable host vbus */ 331 MPP28_GPIO, /* USB enable host vbus */
327 MPP29_GPIO, /* CPLD extension ALE */ 332 MPP29_GPIO, /* GPIO extension ALE */
328 MPP30_GE1_RXCTL, 333 MPP30_GE1_RXCTL,
329 MPP31_GE1_RXCLK, 334 MPP31_GE1_RXCLK,
330 MPP32_GE1_TCLKOUT, 335 MPP32_GE1_TCLKOUT,
@@ -339,12 +344,12 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
339 MPP41_GPIO, /* SATA HDD3 power */ 344 MPP41_GPIO, /* SATA HDD3 power */
340 MPP42_GPIO, /* SATA HDD4 power */ 345 MPP42_GPIO, /* SATA HDD4 power */
341 MPP43_GPIO, /* SATA HDD5 power */ 346 MPP43_GPIO, /* SATA HDD5 power */
342 MPP44_GPIO, /* CPLD extension (data 0) */ 347 MPP44_GPIO, /* GPIO extension (data 0) */
343 MPP45_GPIO, /* CPLD extension (data 1) */ 348 MPP45_GPIO, /* GPIO extension (data 1) */
344 MPP46_GPIO, /* CPLD extension (data 2) */ 349 MPP46_GPIO, /* GPIO extension (data 2) */
345 MPP47_GPIO, /* CPLD extension (addr 0) */ 350 MPP47_GPIO, /* GPIO extension (addr 0) */
346 MPP48_GPIO, /* CPLD extension (addr 1) */ 351 MPP48_GPIO, /* GPIO extension (addr 1) */
347 MPP49_GPIO, /* CPLD extension (addr 2) */ 352 MPP49_GPIO, /* GPIO extension (addr 2) */
348 0 353 0
349}; 354};
350 355
@@ -366,7 +371,10 @@ static void __init netxbig_v2_init(void)
366 else 371 else
367 kirkwood_mpp_conf(net5big_v2_mpp_config); 372 kirkwood_mpp_conf(net5big_v2_mpp_config);
368 373
369 netxbig_v2_sata_power_init(); 374 if (machine_is_net2big_v2())
375 lacie_v2_hdd_power_init(2);
376 else
377 lacie_v2_hdd_power_init(5);
370 378
371 kirkwood_ehci_init(); 379 kirkwood_ehci_init();
372 kirkwood_ge00_init(&netxbig_v2_ge00_data); 380 kirkwood_ge00_init(&netxbig_v2_ge00_data);
@@ -374,13 +382,12 @@ static void __init netxbig_v2_init(void)
374 kirkwood_ge01_init(&netxbig_v2_ge01_data); 382 kirkwood_ge01_init(&netxbig_v2_ge01_data);
375 kirkwood_sata_init(&netxbig_v2_sata_data); 383 kirkwood_sata_init(&netxbig_v2_sata_data);
376 kirkwood_uart0_init(); 384 kirkwood_uart0_init();
377 spi_register_board_info(netxbig_v2_spi_slave_info, 385 lacie_v2_register_flash();
378 ARRAY_SIZE(netxbig_v2_spi_slave_info)); 386 lacie_v2_register_i2c_devices();
379 kirkwood_spi_init();
380 kirkwood_i2c_init();
381 i2c_register_board_info(0, netxbig_v2_i2c_info,
382 ARRAY_SIZE(netxbig_v2_i2c_info));
383 387
388 if (machine_is_net5big_v2())
389 netxbig_v2_leds.dev.platform_data = &net5big_v2_leds_data;
390 platform_device_register(&netxbig_v2_leds);
384 platform_device_register(&netxbig_v2_gpio_buttons); 391 platform_device_register(&netxbig_v2_gpio_buttons);
385 392
386 if (gpio_request(NETXBIG_V2_GPIO_POWER_OFF, "power-off") == 0 && 393 if (gpio_request(NETXBIG_V2_GPIO_POWER_OFF, "power-off") == 0 &&
@@ -392,24 +399,20 @@ static void __init netxbig_v2_init(void)
392 399
393#ifdef CONFIG_MACH_NET2BIG_V2 400#ifdef CONFIG_MACH_NET2BIG_V2
394MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2") 401MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
395 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
396 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
397 .boot_params = 0x00000100, 402 .boot_params = 0x00000100,
398 .init_machine = netxbig_v2_init, 403 .init_machine = netxbig_v2_init,
399 .map_io = kirkwood_map_io, 404 .map_io = kirkwood_map_io,
400 .init_irq = kirkwood_init_irq, 405 .init_irq = kirkwood_init_irq,
401 .timer = &netxbig_v2_timer, 406 .timer = &lacie_v2_timer,
402MACHINE_END 407MACHINE_END
403#endif 408#endif
404 409
405#ifdef CONFIG_MACH_NET5BIG_V2 410#ifdef CONFIG_MACH_NET5BIG_V2
406MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2") 411MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
407 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
408 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
409 .boot_params = 0x00000100, 412 .boot_params = 0x00000100,
410 .init_machine = netxbig_v2_init, 413 .init_machine = netxbig_v2_init,
411 .map_io = kirkwood_map_io, 414 .map_io = kirkwood_map_io,
412 .init_irq = kirkwood_init_irq, 415 .init_irq = kirkwood_init_irq,
413 .timer = &netxbig_v2_timer, 416 .timer = &lacie_v2_timer,
414MACHINE_END 417MACHINE_END
415#endif 418#endif
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index fd06be618815..c9d77fad10ab 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -16,6 +16,7 @@
16#include <linux/ata_platform.h> 16#include <linux/ata_platform.h>
17#include <linux/mv643xx_eth.h> 17#include <linux/mv643xx_eth.h>
18#include <linux/i2c.h> 18#include <linux/i2c.h>
19#include <linux/gpio.h>
19#include <asm/mach-types.h> 20#include <asm/mach-types.h>
20#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
21#include <mach/kirkwood.h> 22#include <mach/kirkwood.h>
@@ -57,7 +58,22 @@ static struct mvsdio_platform_data openrd_mvsdio_data = {
57}; 58};
58 59
59static unsigned int openrd_mpp_config[] __initdata = { 60static unsigned int openrd_mpp_config[] __initdata = {
61 MPP12_SD_CLK,
62 MPP13_SD_CMD,
63 MPP14_SD_D0,
64 MPP15_SD_D1,
65 MPP16_SD_D2,
66 MPP17_SD_D3,
67 MPP28_GPIO,
60 MPP29_GPIO, 68 MPP29_GPIO,
69 MPP34_GPIO,
70 0
71};
72
73/* Configure MPP for UART1 */
74static unsigned int openrd_uart1_mpp_config[] __initdata = {
75 MPP13_UART1_TXD,
76 MPP14_UART1_RXD,
61 0 77 0
62}; 78};
63 79
@@ -67,6 +83,68 @@ static struct i2c_board_info i2c_board_info[] __initdata = {
67 }, 83 },
68}; 84};
69 85
86static int __initdata uart1;
87
88static int __init sd_uart_selection(char *str)
89{
90 uart1 = -EINVAL;
91
92 /* Default is SD. Change if required, for UART */
93 if (!str)
94 return 0;
95
96 if (!strncmp(str, "232", 3)) {
97 uart1 = 232;
98 } else if (!strncmp(str, "485", 3)) {
99 /* OpenRD-Base doesn't have RS485. Treat is as an
100 * unknown argument & just have default setting -
101 * which is SD */
102 if (machine_is_openrd_base()) {
103 uart1 = -ENODEV;
104 return 1;
105 }
106
107 uart1 = 485;
108 }
109 return 1;
110}
111/* Parse boot_command_line string kw_openrd_init_uart1=232/485 */
112__setup("kw_openrd_init_uart1=", sd_uart_selection);
113
114static int __init uart1_mpp_config(void)
115{
116 kirkwood_mpp_conf(openrd_uart1_mpp_config);
117
118 if (gpio_request(34, "SD_UART1_SEL")) {
119 printk(KERN_ERR "GPIO request failed for SD/UART1 selection"
120 ", gpio: 34\n");
121 return -EIO;
122 }
123
124 if (gpio_request(28, "RS232_RS485_SEL")) {
125 printk(KERN_ERR "GPIO request failed for RS232/RS485 selection"
126 ", gpio# 28\n");
127 gpio_free(34);
128 return -EIO;
129 }
130
131 /* Select UART1
132 * Pin # 34: 0 => UART1, 1 => SD */
133 gpio_direction_output(34, 0);
134
135 /* Select RS232 OR RS485
136 * Pin # 28: 0 => RS232, 1 => RS485 */
137 if (uart1 == 232)
138 gpio_direction_output(28, 0);
139 else
140 gpio_direction_output(28, 1);
141
142 gpio_free(34);
143 gpio_free(28);
144
145 return 0;
146}
147
70static void __init openrd_init(void) 148static void __init openrd_init(void)
71{ 149{
72 /* 150 /*
@@ -90,7 +168,6 @@ static void __init openrd_init(void)
90 kirkwood_ge01_init(&openrd_ge01_data); 168 kirkwood_ge01_init(&openrd_ge01_data);
91 169
92 kirkwood_sata_init(&openrd_sata_data); 170 kirkwood_sata_init(&openrd_sata_data);
93 kirkwood_sdio_init(&openrd_mvsdio_data);
94 171
95 kirkwood_i2c_init(); 172 kirkwood_i2c_init();
96 173
@@ -99,6 +176,28 @@ static void __init openrd_init(void)
99 ARRAY_SIZE(i2c_board_info)); 176 ARRAY_SIZE(i2c_board_info));
100 kirkwood_audio_init(); 177 kirkwood_audio_init();
101 } 178 }
179
180 if (uart1 <= 0) {
181 if (uart1 < 0)
182 printk(KERN_ERR "Invalid kernel parameter to select "
183 "UART1. Defaulting to SD. ERROR CODE: %d\n",
184 uart1);
185
186 /* Select SD
187 * Pin # 34: 0 => UART1, 1 => SD */
188 if (gpio_request(34, "SD_UART1_SEL")) {
189 printk(KERN_ERR "GPIO request failed for SD/UART1 "
190 "selection, gpio: 34\n");
191 } else {
192
193 gpio_direction_output(34, 1);
194 gpio_free(34);
195 kirkwood_sdio_init(&openrd_mvsdio_data);
196 }
197 } else {
198 if (!uart1_mpp_config())
199 kirkwood_uart1_init();
200 }
102} 201}
103 202
104static int __init openrd_pci_init(void) 203static int __init openrd_pci_init(void)
@@ -115,8 +214,6 @@ subsys_initcall(openrd_pci_init);
115#ifdef CONFIG_MACH_OPENRD_BASE 214#ifdef CONFIG_MACH_OPENRD_BASE
116MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board") 215MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board")
117 /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */ 216 /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
118 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
119 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
120 .boot_params = 0x00000100, 217 .boot_params = 0x00000100,
121 .init_machine = openrd_init, 218 .init_machine = openrd_init,
122 .map_io = kirkwood_map_io, 219 .map_io = kirkwood_map_io,
@@ -128,8 +225,6 @@ MACHINE_END
128#ifdef CONFIG_MACH_OPENRD_CLIENT 225#ifdef CONFIG_MACH_OPENRD_CLIENT
129MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board") 226MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
130 /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */ 227 /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
131 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
132 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
133 .boot_params = 0x00000100, 228 .boot_params = 0x00000100,
134 .init_machine = openrd_init, 229 .init_machine = openrd_init,
135 .map_io = kirkwood_map_io, 230 .map_io = kirkwood_map_io,
@@ -141,8 +236,6 @@ MACHINE_END
141#ifdef CONFIG_MACH_OPENRD_ULTIMATE 236#ifdef CONFIG_MACH_OPENRD_ULTIMATE
142MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board") 237MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
143 /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */ 238 /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
144 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
145 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
146 .boot_params = 0x00000100, 239 .boot_params = 0x00000100,
147 .init_machine = openrd_init, 240 .init_machine = openrd_init,
148 .map_io = kirkwood_map_io, 241 .map_io = kirkwood_map_io,
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index c34718c2cfe5..0049614cd324 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -79,8 +79,6 @@ subsys_initcall(rd88f6192_pci_init);
79 79
80MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board") 80MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board")
81 /* Maintainer: Saeed Bishara <saeed@marvell.com> */ 81 /* Maintainer: Saeed Bishara <saeed@marvell.com> */
82 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
83 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
84 .boot_params = 0x00000100, 82 .boot_params = 0x00000100,
85 .init_machine = rd88f6192_init, 83 .init_machine = rd88f6192_init,
86 .map_io = kirkwood_map_io, 84 .map_io = kirkwood_map_io,
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 3d1477135e12..0998a08cf42d 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -115,8 +115,6 @@ subsys_initcall(rd88f6281_pci_init);
115 115
116MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board") 116MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board")
117 /* Maintainer: Saeed Bishara <saeed@marvell.com> */ 117 /* Maintainer: Saeed Bishara <saeed@marvell.com> */
118 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
119 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
120 .boot_params = 0x00000100, 118 .boot_params = 0x00000100,
121 .init_machine = rd88f6281_init, 119 .init_machine = rd88f6281_init,
122 .map_io = kirkwood_map_io, 120 .map_io = kirkwood_map_io,
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c
index a00879d34d54..d2eec35dfe0f 100644
--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
@@ -131,8 +131,6 @@ static void __init sheevaplug_init(void)
131#ifdef CONFIG_MACH_SHEEVAPLUG 131#ifdef CONFIG_MACH_SHEEVAPLUG
132MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board") 132MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board")
133 /* Maintainer: shadi Ammouri <shadi@marvell.com> */ 133 /* Maintainer: shadi Ammouri <shadi@marvell.com> */
134 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
135 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
136 .boot_params = 0x00000100, 134 .boot_params = 0x00000100,
137 .init_machine = sheevaplug_init, 135 .init_machine = sheevaplug_init,
138 .map_io = kirkwood_map_io, 136 .map_io = kirkwood_map_io,
@@ -143,8 +141,6 @@ MACHINE_END
143 141
144#ifdef CONFIG_MACH_ESATA_SHEEVAPLUG 142#ifdef CONFIG_MACH_ESATA_SHEEVAPLUG
145MACHINE_START(ESATA_SHEEVAPLUG, "Marvell eSATA SheevaPlug Reference Board") 143MACHINE_START(ESATA_SHEEVAPLUG, "Marvell eSATA SheevaPlug Reference Board")
146 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
147 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
148 .boot_params = 0x00000100, 144 .boot_params = 0x00000100,
149 .init_machine = sheevaplug_init, 145 .init_machine = sheevaplug_init,
150 .map_io = kirkwood_map_io, 146 .map_io = kirkwood_map_io,
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
index d01bf89cedbe..ce50e61aac9f 100644
--- a/arch/arm/mach-kirkwood/t5325-setup.c
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -184,8 +184,6 @@ subsys_initcall(hp_t5325_pci_init);
184 184
185MACHINE_START(T5325, "HP t5325 Thin Client") 185MACHINE_START(T5325, "HP t5325 Thin Client")
186 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */ 186 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
187 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
188 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
189 .boot_params = 0x00000100, 187 .boot_params = 0x00000100,
190 .init_machine = hp_t5325_init, 188 .init_machine = hp_t5325_init,
191 .map_io = kirkwood_map_io, 189 .map_io = kirkwood_map_io,
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index a5bd7fde04a9..6710bd7773b8 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -120,8 +120,6 @@ subsys_initcall(ts219_pci_init);
120 120
121MACHINE_START(TS219, "QNAP TS-119/TS-219") 121MACHINE_START(TS219, "QNAP TS-119/TS-219")
122 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */ 122 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
123 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
124 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
125 .boot_params = 0x00000100, 123 .boot_params = 0x00000100,
126 .init_machine = qnap_ts219_init, 124 .init_machine = qnap_ts219_init,
127 .map_io = kirkwood_map_io, 125 .map_io = kirkwood_map_io,
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index 2e14afef07a2..8be09a0ce4ac 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -149,8 +149,6 @@ subsys_initcall(ts41x_pci_init);
149 149
150MACHINE_START(TS41X, "QNAP TS-41x") 150MACHINE_START(TS41X, "QNAP TS-41x")
151 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */ 151 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
152 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
153 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
154 .boot_params = 0x00000100, 152 .boot_params = 0x00000100,
155 .init_machine = qnap_ts41x_init, 153 .init_machine = qnap_ts41x_init,
156 .map_io = kirkwood_map_io, 154 .map_io = kirkwood_map_io,
diff --git a/arch/arm/mach-ks8695/board-acs5k.c b/arch/arm/mach-ks8695/board-acs5k.c
index 9e3e5a640ad2..3ca4f8e6f54f 100644
--- a/arch/arm/mach-ks8695/board-acs5k.c
+++ b/arch/arm/mach-ks8695/board-acs5k.c
@@ -223,8 +223,6 @@ static void __init acs5k_init(void)
223 223
224MACHINE_START(ACS5K, "Brivo Systems LLC ACS-5000 Master board") 224MACHINE_START(ACS5K, "Brivo Systems LLC ACS-5000 Master board")
225 /* Maintainer: Simtec Electronics. */ 225 /* Maintainer: Simtec Electronics. */
226 .phys_io = KS8695_IO_PA,
227 .io_pg_offst = (KS8695_IO_VA >> 18) & 0xfffc,
228 .boot_params = KS8695_SDRAM_PA + 0x100, 226 .boot_params = KS8695_SDRAM_PA + 0x100,
229 .map_io = ks8695_map_io, 227 .map_io = ks8695_map_io,
230 .init_irq = ks8695_init_irq, 228 .init_irq = ks8695_init_irq,
diff --git a/arch/arm/mach-ks8695/board-dsm320.c b/arch/arm/mach-ks8695/board-dsm320.c
index 521ff0789f39..ada92b6bed24 100644
--- a/arch/arm/mach-ks8695/board-dsm320.c
+++ b/arch/arm/mach-ks8695/board-dsm320.c
@@ -121,8 +121,6 @@ static void __init dsm320_init(void)
121 121
122MACHINE_START(DSM320, "D-Link DSM-320 Wireless Media Player") 122MACHINE_START(DSM320, "D-Link DSM-320 Wireless Media Player")
123 /* Maintainer: Simtec Electronics. */ 123 /* Maintainer: Simtec Electronics. */
124 .phys_io = KS8695_IO_PA,
125 .io_pg_offst = (KS8695_IO_VA >> 18) & 0xfffc,
126 .boot_params = KS8695_SDRAM_PA + 0x100, 124 .boot_params = KS8695_SDRAM_PA + 0x100,
127 .map_io = ks8695_map_io, 125 .map_io = ks8695_map_io,
128 .init_irq = ks8695_init_irq, 126 .init_irq = ks8695_init_irq,
diff --git a/arch/arm/mach-ks8695/board-micrel.c b/arch/arm/mach-ks8695/board-micrel.c
index 8ceaf5ac6e2c..c7ad09bd6ea2 100644
--- a/arch/arm/mach-ks8695/board-micrel.c
+++ b/arch/arm/mach-ks8695/board-micrel.c
@@ -53,8 +53,6 @@ static void __init micrel_init(void)
53 53
54MACHINE_START(KS8695, "KS8695 Centaur Development Board") 54MACHINE_START(KS8695, "KS8695 Centaur Development Board")
55 /* Maintainer: Micrel Semiconductor Inc. */ 55 /* Maintainer: Micrel Semiconductor Inc. */
56 .phys_io = KS8695_IO_PA,
57 .io_pg_offst = (KS8695_IO_VA >> 18) & 0xfffc,
58 .boot_params = KS8695_SDRAM_PA + 0x100, 56 .boot_params = KS8695_SDRAM_PA + 0x100,
59 .map_io = ks8695_map_io, 57 .map_io = ks8695_map_io,
60 .init_irq = ks8695_init_irq, 58 .init_irq = ks8695_init_irq,
diff --git a/arch/arm/mach-ks8695/include/mach/debug-macro.S b/arch/arm/mach-ks8695/include/mach/debug-macro.S
index cf2095da2372..bf516adf1925 100644
--- a/arch/arm/mach-ks8695/include/mach/debug-macro.S
+++ b/arch/arm/mach-ks8695/include/mach/debug-macro.S
@@ -14,11 +14,9 @@
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <mach/regs-uart.h> 15#include <mach/regs-uart.h>
16 16
17 .macro addruart, rx, tmp 17 .macro addruart, rp, rv
18 mrc p15, 0, \rx, c1, c0 18 ldr \rp, =KS8695_UART_PA @ physical base address
19 tst \rx, #1 @ MMU enabled? 19 ldr \rv, =KS8695_UART_VA @ virtual base address
20 ldreq \rx, =KS8695_UART_PA @ physical base address
21 ldrne \rx, =KS8695_UART_VA @ virtual base address
22 .endm 20 .endm
23 21
24 .macro senduart, rd, rx 22 .macro senduart, rd, rx
diff --git a/arch/arm/mach-l7200/include/mach/debug-macro.S b/arch/arm/mach-l7200/include/mach/debug-macro.S
new file mode 100644
index 000000000000..b0a2db77d392
--- /dev/null
+++ b/arch/arm/mach-l7200/include/mach/debug-macro.S
@@ -0,0 +1,38 @@
1/* arch/arm/mach-l7200/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .equ io_virt, IO_BASE
15 .equ io_phys, IO_START
16
17 .macro addruart, rp, rv
18 mov \rp, #0x00044000 @ UART1
19@ mov \rp, #0x00045000 @ UART2
20 add \rv, \rp, #io_virt @ virtual address
21 add \rp, \rp, #io_phys @ physical base address
22 .endm
23
24 .macro senduart,rd,rx
25 str \rd, [\rx, #0x0] @ UARTDR
26 .endm
27
28 .macro waituart,rd,rx
291001: ldr \rd, [\rx, #0x18] @ UARTFLG
30 tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
31 bne 1001b
32 .endm
33
34 .macro busyuart,rd,rx
351001: ldr \rd, [\rx, #0x18] @ UARTFLG
36 tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
37 bne 1001b
38 .endm
diff --git a/arch/arm/mach-lh7a40x/arch-kev7a400.c b/arch/arm/mach-lh7a40x/arch-kev7a400.c
index 3d7bd50b9095..9088c16662e8 100644
--- a/arch/arm/mach-lh7a40x/arch-kev7a400.c
+++ b/arch/arm/mach-lh7a40x/arch-kev7a400.c
@@ -111,8 +111,6 @@ void __init lh7a40x_init_board_irq (void)
111 111
112MACHINE_START (KEV7A400, "Sharp KEV7a400") 112MACHINE_START (KEV7A400, "Sharp KEV7a400")
113 /* Maintainer: Marc Singer */ 113 /* Maintainer: Marc Singer */
114 .phys_io = 0x80000000,
115 .io_pg_offst = ((io_p2v (0x80000000))>>18) & 0xfffc,
116 .boot_params = 0xc0000100, 114 .boot_params = 0xc0000100,
117 .map_io = kev7a400_map_io, 115 .map_io = kev7a400_map_io,
118 .init_irq = lh7a400_init_irq, 116 .init_irq = lh7a400_init_irq,
diff --git a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
index cb15e5d32120..7315a569aea1 100644
--- a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
+++ b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
@@ -398,8 +398,6 @@ lpd7a40x_map_io(void)
398 398
399MACHINE_START (LPD7A400, "Logic Product Development LPD7A400-10") 399MACHINE_START (LPD7A400, "Logic Product Development LPD7A400-10")
400 /* Maintainer: Marc Singer */ 400 /* Maintainer: Marc Singer */
401 .phys_io = 0x80000000,
402 .io_pg_offst = ((io_p2v (0x80000000))>>18) & 0xfffc,
403 .boot_params = 0xc0000100, 401 .boot_params = 0xc0000100,
404 .map_io = lpd7a40x_map_io, 402 .map_io = lpd7a40x_map_io,
405 .init_irq = lh7a400_init_irq, 403 .init_irq = lh7a400_init_irq,
@@ -413,8 +411,6 @@ MACHINE_END
413 411
414MACHINE_START (LPD7A404, "Logic Product Development LPD7A404-10") 412MACHINE_START (LPD7A404, "Logic Product Development LPD7A404-10")
415 /* Maintainer: Marc Singer */ 413 /* Maintainer: Marc Singer */
416 .phys_io = 0x80000000,
417 .io_pg_offst = ((io_p2v (0x80000000))>>18) & 0xfffc,
418 .boot_params = 0xc0000100, 414 .boot_params = 0xc0000100,
419 .map_io = lpd7a40x_map_io, 415 .map_io = lpd7a40x_map_io,
420 .init_irq = lh7a404_init_irq, 416 .init_irq = lh7a404_init_irq,
diff --git a/arch/arm/mach-lh7a40x/include/mach/debug-macro.S b/arch/arm/mach-lh7a40x/include/mach/debug-macro.S
index c0dcbbba22ba..cff33625276f 100644
--- a/arch/arm/mach-lh7a40x/include/mach/debug-macro.S
+++ b/arch/arm/mach-lh7a40x/include/mach/debug-macro.S
@@ -14,12 +14,10 @@
14 @ It is not known if this will be appropriate for every 40x 14 @ It is not known if this will be appropriate for every 40x
15 @ board. 15 @ board.
16 16
17 .macro addruart, rx, tmp 17 .macro addruart, rp, rv
18 mrc p15, 0, \rx, c1, c0 18 mov \rp, #0x00000700 @ offset from base
19 tst \rx, #1 @ MMU enabled? 19 orr \rv, \rp, #0xf8000000 @ virtual base
20 mov \rx, #0x00000700 @ offset from base 20 orr \rp, \rp, #0x80000000 @ physical base
21 orreq \rx, \rx, #0x80000000 @ physical base
22 orrne \rx, \rx, #0xf8000000 @ virtual base
23 .endm 21 .endm
24 22
25 .macro senduart,rd,rx 23 .macro senduart,rd,rx
diff --git a/arch/arm/mach-loki/include/mach/debug-macro.S b/arch/arm/mach-loki/include/mach/debug-macro.S
index 3136c913a92c..cc90d99ac76c 100644
--- a/arch/arm/mach-loki/include/mach/debug-macro.S
+++ b/arch/arm/mach-loki/include/mach/debug-macro.S
@@ -8,12 +8,11 @@
8 8
9#include <mach/loki.h> 9#include <mach/loki.h>
10 10
11 .macro addruart, rx, tmp 11 .macro addruart, rp, rv
12 mrc p15, 0, \rx, c1, c0 12 ldr \rp, =LOKI_REGS_PHYS_BASE
13 tst \rx, #1 @ MMU enabled? 13 ldr \rv, =LOKI_REGS_VIRT_BASE
14 ldreq \rx, =LOKI_REGS_PHYS_BASE 14 orr \rp, \rp, #0x00012000
15 ldrne \rx, =LOKI_REGS_VIRT_BASE 15 orr \rv, \rv, #0x00012000
16 orr \rx, \rx, #0x00012000
17 .endm 16 .endm
18 17
19#define UART_SHIFT 2 18#define UART_SHIFT 2
diff --git a/arch/arm/mach-loki/lb88rc8480-setup.c b/arch/arm/mach-loki/lb88rc8480-setup.c
index 85f9c1296aa0..a1e75e7fc500 100644
--- a/arch/arm/mach-loki/lb88rc8480-setup.c
+++ b/arch/arm/mach-loki/lb88rc8480-setup.c
@@ -90,8 +90,6 @@ static void __init lb88rc8480_init(void)
90 90
91MACHINE_START(LB88RC8480, "Marvell LB88RC8480 Development Board") 91MACHINE_START(LB88RC8480, "Marvell LB88RC8480 Development Board")
92 /* Maintainer: Ke Wei <kewei@marvell.com> */ 92 /* Maintainer: Ke Wei <kewei@marvell.com> */
93 .phys_io = LOKI_REGS_PHYS_BASE,
94 .io_pg_offst = ((LOKI_REGS_VIRT_BASE) >> 18) & 0xfffc,
95 .boot_params = 0x00000100, 93 .boot_params = 0x00000100,
96 .init_machine = lb88rc8480_init, 94 .init_machine = lb88rc8480_init,
97 .map_io = loki_map_io, 95 .map_io = loki_map_io,
diff --git a/arch/arm/mach-lpc32xx/include/mach/debug-macro.S b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
index 621744d6b152..629e744aeb9e 100644
--- a/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
@@ -20,11 +20,9 @@
20 * Debug output is hardcoded to standard UART 5 20 * Debug output is hardcoded to standard UART 5
21*/ 21*/
22 22
23 .macro addruart,rx, tmp 23 .macro addruart, rp, rv
24 mrc p15, 0, \rx, c1, c0 24 ldreq \rp, =0x40090000
25 tst \rx, #1 @ MMU enabled? 25 ldrne \rv, =0xF4090000
26 ldreq \rx, =0x40090000
27 ldrne \rx, =0xF4090000
28 .endm 26 .endm
29 27
30#define UART_SHIFT 2 28#define UART_SHIFT 2
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index 0c936cf5675a..7993b096778e 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -382,8 +382,6 @@ arch_initcall(lpc32xx_display_uid);
382 382
383MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller") 383MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller")
384 /* Maintainer: Kevin Wells, NXP Semiconductors */ 384 /* Maintainer: Kevin Wells, NXP Semiconductors */
385 .phys_io = LPC32XX_UART5_BASE,
386 .io_pg_offst = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
387 .boot_params = 0x80000100, 385 .boot_params = 0x80000100,
388 .map_io = lpc32xx_map_io, 386 .map_io = lpc32xx_map_io,
389 .init_irq = lpc32xx_init_irq, 387 .init_irq = lpc32xx_init_irq,
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 6ab843eaa35b..0711d3b620ad 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -57,6 +57,13 @@ config MACH_MARVELL_JASPER
57 PXA910-based development board. Since MMP2 is compatible to 57 PXA910-based development board. Since MMP2 is compatible to
58 ARMv6 architecture. 58 ARMv6 architecture.
59 59
60config MACH_TETON_BGA
61 bool "Marvell's PXA168 Teton BGA Development Board"
62 select CPU_PXA168
63 help
64 Say 'Y' here if you want to support the Marvell PXA168-based
65 Teton BGA Development Board.
66
60endmenu 67endmenu
61 68
62config CPU_PXA168 69config CPU_PXA168
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 8b66d06739c4..751cdbf733c8 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o
17obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o 17obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o
18obj-$(CONFIG_MACH_FLINT) += flint.o 18obj-$(CONFIG_MACH_FLINT) += flint.o
19obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o 19obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
20obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 0629394a5fb9..06b5fa853c93 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -16,6 +16,7 @@
16#include <linux/mtd/mtd.h> 16#include <linux/mtd/mtd.h>
17#include <linux/mtd/partitions.h> 17#include <linux/mtd/partitions.h>
18#include <linux/mtd/nand.h> 18#include <linux/mtd/nand.h>
19#include <linux/interrupt.h>
19 20
20#include <asm/mach-types.h> 21#include <asm/mach-types.h>
21#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
@@ -23,6 +24,9 @@
23#include <mach/mfp-pxa168.h> 24#include <mach/mfp-pxa168.h>
24#include <mach/pxa168.h> 25#include <mach/pxa168.h>
25#include <mach/gpio.h> 26#include <mach/gpio.h>
27#include <video/pxa168fb.h>
28#include <linux/input.h>
29#include <plat/pxa27x_keypad.h>
26 30
27#include "common.h" 31#include "common.h"
28 32
@@ -66,6 +70,43 @@ static unsigned long common_pin_config[] __initdata = {
66 GPIO115_I2S_BCLK, 70 GPIO115_I2S_BCLK,
67 GPIO116_I2S_RXD, 71 GPIO116_I2S_RXD,
68 GPIO117_I2S_TXD, 72 GPIO117_I2S_TXD,
73
74 /* LCD */
75 GPIO56_LCD_FCLK_RD,
76 GPIO57_LCD_LCLK_A0,
77 GPIO58_LCD_PCLK_WR,
78 GPIO59_LCD_DENA_BIAS,
79 GPIO60_LCD_DD0,
80 GPIO61_LCD_DD1,
81 GPIO62_LCD_DD2,
82 GPIO63_LCD_DD3,
83 GPIO64_LCD_DD4,
84 GPIO65_LCD_DD5,
85 GPIO66_LCD_DD6,
86 GPIO67_LCD_DD7,
87 GPIO68_LCD_DD8,
88 GPIO69_LCD_DD9,
89 GPIO70_LCD_DD10,
90 GPIO71_LCD_DD11,
91 GPIO72_LCD_DD12,
92 GPIO73_LCD_DD13,
93 GPIO74_LCD_DD14,
94 GPIO75_LCD_DD15,
95 GPIO76_LCD_DD16,
96 GPIO77_LCD_DD17,
97 GPIO78_LCD_DD18,
98 GPIO79_LCD_DD19,
99 GPIO80_LCD_DD20,
100 GPIO81_LCD_DD21,
101 GPIO82_LCD_DD22,
102 GPIO83_LCD_DD23,
103
104 /* Keypad */
105 GPIO109_KP_MKIN1,
106 GPIO110_KP_MKIN0,
107 GPIO111_KP_MKOUT7,
108 GPIO112_KP_MKOUT6,
109 GPIO121_KP_MKIN4,
69}; 110};
70 111
71static struct smc91x_platdata smc91x_info = { 112static struct smc91x_platdata smc91x_info = {
@@ -134,6 +175,51 @@ static struct i2c_board_info aspenite_i2c_info[] __initdata = {
134 { I2C_BOARD_INFO("wm8753", 0x1b), }, 175 { I2C_BOARD_INFO("wm8753", 0x1b), },
135}; 176};
136 177
178static struct fb_videomode video_modes[] = {
179 [0] = {
180 .pixclock = 30120,
181 .refresh = 60,
182 .xres = 800,
183 .yres = 480,
184 .hsync_len = 1,
185 .left_margin = 215,
186 .right_margin = 40,
187 .vsync_len = 1,
188 .upper_margin = 34,
189 .lower_margin = 10,
190 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
191 },
192};
193
194struct pxa168fb_mach_info aspenite_lcd_info = {
195 .id = "Graphic Frame",
196 .modes = video_modes,
197 .num_modes = ARRAY_SIZE(video_modes),
198 .pix_fmt = PIX_FMT_RGB565,
199 .io_pin_allocation_mode = PIN_MODE_DUMB_24,
200 .dumb_mode = DUMB_MODE_RGB888,
201 .active = 1,
202 .panel_rbswap = 0,
203 .invert_pixclock = 0,
204};
205
206static unsigned int aspenite_matrix_key_map[] = {
207 KEY(0, 6, KEY_UP), /* SW 4 */
208 KEY(0, 7, KEY_DOWN), /* SW 5 */
209 KEY(1, 6, KEY_LEFT), /* SW 6 */
210 KEY(1, 7, KEY_RIGHT), /* SW 7 */
211 KEY(4, 6, KEY_ENTER), /* SW 8 */
212 KEY(4, 7, KEY_ESC), /* SW 9 */
213};
214
215static struct pxa27x_keypad_platform_data aspenite_keypad_info __initdata = {
216 .matrix_key_rows = 5,
217 .matrix_key_cols = 8,
218 .matrix_key_map = aspenite_matrix_key_map,
219 .matrix_key_map_size = ARRAY_SIZE(aspenite_matrix_key_map),
220 .debounce_interval = 30,
221};
222
137static void __init common_init(void) 223static void __init common_init(void)
138{ 224{
139 mfp_config(ARRAY_AND_SIZE(common_pin_config)); 225 mfp_config(ARRAY_AND_SIZE(common_pin_config));
@@ -143,24 +229,24 @@ static void __init common_init(void)
143 pxa168_add_twsi(1, NULL, ARRAY_AND_SIZE(aspenite_i2c_info)); 229 pxa168_add_twsi(1, NULL, ARRAY_AND_SIZE(aspenite_i2c_info));
144 pxa168_add_ssp(1); 230 pxa168_add_ssp(1);
145 pxa168_add_nand(&aspenite_nand_info); 231 pxa168_add_nand(&aspenite_nand_info);
232 pxa168_add_fb(&aspenite_lcd_info);
233 pxa168_add_keypad(&aspenite_keypad_info);
146 234
147 /* off-chip devices */ 235 /* off-chip devices */
148 platform_device_register(&smc91x_device); 236 platform_device_register(&smc91x_device);
149} 237}
150 238
151MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform") 239MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")
152 .phys_io = APB_PHYS_BASE,
153 .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
154 .map_io = mmp_map_io, 240 .map_io = mmp_map_io,
241 .nr_irqs = IRQ_BOARD_START,
155 .init_irq = pxa168_init_irq, 242 .init_irq = pxa168_init_irq,
156 .timer = &pxa168_timer, 243 .timer = &pxa168_timer,
157 .init_machine = common_init, 244 .init_machine = common_init,
158MACHINE_END 245MACHINE_END
159 246
160MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform") 247MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform")
161 .phys_io = APB_PHYS_BASE,
162 .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
163 .map_io = mmp_map_io, 248 .map_io = mmp_map_io,
249 .nr_irqs = IRQ_BOARD_START,
164 .init_irq = pxa168_init_irq, 250 .init_irq = pxa168_init_irq,
165 .timer = &pxa168_timer, 251 .timer = &pxa168_timer,
166 .init_machine = common_init, 252 .init_machine = common_init,
diff --git a/arch/arm/mach-mmp/avengers_lite.c b/arch/arm/mach-mmp/avengers_lite.c
index 69bcba11f53f..39f0878d64a0 100644
--- a/arch/arm/mach-mmp/avengers_lite.c
+++ b/arch/arm/mach-mmp/avengers_lite.c
@@ -41,8 +41,6 @@ static void __init avengers_lite_init(void)
41} 41}
42 42
43MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform") 43MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform")
44 .phys_io = APB_PHYS_BASE,
45 .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
46 .map_io = mmp_map_io, 44 .map_io = mmp_map_io,
47 .init_irq = pxa168_init_irq, 45 .init_irq = pxa168_init_irq,
48 .timer = &pxa168_timer, 46 .timer = &pxa168_timer,
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 3b29fa7e9b08..0ec0ca80bb3e 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -10,13 +10,20 @@
10 10
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/module.h>
13 14
14#include <asm/page.h> 15#include <asm/page.h>
15#include <asm/mach/map.h> 16#include <asm/mach/map.h>
16#include <mach/addr-map.h> 17#include <mach/addr-map.h>
18#include <mach/cputype.h>
17 19
18#include "common.h" 20#include "common.h"
19 21
22#define MMP_CHIPID (AXI_VIRT_BASE + 0x82c00)
23
24unsigned int mmp_chip_id;
25EXPORT_SYMBOL(mmp_chip_id);
26
20static struct map_desc standard_io_desc[] __initdata = { 27static struct map_desc standard_io_desc[] __initdata = {
21 { 28 {
22 .pfn = __phys_to_pfn(APB_PHYS_BASE), 29 .pfn = __phys_to_pfn(APB_PHYS_BASE),
@@ -34,4 +41,7 @@ static struct map_desc standard_io_desc[] __initdata = {
34void __init mmp_map_io(void) 41void __init mmp_map_io(void)
35{ 42{
36 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); 43 iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
44
45 /* this is early, initialize mmp_chip_id here */
46 mmp_chip_id = __raw_readl(MMP_CHIPID);
37} 47}
diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c
index e4312d238eae..bdeb6db4d49a 100644
--- a/arch/arm/mach-mmp/flint.c
+++ b/arch/arm/mach-mmp/flint.c
@@ -16,6 +16,7 @@
16#include <linux/smc91x.h> 16#include <linux/smc91x.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/gpio.h> 18#include <linux/gpio.h>
19#include <linux/interrupt.h>
19 20
20#include <asm/mach-types.h> 21#include <asm/mach-types.h>
21#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
@@ -25,6 +26,8 @@
25 26
26#include "common.h" 27#include "common.h"
27 28
29#define FLINT_NR_IRQS (IRQ_BOARD_START + 48)
30
28static unsigned long flint_pin_config[] __initdata = { 31static unsigned long flint_pin_config[] __initdata = {
29 /* UART1 */ 32 /* UART1 */
30 GPIO45_UART1_RXD, 33 GPIO45_UART1_RXD,
@@ -113,9 +116,8 @@ static void __init flint_init(void)
113} 116}
114 117
115MACHINE_START(FLINT, "Flint Development Platform") 118MACHINE_START(FLINT, "Flint Development Platform")
116 .phys_io = APB_PHYS_BASE,
117 .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
118 .map_io = mmp_map_io, 119 .map_io = mmp_map_io,
120 .nr_irqs = FLINT_NR_IRQS,
119 .init_irq = mmp2_init_irq, 121 .init_irq = mmp2_init_irq,
120 .timer = &mmp2_timer, 122 .timer = &mmp2_timer,
121 .init_machine = flint_init, 123 .init_machine = flint_init,
diff --git a/arch/arm/mach-mmp/include/mach/cputype.h b/arch/arm/mach-mmp/include/mach/cputype.h
index 83b18721d933..f43a68b213f1 100644
--- a/arch/arm/mach-mmp/include/mach/cputype.h
+++ b/arch/arm/mach-mmp/include/mach/cputype.h
@@ -4,36 +4,51 @@
4#include <asm/cputype.h> 4#include <asm/cputype.h>
5 5
6/* 6/*
7 * CPU Stepping OLD_ID CPU_ID CHIP_ID 7 * CPU Stepping CPU_ID CHIP_ID
8 * 8 *
9 * PXA168 A0 0x41159263 0x56158400 0x00A0A333 9 * PXA168 S0 0x56158400 0x0000C910
10 * PXA910 Y0 0x41159262 0x56158000 0x00F0C910 10 * PXA168 A0 0x56158400 0x00A0A168
11 * MMP2 Z0 0x560f5811 11 * PXA910 Y1 0x56158400 0x00F2C920
12 * PXA910 A0 0x56158400 0x00F2C910
13 * PXA910 A1 0x56158400 0x00A0C910
14 * PXA920 Y0 0x56158400 0x00F2C920
15 * PXA920 A0 0x56158400 0x00A0C920
16 * PXA920 A1 0x56158400 0x00A1C920
17 * MMP2 Z0 0x560f5811 0x00F00410
18 * MMP2 Z1 0x560f5811 0x00E00410
19 * MMP2 A0 0x560f5811 0x00A0A610
12 */ 20 */
13 21
22extern unsigned int mmp_chip_id;
23
14#ifdef CONFIG_CPU_PXA168 24#ifdef CONFIG_CPU_PXA168
15# define __cpu_is_pxa168(id) \ 25static inline int cpu_is_pxa168(void)
16 ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x84; }) 26{
27 return (((read_cpuid_id() >> 8) & 0xff) == 0x84) &&
28 ((mmp_chip_id & 0xfff) == 0x168);
29}
17#else 30#else
18# define __cpu_is_pxa168(id) (0) 31#define cpu_is_pxa168() (0)
19#endif 32#endif
20 33
34/* cpu_is_pxa910() is shared on both pxa910 and pxa920 */
21#ifdef CONFIG_CPU_PXA910 35#ifdef CONFIG_CPU_PXA910
22# define __cpu_is_pxa910(id) \ 36static inline int cpu_is_pxa910(void)
23 ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x80; }) 37{
38 return (((read_cpuid_id() >> 8) & 0xff) == 0x84) &&
39 (((mmp_chip_id & 0xfff) == 0x910) ||
40 ((mmp_chip_id & 0xfff) == 0x920));
41}
24#else 42#else
25# define __cpu_is_pxa910(id) (0) 43#define cpu_is_pxa910() (0)
26#endif 44#endif
27 45
28#ifdef CONFIG_CPU_MMP2 46#ifdef CONFIG_CPU_MMP2
29# define __cpu_is_mmp2(id) \ 47static inline int cpu_is_mmp2(void)
30 ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x58; }) 48{
49 return (((cpu_readid_id() >> 8) & 0xff) == 0x58);
31#else 50#else
32# define __cpu_is_mmp2(id) (0) 51#define cpu_is_mmp2() (0)
33#endif 52#endif
34 53
35#define cpu_is_pxa168() ({ __cpu_is_pxa168(read_cpuid_id()); })
36#define cpu_is_pxa910() ({ __cpu_is_pxa910(read_cpuid_id()); })
37#define cpu_is_mmp2() ({ __cpu_is_mmp2(read_cpuid_id()); })
38
39#endif /* __ASM_MACH_CPUTYPE_H */ 54#endif /* __ASM_MACH_CPUTYPE_H */
diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S
index 76deff238e1c..7e2ebd3efc7c 100644
--- a/arch/arm/mach-mmp/include/mach/debug-macro.S
+++ b/arch/arm/mach-mmp/include/mach/debug-macro.S
@@ -11,12 +11,11 @@
11 11
12#include <mach/addr-map.h> 12#include <mach/addr-map.h>
13 13
14 .macro addruart, rx, tmp 14 .macro addruart, rp, rv
15 mrc p15, 0, \rx, c1, c0 15 ldr \rp, =APB_PHYS_BASE @ physical
16 tst \rx, #1 @ MMU enabled? 16 ldr \rv, =APB_VIRT_BASE @ virtual
17 ldreq \rx, =APB_PHYS_BASE @ physical 17 orr \rp, \rp, #0x00017000
18 ldrne \rx, =APB_VIRT_BASE @ virtual 18 orr \rv, \rv, #0x00017000
19 orr \rx, \rx, #0x00017000
20 .endm 19 .endm
21 20
22#define UART_SHIFT 2 21#define UART_SHIFT 2
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h
index b379cdec4d38..a09d328e2ddd 100644
--- a/arch/arm/mach-mmp/include/mach/irqs.h
+++ b/arch/arm/mach-mmp/include/mach/irqs.h
@@ -222,10 +222,8 @@
222#define IRQ_GPIO_NUM 192 222#define IRQ_GPIO_NUM 192
223#define IRQ_GPIO(x) (IRQ_GPIO_START + (x)) 223#define IRQ_GPIO(x) (IRQ_GPIO_START + (x))
224 224
225/* Board IRQ - 64 by default, increase if not enough */
226#define IRQ_BOARD_START (IRQ_GPIO_START + IRQ_GPIO_NUM) 225#define IRQ_BOARD_START (IRQ_GPIO_START + IRQ_GPIO_NUM)
227#define IRQ_BOARD_END (IRQ_BOARD_START + 64)
228 226
229#define NR_IRQS (IRQ_BOARD_END) 227#define NR_IRQS (IRQ_BOARD_START)
230 228
231#endif /* __ASM_MACH_IRQS_H */ 229#endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
index ded43c455ec3..4621067c7720 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
@@ -289,4 +289,11 @@
289#define GPIO86_PWM1_OUT MFP_CFG(GPIO86, AF2) 289#define GPIO86_PWM1_OUT MFP_CFG(GPIO86, AF2)
290#define GPIO86_PWM2_OUT MFP_CFG(GPIO86, AF3) 290#define GPIO86_PWM2_OUT MFP_CFG(GPIO86, AF3)
291 291
292/* Keypad */
293#define GPIO109_KP_MKIN1 MFP_CFG(GPIO109, AF7)
294#define GPIO110_KP_MKIN0 MFP_CFG(GPIO110, AF7)
295#define GPIO111_KP_MKOUT7 MFP_CFG(GPIO111, AF7)
296#define GPIO112_KP_MKOUT6 MFP_CFG(GPIO112, AF7)
297#define GPIO121_KP_MKIN4 MFP_CFG(GPIO121, AF7)
298
292#endif /* __ASM_MACH_MFP_PXA168_H */ 299#endif /* __ASM_MACH_MFP_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 27e1bc758623..1801e4206232 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -5,11 +5,15 @@ struct sys_timer;
5 5
6extern struct sys_timer pxa168_timer; 6extern struct sys_timer pxa168_timer;
7extern void __init pxa168_init_irq(void); 7extern void __init pxa168_init_irq(void);
8extern void pxa168_clear_keypad_wakeup(void);
8 9
9#include <linux/i2c.h> 10#include <linux/i2c.h>
10#include <mach/devices.h> 11#include <mach/devices.h>
11#include <plat/i2c.h> 12#include <plat/i2c.h>
12#include <plat/pxa3xx_nand.h> 13#include <plat/pxa3xx_nand.h>
14#include <video/pxa168fb.h>
15#include <plat/pxa27x_keypad.h>
16#include <mach/cputype.h>
13 17
14extern struct pxa_device_desc pxa168_device_uart1; 18extern struct pxa_device_desc pxa168_device_uart1;
15extern struct pxa_device_desc pxa168_device_uart2; 19extern struct pxa_device_desc pxa168_device_uart2;
@@ -25,6 +29,8 @@ extern struct pxa_device_desc pxa168_device_ssp3;
25extern struct pxa_device_desc pxa168_device_ssp4; 29extern struct pxa_device_desc pxa168_device_ssp4;
26extern struct pxa_device_desc pxa168_device_ssp5; 30extern struct pxa_device_desc pxa168_device_ssp5;
27extern struct pxa_device_desc pxa168_device_nand; 31extern struct pxa_device_desc pxa168_device_nand;
32extern struct pxa_device_desc pxa168_device_fb;
33extern struct pxa_device_desc pxa168_device_keypad;
28 34
29static inline int pxa168_add_uart(int id) 35static inline int pxa168_add_uart(int id)
30{ 36{
@@ -97,4 +103,18 @@ static inline int pxa168_add_nand(struct pxa3xx_nand_platform_data *info)
97{ 103{
98 return pxa_register_device(&pxa168_device_nand, info, sizeof(*info)); 104 return pxa_register_device(&pxa168_device_nand, info, sizeof(*info));
99} 105}
106
107static inline int pxa168_add_fb(struct pxa168fb_mach_info *mi)
108{
109 return pxa_register_device(&pxa168_device_fb, mi, sizeof(*mi));
110}
111
112static inline int pxa168_add_keypad(struct pxa27x_keypad_platform_data *data)
113{
114 if (cpu_is_pxa168())
115 data->clear_wakeup_event = pxa168_clear_keypad_wakeup;
116
117 return pxa_register_device(&pxa168_device_keypad, data, sizeof(*data));
118}
119
100#endif /* __ASM_MACH_PXA168_H */ 120#endif /* __ASM_MACH_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index 919030514120..ac4702357a6e 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -33,4 +33,16 @@
33#define APMU_FNRST_DIS (1 << 1) 33#define APMU_FNRST_DIS (1 << 1)
34#define APMU_AXIRST_DIS (1 << 0) 34#define APMU_AXIRST_DIS (1 << 0)
35 35
36/* Wake Clear Register */
37#define APMU_WAKE_CLR APMU_REG(0x07c)
38
39#define APMU_PXA168_KP_WAKE_CLR (1 << 7)
40#define APMU_PXA168_CFI_WAKE_CLR (1 << 6)
41#define APMU_PXA168_XD_WAKE_CLR (1 << 5)
42#define APMU_PXA168_MSP_WAKE_CLR (1 << 4)
43#define APMU_PXA168_SD4_WAKE_CLR (1 << 3)
44#define APMU_PXA168_SD3_WAKE_CLR (1 << 2)
45#define APMU_PXA168_SD2_WAKE_CLR (1 << 1)
46#define APMU_PXA168_SD1_WAKE_CLR (1 << 0)
47
36#endif /* __ASM_MACH_REGS_APMU_H */ 48#endif /* __ASM_MACH_REGS_APMU_H */
diff --git a/arch/arm/mach-mmp/include/mach/teton_bga.h b/arch/arm/mach-mmp/include/mach/teton_bga.h
new file mode 100644
index 000000000000..61a539b2cc98
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/teton_bga.h
@@ -0,0 +1,27 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/teton_bga.h
3 *
4 * Support for the Marvell PXA168 Teton BGA Development Platform.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * publishhed by the Free Software Foundation.
9 */
10#ifndef __ASM_MACH_TETON_BGA_H
11#define __ASM_MACH_TETON_BGA_H
12
13/* GPIOs */
14#define MMC_PWENA_GPIO 27
15#define USBHPENB_GPIO 55
16#define RTC_INT_GPIO 78
17#define LCD_VBLK_EN_GPIO 79
18#define LCD_DVDD_EN_GPIO 80
19#define RST_WIFI_GPIO 81
20#define CF_PWEN_GPIO 82
21#define USB_OC_GPIO 83
22#define PWM_GPIO 84
23#define USBHPENA_GPIO 85
24#define TS_INT_GPIO 86
25#define CIR_GPIO 108
26
27#endif /* __ASM_MACH_TETON_BGA_H */
diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c
index 80c3e7ab1e17..2a684fa50773 100644
--- a/arch/arm/mach-mmp/jasper.c
+++ b/arch/arm/mach-mmp/jasper.c
@@ -18,16 +18,18 @@
18#include <linux/regulator/machine.h> 18#include <linux/regulator/machine.h>
19#include <linux/regulator/max8649.h> 19#include <linux/regulator/max8649.h>
20#include <linux/mfd/max8925.h> 20#include <linux/mfd/max8925.h>
21#include <linux/interrupt.h>
21 22
22#include <asm/mach-types.h> 23#include <asm/mach-types.h>
23#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
24#include <mach/addr-map.h> 25#include <mach/addr-map.h>
25#include <mach/mfp-mmp2.h> 26#include <mach/mfp-mmp2.h>
26#include <mach/mmp2.h> 27#include <mach/mmp2.h>
27#include <mach/irqs.h>
28 28
29#include "common.h" 29#include "common.h"
30 30
31#define JASPER_NR_IRQS (IRQ_BOARD_START + 48)
32
31static unsigned long jasper_pin_config[] __initdata = { 33static unsigned long jasper_pin_config[] __initdata = {
32 /* UART1 */ 34 /* UART1 */
33 GPIO29_UART1_RXD, 35 GPIO29_UART1_RXD,
@@ -134,9 +136,8 @@ static void __init jasper_init(void)
134} 136}
135 137
136MACHINE_START(MARVELL_JASPER, "Jasper Development Platform") 138MACHINE_START(MARVELL_JASPER, "Jasper Development Platform")
137 .phys_io = APB_PHYS_BASE,
138 .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
139 .map_io = mmp_map_io, 139 .map_io = mmp_map_io,
140 .nr_irqs = JASPER_NR_IRQS,
140 .init_irq = mmp2_init_irq, 141 .init_irq = mmp2_init_irq,
141 .timer = &mmp2_timer, 142 .timer = &mmp2_timer,
142 .init_machine = jasper_init, 143 .init_machine = jasper_init,
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 652ae660634c..72b4e7631583 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -77,8 +77,10 @@ static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
77static APBC_CLK(ssp3, PXA168_SSP3, 4, 0); 77static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
78static APBC_CLK(ssp4, PXA168_SSP4, 4, 0); 78static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
79static APBC_CLK(ssp5, PXA168_SSP5, 4, 0); 79static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
80static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
80 81
81static APMU_CLK(nand, NAND, 0x01db, 208000000); 82static APMU_CLK(nand, NAND, 0x01db, 208000000);
83static APMU_CLK(lcd, LCD, 0x7f, 312000000);
82 84
83/* device and clock bindings */ 85/* device and clock bindings */
84static struct clk_lookup pxa168_clkregs[] = { 86static struct clk_lookup pxa168_clkregs[] = {
@@ -96,6 +98,8 @@ static struct clk_lookup pxa168_clkregs[] = {
96 INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL), 98 INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
97 INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL), 99 INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
98 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL), 100 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
101 INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
102 INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
99}; 103};
100 104
101static int __init pxa168_init(void) 105static int __init pxa168_init(void)
@@ -132,6 +136,16 @@ struct sys_timer pxa168_timer = {
132 .init = pxa168_timer_init, 136 .init = pxa168_timer_init,
133}; 137};
134 138
139void pxa168_clear_keypad_wakeup(void)
140{
141 uint32_t val;
142 uint32_t mask = APMU_PXA168_KP_WAKE_CLR;
143
144 /* wake event clear is needed in order to clear keypad interrupt */
145 val = __raw_readl(APMU_WAKE_CLR);
146 __raw_writel(val | mask, APMU_WAKE_CLR);
147}
148
135/* on-chip devices */ 149/* on-chip devices */
136PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22); 150PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22);
137PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24); 151PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24);
@@ -147,3 +161,5 @@ PXA168_DEVICE(ssp2, "pxa168-ssp", 1, SSP2, 0xd401c000, 0x40, 54, 55);
147PXA168_DEVICE(ssp3, "pxa168-ssp", 2, SSP3, 0xd401f000, 0x40, 56, 57); 161PXA168_DEVICE(ssp3, "pxa168-ssp", 2, SSP3, 0xd401f000, 0x40, 56, 57);
148PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59); 162PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59);
149PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61); 163PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61);
164PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8);
165PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c);
diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c
index e81db7428215..c296b75c4453 100644
--- a/arch/arm/mach-mmp/tavorevb.c
+++ b/arch/arm/mach-mmp/tavorevb.c
@@ -99,8 +99,6 @@ static void __init tavorevb_init(void)
99} 99}
100 100
101MACHINE_START(TAVOREVB, "PXA910 Evaluation Board (aka TavorEVB)") 101MACHINE_START(TAVOREVB, "PXA910 Evaluation Board (aka TavorEVB)")
102 .phys_io = APB_PHYS_BASE,
103 .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
104 .map_io = mmp_map_io, 102 .map_io = mmp_map_io,
105 .init_irq = pxa910_init_irq, 103 .init_irq = pxa910_init_irq,
106 .timer = &pxa910_timer, 104 .timer = &pxa910_timer,
diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c
new file mode 100644
index 000000000000..bbe4727b96cc
--- /dev/null
+++ b/arch/arm/mach-mmp/teton_bga.c
@@ -0,0 +1,89 @@
1/*
2 * linux/arch/arm/mach-mmp/teton_bga.c
3 *
4 * Support for the Marvell PXA168 Teton BGA Development Platform.
5 *
6 * Author: Mark F. Brown <mark.brown314@gmail.com>
7 *
8 * This code is based on aspenite.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * publishhed by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/kernel.h>
17#include <linux/platform_device.h>
18#include <linux/gpio.h>
19#include <linux/input.h>
20#include <plat/pxa27x_keypad.h>
21#include <linux/i2c.h>
22
23#include <asm/mach-types.h>
24#include <asm/mach/arch.h>
25#include <mach/addr-map.h>
26#include <mach/mfp-pxa168.h>
27#include <mach/pxa168.h>
28#include <mach/teton_bga.h>
29
30#include "common.h"
31
32static unsigned long teton_bga_pin_config[] __initdata = {
33 /* UART1 */
34 GPIO107_UART1_TXD,
35 GPIO108_UART1_RXD,
36
37 /* Keypad */
38 GPIO109_KP_MKIN1,
39 GPIO110_KP_MKIN0,
40 GPIO111_KP_MKOUT7,
41 GPIO112_KP_MKOUT6,
42
43 /* I2C Bus */
44 GPIO105_CI2C_SDA,
45 GPIO106_CI2C_SCL,
46
47 /* RTC */
48 GPIO78_GPIO,
49};
50
51static unsigned int teton_bga_matrix_key_map[] = {
52 KEY(0, 6, KEY_ESC),
53 KEY(0, 7, KEY_ENTER),
54 KEY(1, 6, KEY_LEFT),
55 KEY(1, 7, KEY_RIGHT),
56};
57
58static struct pxa27x_keypad_platform_data teton_bga_keypad_info __initdata = {
59 .matrix_key_rows = 2,
60 .matrix_key_cols = 8,
61 .matrix_key_map = teton_bga_matrix_key_map,
62 .matrix_key_map_size = ARRAY_SIZE(teton_bga_matrix_key_map),
63 .debounce_interval = 30,
64};
65
66static struct i2c_board_info teton_bga_i2c_info[] __initdata = {
67 {
68 I2C_BOARD_INFO("ds1337", 0x68),
69 .irq = gpio_to_irq(RTC_INT_GPIO)
70 },
71};
72
73static void __init teton_bga_init(void)
74{
75 mfp_config(ARRAY_AND_SIZE(teton_bga_pin_config));
76
77 /* on-chip devices */
78 pxa168_add_uart(1);
79 pxa168_add_keypad(&teton_bga_keypad_info);
80 pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(teton_bga_i2c_info));
81}
82
83MACHINE_START(TETON_BGA, "PXA168-based Teton BGA Development Platform")
84 .map_io = mmp_map_io,
85 .nr_irqs = IRQ_BOARD_START,
86 .init_irq = pxa168_init_irq,
87 .timer = &pxa168_timer,
88 .init_machine = teton_bga_init,
89MACHINE_END
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index ee65e05f0cf1..e411039ea59e 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -14,6 +14,7 @@
14#include <linux/mtd/mtd.h> 14#include <linux/mtd/mtd.h>
15#include <linux/mtd/partitions.h> 15#include <linux/mtd/partitions.h>
16#include <linux/mtd/onenand.h> 16#include <linux/mtd/onenand.h>
17#include <linux/interrupt.h>
17 18
18#include <asm/mach-types.h> 19#include <asm/mach-types.h>
19#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
@@ -24,6 +25,8 @@
24 25
25#include "common.h" 26#include "common.h"
26 27
28#define TTCDKB_NR_IRQS (IRQ_BOARD_START + 24)
29
27static unsigned long ttc_dkb_pin_config[] __initdata = { 30static unsigned long ttc_dkb_pin_config[] __initdata = {
28 /* UART2 */ 31 /* UART2 */
29 GPIO47_UART2_RXD, 32 GPIO47_UART2_RXD,
@@ -122,9 +125,8 @@ static void __init ttc_dkb_init(void)
122} 125}
123 126
124MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform") 127MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform")
125 .phys_io = APB_PHYS_BASE,
126 .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
127 .map_io = mmp_map_io, 128 .map_io = mmp_map_io,
129 .nr_irqs = TTCDKB_NR_IRQS,
128 .init_irq = pxa910_init_irq, 130 .init_irq = pxa910_init_irq,
129 .timer = &pxa910_timer, 131 .timer = &pxa910_timer,
130 .init_machine = ttc_dkb_init, 132 .init_machine = ttc_dkb_init,
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 47264a76eeb3..3115a29dec4e 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -10,6 +10,8 @@ config ARCH_MSM7X00A
10 select MSM_SMD 10 select MSM_SMD
11 select MSM_SMD_PKG3 11 select MSM_SMD_PKG3
12 select CPU_V6 12 select CPU_V6
13 select MSM_PROC_COMM
14 select HAS_MSM_DEBUG_UART_PHYS
13 15
14config ARCH_MSM7X30 16config ARCH_MSM7X30
15 bool "MSM7x30" 17 bool "MSM7x30"
@@ -18,6 +20,9 @@ config ARCH_MSM7X30
18 select MSM_VIC 20 select MSM_VIC
19 select CPU_V7 21 select CPU_V7
20 select MSM_REMOTE_SPINLOCK_DEKKERS 22 select MSM_REMOTE_SPINLOCK_DEKKERS
23 select MSM_GPIOMUX
24 select MSM_PROC_COMM
25 select HAS_MSM_DEBUG_UART_PHYS
21 26
22config ARCH_QSD8X50 27config ARCH_QSD8X50
23 bool "QSD8X50" 28 bool "QSD8X50"
@@ -26,6 +31,19 @@ config ARCH_QSD8X50
26 select MSM_VIC 31 select MSM_VIC
27 select CPU_V7 32 select CPU_V7
28 select MSM_REMOTE_SPINLOCK_LDREX 33 select MSM_REMOTE_SPINLOCK_LDREX
34 select MSM_GPIOMUX
35 select MSM_PROC_COMM
36 select HAS_MSM_DEBUG_UART_PHYS
37
38config ARCH_MSM8X60
39 bool "MSM8X60"
40 select ARM_GIC
41 select CPU_V7
42 select MSM_V2_TLMM
43 select MSM_GPIOMUX
44 select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \
45 && !MACH_MSM8X60_FFA)
46
29endchoice 47endchoice
30 48
31config MSM_SOC_REV_A 49config MSM_SOC_REV_A
@@ -36,6 +54,9 @@ config ARCH_MSM_ARM11
36config ARCH_MSM_SCORPION 54config ARCH_MSM_SCORPION
37 bool 55 bool
38 56
57config HAS_MSM_DEBUG_UART_PHYS
58 bool
59
39config MSM_VIC 60config MSM_VIC
40 bool 61 bool
41 62
@@ -74,6 +95,30 @@ config MACH_QSD8X50A_ST1_5
74 help 95 help
75 Support for the Qualcomm ST1.5. 96 Support for the Qualcomm ST1.5.
76 97
98config MACH_MSM8X60_RUMI3
99 depends on ARCH_MSM8X60
100 bool "MSM8x60 RUMI3"
101 help
102 Support for the Qualcomm MSM8x60 RUMI3 emulator.
103
104config MACH_MSM8X60_SURF
105 depends on ARCH_MSM8X60
106 bool "MSM8x60 SURF"
107 help
108 Support for the Qualcomm MSM8x60 SURF eval board.
109
110config MACH_MSM8X60_SIM
111 depends on ARCH_MSM8X60
112 bool "MSM8x60 Simulator"
113 help
114 Support for the Qualcomm MSM8x60 simulator.
115
116config MACH_MSM8X60_FFA
117 depends on ARCH_MSM8X60
118 bool "MSM8x60 FFA"
119 help
120 Support for the Qualcomm MSM8x60 FFA eval board.
121
77endmenu 122endmenu
78 123
79config MSM_DEBUG_UART 124config MSM_DEBUG_UART
@@ -82,6 +127,7 @@ config MSM_DEBUG_UART
82 default 2 if MSM_DEBUG_UART2 127 default 2 if MSM_DEBUG_UART2
83 default 3 if MSM_DEBUG_UART3 128 default 3 if MSM_DEBUG_UART3
84 129
130if HAS_MSM_DEBUG_UART_PHYS
85choice 131choice
86 prompt "Debug UART" 132 prompt "Debug UART"
87 133
@@ -99,11 +145,20 @@ choice
99 config MSM_DEBUG_UART3 145 config MSM_DEBUG_UART3
100 bool "UART3" 146 bool "UART3"
101endchoice 147endchoice
148endif
102 149
103config MSM_SMD_PKG3 150config MSM_SMD_PKG3
104 bool 151 bool
105 152
153config MSM_PROC_COMM
154 bool
155
106config MSM_SMD 156config MSM_SMD
107 bool 157 bool
108 158
159config MSM_GPIOMUX
160 bool
161
162config MSM_V2_TLMM
163 bool
109endif 164endif
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 704610648a25..b5a7b07a44f5 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,16 +1,20 @@
1obj-y += proc_comm.o 1obj-y += io.o idle.o timer.o
2obj-y += io.o idle.o timer.o dma.o 2ifndef CONFIG_ARCH_MSM8X60
3obj-y += vreg.o
4obj-y += acpuclock-arm11.o 3obj-y += acpuclock-arm11.o
5obj-y += clock.o clock-pcom.o 4obj-y += dma.o
6obj-y += gpio.o 5endif
7 6
8ifdef CONFIG_MSM_VIC 7ifdef CONFIG_MSM_VIC
9obj-y += irq-vic.o 8obj-y += irq-vic.o
10else 9else
10ifndef CONFIG_ARCH_MSM8X60
11obj-y += irq.o 11obj-y += irq.o
12endif 12endif
13endif
13 14
15obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o
16obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
17obj-$(CONFIG_MSM_PROC_COMM) += clock.o
14obj-$(CONFIG_ARCH_QSD8X50) += sirc.o 18obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
15obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o 19obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
16obj-$(CONFIG_MSM_SMD) += last_radio_log.o 20obj-$(CONFIG_MSM_SMD) += last_radio_log.o
@@ -19,4 +23,11 @@ obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o d
19obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o 23obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
20obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o 24obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
21obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o 25obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
26obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
22 27
28obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o
29obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
30obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
31ifndef CONFIG_MSM_V2_TLMM
32obj-y += gpio.o
33endif
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 7bd72e8f127e..59edecbe126c 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -95,8 +95,6 @@ static void __init halibut_map_io(void)
95 95
96MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)") 96MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
97#ifdef CONFIG_MSM_DEBUG_UART 97#ifdef CONFIG_MSM_DEBUG_UART
98 .phys_io = MSM_DEBUG_UART_PHYS,
99 .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
100#endif 98#endif
101 .boot_params = 0x10000100, 99 .boot_params = 0x10000100,
102 .fixup = halibut_fixup, 100 .fixup = halibut_fixup,
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
index bcbefdfe7b5e..ef3ebf2f763b 100644
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ b/arch/arm/mach-msm/board-mahimahi.c
@@ -75,8 +75,6 @@ extern struct sys_timer msm_timer;
75 75
76MACHINE_START(MAHIMAHI, "mahimahi") 76MACHINE_START(MAHIMAHI, "mahimahi")
77#ifdef CONFIG_MSM_DEBUG_UART 77#ifdef CONFIG_MSM_DEBUG_UART
78 .phys_io = MSM_DEBUG_UART_PHYS,
79 .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
80#endif 78#endif
81 .boot_params = 0x20000100, 79 .boot_params = 0x20000100,
82 .fixup = mahimahi_fixup, 80 .fixup = mahimahi_fixup,
diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c
index db9381b85bf0..e7a76eff57d9 100644
--- a/arch/arm/mach-msm/board-msm7x27.c
+++ b/arch/arm/mach-msm/board-msm7x27.c
@@ -131,8 +131,6 @@ static void __init msm7x2x_map_io(void)
131 131
132MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF") 132MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF")
133#ifdef CONFIG_MSM_DEBUG_UART 133#ifdef CONFIG_MSM_DEBUG_UART
134 .phys_io = MSM_DEBUG_UART_PHYS,
135 .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
136#endif 134#endif
137 .boot_params = PHYS_OFFSET + 0x100, 135 .boot_params = PHYS_OFFSET + 0x100,
138 .map_io = msm7x2x_map_io, 136 .map_io = msm7x2x_map_io,
@@ -143,8 +141,6 @@ MACHINE_END
143 141
144MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA") 142MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
145#ifdef CONFIG_MSM_DEBUG_UART 143#ifdef CONFIG_MSM_DEBUG_UART
146 .phys_io = MSM_DEBUG_UART_PHYS,
147 .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
148#endif 144#endif
149 .boot_params = PHYS_OFFSET + 0x100, 145 .boot_params = PHYS_OFFSET + 0x100,
150 .map_io = msm7x2x_map_io, 146 .map_io = msm7x2x_map_io,
@@ -155,8 +151,6 @@ MACHINE_END
155 151
156MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF") 152MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
157#ifdef CONFIG_MSM_DEBUG_UART 153#ifdef CONFIG_MSM_DEBUG_UART
158 .phys_io = MSM_DEBUG_UART_PHYS,
159 .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
160#endif 154#endif
161 .boot_params = PHYS_OFFSET + 0x100, 155 .boot_params = PHYS_OFFSET + 0x100,
162 .map_io = msm7x2x_map_io, 156 .map_io = msm7x2x_map_io,
@@ -167,8 +161,6 @@ MACHINE_END
167 161
168MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA") 162MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA")
169#ifdef CONFIG_MSM_DEBUG_UART 163#ifdef CONFIG_MSM_DEBUG_UART
170 .phys_io = MSM_DEBUG_UART_PHYS,
171 .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
172#endif 164#endif
173 .boot_params = PHYS_OFFSET + 0x100, 165 .boot_params = PHYS_OFFSET + 0x100,
174 .map_io = msm7x2x_map_io, 166 .map_io = msm7x2x_map_io,
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index e32981928c77..05241df3f9b6 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -39,27 +39,11 @@
39 39
40extern struct sys_timer msm_timer; 40extern struct sys_timer msm_timer;
41 41
42#ifdef CONFIG_SERIAL_MSM_CONSOLE
43static struct msm_gpio uart2_config_data[] = {
44 { GPIO_CFG(49, 2, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_RFR"},
45 { GPIO_CFG(50, 2, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_CTS"},
46 { GPIO_CFG(51, 2, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Rx"},
47 { GPIO_CFG(52, 2, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Tx"},
48};
49
50static void msm7x30_init_uart2(void)
51{
52 msm_gpios_request_enable(uart2_config_data,
53 ARRAY_SIZE(uart2_config_data));
54
55}
56#endif
57
58static struct platform_device *devices[] __initdata = { 42static struct platform_device *devices[] __initdata = {
59#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER) 43#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
60 &msm_device_uart2, 44 &msm_device_uart2,
61#endif 45#endif
62 46 &msm_device_smd,
63}; 47};
64 48
65static void __init msm7x30_init_irq(void) 49static void __init msm7x30_init_irq(void)
@@ -70,10 +54,6 @@ static void __init msm7x30_init_irq(void)
70static void __init msm7x30_init(void) 54static void __init msm7x30_init(void)
71{ 55{
72 platform_add_devices(devices, ARRAY_SIZE(devices)); 56 platform_add_devices(devices, ARRAY_SIZE(devices));
73#ifdef CONFIG_SERIAL_MSM_CONSOLE
74 msm7x30_init_uart2();
75#endif
76
77} 57}
78 58
79static void __init msm7x30_map_io(void) 59static void __init msm7x30_map_io(void)
@@ -84,8 +64,6 @@ static void __init msm7x30_map_io(void)
84 64
85MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF") 65MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
86#ifdef CONFIG_MSM_DEBUG_UART 66#ifdef CONFIG_MSM_DEBUG_UART
87 .phys_io = MSM_DEBUG_UART_PHYS,
88 .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
89#endif 67#endif
90 .boot_params = PHYS_OFFSET + 0x100, 68 .boot_params = PHYS_OFFSET + 0x100,
91 .map_io = msm7x30_map_io, 69 .map_io = msm7x30_map_io,
@@ -96,8 +74,6 @@ MACHINE_END
96 74
97MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") 75MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
98#ifdef CONFIG_MSM_DEBUG_UART 76#ifdef CONFIG_MSM_DEBUG_UART
99 .phys_io = MSM_DEBUG_UART_PHYS,
100 .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
101#endif 77#endif
102 .boot_params = PHYS_OFFSET + 0x100, 78 .boot_params = PHYS_OFFSET + 0x100,
103 .map_io = msm7x30_map_io, 79 .map_io = msm7x30_map_io,
@@ -108,8 +84,6 @@ MACHINE_END
108 84
109MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") 85MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
110#ifdef CONFIG_MSM_DEBUG_UART 86#ifdef CONFIG_MSM_DEBUG_UART
111 .phys_io = MSM_DEBUG_UART_PHYS,
112 .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
113#endif 87#endif
114 .boot_params = PHYS_OFFSET + 0x100, 88 .boot_params = PHYS_OFFSET + 0x100,
115 .map_io = msm7x30_map_io, 89 .map_io = msm7x30_map_io,
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
new file mode 100644
index 000000000000..7486a681cc71
--- /dev/null
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -0,0 +1,100 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18
19#include <linux/kernel.h>
20#include <linux/platform_device.h>
21#include <linux/io.h>
22#include <linux/irq.h>
23
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/hardware/gic.h>
27
28#include <mach/board.h>
29#include <mach/msm_iomap.h>
30
31void __iomem *gic_cpu_base_addr;
32
33unsigned long clk_get_max_axi_khz(void)
34{
35 return 0;
36}
37
38static void __init msm8x60_map_io(void)
39{
40 msm_map_msm8x60_io();
41}
42
43static void __init msm8x60_init_irq(void)
44{
45 unsigned int i;
46
47 gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START);
48 gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
49 gic_cpu_init(0, MSM_QGIC_CPU_BASE);
50
51 /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
52 writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
53
54 /* RUMI does not adhere to GIC spec by enabling STIs by default.
55 * Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
56 */
57 if (!machine_is_msm8x60_sim())
58 writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
59
60 /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
61 * as they are configured as level, which does not play nice with
62 * handle_percpu_irq.
63 */
64 for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
65 if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
66 set_irq_handler(i, handle_percpu_irq);
67 }
68}
69
70static void __init msm8x60_init(void)
71{
72}
73
74MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
75 .map_io = msm8x60_map_io,
76 .init_irq = msm8x60_init_irq,
77 .init_machine = msm8x60_init,
78 .timer = &msm_timer,
79MACHINE_END
80
81MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
82 .map_io = msm8x60_map_io,
83 .init_irq = msm8x60_init_irq,
84 .init_machine = msm8x60_init,
85 .timer = &msm_timer,
86MACHINE_END
87
88MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
89 .map_io = msm8x60_map_io,
90 .init_irq = msm8x60_init_irq,
91 .init_machine = msm8x60_init,
92 .timer = &msm_timer,
93MACHINE_END
94
95MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
96 .map_io = msm8x60_map_io,
97 .init_irq = msm8x60_init_irq,
98 .init_machine = msm8x60_init,
99 .timer = &msm_timer,
100MACHINE_END
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index e3cc80792d6c..ed2af4ad97ed 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -35,20 +35,49 @@
35 35
36extern struct sys_timer msm_timer; 36extern struct sys_timer msm_timer;
37 37
38static struct msm_gpio uart3_config_data[] = { 38static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300;
39 { GPIO_CFG(86, 1, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Rx"}, 39static const unsigned qsd8x50_surf_smc91x_gpio __initdata = 156;
40 { GPIO_CFG(87, 1, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Tx"}, 40
41/* Leave smc91x resources empty here, as we'll fill them in
42 * at run-time: they vary from board to board, and the true
43 * configuration won't be known until boot.
44 */
45static struct resource smc91x_resources[] __initdata = {
46 [0] = {
47 .flags = IORESOURCE_MEM,
48 },
49 [1] = {
50 .flags = IORESOURCE_IRQ,
51 },
41}; 52};
42 53
43static struct platform_device *devices[] __initdata = { 54static struct platform_device smc91x_device __initdata = {
44 &msm_device_uart3, 55 .name = "smc91x",
56 .id = 0,
57 .num_resources = ARRAY_SIZE(smc91x_resources),
58 .resource = smc91x_resources,
45}; 59};
46 60
47static void msm8x50_init_uart3(void) 61static int __init msm_init_smc91x(void)
48{ 62{
49 msm_gpios_request_enable(uart3_config_data, 63 if (machine_is_qsd8x50_surf()) {
50 ARRAY_SIZE(uart3_config_data)); 64 smc91x_resources[0].start = qsd8x50_surf_smc91x_base;
65 smc91x_resources[0].end = qsd8x50_surf_smc91x_base + 0xff;
66 smc91x_resources[1].start =
67 gpio_to_irq(qsd8x50_surf_smc91x_gpio);
68 smc91x_resources[1].end =
69 gpio_to_irq(qsd8x50_surf_smc91x_gpio);
70 platform_device_register(&smc91x_device);
71 }
72
73 return 0;
51} 74}
75module_init(msm_init_smc91x);
76
77static struct platform_device *devices[] __initdata = {
78 &msm_device_uart3,
79 &msm_device_smd,
80};
52 81
53static void __init qsd8x50_map_io(void) 82static void __init qsd8x50_map_io(void)
54{ 83{
@@ -64,14 +93,11 @@ static void __init qsd8x50_init_irq(void)
64 93
65static void __init qsd8x50_init(void) 94static void __init qsd8x50_init(void)
66{ 95{
67 msm8x50_init_uart3();
68 platform_add_devices(devices, ARRAY_SIZE(devices)); 96 platform_add_devices(devices, ARRAY_SIZE(devices));
69} 97}
70 98
71MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") 99MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
72#ifdef CONFIG_MSM_DEBUG_UART 100#ifdef CONFIG_MSM_DEBUG_UART
73 .phys_io = MSM_DEBUG_UART_PHYS,
74 .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
75#endif 101#endif
76 .boot_params = PHYS_OFFSET + 0x100, 102 .boot_params = PHYS_OFFSET + 0x100,
77 .map_io = qsd8x50_map_io, 103 .map_io = qsd8x50_map_io,
@@ -82,8 +108,6 @@ MACHINE_END
82 108
83MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5") 109MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
84#ifdef CONFIG_MSM_DEBUG_UART 110#ifdef CONFIG_MSM_DEBUG_UART
85 .phys_io = MSM_DEBUG_UART_PHYS,
86 .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
87#endif 111#endif
88 .boot_params = PHYS_OFFSET + 0x100, 112 .boot_params = PHYS_OFFSET + 0x100,
89 .map_io = qsd8x50_map_io, 113 .map_io = qsd8x50_map_io,
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 2bc1b9d5623e..8919ffb17196 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -106,8 +106,6 @@ static void __init sapphire_map_io(void)
106MACHINE_START(SAPPHIRE, "sapphire") 106MACHINE_START(SAPPHIRE, "sapphire")
107/* Maintainer: Brian Swetland <swetland@google.com> */ 107/* Maintainer: Brian Swetland <swetland@google.com> */
108#ifdef CONFIG_MSM_DEBUG_UART 108#ifdef CONFIG_MSM_DEBUG_UART
109 .phys_io = MSM_DEBUG_UART_PHYS,
110 .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
111#endif 109#endif
112 .boot_params = PHYS_OFFSET + 0x100, 110 .boot_params = PHYS_OFFSET + 0x100,
113 .fixup = sapphire_fixup, 111 .fixup = sapphire_fixup,
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 469e0be3499d..73f146066542 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -93,8 +93,6 @@ static void __init trout_map_io(void)
93 93
94MACHINE_START(TROUT, "HTC Dream") 94MACHINE_START(TROUT, "HTC Dream")
95#ifdef CONFIG_MSM_DEBUG_UART 95#ifdef CONFIG_MSM_DEBUG_UART
96 .phys_io = MSM_DEBUG_UART_PHYS,
97 .io_pg_offst = ((MSM_DEBUG_UART_BASE) >> 18) & 0xfffc,
98#endif 96#endif
99 .boot_params = 0x10000100, 97 .boot_params = 0x10000100,
100 .fixup = trout_fixup, 98 .fixup = trout_fixup,
diff --git a/arch/arm/mach-msm/clock-dummy.c b/arch/arm/mach-msm/clock-dummy.c
new file mode 100644
index 000000000000..1250d22082ee
--- /dev/null
+++ b/arch/arm/mach-msm/clock-dummy.c
@@ -0,0 +1,54 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */
18#include <linux/clk.h>
19#include <linux/err.h>
20#include <linux/module.h>
21
22struct clk *clk_get(struct device *dev, const char *id)
23{
24 return ERR_PTR(-ENOENT);
25}
26EXPORT_SYMBOL(clk_get);
27
28int clk_enable(struct clk *clk)
29{
30 return -ENOENT;
31}
32EXPORT_SYMBOL(clk_enable);
33
34void clk_disable(struct clk *clk)
35{
36}
37EXPORT_SYMBOL(clk_disable);
38
39unsigned long clk_get_rate(struct clk *clk)
40{
41 return 0;
42}
43EXPORT_SYMBOL(clk_get_rate);
44
45int clk_set_rate(struct clk *clk, unsigned long rate)
46{
47 return -ENOENT;
48}
49EXPORT_SYMBOL(clk_set_rate);
50
51void clk_put(struct clk *clk)
52{
53}
54EXPORT_SYMBOL(clk_put);
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index b449e8ad2904..7fcf2e3b7698 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -51,6 +51,11 @@ struct platform_device msm_device_uart2 = {
51 .resource = resources_uart2, 51 .resource = resources_uart2,
52}; 52};
53 53
54struct platform_device msm_device_smd = {
55 .name = "msm_smd",
56 .id = -1,
57};
58
54struct clk msm_clocks_7x30[] = { 59struct clk msm_clocks_7x30[] = {
55 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), 60 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
56 CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0), 61 CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0),
diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c b/arch/arm/mach-msm/devices-msm8x60-iommu.c
new file mode 100644
index 000000000000..89b9d4437e92
--- /dev/null
+++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c
@@ -0,0 +1,883 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/bootmem.h>
21
22#include <mach/msm_iomap-8x60.h>
23#include <mach/irqs-8x60.h>
24#include <mach/iommu.h>
25
26static struct resource msm_iommu_jpegd_resources[] = {
27 {
28 .start = MSM_IOMMU_JPEGD_PHYS,
29 .end = MSM_IOMMU_JPEGD_PHYS + MSM_IOMMU_JPEGD_SIZE - 1,
30 .name = "physbase",
31 .flags = IORESOURCE_MEM,
32 },
33 {
34 .name = "nonsecure_irq",
35 .start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
36 .end = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
37 .flags = IORESOURCE_IRQ,
38 },
39 {
40 .name = "secure_irq",
41 .start = SMMU_JPEGD_CB_SC_SECURE_IRQ,
42 .end = SMMU_JPEGD_CB_SC_SECURE_IRQ,
43 .flags = IORESOURCE_IRQ,
44 },
45};
46
47static struct resource msm_iommu_vpe_resources[] = {
48 {
49 .start = MSM_IOMMU_VPE_PHYS,
50 .end = MSM_IOMMU_VPE_PHYS + MSM_IOMMU_VPE_SIZE - 1,
51 .name = "physbase",
52 .flags = IORESOURCE_MEM,
53 },
54 {
55 .name = "nonsecure_irq",
56 .start = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
57 .end = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
58 .flags = IORESOURCE_IRQ,
59 },
60 {
61 .name = "secure_irq",
62 .start = SMMU_VPE_CB_SC_SECURE_IRQ,
63 .end = SMMU_VPE_CB_SC_SECURE_IRQ,
64 .flags = IORESOURCE_IRQ,
65 },
66};
67
68static struct resource msm_iommu_mdp0_resources[] = {
69 {
70 .start = MSM_IOMMU_MDP0_PHYS,
71 .end = MSM_IOMMU_MDP0_PHYS + MSM_IOMMU_MDP0_SIZE - 1,
72 .name = "physbase",
73 .flags = IORESOURCE_MEM,
74 },
75 {
76 .name = "nonsecure_irq",
77 .start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
78 .end = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
79 .flags = IORESOURCE_IRQ,
80 },
81 {
82 .name = "secure_irq",
83 .start = SMMU_MDP0_CB_SC_SECURE_IRQ,
84 .end = SMMU_MDP0_CB_SC_SECURE_IRQ,
85 .flags = IORESOURCE_IRQ,
86 },
87};
88
89static struct resource msm_iommu_mdp1_resources[] = {
90 {
91 .start = MSM_IOMMU_MDP1_PHYS,
92 .end = MSM_IOMMU_MDP1_PHYS + MSM_IOMMU_MDP1_SIZE - 1,
93 .name = "physbase",
94 .flags = IORESOURCE_MEM,
95 },
96 {
97 .name = "nonsecure_irq",
98 .start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
99 .end = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
100 .flags = IORESOURCE_IRQ,
101 },
102 {
103 .name = "secure_irq",
104 .start = SMMU_MDP1_CB_SC_SECURE_IRQ,
105 .end = SMMU_MDP1_CB_SC_SECURE_IRQ,
106 .flags = IORESOURCE_IRQ,
107 },
108};
109
110static struct resource msm_iommu_rot_resources[] = {
111 {
112 .start = MSM_IOMMU_ROT_PHYS,
113 .end = MSM_IOMMU_ROT_PHYS + MSM_IOMMU_ROT_SIZE - 1,
114 .name = "physbase",
115 .flags = IORESOURCE_MEM,
116 },
117 {
118 .name = "nonsecure_irq",
119 .start = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
120 .end = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
121 .flags = IORESOURCE_IRQ,
122 },
123 {
124 .name = "secure_irq",
125 .start = SMMU_ROT_CB_SC_SECURE_IRQ,
126 .end = SMMU_ROT_CB_SC_SECURE_IRQ,
127 .flags = IORESOURCE_IRQ,
128 },
129};
130
131static struct resource msm_iommu_ijpeg_resources[] = {
132 {
133 .start = MSM_IOMMU_IJPEG_PHYS,
134 .end = MSM_IOMMU_IJPEG_PHYS + MSM_IOMMU_IJPEG_SIZE - 1,
135 .name = "physbase",
136 .flags = IORESOURCE_MEM,
137 },
138 {
139 .name = "nonsecure_irq",
140 .start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
141 .end = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
142 .flags = IORESOURCE_IRQ,
143 },
144 {
145 .name = "secure_irq",
146 .start = SMMU_IJPEG_CB_SC_SECURE_IRQ,
147 .end = SMMU_IJPEG_CB_SC_SECURE_IRQ,
148 .flags = IORESOURCE_IRQ,
149 },
150};
151
152static struct resource msm_iommu_vfe_resources[] = {
153 {
154 .start = MSM_IOMMU_VFE_PHYS,
155 .end = MSM_IOMMU_VFE_PHYS + MSM_IOMMU_VFE_SIZE - 1,
156 .name = "physbase",
157 .flags = IORESOURCE_MEM,
158 },
159 {
160 .name = "nonsecure_irq",
161 .start = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
162 .end = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
163 .flags = IORESOURCE_IRQ,
164 },
165 {
166 .name = "secure_irq",
167 .start = SMMU_VFE_CB_SC_SECURE_IRQ,
168 .end = SMMU_VFE_CB_SC_SECURE_IRQ,
169 .flags = IORESOURCE_IRQ,
170 },
171};
172
173static struct resource msm_iommu_vcodec_a_resources[] = {
174 {
175 .start = MSM_IOMMU_VCODEC_A_PHYS,
176 .end = MSM_IOMMU_VCODEC_A_PHYS + MSM_IOMMU_VCODEC_A_SIZE - 1,
177 .name = "physbase",
178 .flags = IORESOURCE_MEM,
179 },
180 {
181 .name = "nonsecure_irq",
182 .start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
183 .end = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
184 .flags = IORESOURCE_IRQ,
185 },
186 {
187 .name = "secure_irq",
188 .start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
189 .end = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
190 .flags = IORESOURCE_IRQ,
191 },
192};
193
194static struct resource msm_iommu_vcodec_b_resources[] = {
195 {
196 .start = MSM_IOMMU_VCODEC_B_PHYS,
197 .end = MSM_IOMMU_VCODEC_B_PHYS + MSM_IOMMU_VCODEC_B_SIZE - 1,
198 .name = "physbase",
199 .flags = IORESOURCE_MEM,
200 },
201 {
202 .name = "nonsecure_irq",
203 .start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
204 .end = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
205 .flags = IORESOURCE_IRQ,
206 },
207 {
208 .name = "secure_irq",
209 .start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
210 .end = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
211 .flags = IORESOURCE_IRQ,
212 },
213};
214
215static struct resource msm_iommu_gfx3d_resources[] = {
216 {
217 .start = MSM_IOMMU_GFX3D_PHYS,
218 .end = MSM_IOMMU_GFX3D_PHYS + MSM_IOMMU_GFX3D_SIZE - 1,
219 .name = "physbase",
220 .flags = IORESOURCE_MEM,
221 },
222 {
223 .name = "nonsecure_irq",
224 .start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
225 .end = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
226 .flags = IORESOURCE_IRQ,
227 },
228 {
229 .name = "secure_irq",
230 .start = SMMU_GFX3D_CB_SC_SECURE_IRQ,
231 .end = SMMU_GFX3D_CB_SC_SECURE_IRQ,
232 .flags = IORESOURCE_IRQ,
233 },
234};
235
236static struct resource msm_iommu_gfx2d0_resources[] = {
237 {
238 .start = MSM_IOMMU_GFX2D0_PHYS,
239 .end = MSM_IOMMU_GFX2D0_PHYS + MSM_IOMMU_GFX2D0_SIZE - 1,
240 .name = "physbase",
241 .flags = IORESOURCE_MEM,
242 },
243 {
244 .name = "nonsecure_irq",
245 .start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
246 .end = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
247 .flags = IORESOURCE_IRQ,
248 },
249 {
250 .name = "secure_irq",
251 .start = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
252 .end = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
253 .flags = IORESOURCE_IRQ,
254 },
255};
256
257static struct platform_device msm_root_iommu_dev = {
258 .name = "msm_iommu",
259 .id = -1,
260};
261
262static struct msm_iommu_dev jpegd_smmu = {
263 .name = "jpegd",
264 .clk_rate = -1
265};
266
267static struct msm_iommu_dev vpe_smmu = {
268 .name = "vpe"
269};
270
271static struct msm_iommu_dev mdp0_smmu = {
272 .name = "mdp0"
273};
274
275static struct msm_iommu_dev mdp1_smmu = {
276 .name = "mdp1"
277};
278
279static struct msm_iommu_dev rot_smmu = {
280 .name = "rot"
281};
282
283static struct msm_iommu_dev ijpeg_smmu = {
284 .name = "ijpeg"
285};
286
287static struct msm_iommu_dev vfe_smmu = {
288 .name = "vfe",
289 .clk_rate = -1
290};
291
292static struct msm_iommu_dev vcodec_a_smmu = {
293 .name = "vcodec_a"
294};
295
296static struct msm_iommu_dev vcodec_b_smmu = {
297 .name = "vcodec_b"
298};
299
300static struct msm_iommu_dev gfx3d_smmu = {
301 .name = "gfx3d",
302 .clk_rate = 27000000
303};
304
305static struct msm_iommu_dev gfx2d0_smmu = {
306 .name = "gfx2d0",
307 .clk_rate = 27000000
308};
309
310static struct platform_device msm_device_smmu_jpegd = {
311 .name = "msm_iommu",
312 .id = 0,
313 .dev = {
314 .parent = &msm_root_iommu_dev.dev,
315 },
316 .num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources),
317 .resource = msm_iommu_jpegd_resources,
318};
319
320static struct platform_device msm_device_smmu_vpe = {
321 .name = "msm_iommu",
322 .id = 1,
323 .dev = {
324 .parent = &msm_root_iommu_dev.dev,
325 },
326 .num_resources = ARRAY_SIZE(msm_iommu_vpe_resources),
327 .resource = msm_iommu_vpe_resources,
328};
329
330static struct platform_device msm_device_smmu_mdp0 = {
331 .name = "msm_iommu",
332 .id = 2,
333 .dev = {
334 .parent = &msm_root_iommu_dev.dev,
335 },
336 .num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources),
337 .resource = msm_iommu_mdp0_resources,
338};
339
340static struct platform_device msm_device_smmu_mdp1 = {
341 .name = "msm_iommu",
342 .id = 3,
343 .dev = {
344 .parent = &msm_root_iommu_dev.dev,
345 },
346 .num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources),
347 .resource = msm_iommu_mdp1_resources,
348};
349
350static struct platform_device msm_device_smmu_rot = {
351 .name = "msm_iommu",
352 .id = 4,
353 .dev = {
354 .parent = &msm_root_iommu_dev.dev,
355 },
356 .num_resources = ARRAY_SIZE(msm_iommu_rot_resources),
357 .resource = msm_iommu_rot_resources,
358};
359
360static struct platform_device msm_device_smmu_ijpeg = {
361 .name = "msm_iommu",
362 .id = 5,
363 .dev = {
364 .parent = &msm_root_iommu_dev.dev,
365 },
366 .num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources),
367 .resource = msm_iommu_ijpeg_resources,
368};
369
370static struct platform_device msm_device_smmu_vfe = {
371 .name = "msm_iommu",
372 .id = 6,
373 .dev = {
374 .parent = &msm_root_iommu_dev.dev,
375 },
376 .num_resources = ARRAY_SIZE(msm_iommu_vfe_resources),
377 .resource = msm_iommu_vfe_resources,
378};
379
380static struct platform_device msm_device_smmu_vcodec_a = {
381 .name = "msm_iommu",
382 .id = 7,
383 .dev = {
384 .parent = &msm_root_iommu_dev.dev,
385 },
386 .num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources),
387 .resource = msm_iommu_vcodec_a_resources,
388};
389
390static struct platform_device msm_device_smmu_vcodec_b = {
391 .name = "msm_iommu",
392 .id = 8,
393 .dev = {
394 .parent = &msm_root_iommu_dev.dev,
395 },
396 .num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources),
397 .resource = msm_iommu_vcodec_b_resources,
398};
399
400static struct platform_device msm_device_smmu_gfx3d = {
401 .name = "msm_iommu",
402 .id = 9,
403 .dev = {
404 .parent = &msm_root_iommu_dev.dev,
405 },
406 .num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources),
407 .resource = msm_iommu_gfx3d_resources,
408};
409
410static struct platform_device msm_device_smmu_gfx2d0 = {
411 .name = "msm_iommu",
412 .id = 10,
413 .dev = {
414 .parent = &msm_root_iommu_dev.dev,
415 },
416 .num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources),
417 .resource = msm_iommu_gfx2d0_resources,
418};
419
420static struct msm_iommu_ctx_dev jpegd_src_ctx = {
421 .name = "jpegd_src",
422 .num = 0,
423 .mids = {0, -1}
424};
425
426static struct msm_iommu_ctx_dev jpegd_dst_ctx = {
427 .name = "jpegd_dst",
428 .num = 1,
429 .mids = {1, -1}
430};
431
432static struct msm_iommu_ctx_dev vpe_src_ctx = {
433 .name = "vpe_src",
434 .num = 0,
435 .mids = {0, -1}
436};
437
438static struct msm_iommu_ctx_dev vpe_dst_ctx = {
439 .name = "vpe_dst",
440 .num = 1,
441 .mids = {1, -1}
442};
443
444static struct msm_iommu_ctx_dev mdp_vg1_ctx = {
445 .name = "mdp_vg1",
446 .num = 0,
447 .mids = {0, 2, -1}
448};
449
450static struct msm_iommu_ctx_dev mdp_rgb1_ctx = {
451 .name = "mdp_rgb1",
452 .num = 1,
453 .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
454};
455
456static struct msm_iommu_ctx_dev mdp_vg2_ctx = {
457 .name = "mdp_vg2",
458 .num = 0,
459 .mids = {0, 2, -1}
460};
461
462static struct msm_iommu_ctx_dev mdp_rgb2_ctx = {
463 .name = "mdp_rgb2",
464 .num = 1,
465 .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
466};
467
468static struct msm_iommu_ctx_dev rot_src_ctx = {
469 .name = "rot_src",
470 .num = 0,
471 .mids = {0, -1}
472};
473
474static struct msm_iommu_ctx_dev rot_dst_ctx = {
475 .name = "rot_dst",
476 .num = 1,
477 .mids = {1, -1}
478};
479
480static struct msm_iommu_ctx_dev ijpeg_src_ctx = {
481 .name = "ijpeg_src",
482 .num = 0,
483 .mids = {0, -1}
484};
485
486static struct msm_iommu_ctx_dev ijpeg_dst_ctx = {
487 .name = "ijpeg_dst",
488 .num = 1,
489 .mids = {1, -1}
490};
491
492static struct msm_iommu_ctx_dev vfe_imgwr_ctx = {
493 .name = "vfe_imgwr",
494 .num = 0,
495 .mids = {2, 3, 4, 5, 6, 7, 8, -1}
496};
497
498static struct msm_iommu_ctx_dev vfe_misc_ctx = {
499 .name = "vfe_misc",
500 .num = 1,
501 .mids = {0, 1, 9, -1}
502};
503
504static struct msm_iommu_ctx_dev vcodec_a_stream_ctx = {
505 .name = "vcodec_a_stream",
506 .num = 0,
507 .mids = {2, 5, -1}
508};
509
510static struct msm_iommu_ctx_dev vcodec_a_mm1_ctx = {
511 .name = "vcodec_a_mm1",
512 .num = 1,
513 .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
514};
515
516static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = {
517 .name = "vcodec_b_mm2",
518 .num = 0,
519 .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
520};
521
522static struct msm_iommu_ctx_dev gfx3d_rbpa_ctx = {
523 .name = "gfx3d_rbpa",
524 .num = 0,
525 .mids = {-1}
526};
527
528static struct msm_iommu_ctx_dev gfx3d_cpvgttc_ctx = {
529 .name = "gfx3d_cpvgttc",
530 .num = 1,
531 .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
532};
533
534static struct msm_iommu_ctx_dev gfx3d_smmu_ctx = {
535 .name = "gfx3d_smmu",
536 .num = 2,
537 .mids = {8, 9, 10, 11, 12, -1}
538};
539
540static struct msm_iommu_ctx_dev gfx2d0_pixv1_ctx = {
541 .name = "gfx2d0_pixv1_smmu",
542 .num = 0,
543 .mids = {0, 3, 4, -1}
544};
545
546static struct msm_iommu_ctx_dev gfx2d0_texv3_ctx = {
547 .name = "gfx2d0_texv3_smmu",
548 .num = 1,
549 .mids = {1, 6, 7, -1}
550};
551
552static struct platform_device msm_device_jpegd_src_ctx = {
553 .name = "msm_iommu_ctx",
554 .id = 0,
555 .dev = {
556 .parent = &msm_device_smmu_jpegd.dev,
557 },
558};
559
560static struct platform_device msm_device_jpegd_dst_ctx = {
561 .name = "msm_iommu_ctx",
562 .id = 1,
563 .dev = {
564 .parent = &msm_device_smmu_jpegd.dev,
565 },
566};
567
568static struct platform_device msm_device_vpe_src_ctx = {
569 .name = "msm_iommu_ctx",
570 .id = 2,
571 .dev = {
572 .parent = &msm_device_smmu_vpe.dev,
573 },
574};
575
576static struct platform_device msm_device_vpe_dst_ctx = {
577 .name = "msm_iommu_ctx",
578 .id = 3,
579 .dev = {
580 .parent = &msm_device_smmu_vpe.dev,
581 },
582};
583
584static struct platform_device msm_device_mdp_vg1_ctx = {
585 .name = "msm_iommu_ctx",
586 .id = 4,
587 .dev = {
588 .parent = &msm_device_smmu_mdp0.dev,
589 },
590};
591
592static struct platform_device msm_device_mdp_rgb1_ctx = {
593 .name = "msm_iommu_ctx",
594 .id = 5,
595 .dev = {
596 .parent = &msm_device_smmu_mdp0.dev,
597 },
598};
599
600static struct platform_device msm_device_mdp_vg2_ctx = {
601 .name = "msm_iommu_ctx",
602 .id = 6,
603 .dev = {
604 .parent = &msm_device_smmu_mdp1.dev,
605 },
606};
607
608static struct platform_device msm_device_mdp_rgb2_ctx = {
609 .name = "msm_iommu_ctx",
610 .id = 7,
611 .dev = {
612 .parent = &msm_device_smmu_mdp1.dev,
613 },
614};
615
616static struct platform_device msm_device_rot_src_ctx = {
617 .name = "msm_iommu_ctx",
618 .id = 8,
619 .dev = {
620 .parent = &msm_device_smmu_rot.dev,
621 },
622};
623
624static struct platform_device msm_device_rot_dst_ctx = {
625 .name = "msm_iommu_ctx",
626 .id = 9,
627 .dev = {
628 .parent = &msm_device_smmu_rot.dev,
629 },
630};
631
632static struct platform_device msm_device_ijpeg_src_ctx = {
633 .name = "msm_iommu_ctx",
634 .id = 10,
635 .dev = {
636 .parent = &msm_device_smmu_ijpeg.dev,
637 },
638};
639
640static struct platform_device msm_device_ijpeg_dst_ctx = {
641 .name = "msm_iommu_ctx",
642 .id = 11,
643 .dev = {
644 .parent = &msm_device_smmu_ijpeg.dev,
645 },
646};
647
648static struct platform_device msm_device_vfe_imgwr_ctx = {
649 .name = "msm_iommu_ctx",
650 .id = 12,
651 .dev = {
652 .parent = &msm_device_smmu_vfe.dev,
653 },
654};
655
656static struct platform_device msm_device_vfe_misc_ctx = {
657 .name = "msm_iommu_ctx",
658 .id = 13,
659 .dev = {
660 .parent = &msm_device_smmu_vfe.dev,
661 },
662};
663
664static struct platform_device msm_device_vcodec_a_stream_ctx = {
665 .name = "msm_iommu_ctx",
666 .id = 14,
667 .dev = {
668 .parent = &msm_device_smmu_vcodec_a.dev,
669 },
670};
671
672static struct platform_device msm_device_vcodec_a_mm1_ctx = {
673 .name = "msm_iommu_ctx",
674 .id = 15,
675 .dev = {
676 .parent = &msm_device_smmu_vcodec_a.dev,
677 },
678};
679
680static struct platform_device msm_device_vcodec_b_mm2_ctx = {
681 .name = "msm_iommu_ctx",
682 .id = 16,
683 .dev = {
684 .parent = &msm_device_smmu_vcodec_b.dev,
685 },
686};
687
688static struct platform_device msm_device_gfx3d_rbpa_ctx = {
689 .name = "msm_iommu_ctx",
690 .id = 17,
691 .dev = {
692 .parent = &msm_device_smmu_gfx3d.dev,
693 },
694};
695
696static struct platform_device msm_device_gfx3d_cpvgttc_ctx = {
697 .name = "msm_iommu_ctx",
698 .id = 18,
699 .dev = {
700 .parent = &msm_device_smmu_gfx3d.dev,
701 },
702};
703
704static struct platform_device msm_device_gfx3d_smmu_ctx = {
705 .name = "msm_iommu_ctx",
706 .id = 19,
707 .dev = {
708 .parent = &msm_device_smmu_gfx3d.dev,
709 },
710};
711
712static struct platform_device msm_device_gfx2d0_pixv1_ctx = {
713 .name = "msm_iommu_ctx",
714 .id = 20,
715 .dev = {
716 .parent = &msm_device_smmu_gfx2d0.dev,
717 },
718};
719
720static struct platform_device msm_device_gfx2d0_texv3_ctx = {
721 .name = "msm_iommu_ctx",
722 .id = 21,
723 .dev = {
724 .parent = &msm_device_smmu_gfx2d0.dev,
725 },
726};
727
728static struct platform_device *msm_iommu_devs[] = {
729 &msm_device_smmu_jpegd,
730 &msm_device_smmu_vpe,
731 &msm_device_smmu_mdp0,
732 &msm_device_smmu_mdp1,
733 &msm_device_smmu_rot,
734 &msm_device_smmu_ijpeg,
735 &msm_device_smmu_vfe,
736 &msm_device_smmu_vcodec_a,
737 &msm_device_smmu_vcodec_b,
738 &msm_device_smmu_gfx3d,
739 &msm_device_smmu_gfx2d0,
740};
741
742static struct msm_iommu_dev *msm_iommu_data[] = {
743 &jpegd_smmu,
744 &vpe_smmu,
745 &mdp0_smmu,
746 &mdp1_smmu,
747 &rot_smmu,
748 &ijpeg_smmu,
749 &vfe_smmu,
750 &vcodec_a_smmu,
751 &vcodec_b_smmu,
752 &gfx3d_smmu,
753 &gfx2d0_smmu,
754};
755
756static struct platform_device *msm_iommu_ctx_devs[] = {
757 &msm_device_jpegd_src_ctx,
758 &msm_device_jpegd_dst_ctx,
759 &msm_device_vpe_src_ctx,
760 &msm_device_vpe_dst_ctx,
761 &msm_device_mdp_vg1_ctx,
762 &msm_device_mdp_rgb1_ctx,
763 &msm_device_mdp_vg2_ctx,
764 &msm_device_mdp_rgb2_ctx,
765 &msm_device_rot_src_ctx,
766 &msm_device_rot_dst_ctx,
767 &msm_device_ijpeg_src_ctx,
768 &msm_device_ijpeg_dst_ctx,
769 &msm_device_vfe_imgwr_ctx,
770 &msm_device_vfe_misc_ctx,
771 &msm_device_vcodec_a_stream_ctx,
772 &msm_device_vcodec_a_mm1_ctx,
773 &msm_device_vcodec_b_mm2_ctx,
774 &msm_device_gfx3d_rbpa_ctx,
775 &msm_device_gfx3d_cpvgttc_ctx,
776 &msm_device_gfx3d_smmu_ctx,
777 &msm_device_gfx2d0_pixv1_ctx,
778 &msm_device_gfx2d0_texv3_ctx,
779};
780
781static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
782 &jpegd_src_ctx,
783 &jpegd_dst_ctx,
784 &vpe_src_ctx,
785 &vpe_dst_ctx,
786 &mdp_vg1_ctx,
787 &mdp_rgb1_ctx,
788 &mdp_vg2_ctx,
789 &mdp_rgb2_ctx,
790 &rot_src_ctx,
791 &rot_dst_ctx,
792 &ijpeg_src_ctx,
793 &ijpeg_dst_ctx,
794 &vfe_imgwr_ctx,
795 &vfe_misc_ctx,
796 &vcodec_a_stream_ctx,
797 &vcodec_a_mm1_ctx,
798 &vcodec_b_mm2_ctx,
799 &gfx3d_rbpa_ctx,
800 &gfx3d_cpvgttc_ctx,
801 &gfx3d_smmu_ctx,
802 &gfx2d0_pixv1_ctx,
803 &gfx2d0_texv3_ctx,
804};
805
806static int msm8x60_iommu_init(void)
807{
808 int ret, i;
809
810 ret = platform_device_register(&msm_root_iommu_dev);
811 if (ret != 0) {
812 pr_err("Failed to register root IOMMU device!\n");
813 goto failure;
814 }
815
816 for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) {
817 ret = platform_device_add_data(msm_iommu_devs[i],
818 msm_iommu_data[i],
819 sizeof(struct msm_iommu_dev));
820 if (ret != 0) {
821 pr_err("platform_device_add_data failed, "
822 "i = %d\n", i);
823 goto failure_unwind;
824 }
825
826 ret = platform_device_register(msm_iommu_devs[i]);
827
828 if (ret != 0) {
829 pr_err("platform_device_register smmu failed, "
830 "i = %d\n", i);
831 goto failure_unwind;
832 }
833 }
834
835 for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) {
836 ret = platform_device_add_data(msm_iommu_ctx_devs[i],
837 msm_iommu_ctx_data[i],
838 sizeof(*msm_iommu_ctx_devs[i]));
839 if (ret != 0) {
840 pr_err("platform_device_add_data smmu failed, "
841 "i = %d\n", i);
842 goto failure_unwind2;
843 }
844
845 ret = platform_device_register(msm_iommu_ctx_devs[i]);
846 if (ret != 0) {
847 pr_err("platform_device_register ctx failed, "
848 "i = %d\n", i);
849 goto failure_unwind2;
850 }
851 }
852 return 0;
853
854failure_unwind2:
855 while (--i >= 0)
856 platform_device_unregister(msm_iommu_ctx_devs[i]);
857failure_unwind:
858 while (--i >= 0)
859 platform_device_unregister(msm_iommu_devs[i]);
860
861 platform_device_unregister(&msm_root_iommu_dev);
862failure:
863 return ret;
864}
865
866static void msm8x60_iommu_exit(void)
867{
868 int i;
869
870 for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++)
871 platform_device_unregister(msm_iommu_ctx_devs[i]);
872
873 for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i)
874 platform_device_unregister(msm_iommu_devs[i]);
875
876 platform_device_unregister(&msm_root_iommu_dev);
877}
878
879subsys_initcall(msm8x60_iommu_init);
880module_exit(msm8x60_iommu_exit);
881
882MODULE_LICENSE("GPL v2");
883MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 4d4a50785e34..6fe67c5d1ae0 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -48,6 +48,11 @@ struct platform_device msm_device_uart3 = {
48 .resource = resources_uart3, 48 .resource = resources_uart3,
49}; 49};
50 50
51struct platform_device msm_device_smd = {
52 .name = "msm_smd",
53 .id = -1,
54};
55
51struct clk msm_clocks_8x50[] = { 56struct clk msm_clocks_8x50[] = {
52 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), 57 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
53 CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN), 58 CLK_PCOM("ebi1_clk", EBI1_CLK, NULL, CLK_MIN),
diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c
index bc32c845c7b0..33051b509e88 100644
--- a/arch/arm/mach-msm/gpio.c
+++ b/arch/arm/mach-msm/gpio.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-msm/gpio.c 1/* linux/arch/arm/mach-msm/gpio.c
2 * 2 *
3 * Copyright (C) 2007 Google, Inc. 3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2009, Code Aurora Forum. All rights reserved. 4 * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
5 * 5 *
6 * This software is licensed under the terms of the GNU General Public 6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and 7 * License version 2, as published by the Free Software Foundation, and
@@ -14,72 +14,363 @@
14 * 14 *
15 */ 15 */
16 16
17#include <linux/bitops.h>
18#include <linux/gpio.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/irq.h>
17#include <linux/module.h> 22#include <linux/module.h>
18#include <mach/gpio.h> 23#include "gpio_hw.h"
19#include "proc_comm.h" 24#include "gpiomux.h"
20 25
21int gpio_tlmm_config(unsigned config, unsigned disable) 26#define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0)
22{ 27
23 return msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, &disable); 28#define MSM_GPIO_BANK(bank, first, last) \
24} 29 { \
25EXPORT_SYMBOL(gpio_tlmm_config); 30 .regs = { \
26 31 .out = MSM_GPIO_OUT_##bank, \
27int msm_gpios_enable(const struct msm_gpio *table, int size) 32 .in = MSM_GPIO_IN_##bank, \
28{ 33 .int_status = MSM_GPIO_INT_STATUS_##bank, \
29 int rc; 34 .int_clear = MSM_GPIO_INT_CLEAR_##bank, \
30 int i; 35 .int_en = MSM_GPIO_INT_EN_##bank, \
31 const struct msm_gpio *g; 36 .int_edge = MSM_GPIO_INT_EDGE_##bank, \
32 for (i = 0; i < size; i++) { 37 .int_pos = MSM_GPIO_INT_POS_##bank, \
33 g = table + i; 38 .oe = MSM_GPIO_OE_##bank, \
34 rc = gpio_tlmm_config(g->gpio_cfg, GPIO_ENABLE); 39 }, \
35 if (rc) { 40 .chip = { \
36 pr_err("gpio_tlmm_config(0x%08x, GPIO_ENABLE)" 41 .base = (first), \
37 " <%s> failed: %d\n", 42 .ngpio = (last) - (first) + 1, \
38 g->gpio_cfg, g->label ?: "?", rc); 43 .get = msm_gpio_get, \
39 pr_err("pin %d func %d dir %d pull %d drvstr %d\n", 44 .set = msm_gpio_set, \
40 GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg), 45 .direction_input = msm_gpio_direction_input, \
41 GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg), 46 .direction_output = msm_gpio_direction_output, \
42 GPIO_DRVSTR(g->gpio_cfg)); 47 .to_irq = msm_gpio_to_irq, \
43 goto err; 48 .request = msm_gpio_request, \
44 } 49 .free = msm_gpio_free, \
50 } \
45 } 51 }
52
53#define MSM_GPIO_BROKEN_INT_CLEAR 1
54
55struct msm_gpio_regs {
56 void __iomem *out;
57 void __iomem *in;
58 void __iomem *int_status;
59 void __iomem *int_clear;
60 void __iomem *int_en;
61 void __iomem *int_edge;
62 void __iomem *int_pos;
63 void __iomem *oe;
64};
65
66struct msm_gpio_chip {
67 spinlock_t lock;
68 struct gpio_chip chip;
69 struct msm_gpio_regs regs;
70#if MSM_GPIO_BROKEN_INT_CLEAR
71 unsigned int_status_copy;
72#endif
73 unsigned int both_edge_detect;
74 unsigned int int_enable[2]; /* 0: awake, 1: sleep */
75};
76
77static int msm_gpio_write(struct msm_gpio_chip *msm_chip,
78 unsigned offset, unsigned on)
79{
80 unsigned mask = BIT(offset);
81 unsigned val;
82
83 val = readl(msm_chip->regs.out);
84 if (on)
85 writel(val | mask, msm_chip->regs.out);
86 else
87 writel(val & ~mask, msm_chip->regs.out);
46 return 0; 88 return 0;
47err: 89}
48 msm_gpios_disable(table, i); 90
49 return rc; 91static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip)
50} 92{
51EXPORT_SYMBOL(msm_gpios_enable); 93 int loop_limit = 100;
52 94 unsigned pol, val, val2, intstat;
53void msm_gpios_disable(const struct msm_gpio *table, int size) 95 do {
54{ 96 val = readl(msm_chip->regs.in);
55 int rc; 97 pol = readl(msm_chip->regs.int_pos);
56 int i; 98 pol = (pol & ~msm_chip->both_edge_detect) |
57 const struct msm_gpio *g; 99 (~val & msm_chip->both_edge_detect);
58 for (i = size-1; i >= 0; i--) { 100 writel(pol, msm_chip->regs.int_pos);
59 g = table + i; 101 intstat = readl(msm_chip->regs.int_status);
60 rc = gpio_tlmm_config(g->gpio_cfg, GPIO_DISABLE); 102 val2 = readl(msm_chip->regs.in);
61 if (rc) { 103 if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0)
62 pr_err("gpio_tlmm_config(0x%08x, GPIO_DISABLE)" 104 return;
63 " <%s> failed: %d\n", 105 } while (loop_limit-- > 0);
64 g->gpio_cfg, g->label ?: "?", rc); 106 printk(KERN_ERR "msm_gpio_update_both_edge_detect, "
65 pr_err("pin %d func %d dir %d pull %d drvstr %d\n", 107 "failed to reach stable state %x != %x\n", val, val2);
66 GPIO_PIN(g->gpio_cfg), GPIO_FUNC(g->gpio_cfg), 108}
67 GPIO_DIR(g->gpio_cfg), GPIO_PULL(g->gpio_cfg), 109
68 GPIO_DRVSTR(g->gpio_cfg)); 110static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip,
69 } 111 unsigned offset)
112{
113 unsigned bit = BIT(offset);
114
115#if MSM_GPIO_BROKEN_INT_CLEAR
116 /* Save interrupts that already triggered before we loose them. */
117 /* Any interrupt that triggers between the read of int_status */
118 /* and the write to int_clear will still be lost though. */
119 msm_chip->int_status_copy |= readl(msm_chip->regs.int_status);
120 msm_chip->int_status_copy &= ~bit;
121#endif
122 writel(bit, msm_chip->regs.int_clear);
123 msm_gpio_update_both_edge_detect(msm_chip);
124 return 0;
125}
126
127static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
128{
129 struct msm_gpio_chip *msm_chip;
130 unsigned long irq_flags;
131
132 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
133 spin_lock_irqsave(&msm_chip->lock, irq_flags);
134 writel(readl(msm_chip->regs.oe) & ~BIT(offset), msm_chip->regs.oe);
135 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
136 return 0;
137}
138
139static int
140msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
141{
142 struct msm_gpio_chip *msm_chip;
143 unsigned long irq_flags;
144
145 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
146 spin_lock_irqsave(&msm_chip->lock, irq_flags);
147 msm_gpio_write(msm_chip, offset, value);
148 writel(readl(msm_chip->regs.oe) | BIT(offset), msm_chip->regs.oe);
149 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
150 return 0;
151}
152
153static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
154{
155 struct msm_gpio_chip *msm_chip;
156
157 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
158 return (readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0;
159}
160
161static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
162{
163 struct msm_gpio_chip *msm_chip;
164 unsigned long irq_flags;
165
166 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
167 spin_lock_irqsave(&msm_chip->lock, irq_flags);
168 msm_gpio_write(msm_chip, offset, value);
169 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
170}
171
172static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
173{
174 return MSM_GPIO_TO_INT(chip->base + offset);
175}
176
177#ifdef CONFIG_MSM_GPIOMUX
178static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
179{
180 return msm_gpiomux_get(chip->base + offset);
181}
182
183static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
184{
185 msm_gpiomux_put(chip->base + offset);
186}
187#else
188#define msm_gpio_request NULL
189#define msm_gpio_free NULL
190#endif
191
192struct msm_gpio_chip msm_gpio_chips[] = {
193#if defined(CONFIG_ARCH_MSM7X00A)
194 MSM_GPIO_BANK(0, 0, 15),
195 MSM_GPIO_BANK(1, 16, 42),
196 MSM_GPIO_BANK(2, 43, 67),
197 MSM_GPIO_BANK(3, 68, 94),
198 MSM_GPIO_BANK(4, 95, 106),
199 MSM_GPIO_BANK(5, 107, 121),
200#elif defined(CONFIG_ARCH_MSM7X25) || defined(CONFIG_ARCH_MSM7X27)
201 MSM_GPIO_BANK(0, 0, 15),
202 MSM_GPIO_BANK(1, 16, 42),
203 MSM_GPIO_BANK(2, 43, 67),
204 MSM_GPIO_BANK(3, 68, 94),
205 MSM_GPIO_BANK(4, 95, 106),
206 MSM_GPIO_BANK(5, 107, 132),
207#elif defined(CONFIG_ARCH_MSM7X30)
208 MSM_GPIO_BANK(0, 0, 15),
209 MSM_GPIO_BANK(1, 16, 43),
210 MSM_GPIO_BANK(2, 44, 67),
211 MSM_GPIO_BANK(3, 68, 94),
212 MSM_GPIO_BANK(4, 95, 106),
213 MSM_GPIO_BANK(5, 107, 133),
214 MSM_GPIO_BANK(6, 134, 150),
215 MSM_GPIO_BANK(7, 151, 181),
216#elif defined(CONFIG_ARCH_QSD8X50)
217 MSM_GPIO_BANK(0, 0, 15),
218 MSM_GPIO_BANK(1, 16, 42),
219 MSM_GPIO_BANK(2, 43, 67),
220 MSM_GPIO_BANK(3, 68, 94),
221 MSM_GPIO_BANK(4, 95, 103),
222 MSM_GPIO_BANK(5, 104, 121),
223 MSM_GPIO_BANK(6, 122, 152),
224 MSM_GPIO_BANK(7, 153, 164),
225#endif
226};
227
228static void msm_gpio_irq_ack(unsigned int irq)
229{
230 unsigned long irq_flags;
231 struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
232 spin_lock_irqsave(&msm_chip->lock, irq_flags);
233 msm_gpio_clear_detect_status(msm_chip,
234 irq - gpio_to_irq(msm_chip->chip.base));
235 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
236}
237
238static void msm_gpio_irq_mask(unsigned int irq)
239{
240 unsigned long irq_flags;
241 struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
242 unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
243
244 spin_lock_irqsave(&msm_chip->lock, irq_flags);
245 /* level triggered interrupts are also latched */
246 if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
247 msm_gpio_clear_detect_status(msm_chip, offset);
248 msm_chip->int_enable[0] &= ~BIT(offset);
249 writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
250 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
251}
252
253static void msm_gpio_irq_unmask(unsigned int irq)
254{
255 unsigned long irq_flags;
256 struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
257 unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
258
259 spin_lock_irqsave(&msm_chip->lock, irq_flags);
260 /* level triggered interrupts are also latched */
261 if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
262 msm_gpio_clear_detect_status(msm_chip, offset);
263 msm_chip->int_enable[0] |= BIT(offset);
264 writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
265 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
266}
267
268static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
269{
270 unsigned long irq_flags;
271 struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
272 unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
273
274 spin_lock_irqsave(&msm_chip->lock, irq_flags);
275
276 if (on)
277 msm_chip->int_enable[1] |= BIT(offset);
278 else
279 msm_chip->int_enable[1] &= ~BIT(offset);
280
281 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
282 return 0;
283}
284
285static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
286{
287 unsigned long irq_flags;
288 struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
289 unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
290 unsigned val, mask = BIT(offset);
291
292 spin_lock_irqsave(&msm_chip->lock, irq_flags);
293 val = readl(msm_chip->regs.int_edge);
294 if (flow_type & IRQ_TYPE_EDGE_BOTH) {
295 writel(val | mask, msm_chip->regs.int_edge);
296 irq_desc[irq].handle_irq = handle_edge_irq;
297 } else {
298 writel(val & ~mask, msm_chip->regs.int_edge);
299 irq_desc[irq].handle_irq = handle_level_irq;
300 }
301 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
302 msm_chip->both_edge_detect |= mask;
303 msm_gpio_update_both_edge_detect(msm_chip);
304 } else {
305 msm_chip->both_edge_detect &= ~mask;
306 val = readl(msm_chip->regs.int_pos);
307 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
308 writel(val | mask, msm_chip->regs.int_pos);
309 else
310 writel(val & ~mask, msm_chip->regs.int_pos);
70 } 311 }
312 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
313 return 0;
71} 314}
72EXPORT_SYMBOL(msm_gpios_disable);
73 315
74int msm_gpios_request_enable(const struct msm_gpio *table, int size) 316static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
75{ 317{
76 int rc = msm_gpios_enable(table, size); 318 int i, j, mask;
77 return rc; 319 unsigned val;
320
321 for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
322 struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
323 val = readl(msm_chip->regs.int_status);
324 val &= msm_chip->int_enable[0];
325 while (val) {
326 mask = val & -val;
327 j = fls(mask) - 1;
328 /* printk("%s %08x %08x bit %d gpio %d irq %d\n",
329 __func__, v, m, j, msm_chip->chip.start + j,
330 FIRST_GPIO_IRQ + msm_chip->chip.start + j); */
331 val &= ~mask;
332 generic_handle_irq(FIRST_GPIO_IRQ +
333 msm_chip->chip.base + j);
334 }
335 }
336 desc->chip->ack(irq);
78} 337}
79EXPORT_SYMBOL(msm_gpios_request_enable);
80 338
81void msm_gpios_disable_free(const struct msm_gpio *table, int size) 339static struct irq_chip msm_gpio_irq_chip = {
340 .name = "msmgpio",
341 .ack = msm_gpio_irq_ack,
342 .mask = msm_gpio_irq_mask,
343 .unmask = msm_gpio_irq_unmask,
344 .set_wake = msm_gpio_irq_set_wake,
345 .set_type = msm_gpio_irq_set_type,
346};
347
348static int __init msm_init_gpio(void)
82{ 349{
83 msm_gpios_disable(table, size); 350 int i, j = 0;
351
352 for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) {
353 if (i - FIRST_GPIO_IRQ >=
354 msm_gpio_chips[j].chip.base +
355 msm_gpio_chips[j].chip.ngpio)
356 j++;
357 set_irq_chip_data(i, &msm_gpio_chips[j]);
358 set_irq_chip(i, &msm_gpio_irq_chip);
359 set_irq_handler(i, handle_edge_irq);
360 set_irq_flags(i, IRQF_VALID);
361 }
362
363 for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
364 spin_lock_init(&msm_gpio_chips[i].lock);
365 writel(0, msm_gpio_chips[i].regs.int_en);
366 gpiochip_add(&msm_gpio_chips[i].chip);
367 }
368
369 set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
370 set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
371 set_irq_wake(INT_GPIO_GROUP1, 1);
372 set_irq_wake(INT_GPIO_GROUP2, 2);
373 return 0;
84} 374}
85EXPORT_SYMBOL(msm_gpios_disable_free); 375
376postcore_initcall(msm_init_gpio);
diff --git a/arch/arm/mach-msm/gpio_hw.h b/arch/arm/mach-msm/gpio_hw.h
new file mode 100644
index 000000000000..6b5066038baa
--- /dev/null
+++ b/arch/arm/mach-msm/gpio_hw.h
@@ -0,0 +1,278 @@
1/* arch/arm/mach-msm/gpio_hw.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __ARCH_ARM_MACH_MSM_GPIO_HW_H
19#define __ARCH_ARM_MACH_MSM_GPIO_HW_H
20
21#include <mach/msm_iomap.h>
22
23/* see 80-VA736-2 Rev C pp 695-751
24**
25** These are actually the *shadow* gpio registers, since the
26** real ones (which allow full access) are only available to the
27** ARM9 side of the world.
28**
29** Since the _BASE need to be page-aligned when we're mapping them
30** to virtual addresses, adjust for the additional offset in these
31** macros.
32*/
33
34#if defined(CONFIG_ARCH_MSM7X30)
35#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
36#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
37#else
38#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
39#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
40#endif
41
42#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X25) ||\
43 defined(CONFIG_ARCH_MSM7X27)
44
45/* output value */
46#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
47#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */
48#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */
49#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
50#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */
51#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 107-121 */
52
53/* same pin map as above, output enable */
54#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10)
55#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08)
56#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14)
57#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18)
58#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C)
59#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54)
60
61/* same pin map as above, input read */
62#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34)
63#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20)
64#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38)
65#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C)
66#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40)
67#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44)
68
69/* same pin map as above, 1=edge 0=level interrup */
70#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60)
71#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
72#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64)
73#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68)
74#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C)
75#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0)
76
77/* same pin map as above, 1=positive 0=negative */
78#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70)
79#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
80#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74)
81#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78)
82#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C)
83#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC)
84
85/* same pin map as above, interrupt enable */
86#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80)
87#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
88#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84)
89#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88)
90#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C)
91#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8)
92
93/* same pin map as above, write 1 to clear interrupt */
94#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90)
95#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
96#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94)
97#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98)
98#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C)
99#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4)
100
101/* same pin map as above, 1=interrupt pending */
102#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0)
103#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
104#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4)
105#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8)
106#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC)
107#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0)
108
109#endif
110
111#if defined(CONFIG_ARCH_QSD8X50)
112/* output value */
113#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
114#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */
115#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */
116#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
117#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 103-95 */
118#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x10) /* gpio 121-104 */
119#define MSM_GPIO_OUT_6 MSM_GPIO1_REG(0x14) /* gpio 152-122 */
120#define MSM_GPIO_OUT_7 MSM_GPIO1_REG(0x18) /* gpio 164-153 */
121
122/* same pin map as above, output enable */
123#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x20)
124#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08)
125#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x24)
126#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x28)
127#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x2C)
128#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x30)
129#define MSM_GPIO_OE_6 MSM_GPIO1_REG(0x34)
130#define MSM_GPIO_OE_7 MSM_GPIO1_REG(0x38)
131
132/* same pin map as above, input read */
133#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x50)
134#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20)
135#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x54)
136#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x58)
137#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x5C)
138#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x60)
139#define MSM_GPIO_IN_6 MSM_GPIO1_REG(0x64)
140#define MSM_GPIO_IN_7 MSM_GPIO1_REG(0x68)
141
142/* same pin map as above, 1=edge 0=level interrup */
143#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x70)
144#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
145#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x74)
146#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x78)
147#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x7C)
148#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0x80)
149#define MSM_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0x84)
150#define MSM_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x88)
151
152/* same pin map as above, 1=positive 0=negative */
153#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x90)
154#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
155#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x94)
156#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x98)
157#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x9C)
158#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xA0)
159#define MSM_GPIO_INT_POS_6 MSM_GPIO1_REG(0xA4)
160#define MSM_GPIO_INT_POS_7 MSM_GPIO1_REG(0xA8)
161
162/* same pin map as above, interrupt enable */
163#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0xB0)
164#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
165#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0xB4)
166#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0xB8)
167#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0xBC)
168#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xC0)
169#define MSM_GPIO_INT_EN_6 MSM_GPIO1_REG(0xC4)
170#define MSM_GPIO_INT_EN_7 MSM_GPIO1_REG(0xC8)
171
172/* same pin map as above, write 1 to clear interrupt */
173#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0xD0)
174#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
175#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0xD4)
176#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0xD8)
177#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0xDC)
178#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xE0)
179#define MSM_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xE4)
180#define MSM_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0xE8)
181
182/* same pin map as above, 1=interrupt pending */
183#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xF0)
184#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
185#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xF4)
186#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xF8)
187#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xFC)
188#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0x100)
189#define MSM_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0x104)
190#define MSM_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x108)
191
192#endif
193
194#if defined(CONFIG_ARCH_MSM7X30)
195
196/* output value */
197#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
198#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 43-16 */
199#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-44 */
200#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
201#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */
202#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 133-107 */
203#define MSM_GPIO_OUT_6 MSM_GPIO1_REG(0xC4) /* gpio 150-134 */
204#define MSM_GPIO_OUT_7 MSM_GPIO1_REG(0x214) /* gpio 181-151 */
205
206/* same pin map as above, output enable */
207#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10)
208#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08)
209#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14)
210#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18)
211#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C)
212#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54)
213#define MSM_GPIO_OE_6 MSM_GPIO1_REG(0xC8)
214#define MSM_GPIO_OE_7 MSM_GPIO1_REG(0x218)
215
216/* same pin map as above, input read */
217#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34)
218#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20)
219#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38)
220#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C)
221#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40)
222#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44)
223#define MSM_GPIO_IN_6 MSM_GPIO1_REG(0xCC)
224#define MSM_GPIO_IN_7 MSM_GPIO1_REG(0x21C)
225
226/* same pin map as above, 1=edge 0=level interrup */
227#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60)
228#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
229#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64)
230#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68)
231#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C)
232#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0)
233#define MSM_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0xD0)
234#define MSM_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x240)
235
236/* same pin map as above, 1=positive 0=negative */
237#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70)
238#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
239#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74)
240#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78)
241#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C)
242#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC)
243#define MSM_GPIO_INT_POS_6 MSM_GPIO1_REG(0xD4)
244#define MSM_GPIO_INT_POS_7 MSM_GPIO1_REG(0x228)
245
246/* same pin map as above, interrupt enable */
247#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80)
248#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
249#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84)
250#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88)
251#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C)
252#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8)
253#define MSM_GPIO_INT_EN_6 MSM_GPIO1_REG(0xD8)
254#define MSM_GPIO_INT_EN_7 MSM_GPIO1_REG(0x22C)
255
256/* same pin map as above, write 1 to clear interrupt */
257#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90)
258#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
259#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94)
260#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98)
261#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C)
262#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4)
263#define MSM_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xDC)
264#define MSM_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0x230)
265
266/* same pin map as above, 1=interrupt pending */
267#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0)
268#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
269#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4)
270#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8)
271#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC)
272#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0)
273#define MSM_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0xE0)
274#define MSM_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x234)
275
276#endif
277
278#endif
diff --git a/arch/arm/mach-msm/gpiomux-7x30.c b/arch/arm/mach-msm/gpiomux-7x30.c
new file mode 100644
index 000000000000..6ce41c5241a5
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-7x30.c
@@ -0,0 +1,38 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17#include "gpiomux.h"
18
19struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
20#ifdef CONFIG_SERIAL_MSM_CONSOLE
21 [49] = { /* UART2 RFR */
22 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
23 GPIOMUX_FUNC_2 | GPIOMUX_VALID,
24 },
25 [50] = { /* UART2 CTS */
26 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
27 GPIOMUX_FUNC_2 | GPIOMUX_VALID,
28 },
29 [51] = { /* UART2 RX */
30 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
31 GPIOMUX_FUNC_2 | GPIOMUX_VALID,
32 },
33 [52] = { /* UART2 TX */
34 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
35 GPIOMUX_FUNC_2 | GPIOMUX_VALID,
36 },
37#endif
38};
diff --git a/arch/arm/mach-msm/gpiomux-8x50.c b/arch/arm/mach-msm/gpiomux-8x50.c
new file mode 100644
index 000000000000..4406e0f4ae95
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-8x50.c
@@ -0,0 +1,28 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17#include "gpiomux.h"
18
19struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
20 [86] = { /* UART3 RX */
21 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
22 GPIOMUX_FUNC_1 | GPIOMUX_VALID,
23 },
24 [87] = { /* UART3 TX */
25 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
26 GPIOMUX_FUNC_1 | GPIOMUX_VALID,
27 },
28};
diff --git a/arch/arm/mach-msm/gpiomux-8x60.c b/arch/arm/mach-msm/gpiomux-8x60.c
new file mode 100644
index 000000000000..7b380b31bd0e
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-8x60.c
@@ -0,0 +1,19 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17#include "gpiomux.h"
18
19struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {};
diff --git a/arch/arm/mach-msm/gpiomux-v1.c b/arch/arm/mach-msm/gpiomux-v1.c
new file mode 100644
index 000000000000..27de2abd7144
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-v1.c
@@ -0,0 +1,33 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17#include <linux/kernel.h>
18#include "gpiomux.h"
19#include "proc_comm.h"
20
21void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val)
22{
23 unsigned tlmm_config = (val & ~GPIOMUX_CTL_MASK) |
24 ((gpio & 0x3ff) << 4);
25 unsigned tlmm_disable = 0;
26 int rc;
27
28 rc = msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX,
29 &tlmm_config, &tlmm_disable);
30 if (rc)
31 pr_err("%s: unexpected proc_comm failure %d: %08x %08x\n",
32 __func__, rc, tlmm_config, tlmm_disable);
33}
diff --git a/arch/arm/mach-msm/gpiomux-v1.h b/arch/arm/mach-msm/gpiomux-v1.h
new file mode 100644
index 000000000000..71d86feba450
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-v1.h
@@ -0,0 +1,67 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_V1_H
18#define __ARCH_ARM_MACH_MSM_GPIOMUX_V1_H
19
20#if defined(CONFIG_ARCH_MSM7X30)
21#define GPIOMUX_NGPIOS 182
22#elif defined(CONFIG_ARCH_QSD8X50)
23#define GPIOMUX_NGPIOS 165
24#else
25#define GPIOMUX_NGPIOS 133
26#endif
27
28typedef u32 gpiomux_config_t;
29
30enum {
31 GPIOMUX_DRV_2MA = 0UL << 17,
32 GPIOMUX_DRV_4MA = 1UL << 17,
33 GPIOMUX_DRV_6MA = 2UL << 17,
34 GPIOMUX_DRV_8MA = 3UL << 17,
35 GPIOMUX_DRV_10MA = 4UL << 17,
36 GPIOMUX_DRV_12MA = 5UL << 17,
37 GPIOMUX_DRV_14MA = 6UL << 17,
38 GPIOMUX_DRV_16MA = 7UL << 17,
39};
40
41enum {
42 GPIOMUX_FUNC_GPIO = 0UL,
43 GPIOMUX_FUNC_1 = 1UL,
44 GPIOMUX_FUNC_2 = 2UL,
45 GPIOMUX_FUNC_3 = 3UL,
46 GPIOMUX_FUNC_4 = 4UL,
47 GPIOMUX_FUNC_5 = 5UL,
48 GPIOMUX_FUNC_6 = 6UL,
49 GPIOMUX_FUNC_7 = 7UL,
50 GPIOMUX_FUNC_8 = 8UL,
51 GPIOMUX_FUNC_9 = 9UL,
52 GPIOMUX_FUNC_A = 10UL,
53 GPIOMUX_FUNC_B = 11UL,
54 GPIOMUX_FUNC_C = 12UL,
55 GPIOMUX_FUNC_D = 13UL,
56 GPIOMUX_FUNC_E = 14UL,
57 GPIOMUX_FUNC_F = 15UL,
58};
59
60enum {
61 GPIOMUX_PULL_NONE = 0UL << 15,
62 GPIOMUX_PULL_DOWN = 1UL << 15,
63 GPIOMUX_PULL_KEEPER = 2UL << 15,
64 GPIOMUX_PULL_UP = 3UL << 15,
65};
66
67#endif
diff --git a/arch/arm/mach-msm/gpiomux-v2.c b/arch/arm/mach-msm/gpiomux-v2.c
new file mode 100644
index 000000000000..273396d2b127
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-v2.c
@@ -0,0 +1,25 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17#include <linux/io.h>
18#include <mach/msm_iomap.h>
19#include "gpiomux.h"
20
21void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val)
22{
23 writel(val & ~GPIOMUX_CTL_MASK,
24 MSM_TLMM_BASE + 0x1000 + (0x10 * gpio));
25}
diff --git a/arch/arm/mach-msm/gpiomux-v2.h b/arch/arm/mach-msm/gpiomux-v2.h
new file mode 100644
index 000000000000..3bf10e7f0381
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux-v2.h
@@ -0,0 +1,61 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_V2_H
18#define __ARCH_ARM_MACH_MSM_GPIOMUX_V2_H
19
20#define GPIOMUX_NGPIOS 173
21
22typedef u16 gpiomux_config_t;
23
24enum {
25 GPIOMUX_DRV_2MA = 0UL << 6,
26 GPIOMUX_DRV_4MA = 1UL << 6,
27 GPIOMUX_DRV_6MA = 2UL << 6,
28 GPIOMUX_DRV_8MA = 3UL << 6,
29 GPIOMUX_DRV_10MA = 4UL << 6,
30 GPIOMUX_DRV_12MA = 5UL << 6,
31 GPIOMUX_DRV_14MA = 6UL << 6,
32 GPIOMUX_DRV_16MA = 7UL << 6,
33};
34
35enum {
36 GPIOMUX_FUNC_GPIO = 0UL << 2,
37 GPIOMUX_FUNC_1 = 1UL << 2,
38 GPIOMUX_FUNC_2 = 2UL << 2,
39 GPIOMUX_FUNC_3 = 3UL << 2,
40 GPIOMUX_FUNC_4 = 4UL << 2,
41 GPIOMUX_FUNC_5 = 5UL << 2,
42 GPIOMUX_FUNC_6 = 6UL << 2,
43 GPIOMUX_FUNC_7 = 7UL << 2,
44 GPIOMUX_FUNC_8 = 8UL << 2,
45 GPIOMUX_FUNC_9 = 9UL << 2,
46 GPIOMUX_FUNC_A = 10UL << 2,
47 GPIOMUX_FUNC_B = 11UL << 2,
48 GPIOMUX_FUNC_C = 12UL << 2,
49 GPIOMUX_FUNC_D = 13UL << 2,
50 GPIOMUX_FUNC_E = 14UL << 2,
51 GPIOMUX_FUNC_F = 15UL << 2,
52};
53
54enum {
55 GPIOMUX_PULL_NONE = 0UL,
56 GPIOMUX_PULL_DOWN = 1UL,
57 GPIOMUX_PULL_KEEPER = 2UL,
58 GPIOMUX_PULL_UP = 3UL,
59};
60
61#endif
diff --git a/arch/arm/mach-msm/gpiomux.c b/arch/arm/mach-msm/gpiomux.c
new file mode 100644
index 000000000000..53af21abd155
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux.c
@@ -0,0 +1,96 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17#include <linux/module.h>
18#include <linux/spinlock.h>
19#include "gpiomux.h"
20
21static DEFINE_SPINLOCK(gpiomux_lock);
22
23int msm_gpiomux_write(unsigned gpio,
24 gpiomux_config_t active,
25 gpiomux_config_t suspended)
26{
27 struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
28 unsigned long irq_flags;
29 gpiomux_config_t setting;
30
31 if (gpio >= GPIOMUX_NGPIOS)
32 return -EINVAL;
33
34 spin_lock_irqsave(&gpiomux_lock, irq_flags);
35
36 if (active & GPIOMUX_VALID)
37 cfg->active = active;
38
39 if (suspended & GPIOMUX_VALID)
40 cfg->suspended = suspended;
41
42 setting = cfg->ref ? active : suspended;
43 if (setting & GPIOMUX_VALID)
44 __msm_gpiomux_write(gpio, setting);
45
46 spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
47 return 0;
48}
49EXPORT_SYMBOL(msm_gpiomux_write);
50
51int msm_gpiomux_get(unsigned gpio)
52{
53 struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
54 unsigned long irq_flags;
55
56 if (gpio >= GPIOMUX_NGPIOS)
57 return -EINVAL;
58
59 spin_lock_irqsave(&gpiomux_lock, irq_flags);
60 if (cfg->ref++ == 0 && cfg->active & GPIOMUX_VALID)
61 __msm_gpiomux_write(gpio, cfg->active);
62 spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
63 return 0;
64}
65EXPORT_SYMBOL(msm_gpiomux_get);
66
67int msm_gpiomux_put(unsigned gpio)
68{
69 struct msm_gpiomux_config *cfg = msm_gpiomux_configs + gpio;
70 unsigned long irq_flags;
71
72 if (gpio >= GPIOMUX_NGPIOS)
73 return -EINVAL;
74
75 spin_lock_irqsave(&gpiomux_lock, irq_flags);
76 BUG_ON(cfg->ref == 0);
77 if (--cfg->ref == 0 && cfg->suspended & GPIOMUX_VALID)
78 __msm_gpiomux_write(gpio, cfg->suspended);
79 spin_unlock_irqrestore(&gpiomux_lock, irq_flags);
80 return 0;
81}
82EXPORT_SYMBOL(msm_gpiomux_put);
83
84static int __init gpiomux_init(void)
85{
86 unsigned n;
87
88 for (n = 0; n < GPIOMUX_NGPIOS; ++n) {
89 msm_gpiomux_configs[n].ref = 0;
90 if (!(msm_gpiomux_configs[n].suspended & GPIOMUX_VALID))
91 continue;
92 __msm_gpiomux_write(n, msm_gpiomux_configs[n].suspended);
93 }
94 return 0;
95}
96postcore_initcall(gpiomux_init);
diff --git a/arch/arm/mach-msm/gpiomux.h b/arch/arm/mach-msm/gpiomux.h
new file mode 100644
index 000000000000..b178d9cb742f
--- /dev/null
+++ b/arch/arm/mach-msm/gpiomux.h
@@ -0,0 +1,114 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17#ifndef __ARCH_ARM_MACH_MSM_GPIOMUX_H
18#define __ARCH_ARM_MACH_MSM_GPIOMUX_H
19
20#include <linux/bitops.h>
21#include <linux/errno.h>
22
23#if defined(CONFIG_MSM_V2_TLMM)
24#include "gpiomux-v2.h"
25#else
26#include "gpiomux-v1.h"
27#endif
28
29/**
30 * struct msm_gpiomux_config: gpiomux settings for one gpio line.
31 *
32 * A complete gpiomux config is the bitwise-or of a drive-strength,
33 * function, and pull. For functions other than GPIO, the OE
34 * is hard-wired according to the function. For GPIO mode,
35 * OE is controlled by gpiolib.
36 *
37 * Available settings differ by target; see the gpiomux header
38 * specific to your target arch for available configurations.
39 *
40 * @active: The configuration to be installed when the line is
41 * active, or its reference count is > 0.
42 * @suspended: The configuration to be installed when the line
43 * is suspended, or its reference count is 0.
44 * @ref: The reference count of the line. For internal use of
45 * the gpiomux framework only.
46 */
47struct msm_gpiomux_config {
48 gpiomux_config_t active;
49 gpiomux_config_t suspended;
50 unsigned ref;
51};
52
53/**
54 * @GPIOMUX_VALID: If set, the config field contains 'good data'.
55 * The absence of this bit will prevent the gpiomux
56 * system from applying the configuration under all
57 * circumstances.
58 */
59enum {
60 GPIOMUX_VALID = BIT(sizeof(gpiomux_config_t) * BITS_PER_BYTE - 1),
61 GPIOMUX_CTL_MASK = GPIOMUX_VALID,
62};
63
64#ifdef CONFIG_MSM_GPIOMUX
65
66/* Each architecture must provide its own instance of this table.
67 * To avoid having gpiomux manage any given gpio, one or both of
68 * the entries can avoid setting GPIOMUX_VALID - the absence
69 * of that flag will prevent the configuration from being applied
70 * during state transitions.
71 */
72extern struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS];
73
74/* Increment a gpio's reference count, possibly activating the line. */
75int __must_check msm_gpiomux_get(unsigned gpio);
76
77/* Decrement a gpio's reference count, possibly suspending the line. */
78int msm_gpiomux_put(unsigned gpio);
79
80/* Install a new configuration to the gpio line. To avoid overwriting
81 * a configuration, leave the VALID bit out.
82 */
83int msm_gpiomux_write(unsigned gpio,
84 gpiomux_config_t active,
85 gpiomux_config_t suspended);
86
87/* Architecture-internal function for use by the framework only.
88 * This function can assume the following:
89 * - the gpio value has passed a bounds-check
90 * - the gpiomux spinlock has been obtained
91 *
92 * This function is not for public consumption. External users
93 * should use msm_gpiomux_write.
94 */
95void __msm_gpiomux_write(unsigned gpio, gpiomux_config_t val);
96#else
97static inline int __must_check msm_gpiomux_get(unsigned gpio)
98{
99 return -ENOSYS;
100}
101
102static inline int msm_gpiomux_put(unsigned gpio)
103{
104 return -ENOSYS;
105}
106
107static inline int msm_gpiomux_write(unsigned gpio,
108 gpiomux_config_t active,
109 gpiomux_config_t suspended)
110{
111 return -ENOSYS;
112}
113#endif
114#endif
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 5a79bcf50413..6abf4a6eadc1 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -33,6 +33,8 @@ struct msm_acpu_clock_platform_data
33 33
34struct clk; 34struct clk;
35 35
36extern struct sys_timer msm_timer;
37
36/* common init routines for use by arch/arm/mach-msm/board-*.c */ 38/* common init routines for use by arch/arm/mach-msm/board-*.c */
37 39
38void __init msm_add_devices(void); 40void __init msm_add_devices(void);
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S
index 528750f307e9..fbd5d90dcc8c 100644
--- a/arch/arm/mach-msm/include/mach/debug-macro.S
+++ b/arch/arm/mach-msm/include/mach/debug-macro.S
@@ -19,13 +19,10 @@
19#include <mach/hardware.h> 19#include <mach/hardware.h>
20#include <mach/msm_iomap.h> 20#include <mach/msm_iomap.h>
21 21
22#ifdef CONFIG_MSM_DEBUG_UART 22#ifdef CONFIG_HAS_MSM_DEBUG_UART_PHYS
23 .macro addruart, rx, tmp 23 .macro addruart, rp, rv
24 @ see if the MMU is enabled and select appropriate base address 24 ldr \rp, =MSM_DEBUG_UART_PHYS
25 mrc p15, 0, \rx, c1, c0 25 ldr \rv, =MSM_DEBUG_UART_BASE
26 tst \rx, #1
27 ldreq \rx, =MSM_DEBUG_UART_PHYS
28 ldrne \rx, =MSM_DEBUG_UART_BASE
29 .endm 26 .endm
30 27
31 .macro senduart,rd,rx 28 .macro senduart,rd,rx
@@ -39,16 +36,7 @@
39 tst \rd, #0x04 36 tst \rd, #0x04
40 beq 1001b 37 beq 1001b
41 .endm 38 .endm
42#else
43 .macro addruart, rx, tmp
44 .endm
45
46 .macro senduart,rd,rx
47 .endm
48
49 .macro waituart,rd,rx
50 .endm
51#endif
52 39
53 .macro busyuart,rd,rx 40 .macro busyuart,rd,rx
54 .endm 41 .endm
42#endif
diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
index 00f9bbfadbe6..05583f569524 100644
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ b/arch/arm/mach-msm/include/mach/dma.h
@@ -32,10 +32,18 @@ struct msm_dmov_cmd {
32 void *data; 32 void *data;
33}; 33};
34 34
35#ifndef CONFIG_ARCH_MSM8X60
35void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd); 36void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
36void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful); 37void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
37int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr); 38int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
38 39#else
40static inline
41void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd) { }
42static inline
43void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful) { }
44static inline
45int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) { return -EIO; }
46#endif
39 47
40 48
41#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2)) 49#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
diff --git a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
new file mode 100644
index 000000000000..4dc99aa65d07
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
@@ -0,0 +1,88 @@
1/*
2 * Low-level IRQ helper macros
3 *
4 * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <mach/hardware.h>
12#include <asm/hardware/gic.h>
13
14 .macro disable_fiq
15 .endm
16
17 .macro get_irqnr_preamble, base, tmp
18 ldr \base, =gic_cpu_base_addr
19 ldr \base, [\base]
20 .endm
21
22 .macro arch_ret_to_user, tmp1, tmp2
23 .endm
24
25 /*
26 * The interrupt numbering scheme is defined in the
27 * interrupt controller spec. To wit:
28 *
29 * Migrated the code from ARM MP port to be more consistant
30 * with interrupt processing , the following still holds true
31 * however, all interrupts are treated the same regardless of
32 * if they are local IPI or PPI
33 *
34 * Interrupts 0-15 are IPI
35 * 16-31 are PPI
36 * (16-18 are the timers)
37 * 32-1020 are global
38 * 1021-1022 are reserved
39 * 1023 is "spurious" (no interrupt)
40 *
41 * A simple read from the controller will tell us the number of the
42 * highest priority enabled interrupt. We then just need to check
43 * whether it is in the valid range for an IRQ (0-1020 inclusive).
44 *
45 * Base ARM code assumes that the local (private) peripheral interrupts
46 * are not valid, we treat them differently, in that the privates are
47 * handled like normal shared interrupts with the exception that only
48 * one processor can register the interrupt and the handler must be
49 * the same for all processors.
50 */
51
52 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
53
54 ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 =srcCPU,
55 9-0 =int # */
56
57 bic \irqnr, \irqstat, #0x1c00 @mask src
58 cmp \irqnr, #15
59 ldr \tmp, =1021
60 cmpcc \irqnr, \irqnr
61 cmpne \irqnr, \tmp
62 cmpcs \irqnr, \irqnr
63
64 .endm
65
66 /* We assume that irqstat (the raw value of the IRQ acknowledge
67 * register) is preserved from the macro above.
68 * If there is an IPI, we immediately signal end of interrupt on the
69 * controller, since this requires the original irqstat value which
70 * we won't easily be able to recreate later.
71 */
72 .macro test_for_ipi, irqnr, irqstat, base, tmp
73 bic \irqnr, \irqstat, #0x1c00
74 cmp \irqnr, #16
75 strcc \irqstat, [\base, #GIC_CPU_EOI]
76 cmpcs \irqnr, \irqnr
77 .endm
78
79 /* As above, this assumes that irqstat and base are preserved.. */
80
81 .macro test_for_ltirq, irqnr, irqstat, base, tmp
82 bic \irqnr, \irqstat, #0x1c00
83 mov \tmp, #0
84 cmp \irqnr, #16
85 moveq \tmp, #1
86 streq \irqstat, [\base, #GIC_CPU_EOI]
87 cmp \tmp, #0
88 .endm
diff --git a/arch/arm/mach-msm/include/mach/entry-macro-vic.S b/arch/arm/mach-msm/include/mach/entry-macro-vic.S
new file mode 100644
index 000000000000..70563ed11b36
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/entry-macro-vic.S
@@ -0,0 +1,37 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Author: Brian Swetland <swetland@google.com>
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <mach/msm_iomap.h>
17
18 .macro disable_fiq
19 .endm
20
21 .macro get_irqnr_preamble, base, tmp
22 @ enable imprecise aborts
23 cpsie a
24 mov \base, #MSM_VIC_BASE
25 .endm
26
27 .macro arch_ret_to_user, tmp1, tmp2
28 .endm
29
30 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
31 @ 0xD0 has irq# or old irq# if the irq has been handled
32 @ 0xD4 has irq# or -1 if none pending *but* if you just
33 @ read 0xD4 you never get the first irq for some reason
34 ldr \irqnr, [\base, #0xD0]
35 ldr \irqnr, [\base, #0xD4]
36 cmp \irqnr, #0xffffffff
37 .endm
diff --git a/arch/arm/mach-msm/include/mach/entry-macro.S b/arch/arm/mach-msm/include/mach/entry-macro.S
index d2259486bcb1..b16f082eeb6f 100644
--- a/arch/arm/mach-msm/include/mach/entry-macro.S
+++ b/arch/arm/mach-msm/include/mach/entry-macro.S
@@ -1,38 +1,23 @@
1/* arch/arm/mach-msm7200/include/mach/entry-macro.S 1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 * 2 *
3 * Copyright (C) 2007 Google, Inc. 3 * This program is free software; you can redistribute it and/or modify
4 * Author: Brian Swetland <swetland@google.com> 4 * it under the terms of the GNU General Public License version 2 and
5 * 5 * only version 2 as published by the Free Software Foundation.
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 * 6 *
10 * This program is distributed in the hope that it will be useful, 7 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 10 * GNU General Public License for more details.
14 * 11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
15 */ 17 */
16 18
17#include <mach/msm_iomap.h> 19#if defined(CONFIG_ARM_GIC)
18 20#include <mach/entry-macro-qgic.S>
19 .macro disable_fiq 21#else
20 .endm 22#include <mach/entry-macro-vic.S>
21 23#endif
22 .macro get_irqnr_preamble, base, tmp
23 @ enable imprecise aborts
24 cpsie a
25 mov \base, #MSM_VIC_BASE
26 .endm
27
28 .macro arch_ret_to_user, tmp1, tmp2
29 .endm
30
31 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
32 @ 0xD0 has irq# or old irq# if the irq has been handled
33 @ 0xD4 has irq# or -1 if none pending *but* if you just
34 @ read 0xD4 you never get the first irq for some reason
35 ldr \irqnr, [\base, #0xD0]
36 ldr \irqnr, [\base, #0xD4]
37 cmp \irqnr, #0xffffffff
38 .endm
diff --git a/arch/arm/mach-msm/include/mach/gpio.h b/arch/arm/mach-msm/include/mach/gpio.h
index 83e47c0d5c2e..36ad50d3bfaa 100644
--- a/arch/arm/mach-msm/include/mach/gpio.h
+++ b/arch/arm/mach-msm/include/mach/gpio.h
@@ -23,127 +23,4 @@
23#define gpio_cansleep __gpio_cansleep 23#define gpio_cansleep __gpio_cansleep
24#define gpio_to_irq __gpio_to_irq 24#define gpio_to_irq __gpio_to_irq
25 25
26/**
27 * struct msm_gpio - GPIO pin description
28 * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config()
29 * @label - textual label
30 *
31 * Usually, GPIO's are operated by sets.
32 * This struct accumulate all GPIO information in single source
33 * and facilitete group operations provided by msm_gpios_xxx()
34 */
35struct msm_gpio {
36 u32 gpio_cfg;
37 const char *label;
38};
39
40/**
41 * msm_gpios_request_enable() - request and enable set of GPIOs
42 *
43 * Request and configure set of GPIO's
44 * In case of error, all operations rolled back.
45 * Return error code.
46 *
47 * @table: GPIO table
48 * @size: number of entries in @table
49 */
50int msm_gpios_request_enable(const struct msm_gpio *table, int size);
51
52/**
53 * msm_gpios_disable_free() - disable and free set of GPIOs
54 *
55 * @table: GPIO table
56 * @size: number of entries in @table
57 */
58void msm_gpios_disable_free(const struct msm_gpio *table, int size);
59
60/**
61 * msm_gpios_request() - request set of GPIOs
62 * In case of error, all operations rolled back.
63 * Return error code.
64 *
65 * @table: GPIO table
66 * @size: number of entries in @table
67 */
68int msm_gpios_request(const struct msm_gpio *table, int size);
69
70/**
71 * msm_gpios_free() - free set of GPIOs
72 *
73 * @table: GPIO table
74 * @size: number of entries in @table
75 */
76void msm_gpios_free(const struct msm_gpio *table, int size);
77
78/**
79 * msm_gpios_enable() - enable set of GPIOs
80 * In case of error, all operations rolled back.
81 * Return error code.
82 *
83 * @table: GPIO table
84 * @size: number of entries in @table
85 */
86int msm_gpios_enable(const struct msm_gpio *table, int size);
87
88/**
89 * msm_gpios_disable() - disable set of GPIOs
90 *
91 * @table: GPIO table
92 * @size: number of entries in @table
93 */
94void msm_gpios_disable(const struct msm_gpio *table, int size);
95
96/* GPIO TLMM (Top Level Multiplexing) Definitions */
97
98/* GPIO TLMM: Function -- GPIO specific */
99
100/* GPIO TLMM: Direction */
101enum {
102 GPIO_INPUT,
103 GPIO_OUTPUT,
104};
105
106/* GPIO TLMM: Pullup/Pulldown */
107enum {
108 GPIO_NO_PULL,
109 GPIO_PULL_DOWN,
110 GPIO_KEEPER,
111 GPIO_PULL_UP,
112};
113
114/* GPIO TLMM: Drive Strength */
115enum {
116 GPIO_2MA,
117 GPIO_4MA,
118 GPIO_6MA,
119 GPIO_8MA,
120 GPIO_10MA,
121 GPIO_12MA,
122 GPIO_14MA,
123 GPIO_16MA,
124};
125
126enum {
127 GPIO_ENABLE,
128 GPIO_DISABLE,
129};
130
131#define GPIO_CFG(gpio, func, dir, pull, drvstr) \
132 ((((gpio) & 0x3FF) << 4) | \
133 ((func) & 0xf) | \
134 (((dir) & 0x1) << 14) | \
135 (((pull) & 0x3) << 15) | \
136 (((drvstr) & 0xF) << 17))
137
138/**
139 * extract GPIO pin from bit-field used for gpio_tlmm_config
140 */
141#define GPIO_PIN(gpio_cfg) (((gpio_cfg) >> 4) & 0x3ff)
142#define GPIO_FUNC(gpio_cfg) (((gpio_cfg) >> 0) & 0xf)
143#define GPIO_DIR(gpio_cfg) (((gpio_cfg) >> 14) & 0x1)
144#define GPIO_PULL(gpio_cfg) (((gpio_cfg) >> 15) & 0x3)
145#define GPIO_DRVSTR(gpio_cfg) (((gpio_cfg) >> 17) & 0xf)
146
147int gpio_tlmm_config(unsigned config, unsigned disable);
148
149#endif /* __ASM_ARCH_MSM_GPIO_H */ 26#endif /* __ASM_ARCH_MSM_GPIO_H */
diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index c35b29f9ac0f..7386e732baad 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -28,6 +28,7 @@ void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int m
28 28
29void msm_map_qsd8x50_io(void); 29void msm_map_qsd8x50_io(void);
30void msm_map_msm7x30_io(void); 30void msm_map_msm7x30_io(void);
31void msm_map_msm8x60_io(void);
31 32
32extern unsigned int msm_shared_ram_phys; 33extern unsigned int msm_shared_ram_phys;
33 34
diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h
new file mode 100644
index 000000000000..218ef5732a24
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/iommu.h
@@ -0,0 +1,103 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#ifndef MSM_IOMMU_H
19#define MSM_IOMMU_H
20
21#include <linux/interrupt.h>
22
23/* Maximum number of Machine IDs that we are allowing to be mapped to the same
24 * context bank. The number of MIDs mapped to the same CB does not affect
25 * performance, but there is a practical limit on how many distinct MIDs may
26 * be present. These mappings are typically determined at design time and are
27 * not expected to change at run time.
28 */
29#define MAX_NUM_MIDS 16
30
31/**
32 * struct msm_iommu_dev - a single IOMMU hardware instance
33 * name Human-readable name given to this IOMMU HW instance
34 * clk_rate Rate to set for this IOMMU's clock, if applicable to this
35 * particular IOMMU. 0 means don't set a rate.
36 * -1 means it is an AXI clock with no valid rate
37 *
38 */
39struct msm_iommu_dev {
40 const char *name;
41 int clk_rate;
42};
43
44/**
45 * struct msm_iommu_ctx_dev - an IOMMU context bank instance
46 * name Human-readable name given to this context bank
47 * num Index of this context bank within the hardware
48 * mids List of Machine IDs that are to be mapped into this context
49 * bank, terminated by -1. The MID is a set of signals on the
50 * AXI bus that identifies the function associated with a specific
51 * memory request. (See ARM spec).
52 */
53struct msm_iommu_ctx_dev {
54 const char *name;
55 int num;
56 int mids[MAX_NUM_MIDS];
57};
58
59
60/**
61 * struct msm_iommu_drvdata - A single IOMMU hardware instance
62 * @base: IOMMU config port base address (VA)
63 * @irq: Interrupt number
64 *
65 * A msm_iommu_drvdata holds the global driver data about a single piece
66 * of an IOMMU hardware instance.
67 */
68struct msm_iommu_drvdata {
69 void __iomem *base;
70 int irq;
71};
72
73/**
74 * struct msm_iommu_ctx_drvdata - an IOMMU context bank instance
75 * @num: Hardware context number of this context
76 * @pdev: Platform device associated wit this HW instance
77 * @attached_elm: List element for domains to track which devices are
78 * attached to them
79 *
80 * A msm_iommu_ctx_drvdata holds the driver data for a single context bank
81 * within each IOMMU hardware instance
82 */
83struct msm_iommu_ctx_drvdata {
84 int num;
85 struct platform_device *pdev;
86 struct list_head attached_elm;
87};
88
89/*
90 * Look up an IOMMU context device by its context name. NULL if none found.
91 * Useful for testing and drivers that do not yet fully have IOMMU stuff in
92 * their platform devices.
93 */
94struct device *msm_iommu_get_ctx(const char *ctx_name);
95
96/*
97 * Interrupt handler for the IOMMU context fault interrupt. Hooking the
98 * interrupt is not supported in the API yet, but this will print an error
99 * message and dump useful IOMMU registers.
100 */
101irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
102
103#endif
diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
new file mode 100644
index 000000000000..f9386d3a2f77
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
@@ -0,0 +1,1871 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#ifndef __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H
19#define __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H
20
21#define CTX_SHIFT 12
22
23#define GET_GLOBAL_REG(reg, base) (readl((base) + (reg)))
24#define GET_CTX_REG(reg, base, ctx) \
25 (readl((base) + (reg) + ((ctx) << CTX_SHIFT)))
26
27#define SET_GLOBAL_REG(reg, base, val) writel((val), ((base) + (reg)))
28
29#define SET_CTX_REG(reg, base, ctx, val) \
30 writel((val), ((base) + (reg) + ((ctx) << CTX_SHIFT)))
31
32/* Wrappers for numbered registers */
33#define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v))
34#define GET_GLOBAL_REG_N(b, n, r) GET_GLOBAL_REG(b, ((r) + (n << 2)))
35
36/* Field wrappers */
37#define GET_GLOBAL_FIELD(b, r, F) GET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT)
38#define GET_CONTEXT_FIELD(b, c, r, F) \
39 GET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT)
40
41#define SET_GLOBAL_FIELD(b, r, F, v) \
42 SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v))
43#define SET_CONTEXT_FIELD(b, c, r, F, v) \
44 SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v))
45
46#define GET_FIELD(addr, mask, shift) ((readl(addr) >> (shift)) & (mask))
47
48#define SET_FIELD(addr, mask, shift, v) \
49do { \
50 int t = readl(addr); \
51 writel((t & ~((mask) << (shift))) + (((v) & (mask)) << (shift)), addr);\
52} while (0)
53
54
55#define NUM_FL_PTE 4096
56#define NUM_SL_PTE 256
57
58/* First-level page table bits */
59#define FL_BASE_MASK 0xFFFFFC00
60#define FL_TYPE_TABLE (1 << 0)
61#define FL_TYPE_SECT (2 << 0)
62#define FL_SUPERSECTION (1 << 18)
63#define FL_AP_WRITE (1 << 10)
64#define FL_AP_READ (1 << 11)
65#define FL_SHARED (1 << 16)
66#define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20)
67
68/* Second-level page table bits */
69#define SL_BASE_MASK_LARGE 0xFFFF0000
70#define SL_BASE_MASK_SMALL 0xFFFFF000
71#define SL_TYPE_LARGE (1 << 0)
72#define SL_TYPE_SMALL (2 << 0)
73#define SL_AP0 (1 << 4)
74#define SL_AP1 (2 << 4)
75#define SL_SHARED (1 << 10)
76#define SL_OFFSET(va) (((va) & 0xFF000) >> 12)
77
78/* Global register setters / getters */
79#define SET_M2VCBR_N(b, N, v) SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v))
80#define SET_CBACR_N(b, N, v) SET_GLOBAL_REG_N(CBACR_N, N, (b), (v))
81#define SET_TLBRSW(b, v) SET_GLOBAL_REG(TLBRSW, (b), (v))
82#define SET_TLBTR0(b, v) SET_GLOBAL_REG(TLBTR0, (b), (v))
83#define SET_TLBTR1(b, v) SET_GLOBAL_REG(TLBTR1, (b), (v))
84#define SET_TLBTR2(b, v) SET_GLOBAL_REG(TLBTR2, (b), (v))
85#define SET_TESTBUSCR(b, v) SET_GLOBAL_REG(TESTBUSCR, (b), (v))
86#define SET_GLOBAL_TLBIALL(b, v) SET_GLOBAL_REG(GLOBAL_TLBIALL, (b), (v))
87#define SET_TLBIVMID(b, v) SET_GLOBAL_REG(TLBIVMID, (b), (v))
88#define SET_CR(b, v) SET_GLOBAL_REG(CR, (b), (v))
89#define SET_EAR(b, v) SET_GLOBAL_REG(EAR, (b), (v))
90#define SET_ESR(b, v) SET_GLOBAL_REG(ESR, (b), (v))
91#define SET_ESRRESTORE(b, v) SET_GLOBAL_REG(ESRRESTORE, (b), (v))
92#define SET_ESYNR0(b, v) SET_GLOBAL_REG(ESYNR0, (b), (v))
93#define SET_ESYNR1(b, v) SET_GLOBAL_REG(ESYNR1, (b), (v))
94#define SET_RPU_ACR(b, v) SET_GLOBAL_REG(RPU_ACR, (b), (v))
95
96#define GET_M2VCBR_N(b, N) GET_GLOBAL_REG_N(M2VCBR_N, N, (b))
97#define GET_CBACR_N(b, N) GET_GLOBAL_REG_N(CBACR_N, N, (b))
98#define GET_TLBTR0(b) GET_GLOBAL_REG(TLBTR0, (b))
99#define GET_TLBTR1(b) GET_GLOBAL_REG(TLBTR1, (b))
100#define GET_TLBTR2(b) GET_GLOBAL_REG(TLBTR2, (b))
101#define GET_TESTBUSCR(b) GET_GLOBAL_REG(TESTBUSCR, (b))
102#define GET_GLOBAL_TLBIALL(b) GET_GLOBAL_REG(GLOBAL_TLBIALL, (b))
103#define GET_TLBIVMID(b) GET_GLOBAL_REG(TLBIVMID, (b))
104#define GET_CR(b) GET_GLOBAL_REG(CR, (b))
105#define GET_EAR(b) GET_GLOBAL_REG(EAR, (b))
106#define GET_ESR(b) GET_GLOBAL_REG(ESR, (b))
107#define GET_ESRRESTORE(b) GET_GLOBAL_REG(ESRRESTORE, (b))
108#define GET_ESYNR0(b) GET_GLOBAL_REG(ESYNR0, (b))
109#define GET_ESYNR1(b) GET_GLOBAL_REG(ESYNR1, (b))
110#define GET_REV(b) GET_GLOBAL_REG(REV, (b))
111#define GET_IDR(b) GET_GLOBAL_REG(IDR, (b))
112#define GET_RPU_ACR(b) GET_GLOBAL_REG(RPU_ACR, (b))
113
114
115/* Context register setters/getters */
116#define SET_SCTLR(b, c, v) SET_CTX_REG(SCTLR, (b), (c), (v))
117#define SET_ACTLR(b, c, v) SET_CTX_REG(ACTLR, (b), (c), (v))
118#define SET_CONTEXTIDR(b, c, v) SET_CTX_REG(CONTEXTIDR, (b), (c), (v))
119#define SET_TTBR0(b, c, v) SET_CTX_REG(TTBR0, (b), (c), (v))
120#define SET_TTBR1(b, c, v) SET_CTX_REG(TTBR1, (b), (c), (v))
121#define SET_TTBCR(b, c, v) SET_CTX_REG(TTBCR, (b), (c), (v))
122#define SET_PAR(b, c, v) SET_CTX_REG(PAR, (b), (c), (v))
123#define SET_FSR(b, c, v) SET_CTX_REG(FSR, (b), (c), (v))
124#define SET_FSRRESTORE(b, c, v) SET_CTX_REG(FSRRESTORE, (b), (c), (v))
125#define SET_FAR(b, c, v) SET_CTX_REG(FAR, (b), (c), (v))
126#define SET_FSYNR0(b, c, v) SET_CTX_REG(FSYNR0, (b), (c), (v))
127#define SET_FSYNR1(b, c, v) SET_CTX_REG(FSYNR1, (b), (c), (v))
128#define SET_PRRR(b, c, v) SET_CTX_REG(PRRR, (b), (c), (v))
129#define SET_NMRR(b, c, v) SET_CTX_REG(NMRR, (b), (c), (v))
130#define SET_TLBLKCR(b, c, v) SET_CTX_REG(TLBLCKR, (b), (c), (v))
131#define SET_V2PSR(b, c, v) SET_CTX_REG(V2PSR, (b), (c), (v))
132#define SET_TLBFLPTER(b, c, v) SET_CTX_REG(TLBFLPTER, (b), (c), (v))
133#define SET_TLBSLPTER(b, c, v) SET_CTX_REG(TLBSLPTER, (b), (c), (v))
134#define SET_BFBCR(b, c, v) SET_CTX_REG(BFBCR, (b), (c), (v))
135#define SET_CTX_TLBIALL(b, c, v) SET_CTX_REG(CTX_TLBIALL, (b), (c), (v))
136#define SET_TLBIASID(b, c, v) SET_CTX_REG(TLBIASID, (b), (c), (v))
137#define SET_TLBIVA(b, c, v) SET_CTX_REG(TLBIVA, (b), (c), (v))
138#define SET_TLBIVAA(b, c, v) SET_CTX_REG(TLBIVAA, (b), (c), (v))
139#define SET_V2PPR(b, c, v) SET_CTX_REG(V2PPR, (b), (c), (v))
140#define SET_V2PPW(b, c, v) SET_CTX_REG(V2PPW, (b), (c), (v))
141#define SET_V2PUR(b, c, v) SET_CTX_REG(V2PUR, (b), (c), (v))
142#define SET_V2PUW(b, c, v) SET_CTX_REG(V2PUW, (b), (c), (v))
143#define SET_RESUME(b, c, v) SET_CTX_REG(RESUME, (b), (c), (v))
144
145#define GET_SCTLR(b, c) GET_CTX_REG(SCTLR, (b), (c))
146#define GET_ACTLR(b, c) GET_CTX_REG(ACTLR, (b), (c))
147#define GET_CONTEXTIDR(b, c) GET_CTX_REG(CONTEXTIDR, (b), (c))
148#define GET_TTBR0(b, c) GET_CTX_REG(TTBR0, (b), (c))
149#define GET_TTBR1(b, c) GET_CTX_REG(TTBR1, (b), (c))
150#define GET_TTBCR(b, c) GET_CTX_REG(TTBCR, (b), (c))
151#define GET_PAR(b, c) GET_CTX_REG(PAR, (b), (c))
152#define GET_FSR(b, c) GET_CTX_REG(FSR, (b), (c))
153#define GET_FSRRESTORE(b, c) GET_CTX_REG(FSRRESTORE, (b), (c))
154#define GET_FAR(b, c) GET_CTX_REG(FAR, (b), (c))
155#define GET_FSYNR0(b, c) GET_CTX_REG(FSYNR0, (b), (c))
156#define GET_FSYNR1(b, c) GET_CTX_REG(FSYNR1, (b), (c))
157#define GET_PRRR(b, c) GET_CTX_REG(PRRR, (b), (c))
158#define GET_NMRR(b, c) GET_CTX_REG(NMRR, (b), (c))
159#define GET_TLBLCKR(b, c) GET_CTX_REG(TLBLCKR, (b), (c))
160#define GET_V2PSR(b, c) GET_CTX_REG(V2PSR, (b), (c))
161#define GET_TLBFLPTER(b, c) GET_CTX_REG(TLBFLPTER, (b), (c))
162#define GET_TLBSLPTER(b, c) GET_CTX_REG(TLBSLPTER, (b), (c))
163#define GET_BFBCR(b, c) GET_CTX_REG(BFBCR, (b), (c))
164#define GET_CTX_TLBIALL(b, c) GET_CTX_REG(CTX_TLBIALL, (b), (c))
165#define GET_TLBIASID(b, c) GET_CTX_REG(TLBIASID, (b), (c))
166#define GET_TLBIVA(b, c) GET_CTX_REG(TLBIVA, (b), (c))
167#define GET_TLBIVAA(b, c) GET_CTX_REG(TLBIVAA, (b), (c))
168#define GET_V2PPR(b, c) GET_CTX_REG(V2PPR, (b), (c))
169#define GET_V2PPW(b, c) GET_CTX_REG(V2PPW, (b), (c))
170#define GET_V2PUR(b, c) GET_CTX_REG(V2PUR, (b), (c))
171#define GET_V2PUW(b, c) GET_CTX_REG(V2PUW, (b), (c))
172#define GET_RESUME(b, c) GET_CTX_REG(RESUME, (b), (c))
173
174
175/* Global field setters / getters */
176/* Global Field Setters: */
177/* CBACR_N */
178#define SET_RWVMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWVMID, v)
179#define SET_RWE(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWE, v)
180#define SET_RWGE(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWGE, v)
181#define SET_CBVMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), CBVMID, v)
182#define SET_IRPTNDX(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), IRPTNDX, v)
183
184
185/* M2VCBR_N */
186#define SET_VMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID, v)
187#define SET_CBNDX(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), CBNDX, v)
188#define SET_BYPASSD(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BYPASSD, v)
189#define SET_BPRCOSH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCOSH, v)
190#define SET_BPRCISH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCISH, v)
191#define SET_BPRCNSH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCNSH, v)
192#define SET_BPSHCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPSHCFG, v)
193#define SET_NSCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), NSCFG, v)
194#define SET_BPMTCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMTCFG, v)
195#define SET_BPMEMTYPE(b, n, v) \
196 SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMEMTYPE, v)
197
198
199/* CR */
200#define SET_RPUE(b, v) SET_GLOBAL_FIELD(b, CR, RPUE, v)
201#define SET_RPUERE(b, v) SET_GLOBAL_FIELD(b, CR, RPUERE, v)
202#define SET_RPUEIE(b, v) SET_GLOBAL_FIELD(b, CR, RPUEIE, v)
203#define SET_DCDEE(b, v) SET_GLOBAL_FIELD(b, CR, DCDEE, v)
204#define SET_CLIENTPD(b, v) SET_GLOBAL_FIELD(b, CR, CLIENTPD, v)
205#define SET_STALLD(b, v) SET_GLOBAL_FIELD(b, CR, STALLD, v)
206#define SET_TLBLKCRWE(b, v) SET_GLOBAL_FIELD(b, CR, TLBLKCRWE, v)
207#define SET_CR_TLBIALLCFG(b, v) SET_GLOBAL_FIELD(b, CR, CR_TLBIALLCFG, v)
208#define SET_TLBIVMIDCFG(b, v) SET_GLOBAL_FIELD(b, CR, TLBIVMIDCFG, v)
209#define SET_CR_HUME(b, v) SET_GLOBAL_FIELD(b, CR, CR_HUME, v)
210
211
212/* ESR */
213#define SET_CFG(b, v) SET_GLOBAL_FIELD(b, ESR, CFG, v)
214#define SET_BYPASS(b, v) SET_GLOBAL_FIELD(b, ESR, BYPASS, v)
215#define SET_ESR_MULTI(b, v) SET_GLOBAL_FIELD(b, ESR, ESR_MULTI, v)
216
217
218/* ESYNR0 */
219#define SET_ESYNR0_AMID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AMID, v)
220#define SET_ESYNR0_APID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_APID, v)
221#define SET_ESYNR0_ABID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ABID, v)
222#define SET_ESYNR0_AVMID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AVMID, v)
223#define SET_ESYNR0_ATID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ATID, v)
224
225
226/* ESYNR1 */
227#define SET_ESYNR1_AMEMTYPE(b, v) \
228 SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AMEMTYPE, v)
229#define SET_ESYNR1_ASHARED(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASHARED, v)
230#define SET_ESYNR1_AINNERSHARED(b, v) \
231 SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINNERSHARED, v)
232#define SET_ESYNR1_APRIV(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APRIV, v)
233#define SET_ESYNR1_APROTNS(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APROTNS, v)
234#define SET_ESYNR1_AINST(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINST, v)
235#define SET_ESYNR1_AWRITE(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AWRITE, v)
236#define SET_ESYNR1_ABURST(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ABURST, v)
237#define SET_ESYNR1_ALEN(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALEN, v)
238#define SET_ESYNR1_ASIZE(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASIZE, v)
239#define SET_ESYNR1_ALOCK(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALOCK, v)
240#define SET_ESYNR1_AOOO(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AOOO, v)
241#define SET_ESYNR1_AFULL(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AFULL, v)
242#define SET_ESYNR1_AC(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AC, v)
243#define SET_ESYNR1_DCD(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_DCD, v)
244
245
246/* TESTBUSCR */
247#define SET_TBE(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBE, v)
248#define SET_SPDMBE(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDMBE, v)
249#define SET_WGSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, WGSEL, v)
250#define SET_TBLSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBLSEL, v)
251#define SET_TBHSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBHSEL, v)
252#define SET_SPDM0SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM0SEL, v)
253#define SET_SPDM1SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM1SEL, v)
254#define SET_SPDM2SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM2SEL, v)
255#define SET_SPDM3SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM3SEL, v)
256
257
258/* TLBIVMID */
259#define SET_TLBIVMID_VMID(b, v) SET_GLOBAL_FIELD(b, TLBIVMID, TLBIVMID_VMID, v)
260
261
262/* TLBRSW */
263#define SET_TLBRSW_INDEX(b, v) SET_GLOBAL_FIELD(b, TLBRSW, TLBRSW_INDEX, v)
264#define SET_TLBBFBS(b, v) SET_GLOBAL_FIELD(b, TLBRSW, TLBBFBS, v)
265
266
267/* TLBTR0 */
268#define SET_PR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, PR, v)
269#define SET_PW(b, v) SET_GLOBAL_FIELD(b, TLBTR0, PW, v)
270#define SET_UR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, UR, v)
271#define SET_UW(b, v) SET_GLOBAL_FIELD(b, TLBTR0, UW, v)
272#define SET_XN(b, v) SET_GLOBAL_FIELD(b, TLBTR0, XN, v)
273#define SET_NSDESC(b, v) SET_GLOBAL_FIELD(b, TLBTR0, NSDESC, v)
274#define SET_ISH(b, v) SET_GLOBAL_FIELD(b, TLBTR0, ISH, v)
275#define SET_SH(b, v) SET_GLOBAL_FIELD(b, TLBTR0, SH, v)
276#define SET_MT(b, v) SET_GLOBAL_FIELD(b, TLBTR0, MT, v)
277#define SET_DPSIZR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, DPSIZR, v)
278#define SET_DPSIZC(b, v) SET_GLOBAL_FIELD(b, TLBTR0, DPSIZC, v)
279
280
281/* TLBTR1 */
282#define SET_TLBTR1_VMID(b, v) SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_VMID, v)
283#define SET_TLBTR1_PA(b, v) SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_PA, v)
284
285
286/* TLBTR2 */
287#define SET_TLBTR2_ASID(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_ASID, v)
288#define SET_TLBTR2_V(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_V, v)
289#define SET_TLBTR2_NSTID(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NSTID, v)
290#define SET_TLBTR2_NV(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NV, v)
291#define SET_TLBTR2_VA(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_VA, v)
292
293
294/* Global Field Getters */
295/* CBACR_N */
296#define GET_RWVMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWVMID)
297#define GET_RWE(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWE)
298#define GET_RWGE(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWGE)
299#define GET_CBVMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), CBVMID)
300#define GET_IRPTNDX(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), IRPTNDX)
301
302
303/* M2VCBR_N */
304#define GET_VMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID)
305#define GET_CBNDX(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), CBNDX)
306#define GET_BYPASSD(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BYPASSD)
307#define GET_BPRCOSH(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCOSH)
308#define GET_BPRCISH(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCISH)
309#define GET_BPRCNSH(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCNSH)
310#define GET_BPSHCFG(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPSHCFG)
311#define GET_NSCFG(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), NSCFG)
312#define GET_BPMTCFG(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMTCFG)
313#define GET_BPMEMTYPE(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMEMTYPE)
314
315
316/* CR */
317#define GET_RPUE(b) GET_GLOBAL_FIELD(b, CR, RPUE)
318#define GET_RPUERE(b) GET_GLOBAL_FIELD(b, CR, RPUERE)
319#define GET_RPUEIE(b) GET_GLOBAL_FIELD(b, CR, RPUEIE)
320#define GET_DCDEE(b) GET_GLOBAL_FIELD(b, CR, DCDEE)
321#define GET_CLIENTPD(b) GET_GLOBAL_FIELD(b, CR, CLIENTPD)
322#define GET_STALLD(b) GET_GLOBAL_FIELD(b, CR, STALLD)
323#define GET_TLBLKCRWE(b) GET_GLOBAL_FIELD(b, CR, TLBLKCRWE)
324#define GET_CR_TLBIALLCFG(b) GET_GLOBAL_FIELD(b, CR, CR_TLBIALLCFG)
325#define GET_TLBIVMIDCFG(b) GET_GLOBAL_FIELD(b, CR, TLBIVMIDCFG)
326#define GET_CR_HUME(b) GET_GLOBAL_FIELD(b, CR, CR_HUME)
327
328
329/* ESR */
330#define GET_CFG(b) GET_GLOBAL_FIELD(b, ESR, CFG)
331#define GET_BYPASS(b) GET_GLOBAL_FIELD(b, ESR, BYPASS)
332#define GET_ESR_MULTI(b) GET_GLOBAL_FIELD(b, ESR, ESR_MULTI)
333
334
335/* ESYNR0 */
336#define GET_ESYNR0_AMID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AMID)
337#define GET_ESYNR0_APID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_APID)
338#define GET_ESYNR0_ABID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ABID)
339#define GET_ESYNR0_AVMID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AVMID)
340#define GET_ESYNR0_ATID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ATID)
341
342
343/* ESYNR1 */
344#define GET_ESYNR1_AMEMTYPE(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AMEMTYPE)
345#define GET_ESYNR1_ASHARED(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASHARED)
346#define GET_ESYNR1_AINNERSHARED(b) \
347 GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINNERSHARED)
348#define GET_ESYNR1_APRIV(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APRIV)
349#define GET_ESYNR1_APROTNS(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APROTNS)
350#define GET_ESYNR1_AINST(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINST)
351#define GET_ESYNR1_AWRITE(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AWRITE)
352#define GET_ESYNR1_ABURST(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ABURST)
353#define GET_ESYNR1_ALEN(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALEN)
354#define GET_ESYNR1_ASIZE(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASIZE)
355#define GET_ESYNR1_ALOCK(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALOCK)
356#define GET_ESYNR1_AOOO(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AOOO)
357#define GET_ESYNR1_AFULL(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AFULL)
358#define GET_ESYNR1_AC(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AC)
359#define GET_ESYNR1_DCD(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_DCD)
360
361
362/* IDR */
363#define GET_NM2VCBMT(b) GET_GLOBAL_FIELD(b, IDR, NM2VCBMT)
364#define GET_HTW(b) GET_GLOBAL_FIELD(b, IDR, HTW)
365#define GET_HUM(b) GET_GLOBAL_FIELD(b, IDR, HUM)
366#define GET_TLBSIZE(b) GET_GLOBAL_FIELD(b, IDR, TLBSIZE)
367#define GET_NCB(b) GET_GLOBAL_FIELD(b, IDR, NCB)
368#define GET_NIRPT(b) GET_GLOBAL_FIELD(b, IDR, NIRPT)
369
370
371/* REV */
372#define GET_MAJOR(b) GET_GLOBAL_FIELD(b, REV, MAJOR)
373#define GET_MINOR(b) GET_GLOBAL_FIELD(b, REV, MINOR)
374
375
376/* TESTBUSCR */
377#define GET_TBE(b) GET_GLOBAL_FIELD(b, TESTBUSCR, TBE)
378#define GET_SPDMBE(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDMBE)
379#define GET_WGSEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, WGSEL)
380#define GET_TBLSEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, TBLSEL)
381#define GET_TBHSEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, TBHSEL)
382#define GET_SPDM0SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM0SEL)
383#define GET_SPDM1SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM1SEL)
384#define GET_SPDM2SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM2SEL)
385#define GET_SPDM3SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM3SEL)
386
387
388/* TLBIVMID */
389#define GET_TLBIVMID_VMID(b) GET_GLOBAL_FIELD(b, TLBIVMID, TLBIVMID_VMID)
390
391
392/* TLBTR0 */
393#define GET_PR(b) GET_GLOBAL_FIELD(b, TLBTR0, PR)
394#define GET_PW(b) GET_GLOBAL_FIELD(b, TLBTR0, PW)
395#define GET_UR(b) GET_GLOBAL_FIELD(b, TLBTR0, UR)
396#define GET_UW(b) GET_GLOBAL_FIELD(b, TLBTR0, UW)
397#define GET_XN(b) GET_GLOBAL_FIELD(b, TLBTR0, XN)
398#define GET_NSDESC(b) GET_GLOBAL_FIELD(b, TLBTR0, NSDESC)
399#define GET_ISH(b) GET_GLOBAL_FIELD(b, TLBTR0, ISH)
400#define GET_SH(b) GET_GLOBAL_FIELD(b, TLBTR0, SH)
401#define GET_MT(b) GET_GLOBAL_FIELD(b, TLBTR0, MT)
402#define GET_DPSIZR(b) GET_GLOBAL_FIELD(b, TLBTR0, DPSIZR)
403#define GET_DPSIZC(b) GET_GLOBAL_FIELD(b, TLBTR0, DPSIZC)
404
405
406/* TLBTR1 */
407#define GET_TLBTR1_VMID(b) GET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_VMID)
408#define GET_TLBTR1_PA(b) GET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_PA)
409
410
411/* TLBTR2 */
412#define GET_TLBTR2_ASID(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_ASID)
413#define GET_TLBTR2_V(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_V)
414#define GET_TLBTR2_NSTID(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NSTID)
415#define GET_TLBTR2_NV(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NV)
416#define GET_TLBTR2_VA(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_VA)
417
418
419/* Context Register setters / getters */
420/* Context Register setters */
421/* ACTLR */
422#define SET_CFERE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFERE, v)
423#define SET_CFEIE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFEIE, v)
424#define SET_PTSHCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTSHCFG, v)
425#define SET_RCOSH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCOSH, v)
426#define SET_RCISH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCISH, v)
427#define SET_RCNSH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCNSH, v)
428#define SET_PRIVCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PRIVCFG, v)
429#define SET_DNA(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, DNA, v)
430#define SET_DNLV2PA(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, DNLV2PA, v)
431#define SET_TLBMCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, TLBMCFG, v)
432#define SET_CFCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFCFG, v)
433#define SET_TIPCF(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, TIPCF, v)
434#define SET_V2PCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, V2PCFG, v)
435#define SET_HUME(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, HUME, v)
436#define SET_PTMTCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTMTCFG, v)
437#define SET_PTMEMTYPE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTMEMTYPE, v)
438
439
440/* BFBCR */
441#define SET_BFBDFE(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, BFBDFE, v)
442#define SET_BFBSFE(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, BFBSFE, v)
443#define SET_SFVS(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, SFVS, v)
444#define SET_FLVIC(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, FLVIC, v)
445#define SET_SLVIC(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, SLVIC, v)
446
447
448/* CONTEXTIDR */
449#define SET_CONTEXTIDR_ASID(b, c, v) \
450 SET_CONTEXT_FIELD(b, c, CONTEXTIDR, CONTEXTIDR_ASID, v)
451#define SET_CONTEXTIDR_PROCID(b, c, v) \
452 SET_CONTEXT_FIELD(b, c, CONTEXTIDR, PROCID, v)
453
454
455/* FSR */
456#define SET_TF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, TF, v)
457#define SET_AFF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, AFF, v)
458#define SET_APF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, APF, v)
459#define SET_TLBMF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, TLBMF, v)
460#define SET_HTWDEEF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, HTWDEEF, v)
461#define SET_HTWSEEF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, HTWSEEF, v)
462#define SET_MHF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, MHF, v)
463#define SET_SL(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, SL, v)
464#define SET_SS(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, SS, v)
465#define SET_MULTI(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, MULTI, v)
466
467
468/* FSYNR0 */
469#define SET_AMID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, AMID, v)
470#define SET_APID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, APID, v)
471#define SET_ABID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, ABID, v)
472#define SET_ATID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, ATID, v)
473
474
475/* FSYNR1 */
476#define SET_AMEMTYPE(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AMEMTYPE, v)
477#define SET_ASHARED(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ASHARED, v)
478#define SET_AINNERSHARED(b, c, v) \
479 SET_CONTEXT_FIELD(b, c, FSYNR1, AINNERSHARED, v)
480#define SET_APRIV(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, APRIV, v)
481#define SET_APROTNS(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, APROTNS, v)
482#define SET_AINST(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AINST, v)
483#define SET_AWRITE(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AWRITE, v)
484#define SET_ABURST(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ABURST, v)
485#define SET_ALEN(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ALEN, v)
486#define SET_FSYNR1_ASIZE(b, c, v) \
487 SET_CONTEXT_FIELD(b, c, FSYNR1, FSYNR1_ASIZE, v)
488#define SET_ALOCK(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ALOCK, v)
489#define SET_AFULL(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AFULL, v)
490
491
492/* NMRR */
493#define SET_ICPC0(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC0, v)
494#define SET_ICPC1(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC1, v)
495#define SET_ICPC2(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC2, v)
496#define SET_ICPC3(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC3, v)
497#define SET_ICPC4(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC4, v)
498#define SET_ICPC5(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC5, v)
499#define SET_ICPC6(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC6, v)
500#define SET_ICPC7(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC7, v)
501#define SET_OCPC0(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC0, v)
502#define SET_OCPC1(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC1, v)
503#define SET_OCPC2(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC2, v)
504#define SET_OCPC3(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC3, v)
505#define SET_OCPC4(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC4, v)
506#define SET_OCPC5(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC5, v)
507#define SET_OCPC6(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC6, v)
508#define SET_OCPC7(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC7, v)
509
510
511/* PAR */
512#define SET_FAULT(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT, v)
513
514#define SET_FAULT_TF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_TF, v)
515#define SET_FAULT_AFF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_AFF, v)
516#define SET_FAULT_APF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_APF, v)
517#define SET_FAULT_TLBMF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_TLBMF, v)
518#define SET_FAULT_HTWDEEF(b, c, v) \
519 SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWDEEF, v)
520#define SET_FAULT_HTWSEEF(b, c, v) \
521 SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWSEEF, v)
522#define SET_FAULT_MHF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_MHF, v)
523#define SET_FAULT_SL(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_SL, v)
524#define SET_FAULT_SS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_SS, v)
525
526#define SET_NOFAULT_SS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SS, v)
527#define SET_NOFAULT_MT(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_MT, v)
528#define SET_NOFAULT_SH(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SH, v)
529#define SET_NOFAULT_NS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NS, v)
530#define SET_NOFAULT_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NOS, v)
531#define SET_NPFAULT_PA(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NPFAULT_PA, v)
532
533
534/* PRRR */
535#define SET_MTC0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC0, v)
536#define SET_MTC1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC1, v)
537#define SET_MTC2(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC2, v)
538#define SET_MTC3(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC3, v)
539#define SET_MTC4(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC4, v)
540#define SET_MTC5(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC5, v)
541#define SET_MTC6(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC6, v)
542#define SET_MTC7(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC7, v)
543#define SET_SHDSH0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHDSH0, v)
544#define SET_SHDSH1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHDSH1, v)
545#define SET_SHNMSH0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH0, v)
546#define SET_SHNMSH1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH1, v)
547#define SET_NOS0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS0, v)
548#define SET_NOS1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS1, v)
549#define SET_NOS2(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS2, v)
550#define SET_NOS3(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS3, v)
551#define SET_NOS4(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS4, v)
552#define SET_NOS5(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS5, v)
553#define SET_NOS6(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS6, v)
554#define SET_NOS7(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS7, v)
555
556
557/* RESUME */
558#define SET_TNR(b, c, v) SET_CONTEXT_FIELD(b, c, RESUME, TNR, v)
559
560
561/* SCTLR */
562#define SET_M(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, M, v)
563#define SET_TRE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, TRE, v)
564#define SET_AFE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, AFE, v)
565#define SET_HAF(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, HAF, v)
566#define SET_BE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, BE, v)
567#define SET_AFFD(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, AFFD, v)
568
569
570/* TLBLKCR */
571#define SET_LKE(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, LKE, v)
572#define SET_TLBLKCR_TLBIALLCFG(b, c, v) \
573 SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBLCKR_TLBIALLCFG, v)
574#define SET_TLBIASIDCFG(b, c, v) \
575 SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIASIDCFG, v)
576#define SET_TLBIVAACFG(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIVAACFG, v)
577#define SET_FLOOR(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, FLOOR, v)
578#define SET_VICTIM(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, VICTIM, v)
579
580
581/* TTBCR */
582#define SET_N(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, N, v)
583#define SET_PD0(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, PD0, v)
584#define SET_PD1(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, PD1, v)
585
586
587/* TTBR0 */
588#define SET_TTBR0_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNH, v)
589#define SET_TTBR0_SH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_SH, v)
590#define SET_TTBR0_ORGN(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_ORGN, v)
591#define SET_TTBR0_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_NOS, v)
592#define SET_TTBR0_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNL, v)
593#define SET_TTBR0_PA(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_PA, v)
594
595
596/* TTBR1 */
597#define SET_TTBR1_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNH, v)
598#define SET_TTBR1_SH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_SH, v)
599#define SET_TTBR1_ORGN(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_ORGN, v)
600#define SET_TTBR1_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_NOS, v)
601#define SET_TTBR1_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNL, v)
602#define SET_TTBR1_PA(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_PA, v)
603
604
605/* V2PSR */
606#define SET_HIT(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, HIT, v)
607#define SET_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, INDEX, v)
608
609
610/* V2Pxx UW UR PW PR */
611#define SET_V2PUW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX, v)
612#define SET_V2PUW_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA, v)
613
614#define SET_V2PUR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX, v)
615#define SET_V2PUR_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA, v)
616
617#define SET_V2PPW_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX, v)
618#define SET_V2PPW_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA, v)
619
620#define SET_V2PPR_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX, v)
621#define SET_V2PPR_VA(b, c, v) SET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA, v)
622
623
624/* Context Register getters */
625/* ACTLR */
626#define GET_CFERE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFERE)
627#define GET_CFEIE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFEIE)
628#define GET_PTSHCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PTSHCFG)
629#define GET_RCOSH(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, RCOSH)
630#define GET_RCISH(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, RCISH)
631#define GET_RCNSH(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, RCNSH)
632#define GET_PRIVCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PRIVCFG)
633#define GET_DNA(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, DNA)
634#define GET_DNLV2PA(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, DNLV2PA)
635#define GET_TLBMCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, TLBMCFG)
636#define GET_CFCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFCFG)
637#define GET_TIPCF(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, TIPCF)
638#define GET_V2PCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, V2PCFG)
639#define GET_HUME(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, HUME)
640#define GET_PTMTCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PTMTCFG)
641#define GET_PTMEMTYPE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PTMEMTYPE)
642
643/* BFBCR */
644#define GET_BFBDFE(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, BFBDFE)
645#define GET_BFBSFE(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, BFBSFE)
646#define GET_SFVS(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, SFVS)
647#define GET_FLVIC(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, FLVIC)
648#define GET_SLVIC(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, SLVIC)
649
650
651/* CONTEXTIDR */
652#define GET_CONTEXTIDR_ASID(b, c) \
653 GET_CONTEXT_FIELD(b, c, CONTEXTIDR, CONTEXTIDR_ASID)
654#define GET_CONTEXTIDR_PROCID(b, c) GET_CONTEXT_FIELD(b, c, CONTEXTIDR, PROCID)
655
656
657/* FSR */
658#define GET_TF(b, c) GET_CONTEXT_FIELD(b, c, FSR, TF)
659#define GET_AFF(b, c) GET_CONTEXT_FIELD(b, c, FSR, AFF)
660#define GET_APF(b, c) GET_CONTEXT_FIELD(b, c, FSR, APF)
661#define GET_TLBMF(b, c) GET_CONTEXT_FIELD(b, c, FSR, TLBMF)
662#define GET_HTWDEEF(b, c) GET_CONTEXT_FIELD(b, c, FSR, HTWDEEF)
663#define GET_HTWSEEF(b, c) GET_CONTEXT_FIELD(b, c, FSR, HTWSEEF)
664#define GET_MHF(b, c) GET_CONTEXT_FIELD(b, c, FSR, MHF)
665#define GET_SL(b, c) GET_CONTEXT_FIELD(b, c, FSR, SL)
666#define GET_SS(b, c) GET_CONTEXT_FIELD(b, c, FSR, SS)
667#define GET_MULTI(b, c) GET_CONTEXT_FIELD(b, c, FSR, MULTI)
668
669
670/* FSYNR0 */
671#define GET_AMID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, AMID)
672#define GET_APID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, APID)
673#define GET_ABID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, ABID)
674#define GET_ATID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, ATID)
675
676
677/* FSYNR1 */
678#define GET_AMEMTYPE(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AMEMTYPE)
679#define GET_ASHARED(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ASHARED)
680#define GET_AINNERSHARED(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AINNERSHARED)
681#define GET_APRIV(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, APRIV)
682#define GET_APROTNS(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, APROTNS)
683#define GET_AINST(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AINST)
684#define GET_AWRITE(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AWRITE)
685#define GET_ABURST(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ABURST)
686#define GET_ALEN(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ALEN)
687#define GET_FSYNR1_ASIZE(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, FSYNR1_ASIZE)
688#define GET_ALOCK(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ALOCK)
689#define GET_AFULL(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AFULL)
690
691
692/* NMRR */
693#define GET_ICPC0(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC0)
694#define GET_ICPC1(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC1)
695#define GET_ICPC2(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC2)
696#define GET_ICPC3(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC3)
697#define GET_ICPC4(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC4)
698#define GET_ICPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC5)
699#define GET_ICPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC6)
700#define GET_ICPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC7)
701#define GET_OCPC0(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC0)
702#define GET_OCPC1(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC1)
703#define GET_OCPC2(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC2)
704#define GET_OCPC3(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC3)
705#define GET_OCPC4(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC4)
706#define GET_OCPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC5)
707#define GET_OCPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC6)
708#define GET_OCPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC7)
709
710
711/* PAR */
712#define GET_FAULT(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT)
713
714#define GET_FAULT_TF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_TF)
715#define GET_FAULT_AFF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_AFF)
716#define GET_FAULT_APF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_APF)
717#define GET_FAULT_TLBMF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_TLBMF)
718#define GET_FAULT_HTWDEEF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWDEEF)
719#define GET_FAULT_HTWSEEF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWSEEF)
720#define GET_FAULT_MHF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_MHF)
721#define GET_FAULT_SL(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_SL)
722#define GET_FAULT_SS(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_SS)
723
724#define GET_NOFAULT_SS(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_SS)
725#define GET_NOFAULT_MT(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_MT)
726#define GET_NOFAULT_SH(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_SH)
727#define GET_NOFAULT_NS(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_NS)
728#define GET_NOFAULT_NOS(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_NOS)
729#define GET_NPFAULT_PA(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NPFAULT_PA)
730
731
732/* PRRR */
733#define GET_MTC0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC0)
734#define GET_MTC1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC1)
735#define GET_MTC2(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC2)
736#define GET_MTC3(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC3)
737#define GET_MTC4(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC4)
738#define GET_MTC5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC5)
739#define GET_MTC6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC6)
740#define GET_MTC7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC7)
741#define GET_SHDSH0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHDSH0)
742#define GET_SHDSH1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHDSH1)
743#define GET_SHNMSH0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHNMSH0)
744#define GET_SHNMSH1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHNMSH1)
745#define GET_NOS0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS0)
746#define GET_NOS1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS1)
747#define GET_NOS2(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS2)
748#define GET_NOS3(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS3)
749#define GET_NOS4(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS4)
750#define GET_NOS5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS5)
751#define GET_NOS6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS6)
752#define GET_NOS7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS7)
753
754
755/* RESUME */
756#define GET_TNR(b, c) GET_CONTEXT_FIELD(b, c, RESUME, TNR)
757
758
759/* SCTLR */
760#define GET_M(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, M)
761#define GET_TRE(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, TRE)
762#define GET_AFE(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, AFE)
763#define GET_HAF(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, HAF)
764#define GET_BE(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, BE)
765#define GET_AFFD(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, AFFD)
766
767
768/* TLBLKCR */
769#define GET_LKE(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, LKE)
770#define GET_TLBLCKR_TLBIALLCFG(b, c) \
771 GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBLCKR_TLBIALLCFG)
772#define GET_TLBIASIDCFG(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIASIDCFG)
773#define GET_TLBIVAACFG(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIVAACFG)
774#define GET_FLOOR(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, FLOOR)
775#define GET_VICTIM(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, VICTIM)
776
777
778/* TTBCR */
779#define GET_N(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, N)
780#define GET_PD0(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, PD0)
781#define GET_PD1(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, PD1)
782
783
784/* TTBR0 */
785#define GET_TTBR0_IRGNH(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNH)
786#define GET_TTBR0_SH(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_SH)
787#define GET_TTBR0_ORGN(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_ORGN)
788#define GET_TTBR0_NOS(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_NOS)
789#define GET_TTBR0_IRGNL(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNL)
790#define GET_TTBR0_PA(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_PA)
791
792
793/* TTBR1 */
794#define GET_TTBR1_IRGNH(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNH)
795#define GET_TTBR1_SH(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_SH)
796#define GET_TTBR1_ORGN(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_ORGN)
797#define GET_TTBR1_NOS(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_NOS)
798#define GET_TTBR1_IRGNL(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNL)
799#define GET_TTBR1_PA(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_PA)
800
801
802/* V2PSR */
803#define GET_HIT(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, HIT)
804#define GET_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, INDEX)
805
806
807/* V2Pxx UW UR PW PR */
808#define GET_V2PUW_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_INDEX)
809#define GET_V2PUW_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PUW, V2Pxx_VA)
810
811#define GET_V2PUR_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_INDEX)
812#define GET_V2PUR_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PUR, V2Pxx_VA)
813
814#define GET_V2PPW_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_INDEX)
815#define GET_V2PPW_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PPW, V2Pxx_VA)
816
817#define GET_V2PPR_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_INDEX)
818#define GET_V2PPR_VA(b, c) GET_CONTEXT_FIELD(b, c, V2PPR, V2Pxx_VA)
819
820
821/* Global Registers */
822#define M2VCBR_N (0xFF000)
823#define CBACR_N (0xFF800)
824#define TLBRSW (0xFFE00)
825#define TLBTR0 (0xFFE80)
826#define TLBTR1 (0xFFE84)
827#define TLBTR2 (0xFFE88)
828#define TESTBUSCR (0xFFE8C)
829#define GLOBAL_TLBIALL (0xFFF00)
830#define TLBIVMID (0xFFF04)
831#define CR (0xFFF80)
832#define EAR (0xFFF84)
833#define ESR (0xFFF88)
834#define ESRRESTORE (0xFFF8C)
835#define ESYNR0 (0xFFF90)
836#define ESYNR1 (0xFFF94)
837#define REV (0xFFFF4)
838#define IDR (0xFFFF8)
839#define RPU_ACR (0xFFFFC)
840
841
842/* Context Bank Registers */
843#define SCTLR (0x000)
844#define ACTLR (0x004)
845#define CONTEXTIDR (0x008)
846#define TTBR0 (0x010)
847#define TTBR1 (0x014)
848#define TTBCR (0x018)
849#define PAR (0x01C)
850#define FSR (0x020)
851#define FSRRESTORE (0x024)
852#define FAR (0x028)
853#define FSYNR0 (0x02C)
854#define FSYNR1 (0x030)
855#define PRRR (0x034)
856#define NMRR (0x038)
857#define TLBLCKR (0x03C)
858#define V2PSR (0x040)
859#define TLBFLPTER (0x044)
860#define TLBSLPTER (0x048)
861#define BFBCR (0x04C)
862#define CTX_TLBIALL (0x800)
863#define TLBIASID (0x804)
864#define TLBIVA (0x808)
865#define TLBIVAA (0x80C)
866#define V2PPR (0x810)
867#define V2PPW (0x814)
868#define V2PUR (0x818)
869#define V2PUW (0x81C)
870#define RESUME (0x820)
871
872
873/* Global Register Fields */
874/* CBACRn */
875#define RWVMID (RWVMID_MASK << RWVMID_SHIFT)
876#define RWE (RWE_MASK << RWE_SHIFT)
877#define RWGE (RWGE_MASK << RWGE_SHIFT)
878#define CBVMID (CBVMID_MASK << CBVMID_SHIFT)
879#define IRPTNDX (IRPTNDX_MASK << IRPTNDX_SHIFT)
880
881
882/* CR */
883#define RPUE (RPUE_MASK << RPUE_SHIFT)
884#define RPUERE (RPUERE_MASK << RPUERE_SHIFT)
885#define RPUEIE (RPUEIE_MASK << RPUEIE_SHIFT)
886#define DCDEE (DCDEE_MASK << DCDEE_SHIFT)
887#define CLIENTPD (CLIENTPD_MASK << CLIENTPD_SHIFT)
888#define STALLD (STALLD_MASK << STALLD_SHIFT)
889#define TLBLKCRWE (TLBLKCRWE_MASK << TLBLKCRWE_SHIFT)
890#define CR_TLBIALLCFG (CR_TLBIALLCFG_MASK << CR_TLBIALLCFG_SHIFT)
891#define TLBIVMIDCFG (TLBIVMIDCFG_MASK << TLBIVMIDCFG_SHIFT)
892#define CR_HUME (CR_HUME_MASK << CR_HUME_SHIFT)
893
894
895/* ESR */
896#define CFG (CFG_MASK << CFG_SHIFT)
897#define BYPASS (BYPASS_MASK << BYPASS_SHIFT)
898#define ESR_MULTI (ESR_MULTI_MASK << ESR_MULTI_SHIFT)
899
900
901/* ESYNR0 */
902#define ESYNR0_AMID (ESYNR0_AMID_MASK << ESYNR0_AMID_SHIFT)
903#define ESYNR0_APID (ESYNR0_APID_MASK << ESYNR0_APID_SHIFT)
904#define ESYNR0_ABID (ESYNR0_ABID_MASK << ESYNR0_ABID_SHIFT)
905#define ESYNR0_AVMID (ESYNR0_AVMID_MASK << ESYNR0_AVMID_SHIFT)
906#define ESYNR0_ATID (ESYNR0_ATID_MASK << ESYNR0_ATID_SHIFT)
907
908
909/* ESYNR1 */
910#define ESYNR1_AMEMTYPE (ESYNR1_AMEMTYPE_MASK << ESYNR1_AMEMTYPE_SHIFT)
911#define ESYNR1_ASHARED (ESYNR1_ASHARED_MASK << ESYNR1_ASHARED_SHIFT)
912#define ESYNR1_AINNERSHARED (ESYNR1_AINNERSHARED_MASK<< \
913 ESYNR1_AINNERSHARED_SHIFT)
914#define ESYNR1_APRIV (ESYNR1_APRIV_MASK << ESYNR1_APRIV_SHIFT)
915#define ESYNR1_APROTNS (ESYNR1_APROTNS_MASK << ESYNR1_APROTNS_SHIFT)
916#define ESYNR1_AINST (ESYNR1_AINST_MASK << ESYNR1_AINST_SHIFT)
917#define ESYNR1_AWRITE (ESYNR1_AWRITE_MASK << ESYNR1_AWRITE_SHIFT)
918#define ESYNR1_ABURST (ESYNR1_ABURST_MASK << ESYNR1_ABURST_SHIFT)
919#define ESYNR1_ALEN (ESYNR1_ALEN_MASK << ESYNR1_ALEN_SHIFT)
920#define ESYNR1_ASIZE (ESYNR1_ASIZE_MASK << ESYNR1_ASIZE_SHIFT)
921#define ESYNR1_ALOCK (ESYNR1_ALOCK_MASK << ESYNR1_ALOCK_SHIFT)
922#define ESYNR1_AOOO (ESYNR1_AOOO_MASK << ESYNR1_AOOO_SHIFT)
923#define ESYNR1_AFULL (ESYNR1_AFULL_MASK << ESYNR1_AFULL_SHIFT)
924#define ESYNR1_AC (ESYNR1_AC_MASK << ESYNR1_AC_SHIFT)
925#define ESYNR1_DCD (ESYNR1_DCD_MASK << ESYNR1_DCD_SHIFT)
926
927
928/* IDR */
929#define NM2VCBMT (NM2VCBMT_MASK << NM2VCBMT_SHIFT)
930#define HTW (HTW_MASK << HTW_SHIFT)
931#define HUM (HUM_MASK << HUM_SHIFT)
932#define TLBSIZE (TLBSIZE_MASK << TLBSIZE_SHIFT)
933#define NCB (NCB_MASK << NCB_SHIFT)
934#define NIRPT (NIRPT_MASK << NIRPT_SHIFT)
935
936
937/* M2VCBRn */
938#define VMID (VMID_MASK << VMID_SHIFT)
939#define CBNDX (CBNDX_MASK << CBNDX_SHIFT)
940#define BYPASSD (BYPASSD_MASK << BYPASSD_SHIFT)
941#define BPRCOSH (BPRCOSH_MASK << BPRCOSH_SHIFT)
942#define BPRCISH (BPRCISH_MASK << BPRCISH_SHIFT)
943#define BPRCNSH (BPRCNSH_MASK << BPRCNSH_SHIFT)
944#define BPSHCFG (BPSHCFG_MASK << BPSHCFG_SHIFT)
945#define NSCFG (NSCFG_MASK << NSCFG_SHIFT)
946#define BPMTCFG (BPMTCFG_MASK << BPMTCFG_SHIFT)
947#define BPMEMTYPE (BPMEMTYPE_MASK << BPMEMTYPE_SHIFT)
948
949
950/* REV */
951#define IDR_MINOR (MINOR_MASK << MINOR_SHIFT)
952#define IDR_MAJOR (MAJOR_MASK << MAJOR_SHIFT)
953
954
955/* TESTBUSCR */
956#define TBE (TBE_MASK << TBE_SHIFT)
957#define SPDMBE (SPDMBE_MASK << SPDMBE_SHIFT)
958#define WGSEL (WGSEL_MASK << WGSEL_SHIFT)
959#define TBLSEL (TBLSEL_MASK << TBLSEL_SHIFT)
960#define TBHSEL (TBHSEL_MASK << TBHSEL_SHIFT)
961#define SPDM0SEL (SPDM0SEL_MASK << SPDM0SEL_SHIFT)
962#define SPDM1SEL (SPDM1SEL_MASK << SPDM1SEL_SHIFT)
963#define SPDM2SEL (SPDM2SEL_MASK << SPDM2SEL_SHIFT)
964#define SPDM3SEL (SPDM3SEL_MASK << SPDM3SEL_SHIFT)
965
966
967/* TLBIVMID */
968#define TLBIVMID_VMID (TLBIVMID_VMID_MASK << TLBIVMID_VMID_SHIFT)
969
970
971/* TLBRSW */
972#define TLBRSW_INDEX (TLBRSW_INDEX_MASK << TLBRSW_INDEX_SHIFT)
973#define TLBBFBS (TLBBFBS_MASK << TLBBFBS_SHIFT)
974
975
976/* TLBTR0 */
977#define PR (PR_MASK << PR_SHIFT)
978#define PW (PW_MASK << PW_SHIFT)
979#define UR (UR_MASK << UR_SHIFT)
980#define UW (UW_MASK << UW_SHIFT)
981#define XN (XN_MASK << XN_SHIFT)
982#define NSDESC (NSDESC_MASK << NSDESC_SHIFT)
983#define ISH (ISH_MASK << ISH_SHIFT)
984#define SH (SH_MASK << SH_SHIFT)
985#define MT (MT_MASK << MT_SHIFT)
986#define DPSIZR (DPSIZR_MASK << DPSIZR_SHIFT)
987#define DPSIZC (DPSIZC_MASK << DPSIZC_SHIFT)
988
989
990/* TLBTR1 */
991#define TLBTR1_VMID (TLBTR1_VMID_MASK << TLBTR1_VMID_SHIFT)
992#define TLBTR1_PA (TLBTR1_PA_MASK << TLBTR1_PA_SHIFT)
993
994
995/* TLBTR2 */
996#define TLBTR2_ASID (TLBTR2_ASID_MASK << TLBTR2_ASID_SHIFT)
997#define TLBTR2_V (TLBTR2_V_MASK << TLBTR2_V_SHIFT)
998#define TLBTR2_NSTID (TLBTR2_NSTID_MASK << TLBTR2_NSTID_SHIFT)
999#define TLBTR2_NV (TLBTR2_NV_MASK << TLBTR2_NV_SHIFT)
1000#define TLBTR2_VA (TLBTR2_VA_MASK << TLBTR2_VA_SHIFT)
1001
1002
1003/* Context Register Fields */
1004/* ACTLR */
1005#define CFERE (CFERE_MASK << CFERE_SHIFT)
1006#define CFEIE (CFEIE_MASK << CFEIE_SHIFT)
1007#define PTSHCFG (PTSHCFG_MASK << PTSHCFG_SHIFT)
1008#define RCOSH (RCOSH_MASK << RCOSH_SHIFT)
1009#define RCISH (RCISH_MASK << RCISH_SHIFT)
1010#define RCNSH (RCNSH_MASK << RCNSH_SHIFT)
1011#define PRIVCFG (PRIVCFG_MASK << PRIVCFG_SHIFT)
1012#define DNA (DNA_MASK << DNA_SHIFT)
1013#define DNLV2PA (DNLV2PA_MASK << DNLV2PA_SHIFT)
1014#define TLBMCFG (TLBMCFG_MASK << TLBMCFG_SHIFT)
1015#define CFCFG (CFCFG_MASK << CFCFG_SHIFT)
1016#define TIPCF (TIPCF_MASK << TIPCF_SHIFT)
1017#define V2PCFG (V2PCFG_MASK << V2PCFG_SHIFT)
1018#define HUME (HUME_MASK << HUME_SHIFT)
1019#define PTMTCFG (PTMTCFG_MASK << PTMTCFG_SHIFT)
1020#define PTMEMTYPE (PTMEMTYPE_MASK << PTMEMTYPE_SHIFT)
1021
1022
1023/* BFBCR */
1024#define BFBDFE (BFBDFE_MASK << BFBDFE_SHIFT)
1025#define BFBSFE (BFBSFE_MASK << BFBSFE_SHIFT)
1026#define SFVS (SFVS_MASK << SFVS_SHIFT)
1027#define FLVIC (FLVIC_MASK << FLVIC_SHIFT)
1028#define SLVIC (SLVIC_MASK << SLVIC_SHIFT)
1029
1030
1031/* CONTEXTIDR */
1032#define CONTEXTIDR_ASID (CONTEXTIDR_ASID_MASK << CONTEXTIDR_ASID_SHIFT)
1033#define PROCID (PROCID_MASK << PROCID_SHIFT)
1034
1035
1036/* FSR */
1037#define TF (TF_MASK << TF_SHIFT)
1038#define AFF (AFF_MASK << AFF_SHIFT)
1039#define APF (APF_MASK << APF_SHIFT)
1040#define TLBMF (TLBMF_MASK << TLBMF_SHIFT)
1041#define HTWDEEF (HTWDEEF_MASK << HTWDEEF_SHIFT)
1042#define HTWSEEF (HTWSEEF_MASK << HTWSEEF_SHIFT)
1043#define MHF (MHF_MASK << MHF_SHIFT)
1044#define SL (SL_MASK << SL_SHIFT)
1045#define SS (SS_MASK << SS_SHIFT)
1046#define MULTI (MULTI_MASK << MULTI_SHIFT)
1047
1048
1049/* FSYNR0 */
1050#define AMID (AMID_MASK << AMID_SHIFT)
1051#define APID (APID_MASK << APID_SHIFT)
1052#define ABID (ABID_MASK << ABID_SHIFT)
1053#define ATID (ATID_MASK << ATID_SHIFT)
1054
1055
1056/* FSYNR1 */
1057#define AMEMTYPE (AMEMTYPE_MASK << AMEMTYPE_SHIFT)
1058#define ASHARED (ASHARED_MASK << ASHARED_SHIFT)
1059#define AINNERSHARED (AINNERSHARED_MASK << AINNERSHARED_SHIFT)
1060#define APRIV (APRIV_MASK << APRIV_SHIFT)
1061#define APROTNS (APROTNS_MASK << APROTNS_SHIFT)
1062#define AINST (AINST_MASK << AINST_SHIFT)
1063#define AWRITE (AWRITE_MASK << AWRITE_SHIFT)
1064#define ABURST (ABURST_MASK << ABURST_SHIFT)
1065#define ALEN (ALEN_MASK << ALEN_SHIFT)
1066#define FSYNR1_ASIZE (FSYNR1_ASIZE_MASK << FSYNR1_ASIZE_SHIFT)
1067#define ALOCK (ALOCK_MASK << ALOCK_SHIFT)
1068#define AFULL (AFULL_MASK << AFULL_SHIFT)
1069
1070
1071/* NMRR */
1072#define ICPC0 (ICPC0_MASK << ICPC0_SHIFT)
1073#define ICPC1 (ICPC1_MASK << ICPC1_SHIFT)
1074#define ICPC2 (ICPC2_MASK << ICPC2_SHIFT)
1075#define ICPC3 (ICPC3_MASK << ICPC3_SHIFT)
1076#define ICPC4 (ICPC4_MASK << ICPC4_SHIFT)
1077#define ICPC5 (ICPC5_MASK << ICPC5_SHIFT)
1078#define ICPC6 (ICPC6_MASK << ICPC6_SHIFT)
1079#define ICPC7 (ICPC7_MASK << ICPC7_SHIFT)
1080#define OCPC0 (OCPC0_MASK << OCPC0_SHIFT)
1081#define OCPC1 (OCPC1_MASK << OCPC1_SHIFT)
1082#define OCPC2 (OCPC2_MASK << OCPC2_SHIFT)
1083#define OCPC3 (OCPC3_MASK << OCPC3_SHIFT)
1084#define OCPC4 (OCPC4_MASK << OCPC4_SHIFT)
1085#define OCPC5 (OCPC5_MASK << OCPC5_SHIFT)
1086#define OCPC6 (OCPC6_MASK << OCPC6_SHIFT)
1087#define OCPC7 (OCPC7_MASK << OCPC7_SHIFT)
1088
1089
1090/* PAR */
1091#define FAULT (FAULT_MASK << FAULT_SHIFT)
1092/* If a fault is present, these are the
1093same as the fault fields in the FAR */
1094#define FAULT_TF (FAULT_TF_MASK << FAULT_TF_SHIFT)
1095#define FAULT_AFF (FAULT_AFF_MASK << FAULT_AFF_SHIFT)
1096#define FAULT_APF (FAULT_APF_MASK << FAULT_APF_SHIFT)
1097#define FAULT_TLBMF (FAULT_TLBMF_MASK << FAULT_TLBMF_SHIFT)
1098#define FAULT_HTWDEEF (FAULT_HTWDEEF_MASK << FAULT_HTWDEEF_SHIFT)
1099#define FAULT_HTWSEEF (FAULT_HTWSEEF_MASK << FAULT_HTWSEEF_SHIFT)
1100#define FAULT_MHF (FAULT_MHF_MASK << FAULT_MHF_SHIFT)
1101#define FAULT_SL (FAULT_SL_MASK << FAULT_SL_SHIFT)
1102#define FAULT_SS (FAULT_SS_MASK << FAULT_SS_SHIFT)
1103
1104/* If NO fault is present, the following fields are in effect */
1105/* (FAULT remains as before) */
1106#define PAR_NOFAULT_SS (PAR_NOFAULT_SS_MASK << PAR_NOFAULT_SS_SHIFT)
1107#define PAR_NOFAULT_MT (PAR_NOFAULT_MT_MASK << PAR_NOFAULT_MT_SHIFT)
1108#define PAR_NOFAULT_SH (PAR_NOFAULT_SH_MASK << PAR_NOFAULT_SH_SHIFT)
1109#define PAR_NOFAULT_NS (PAR_NOFAULT_NS_MASK << PAR_NOFAULT_NS_SHIFT)
1110#define PAR_NOFAULT_NOS (PAR_NOFAULT_NOS_MASK << PAR_NOFAULT_NOS_SHIFT)
1111#define PAR_NPFAULT_PA (PAR_NPFAULT_PA_MASK << PAR_NPFAULT_PA_SHIFT)
1112
1113
1114/* PRRR */
1115#define MTC0 (MTC0_MASK << MTC0_SHIFT)
1116#define MTC1 (MTC1_MASK << MTC1_SHIFT)
1117#define MTC2 (MTC2_MASK << MTC2_SHIFT)
1118#define MTC3 (MTC3_MASK << MTC3_SHIFT)
1119#define MTC4 (MTC4_MASK << MTC4_SHIFT)
1120#define MTC5 (MTC5_MASK << MTC5_SHIFT)
1121#define MTC6 (MTC6_MASK << MTC6_SHIFT)
1122#define MTC7 (MTC7_MASK << MTC7_SHIFT)
1123#define SHDSH0 (SHDSH0_MASK << SHDSH0_SHIFT)
1124#define SHDSH1 (SHDSH1_MASK << SHDSH1_SHIFT)
1125#define SHNMSH0 (SHNMSH0_MASK << SHNMSH0_SHIFT)
1126#define SHNMSH1 (SHNMSH1_MASK << SHNMSH1_SHIFT)
1127#define NOS0 (NOS0_MASK << NOS0_SHIFT)
1128#define NOS1 (NOS1_MASK << NOS1_SHIFT)
1129#define NOS2 (NOS2_MASK << NOS2_SHIFT)
1130#define NOS3 (NOS3_MASK << NOS3_SHIFT)
1131#define NOS4 (NOS4_MASK << NOS4_SHIFT)
1132#define NOS5 (NOS5_MASK << NOS5_SHIFT)
1133#define NOS6 (NOS6_MASK << NOS6_SHIFT)
1134#define NOS7 (NOS7_MASK << NOS7_SHIFT)
1135
1136
1137/* RESUME */
1138#define TNR (TNR_MASK << TNR_SHIFT)
1139
1140
1141/* SCTLR */
1142#define M (M_MASK << M_SHIFT)
1143#define TRE (TRE_MASK << TRE_SHIFT)
1144#define AFE (AFE_MASK << AFE_SHIFT)
1145#define HAF (HAF_MASK << HAF_SHIFT)
1146#define BE (BE_MASK << BE_SHIFT)
1147#define AFFD (AFFD_MASK << AFFD_SHIFT)
1148
1149
1150/* TLBIASID */
1151#define TLBIASID_ASID (TLBIASID_ASID_MASK << TLBIASID_ASID_SHIFT)
1152
1153
1154/* TLBIVA */
1155#define TLBIVA_ASID (TLBIVA_ASID_MASK << TLBIVA_ASID_SHIFT)
1156#define TLBIVA_VA (TLBIVA_VA_MASK << TLBIVA_VA_SHIFT)
1157
1158
1159/* TLBIVAA */
1160#define TLBIVAA_VA (TLBIVAA_VA_MASK << TLBIVAA_VA_SHIFT)
1161
1162
1163/* TLBLCKR */
1164#define LKE (LKE_MASK << LKE_SHIFT)
1165#define TLBLCKR_TLBIALLCFG (TLBLCKR_TLBIALLCFG_MASK<<TLBLCKR_TLBIALLCFG_SHIFT)
1166#define TLBIASIDCFG (TLBIASIDCFG_MASK << TLBIASIDCFG_SHIFT)
1167#define TLBIVAACFG (TLBIVAACFG_MASK << TLBIVAACFG_SHIFT)
1168#define FLOOR (FLOOR_MASK << FLOOR_SHIFT)
1169#define VICTIM (VICTIM_MASK << VICTIM_SHIFT)
1170
1171
1172/* TTBCR */
1173#define N (N_MASK << N_SHIFT)
1174#define PD0 (PD0_MASK << PD0_SHIFT)
1175#define PD1 (PD1_MASK << PD1_SHIFT)
1176
1177
1178/* TTBR0 */
1179#define TTBR0_IRGNH (TTBR0_IRGNH_MASK << TTBR0_IRGNH_SHIFT)
1180#define TTBR0_SH (TTBR0_SH_MASK << TTBR0_SH_SHIFT)
1181#define TTBR0_ORGN (TTBR0_ORGN_MASK << TTBR0_ORGN_SHIFT)
1182#define TTBR0_NOS (TTBR0_NOS_MASK << TTBR0_NOS_SHIFT)
1183#define TTBR0_IRGNL (TTBR0_IRGNL_MASK << TTBR0_IRGNL_SHIFT)
1184#define TTBR0_PA (TTBR0_PA_MASK << TTBR0_PA_SHIFT)
1185
1186
1187/* TTBR1 */
1188#define TTBR1_IRGNH (TTBR1_IRGNH_MASK << TTBR1_IRGNH_SHIFT)
1189#define TTBR1_SH (TTBR1_SH_MASK << TTBR1_SH_SHIFT)
1190#define TTBR1_ORGN (TTBR1_ORGN_MASK << TTBR1_ORGN_SHIFT)
1191#define TTBR1_NOS (TTBR1_NOS_MASK << TTBR1_NOS_SHIFT)
1192#define TTBR1_IRGNL (TTBR1_IRGNL_MASK << TTBR1_IRGNL_SHIFT)
1193#define TTBR1_PA (TTBR1_PA_MASK << TTBR1_PA_SHIFT)
1194
1195
1196/* V2PSR */
1197#define HIT (HIT_MASK << HIT_SHIFT)
1198#define INDEX (INDEX_MASK << INDEX_SHIFT)
1199
1200
1201/* V2Pxx */
1202#define V2Pxx_INDEX (V2Pxx_INDEX_MASK << V2Pxx_INDEX_SHIFT)
1203#define V2Pxx_VA (V2Pxx_VA_MASK << V2Pxx_VA_SHIFT)
1204
1205
1206/* Global Register Masks */
1207/* CBACRn */
1208#define RWVMID_MASK 0x1F
1209#define RWE_MASK 0x01
1210#define RWGE_MASK 0x01
1211#define CBVMID_MASK 0x1F
1212#define IRPTNDX_MASK 0xFF
1213
1214
1215/* CR */
1216#define RPUE_MASK 0x01
1217#define RPUERE_MASK 0x01
1218#define RPUEIE_MASK 0x01
1219#define DCDEE_MASK 0x01
1220#define CLIENTPD_MASK 0x01
1221#define STALLD_MASK 0x01
1222#define TLBLKCRWE_MASK 0x01
1223#define CR_TLBIALLCFG_MASK 0x01
1224#define TLBIVMIDCFG_MASK 0x01
1225#define CR_HUME_MASK 0x01
1226
1227
1228/* ESR */
1229#define CFG_MASK 0x01
1230#define BYPASS_MASK 0x01
1231#define ESR_MULTI_MASK 0x01
1232
1233
1234/* ESYNR0 */
1235#define ESYNR0_AMID_MASK 0xFF
1236#define ESYNR0_APID_MASK 0x1F
1237#define ESYNR0_ABID_MASK 0x07
1238#define ESYNR0_AVMID_MASK 0x1F
1239#define ESYNR0_ATID_MASK 0xFF
1240
1241
1242/* ESYNR1 */
1243#define ESYNR1_AMEMTYPE_MASK 0x07
1244#define ESYNR1_ASHARED_MASK 0x01
1245#define ESYNR1_AINNERSHARED_MASK 0x01
1246#define ESYNR1_APRIV_MASK 0x01
1247#define ESYNR1_APROTNS_MASK 0x01
1248#define ESYNR1_AINST_MASK 0x01
1249#define ESYNR1_AWRITE_MASK 0x01
1250#define ESYNR1_ABURST_MASK 0x01
1251#define ESYNR1_ALEN_MASK 0x0F
1252#define ESYNR1_ASIZE_MASK 0x01
1253#define ESYNR1_ALOCK_MASK 0x03
1254#define ESYNR1_AOOO_MASK 0x01
1255#define ESYNR1_AFULL_MASK 0x01
1256#define ESYNR1_AC_MASK 0x01
1257#define ESYNR1_DCD_MASK 0x01
1258
1259
1260/* IDR */
1261#define NM2VCBMT_MASK 0x1FF
1262#define HTW_MASK 0x01
1263#define HUM_MASK 0x01
1264#define TLBSIZE_MASK 0x0F
1265#define NCB_MASK 0xFF
1266#define NIRPT_MASK 0xFF
1267
1268
1269/* M2VCBRn */
1270#define VMID_MASK 0x1F
1271#define CBNDX_MASK 0xFF
1272#define BYPASSD_MASK 0x01
1273#define BPRCOSH_MASK 0x01
1274#define BPRCISH_MASK 0x01
1275#define BPRCNSH_MASK 0x01
1276#define BPSHCFG_MASK 0x03
1277#define NSCFG_MASK 0x03
1278#define BPMTCFG_MASK 0x01
1279#define BPMEMTYPE_MASK 0x07
1280
1281
1282/* REV */
1283#define MINOR_MASK 0x0F
1284#define MAJOR_MASK 0x0F
1285
1286
1287/* TESTBUSCR */
1288#define TBE_MASK 0x01
1289#define SPDMBE_MASK 0x01
1290#define WGSEL_MASK 0x03
1291#define TBLSEL_MASK 0x03
1292#define TBHSEL_MASK 0x03
1293#define SPDM0SEL_MASK 0x0F
1294#define SPDM1SEL_MASK 0x0F
1295#define SPDM2SEL_MASK 0x0F
1296#define SPDM3SEL_MASK 0x0F
1297
1298
1299/* TLBIMID */
1300#define TLBIVMID_VMID_MASK 0x1F
1301
1302
1303/* TLBRSW */
1304#define TLBRSW_INDEX_MASK 0xFF
1305#define TLBBFBS_MASK 0x03
1306
1307
1308/* TLBTR0 */
1309#define PR_MASK 0x01
1310#define PW_MASK 0x01
1311#define UR_MASK 0x01
1312#define UW_MASK 0x01
1313#define XN_MASK 0x01
1314#define NSDESC_MASK 0x01
1315#define ISH_MASK 0x01
1316#define SH_MASK 0x01
1317#define MT_MASK 0x07
1318#define DPSIZR_MASK 0x07
1319#define DPSIZC_MASK 0x07
1320
1321
1322/* TLBTR1 */
1323#define TLBTR1_VMID_MASK 0x1F
1324#define TLBTR1_PA_MASK 0x000FFFFF
1325
1326
1327/* TLBTR2 */
1328#define TLBTR2_ASID_MASK 0xFF
1329#define TLBTR2_V_MASK 0x01
1330#define TLBTR2_NSTID_MASK 0x01
1331#define TLBTR2_NV_MASK 0x01
1332#define TLBTR2_VA_MASK 0x000FFFFF
1333
1334
1335/* Global Register Shifts */
1336/* CBACRn */
1337#define RWVMID_SHIFT 0
1338#define RWE_SHIFT 8
1339#define RWGE_SHIFT 9
1340#define CBVMID_SHIFT 16
1341#define IRPTNDX_SHIFT 24
1342
1343
1344/* CR */
1345#define RPUE_SHIFT 0
1346#define RPUERE_SHIFT 1
1347#define RPUEIE_SHIFT 2
1348#define DCDEE_SHIFT 3
1349#define CLIENTPD_SHIFT 4
1350#define STALLD_SHIFT 5
1351#define TLBLKCRWE_SHIFT 6
1352#define CR_TLBIALLCFG_SHIFT 7
1353#define TLBIVMIDCFG_SHIFT 8
1354#define CR_HUME_SHIFT 9
1355
1356
1357/* ESR */
1358#define CFG_SHIFT 0
1359#define BYPASS_SHIFT 1
1360#define ESR_MULTI_SHIFT 31
1361
1362
1363/* ESYNR0 */
1364#define ESYNR0_AMID_SHIFT 0
1365#define ESYNR0_APID_SHIFT 8
1366#define ESYNR0_ABID_SHIFT 13
1367#define ESYNR0_AVMID_SHIFT 16
1368#define ESYNR0_ATID_SHIFT 24
1369
1370
1371/* ESYNR1 */
1372#define ESYNR1_AMEMTYPE_SHIFT 0
1373#define ESYNR1_ASHARED_SHIFT 3
1374#define ESYNR1_AINNERSHARED_SHIFT 4
1375#define ESYNR1_APRIV_SHIFT 5
1376#define ESYNR1_APROTNS_SHIFT 6
1377#define ESYNR1_AINST_SHIFT 7
1378#define ESYNR1_AWRITE_SHIFT 8
1379#define ESYNR1_ABURST_SHIFT 10
1380#define ESYNR1_ALEN_SHIFT 12
1381#define ESYNR1_ASIZE_SHIFT 16
1382#define ESYNR1_ALOCK_SHIFT 20
1383#define ESYNR1_AOOO_SHIFT 22
1384#define ESYNR1_AFULL_SHIFT 24
1385#define ESYNR1_AC_SHIFT 30
1386#define ESYNR1_DCD_SHIFT 31
1387
1388
1389/* IDR */
1390#define NM2VCBMT_SHIFT 0
1391#define HTW_SHIFT 9
1392#define HUM_SHIFT 10
1393#define TLBSIZE_SHIFT 12
1394#define NCB_SHIFT 16
1395#define NIRPT_SHIFT 24
1396
1397
1398/* M2VCBRn */
1399#define VMID_SHIFT 0
1400#define CBNDX_SHIFT 8
1401#define BYPASSD_SHIFT 16
1402#define BPRCOSH_SHIFT 17
1403#define BPRCISH_SHIFT 18
1404#define BPRCNSH_SHIFT 19
1405#define BPSHCFG_SHIFT 20
1406#define NSCFG_SHIFT 22
1407#define BPMTCFG_SHIFT 24
1408#define BPMEMTYPE_SHIFT 25
1409
1410
1411/* REV */
1412#define MINOR_SHIFT 0
1413#define MAJOR_SHIFT 4
1414
1415
1416/* TESTBUSCR */
1417#define TBE_SHIFT 0
1418#define SPDMBE_SHIFT 1
1419#define WGSEL_SHIFT 8
1420#define TBLSEL_SHIFT 12
1421#define TBHSEL_SHIFT 14
1422#define SPDM0SEL_SHIFT 16
1423#define SPDM1SEL_SHIFT 20
1424#define SPDM2SEL_SHIFT 24
1425#define SPDM3SEL_SHIFT 28
1426
1427
1428/* TLBIMID */
1429#define TLBIVMID_VMID_SHIFT 0
1430
1431
1432/* TLBRSW */
1433#define TLBRSW_INDEX_SHIFT 0
1434#define TLBBFBS_SHIFT 8
1435
1436
1437/* TLBTR0 */
1438#define PR_SHIFT 0
1439#define PW_SHIFT 1
1440#define UR_SHIFT 2
1441#define UW_SHIFT 3
1442#define XN_SHIFT 4
1443#define NSDESC_SHIFT 6
1444#define ISH_SHIFT 7
1445#define SH_SHIFT 8
1446#define MT_SHIFT 9
1447#define DPSIZR_SHIFT 16
1448#define DPSIZC_SHIFT 20
1449
1450
1451/* TLBTR1 */
1452#define TLBTR1_VMID_SHIFT 0
1453#define TLBTR1_PA_SHIFT 12
1454
1455
1456/* TLBTR2 */
1457#define TLBTR2_ASID_SHIFT 0
1458#define TLBTR2_V_SHIFT 8
1459#define TLBTR2_NSTID_SHIFT 9
1460#define TLBTR2_NV_SHIFT 10
1461#define TLBTR2_VA_SHIFT 12
1462
1463
1464/* Context Register Masks */
1465/* ACTLR */
1466#define CFERE_MASK 0x01
1467#define CFEIE_MASK 0x01
1468#define PTSHCFG_MASK 0x03
1469#define RCOSH_MASK 0x01
1470#define RCISH_MASK 0x01
1471#define RCNSH_MASK 0x01
1472#define PRIVCFG_MASK 0x03
1473#define DNA_MASK 0x01
1474#define DNLV2PA_MASK 0x01
1475#define TLBMCFG_MASK 0x03
1476#define CFCFG_MASK 0x01
1477#define TIPCF_MASK 0x01
1478#define V2PCFG_MASK 0x03
1479#define HUME_MASK 0x01
1480#define PTMTCFG_MASK 0x01
1481#define PTMEMTYPE_MASK 0x07
1482
1483
1484/* BFBCR */
1485#define BFBDFE_MASK 0x01
1486#define BFBSFE_MASK 0x01
1487#define SFVS_MASK 0x01
1488#define FLVIC_MASK 0x0F
1489#define SLVIC_MASK 0x0F
1490
1491
1492/* CONTEXTIDR */
1493#define CONTEXTIDR_ASID_MASK 0xFF
1494#define PROCID_MASK 0x00FFFFFF
1495
1496
1497/* FSR */
1498#define TF_MASK 0x01
1499#define AFF_MASK 0x01
1500#define APF_MASK 0x01
1501#define TLBMF_MASK 0x01
1502#define HTWDEEF_MASK 0x01
1503#define HTWSEEF_MASK 0x01
1504#define MHF_MASK 0x01
1505#define SL_MASK 0x01
1506#define SS_MASK 0x01
1507#define MULTI_MASK 0x01
1508
1509
1510/* FSYNR0 */
1511#define AMID_MASK 0xFF
1512#define APID_MASK 0x1F
1513#define ABID_MASK 0x07
1514#define ATID_MASK 0xFF
1515
1516
1517/* FSYNR1 */
1518#define AMEMTYPE_MASK 0x07
1519#define ASHARED_MASK 0x01
1520#define AINNERSHARED_MASK 0x01
1521#define APRIV_MASK 0x01
1522#define APROTNS_MASK 0x01
1523#define AINST_MASK 0x01
1524#define AWRITE_MASK 0x01
1525#define ABURST_MASK 0x01
1526#define ALEN_MASK 0x0F
1527#define FSYNR1_ASIZE_MASK 0x07
1528#define ALOCK_MASK 0x03
1529#define AFULL_MASK 0x01
1530
1531
1532/* NMRR */
1533#define ICPC0_MASK 0x03
1534#define ICPC1_MASK 0x03
1535#define ICPC2_MASK 0x03
1536#define ICPC3_MASK 0x03
1537#define ICPC4_MASK 0x03
1538#define ICPC5_MASK 0x03
1539#define ICPC6_MASK 0x03
1540#define ICPC7_MASK 0x03
1541#define OCPC0_MASK 0x03
1542#define OCPC1_MASK 0x03
1543#define OCPC2_MASK 0x03
1544#define OCPC3_MASK 0x03
1545#define OCPC4_MASK 0x03
1546#define OCPC5_MASK 0x03
1547#define OCPC6_MASK 0x03
1548#define OCPC7_MASK 0x03
1549
1550
1551/* PAR */
1552#define FAULT_MASK 0x01
1553/* If a fault is present, these are the
1554same as the fault fields in the FAR */
1555#define FAULT_TF_MASK 0x01
1556#define FAULT_AFF_MASK 0x01
1557#define FAULT_APF_MASK 0x01
1558#define FAULT_TLBMF_MASK 0x01
1559#define FAULT_HTWDEEF_MASK 0x01
1560#define FAULT_HTWSEEF_MASK 0x01
1561#define FAULT_MHF_MASK 0x01
1562#define FAULT_SL_MASK 0x01
1563#define FAULT_SS_MASK 0x01
1564
1565/* If NO fault is present, the following
1566 * fields are in effect
1567 * (FAULT remains as before) */
1568#define PAR_NOFAULT_SS_MASK 0x01
1569#define PAR_NOFAULT_MT_MASK 0x07
1570#define PAR_NOFAULT_SH_MASK 0x01
1571#define PAR_NOFAULT_NS_MASK 0x01
1572#define PAR_NOFAULT_NOS_MASK 0x01
1573#define PAR_NPFAULT_PA_MASK 0x000FFFFF
1574
1575
1576/* PRRR */
1577#define MTC0_MASK 0x03
1578#define MTC1_MASK 0x03
1579#define MTC2_MASK 0x03
1580#define MTC3_MASK 0x03
1581#define MTC4_MASK 0x03
1582#define MTC5_MASK 0x03
1583#define MTC6_MASK 0x03
1584#define MTC7_MASK 0x03
1585#define SHDSH0_MASK 0x01
1586#define SHDSH1_MASK 0x01
1587#define SHNMSH0_MASK 0x01
1588#define SHNMSH1_MASK 0x01
1589#define NOS0_MASK 0x01
1590#define NOS1_MASK 0x01
1591#define NOS2_MASK 0x01
1592#define NOS3_MASK 0x01
1593#define NOS4_MASK 0x01
1594#define NOS5_MASK 0x01
1595#define NOS6_MASK 0x01
1596#define NOS7_MASK 0x01
1597
1598
1599/* RESUME */
1600#define TNR_MASK 0x01
1601
1602
1603/* SCTLR */
1604#define M_MASK 0x01
1605#define TRE_MASK 0x01
1606#define AFE_MASK 0x01
1607#define HAF_MASK 0x01
1608#define BE_MASK 0x01
1609#define AFFD_MASK 0x01
1610
1611
1612/* TLBIASID */
1613#define TLBIASID_ASID_MASK 0xFF
1614
1615
1616/* TLBIVA */
1617#define TLBIVA_ASID_MASK 0xFF
1618#define TLBIVA_VA_MASK 0x000FFFFF
1619
1620
1621/* TLBIVAA */
1622#define TLBIVAA_VA_MASK 0x000FFFFF
1623
1624
1625/* TLBLCKR */
1626#define LKE_MASK 0x01
1627#define TLBLCKR_TLBIALLCFG_MASK 0x01
1628#define TLBIASIDCFG_MASK 0x01
1629#define TLBIVAACFG_MASK 0x01
1630#define FLOOR_MASK 0xFF
1631#define VICTIM_MASK 0xFF
1632
1633
1634/* TTBCR */
1635#define N_MASK 0x07
1636#define PD0_MASK 0x01
1637#define PD1_MASK 0x01
1638
1639
1640/* TTBR0 */
1641#define TTBR0_IRGNH_MASK 0x01
1642#define TTBR0_SH_MASK 0x01
1643#define TTBR0_ORGN_MASK 0x03
1644#define TTBR0_NOS_MASK 0x01
1645#define TTBR0_IRGNL_MASK 0x01
1646#define TTBR0_PA_MASK 0x0003FFFF
1647
1648
1649/* TTBR1 */
1650#define TTBR1_IRGNH_MASK 0x01
1651#define TTBR1_SH_MASK 0x01
1652#define TTBR1_ORGN_MASK 0x03
1653#define TTBR1_NOS_MASK 0x01
1654#define TTBR1_IRGNL_MASK 0x01
1655#define TTBR1_PA_MASK 0x0003FFFF
1656
1657
1658/* V2PSR */
1659#define HIT_MASK 0x01
1660#define INDEX_MASK 0xFF
1661
1662
1663/* V2Pxx */
1664#define V2Pxx_INDEX_MASK 0xFF
1665#define V2Pxx_VA_MASK 0x000FFFFF
1666
1667
1668/* Context Register Shifts */
1669/* ACTLR */
1670#define CFERE_SHIFT 0
1671#define CFEIE_SHIFT 1
1672#define PTSHCFG_SHIFT 2
1673#define RCOSH_SHIFT 4
1674#define RCISH_SHIFT 5
1675#define RCNSH_SHIFT 6
1676#define PRIVCFG_SHIFT 8
1677#define DNA_SHIFT 10
1678#define DNLV2PA_SHIFT 11
1679#define TLBMCFG_SHIFT 12
1680#define CFCFG_SHIFT 14
1681#define TIPCF_SHIFT 15
1682#define V2PCFG_SHIFT 16
1683#define HUME_SHIFT 18
1684#define PTMTCFG_SHIFT 20
1685#define PTMEMTYPE_SHIFT 21
1686
1687
1688/* BFBCR */
1689#define BFBDFE_SHIFT 0
1690#define BFBSFE_SHIFT 1
1691#define SFVS_SHIFT 2
1692#define FLVIC_SHIFT 4
1693#define SLVIC_SHIFT 8
1694
1695
1696/* CONTEXTIDR */
1697#define CONTEXTIDR_ASID_SHIFT 0
1698#define PROCID_SHIFT 8
1699
1700
1701/* FSR */
1702#define TF_SHIFT 1
1703#define AFF_SHIFT 2
1704#define APF_SHIFT 3
1705#define TLBMF_SHIFT 4
1706#define HTWDEEF_SHIFT 5
1707#define HTWSEEF_SHIFT 6
1708#define MHF_SHIFT 7
1709#define SL_SHIFT 16
1710#define SS_SHIFT 30
1711#define MULTI_SHIFT 31
1712
1713
1714/* FSYNR0 */
1715#define AMID_SHIFT 0
1716#define APID_SHIFT 8
1717#define ABID_SHIFT 13
1718#define ATID_SHIFT 24
1719
1720
1721/* FSYNR1 */
1722#define AMEMTYPE_SHIFT 0
1723#define ASHARED_SHIFT 3
1724#define AINNERSHARED_SHIFT 4
1725#define APRIV_SHIFT 5
1726#define APROTNS_SHIFT 6
1727#define AINST_SHIFT 7
1728#define AWRITE_SHIFT 8
1729#define ABURST_SHIFT 10
1730#define ALEN_SHIFT 12
1731#define FSYNR1_ASIZE_SHIFT 16
1732#define ALOCK_SHIFT 20
1733#define AFULL_SHIFT 24
1734
1735
1736/* NMRR */
1737#define ICPC0_SHIFT 0
1738#define ICPC1_SHIFT 2
1739#define ICPC2_SHIFT 4
1740#define ICPC3_SHIFT 6
1741#define ICPC4_SHIFT 8
1742#define ICPC5_SHIFT 10
1743#define ICPC6_SHIFT 12
1744#define ICPC7_SHIFT 14
1745#define OCPC0_SHIFT 16
1746#define OCPC1_SHIFT 18
1747#define OCPC2_SHIFT 20
1748#define OCPC3_SHIFT 22
1749#define OCPC4_SHIFT 24
1750#define OCPC5_SHIFT 26
1751#define OCPC6_SHIFT 28
1752#define OCPC7_SHIFT 30
1753
1754
1755/* PAR */
1756#define FAULT_SHIFT 0
1757/* If a fault is present, these are the
1758same as the fault fields in the FAR */
1759#define FAULT_TF_SHIFT 1
1760#define FAULT_AFF_SHIFT 2
1761#define FAULT_APF_SHIFT 3
1762#define FAULT_TLBMF_SHIFT 4
1763#define FAULT_HTWDEEF_SHIFT 5
1764#define FAULT_HTWSEEF_SHIFT 6
1765#define FAULT_MHF_SHIFT 7
1766#define FAULT_SL_SHIFT 16
1767#define FAULT_SS_SHIFT 30
1768
1769/* If NO fault is present, the following
1770 * fields are in effect
1771 * (FAULT remains as before) */
1772#define PAR_NOFAULT_SS_SHIFT 1
1773#define PAR_NOFAULT_MT_SHIFT 4
1774#define PAR_NOFAULT_SH_SHIFT 7
1775#define PAR_NOFAULT_NS_SHIFT 9
1776#define PAR_NOFAULT_NOS_SHIFT 10
1777#define PAR_NPFAULT_PA_SHIFT 12
1778
1779
1780/* PRRR */
1781#define MTC0_SHIFT 0
1782#define MTC1_SHIFT 2
1783#define MTC2_SHIFT 4
1784#define MTC3_SHIFT 6
1785#define MTC4_SHIFT 8
1786#define MTC5_SHIFT 10
1787#define MTC6_SHIFT 12
1788#define MTC7_SHIFT 14
1789#define SHDSH0_SHIFT 16
1790#define SHDSH1_SHIFT 17
1791#define SHNMSH0_SHIFT 18
1792#define SHNMSH1_SHIFT 19
1793#define NOS0_SHIFT 24
1794#define NOS1_SHIFT 25
1795#define NOS2_SHIFT 26
1796#define NOS3_SHIFT 27
1797#define NOS4_SHIFT 28
1798#define NOS5_SHIFT 29
1799#define NOS6_SHIFT 30
1800#define NOS7_SHIFT 31
1801
1802
1803/* RESUME */
1804#define TNR_SHIFT 0
1805
1806
1807/* SCTLR */
1808#define M_SHIFT 0
1809#define TRE_SHIFT 1
1810#define AFE_SHIFT 2
1811#define HAF_SHIFT 3
1812#define BE_SHIFT 4
1813#define AFFD_SHIFT 5
1814
1815
1816/* TLBIASID */
1817#define TLBIASID_ASID_SHIFT 0
1818
1819
1820/* TLBIVA */
1821#define TLBIVA_ASID_SHIFT 0
1822#define TLBIVA_VA_SHIFT 12
1823
1824
1825/* TLBIVAA */
1826#define TLBIVAA_VA_SHIFT 12
1827
1828
1829/* TLBLCKR */
1830#define LKE_SHIFT 0
1831#define TLBLCKR_TLBIALLCFG_SHIFT 1
1832#define TLBIASIDCFG_SHIFT 2
1833#define TLBIVAACFG_SHIFT 3
1834#define FLOOR_SHIFT 8
1835#define VICTIM_SHIFT 8
1836
1837
1838/* TTBCR */
1839#define N_SHIFT 3
1840#define PD0_SHIFT 4
1841#define PD1_SHIFT 5
1842
1843
1844/* TTBR0 */
1845#define TTBR0_IRGNH_SHIFT 0
1846#define TTBR0_SH_SHIFT 1
1847#define TTBR0_ORGN_SHIFT 3
1848#define TTBR0_NOS_SHIFT 5
1849#define TTBR0_IRGNL_SHIFT 6
1850#define TTBR0_PA_SHIFT 14
1851
1852
1853/* TTBR1 */
1854#define TTBR1_IRGNH_SHIFT 0
1855#define TTBR1_SH_SHIFT 1
1856#define TTBR1_ORGN_SHIFT 3
1857#define TTBR1_NOS_SHIFT 5
1858#define TTBR1_IRGNL_SHIFT 6
1859#define TTBR1_PA_SHIFT 14
1860
1861
1862/* V2PSR */
1863#define HIT_SHIFT 0
1864#define INDEX_SHIFT 8
1865
1866
1867/* V2Pxx */
1868#define V2Pxx_INDEX_SHIFT 0
1869#define V2Pxx_VA_SHIFT 12
1870
1871#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs-8x60.h b/arch/arm/mach-msm/include/mach/irqs-8x60.h
new file mode 100644
index 000000000000..36074cfc9ad2
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/irqs-8x60.h
@@ -0,0 +1,253 @@
1/* Copyright (c) 2010 Code Aurora Forum. All rights reserved.
2 *
3 * This software is licensed under the terms of the GNU General Public
4 * License version 2, as published by the Free Software Foundation, and
5 * may be copied, distributed, and modified under those terms.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#ifndef __ASM_ARCH_MSM_IRQS_8X60_H
15#define __ASM_ARCH_MSM_IRQS_8X60_H
16
17/* MSM ACPU Interrupt Numbers */
18
19/* 0-15: STI/SGI (software triggered/generated interrupts)
20 * 16-31: PPI (private peripheral interrupts)
21 * 32+: SPI (shared peripheral interrupts)
22 */
23
24#define GIC_PPI_START 16
25#define GIC_SPI_START 32
26
27#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 0)
28#define INT_GP_TIMER_EXP (GIC_PPI_START + 1)
29#define INT_GP_TIMER2_EXP (GIC_PPI_START + 2)
30#define WDT0_ACCSCSSNBARK_INT (GIC_PPI_START + 3)
31#define WDT1_ACCSCSSNBARK_INT (GIC_PPI_START + 4)
32#define AVS_SVICINT (GIC_PPI_START + 5)
33#define AVS_SVICINTSWDONE (GIC_PPI_START + 6)
34#define CPU_DBGCPUXCOMMRXFULL (GIC_PPI_START + 7)
35#define CPU_DBGCPUXCOMMTXEMPTY (GIC_PPI_START + 8)
36#define CPU_SICCPUXPERFMONIRPTREQ (GIC_PPI_START + 9)
37#define SC_AVSCPUXDOWN (GIC_PPI_START + 10)
38#define SC_AVSCPUXUP (GIC_PPI_START + 11)
39#define SC_SICCPUXACGIRPTREQ (GIC_PPI_START + 12)
40/* PPI 13 to 15 are unused */
41
42
43#define SC_SICMPUIRPTREQ (GIC_SPI_START + 0)
44#define SC_SICL2IRPTREQ (GIC_SPI_START + 1)
45#define SC_SICL2ACGIRPTREQ (GIC_SPI_START + 2)
46#define NC (GIC_SPI_START + 3)
47#define TLMM_SCSS_DIR_CONN_IRQ_0 (GIC_SPI_START + 4)
48#define TLMM_SCSS_DIR_CONN_IRQ_1 (GIC_SPI_START + 5)
49#define TLMM_SCSS_DIR_CONN_IRQ_2 (GIC_SPI_START + 6)
50#define TLMM_SCSS_DIR_CONN_IRQ_3 (GIC_SPI_START + 7)
51#define TLMM_SCSS_DIR_CONN_IRQ_4 (GIC_SPI_START + 8)
52#define TLMM_SCSS_DIR_CONN_IRQ_5 (GIC_SPI_START + 9)
53#define TLMM_SCSS_DIR_CONN_IRQ_6 (GIC_SPI_START + 10)
54#define TLMM_SCSS_DIR_CONN_IRQ_7 (GIC_SPI_START + 11)
55#define TLMM_SCSS_DIR_CONN_IRQ_8 (GIC_SPI_START + 12)
56#define TLMM_SCSS_DIR_CONN_IRQ_9 (GIC_SPI_START + 13)
57#define PM8058_SEC_IRQ_N (GIC_SPI_START + 14)
58#define PM8901_SEC_IRQ_N (GIC_SPI_START + 15)
59#define TLMM_SCSS_SUMMARY_IRQ (GIC_SPI_START + 16)
60#define SPDM_RT_1_IRQ (GIC_SPI_START + 17)
61#define SPDM_DIAG_IRQ (GIC_SPI_START + 18)
62#define RPM_SCSS_CPU0_GP_HIGH_IRQ (GIC_SPI_START + 19)
63#define RPM_SCSS_CPU0_GP_MEDIUM_IRQ (GIC_SPI_START + 20)
64#define RPM_SCSS_CPU0_GP_LOW_IRQ (GIC_SPI_START + 21)
65#define RPM_SCSS_CPU0_WAKE_UP_IRQ (GIC_SPI_START + 22)
66#define RPM_SCSS_CPU1_GP_HIGH_IRQ (GIC_SPI_START + 23)
67#define RPM_SCSS_CPU1_GP_MEDIUM_IRQ (GIC_SPI_START + 24)
68#define RPM_SCSS_CPU1_GP_LOW_IRQ (GIC_SPI_START + 25)
69#define RPM_SCSS_CPU1_WAKE_UP_IRQ (GIC_SPI_START + 26)
70#define SSBI2_2_SC_CPU0_SECURE_INT (GIC_SPI_START + 27)
71#define SSBI2_2_SC_CPU0_NON_SECURE_INT (GIC_SPI_START + 28)
72#define SSBI2_1_SC_CPU0_SECURE_INT (GIC_SPI_START + 29)
73#define SSBI2_1_SC_CPU0_NON_SECURE_INT (GIC_SPI_START + 30)
74#define MSMC_SC_SEC_CE_IRQ (GIC_SPI_START + 31)
75#define MSMC_SC_PRI_CE_IRQ (GIC_SPI_START + 32)
76#define MARM_FIQ (GIC_SPI_START + 33)
77#define MARM_IRQ (GIC_SPI_START + 34)
78#define MARM_L2CC_IRQ (GIC_SPI_START + 35)
79#define MARM_WDOG_EXPIRED (GIC_SPI_START + 36)
80#define MARM_SCSS_GP_IRQ_0 (GIC_SPI_START + 37)
81#define MARM_SCSS_GP_IRQ_1 (GIC_SPI_START + 38)
82#define MARM_SCSS_GP_IRQ_2 (GIC_SPI_START + 39)
83#define MARM_SCSS_GP_IRQ_3 (GIC_SPI_START + 40)
84#define MARM_SCSS_GP_IRQ_4 (GIC_SPI_START + 41)
85#define MARM_SCSS_GP_IRQ_5 (GIC_SPI_START + 42)
86#define MARM_SCSS_GP_IRQ_6 (GIC_SPI_START + 43)
87#define MARM_SCSS_GP_IRQ_7 (GIC_SPI_START + 44)
88#define MARM_SCSS_GP_IRQ_8 (GIC_SPI_START + 45)
89#define MARM_SCSS_GP_IRQ_9 (GIC_SPI_START + 46)
90#define VPE_IRQ (GIC_SPI_START + 47)
91#define VFE_IRQ (GIC_SPI_START + 48)
92#define VCODEC_IRQ (GIC_SPI_START + 49)
93#define TV_ENC_IRQ (GIC_SPI_START + 50)
94#define SMMU_VPE_CB_SC_SECURE_IRQ (GIC_SPI_START + 51)
95#define SMMU_VPE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 52)
96#define SMMU_VFE_CB_SC_SECURE_IRQ (GIC_SPI_START + 53)
97#define SMMU_VFE_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 54)
98#define SMMU_VCODEC_B_CB_SC_SECURE_IRQ (GIC_SPI_START + 55)
99#define SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 56)
100#define SMMU_VCODEC_A_CB_SC_SECURE_IRQ (GIC_SPI_START + 57)
101#define SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 58)
102#define SMMU_ROT_CB_SC_SECURE_IRQ (GIC_SPI_START + 59)
103#define SMMU_ROT_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 60)
104#define SMMU_MDP1_CB_SC_SECURE_IRQ (GIC_SPI_START + 61)
105#define SMMU_MDP1_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 62)
106#define SMMU_MDP0_CB_SC_SECURE_IRQ (GIC_SPI_START + 63)
107#define SMMU_MDP0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 64)
108#define SMMU_JPEGD_CB_SC_SECURE_IRQ (GIC_SPI_START + 65)
109#define SMMU_JPEGD_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 66)
110#define SMMU_IJPEG_CB_SC_SECURE_IRQ (GIC_SPI_START + 67)
111#define SMMU_IJPEG_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 68)
112#define SMMU_GFX3D_CB_SC_SECURE_IRQ (GIC_SPI_START + 69)
113#define SMMU_GFX3D_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 70)
114#define SMMU_GFX2D0_CB_SC_SECURE_IRQ (GIC_SPI_START + 71)
115#define SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ (GIC_SPI_START + 72)
116#define ROT_IRQ (GIC_SPI_START + 73)
117#define MMSS_FABRIC_IRQ (GIC_SPI_START + 74)
118#define MDP_IRQ (GIC_SPI_START + 75)
119#define JPEGD_IRQ (GIC_SPI_START + 76)
120#define JPEG_IRQ (GIC_SPI_START + 77)
121#define MMSS_IMEM_IRQ (GIC_SPI_START + 78)
122#define HDMI_IRQ (GIC_SPI_START + 79)
123#define GFX3D_IRQ (GIC_SPI_START + 80)
124#define GFX2D0_IRQ (GIC_SPI_START + 81)
125#define DSI_IRQ (GIC_SPI_START + 82)
126#define CSI_1_IRQ (GIC_SPI_START + 83)
127#define CSI_0_IRQ (GIC_SPI_START + 84)
128#define LPASS_SCSS_AUDIO_IF_OUT0_IRQ (GIC_SPI_START + 85)
129#define LPASS_SCSS_MIDI_IRQ (GIC_SPI_START + 86)
130#define LPASS_Q6SS_WDOG_EXPIRED (GIC_SPI_START + 87)
131#define LPASS_SCSS_GP_LOW_IRQ (GIC_SPI_START + 88)
132#define LPASS_SCSS_GP_MEDIUM_IRQ (GIC_SPI_START + 89)
133#define LPASS_SCSS_GP_HIGH_IRQ (GIC_SPI_START + 90)
134#define TOP_IMEM_IRQ (GIC_SPI_START + 91)
135#define FABRIC_SYS_IRQ (GIC_SPI_START + 92)
136#define FABRIC_APPS_IRQ (GIC_SPI_START + 93)
137#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94)
138#define SDC4_BAM_IRQ (GIC_SPI_START + 95)
139#define SDC3_BAM_IRQ (GIC_SPI_START + 96)
140#define SDC2_BAM_IRQ (GIC_SPI_START + 97)
141#define SDC1_BAM_IRQ (GIC_SPI_START + 98)
142#define FABRIC_SPS_IRQ (GIC_SPI_START + 99)
143#define USB1_HS_IRQ (GIC_SPI_START + 100)
144#define SDC4_IRQ_0 (GIC_SPI_START + 101)
145#define SDC3_IRQ_0 (GIC_SPI_START + 102)
146#define SDC2_IRQ_0 (GIC_SPI_START + 103)
147#define SDC1_IRQ_0 (GIC_SPI_START + 104)
148#define SPS_BAM_DMA_IRQ (GIC_SPI_START + 105)
149#define SPS_SEC_VIOL_IRQ (GIC_SPI_START + 106)
150#define SPS_MTI_0 (GIC_SPI_START + 107)
151#define SPS_MTI_1 (GIC_SPI_START + 108)
152#define SPS_MTI_2 (GIC_SPI_START + 109)
153#define SPS_MTI_3 (GIC_SPI_START + 110)
154#define SPS_MTI_4 (GIC_SPI_START + 111)
155#define SPS_MTI_5 (GIC_SPI_START + 112)
156#define SPS_MTI_6 (GIC_SPI_START + 113)
157#define SPS_MTI_7 (GIC_SPI_START + 114)
158#define SPS_MTI_8 (GIC_SPI_START + 115)
159#define SPS_MTI_9 (GIC_SPI_START + 116)
160#define SPS_MTI_10 (GIC_SPI_START + 117)
161#define SPS_MTI_11 (GIC_SPI_START + 118)
162#define SPS_MTI_12 (GIC_SPI_START + 119)
163#define SPS_MTI_13 (GIC_SPI_START + 120)
164#define SPS_MTI_14 (GIC_SPI_START + 121)
165#define SPS_MTI_15 (GIC_SPI_START + 122)
166#define SPS_MTI_16 (GIC_SPI_START + 123)
167#define SPS_MTI_17 (GIC_SPI_START + 124)
168#define SPS_MTI_18 (GIC_SPI_START + 125)
169#define SPS_MTI_19 (GIC_SPI_START + 126)
170#define SPS_MTI_20 (GIC_SPI_START + 127)
171#define SPS_MTI_21 (GIC_SPI_START + 128)
172#define SPS_MTI_22 (GIC_SPI_START + 129)
173#define SPS_MTI_23 (GIC_SPI_START + 130)
174#define SPS_MTI_24 (GIC_SPI_START + 131)
175#define SPS_MTI_25 (GIC_SPI_START + 132)
176#define SPS_MTI_26 (GIC_SPI_START + 133)
177#define SPS_MTI_27 (GIC_SPI_START + 134)
178#define SPS_MTI_28 (GIC_SPI_START + 135)
179#define SPS_MTI_29 (GIC_SPI_START + 136)
180#define SPS_MTI_30 (GIC_SPI_START + 137)
181#define SPS_MTI_31 (GIC_SPI_START + 138)
182#define UXMC_EBI2_WR_ER_DONE_IRQ (GIC_SPI_START + 139)
183#define UXMC_EBI2_OP_DONE_IRQ (GIC_SPI_START + 140)
184#define USB2_IRQ (GIC_SPI_START + 141)
185#define USB1_IRQ (GIC_SPI_START + 142)
186#define TSSC_SSBI_IRQ (GIC_SPI_START + 143)
187#define TSSC_SAMPLE_IRQ (GIC_SPI_START + 144)
188#define TSSC_PENUP_IRQ (GIC_SPI_START + 145)
189#define INT_UART1DM_IRQ (GIC_SPI_START + 146)
190#define GSBI1_QUP_IRQ (GIC_SPI_START + 147)
191#define INT_UART2DM_IRQ (GIC_SPI_START + 148)
192#define GSBI2_QUP_IRQ (GIC_SPI_START + 149)
193#define INT_UART3DM_IRQ (GIC_SPI_START + 150)
194#define GSBI3_QUP_IRQ (GIC_SPI_START + 151)
195#define INT_UART4DM_IRQ (GIC_SPI_START + 152)
196#define GSBI4_QUP_IRQ (GIC_SPI_START + 153)
197#define INT_UART5DM_IRQ (GIC_SPI_START + 154)
198#define GSBI5_QUP_IRQ (GIC_SPI_START + 155)
199#define INT_UART6DM_IRQ (GIC_SPI_START + 156)
200#define GSBI6_QUP_IRQ (GIC_SPI_START + 157)
201#define INT_UART7DM_IRQ (GIC_SPI_START + 158)
202#define GSBI7_QUP_IRQ (GIC_SPI_START + 159)
203#define INT_UART8DM_IRQ (GIC_SPI_START + 160)
204#define GSBI8_QUP_IRQ (GIC_SPI_START + 161)
205#define TSIF_TSPP_IRQ (GIC_SPI_START + 162)
206#define TSIF_BAM_IRQ (GIC_SPI_START + 163)
207#define TSIF2_IRQ (GIC_SPI_START + 164)
208#define TSIF1_IRQ (GIC_SPI_START + 165)
209#define INT_ADM1_MASTER (GIC_SPI_START + 166)
210#define INT_ADM1_AARM (GIC_SPI_START + 167)
211#define INT_ADM1_SD2 (GIC_SPI_START + 168)
212#define INT_ADM1_SD3 (GIC_SPI_START + 169)
213#define INT_ADM0_MASTER (GIC_SPI_START + 170)
214#define INT_ADM0_AARM (GIC_SPI_START + 171)
215#define INT_ADM0_SD2 (GIC_SPI_START + 172)
216#define INT_ADM0_SD3 (GIC_SPI_START + 173)
217#define CC_SCSS_WDT1CPU1BITEEXPIRED (GIC_SPI_START + 174)
218#define CC_SCSS_WDT1CPU0BITEEXPIRED (GIC_SPI_START + 175)
219#define CC_SCSS_WDT0CPU1BITEEXPIRED (GIC_SPI_START + 176)
220#define CC_SCSS_WDT0CPU0BITEEXPIRED (GIC_SPI_START + 177)
221#define TSENS_UPPER_LOWER_INT (GIC_SPI_START + 178)
222#define SSBI2_2_SC_CPU1_SECURE_INT (GIC_SPI_START + 179)
223#define SSBI2_2_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 180)
224#define SSBI2_1_SC_CPU1_SECURE_INT (GIC_SPI_START + 181)
225#define SSBI2_1_SC_CPU1_NON_SECURE_INT (GIC_SPI_START + 182)
226#define XPU_SUMMARY_IRQ (GIC_SPI_START + 183)
227#define BUS_EXCEPTION_SUMMARY_IRQ (GIC_SPI_START + 184)
228#define HSDDRX_SMICH0_IRQ (GIC_SPI_START + 185)
229#define HSDDRX_EBI1_IRQ (GIC_SPI_START + 186)
230#define SDC5_BAM_IRQ (GIC_SPI_START + 187)
231#define SDC5_IRQ_0 (GIC_SPI_START + 188)
232#define INT_UART9DM_IRQ (GIC_SPI_START + 189)
233#define GSBI9_QUP_IRQ (GIC_SPI_START + 190)
234#define INT_UART10DM_IRQ (GIC_SPI_START + 191)
235#define GSBI10_QUP_IRQ (GIC_SPI_START + 192)
236#define INT_UART11DM_IRQ (GIC_SPI_START + 193)
237#define GSBI11_QUP_IRQ (GIC_SPI_START + 194)
238#define INT_UART12DM_IRQ (GIC_SPI_START + 195)
239#define GSBI12_QUP_IRQ (GIC_SPI_START + 196)
240/*SPI 197 to 216 arent used in 8x60*/
241#define SMPSS_SPARE_1 (GIC_SPI_START + 217)
242#define SMPSS_SPARE_2 (GIC_SPI_START + 218)
243#define SMPSS_SPARE_3 (GIC_SPI_START + 219)
244#define SMPSS_SPARE_4 (GIC_SPI_START + 220)
245#define SMPSS_SPARE_5 (GIC_SPI_START + 221)
246#define SMPSS_SPARE_6 (GIC_SPI_START + 222)
247#define SMPSS_SPARE_7 (GIC_SPI_START + 223)
248
249#define NR_GPIO_IRQS 173
250#define NR_MSM_IRQS 256
251#define NR_BOARD_IRQS 0
252
253#endif
diff --git a/arch/arm/mach-msm/include/mach/irqs.h b/arch/arm/mach-msm/include/mach/irqs.h
index 164d355c96ea..8679a4564744 100644
--- a/arch/arm/mach-msm/include/mach/irqs.h
+++ b/arch/arm/mach-msm/include/mach/irqs.h
@@ -24,6 +24,8 @@
24#elif defined(CONFIG_ARCH_QSD8X50) 24#elif defined(CONFIG_ARCH_QSD8X50)
25#include "irqs-8x50.h" 25#include "irqs-8x50.h"
26#include "sirc.h" 26#include "sirc.h"
27#elif defined(CONFIG_ARCH_MSM8X60)
28#include "irqs-8x60.h"
27#elif defined(CONFIG_ARCH_MSM_ARM11) 29#elif defined(CONFIG_ARCH_MSM_ARM11)
28#include "irqs-7x00.h" 30#include "irqs-7x00.h"
29#else 31#else
diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
index 50c7847e6002..070e17d237f1 100644
--- a/arch/arm/mach-msm/include/mach/memory.h
+++ b/arch/arm/mach-msm/include/mach/memory.h
@@ -23,6 +23,8 @@
23#define PHYS_OFFSET UL(0x20000000) 23#define PHYS_OFFSET UL(0x20000000)
24#elif defined(CONFIG_ARCH_MSM7X30) 24#elif defined(CONFIG_ARCH_MSM7X30)
25#define PHYS_OFFSET UL(0x00200000) 25#define PHYS_OFFSET UL(0x00200000)
26#elif defined(CONFIG_ARCH_MSM8X60)
27#define PHYS_OFFSET UL(0x40200000)
26#else 28#else
27#define PHYS_OFFSET UL(0x10000000) 29#define PHYS_OFFSET UL(0x10000000)
28#endif 30#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
new file mode 100644
index 000000000000..45bab50e3ee6
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -0,0 +1,101 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 *
16 * The MSM peripherals are spread all over across 768MB of physical
17 * space, which makes just having a simple IO_ADDRESS macro to slide
18 * them into the right virtual location rough. Instead, we will
19 * provide a master phys->virt mapping for peripherals here.
20 *
21 */
22
23#ifndef __ASM_ARCH_MSM_IOMAP_8X60_H
24#define __ASM_ARCH_MSM_IOMAP_8X60_H
25
26/* Physical base address and size of peripherals.
27 * Ordered by the virtual base addresses they will be mapped at.
28 *
29 * MSM_VIC_BASE must be an value that can be loaded via a "mov"
30 * instruction, otherwise entry-macro.S will not compile.
31 *
32 * If you add or remove entries here, you'll want to edit the
33 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
34 * changes.
35 *
36 */
37
38#define MSM_QGIC_DIST_BASE IOMEM(0xF0000000)
39#define MSM_QGIC_DIST_PHYS 0x02080000
40#define MSM_QGIC_DIST_SIZE SZ_4K
41
42#define MSM_QGIC_CPU_BASE IOMEM(0xF0001000)
43#define MSM_QGIC_CPU_PHYS 0x02081000
44#define MSM_QGIC_CPU_SIZE SZ_4K
45
46#define MSM_ACC_BASE IOMEM(0xF0002000)
47#define MSM_ACC_PHYS 0x02001000
48#define MSM_ACC_SIZE SZ_4K
49
50#define MSM_GCC_BASE IOMEM(0xF0003000)
51#define MSM_GCC_PHYS 0x02082000
52#define MSM_GCC_SIZE SZ_4K
53
54#define MSM_TLMM_BASE IOMEM(0xF0004000)
55#define MSM_TLMM_PHYS 0x00800000
56#define MSM_TLMM_SIZE SZ_16K
57
58#define MSM_SHARED_RAM_BASE IOMEM(0xF0100000)
59#define MSM_SHARED_RAM_SIZE SZ_1M
60
61#define MSM_TMR_BASE IOMEM(0xF0200000)
62#define MSM_TMR_PHYS 0x02000000
63#define MSM_TMR_SIZE (SZ_1M)
64
65#define MSM_GPT_BASE (MSM_TMR_BASE + 0x4)
66#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
67
68#define MSM_IOMMU_JPEGD_PHYS 0x07300000
69#define MSM_IOMMU_JPEGD_SIZE SZ_1M
70
71#define MSM_IOMMU_VPE_PHYS 0x07400000
72#define MSM_IOMMU_VPE_SIZE SZ_1M
73
74#define MSM_IOMMU_MDP0_PHYS 0x07500000
75#define MSM_IOMMU_MDP0_SIZE SZ_1M
76
77#define MSM_IOMMU_MDP1_PHYS 0x07600000
78#define MSM_IOMMU_MDP1_SIZE SZ_1M
79
80#define MSM_IOMMU_ROT_PHYS 0x07700000
81#define MSM_IOMMU_ROT_SIZE SZ_1M
82
83#define MSM_IOMMU_IJPEG_PHYS 0x07800000
84#define MSM_IOMMU_IJPEG_SIZE SZ_1M
85
86#define MSM_IOMMU_VFE_PHYS 0x07900000
87#define MSM_IOMMU_VFE_SIZE SZ_1M
88
89#define MSM_IOMMU_VCODEC_A_PHYS 0x07A00000
90#define MSM_IOMMU_VCODEC_A_SIZE SZ_1M
91
92#define MSM_IOMMU_VCODEC_B_PHYS 0x07B00000
93#define MSM_IOMMU_VCODEC_B_SIZE SZ_1M
94
95#define MSM_IOMMU_GFX3D_PHYS 0x07C00000
96#define MSM_IOMMU_GFX3D_SIZE SZ_1M
97
98#define MSM_IOMMU_GFX2D0_PHYS 0x07D00000
99#define MSM_IOMMU_GFX2D0_SIZE SZ_1M
100
101#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index e6b1821cc4ea..8e24dd812139 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -47,8 +47,12 @@
47#include "msm_iomap-7x30.h" 47#include "msm_iomap-7x30.h"
48#elif defined(CONFIG_ARCH_QSD8X50) 48#elif defined(CONFIG_ARCH_QSD8X50)
49#include "msm_iomap-8x50.h" 49#include "msm_iomap-8x50.h"
50#elif defined(CONFIG_ARCH_MSM8X60)
51#include "msm_iomap-8x60.h"
50#else 52#else
51#include "msm_iomap-7x00.h" 53#include "msm_iomap-7x00.h"
52#endif 54#endif
53 55
56
57
54#endif 58#endif
diff --git a/arch/arm/mach-msm/include/mach/smp.h b/arch/arm/mach-msm/include/mach/smp.h
new file mode 100644
index 000000000000..3ff7bf5e679e
--- /dev/null
+++ b/arch/arm/mach-msm/include/mach/smp.h
@@ -0,0 +1,39 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * Redistribution and use in source and binary forms, with or without
4 * modification, are permitted provided that the following conditions are met:
5 * * Redistributions of source code must retain the above copyright
6 * notice, this list of conditions and the following disclaimer.
7 * * Redistributions in binary form must reproduce the above copyright
8 * notice, this list of conditions and the following disclaimer in the
9 * documentation and/or other materials provided with the distribution.
10 * * Neither the name of Code Aurora nor
11 * the names of its contributors may be used to endorse or promote
12 * products derived from this software without specific prior written
13 * permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
19 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
20 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
21 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
22 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
23 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
24 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
25 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 */
28
29#ifndef __ASM_ARCH_MSM_SMP_H
30#define __ASM_ARCH_MSM_SMP_H
31
32#include <asm/hardware/gic.h>
33
34static inline void smp_cross_call(const struct cpumask *mask)
35{
36 gic_raise_softirq(mask, 1);
37}
38
39#endif
diff --git a/arch/arm/mach-msm/include/mach/vmalloc.h b/arch/arm/mach-msm/include/mach/vmalloc.h
index 05f81fd8623c..31a32ad062dc 100644
--- a/arch/arm/mach-msm/include/mach/vmalloc.h
+++ b/arch/arm/mach-msm/include/mach/vmalloc.h
@@ -16,7 +16,7 @@
16#ifndef __ASM_ARCH_MSM_VMALLOC_H 16#ifndef __ASM_ARCH_MSM_VMALLOC_H
17#define __ASM_ARCH_MSM_VMALLOC_H 17#define __ASM_ARCH_MSM_VMALLOC_H
18 18
19#define VMALLOC_END (PAGE_OFFSET + 0x10000000) 19#define VMALLOC_END 0xd0000000
20 20
21#endif 21#endif
22 22
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 1c05060b5f3b..d36b61074146 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -100,6 +100,21 @@ void __init msm_map_qsd8x50_io(void)
100} 100}
101#endif /* CONFIG_ARCH_QSD8X50 */ 101#endif /* CONFIG_ARCH_QSD8X50 */
102 102
103#ifdef CONFIG_ARCH_MSM8X60
104static struct map_desc msm8x60_io_desc[] __initdata = {
105 MSM_DEVICE(QGIC_DIST),
106 MSM_DEVICE(QGIC_CPU),
107 MSM_DEVICE(TMR),
108 MSM_DEVICE(ACC),
109 MSM_DEVICE(GCC),
110};
111
112void __init msm_map_msm8x60_io(void)
113{
114 iotable_init(msm8x60_io_desc, ARRAY_SIZE(msm8x60_io_desc));
115}
116#endif /* CONFIG_ARCH_MSM8X60 */
117
103#ifdef CONFIG_ARCH_MSM7X30 118#ifdef CONFIG_ARCH_MSM7X30
104static struct map_desc msm7x30_io_desc[] __initdata = { 119static struct map_desc msm7x30_io_desc[] __initdata = {
105 MSM_DEVICE(VIC), 120 MSM_DEVICE(VIC),
diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c
new file mode 100644
index 000000000000..f71747db3bee
--- /dev/null
+++ b/arch/arm/mach-msm/iommu.c
@@ -0,0 +1,597 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/errno.h>
23#include <linux/io.h>
24#include <linux/interrupt.h>
25#include <linux/list.h>
26#include <linux/spinlock.h>
27#include <linux/slab.h>
28#include <linux/iommu.h>
29
30#include <asm/cacheflush.h>
31#include <asm/sizes.h>
32
33#include <mach/iommu_hw-8xxx.h>
34#include <mach/iommu.h>
35
36DEFINE_SPINLOCK(msm_iommu_lock);
37
38struct msm_priv {
39 unsigned long *pgtable;
40 struct list_head list_attached;
41};
42
43static void __flush_iotlb(struct iommu_domain *domain)
44{
45 struct msm_priv *priv = domain->priv;
46 struct msm_iommu_drvdata *iommu_drvdata;
47 struct msm_iommu_ctx_drvdata *ctx_drvdata;
48
49#ifndef CONFIG_IOMMU_PGTABLES_L2
50 unsigned long *fl_table = priv->pgtable;
51 int i;
52
53 dmac_flush_range(fl_table, fl_table + SZ_16K);
54
55 for (i = 0; i < NUM_FL_PTE; i++)
56 if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) {
57 void *sl_table = __va(fl_table[i] & FL_BASE_MASK);
58 dmac_flush_range(sl_table, sl_table + SZ_4K);
59 }
60#endif
61
62 list_for_each_entry(ctx_drvdata, &priv->list_attached, attached_elm) {
63 if (!ctx_drvdata->pdev || !ctx_drvdata->pdev->dev.parent)
64 BUG();
65
66 iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
67 SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0);
68 }
69}
70
71static void __reset_context(void __iomem *base, int ctx)
72{
73 SET_BPRCOSH(base, ctx, 0);
74 SET_BPRCISH(base, ctx, 0);
75 SET_BPRCNSH(base, ctx, 0);
76 SET_BPSHCFG(base, ctx, 0);
77 SET_BPMTCFG(base, ctx, 0);
78 SET_ACTLR(base, ctx, 0);
79 SET_SCTLR(base, ctx, 0);
80 SET_FSRRESTORE(base, ctx, 0);
81 SET_TTBR0(base, ctx, 0);
82 SET_TTBR1(base, ctx, 0);
83 SET_TTBCR(base, ctx, 0);
84 SET_BFBCR(base, ctx, 0);
85 SET_PAR(base, ctx, 0);
86 SET_FAR(base, ctx, 0);
87 SET_CTX_TLBIALL(base, ctx, 0);
88 SET_TLBFLPTER(base, ctx, 0);
89 SET_TLBSLPTER(base, ctx, 0);
90 SET_TLBLKCR(base, ctx, 0);
91 SET_PRRR(base, ctx, 0);
92 SET_NMRR(base, ctx, 0);
93 SET_CONTEXTIDR(base, ctx, 0);
94}
95
96static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable)
97{
98 __reset_context(base, ctx);
99
100 /* Set up HTW mode */
101 /* TLB miss configuration: perform HTW on miss */
102 SET_TLBMCFG(base, ctx, 0x3);
103
104 /* V2P configuration: HTW for access */
105 SET_V2PCFG(base, ctx, 0x3);
106
107 SET_TTBCR(base, ctx, 0);
108 SET_TTBR0_PA(base, ctx, (pgtable >> 14));
109
110 /* Invalidate the TLB for this context */
111 SET_CTX_TLBIALL(base, ctx, 0);
112
113 /* Set interrupt number to "secure" interrupt */
114 SET_IRPTNDX(base, ctx, 0);
115
116 /* Enable context fault interrupt */
117 SET_CFEIE(base, ctx, 1);
118
119 /* Stall access on a context fault and let the handler deal with it */
120 SET_CFCFG(base, ctx, 1);
121
122 /* Redirect all cacheable requests to L2 slave port. */
123 SET_RCISH(base, ctx, 1);
124 SET_RCOSH(base, ctx, 1);
125 SET_RCNSH(base, ctx, 1);
126
127 /* Turn on TEX Remap */
128 SET_TRE(base, ctx, 1);
129
130 /* Do not configure PRRR / NMRR on the IOMMU for now. We will assume
131 * TEX class 0 for everything until attributes are properly worked out
132 */
133 SET_PRRR(base, ctx, 0);
134 SET_NMRR(base, ctx, 0);
135
136 /* Turn on BFB prefetch */
137 SET_BFBDFE(base, ctx, 1);
138
139#ifdef CONFIG_IOMMU_PGTABLES_L2
140 /* Configure page tables as inner-cacheable and shareable to reduce
141 * the TLB miss penalty.
142 */
143 SET_TTBR0_SH(base, ctx, 1);
144 SET_TTBR1_SH(base, ctx, 1);
145
146 SET_TTBR0_NOS(base, ctx, 1);
147 SET_TTBR1_NOS(base, ctx, 1);
148
149 SET_TTBR0_IRGNH(base, ctx, 0); /* WB, WA */
150 SET_TTBR0_IRGNL(base, ctx, 1);
151
152 SET_TTBR1_IRGNH(base, ctx, 0); /* WB, WA */
153 SET_TTBR1_IRGNL(base, ctx, 1);
154
155 SET_TTBR0_ORGN(base, ctx, 1); /* WB, WA */
156 SET_TTBR1_ORGN(base, ctx, 1); /* WB, WA */
157#endif
158
159 /* Enable the MMU */
160 SET_M(base, ctx, 1);
161}
162
163static int msm_iommu_domain_init(struct iommu_domain *domain)
164{
165 struct msm_priv *priv = kzalloc(sizeof(*priv), GFP_KERNEL);
166
167 if (!priv)
168 goto fail_nomem;
169
170 INIT_LIST_HEAD(&priv->list_attached);
171 priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL,
172 get_order(SZ_16K));
173
174 if (!priv->pgtable)
175 goto fail_nomem;
176
177 memset(priv->pgtable, 0, SZ_16K);
178 domain->priv = priv;
179 return 0;
180
181fail_nomem:
182 kfree(priv);
183 return -ENOMEM;
184}
185
186static void msm_iommu_domain_destroy(struct iommu_domain *domain)
187{
188 struct msm_priv *priv;
189 unsigned long flags;
190 unsigned long *fl_table;
191 int i;
192
193 spin_lock_irqsave(&msm_iommu_lock, flags);
194 priv = domain->priv;
195 domain->priv = NULL;
196
197 if (priv) {
198 fl_table = priv->pgtable;
199
200 for (i = 0; i < NUM_FL_PTE; i++)
201 if ((fl_table[i] & 0x03) == FL_TYPE_TABLE)
202 free_page((unsigned long) __va(((fl_table[i]) &
203 FL_BASE_MASK)));
204
205 free_pages((unsigned long)priv->pgtable, get_order(SZ_16K));
206 priv->pgtable = NULL;
207 }
208
209 kfree(priv);
210 spin_unlock_irqrestore(&msm_iommu_lock, flags);
211}
212
213static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
214{
215 struct msm_priv *priv;
216 struct msm_iommu_ctx_dev *ctx_dev;
217 struct msm_iommu_drvdata *iommu_drvdata;
218 struct msm_iommu_ctx_drvdata *ctx_drvdata;
219 struct msm_iommu_ctx_drvdata *tmp_drvdata;
220 int ret = 0;
221 unsigned long flags;
222
223 spin_lock_irqsave(&msm_iommu_lock, flags);
224
225 priv = domain->priv;
226
227 if (!priv || !dev) {
228 ret = -EINVAL;
229 goto fail;
230 }
231
232 iommu_drvdata = dev_get_drvdata(dev->parent);
233 ctx_drvdata = dev_get_drvdata(dev);
234 ctx_dev = dev->platform_data;
235
236 if (!iommu_drvdata || !ctx_drvdata || !ctx_dev) {
237 ret = -EINVAL;
238 goto fail;
239 }
240
241 list_for_each_entry(tmp_drvdata, &priv->list_attached, attached_elm)
242 if (tmp_drvdata == ctx_drvdata) {
243 ret = -EBUSY;
244 goto fail;
245 }
246
247 __program_context(iommu_drvdata->base, ctx_dev->num,
248 __pa(priv->pgtable));
249
250 list_add(&(ctx_drvdata->attached_elm), &priv->list_attached);
251 __flush_iotlb(domain);
252
253fail:
254 spin_unlock_irqrestore(&msm_iommu_lock, flags);
255 return ret;
256}
257
258static void msm_iommu_detach_dev(struct iommu_domain *domain,
259 struct device *dev)
260{
261 struct msm_priv *priv;
262 struct msm_iommu_ctx_dev *ctx_dev;
263 struct msm_iommu_drvdata *iommu_drvdata;
264 struct msm_iommu_ctx_drvdata *ctx_drvdata;
265 unsigned long flags;
266
267 spin_lock_irqsave(&msm_iommu_lock, flags);
268 priv = domain->priv;
269
270 if (!priv || !dev)
271 goto fail;
272
273 iommu_drvdata = dev_get_drvdata(dev->parent);
274 ctx_drvdata = dev_get_drvdata(dev);
275 ctx_dev = dev->platform_data;
276
277 if (!iommu_drvdata || !ctx_drvdata || !ctx_dev)
278 goto fail;
279
280 __flush_iotlb(domain);
281 __reset_context(iommu_drvdata->base, ctx_dev->num);
282 list_del_init(&ctx_drvdata->attached_elm);
283
284fail:
285 spin_unlock_irqrestore(&msm_iommu_lock, flags);
286}
287
288static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
289 phys_addr_t pa, int order, int prot)
290{
291 struct msm_priv *priv;
292 unsigned long flags;
293 unsigned long *fl_table;
294 unsigned long *fl_pte;
295 unsigned long fl_offset;
296 unsigned long *sl_table;
297 unsigned long *sl_pte;
298 unsigned long sl_offset;
299 size_t len = 0x1000UL << order;
300 int ret = 0;
301
302 spin_lock_irqsave(&msm_iommu_lock, flags);
303 priv = domain->priv;
304
305 if (!priv) {
306 ret = -EINVAL;
307 goto fail;
308 }
309
310 fl_table = priv->pgtable;
311
312 if (len != SZ_16M && len != SZ_1M &&
313 len != SZ_64K && len != SZ_4K) {
314 pr_debug("Bad size: %d\n", len);
315 ret = -EINVAL;
316 goto fail;
317 }
318
319 if (!fl_table) {
320 pr_debug("Null page table\n");
321 ret = -EINVAL;
322 goto fail;
323 }
324
325 fl_offset = FL_OFFSET(va); /* Upper 12 bits */
326 fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */
327
328 if (len == SZ_16M) {
329 int i = 0;
330 for (i = 0; i < 16; i++)
331 *(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION |
332 FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT |
333 FL_SHARED;
334 }
335
336 if (len == SZ_1M)
337 *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE |
338 FL_TYPE_SECT | FL_SHARED;
339
340 /* Need a 2nd level table */
341 if ((len == SZ_4K || len == SZ_64K) && (*fl_pte) == 0) {
342 unsigned long *sl;
343 sl = (unsigned long *) __get_free_pages(GFP_KERNEL,
344 get_order(SZ_4K));
345
346 if (!sl) {
347 pr_debug("Could not allocate second level table\n");
348 ret = -ENOMEM;
349 goto fail;
350 }
351
352 memset(sl, 0, SZ_4K);
353 *fl_pte = ((((int)__pa(sl)) & FL_BASE_MASK) | FL_TYPE_TABLE);
354 }
355
356 sl_table = (unsigned long *) __va(((*fl_pte) & FL_BASE_MASK));
357 sl_offset = SL_OFFSET(va);
358 sl_pte = sl_table + sl_offset;
359
360
361 if (len == SZ_4K)
362 *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 |
363 SL_SHARED | SL_TYPE_SMALL;
364
365 if (len == SZ_64K) {
366 int i;
367
368 for (i = 0; i < 16; i++)
369 *(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 |
370 SL_AP1 | SL_SHARED | SL_TYPE_LARGE;
371 }
372
373 __flush_iotlb(domain);
374fail:
375 spin_unlock_irqrestore(&msm_iommu_lock, flags);
376 return ret;
377}
378
379static int msm_iommu_unmap(struct iommu_domain *domain, unsigned long va,
380 int order)
381{
382 struct msm_priv *priv;
383 unsigned long flags;
384 unsigned long *fl_table;
385 unsigned long *fl_pte;
386 unsigned long fl_offset;
387 unsigned long *sl_table;
388 unsigned long *sl_pte;
389 unsigned long sl_offset;
390 size_t len = 0x1000UL << order;
391 int i, ret = 0;
392
393 spin_lock_irqsave(&msm_iommu_lock, flags);
394
395 priv = domain->priv;
396
397 if (!priv) {
398 ret = -ENODEV;
399 goto fail;
400 }
401
402 fl_table = priv->pgtable;
403
404 if (len != SZ_16M && len != SZ_1M &&
405 len != SZ_64K && len != SZ_4K) {
406 pr_debug("Bad length: %d\n", len);
407 ret = -EINVAL;
408 goto fail;
409 }
410
411 if (!fl_table) {
412 pr_debug("Null page table\n");
413 ret = -EINVAL;
414 goto fail;
415 }
416
417 fl_offset = FL_OFFSET(va); /* Upper 12 bits */
418 fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */
419
420 if (*fl_pte == 0) {
421 pr_debug("First level PTE is 0\n");
422 ret = -ENODEV;
423 goto fail;
424 }
425
426 /* Unmap supersection */
427 if (len == SZ_16M)
428 for (i = 0; i < 16; i++)
429 *(fl_pte+i) = 0;
430
431 if (len == SZ_1M)
432 *fl_pte = 0;
433
434 sl_table = (unsigned long *) __va(((*fl_pte) & FL_BASE_MASK));
435 sl_offset = SL_OFFSET(va);
436 sl_pte = sl_table + sl_offset;
437
438 if (len == SZ_64K) {
439 for (i = 0; i < 16; i++)
440 *(sl_pte+i) = 0;
441 }
442
443 if (len == SZ_4K)
444 *sl_pte = 0;
445
446 if (len == SZ_4K || len == SZ_64K) {
447 int used = 0;
448
449 for (i = 0; i < NUM_SL_PTE; i++)
450 if (sl_table[i])
451 used = 1;
452 if (!used) {
453 free_page((unsigned long)sl_table);
454 *fl_pte = 0;
455 }
456 }
457
458 __flush_iotlb(domain);
459fail:
460 spin_unlock_irqrestore(&msm_iommu_lock, flags);
461 return ret;
462}
463
464static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
465 unsigned long va)
466{
467 struct msm_priv *priv;
468 struct msm_iommu_drvdata *iommu_drvdata;
469 struct msm_iommu_ctx_drvdata *ctx_drvdata;
470 unsigned int par;
471 unsigned long flags;
472 void __iomem *base;
473 phys_addr_t ret = 0;
474 int ctx;
475
476 spin_lock_irqsave(&msm_iommu_lock, flags);
477
478 priv = domain->priv;
479 if (list_empty(&priv->list_attached))
480 goto fail;
481
482 ctx_drvdata = list_entry(priv->list_attached.next,
483 struct msm_iommu_ctx_drvdata, attached_elm);
484 iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
485
486 base = iommu_drvdata->base;
487 ctx = ctx_drvdata->num;
488
489 /* Invalidate context TLB */
490 SET_CTX_TLBIALL(base, ctx, 0);
491 SET_V2PPR_VA(base, ctx, va >> V2Pxx_VA_SHIFT);
492
493 if (GET_FAULT(base, ctx))
494 goto fail;
495
496 par = GET_PAR(base, ctx);
497
498 /* We are dealing with a supersection */
499 if (GET_NOFAULT_SS(base, ctx))
500 ret = (par & 0xFF000000) | (va & 0x00FFFFFF);
501 else /* Upper 20 bits from PAR, lower 12 from VA */
502 ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
503
504fail:
505 spin_unlock_irqrestore(&msm_iommu_lock, flags);
506 return ret;
507}
508
509static int msm_iommu_domain_has_cap(struct iommu_domain *domain,
510 unsigned long cap)
511{
512 return 0;
513}
514
515static void print_ctx_regs(void __iomem *base, int ctx)
516{
517 unsigned int fsr = GET_FSR(base, ctx);
518 pr_err("FAR = %08x PAR = %08x\n",
519 GET_FAR(base, ctx), GET_PAR(base, ctx));
520 pr_err("FSR = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr,
521 (fsr & 0x02) ? "TF " : "",
522 (fsr & 0x04) ? "AFF " : "",
523 (fsr & 0x08) ? "APF " : "",
524 (fsr & 0x10) ? "TLBMF " : "",
525 (fsr & 0x20) ? "HTWDEEF " : "",
526 (fsr & 0x40) ? "HTWSEEF " : "",
527 (fsr & 0x80) ? "MHF " : "",
528 (fsr & 0x10000) ? "SL " : "",
529 (fsr & 0x40000000) ? "SS " : "",
530 (fsr & 0x80000000) ? "MULTI " : "");
531
532 pr_err("FSYNR0 = %08x FSYNR1 = %08x\n",
533 GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx));
534 pr_err("TTBR0 = %08x TTBR1 = %08x\n",
535 GET_TTBR0(base, ctx), GET_TTBR1(base, ctx));
536 pr_err("SCTLR = %08x ACTLR = %08x\n",
537 GET_SCTLR(base, ctx), GET_ACTLR(base, ctx));
538 pr_err("PRRR = %08x NMRR = %08x\n",
539 GET_PRRR(base, ctx), GET_NMRR(base, ctx));
540}
541
542irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
543{
544 struct msm_iommu_drvdata *drvdata = dev_id;
545 void __iomem *base;
546 unsigned int fsr = 0;
547 int ncb = 0, i = 0;
548
549 spin_lock(&msm_iommu_lock);
550
551 if (!drvdata) {
552 pr_err("Invalid device ID in context interrupt handler\n");
553 goto fail;
554 }
555
556 base = drvdata->base;
557
558 pr_err("===== WOAH! =====\n");
559 pr_err("Unexpected IOMMU page fault!\n");
560 pr_err("base = %08x\n", (unsigned int) base);
561
562 ncb = GET_NCB(base)+1;
563 for (i = 0; i < ncb; i++) {
564 fsr = GET_FSR(base, i);
565 if (fsr) {
566 pr_err("Fault occurred in context %d.\n", i);
567 pr_err("Interesting registers:\n");
568 print_ctx_regs(base, i);
569 SET_FSR(base, i, 0x4000000F);
570 }
571 }
572fail:
573 spin_unlock(&msm_iommu_lock);
574 return 0;
575}
576
577static struct iommu_ops msm_iommu_ops = {
578 .domain_init = msm_iommu_domain_init,
579 .domain_destroy = msm_iommu_domain_destroy,
580 .attach_dev = msm_iommu_attach_dev,
581 .detach_dev = msm_iommu_detach_dev,
582 .map = msm_iommu_map,
583 .unmap = msm_iommu_unmap,
584 .iova_to_phys = msm_iommu_iova_to_phys,
585 .domain_has_cap = msm_iommu_domain_has_cap
586};
587
588static int msm_iommu_init(void)
589{
590 register_iommu(&msm_iommu_ops);
591 return 0;
592}
593
594subsys_initcall(msm_iommu_init);
595
596MODULE_LICENSE("GPL v2");
597MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
diff --git a/arch/arm/mach-msm/iommu_dev.c b/arch/arm/mach-msm/iommu_dev.c
new file mode 100644
index 000000000000..c33ae786c41f
--- /dev/null
+++ b/arch/arm/mach-msm/iommu_dev.c
@@ -0,0 +1,374 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/io.h>
24#include <linux/clk.h>
25#include <linux/iommu.h>
26#include <linux/interrupt.h>
27#include <linux/err.h>
28#include <linux/slab.h>
29
30#include <mach/iommu_hw-8xxx.h>
31#include <mach/iommu.h>
32
33struct iommu_ctx_iter_data {
34 /* input */
35 const char *name;
36
37 /* output */
38 struct device *dev;
39};
40
41static struct platform_device *msm_iommu_root_dev;
42
43static int each_iommu_ctx(struct device *dev, void *data)
44{
45 struct iommu_ctx_iter_data *res = data;
46 struct msm_iommu_ctx_dev *c = dev->platform_data;
47
48 if (!res || !c || !c->name || !res->name)
49 return -EINVAL;
50
51 if (!strcmp(res->name, c->name)) {
52 res->dev = dev;
53 return 1;
54 }
55 return 0;
56}
57
58static int each_iommu(struct device *dev, void *data)
59{
60 return device_for_each_child(dev, data, each_iommu_ctx);
61}
62
63struct device *msm_iommu_get_ctx(const char *ctx_name)
64{
65 struct iommu_ctx_iter_data r;
66 int found;
67
68 if (!msm_iommu_root_dev) {
69 pr_err("No root IOMMU device.\n");
70 goto fail;
71 }
72
73 r.name = ctx_name;
74 found = device_for_each_child(&msm_iommu_root_dev->dev, &r, each_iommu);
75
76 if (!found) {
77 pr_err("Could not find context <%s>\n", ctx_name);
78 goto fail;
79 }
80
81 return r.dev;
82fail:
83 return NULL;
84}
85EXPORT_SYMBOL(msm_iommu_get_ctx);
86
87static void msm_iommu_reset(void __iomem *base)
88{
89 int ctx, ncb;
90
91 SET_RPUE(base, 0);
92 SET_RPUEIE(base, 0);
93 SET_ESRRESTORE(base, 0);
94 SET_TBE(base, 0);
95 SET_CR(base, 0);
96 SET_SPDMBE(base, 0);
97 SET_TESTBUSCR(base, 0);
98 SET_TLBRSW(base, 0);
99 SET_GLOBAL_TLBIALL(base, 0);
100 SET_RPU_ACR(base, 0);
101 SET_TLBLKCRWE(base, 1);
102 ncb = GET_NCB(base)+1;
103
104 for (ctx = 0; ctx < ncb; ctx++) {
105 SET_BPRCOSH(base, ctx, 0);
106 SET_BPRCISH(base, ctx, 0);
107 SET_BPRCNSH(base, ctx, 0);
108 SET_BPSHCFG(base, ctx, 0);
109 SET_BPMTCFG(base, ctx, 0);
110 SET_ACTLR(base, ctx, 0);
111 SET_SCTLR(base, ctx, 0);
112 SET_FSRRESTORE(base, ctx, 0);
113 SET_TTBR0(base, ctx, 0);
114 SET_TTBR1(base, ctx, 0);
115 SET_TTBCR(base, ctx, 0);
116 SET_BFBCR(base, ctx, 0);
117 SET_PAR(base, ctx, 0);
118 SET_FAR(base, ctx, 0);
119 SET_CTX_TLBIALL(base, ctx, 0);
120 SET_TLBFLPTER(base, ctx, 0);
121 SET_TLBSLPTER(base, ctx, 0);
122 SET_TLBLKCR(base, ctx, 0);
123 SET_PRRR(base, ctx, 0);
124 SET_NMRR(base, ctx, 0);
125 SET_CONTEXTIDR(base, ctx, 0);
126 }
127}
128
129static int msm_iommu_probe(struct platform_device *pdev)
130{
131 struct resource *r;
132 struct clk *iommu_clk;
133 struct msm_iommu_drvdata *drvdata;
134 struct msm_iommu_dev *iommu_dev = pdev->dev.platform_data;
135 void __iomem *regs_base;
136 resource_size_t len;
137 int ret = 0, ncb, nm2v, irq;
138
139 if (pdev->id != -1) {
140 drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
141
142 if (!drvdata) {
143 ret = -ENOMEM;
144 goto fail;
145 }
146
147 if (!iommu_dev) {
148 ret = -ENODEV;
149 goto fail;
150 }
151
152 if (iommu_dev->clk_rate != 0) {
153 iommu_clk = clk_get(&pdev->dev, "iommu_clk");
154
155 if (IS_ERR(iommu_clk)) {
156 ret = -ENODEV;
157 goto fail;
158 }
159
160 if (iommu_dev->clk_rate > 0) {
161 ret = clk_set_rate(iommu_clk,
162 iommu_dev->clk_rate);
163 if (ret) {
164 clk_put(iommu_clk);
165 goto fail;
166 }
167 }
168
169 ret = clk_enable(iommu_clk);
170 if (ret) {
171 clk_put(iommu_clk);
172 goto fail;
173 }
174 clk_put(iommu_clk);
175 }
176
177 r = platform_get_resource_byname(pdev, IORESOURCE_MEM,
178 "physbase");
179 if (!r) {
180 ret = -ENODEV;
181 goto fail;
182 }
183
184 len = r->end - r->start + 1;
185
186 r = request_mem_region(r->start, len, r->name);
187 if (!r) {
188 pr_err("Could not request memory region: "
189 "start=%p, len=%d\n", (void *) r->start, len);
190 ret = -EBUSY;
191 goto fail;
192 }
193
194 regs_base = ioremap(r->start, len);
195
196 if (!regs_base) {
197 pr_err("Could not ioremap: start=%p, len=%d\n",
198 (void *) r->start, len);
199 ret = -EBUSY;
200 goto fail;
201 }
202
203 irq = platform_get_irq_byname(pdev, "secure_irq");
204 if (irq < 0) {
205 ret = -ENODEV;
206 goto fail;
207 }
208
209 mb();
210
211 if (GET_IDR(regs_base) == 0) {
212 pr_err("Invalid IDR value detected\n");
213 ret = -ENODEV;
214 goto fail;
215 }
216
217 ret = request_irq(irq, msm_iommu_fault_handler, 0,
218 "msm_iommu_secure_irpt_handler", drvdata);
219 if (ret) {
220 pr_err("Request IRQ %d failed with ret=%d\n", irq, ret);
221 goto fail;
222 }
223
224 msm_iommu_reset(regs_base);
225 drvdata->base = regs_base;
226 drvdata->irq = irq;
227
228 nm2v = GET_NM2VCBMT((unsigned long) regs_base);
229 ncb = GET_NCB((unsigned long) regs_base);
230
231 pr_info("device %s mapped at %p, irq %d with %d ctx banks\n",
232 iommu_dev->name, regs_base, irq, ncb+1);
233
234 platform_set_drvdata(pdev, drvdata);
235 } else
236 msm_iommu_root_dev = pdev;
237
238 return 0;
239
240fail:
241 kfree(drvdata);
242 return ret;
243}
244
245static int msm_iommu_remove(struct platform_device *pdev)
246{
247 struct msm_iommu_drvdata *drv = NULL;
248
249 drv = platform_get_drvdata(pdev);
250 if (drv) {
251 memset(drv, 0, sizeof(struct msm_iommu_drvdata));
252 kfree(drv);
253 platform_set_drvdata(pdev, NULL);
254 }
255 return 0;
256}
257
258static int msm_iommu_ctx_probe(struct platform_device *pdev)
259{
260 struct msm_iommu_ctx_dev *c = pdev->dev.platform_data;
261 struct msm_iommu_drvdata *drvdata;
262 struct msm_iommu_ctx_drvdata *ctx_drvdata = NULL;
263 int i, ret = 0;
264 if (!c || !pdev->dev.parent) {
265 ret = -EINVAL;
266 goto fail;
267 }
268
269 drvdata = dev_get_drvdata(pdev->dev.parent);
270
271 if (!drvdata) {
272 ret = -ENODEV;
273 goto fail;
274 }
275
276 ctx_drvdata = kzalloc(sizeof(*ctx_drvdata), GFP_KERNEL);
277 if (!ctx_drvdata) {
278 ret = -ENOMEM;
279 goto fail;
280 }
281 ctx_drvdata->num = c->num;
282 ctx_drvdata->pdev = pdev;
283
284 INIT_LIST_HEAD(&ctx_drvdata->attached_elm);
285 platform_set_drvdata(pdev, ctx_drvdata);
286
287 /* Program the M2V tables for this context */
288 for (i = 0; i < MAX_NUM_MIDS; i++) {
289 int mid = c->mids[i];
290 if (mid == -1)
291 break;
292
293 SET_M2VCBR_N(drvdata->base, mid, 0);
294 SET_CBACR_N(drvdata->base, c->num, 0);
295
296 /* Set VMID = MID */
297 SET_VMID(drvdata->base, mid, mid);
298
299 /* Set the context number for that MID to this context */
300 SET_CBNDX(drvdata->base, mid, c->num);
301
302 /* Set MID associated with this context bank */
303 SET_CBVMID(drvdata->base, c->num, mid);
304
305 /* Set security bit override to be Non-secure */
306 SET_NSCFG(drvdata->base, mid, 3);
307 }
308
309 pr_info("context device %s with bank index %d\n", c->name, c->num);
310
311 return 0;
312fail:
313 kfree(ctx_drvdata);
314 return ret;
315}
316
317static int msm_iommu_ctx_remove(struct platform_device *pdev)
318{
319 struct msm_iommu_ctx_drvdata *drv = NULL;
320 drv = platform_get_drvdata(pdev);
321 if (drv) {
322 memset(drv, 0, sizeof(struct msm_iommu_ctx_drvdata));
323 kfree(drv);
324 platform_set_drvdata(pdev, NULL);
325 }
326 return 0;
327}
328
329static struct platform_driver msm_iommu_driver = {
330 .driver = {
331 .name = "msm_iommu",
332 },
333 .probe = msm_iommu_probe,
334 .remove = msm_iommu_remove,
335};
336
337static struct platform_driver msm_iommu_ctx_driver = {
338 .driver = {
339 .name = "msm_iommu_ctx",
340 },
341 .probe = msm_iommu_ctx_probe,
342 .remove = msm_iommu_ctx_remove,
343};
344
345static int msm_iommu_driver_init(void)
346{
347 int ret;
348 ret = platform_driver_register(&msm_iommu_driver);
349 if (ret != 0) {
350 pr_err("Failed to register IOMMU driver\n");
351 goto error;
352 }
353
354 ret = platform_driver_register(&msm_iommu_ctx_driver);
355 if (ret != 0) {
356 pr_err("Failed to register IOMMU context driver\n");
357 goto error;
358 }
359
360error:
361 return ret;
362}
363
364static void msm_iommu_driver_exit(void)
365{
366 platform_driver_unregister(&msm_iommu_ctx_driver);
367 platform_driver_unregister(&msm_iommu_driver);
368}
369
370subsys_initcall(msm_iommu_driver_init);
371module_exit(msm_iommu_driver_exit);
372
373MODULE_LICENSE("GPL v2");
374MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index dec5ca622d7d..7689848ec680 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -28,7 +28,6 @@
28#ifndef MSM_DGT_BASE 28#ifndef MSM_DGT_BASE
29#define MSM_DGT_BASE (MSM_GPT_BASE + 0x10) 29#define MSM_DGT_BASE (MSM_GPT_BASE + 0x10)
30#endif 30#endif
31#define MSM_DGT_SHIFT (5)
32 31
33#define TIMER_MATCH_VAL 0x0000 32#define TIMER_MATCH_VAL 0x0000
34#define TIMER_COUNT_VAL 0x0004 33#define TIMER_COUNT_VAL 0x0004
@@ -36,12 +35,28 @@
36#define TIMER_ENABLE_CLR_ON_MATCH_EN 2 35#define TIMER_ENABLE_CLR_ON_MATCH_EN 2
37#define TIMER_ENABLE_EN 1 36#define TIMER_ENABLE_EN 1
38#define TIMER_CLEAR 0x000C 37#define TIMER_CLEAR 0x000C
39 38#define DGT_CLK_CTL 0x0034
39enum {
40 DGT_CLK_CTL_DIV_1 = 0,
41 DGT_CLK_CTL_DIV_2 = 1,
42 DGT_CLK_CTL_DIV_3 = 2,
43 DGT_CLK_CTL_DIV_4 = 3,
44};
40#define CSR_PROTECTION 0x0020 45#define CSR_PROTECTION 0x0020
41#define CSR_PROTECTION_EN 1 46#define CSR_PROTECTION_EN 1
42 47
43#define GPT_HZ 32768 48#define GPT_HZ 32768
49
50#if defined(CONFIG_ARCH_QSD8X50)
51#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
52#define MSM_DGT_SHIFT (0)
53#elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60)
54#define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
55#define MSM_DGT_SHIFT (0)
56#else
44#define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */ 57#define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
58#define MSM_DGT_SHIFT (5)
59#endif
45 60
46struct msm_clock { 61struct msm_clock {
47 struct clock_event_device clockevent; 62 struct clock_event_device clockevent;
@@ -170,6 +185,10 @@ static void __init msm_timer_init(void)
170 int i; 185 int i;
171 int res; 186 int res;
172 187
188#ifdef CONFIG_ARCH_MSM8X60
189 writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
190#endif
191
173 for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) { 192 for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
174 struct msm_clock *clock = &msm_clocks[i]; 193 struct msm_clock *clock = &msm_clocks[i];
175 struct clock_event_device *ce = &clock->clockevent; 194 struct clock_event_device *ce = &clock->clockevent;
diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
index 61e5e583603b..29e390e89ff4 100644
--- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
+++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
@@ -145,8 +145,6 @@ subsys_initcall(wxl_pci_init);
145 145
146MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL") 146MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL")
147 /* Maintainer: Sebastien Requiem <sebastien@requiem.fr> */ 147 /* Maintainer: Sebastien Requiem <sebastien@requiem.fr> */
148 .phys_io = MV78XX0_REGS_PHYS_BASE,
149 .io_pg_offst = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc,
150 .boot_params = 0x00000100, 148 .boot_params = 0x00000100,
151 .init_machine = wxl_init, 149 .init_machine = wxl_init,
152 .map_io = mv78xx0_map_io, 150 .map_io = mv78xx0_map_io,
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
index efdabe04c69e..207c95e403b9 100644
--- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
@@ -93,8 +93,6 @@ subsys_initcall(db78x00_pci_init);
93 93
94MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board") 94MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
95 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ 95 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
96 .phys_io = MV78XX0_REGS_PHYS_BASE,
97 .io_pg_offst = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc,
98 .boot_params = 0x00000100, 96 .boot_params = 0x00000100,
99 .init_machine = db78x00_init, 97 .init_machine = db78x00_init,
100 .map_io = mv78xx0_map_io, 98 .map_io = mv78xx0_map_io,
diff --git a/arch/arm/mach-mv78xx0/include/mach/debug-macro.S b/arch/arm/mach-mv78xx0/include/mach/debug-macro.S
index cd81689c4621..04891428e48b 100644
--- a/arch/arm/mach-mv78xx0/include/mach/debug-macro.S
+++ b/arch/arm/mach-mv78xx0/include/mach/debug-macro.S
@@ -8,12 +8,11 @@
8 8
9#include <mach/mv78xx0.h> 9#include <mach/mv78xx0.h>
10 10
11 .macro addruart, rx, tmp 11 .macro addruart, rp, rv
12 mrc p15, 0, \rx, c1, c0 12 ldr \rp, =MV78XX0_REGS_PHYS_BASE
13 tst \rx, #1 @ MMU enabled? 13 ldr \rv, =MV78XX0_REGS_VIRT_BASE
14 ldreq \rx, =MV78XX0_REGS_PHYS_BASE 14 orr \rp, \rp, #0x00012000
15 ldrne \rx, =MV78XX0_REGS_VIRT_BASE 15 orr \rv, \rv, #0x00012000
16 orr \rx, \rx, #0x00012000
17 .endm 16 .endm
18 17
19#define UART_SHIFT 2 18#define UART_SHIFT 2
diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
index e136b7a03355..3511ad4d973b 100644
--- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
+++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
@@ -78,8 +78,6 @@ subsys_initcall(rd78x00_pci_init);
78 78
79MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board") 79MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board")
80 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ 80 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
81 .phys_io = MV78XX0_REGS_PHYS_BASE,
82 .io_pg_offst = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc,
83 .boot_params = 0x00000100, 81 .boot_params = 0x00000100,
84 .init_machine = rd78x00_masa_init, 82 .init_machine = rd78x00_masa_init,
85 .map_io = mv78xx0_map_io, 83 .map_io = mv78xx0_map_io,
diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
index c71a7bc19284..aa57e35ce3cd 100644
--- a/arch/arm/mach-mx25/Kconfig
+++ b/arch/arm/mach-mx25/Kconfig
@@ -12,6 +12,8 @@ config MACH_EUKREA_CPUIMX25
12 select IMX_HAVE_PLATFORM_IMX_I2C 12 select IMX_HAVE_PLATFORM_IMX_I2C
13 select IMX_HAVE_PLATFORM_IMX_UART 13 select IMX_HAVE_PLATFORM_IMX_UART
14 select IMX_HAVE_PLATFORM_MXC_NAND 14 select IMX_HAVE_PLATFORM_MXC_NAND
15 select IMX_HAVE_PLATFORM_FLEXCAN
16 select IMX_HAVE_PLATFORM_ESDHC
15 select MXC_ULPI if USB_ULPI 17 select MXC_ULPI if USB_ULPI
16 18
17choice 19choice
@@ -20,8 +22,8 @@ choice
20 default MACH_EUKREA_MBIMXSD25_BASEBOARD 22 default MACH_EUKREA_MBIMXSD25_BASEBOARD
21 23
22config MACH_EUKREA_MBIMXSD25_BASEBOARD 24config MACH_EUKREA_MBIMXSD25_BASEBOARD
23 prompt "Eukrea MBIMXSD development board" 25 bool "Eukrea MBIMXSD development board"
24 bool 26 select IMX_HAVE_PLATFORM_IMX_SSI
25 help 27 help
26 This adds board specific devices that can be found on Eukrea's 28 This adds board specific devices that can be found on Eukrea's
27 MBIMXSD evaluation board. 29 MBIMXSD evaluation board.
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 40c7cc41cee3..9e4a5578c2fb 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -72,7 +72,7 @@ unsigned long get_rate_arm(struct clk *clk)
72 unsigned long rate = get_rate_mpll(); 72 unsigned long rate = get_rate_mpll();
73 73
74 if (cctl & (1 << 14)) 74 if (cctl & (1 << 14))
75 rate = (rate * 3) >> 1; 75 rate = (rate * 3) >> 2;
76 76
77 return rate / ((cctl >> 30) + 1); 77 return rate / ((cctl >> 30) + 1);
78} 78}
@@ -99,7 +99,7 @@ static unsigned long get_rate_per(int per)
99 if (readl(CRM_BASE + 0x64) & (1 << per)) 99 if (readl(CRM_BASE + 0x64) & (1 << per))
100 fref = get_rate_upll(); 100 fref = get_rate_upll();
101 else 101 else
102 fref = get_rate_ipg(NULL); 102 fref = get_rate_ahb(NULL);
103 103
104 return fref / (val + 1); 104 return fref / (val + 1);
105} 105}
@@ -139,6 +139,16 @@ static unsigned long get_rate_lcdc(struct clk *clk)
139 return get_rate_per(7); 139 return get_rate_per(7);
140} 140}
141 141
142static unsigned long get_rate_esdhc1(struct clk *clk)
143{
144 return get_rate_per(3);
145}
146
147static unsigned long get_rate_esdhc2(struct clk *clk)
148{
149 return get_rate_per(4);
150}
151
142static unsigned long get_rate_csi(struct clk *clk) 152static unsigned long get_rate_csi(struct clk *clk)
143{ 153{
144 return get_rate_per(0); 154 return get_rate_per(0);
@@ -213,6 +223,12 @@ DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL);
213DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL); 223DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL);
214DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL); 224DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL);
215DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL); 225DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL);
226DEFINE_CLOCK(esdhc1_ahb_clk, 0, CCM_CGCR0, 21, get_rate_esdhc1, NULL, NULL);
227DEFINE_CLOCK(esdhc1_per_clk, 0, CCM_CGCR0, 3, get_rate_esdhc1, NULL,
228 &esdhc1_ahb_clk);
229DEFINE_CLOCK(esdhc2_ahb_clk, 0, CCM_CGCR0, 22, get_rate_esdhc2, NULL, NULL);
230DEFINE_CLOCK(esdhc2_per_clk, 0, CCM_CGCR0, 4, get_rate_esdhc2, NULL,
231 &esdhc2_ahb_clk);
216DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL); 232DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL);
217DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL); 233DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL, NULL, NULL);
218DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk); 234DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0, 7, NULL, NULL, &lcdc_ahb_clk);
@@ -238,10 +254,14 @@ DEFINE_CLOCK(lcdc_clk, 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
238DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL); 254DEFINE_CLOCK(wdt_clk, 0, CCM_CGCR2, 19, get_rate_ipg, NULL, NULL);
239DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk); 255DEFINE_CLOCK(ssi1_clk, 0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
240DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk); 256DEFINE_CLOCK(ssi2_clk, 1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
257DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGCR1, 13, get_rate_esdhc1, NULL,
258 &esdhc1_per_clk);
259DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGCR1, 14, get_rate_esdhc2, NULL,
260 &esdhc2_per_clk);
241DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL); 261DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
242DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk); 262DEFINE_CLOCK(csi_clk, 0, CCM_CGCR1, 4, get_rate_csi, NULL, &csi_per_clk);
243DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL); 263DEFINE_CLOCK(can1_clk, 0, CCM_CGCR1, 2, get_rate_ipg, NULL, NULL);
244DEFINE_CLOCK(can2_clk, 0, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL); 264DEFINE_CLOCK(can2_clk, 1, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL);
245 265
246#define _REGISTER_CLOCK(d, n, c) \ 266#define _REGISTER_CLOCK(d, n, c) \
247 { \ 267 { \
@@ -261,9 +281,9 @@ static struct clk_lookup lookups[] = {
261 _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk) 281 _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
262 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk) 282 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
263 _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) 283 _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
264 _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) 284 _REGISTER_CLOCK("imx25-cspi.0", NULL, cspi1_clk)
265 _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) 285 _REGISTER_CLOCK("imx25-cspi.1", NULL, cspi2_clk)
266 _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk) 286 _REGISTER_CLOCK("imx25-cspi.2", NULL, cspi3_clk)
267 _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk) 287 _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk)
268 _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk) 288 _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
269 _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk) 289 _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
@@ -279,6 +299,8 @@ static struct clk_lookup lookups[] = {
279 _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk) 299 _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk)
280 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) 300 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
281 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) 301 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
302 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
303 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
282 _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk) 304 _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
283 _REGISTER_CLOCK(NULL, "audmux", audmux_clk) 305 _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
284 _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) 306 _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h
index d86a7c3ca8b0..93afa10b13cf 100644
--- a/arch/arm/mach-mx25/devices-imx25.h
+++ b/arch/arm/mach-mx25/devices-imx25.h
@@ -9,35 +9,46 @@
9#include <mach/mx25.h> 9#include <mach/mx25.h>
10#include <mach/devices-common.h> 10#include <mach/devices-common.h>
11 11
12extern const struct imx_fec_data imx25_fec_data __initconst;
13#define imx25_add_fec(pdata) \
14 imx_add_fec(&imx25_fec_data, pdata)
15
12#define imx25_add_flexcan0(pdata) \ 16#define imx25_add_flexcan0(pdata) \
13 imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata) 17 imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata)
14#define imx25_add_flexcan1(pdata) \ 18#define imx25_add_flexcan1(pdata) \
15 imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata) 19 imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata)
16 20
17#define imx25_add_imx_i2c0(pdata) \ 21extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst;
18 imx_add_imx_i2c(0, MX25_I2C1_BASE_ADDR, SZ_16K, MX25_INT_I2C1, pdata) 22#define imx25_add_imx_i2c(id, pdata) \
19#define imx25_add_imx_i2c1(pdata) \ 23 imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata)
20 imx_add_imx_i2c(1, MX25_I2C2_BASE_ADDR, SZ_16K, MX25_INT_I2C2, pdata) 24#define imx25_add_imx_i2c0(pdata) imx25_add_imx_i2c(0, pdata)
21#define imx25_add_imx_i2c2(pdata) \ 25#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata)
22 imx_add_imx_i2c(2, MX25_I2C3_BASE_ADDR, SZ_16K, MX25_INT_I2C3, pdata) 26#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata)
23 27
24#define imx25_add_imx_uart0(pdata) \ 28extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst;
25 imx_add_imx_uart_1irq(0, MX25_UART1_BASE_ADDR, SZ_16K, MX25_INT_UART1, pdata) 29#define imx25_add_imx_ssi(id, pdata) \
26#define imx25_add_imx_uart1(pdata) \ 30 imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata)
27 imx_add_imx_uart_1irq(1, MX25_UART2_BASE_ADDR, SZ_16K, MX25_INT_UART2, pdata) 31
28#define imx25_add_imx_uart2(pdata) \ 32extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst;
29 imx_add_imx_uart_1irq(2, MX25_UART3_BASE_ADDR, SZ_16K, MX25_INT_UART3, pdata) 33#define imx25_add_imx_uart(id, pdata) \
30#define imx25_add_imx_uart3(pdata) \ 34 imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata)
31 imx_add_imx_uart_1irq(3, MX25_UART4_BASE_ADDR, SZ_16K, MX25_INT_UART4, pdata) 35#define imx25_add_imx_uart0(pdata) imx25_add_imx_uart(0, pdata)
32#define imx25_add_imx_uart4(pdata) \ 36#define imx25_add_imx_uart1(pdata) imx25_add_imx_uart(1, pdata)
33 imx_add_imx_uart_1irq(4, MX25_UART5_BASE_ADDR, SZ_16K, MX25_INT_UART5, pdata) 37#define imx25_add_imx_uart2(pdata) imx25_add_imx_uart(2, pdata)
38#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata)
39#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata)
34 40
41extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst;
35#define imx25_add_mxc_nand(pdata) \ 42#define imx25_add_mxc_nand(pdata) \
36 imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata) 43 imx_add_mxc_nand(&imx25_mxc_nand_data, pdata)
37 44
38#define imx25_add_spi_imx0(pdata) \ 45extern const struct imx_spi_imx_data imx25_spi_imx_data[] __initconst;
39 imx_add_spi_imx(0, MX25_CSPI1_BASE_ADDR, SZ_16K, MX25_INT_CSPI1, pdata) 46#define imx25_add_spi_imx(id, pdata) \
40#define imx25_add_spi_imx1(pdata) \ 47 imx_add_spi_imx(&imx25_spi_imx_data[id], pdata)
41 imx_add_spi_imx(1, MX25_CSPI2_BASE_ADDR, SZ_16K, MX25_INT_CSPI2, pdata) 48#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata)
42#define imx25_add_spi_imx2(pdata) \ 49#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata)
43 imx_add_spi_imx(2, MX25_CSPI3_BASE_ADDR, SZ_16K, MX25_INT_CSPI3, pdata) 50#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata)
51
52extern const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst;
53#define imx25_add_esdhc(id, pdata) \
54 imx_add_esdhc(&imx25_esdhc_data[id], pdata)
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index 3468eb15b236..1d0eb3e85941 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -208,26 +208,6 @@ int __init imx25_register_gpios(void)
208 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); 208 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
209} 209}
210 210
211static struct resource mx25_fec_resources[] = {
212 {
213 .start = MX25_FEC_BASE_ADDR,
214 .end = MX25_FEC_BASE_ADDR + 0xfff,
215 .flags = IORESOURCE_MEM,
216 },
217 {
218 .start = MX25_INT_FEC,
219 .end = MX25_INT_FEC,
220 .flags = IORESOURCE_IRQ,
221 },
222};
223
224struct platform_device mx25_fec_device = {
225 .name = "fec",
226 .id = 0,
227 .num_resources = ARRAY_SIZE(mx25_fec_resources),
228 .resource = mx25_fec_resources,
229};
230
231static struct resource mx25_rtc_resources[] = { 211static struct resource mx25_rtc_resources[] = {
232 { 212 {
233 .start = MX25_DRYICE_BASE_ADDR, 213 .start = MX25_DRYICE_BASE_ADDR,
@@ -305,44 +285,6 @@ struct platform_device mx25_kpp_device = {
305 .resource = mx25_kpp_resources, 285 .resource = mx25_kpp_resources,
306}; 286};
307 287
308static struct resource imx_ssi_resources0[] = {
309 {
310 .start = MX25_SSI1_BASE_ADDR,
311 .end = MX25_SSI1_BASE_ADDR + 0x3fff,
312 .flags = IORESOURCE_MEM,
313 }, {
314 .start = MX25_INT_SSI1,
315 .end = MX25_INT_SSI1,
316 .flags = IORESOURCE_IRQ,
317 },
318};
319
320static struct resource imx_ssi_resources1[] = {
321 {
322 .start = MX25_SSI2_BASE_ADDR,
323 .end = MX25_SSI2_BASE_ADDR + 0x3fff,
324 .flags = IORESOURCE_MEM
325 }, {
326 .start = MX25_INT_SSI2,
327 .end = MX25_INT_SSI2,
328 .flags = IORESOURCE_IRQ,
329 },
330};
331
332struct platform_device imx_ssi_device0 = {
333 .name = "imx-ssi",
334 .id = 0,
335 .num_resources = ARRAY_SIZE(imx_ssi_resources0),
336 .resource = imx_ssi_resources0,
337};
338
339struct platform_device imx_ssi_device1 = {
340 .name = "imx-ssi",
341 .id = 1,
342 .num_resources = ARRAY_SIZE(imx_ssi_resources1),
343 .resource = imx_ssi_resources1,
344};
345
346static struct resource mx25_csi_resources[] = { 288static struct resource mx25_csi_resources[] = {
347 { 289 {
348 .start = MX25_CSI_BASE_ADDR, 290 .start = MX25_CSI_BASE_ADDR,
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
index 4aceb68e35a7..7b70a43c3a4b 100644
--- a/arch/arm/mach-mx25/devices.h
+++ b/arch/arm/mach-mx25/devices.h
@@ -6,11 +6,8 @@ extern struct platform_device mxc_pwm_device1;
6extern struct platform_device mxc_pwm_device2; 6extern struct platform_device mxc_pwm_device2;
7extern struct platform_device mxc_pwm_device3; 7extern struct platform_device mxc_pwm_device3;
8extern struct platform_device mxc_keypad_device; 8extern struct platform_device mxc_keypad_device;
9extern struct platform_device mx25_fec_device;
10extern struct platform_device mx25_rtc_device; 9extern struct platform_device mx25_rtc_device;
11extern struct platform_device mx25_fb_device; 10extern struct platform_device mx25_fb_device;
12extern struct platform_device mxc_wdt; 11extern struct platform_device mxc_wdt;
13extern struct platform_device mx25_kpp_device; 12extern struct platform_device mx25_kpp_device;
14extern struct platform_device imx_ssi_device0;
15extern struct platform_device imx_ssi_device1;
16extern struct platform_device mx25_csi_device; 13extern struct platform_device mx25_csi_device;
diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
index 4aaadc753d3e..e765ac5d9a08 100644
--- a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
@@ -34,7 +34,6 @@
34#include <mach/mx25.h> 34#include <mach/mx25.h>
35#include <mach/imx-uart.h> 35#include <mach/imx-uart.h>
36#include <mach/imxfb.h> 36#include <mach/imxfb.h>
37#include <mach/ssi.h>
38#include <mach/audmux.h> 37#include <mach/audmux.h>
39 38
40#include "devices-imx25.h" 39#include "devices-imx25.h"
@@ -90,6 +89,9 @@ static struct pad_desc eukrea_mbimxsd_pads[] = {
90 MX25_PAD_KPP_COL2__AUD5_TXC, 89 MX25_PAD_KPP_COL2__AUD5_TXC,
91 MX25_PAD_KPP_COL1__AUD5_RXD, 90 MX25_PAD_KPP_COL1__AUD5_RXD,
92 MX25_PAD_KPP_COL0__AUD5_TXD, 91 MX25_PAD_KPP_COL0__AUD5_TXD,
92 /* CAN */
93 MX25_PAD_GPIO_D__CAN2_RX,
94 MX25_PAD_GPIO_C__CAN2_TX,
93}; 95};
94 96
95#define GPIO_LED1 83 97#define GPIO_LED1 83
@@ -114,6 +116,38 @@ static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
114 }, 116 },
115 .bpp = 16, 117 .bpp = 16,
116 .pcr = 0xCAD08B80, 118 .pcr = 0xCAD08B80,
119 }, {
120 .mode = {
121 .name = "DVI-VGA",
122 .refresh = 60,
123 .xres = 640,
124 .yres = 480,
125 .pixclock = 32000,
126 .hsync_len = 7,
127 .left_margin = 100,
128 .right_margin = 100,
129 .vsync_len = 7,
130 .upper_margin = 7,
131 .lower_margin = 100,
132 },
133 .pcr = 0xFA208B80,
134 .bpp = 16,
135 }, {
136 .mode = {
137 .name = "DVI-SVGA",
138 .refresh = 60,
139 .xres = 800,
140 .yres = 600,
141 .pixclock = 25000,
142 .hsync_len = 7,
143 .left_margin = 75,
144 .right_margin = 75,
145 .vsync_len = 7,
146 .upper_margin = 7,
147 .lower_margin = 75,
148 },
149 .pcr = 0xFA208B80,
150 .bpp = 16,
117 }, 151 },
118}; 152};
119 153
@@ -205,7 +239,8 @@ static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
205 }, 239 },
206}; 240};
207 241
208struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = { 242static const
243struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
209 .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, 244 .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
210}; 245};
211 246
@@ -239,7 +274,10 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
239 274
240 imx25_add_imx_uart1(&uart_pdata); 275 imx25_add_imx_uart1(&uart_pdata);
241 mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata); 276 mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata);
242 mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata); 277 imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
278
279 imx25_add_flexcan1(NULL);
280 imx25_add_esdhc(0, NULL);
243 281
244 gpio_request(GPIO_LED1, "LED1"); 282 gpio_request(GPIO_LED1, "LED1");
245 gpio_direction_output(GPIO_LED1, 1); 283 gpio_direction_output(GPIO_LED1, 1);
diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-mx25/mach-cpuimx25.c
index e064bb3d6919..f6f9ad60c25e 100644
--- a/arch/arm/mach-mx25/mach-cpuimx25.c
+++ b/arch/arm/mach-mx25/mach-cpuimx25.c
@@ -23,7 +23,6 @@
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/irq.h> 24#include <linux/irq.h>
25#include <linux/gpio.h> 25#include <linux/gpio.h>
26#include <linux/fec.h>
27#include <linux/platform_device.h> 26#include <linux/platform_device.h>
28#include <linux/usb/otg.h> 27#include <linux/usb/otg.h>
29#include <linux/usb/ulpi.h> 28#include <linux/usb/ulpi.h>
@@ -41,7 +40,6 @@
41#include <mach/mxc_nand.h> 40#include <mach/mxc_nand.h>
42#include <mach/imxfb.h> 41#include <mach/imxfb.h>
43#include <mach/mxc_ehci.h> 42#include <mach/mxc_ehci.h>
44#include <mach/ulpi.h>
45#include <mach/iomux-mx25.h> 43#include <mach/iomux-mx25.h>
46 44
47#include "devices-imx25.h" 45#include "devices-imx25.h"
@@ -67,7 +65,7 @@ static struct pad_desc eukrea_cpuimx25_pads[] = {
67 MX25_PAD_I2C1_DAT__I2C1_DAT, 65 MX25_PAD_I2C1_DAT__I2C1_DAT,
68}; 66};
69 67
70static struct fec_platform_data mx25_fec_pdata = { 68static const struct fec_platform_data mx25_fec_pdata __initconst = {
71 .phy = PHY_INTERFACE_MODE_RMII, 69 .phy = PHY_INTERFACE_MODE_RMII,
72}; 70};
73 71
@@ -129,24 +127,19 @@ static void __init eukrea_cpuimx25_init(void)
129 imx25_add_imx_uart0(&uart_pdata); 127 imx25_add_imx_uart0(&uart_pdata);
130 imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info); 128 imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
131 mxc_register_device(&mx25_rtc_device, NULL); 129 mxc_register_device(&mx25_rtc_device, NULL);
132 mxc_register_device(&mx25_fec_device, &mx25_fec_pdata); 130 imx25_add_fec(&mx25_fec_pdata);
133 131
134 i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices, 132 i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
135 ARRAY_SIZE(eukrea_cpuimx25_i2c_devices)); 133 ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
136 imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data); 134 imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
137 135
138#if defined(CONFIG_USB_ULPI) 136 if (otg_mode_host)
139 if (otg_mode_host) {
140 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
141 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
142
143 mxc_register_device(&mxc_otg, &otg_pdata); 137 mxc_register_device(&mxc_otg, &otg_pdata);
144 } 138 else
145 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
146#endif
147 if (!otg_mode_host)
148 mxc_register_device(&otg_udc_device, &otg_device_pdata); 139 mxc_register_device(&otg_udc_device, &otg_device_pdata);
149 140
141 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
142
150#ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD 143#ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD
151 eukrea_mbimxsd25_baseboard_init(); 144 eukrea_mbimxsd25_baseboard_init();
152#endif 145#endif
@@ -163,8 +156,6 @@ static struct sys_timer eukrea_cpuimx25_timer = {
163 156
164MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25") 157MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25")
165 /* Maintainer: Eukrea Electromatique */ 158 /* Maintainer: Eukrea Electromatique */
166 .phys_io = MX25_AIPS1_BASE_ADDR,
167 .io_pg_offst = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
168 .boot_params = MX25_PHYS_OFFSET + 0x100, 159 .boot_params = MX25_PHYS_OFFSET + 0x100,
169 .map_io = mx25_map_io, 160 .map_io = mx25_map_io,
170 .init_irq = mx25_init_irq, 161 .init_irq = mx25_init_irq,
diff --git a/arch/arm/mach-mx25/mach-mx25_3ds.c b/arch/arm/mach-mx25/mach-mx25_3ds.c
index 62bc21f11a71..80805107a73e 100644
--- a/arch/arm/mach-mx25/mach-mx25_3ds.c
+++ b/arch/arm/mach-mx25/mach-mx25_3ds.c
@@ -28,7 +28,6 @@
28#include <linux/clk.h> 28#include <linux/clk.h>
29#include <linux/irq.h> 29#include <linux/irq.h>
30#include <linux/gpio.h> 30#include <linux/gpio.h>
31#include <linux/fec.h>
32#include <linux/platform_device.h> 31#include <linux/platform_device.h>
33#include <linux/input/matrix_keypad.h> 32#include <linux/input/matrix_keypad.h>
34 33
@@ -99,7 +98,7 @@ static struct pad_desc mx25pdk_pads[] = {
99 MX25_PAD_KPP_COL3__KPP_COL3, 98 MX25_PAD_KPP_COL3__KPP_COL3,
100}; 99};
101 100
102static struct fec_platform_data mx25_fec_pdata = { 101static const struct fec_platform_data mx25_fec_pdata __initconst = {
103 .phy = PHY_INTERFACE_MODE_RMII, 102 .phy = PHY_INTERFACE_MODE_RMII,
104}; 103};
105 104
@@ -192,7 +191,7 @@ static void __init mx25pdk_init(void)
192 mxc_register_device(&mxc_wdt, NULL); 191 mxc_register_device(&mxc_wdt, NULL);
193 192
194 mx25pdk_fec_reset(); 193 mx25pdk_fec_reset();
195 mxc_register_device(&mx25_fec_device, &mx25_fec_pdata); 194 imx25_add_fec(&mx25_fec_pdata);
196 mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data); 195 mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data);
197} 196}
198 197
@@ -207,8 +206,6 @@ static struct sys_timer mx25pdk_timer = {
207 206
208MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)") 207MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
209 /* Maintainer: Freescale Semiconductor, Inc. */ 208 /* Maintainer: Freescale Semiconductor, Inc. */
210 .phys_io = MX25_AIPS1_BASE_ADDR,
211 .io_pg_offst = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
212 .boot_params = MX25_PHYS_OFFSET + 0x100, 209 .boot_params = MX25_PHYS_OFFSET + 0x100,
213 .map_io = mx25_map_io, 210 .map_io = mx25_map_io,
214 .init_irq = mx25_init_irq, 211 .init_irq = mx25_init_irq,
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 85beece802aa..096fd33f8ab9 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -9,6 +9,7 @@ config ARCH_MX35
9 bool 9 bool
10 select ARCH_MXC_IOMUX_V3 10 select ARCH_MXC_IOMUX_V3
11 select ARCH_MXC_AUDMUX_V2 11 select ARCH_MXC_AUDMUX_V2
12 select HAVE_EPIT
12 13
13comment "MX3 platforms:" 14comment "MX3 platforms:"
14 15
@@ -16,6 +17,7 @@ config MACH_MX31ADS
16 bool "Support MX31ADS platforms" 17 bool "Support MX31ADS platforms"
17 select ARCH_MX31 18 select ARCH_MX31
18 select IMX_HAVE_PLATFORM_IMX_I2C 19 select IMX_HAVE_PLATFORM_IMX_I2C
20 select IMX_HAVE_PLATFORM_IMX_SSI
19 select IMX_HAVE_PLATFORM_IMX_UART 21 select IMX_HAVE_PLATFORM_IMX_UART
20 default y 22 default y
21 help 23 help
@@ -117,9 +119,11 @@ config MACH_PCM043
117 bool "Support Phytec pcm043 (i.MX35) platforms" 119 bool "Support Phytec pcm043 (i.MX35) platforms"
118 select ARCH_MX35 120 select ARCH_MX35
119 select IMX_HAVE_PLATFORM_IMX_I2C 121 select IMX_HAVE_PLATFORM_IMX_I2C
122 select IMX_HAVE_PLATFORM_IMX_SSI
120 select IMX_HAVE_PLATFORM_IMX_UART 123 select IMX_HAVE_PLATFORM_IMX_UART
121 select IMX_HAVE_PLATFORM_MXC_NAND 124 select IMX_HAVE_PLATFORM_MXC_NAND
122 select IMX_HAVE_PLATFORM_FLEXCAN 125 select IMX_HAVE_PLATFORM_FLEXCAN
126 select IMX_HAVE_PLATFORM_ESDHC
123 select MXC_ULPI if USB_ULPI 127 select MXC_ULPI if USB_ULPI
124 help 128 help
125 Include support for Phytec pcm043 platform. This includes 129 Include support for Phytec pcm043 platform. This includes
@@ -140,6 +144,7 @@ config MACH_MX35_3DS
140 bool "Support MX35PDK platform" 144 bool "Support MX35PDK platform"
141 select ARCH_MX35 145 select ARCH_MX35
142 select IMX_HAVE_PLATFORM_IMX_UART 146 select IMX_HAVE_PLATFORM_IMX_UART
147 select IMX_HAVE_PLATFORM_MXC_NAND
143 default n 148 default n
144 help 149 help
145 Include support for MX35PDK platform. This includes specific 150 Include support for MX35PDK platform. This includes specific
@@ -159,6 +164,8 @@ config MACH_EUKREA_CPUIMX35
159 select IMX_HAVE_PLATFORM_IMX_UART 164 select IMX_HAVE_PLATFORM_IMX_UART
160 select IMX_HAVE_PLATFORM_IMX_I2C 165 select IMX_HAVE_PLATFORM_IMX_I2C
161 select IMX_HAVE_PLATFORM_MXC_NAND 166 select IMX_HAVE_PLATFORM_MXC_NAND
167 select IMX_HAVE_PLATFORM_FLEXCAN
168 select IMX_HAVE_PLATFORM_ESDHC
162 select MXC_ULPI if USB_ULPI 169 select MXC_ULPI if USB_ULPI
163 help 170 help
164 Include support for Eukrea CPUIMX35 platform. This includes 171 Include support for Eukrea CPUIMX35 platform. This includes
@@ -170,8 +177,8 @@ choice
170 default MACH_EUKREA_MBIMXSD35_BASEBOARD 177 default MACH_EUKREA_MBIMXSD35_BASEBOARD
171 178
172config MACH_EUKREA_MBIMXSD35_BASEBOARD 179config MACH_EUKREA_MBIMXSD35_BASEBOARD
173 prompt "Eukrea MBIMXSD development board" 180 bool "Eukrea MBIMXSD development board"
174 bool 181 select IMX_HAVE_PLATFORM_IMX_SSI
175 help 182 help
176 This adds board specific devices that can be found on Eukrea's 183 This adds board specific devices that can be found on Eukrea's
177 MBIMXSD evaluation board. 184 MBIMXSD evaluation board.
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 2bd7beceb991..8a182d0a3fcf 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -7,7 +7,6 @@
7obj-y := mm.o devices.o cpu.o 7obj-y := mm.o devices.o cpu.o
8CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS 8CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
9CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS 9CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
10CFLAGS_cpu.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
11obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o 10obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o
12obj-$(CONFIG_ARCH_MX35) += clock-imx35.o 11obj-$(CONFIG_ARCH_MX35) += clock-imx35.o
13obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o 12obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-mx3/clock-imx31.c
index 9a9eb6de6127..109e98f323e0 100644
--- a/arch/arm/mach-mx3/clock-imx31.c
+++ b/arch/arm/mach-mx3/clock-imx31.c
@@ -477,7 +477,7 @@ DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk);
477DEFINE_CLOCK(epit2_clk, 1, MXC_CCM_CGR0, 8, NULL, NULL, &perclk_clk); 477DEFINE_CLOCK(epit2_clk, 1, MXC_CCM_CGR0, 8, NULL, NULL, &perclk_clk);
478DEFINE_CLOCK(iim_clk, 0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk); 478DEFINE_CLOCK(iim_clk, 0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
479DEFINE_CLOCK(ata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk); 479DEFINE_CLOCK(ata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
480DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, &sdma_clk1, &ahb_clk); 480DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk);
481DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk); 481DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk);
482DEFINE_CLOCK(rng_clk, 0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk); 482DEFINE_CLOCK(rng_clk, 0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk);
483DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk); 483DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk);
@@ -525,9 +525,9 @@ DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk);
525 525
526static struct clk_lookup lookups[] = { 526static struct clk_lookup lookups[] = {
527 _REGISTER_CLOCK(NULL, "emi", emi_clk) 527 _REGISTER_CLOCK(NULL, "emi", emi_clk)
528 _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) 528 _REGISTER_CLOCK("imx31-cspi.0", NULL, cspi1_clk)
529 _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) 529 _REGISTER_CLOCK("imx31-cspi.1", NULL, cspi2_clk)
530 _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk) 530 _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk)
531 _REGISTER_CLOCK(NULL, "gpt", gpt_clk) 531 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
532 _REGISTER_CLOCK(NULL, "pwm", pwm_clk) 532 _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
533 _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) 533 _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
@@ -564,7 +564,7 @@ static struct clk_lookup lookups[] = {
564 _REGISTER_CLOCK(NULL, "ata", ata_clk) 564 _REGISTER_CLOCK(NULL, "ata", ata_clk)
565 _REGISTER_CLOCK(NULL, "rtic", rtic_clk) 565 _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
566 _REGISTER_CLOCK(NULL, "rng", rng_clk) 566 _REGISTER_CLOCK(NULL, "rng", rng_clk)
567 _REGISTER_CLOCK(NULL, "sdma_ahb", sdma_clk1) 567 _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk1)
568 _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2) 568 _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2)
569 _REGISTER_CLOCK(NULL, "mstick", mstick1_clk) 569 _REGISTER_CLOCK(NULL, "mstick", mstick1_clk)
570 _REGISTER_CLOCK(NULL, "mstick", mstick2_clk) 570 _REGISTER_CLOCK(NULL, "mstick", mstick2_clk)
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index 7a62e744a8b0..61e4a318980a 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -364,8 +364,8 @@ DEFINE_CLOCK(cspi2_clk, 1, CCM_CGR0, 12, get_rate_ipg, NULL);
364DEFINE_CLOCK(ect_clk, 0, CCM_CGR0, 14, get_rate_ipg, NULL); 364DEFINE_CLOCK(ect_clk, 0, CCM_CGR0, 14, get_rate_ipg, NULL);
365DEFINE_CLOCK(edio_clk, 0, CCM_CGR0, 16, NULL, NULL); 365DEFINE_CLOCK(edio_clk, 0, CCM_CGR0, 16, NULL, NULL);
366DEFINE_CLOCK(emi_clk, 0, CCM_CGR0, 18, get_rate_ipg, NULL); 366DEFINE_CLOCK(emi_clk, 0, CCM_CGR0, 18, get_rate_ipg, NULL);
367DEFINE_CLOCK(epit1_clk, 0, CCM_CGR0, 20, get_rate_ipg_per, NULL); 367DEFINE_CLOCK(epit1_clk, 0, CCM_CGR0, 20, get_rate_ipg, NULL);
368DEFINE_CLOCK(epit2_clk, 1, CCM_CGR0, 22, get_rate_ipg_per, NULL); 368DEFINE_CLOCK(epit2_clk, 1, CCM_CGR0, 22, get_rate_ipg, NULL);
369DEFINE_CLOCK(esai_clk, 0, CCM_CGR0, 24, NULL, NULL); 369DEFINE_CLOCK(esai_clk, 0, CCM_CGR0, 24, NULL, NULL);
370DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL); 370DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL);
371DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL); 371DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL);
@@ -451,17 +451,17 @@ static struct clk_lookup lookups[] = {
451 _REGISTER_CLOCK(NULL, "ata", ata_clk) 451 _REGISTER_CLOCK(NULL, "ata", ata_clk)
452 _REGISTER_CLOCK("flexcan.0", NULL, can1_clk) 452 _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
453 _REGISTER_CLOCK("flexcan.1", NULL, can2_clk) 453 _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
454 _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) 454 _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk)
455 _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) 455 _REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk)
456 _REGISTER_CLOCK(NULL, "ect", ect_clk) 456 _REGISTER_CLOCK(NULL, "ect", ect_clk)
457 _REGISTER_CLOCK(NULL, "edio", edio_clk) 457 _REGISTER_CLOCK(NULL, "edio", edio_clk)
458 _REGISTER_CLOCK(NULL, "emi", emi_clk) 458 _REGISTER_CLOCK(NULL, "emi", emi_clk)
459 _REGISTER_CLOCK(NULL, "epit", epit1_clk) 459 _REGISTER_CLOCK("imx-epit.0", NULL, epit1_clk)
460 _REGISTER_CLOCK(NULL, "epit", epit2_clk) 460 _REGISTER_CLOCK("imx-epit.1", NULL, epit2_clk)
461 _REGISTER_CLOCK(NULL, "esai", esai_clk) 461 _REGISTER_CLOCK(NULL, "esai", esai_clk)
462 _REGISTER_CLOCK(NULL, "sdhc", esdhc1_clk) 462 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
463 _REGISTER_CLOCK(NULL, "sdhc", esdhc2_clk) 463 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
464 _REGISTER_CLOCK(NULL, "sdhc", esdhc3_clk) 464 _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk)
465 _REGISTER_CLOCK("fec.0", NULL, fec_clk) 465 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
466 _REGISTER_CLOCK(NULL, "gpio", gpio1_clk) 466 _REGISTER_CLOCK(NULL, "gpio", gpio1_clk)
467 _REGISTER_CLOCK(NULL, "gpio", gpio2_clk) 467 _REGISTER_CLOCK(NULL, "gpio", gpio2_clk)
@@ -482,7 +482,7 @@ static struct clk_lookup lookups[] = {
482 _REGISTER_CLOCK(NULL, "rtc", rtc_clk) 482 _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
483 _REGISTER_CLOCK(NULL, "rtic", rtic_clk) 483 _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
484 _REGISTER_CLOCK(NULL, "scc", scc_clk) 484 _REGISTER_CLOCK(NULL, "scc", scc_clk)
485 _REGISTER_CLOCK(NULL, "sdma", sdma_clk) 485 _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
486 _REGISTER_CLOCK(NULL, "spba", spba_clk) 486 _REGISTER_CLOCK(NULL, "spba", spba_clk)
487 _REGISTER_CLOCK(NULL, "spdif", spdif_clk) 487 _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
488 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) 488 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
@@ -535,8 +535,16 @@ int __init mx35_clocks_init()
535 __raw_writel(cgr2, CCM_BASE + CCM_CGR2); 535 __raw_writel(cgr2, CCM_BASE + CCM_CGR2);
536 __raw_writel(cgr3, CCM_BASE + CCM_CGR3); 536 __raw_writel(cgr3, CCM_BASE + CCM_CGR3);
537 537
538 clk_enable(&iim_clk);
539 mx35_read_cpu_rev();
540
541#ifdef CONFIG_MXC_USE_EPIT
542 epit_timer_init(&epit1_clk,
543 MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
544#else
538 mxc_timer_init(&gpt_clk, 545 mxc_timer_init(&gpt_clk,
539 MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT); 546 MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
547#endif
540 548
541 return 0; 549 return 0;
542} 550}
diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c
index 861afe0fe3ad..d00a75457812 100644
--- a/arch/arm/mach-mx3/cpu.c
+++ b/arch/arm/mach-mx3/cpu.c
@@ -25,15 +25,15 @@ struct mx3_cpu_type {
25}; 25};
26 26
27static struct mx3_cpu_type mx31_cpu_type[] __initdata = { 27static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
28 { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = CHIP_REV_1_0 }, 28 { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = MX3x_CHIP_REV_1_0 },
29 { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = CHIP_REV_1_1 }, 29 { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = MX3x_CHIP_REV_1_1 },
30 { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = CHIP_REV_1_1 }, 30 { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = MX3x_CHIP_REV_1_1 },
31 { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = CHIP_REV_1_1 }, 31 { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = MX3x_CHIP_REV_1_1 },
32 { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = CHIP_REV_1_1 }, 32 { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = MX3x_CHIP_REV_1_1 },
33 { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = CHIP_REV_1_2 }, 33 { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = MX3x_CHIP_REV_1_2 },
34 { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = CHIP_REV_1_2 }, 34 { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = MX3x_CHIP_REV_1_2 },
35 { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = CHIP_REV_2_0 }, 35 { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = MX3x_CHIP_REV_2_0 },
36 { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = CHIP_REV_2_0 }, 36 { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = MX3x_CHIP_REV_2_0 },
37}; 37};
38 38
39void __init mx31_read_cpu_rev(void) 39void __init mx31_read_cpu_rev(void)
@@ -41,7 +41,7 @@ void __init mx31_read_cpu_rev(void)
41 u32 i, srev; 41 u32 i, srev;
42 42
43 /* read SREV register from IIM module */ 43 /* read SREV register from IIM module */
44 srev = __raw_readl(IO_ADDRESS(IIM_BASE_ADDR + MXC_IIMSREV)); 44 srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
45 45
46 for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++) 46 for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
47 if (srev == mx31_cpu_type[i].srev) { 47 if (srev == mx31_cpu_type[i].srev) {
@@ -55,3 +55,30 @@ void __init mx31_read_cpu_rev(void)
55 55
56 printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev); 56 printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
57} 57}
58
59unsigned int mx35_cpu_rev;
60EXPORT_SYMBOL(mx35_cpu_rev);
61
62void __init mx35_read_cpu_rev(void)
63{
64 u32 rev;
65 char *srev = "unknown";
66
67 rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
68 switch (rev) {
69 case 0x00:
70 mx35_cpu_rev = MX3x_CHIP_REV_1_0;
71 srev = "1.0";
72 break;
73 case 0x10:
74 mx35_cpu_rev = MX3x_CHIP_REV_2_0;
75 srev = "2.0";
76 break;
77 case 0x11:
78 mx35_cpu_rev = MX3x_CHIP_REV_2_1;
79 srev = "2.1";
80 break;
81 }
82
83 printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
84}
diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h
index 3b1a44a20585..de9598590eba 100644
--- a/arch/arm/mach-mx3/devices-imx31.h
+++ b/arch/arm/mach-mx3/devices-imx31.h
@@ -9,30 +9,33 @@
9#include <mach/mx31.h> 9#include <mach/mx31.h>
10#include <mach/devices-common.h> 10#include <mach/devices-common.h>
11 11
12#define imx31_add_imx_i2c0(pdata) \ 12extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst;
13 imx_add_imx_i2c(0, MX31_I2C1_BASE_ADDR, SZ_4K, MX31_INT_I2C1, pdata) 13#define imx31_add_imx_i2c(id, pdata) \
14#define imx31_add_imx_i2c1(pdata) \ 14 imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata)
15 imx_add_imx_i2c(1, MX31_I2C2_BASE_ADDR, SZ_4K, MX31_INT_I2C2, pdata) 15#define imx31_add_imx_i2c0(pdata) imx31_add_imx_i2c(0, pdata)
16#define imx31_add_imx_i2c2(pdata) \ 16#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata)
17 imx_add_imx_i2c(2, MX31_I2C3_BASE_ADDR, SZ_4K, MX31_INT_I2C3, pdata) 17#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata)
18 18
19#define imx31_add_imx_uart0(pdata) \ 19extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst;
20 imx_add_imx_uart_1irq(0, MX31_UART1_BASE_ADDR, SZ_16K, MX31_INT_UART1, pdata) 20#define imx31_add_imx_ssi(id, pdata) \
21#define imx31_add_imx_uart1(pdata) \ 21 imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata)
22 imx_add_imx_uart_1irq(1, MX31_UART2_BASE_ADDR, SZ_16K, MX31_INT_UART2, pdata)
23#define imx31_add_imx_uart2(pdata) \
24 imx_add_imx_uart_1irq(2, MX31_UART3_BASE_ADDR, SZ_16K, MX31_INT_UART3, pdata)
25#define imx31_add_imx_uart3(pdata) \
26 imx_add_imx_uart_1irq(3, MX31_UART4_BASE_ADDR, SZ_16K, MX31_INT_UART4, pdata)
27#define imx31_add_imx_uart4(pdata) \
28 imx_add_imx_uart_1irq(4, MX31_UART5_BASE_ADDR, SZ_16K, MX31_INT_UART5, pdata)
29 22
23extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst;
24#define imx31_add_imx_uart(id, pdata) \
25 imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata)
26#define imx31_add_imx_uart0(pdata) imx31_add_imx_uart(0, pdata)
27#define imx31_add_imx_uart1(pdata) imx31_add_imx_uart(1, pdata)
28#define imx31_add_imx_uart2(pdata) imx31_add_imx_uart(2, pdata)
29#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata)
30#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata)
31
32extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst;
30#define imx31_add_mxc_nand(pdata) \ 33#define imx31_add_mxc_nand(pdata) \
31 imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata) 34 imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
32 35
33#define imx31_add_spi_imx0(pdata) \ 36extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst;
34 imx_add_spi_imx(0, MX31_CSPI1_BASE_ADDR, SZ_4K, MX31_INT_CSPI1, pdata) 37#define imx31_add_cspi(id, pdata) \
35#define imx31_add_spi_imx1(pdata) \ 38 imx_add_spi_imx(&imx31_cspi_data[id], pdata)
36 imx_add_spi_imx(1, MX31_CSPI2_BASE_ADDR, SZ_4K, MX31_INT_CSPI2, pdata) 39#define imx31_add_spi_imx0(pdata) imx31_add_cspi(0, pdata)
37#define imx31_add_spi_imx2(pdata) \ 40#define imx31_add_spi_imx1(pdata) imx31_add_cspi(1, pdata)
38 imx_add_spi_imx(2, MX31_CSPI3_BASE_ADDR, SZ_4K, MX31_INT_CSPI3, pdata) 41#define imx31_add_spi_imx2(pdata) imx31_add_cspi(2, pdata)
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
index f6a431a4c3d2..5eb917b638d0 100644
--- a/arch/arm/mach-mx3/devices-imx35.h
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -9,29 +9,43 @@
9#include <mach/mx35.h> 9#include <mach/mx35.h>
10#include <mach/devices-common.h> 10#include <mach/devices-common.h>
11 11
12extern const struct imx_fec_data imx35_fec_data __initconst;
13#define imx35_add_fec(pdata) \
14 imx_add_fec(&imx35_fec_data, pdata)
15
12#define imx35_add_flexcan0(pdata) \ 16#define imx35_add_flexcan0(pdata) \
13 imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata) 17 imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata)
14#define imx35_add_flexcan1(pdata) \ 18#define imx35_add_flexcan1(pdata) \
15 imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata) 19 imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata)
16 20
17#define imx35_add_imx_i2c0(pdata) \ 21extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
18 imx_add_imx_i2c(0, MX35_I2C1_BASE_ADDR, SZ_4K, MX35_INT_I2C1, pdata) 22#define imx35_add_imx_i2c(id, pdata) \
19#define imx35_add_imx_i2c1(pdata) \ 23 imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata)
20 imx_add_imx_i2c(1, MX35_I2C2_BASE_ADDR, SZ_4K, MX35_INT_I2C2, pdata) 24#define imx35_add_imx_i2c0(pdata) imx35_add_imx_i2c(0, pdata)
21#define imx35_add_imx_i2c2(pdata) \ 25#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata)
22 imx_add_imx_i2c(2, MX35_I2C3_BASE_ADDR, SZ_4K, MX35_INT_I2C3, pdata) 26#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata)
27
28extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst;
29#define imx35_add_imx_ssi(id, pdata) \
30 imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata)
23 31
24#define imx35_add_imx_uart0(pdata) \ 32extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst;
25 imx_add_imx_uart_1irq(0, MX35_UART1_BASE_ADDR, SZ_16K, MX35_INT_UART1, pdata) 33#define imx35_add_imx_uart(id, pdata) \
26#define imx35_add_imx_uart1(pdata) \ 34 imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata)
27 imx_add_imx_uart_1irq(1, MX35_UART2_BASE_ADDR, SZ_16K, MX35_INT_UART2, pdata) 35#define imx35_add_imx_uart0(pdata) imx35_add_imx_uart(0, pdata)
28#define imx35_add_imx_uart2(pdata) \ 36#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata)
29 imx_add_imx_uart_1irq(2, MX35_UART3_BASE_ADDR, SZ_16K, MX35_INT_UART3, pdata) 37#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata)
30 38
39extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst;
31#define imx35_add_mxc_nand(pdata) \ 40#define imx35_add_mxc_nand(pdata) \
32 imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata) 41 imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
42
43extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst;
44#define imx35_add_cspi(id, pdata) \
45 imx_add_spi_imx(&imx35_cspi_data[id], pdata)
46#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata)
47#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata)
33 48
34#define imx35_add_spi_imx0(pdata) \ 49extern const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst;
35 imx_add_spi_imx(0, MX35_CSPI1_BASE_ADDR, SZ_4K, MX35_INT_CSPI1, pdata) 50#define imx35_add_esdhc(id, pdata) \
36#define imx35_add_spi_imx1(pdata) \ 51 imx_add_esdhc(&imx35_esdhc_data[id], pdata)
37 imx_add_spi_imx(1, MX35_CSPI2_BASE_ADDR, SZ_4K, MX35_INT_CSPI2, pdata)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index a4fd1a26fc91..f4dff11aaee7 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -281,65 +281,6 @@ struct platform_device mxc_usbh2 = {
281 .num_resources = ARRAY_SIZE(mxc_usbh2_resources), 281 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
282}; 282};
283 283
284#if defined(CONFIG_ARCH_MX35)
285static struct resource mxc_fec_resources[] = {
286 {
287 .start = MXC_FEC_BASE_ADDR,
288 .end = MXC_FEC_BASE_ADDR + 0xfff,
289 .flags = IORESOURCE_MEM,
290 }, {
291 .start = MXC_INT_FEC,
292 .end = MXC_INT_FEC,
293 .flags = IORESOURCE_IRQ,
294 },
295};
296
297struct platform_device mxc_fec_device = {
298 .name = "fec",
299 .id = 0,
300 .num_resources = ARRAY_SIZE(mxc_fec_resources),
301 .resource = mxc_fec_resources,
302};
303#endif
304
305static struct resource imx_ssi_resources0[] = {
306 {
307 .start = SSI1_BASE_ADDR,
308 .end = SSI1_BASE_ADDR + 0xfff,
309 .flags = IORESOURCE_MEM,
310 }, {
311 .start = MX31_INT_SSI1,
312 .end = MX31_INT_SSI1,
313 .flags = IORESOURCE_IRQ,
314 },
315};
316
317static struct resource imx_ssi_resources1[] = {
318 {
319 .start = SSI2_BASE_ADDR,
320 .end = SSI2_BASE_ADDR + 0xfff,
321 .flags = IORESOURCE_MEM
322 }, {
323 .start = MX31_INT_SSI2,
324 .end = MX31_INT_SSI2,
325 .flags = IORESOURCE_IRQ,
326 },
327};
328
329struct platform_device imx_ssi_device0 = {
330 .name = "imx-ssi",
331 .id = 0,
332 .num_resources = ARRAY_SIZE(imx_ssi_resources0),
333 .resource = imx_ssi_resources0,
334};
335
336struct platform_device imx_ssi_device1 = {
337 .name = "imx-ssi",
338 .id = 1,
339 .num_resources = ARRAY_SIZE(imx_ssi_resources1),
340 .resource = imx_ssi_resources1,
341};
342
343static struct resource imx_wdt_resources[] = { 284static struct resource imx_wdt_resources[] = {
344 { 285 {
345 .flags = IORESOURCE_MEM, 286 .flags = IORESOURCE_MEM,
@@ -410,10 +351,6 @@ static int __init mx3_devices_init(void)
410 mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff; 351 mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
411 mxc_usbh1_resources[1].start = MXC_INT_USBHS; 352 mxc_usbh1_resources[1].start = MXC_INT_USBHS;
412 mxc_usbh1_resources[1].end = MXC_INT_USBHS; 353 mxc_usbh1_resources[1].end = MXC_INT_USBHS;
413 imx_ssi_resources0[1].start = MX35_INT_SSI1;
414 imx_ssi_resources0[1].end = MX35_INT_SSI1;
415 imx_ssi_resources1[1].start = MX35_INT_SSI2;
416 imx_ssi_resources1[1].end = MX35_INT_SSI2;
417 imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR; 354 imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
418 imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff; 355 imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
419 } 356 }
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index e5535234839f..585f814473d5 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -2,7 +2,6 @@ extern struct platform_device mxc_w1_master_device;
2extern struct platform_device mx3_ipu; 2extern struct platform_device mx3_ipu;
3extern struct platform_device mx3_fb; 3extern struct platform_device mx3_fb;
4extern struct platform_device mx3_camera; 4extern struct platform_device mx3_camera;
5extern struct platform_device mxc_fec_device;
6extern struct platform_device mxcsdhc_device0; 5extern struct platform_device mxcsdhc_device0;
7extern struct platform_device mxcsdhc_device1; 6extern struct platform_device mxcsdhc_device1;
8extern struct platform_device mxc_otg_udc_device; 7extern struct platform_device mxc_otg_udc_device;
@@ -10,9 +9,6 @@ extern struct platform_device mxc_otg_host;
10extern struct platform_device mxc_usbh1; 9extern struct platform_device mxc_usbh1;
11extern struct platform_device mxc_usbh2; 10extern struct platform_device mxc_usbh2;
12extern struct platform_device mxc_rnga_device; 11extern struct platform_device mxc_rnga_device;
13extern struct platform_device imx_ssi_device0;
14extern struct platform_device imx_ssi_device1;
15extern struct platform_device imx_ssi_device1;
16extern struct platform_device imx_wdt_device0; 12extern struct platform_device imx_wdt_device0;
17extern struct platform_device imx_rtc_device0; 13extern struct platform_device imx_rtc_device0;
18extern struct platform_device imx_kpp_device; 14extern struct platform_device imx_kpp_device;
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
index f8f15e3ac7a0..1abc10d52922 100644
--- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
@@ -43,14 +43,13 @@
43#include <mach/ipu.h> 43#include <mach/ipu.h>
44#include <mach/mx3fb.h> 44#include <mach/mx3fb.h>
45#include <mach/audmux.h> 45#include <mach/audmux.h>
46#include <mach/ssi.h>
47 46
48#include "devices-imx35.h" 47#include "devices-imx35.h"
49#include "devices.h" 48#include "devices.h"
50 49
51static const struct fb_videomode fb_modedb[] = { 50static const struct fb_videomode fb_modedb[] = {
52 { 51 {
53 .name = "CMO_QVGA", 52 .name = "CMO-QVGA",
54 .refresh = 60, 53 .refresh = 60,
55 .xres = 320, 54 .xres = 320,
56 .yres = 240, 55 .yres = 240,
@@ -65,6 +64,40 @@ static const struct fb_videomode fb_modedb[] = {
65 .vmode = FB_VMODE_NONINTERLACED, 64 .vmode = FB_VMODE_NONINTERLACED,
66 .flag = 0, 65 .flag = 0,
67 }, 66 },
67 {
68 .name = "DVI-VGA",
69 .refresh = 60,
70 .xres = 640,
71 .yres = 480,
72 .pixclock = 32000,
73 .left_margin = 100,
74 .right_margin = 100,
75 .upper_margin = 7,
76 .lower_margin = 100,
77 .hsync_len = 7,
78 .vsync_len = 7,
79 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT |
80 FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
81 .vmode = FB_VMODE_NONINTERLACED,
82 .flag = 0,
83 },
84 {
85 .name = "DVI-SVGA",
86 .refresh = 60,
87 .xres = 800,
88 .yres = 600,
89 .pixclock = 25000,
90 .left_margin = 75,
91 .right_margin = 75,
92 .upper_margin = 7,
93 .lower_margin = 75,
94 .hsync_len = 7,
95 .vsync_len = 7,
96 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT |
97 FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
98 .vmode = FB_VMODE_NONINTERLACED,
99 .flag = 0,
100 },
68}; 101};
69 102
70static struct ipu_platform_data mx3_ipu_data = { 103static struct ipu_platform_data mx3_ipu_data = {
@@ -73,7 +106,7 @@ static struct ipu_platform_data mx3_ipu_data = {
73 106
74static struct mx3fb_platform_data mx3fb_pdata = { 107static struct mx3fb_platform_data mx3fb_pdata = {
75 .dma_dev = &mx3_ipu.dev, 108 .dma_dev = &mx3_ipu.dev,
76 .name = "CMO_QVGA", 109 .name = "CMO-QVGA",
77 .mode = fb_modedb, 110 .mode = fb_modedb,
78 .num_modes = ARRAY_SIZE(fb_modedb), 111 .num_modes = ARRAY_SIZE(fb_modedb),
79}; 112};
@@ -120,6 +153,16 @@ static struct pad_desc eukrea_mbimxsd_pads[] = {
120 MX35_PAD_STXD4__AUDMUX_AUD4_TXD, 153 MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
121 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, 154 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
122 MX35_PAD_SCK4__AUDMUX_AUD4_TXC, 155 MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
156 /* CAN2 */
157 MX35_PAD_TX5_RX0__CAN2_TXCAN,
158 MX35_PAD_TX4_RX1__CAN2_RXCAN,
159 /* SDCARD */
160 MX35_PAD_SD1_CMD__ESDHC1_CMD,
161 MX35_PAD_SD1_CLK__ESDHC1_CLK,
162 MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
163 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
164 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
165 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
123}; 166};
124 167
125#define GPIO_LED1 (2 * 32 + 29) 168#define GPIO_LED1 (2 * 32 + 29)
@@ -206,7 +249,8 @@ static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
206 }, 249 },
207}; 250};
208 251
209struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = { 252static const
253struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
210 .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE, 254 .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
211}; 255};
212 256
@@ -242,7 +286,10 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
242 mxc_register_device(&mx3_ipu, &mx3_ipu_data); 286 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
243 mxc_register_device(&mx3_fb, &mx3fb_pdata); 287 mxc_register_device(&mx3_fb, &mx3fb_pdata);
244 288
245 mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata); 289 imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
290
291 imx35_add_flexcan1(NULL);
292 imx35_add_esdhc(0, NULL);
246 293
247 gpio_request(GPIO_LED1, "LED1"); 294 gpio_request(GPIO_LED1, "LED1");
248 gpio_direction_output(GPIO_LED1, 1); 295 gpio_direction_output(GPIO_LED1, 1);
@@ -254,7 +301,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
254 301
255 gpio_request(GPIO_LCDPWR, "LCDPWR"); 302 gpio_request(GPIO_LCDPWR, "LCDPWR");
256 gpio_direction_output(GPIO_LCDPWR, 1); 303 gpio_direction_output(GPIO_LCDPWR, 1);
257 gpio_free(GPIO_SWITCH1); 304 gpio_free(GPIO_LCDPWR);
258 305
259 i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices, 306 i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
260 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices)); 307 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 68879c996a55..aaa30fe18f85 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -571,8 +571,6 @@ static struct sys_timer armadillo5x0_timer = {
571 571
572MACHINE_START(ARMADILLO5X0, "Armadillo-500") 572MACHINE_START(ARMADILLO5X0, "Armadillo-500")
573 /* Maintainer: Alberto Panizzo */ 573 /* Maintainer: Alberto Panizzo */
574 .phys_io = MX31_AIPS1_BASE_ADDR,
575 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
576 .boot_params = MX3x_PHYS_OFFSET + 0x100, 574 .boot_params = MX3x_PHYS_OFFSET + 0x100,
577 .map_io = mx31_map_io, 575 .map_io = mx31_map_io,
578 .init_irq = mx31_init_irq, 576 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
index 2a4f8b781ba4..8533bf04284a 100644
--- a/arch/arm/mach-mx3/mach-cpuimx35.c
+++ b/arch/arm/mach-mx3/mach-cpuimx35.c
@@ -31,6 +31,7 @@
31#include <linux/usb/otg.h> 31#include <linux/usb/otg.h>
32#include <linux/usb/ulpi.h> 32#include <linux/usb/ulpi.h>
33#include <linux/fsl_devices.h> 33#include <linux/fsl_devices.h>
34#include <linux/i2c-gpio.h>
34 35
35#include <asm/mach-types.h> 36#include <asm/mach-types.h>
36#include <asm/mach/arch.h> 37#include <asm/mach/arch.h>
@@ -43,7 +44,6 @@
43#include <mach/iomux-mx35.h> 44#include <mach/iomux-mx35.h>
44#include <mach/mxc_nand.h> 45#include <mach/mxc_nand.h>
45#include <mach/mxc_ehci.h> 46#include <mach/mxc_ehci.h>
46#include <mach/ulpi.h>
47 47
48#include "devices-imx35.h" 48#include "devices-imx35.h"
49#include "devices.h" 49#include "devices.h"
@@ -53,39 +53,16 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
53}; 53};
54 54
55static const struct imxi2c_platform_data 55static const struct imxi2c_platform_data
56eukrea_cpuimx35_i2c0_data __initconst = { 56 eukrea_cpuimx35_i2c0_data __initconst = {
57 .bitrate = 50000, 57 .bitrate = 100000,
58}; 58};
59 59
60#define TSC2007_IRQGPIO (2 * 32 + 2)
61static int ts_get_pendown_state(void)
62{
63 int val = 0;
64 gpio_free(TSC2007_IRQGPIO);
65 gpio_request(TSC2007_IRQGPIO, NULL);
66 gpio_direction_input(TSC2007_IRQGPIO);
67
68 val = gpio_get_value(TSC2007_IRQGPIO);
69
70 gpio_free(TSC2007_IRQGPIO);
71 gpio_request(TSC2007_IRQGPIO, NULL);
72
73 return val ? 0 : 1;
74}
75
76static int ts_init(void)
77{
78 gpio_request(TSC2007_IRQGPIO, NULL);
79 return 0;
80}
81
82static struct tsc2007_platform_data tsc2007_info = { 60static struct tsc2007_platform_data tsc2007_info = {
83 .model = 2007, 61 .model = 2007,
84 .x_plate_ohms = 180, 62 .x_plate_ohms = 180,
85 .get_pendown_state = ts_get_pendown_state,
86 .init_platform_hw = ts_init,
87}; 63};
88 64
65#define TSC2007_IRQGPIO (2 * 32 + 2)
89static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = { 66static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
90 { 67 {
91 I2C_BOARD_INFO("pcf8563", 0x51), 68 I2C_BOARD_INFO("pcf8563", 0x51),
@@ -98,7 +75,6 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
98}; 75};
99 76
100static struct platform_device *devices[] __initdata = { 77static struct platform_device *devices[] __initdata = {
101 &mxc_fec_device,
102 &imx_wdt_device0, 78 &imx_wdt_device0,
103}; 79};
104 80
@@ -135,18 +111,18 @@ static struct pad_desc eukrea_cpuimx35_pads[] = {
135}; 111};
136 112
137static const struct mxc_nand_platform_data 113static const struct mxc_nand_platform_data
138eukrea_cpuimx35_nand_board_info __initconst = { 114 eukrea_cpuimx35_nand_board_info __initconst = {
139 .width = 1, 115 .width = 1,
140 .hw_ecc = 1, 116 .hw_ecc = 1,
141 .flash_bbt = 1, 117 .flash_bbt = 1,
142}; 118};
143 119
144static struct mxc_usbh_platform_data otg_pdata = { 120static struct mxc_usbh_platform_data __maybe_unused otg_pdata = {
145 .portsc = MXC_EHCI_MODE_UTMI, 121 .portsc = MXC_EHCI_MODE_UTMI,
146 .flags = MXC_EHCI_INTERFACE_DIFF_UNI, 122 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
147}; 123};
148 124
149static struct mxc_usbh_platform_data usbh1_pdata = { 125static struct mxc_usbh_platform_data __maybe_unused usbh1_pdata = {
150 .portsc = MXC_EHCI_MODE_SERIAL, 126 .portsc = MXC_EHCI_MODE_SERIAL,
151 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | 127 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
152 MXC_EHCI_IPPUE_DOWN, 128 MXC_EHCI_IPPUE_DOWN,
@@ -180,6 +156,7 @@ static void __init mxc_board_init(void)
180 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads, 156 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
181 ARRAY_SIZE(eukrea_cpuimx35_pads)); 157 ARRAY_SIZE(eukrea_cpuimx35_pads));
182 158
159 imx35_add_fec(NULL);
183 platform_add_devices(devices, ARRAY_SIZE(devices)); 160 platform_add_devices(devices, ARRAY_SIZE(devices));
184 161
185 imx35_add_imx_uart0(&uart_pdata); 162 imx35_add_imx_uart0(&uart_pdata);
@@ -189,18 +166,13 @@ static void __init mxc_board_init(void)
189 ARRAY_SIZE(eukrea_cpuimx35_i2c_devices)); 166 ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
190 imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data); 167 imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
191 168
192#if defined(CONFIG_USB_ULPI) 169 if (otg_mode_host)
193 if (otg_mode_host) {
194 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
195 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
196
197 mxc_register_device(&mxc_otg_host, &otg_pdata); 170 mxc_register_device(&mxc_otg_host, &otg_pdata);
198 } 171 else
199 mxc_register_device(&mxc_usbh1, &usbh1_pdata);
200#endif
201 if (!otg_mode_host)
202 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); 172 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
203 173
174 mxc_register_device(&mxc_usbh1, &usbh1_pdata);
175
204#ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD 176#ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD
205 eukrea_mbimxsd35_baseboard_init(); 177 eukrea_mbimxsd35_baseboard_init();
206#endif 178#endif
@@ -217,8 +189,6 @@ struct sys_timer eukrea_cpuimx35_timer = {
217 189
218MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35") 190MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
219 /* Maintainer: Eukrea Electromatique */ 191 /* Maintainer: Eukrea Electromatique */
220 .phys_io = MX35_AIPS1_BASE_ADDR,
221 .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
222 .boot_params = MX3x_PHYS_OFFSET + 0x100, 192 .boot_params = MX3x_PHYS_OFFSET + 0x100,
223 .map_io = mx35_map_io, 193 .map_io = mx35_map_io,
224 .init_irq = mx35_init_irq, 194 .init_irq = mx35_init_irq,
diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
index 5b23e416d6c7..042cd5655e17 100644
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
@@ -274,8 +274,6 @@ static struct sys_timer kzm_timer = {
274 * initialize __mach_desc_KZM_ARM11_01 data structure. 274 * initialize __mach_desc_KZM_ARM11_01 data structure.
275 */ 275 */
276MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") 276MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
277 .phys_io = MX31_AIPS1_BASE_ADDR,
278 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
279 .boot_params = MX3x_PHYS_OFFSET + 0x100, 277 .boot_params = MX3x_PHYS_OFFSET + 0x100,
280 .map_io = kzm_map_io, 278 .map_io = kzm_map_io,
281 .init_irq = mx31_init_irq, 279 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 6fe69e124d30..5c1d0e86c91e 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -301,8 +301,6 @@ static struct sys_timer mx31_3ds_timer = {
301 */ 301 */
302MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") 302MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
303 /* Maintainer: Freescale Semiconductor, Inc. */ 303 /* Maintainer: Freescale Semiconductor, Inc. */
304 .phys_io = MX31_AIPS1_BASE_ADDR,
305 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
306 .boot_params = MX3x_PHYS_OFFSET + 0x100, 304 .boot_params = MX3x_PHYS_OFFSET + 0x100,
307 .map_io = mx31_3ds_map_io, 305 .map_io = mx31_3ds_map_io,
308 .init_irq = mx31_init_irq, 306 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index 94b3e7c42404..b993b9bf6179 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -22,13 +22,13 @@
22#include <linux/i2c.h> 22#include <linux/i2c.h>
23#include <linux/irq.h> 23#include <linux/irq.h>
24 24
25#include <mach/hardware.h>
26#include <asm/mach-types.h> 25#include <asm/mach-types.h>
27#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
28#include <asm/mach/time.h> 27#include <asm/mach/time.h>
29#include <asm/memory.h> 28#include <asm/memory.h>
30#include <asm/mach/map.h> 29#include <asm/mach/map.h>
31#include <mach/common.h> 30#include <mach/common.h>
31#include <mach/board-mx31ads.h>
32#include <mach/iomux-mx3.h> 32#include <mach/iomux-mx3.h>
33 33
34#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 34#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
@@ -40,10 +40,6 @@
40#include "devices-imx31.h" 40#include "devices-imx31.h"
41#include "devices.h" 41#include "devices.h"
42 42
43/* Base address of PBC controller */
44#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
45/* Offsets for the PBC Controller register */
46
47/* PBC Board interrupt status register */ 43/* PBC Board interrupt status register */
48#define PBC_INTSTATUS 0x000016 44#define PBC_INTSTATUS 0x000016
49 45
@@ -67,7 +63,6 @@
67#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS) 63#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
68#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4) 64#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
69 65
70#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
71#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE) 66#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
72 67
73#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10) 68#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
@@ -517,7 +512,7 @@ static unsigned int ssi_pins[] = {
517 512
518static void mxc_init_audio(void) 513static void mxc_init_audio(void)
519{ 514{
520 mxc_register_device(&imx_ssi_device0, NULL); 515 imx31_add_imx_ssi(0, NULL);
521 mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi"); 516 mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
522} 517}
523 518
@@ -574,8 +569,6 @@ static struct sys_timer mx31ads_timer = {
574 */ 569 */
575MACHINE_START(MX31ADS, "Freescale MX31ADS") 570MACHINE_START(MX31ADS, "Freescale MX31ADS")
576 /* Maintainer: Freescale Semiconductor, Inc. */ 571 /* Maintainer: Freescale Semiconductor, Inc. */
577 .phys_io = MX31_AIPS1_BASE_ADDR,
578 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
579 .boot_params = MX3x_PHYS_OFFSET + 0x100, 572 .boot_params = MX3x_PHYS_OFFSET + 0x100,
580 .map_io = mx31ads_map_io, 573 .map_io = mx31ads_map_io,
581 .init_irq = mx31ads_init_irq, 574 .init_irq = mx31ads_init_irq,
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index 7c37daabb757..42f47faa6fd6 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -348,8 +348,6 @@ static struct sys_timer mx31lilly_timer = {
348}; 348};
349 349
350MACHINE_START(LILLY1131, "INCO startec LILLY-1131") 350MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
351 .phys_io = MX31_AIPS1_BASE_ADDR,
352 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
353 .boot_params = MX3x_PHYS_OFFSET + 0x100, 351 .boot_params = MX3x_PHYS_OFFSET + 0x100,
354 .map_io = mx31_map_io, 352 .map_io = mx31_map_io,
355 .init_irq = mx31_init_irq, 353 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index f66a9576d8c2..b93895814cdf 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -282,8 +282,6 @@ struct sys_timer mx31lite_timer = {
282 282
283MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") 283MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
284 /* Maintainer: Freescale Semiconductor, Inc. */ 284 /* Maintainer: Freescale Semiconductor, Inc. */
285 .phys_io = MX31_AIPS1_BASE_ADDR,
286 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
287 .boot_params = MX3x_PHYS_OFFSET + 0x100, 285 .boot_params = MX3x_PHYS_OFFSET + 0x100,
288 .map_io = mx31lite_map_io, 286 .map_io = mx31lite_map_io,
289 .init_irq = mx31_init_irq, 287 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index 7a075e8bf2d4..eb5f426df224 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -560,8 +560,6 @@ struct sys_timer mx31moboard_timer = {
560 560
561MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") 561MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
562 /* Maintainer: Valentin Longchamp, EPFL Mobots group */ 562 /* Maintainer: Valentin Longchamp, EPFL Mobots group */
563 .phys_io = MX31_AIPS1_BASE_ADDR,
564 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
565 .boot_params = MX3x_PHYS_OFFSET + 0x100, 563 .boot_params = MX3x_PHYS_OFFSET + 0x100,
566 .map_io = mx31_map_io, 564 .map_io = mx31_map_io,
567 .init_irq = mx31_init_irq, 565 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c
index 1c30d7212f17..05f628d90725 100644
--- a/arch/arm/mach-mx3/mach-mx35_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx35_3ds.c
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix
3 * 4 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 * 6 *
@@ -27,6 +28,8 @@
27#include <linux/gpio.h> 28#include <linux/gpio.h>
28#include <linux/fsl_devices.h> 29#include <linux/fsl_devices.h>
29 30
31#include <linux/mtd/physmap.h>
32
30#include <asm/mach-types.h> 33#include <asm/mach-types.h>
31#include <asm/mach/arch.h> 34#include <asm/mach/arch.h>
32#include <asm/mach/time.h> 35#include <asm/mach/time.h>
@@ -35,6 +38,7 @@
35#include <mach/hardware.h> 38#include <mach/hardware.h>
36#include <mach/common.h> 39#include <mach/common.h>
37#include <mach/iomux-mx35.h> 40#include <mach/iomux-mx35.h>
41#include <mach/mxc_ehci.h>
38 42
39#include "devices-imx35.h" 43#include "devices-imx35.h"
40#include "devices.h" 44#include "devices.h"
@@ -43,8 +47,34 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
43 .flags = IMXUART_HAVE_RTSCTS, 47 .flags = IMXUART_HAVE_RTSCTS,
44}; 48};
45 49
50static struct physmap_flash_data mx35pdk_flash_data = {
51 .width = 2,
52};
53
54static struct resource mx35pdk_flash_resource = {
55 .start = MX35_CS0_BASE_ADDR,
56 .end = MX35_CS0_BASE_ADDR + SZ_64M - 1,
57 .flags = IORESOURCE_MEM,
58};
59
60static struct platform_device mx35pdk_flash = {
61 .name = "physmap-flash",
62 .id = 0,
63 .dev = {
64 .platform_data = &mx35pdk_flash_data,
65 },
66 .resource = &mx35pdk_flash_resource,
67 .num_resources = 1,
68};
69
70static const struct mxc_nand_platform_data mx35pdk_nand_board_info __initconst = {
71 .width = 1,
72 .hw_ecc = 1,
73 .flash_bbt = 1,
74};
75
46static struct platform_device *devices[] __initdata = { 76static struct platform_device *devices[] __initdata = {
47 &mxc_fec_device, 77 &mx35pdk_flash,
48}; 78};
49 79
50static struct pad_desc mx35pdk_pads[] = { 80static struct pad_desc mx35pdk_pads[] = {
@@ -75,14 +105,24 @@ static struct pad_desc mx35pdk_pads[] = {
75 /* USBOTG */ 105 /* USBOTG */
76 MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, 106 MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
77 MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, 107 MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
108 /* USBH1 */
109 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
110 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
78}; 111};
79 112
80/* OTG config */ 113/* OTG config */
81static struct fsl_usb2_platform_data usb_pdata = { 114static struct fsl_usb2_platform_data usb_otg_pdata = {
82 .operating_mode = FSL_USB2_DR_DEVICE, 115 .operating_mode = FSL_USB2_DR_DEVICE,
83 .phy_mode = FSL_USB2_PHY_UTMI_WIDE, 116 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
84}; 117};
85 118
119/* USB HOST config */
120static struct mxc_usbh_platform_data usb_host_pdata = {
121 .portsc = MXC_EHCI_MODE_SERIAL,
122 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI |
123 MXC_EHCI_INTERNAL_PHY,
124};
125
86/* 126/*
87 * Board specific initialization. 127 * Board specific initialization.
88 */ 128 */
@@ -90,11 +130,16 @@ static void __init mxc_board_init(void)
90{ 130{
91 mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); 131 mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
92 132
133 imx35_add_fec(NULL);
93 platform_add_devices(devices, ARRAY_SIZE(devices)); 134 platform_add_devices(devices, ARRAY_SIZE(devices));
94 135
95 imx35_add_imx_uart0(&uart_pdata); 136 imx35_add_imx_uart0(&uart_pdata);
96 137
97 mxc_register_device(&mxc_otg_udc_device, &usb_pdata); 138 mxc_register_device(&mxc_otg_udc_device, &usb_otg_pdata);
139
140 mxc_register_device(&mxc_usbh1, &usb_host_pdata);
141
142 imx35_add_mxc_nand(&mx35pdk_nand_board_info);
98} 143}
99 144
100static void __init mx35pdk_timer_init(void) 145static void __init mx35pdk_timer_init(void)
@@ -108,8 +153,6 @@ struct sys_timer mx35pdk_timer = {
108 153
109MACHINE_START(MX35_3DS, "Freescale MX35PDK") 154MACHINE_START(MX35_3DS, "Freescale MX35PDK")
110 /* Maintainer: Freescale Semiconductor, Inc */ 155 /* Maintainer: Freescale Semiconductor, Inc */
111 .phys_io = MX35_AIPS1_BASE_ADDR,
112 .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
113 .boot_params = MX3x_PHYS_OFFSET + 0x100, 156 .boot_params = MX3x_PHYS_OFFSET + 0x100,
114 .map_io = mx35_map_io, 157 .map_io = mx35_map_io,
115 .init_irq = mx35_init_irq, 158 .init_irq = mx35_init_irq,
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index 214de11b20b9..86e86c1300d5 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -680,8 +680,6 @@ struct sys_timer pcm037_timer = {
680 680
681MACHINE_START(PCM037, "Phytec Phycore pcm037") 681MACHINE_START(PCM037, "Phytec Phycore pcm037")
682 /* Maintainer: Pengutronix */ 682 /* Maintainer: Pengutronix */
683 .phys_io = MX31_AIPS1_BASE_ADDR,
684 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
685 .boot_params = MX3x_PHYS_OFFSET + 0x100, 683 .boot_params = MX3x_PHYS_OFFSET + 0x100,
686 .map_io = mx31_map_io, 684 .map_io = mx31_map_io,
687 .init_irq = mx31_init_irq, 685 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c
index c8b98218efee..99e0894e07db 100644
--- a/arch/arm/mach-mx3/mach-pcm037_eet.c
+++ b/arch/arm/mach-mx3/mach-pcm037_eet.c
@@ -19,6 +19,7 @@
19 19
20#include "pcm037.h" 20#include "pcm037.h"
21#include "devices.h" 21#include "devices.h"
22#include "devices-imx31.h"
22 23
23static unsigned int pcm037_eet_pins[] = { 24static unsigned int pcm037_eet_pins[] = {
24 /* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */ 25 /* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */
@@ -181,7 +182,7 @@ static int eet_init_devices(void)
181 /* SPI */ 182 /* SPI */
182 spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev)); 183 spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
183#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE) 184#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
184 imx35_add_spi_imx0(&pcm037_spi1_pdata); 185 imx31_add_spi_imx0(&pcm037_spi1_pdata);
185#endif 186#endif
186 187
187 platform_device_register(&pcm037_gpio_keys_device); 188 platform_device_register(&pcm037_gpio_keys_device);
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index 28886f0e62f9..4e1de87995d4 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -42,7 +42,6 @@
42#include <mach/mxc_ehci.h> 42#include <mach/mxc_ehci.h>
43#include <mach/ulpi.h> 43#include <mach/ulpi.h>
44#include <mach/audmux.h> 44#include <mach/audmux.h>
45#include <mach/ssi.h>
46 45
47#include "devices-imx35.h" 46#include "devices-imx35.h"
48#include "devices.h" 47#include "devices.h"
@@ -141,7 +140,6 @@ static struct i2c_board_info pcm043_i2c_devices[] = {
141 140
142static struct platform_device *devices[] __initdata = { 141static struct platform_device *devices[] __initdata = {
143 &pcm043_flash, 142 &pcm043_flash,
144 &mxc_fec_device,
145 &imx_wdt_device0, 143 &imx_wdt_device0,
146}; 144};
147 145
@@ -217,6 +215,13 @@ static struct pad_desc pcm043_pads[] = {
217 /* CAN2 */ 215 /* CAN2 */
218 MX35_PAD_TX5_RX0__CAN2_TXCAN, 216 MX35_PAD_TX5_RX0__CAN2_TXCAN,
219 MX35_PAD_TX4_RX1__CAN2_RXCAN, 217 MX35_PAD_TX4_RX1__CAN2_RXCAN,
218 /* esdhc */
219 MX35_PAD_SD1_CMD__ESDHC1_CMD,
220 MX35_PAD_SD1_CLK__ESDHC1_CLK,
221 MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
222 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
223 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
224 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
220}; 225};
221 226
222#define AC97_GPIO_TXFS (1 * 32 + 31) 227#define AC97_GPIO_TXFS (1 * 32 + 31)
@@ -293,7 +298,7 @@ err1:
293 mdelay(1); 298 mdelay(1);
294} 299}
295 300
296static struct imx_ssi_platform_data pcm043_ssi_pdata = { 301static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
297 .ac97_reset = pcm043_ac97_cold_reset, 302 .ac97_reset = pcm043_ac97_cold_reset,
298 .ac97_warm_reset = pcm043_ac97_warm_reset, 303 .ac97_warm_reset = pcm043_ac97_warm_reset,
299 .flags = IMX_SSI_USE_AC97, 304 .flags = IMX_SSI_USE_AC97,
@@ -357,11 +362,12 @@ static void __init mxc_board_init(void)
357 MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */ 362 MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
358 MXC_AUDMUX_V2_PDCR_RXDSEL(3)); 363 MXC_AUDMUX_V2_PDCR_RXDSEL(3));
359 364
365 imx35_add_fec(NULL);
360 platform_add_devices(devices, ARRAY_SIZE(devices)); 366 platform_add_devices(devices, ARRAY_SIZE(devices));
361 367
362 imx35_add_imx_uart0(&uart_pdata); 368 imx35_add_imx_uart0(&uart_pdata);
363 imx35_add_mxc_nand(&pcm037_nand_board_info); 369 imx35_add_mxc_nand(&pcm037_nand_board_info);
364 mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata); 370 imx35_add_imx_ssi(0, &pcm043_ssi_pdata);
365 371
366 imx35_add_imx_uart1(&uart_pdata); 372 imx35_add_imx_uart1(&uart_pdata);
367 373
@@ -389,6 +395,7 @@ static void __init mxc_board_init(void)
389 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); 395 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
390 396
391 imx35_add_flexcan1(NULL); 397 imx35_add_flexcan1(NULL);
398 imx35_add_esdhc(0, NULL);
392} 399}
393 400
394static void __init pcm043_timer_init(void) 401static void __init pcm043_timer_init(void)
@@ -402,8 +409,6 @@ struct sys_timer pcm043_timer = {
402 409
403MACHINE_START(PCM043, "Phytec Phycore pcm043") 410MACHINE_START(PCM043, "Phytec Phycore pcm043")
404 /* Maintainer: Pengutronix */ 411 /* Maintainer: Pengutronix */
405 .phys_io = MX35_AIPS1_BASE_ADDR,
406 .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
407 .boot_params = MX3x_PHYS_OFFSET + 0x100, 412 .boot_params = MX3x_PHYS_OFFSET + 0x100,
408 .map_io = mx35_map_io, 413 .map_io = mx35_map_io,
409 .init_irq = mx35_init_irq, 414 .init_irq = mx35_init_irq,
diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c
index c8c380eef74c..fd1050c40964 100644
--- a/arch/arm/mach-mx3/mach-qong.c
+++ b/arch/arm/mach-mx3/mach-qong.c
@@ -270,8 +270,6 @@ static struct sys_timer qong_timer = {
270 270
271MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") 271MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
272 /* Maintainer: DENX Software Engineering GmbH */ 272 /* Maintainer: DENX Software Engineering GmbH */
273 .phys_io = MX31_AIPS1_BASE_ADDR,
274 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
275 .boot_params = MX3x_PHYS_OFFSET + 0x100, 273 .boot_params = MX3x_PHYS_OFFSET + 0x100,
276 .map_io = mx31_map_io, 274 .map_io = mx31_map_io,
277 .init_irq = mx31_init_irq, 275 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 20e48c0195c4..b4ffc531a82c 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -110,6 +110,24 @@ void __init mx35_init_irq(void)
110static int mxc_init_l2x0(void) 110static int mxc_init_l2x0(void)
111{ 111{
112 void __iomem *l2x0_base; 112 void __iomem *l2x0_base;
113 void __iomem *clkctl_base;
114/*
115 * First of all, we must repair broken chip settings. There are some
116 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
117 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
118 * Workaraound is to setup the correct register setting prior enabling the
119 * L2 cache. This should not hurt already working CPUs, as they are using the
120 * same value
121 */
122#define L2_MEM_VAL 0x10
123
124 clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
125 if (clkctl_base != NULL) {
126 writel(0x00000515, clkctl_base + L2_MEM_VAL);
127 iounmap(clkctl_base);
128 } else {
129 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
130 }
113 131
114 l2x0_base = ioremap(L2CC_BASE_ADDR, 4096); 132 l2x0_base = ioremap(L2CC_BASE_ADDR, 4096);
115 if (IS_ERR(l2x0_base)) { 133 if (IS_ERR(l2x0_base)) {
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 0848db5dd364..a2df9ac37996 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -5,11 +5,14 @@ config ARCH_MX51
5 default y 5 default y
6 select MXC_TZIC 6 select MXC_TZIC
7 select ARCH_MXC_IOMUX_V3 7 select ARCH_MXC_IOMUX_V3
8 select ARCH_MXC_AUDMUX_V2
8 9
9comment "MX5 platforms:" 10comment "MX5 platforms:"
10 11
11config MACH_MX51_BABBAGE 12config MACH_MX51_BABBAGE
12 bool "Support MX51 BABBAGE platforms" 13 bool "Support MX51 BABBAGE platforms"
14 select IMX_HAVE_PLATFORM_IMX_I2C
15 select IMX_HAVE_PLATFORM_IMX_UART
13 help 16 help
14 Include support for MX51 Babbage platform, also known as MX51EVK in 17 Include support for MX51 Babbage platform, also known as MX51EVK in
15 u-boot. This includes specific configurations for the board and its 18 u-boot. This includes specific configurations for the board and its
@@ -17,6 +20,8 @@ config MACH_MX51_BABBAGE
17 20
18config MACH_MX51_3DS 21config MACH_MX51_3DS
19 bool "Support MX51PDK (3DS)" 22 bool "Support MX51PDK (3DS)"
23 select IMX_HAVE_PLATFORM_IMX_UART
24 select IMX_HAVE_PLATFORM_SPI_IMX
20 select MXC_DEBUG_BOARD 25 select MXC_DEBUG_BOARD
21 help 26 help
22 Include support for MX51PDK (3DS) platform. This includes specific 27 Include support for MX51PDK (3DS) platform. This includes specific
@@ -24,6 +29,10 @@ config MACH_MX51_3DS
24 29
25config MACH_EUKREA_CPUIMX51 30config MACH_EUKREA_CPUIMX51
26 bool "Support Eukrea CPUIMX51 module" 31 bool "Support Eukrea CPUIMX51 module"
32 select IMX_HAVE_PLATFORM_IMX_I2C
33 select IMX_HAVE_PLATFORM_IMX_UART
34 select IMX_HAVE_PLATFORM_MXC_NAND
35 select IMX_HAVE_PLATFORM_SPI_IMX
27 help 36 help
28 Include support for Eukrea CPUIMX51 platform. This includes 37 Include support for Eukrea CPUIMX51 platform. This includes
29 specific configurations for the module and its peripherals. 38 specific configurations for the module and its peripherals.
@@ -36,10 +45,43 @@ choice
36config MACH_EUKREA_MBIMX51_BASEBOARD 45config MACH_EUKREA_MBIMX51_BASEBOARD
37 prompt "Eukrea MBIMX51 development board" 46 prompt "Eukrea MBIMX51 development board"
38 bool 47 bool
48 select IMX_HAVE_PLATFORM_ESDHC
39 help 49 help
40 This adds board specific devices that can be found on Eukrea's 50 This adds board specific devices that can be found on Eukrea's
41 MBIMX51 evaluation board. 51 MBIMX51 evaluation board.
42 52
43endchoice 53endchoice
44 54
55config MACH_EUKREA_CPUIMX51SD
56 bool "Support Eukrea CPUIMX51SD module"
57 select IMX_HAVE_PLATFORM_IMX_I2C
58 select IMX_HAVE_PLATFORM_SPI_IMX
59 select IMX_HAVE_PLATFORM_IMX_UART
60 select IMX_HAVE_PLATFORM_MXC_NAND
61 help
62 Include support for Eukrea CPUIMX51SD platform. This includes
63 specific configurations for the module and its peripherals.
64
65choice
66 prompt "Baseboard"
67 depends on MACH_EUKREA_CPUIMX51SD
68 default MACH_EUKREA_MBIMXSD51_BASEBOARD
69
70config MACH_EUKREA_MBIMXSD51_BASEBOARD
71 prompt "Eukrea MBIMXSD development board"
72 bool
73 select IMX_HAVE_PLATFORM_ESDHC
74 help
75 This adds board specific devices that can be found on Eukrea's
76 MBIMXSD evaluation board.
77
78endchoice
79
80config MACH_MX51_EFIKAMX
81 bool "Support MX51 Genesi Efika MX nettop"
82 select IMX_HAVE_PLATFORM_IMX_UART
83 help
84 Include support for Genesi Efika MX nettop. This includes specific
85 configurations for the board and its peripherals.
86
45endif 87endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 86c66e7f52f3..1769c161a60d 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -9,3 +9,6 @@ obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
9obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o 9obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
10obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o 10obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
11obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o 11obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
12obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
13obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
14obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index 623607a20f57..6a9792fd0a76 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -28,9 +28,7 @@
28#include <mach/eukrea-baseboards.h> 28#include <mach/eukrea-baseboards.h>
29#include <mach/common.h> 29#include <mach/common.h>
30#include <mach/hardware.h> 30#include <mach/hardware.h>
31#include <mach/imx-uart.h>
32#include <mach/iomux-mx51.h> 31#include <mach/iomux-mx51.h>
33#include <mach/i2c.h>
34#include <mach/mxc_ehci.h> 32#include <mach/mxc_ehci.h>
35 33
36#include <asm/irq.h> 34#include <asm/irq.h>
@@ -39,6 +37,7 @@
39#include <asm/mach/arch.h> 37#include <asm/mach/arch.h>
40#include <asm/mach/time.h> 38#include <asm/mach/time.h>
41 39
40#include "devices-imx51.h"
42#include "devices.h" 41#include "devices.h"
43 42
44#define CPUIMX51_USBH1_STP (0*32 + 27) 43#define CPUIMX51_USBH1_STP (0*32 + 27)
@@ -109,7 +108,6 @@ static struct platform_device serial_device = {
109#endif 108#endif
110 109
111static struct platform_device *devices[] __initdata = { 110static struct platform_device *devices[] __initdata = {
112 &mxc_fec_device,
113#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 111#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
114 &serial_device, 112 &serial_device,
115#endif 113#endif
@@ -148,11 +146,19 @@ static struct pad_desc eukrea_cpuimx51_pads[] = {
148 MX51_PAD_USBH1_STP__USBH1_STP, 146 MX51_PAD_USBH1_STP__USBH1_STP,
149}; 147};
150 148
151static struct imxuart_platform_data uart_pdata = { 149static const struct mxc_nand_platform_data
150 eukrea_cpuimx51_nand_board_info __initconst = {
151 .width = 1,
152 .hw_ecc = 1,
153 .flash_bbt = 1,
154};
155
156static const struct imxuart_platform_data uart_pdata __initconst = {
152 .flags = IMXUART_HAVE_RTSCTS, 157 .flags = IMXUART_HAVE_RTSCTS,
153}; 158};
154 159
155static struct imxi2c_platform_data eukrea_cpuimx51_i2c_data = { 160static const
161struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = {
156 .bitrate = 100000, 162 .bitrate = 100000,
157}; 163};
158 164
@@ -239,7 +245,9 @@ static void __init eukrea_cpuimx51_init(void)
239 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads, 245 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
240 ARRAY_SIZE(eukrea_cpuimx51_pads)); 246 ARRAY_SIZE(eukrea_cpuimx51_pads));
241 247
242 mxc_register_device(&mxc_uart_device0, &uart_pdata); 248 imx51_add_imx_uart(0, &uart_pdata);
249 imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info);
250
243 gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq"); 251 gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
244 gpio_direction_input(CPUIMX51_QUARTA_GPIO); 252 gpio_direction_input(CPUIMX51_QUARTA_GPIO);
245 gpio_free(CPUIMX51_QUARTA_GPIO); 253 gpio_free(CPUIMX51_QUARTA_GPIO);
@@ -253,9 +261,10 @@ static void __init eukrea_cpuimx51_init(void)
253 gpio_direction_input(CPUIMX51_QUARTD_GPIO); 261 gpio_direction_input(CPUIMX51_QUARTD_GPIO);
254 gpio_free(CPUIMX51_QUARTD_GPIO); 262 gpio_free(CPUIMX51_QUARTD_GPIO);
255 263
264 imx51_add_fec(NULL);
256 platform_add_devices(devices, ARRAY_SIZE(devices)); 265 platform_add_devices(devices, ARRAY_SIZE(devices));
257 266
258 mxc_register_device(&mxc_i2c_device1, &eukrea_cpuimx51_i2c_data); 267 imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data);
259 i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices, 268 i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
260 ARRAY_SIZE(eukrea_cpuimx51_i2c_devices)); 269 ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
261 270
@@ -283,8 +292,6 @@ static struct sys_timer mxc_timer = {
283 292
284MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module") 293MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
285 /* Maintainer: Eric Bénard <eric@eukrea.com> */ 294 /* Maintainer: Eric Bénard <eric@eukrea.com> */
286 .phys_io = MX51_AIPS1_BASE_ADDR,
287 .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
288 .boot_params = PHYS_OFFSET + 0x100, 295 .boot_params = PHYS_OFFSET + 0x100,
289 .map_io = mx51_map_io, 296 .map_io = mx51_map_io,
290 .init_irq = mx51_init_irq, 297 .init_irq = mx51_init_irq,
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
new file mode 100644
index 000000000000..4b3a6119c5fb
--- /dev/null
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -0,0 +1,331 @@
1/*
2 *
3 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
4 *
5 * based on board-mx51_babbage.c which is
6 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/i2c/tsc2007.h>
21#include <linux/gpio.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/fsl_devices.h>
27#include <linux/i2c-gpio.h>
28#include <linux/spi/spi.h>
29#include <linux/can/platform/mcp251x.h>
30
31#include <mach/eukrea-baseboards.h>
32#include <mach/common.h>
33#include <mach/hardware.h>
34#include <mach/iomux-mx51.h>
35#include <mach/mxc_ehci.h>
36
37#include <asm/irq.h>
38#include <asm/setup.h>
39#include <asm/mach-types.h>
40#include <asm/mach/arch.h>
41#include <asm/mach/time.h>
42
43#include "devices-imx51.h"
44#include "devices.h"
45
46#define USBH1_RST (1*32 + 28)
47#define ETH_RST (1*32 + 31)
48#define TSC2007_IRQGPIO (2*32 + 12)
49#define CAN_IRQGPIO (0*32 + 1)
50#define CAN_RST (3*32 + 15)
51#define CAN_NCS (3*32 + 24)
52#define CAN_RXOBF (0*32 + 4)
53#define CAN_RX1BF (0*32 + 6)
54#define CAN_TXORTS (0*32 + 7)
55#define CAN_TX1RTS (0*32 + 8)
56#define CAN_TX2RTS (0*32 + 9)
57#define I2C_SCL (3*32 + 16)
58#define I2C_SDA (3*32 + 17)
59
60/* USB_CTRL_1 */
61#define MX51_USB_CTRL_1_OFFSET 0x10
62#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
63
64#define MX51_USB_PLLDIV_12_MHZ 0x00
65#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
66#define MX51_USB_PLL_DIV_24_MHZ 0x02
67
68#define CPUIMX51SD_GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, \
69 MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
70
71static struct pad_desc eukrea_cpuimx51sd_pads[] = {
72 /* UART1 */
73 MX51_PAD_UART1_RXD__UART1_RXD,
74 MX51_PAD_UART1_TXD__UART1_TXD,
75 MX51_PAD_UART1_RTS__UART1_RTS,
76 MX51_PAD_UART1_CTS__UART1_CTS,
77
78 /* USB HOST1 */
79 MX51_PAD_USBH1_CLK__USBH1_CLK,
80 MX51_PAD_USBH1_DIR__USBH1_DIR,
81 MX51_PAD_USBH1_NXT__USBH1_NXT,
82 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
83 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
84 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
85 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
86 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
87 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
88 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
89 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
90 MX51_PAD_USBH1_STP__USBH1_STP,
91 MX51_PAD_EIM_CS3__GPIO_2_28, /* PHY nRESET */
92
93 /* FEC */
94 MX51_PAD_EIM_DTACK__GPIO_2_31, /* PHY nRESET */
95
96 /* HSI2C */
97 MX51_PAD_I2C1_CLK__GPIO_4_16,
98 MX51_PAD_I2C1_DAT__GPIO_4_17,
99
100 /* CAN */
101 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
102 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
103 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
104 MX51_PAD_CSPI1_SS0__GPIO_4_24, /* nCS */
105 MX51_PAD_CSI2_PIXCLK__GPIO_4_15, /* nReset */
106 MX51_PAD_GPIO_1_1__GPIO_1_1, /* IRQ */
107 MX51_PAD_GPIO_1_4__GPIO_1_4, /* Control signals */
108 MX51_PAD_GPIO_1_6__GPIO_1_6,
109 MX51_PAD_GPIO_1_7__GPIO_1_7,
110 MX51_PAD_GPIO_1_8__GPIO_1_8,
111 MX51_PAD_GPIO_1_9__GPIO_1_9,
112
113 /* Touchscreen */
114 CPUIMX51SD_GPIO_3_12, /* IRQ */
115};
116
117static const struct imxuart_platform_data uart_pdata __initconst = {
118 .flags = IMXUART_HAVE_RTSCTS,
119};
120
121static int ts_get_pendown_state(void)
122{
123 return gpio_get_value(TSC2007_IRQGPIO) ? 0 : 1;
124}
125
126static struct tsc2007_platform_data tsc2007_info = {
127 .model = 2007,
128 .x_plate_ohms = 180,
129 .get_pendown_state = ts_get_pendown_state,
130};
131
132static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
133 {
134 I2C_BOARD_INFO("pcf8563", 0x51),
135 }, {
136 I2C_BOARD_INFO("tsc2007", 0x49),
137 .type = "tsc2007",
138 .platform_data = &tsc2007_info,
139 .irq = gpio_to_irq(TSC2007_IRQGPIO),
140 },
141};
142
143static const struct mxc_nand_platform_data
144 eukrea_cpuimx51sd_nand_board_info __initconst = {
145 .width = 1,
146 .hw_ecc = 1,
147 .flash_bbt = 1,
148};
149
150/* This function is board specific as the bit mask for the plldiv will also
151be different for other Freescale SoCs, thus a common bitmask is not
152possible and cannot get place in /plat-mxc/ehci.c.*/
153static int initialize_otg_port(struct platform_device *pdev)
154{
155 u32 v;
156 void __iomem *usb_base;
157 void __iomem *usbother_base;
158
159 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
160 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
161
162 /* Set the PHY clock to 19.2MHz */
163 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
164 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
165 v |= MX51_USB_PLL_DIV_19_2_MHZ;
166 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
167 iounmap(usb_base);
168 return 0;
169}
170
171static int initialize_usbh1_port(struct platform_device *pdev)
172{
173 u32 v;
174 void __iomem *usb_base;
175 void __iomem *usbother_base;
176
177 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
178 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
179
180 /* The clock for the USBH1 ULPI port will come from the PHY. */
181 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
182 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
183 usbother_base + MX51_USB_CTRL_1_OFFSET);
184 iounmap(usb_base);
185 return 0;
186}
187
188static struct mxc_usbh_platform_data dr_utmi_config = {
189 .init = initialize_otg_port,
190 .portsc = MXC_EHCI_UTMI_16BIT,
191 .flags = MXC_EHCI_INTERNAL_PHY,
192};
193
194static struct fsl_usb2_platform_data usb_pdata = {
195 .operating_mode = FSL_USB2_DR_DEVICE,
196 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
197};
198
199static struct mxc_usbh_platform_data usbh1_config = {
200 .init = initialize_usbh1_port,
201 .portsc = MXC_EHCI_MODE_ULPI,
202 .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
203};
204
205static int otg_mode_host;
206
207static int __init eukrea_cpuimx51sd_otg_mode(char *options)
208{
209 if (!strcmp(options, "host"))
210 otg_mode_host = 1;
211 else if (!strcmp(options, "device"))
212 otg_mode_host = 0;
213 else
214 pr_info("otg_mode neither \"host\" nor \"device\". "
215 "Defaulting to device\n");
216 return 0;
217}
218__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
219
220static struct i2c_gpio_platform_data pdata = {
221 .sda_pin = I2C_SDA,
222 .sda_is_open_drain = 0,
223 .scl_pin = I2C_SCL,
224 .scl_is_open_drain = 0,
225 .udelay = 2,
226};
227
228static struct platform_device hsi2c_gpio_device = {
229 .name = "i2c-gpio",
230 .id = 0,
231 .dev.platform_data = &pdata,
232};
233
234static struct mcp251x_platform_data mcp251x_info = {
235 .oscillator_frequency = 24E6,
236};
237
238static struct spi_board_info cpuimx51sd_spi_device[] = {
239 {
240 .modalias = "mcp2515",
241 .max_speed_hz = 6500000,
242 .bus_num = 0,
243 .mode = SPI_MODE_0,
244 .chip_select = 0,
245 .platform_data = &mcp251x_info,
246 .irq = gpio_to_irq(0 * 32 + 1)
247 },
248};
249
250static int cpuimx51sd_spi1_cs[] = {
251 CAN_NCS,
252};
253
254static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
255 .chipselect = cpuimx51sd_spi1_cs,
256 .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
257};
258
259static struct platform_device *platform_devices[] __initdata = {
260 &hsi2c_gpio_device,
261};
262
263static void __init eukrea_cpuimx51sd_init(void)
264{
265 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
266 ARRAY_SIZE(eukrea_cpuimx51sd_pads));
267
268 imx51_add_imx_uart(0, &uart_pdata);
269 imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
270
271 gpio_request(ETH_RST, "eth_rst");
272 gpio_set_value(ETH_RST, 1);
273 imx51_add_fec(NULL);
274
275 gpio_request(CAN_IRQGPIO, "can_irq");
276 gpio_direction_input(CAN_IRQGPIO);
277 gpio_free(CAN_IRQGPIO);
278 gpio_request(CAN_NCS, "can_ncs");
279 gpio_direction_output(CAN_NCS, 1);
280 gpio_free(CAN_NCS);
281 gpio_request(CAN_RST, "can_rst");
282 gpio_direction_output(CAN_RST, 0);
283 msleep(20);
284 gpio_set_value(CAN_RST, 1);
285 imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
286 spi_register_board_info(cpuimx51sd_spi_device,
287 ARRAY_SIZE(cpuimx51sd_spi_device));
288
289 gpio_request(TSC2007_IRQGPIO, "tsc2007_irq");
290 gpio_direction_input(TSC2007_IRQGPIO);
291 gpio_free(TSC2007_IRQGPIO);
292
293 i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
294 ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
295 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
296
297 if (otg_mode_host)
298 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
299 else {
300 initialize_otg_port(NULL);
301 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
302 }
303
304 gpio_request(USBH1_RST, "usb_rst");
305 gpio_direction_output(USBH1_RST, 0);
306 msleep(20);
307 gpio_set_value(USBH1_RST, 1);
308 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
309
310#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
311 eukrea_mbimxsd51_baseboard_init();
312#endif
313}
314
315static void __init eukrea_cpuimx51sd_timer_init(void)
316{
317 mx51_clocks_init(32768, 24000000, 22579200, 0);
318}
319
320static struct sys_timer mxc_timer = {
321 .init = eukrea_cpuimx51sd_timer_init,
322};
323
324MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
325 /* Maintainer: Eric Bénard <eric@eukrea.com> */
326 .boot_params = PHYS_OFFSET + 0x100,
327 .map_io = mx51_map_io,
328 .init_irq = mx51_init_irq,
329 .init_machine = eukrea_cpuimx51sd_init,
330 .timer = &mxc_timer,
331MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index f95c2fd94667..79ce8dcf3cda 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -13,6 +13,7 @@
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/input/matrix_keypad.h> 15#include <linux/input/matrix_keypad.h>
16#include <linux/spi/spi.h>
16 17
17#include <asm/mach-types.h> 18#include <asm/mach-types.h>
18#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
@@ -21,12 +22,13 @@
21#include <mach/hardware.h> 22#include <mach/hardware.h>
22#include <mach/common.h> 23#include <mach/common.h>
23#include <mach/iomux-mx51.h> 24#include <mach/iomux-mx51.h>
24#include <mach/imx-uart.h>
25#include <mach/3ds_debugboard.h> 25#include <mach/3ds_debugboard.h>
26 26
27#include "devices-imx51.h"
27#include "devices.h" 28#include "devices.h"
28 29
29#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6) 30#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
31#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28)
30 32
31static struct pad_desc mx51_3ds_pads[] = { 33static struct pad_desc mx51_3ds_pads[] = {
32 /* UART1 */ 34 /* UART1 */
@@ -61,19 +63,25 @@ static struct pad_desc mx51_3ds_pads[] = {
61 MX51_PAD_KEY_COL3__KEY_COL3, 63 MX51_PAD_KEY_COL3__KEY_COL3,
62 MX51_PAD_KEY_COL4__KEY_COL4, 64 MX51_PAD_KEY_COL4__KEY_COL4,
63 MX51_PAD_KEY_COL5__KEY_COL5, 65 MX51_PAD_KEY_COL5__KEY_COL5,
66
67 /* eCSPI2 */
68 MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
69 MX51_PAD_NANDF_RB3__ECSPI2_MISO,
70 MX51_PAD_NANDF_D15__ECSPI2_MOSI,
71 MX51_PAD_NANDF_D12__GPIO_3_28,
64}; 72};
65 73
66/* Serial ports */ 74/* Serial ports */
67#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) 75#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
68static struct imxuart_platform_data uart_pdata = { 76static const struct imxuart_platform_data uart_pdata __initconst = {
69 .flags = IMXUART_HAVE_RTSCTS, 77 .flags = IMXUART_HAVE_RTSCTS,
70}; 78};
71 79
72static inline void mxc_init_imx_uart(void) 80static inline void mxc_init_imx_uart(void)
73{ 81{
74 mxc_register_device(&mxc_uart_device0, &uart_pdata); 82 imx51_add_imx_uart(0, &uart_pdata);
75 mxc_register_device(&mxc_uart_device1, &uart_pdata); 83 imx51_add_imx_uart(1, &uart_pdata);
76 mxc_register_device(&mxc_uart_device2, &uart_pdata); 84 imx51_add_imx_uart(2, &uart_pdata);
77} 85}
78#else /* !SERIAL_IMX */ 86#else /* !SERIAL_IMX */
79static inline void mxc_init_imx_uart(void) 87static inline void mxc_init_imx_uart(void)
@@ -127,6 +135,26 @@ static inline void mxc_init_keypad(void)
127} 135}
128#endif 136#endif
129 137
138static int mx51_3ds_spi2_cs[] = {
139 MXC_SPI_CS(0),
140 MX51_3DS_ECSPI2_CS,
141};
142
143static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = {
144 .chipselect = mx51_3ds_spi2_cs,
145 .num_chipselect = ARRAY_SIZE(mx51_3ds_spi2_cs),
146};
147
148static struct spi_board_info mx51_3ds_spi_nor_device[] = {
149 {
150 .modalias = "m25p80",
151 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
152 .bus_num = 1,
153 .chip_select = 1,
154 .mode = SPI_MODE_0,
155 .platform_data = NULL,},
156};
157
130/* 158/*
131 * Board specific initialization. 159 * Board specific initialization.
132 */ 160 */
@@ -136,6 +164,10 @@ static void __init mxc_board_init(void)
136 ARRAY_SIZE(mx51_3ds_pads)); 164 ARRAY_SIZE(mx51_3ds_pads));
137 mxc_init_imx_uart(); 165 mxc_init_imx_uart();
138 166
167 imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
168 spi_register_board_info(mx51_3ds_spi_nor_device,
169 ARRAY_SIZE(mx51_3ds_spi_nor_device));
170
139 if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT)) 171 if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
140 printk(KERN_WARNING "Init of the debugboard failed, all " 172 printk(KERN_WARNING "Init of the debugboard failed, all "
141 "devices on the board are unusable.\n"); 173 "devices on the board are unusable.\n");
@@ -154,8 +186,6 @@ static struct sys_timer mxc_timer = {
154 186
155MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") 187MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
156 /* Maintainer: Freescale Semiconductor, Inc. */ 188 /* Maintainer: Freescale Semiconductor, Inc. */
157 .phys_io = MX51_AIPS1_BASE_ADDR,
158 .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
159 .boot_params = PHYS_OFFSET + 0x100, 189 .boot_params = PHYS_OFFSET + 0x100,
160 .map_io = mx51_map_io, 190 .map_io = mx51_map_io,
161 .init_irq = mx51_init_irq, 191 .init_irq = mx51_init_irq,
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 6e384d92e625..0821fe9b3b27 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -17,12 +17,11 @@
17#include <linux/delay.h> 17#include <linux/delay.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/fsl_devices.h> 19#include <linux/fsl_devices.h>
20#include <linux/fec.h>
20 21
21#include <mach/common.h> 22#include <mach/common.h>
22#include <mach/hardware.h> 23#include <mach/hardware.h>
23#include <mach/imx-uart.h>
24#include <mach/iomux-mx51.h> 24#include <mach/iomux-mx51.h>
25#include <mach/i2c.h>
26#include <mach/mxc_ehci.h> 25#include <mach/mxc_ehci.h>
27 26
28#include <asm/irq.h> 27#include <asm/irq.h>
@@ -31,11 +30,13 @@
31#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
32#include <asm/mach/time.h> 31#include <asm/mach/time.h>
33 32
33#include "devices-imx51.h"
34#include "devices.h" 34#include "devices.h"
35 35
36#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */ 36#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */
37#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */ 37#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */
38#define BABBAGE_PHY_RESET (1*32 +5) /* GPIO_2_5 */ 38#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */
39#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */
39 40
40/* USB_CTRL_1 */ 41/* USB_CTRL_1 */
41#define MX51_USB_CTRL_1_OFFSET 0x10 42#define MX51_USB_CTRL_1_OFFSET 0x10
@@ -45,10 +46,6 @@
45#define MX51_USB_PLL_DIV_19_2_MHZ 0x01 46#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
46#define MX51_USB_PLL_DIV_24_MHZ 0x02 47#define MX51_USB_PLL_DIV_24_MHZ 0x02
47 48
48static struct platform_device *devices[] __initdata = {
49 &mxc_fec_device,
50};
51
52static struct pad_desc mx51babbage_pads[] = { 49static struct pad_desc mx51babbage_pads[] = {
53 /* UART1 */ 50 /* UART1 */
54 MX51_PAD_UART1_RXD__UART1_RXD, 51 MX51_PAD_UART1_RXD__UART1_RXD,
@@ -93,19 +90,41 @@ static struct pad_desc mx51babbage_pads[] = {
93 90
94 /* USB HUB reset line*/ 91 /* USB HUB reset line*/
95 MX51_PAD_GPIO_1_7__GPIO_1_7, 92 MX51_PAD_GPIO_1_7__GPIO_1_7,
93
94 /* FEC */
95 MX51_PAD_EIM_EB2__FEC_MDIO,
96 MX51_PAD_EIM_EB3__FEC_RDAT1,
97 MX51_PAD_EIM_CS2__FEC_RDAT2,
98 MX51_PAD_EIM_CS3__FEC_RDAT3,
99 MX51_PAD_EIM_CS4__FEC_RX_ER,
100 MX51_PAD_EIM_CS5__FEC_CRS,
101 MX51_PAD_NANDF_RB2__FEC_COL,
102 MX51_PAD_NANDF_RB3__FEC_RXCLK,
103 MX51_PAD_NANDF_RB6__FEC_RDAT0,
104 MX51_PAD_NANDF_RB7__FEC_TDAT0,
105 MX51_PAD_NANDF_CS2__FEC_TX_ER,
106 MX51_PAD_NANDF_CS3__FEC_MDC,
107 MX51_PAD_NANDF_CS4__FEC_TDAT1,
108 MX51_PAD_NANDF_CS5__FEC_TDAT2,
109 MX51_PAD_NANDF_CS6__FEC_TDAT3,
110 MX51_PAD_NANDF_CS7__FEC_TX_EN,
111 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
112
113 /* FEC PHY reset line */
114 MX51_PAD_EIM_A20__GPIO_2_14,
96}; 115};
97 116
98/* Serial ports */ 117/* Serial ports */
99#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE) 118#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
100static struct imxuart_platform_data uart_pdata = { 119static const struct imxuart_platform_data uart_pdata __initconst = {
101 .flags = IMXUART_HAVE_RTSCTS, 120 .flags = IMXUART_HAVE_RTSCTS,
102}; 121};
103 122
104static inline void mxc_init_imx_uart(void) 123static inline void mxc_init_imx_uart(void)
105{ 124{
106 mxc_register_device(&mxc_uart_device0, &uart_pdata); 125 imx51_add_imx_uart(0, &uart_pdata);
107 mxc_register_device(&mxc_uart_device1, &uart_pdata); 126 imx51_add_imx_uart(1, &uart_pdata);
108 mxc_register_device(&mxc_uart_device2, &uart_pdata); 127 imx51_add_imx_uart(2, &uart_pdata);
109} 128}
110#else /* !SERIAL_IMX */ 129#else /* !SERIAL_IMX */
111static inline void mxc_init_imx_uart(void) 130static inline void mxc_init_imx_uart(void)
@@ -113,7 +132,7 @@ static inline void mxc_init_imx_uart(void)
113} 132}
114#endif /* SERIAL_IMX */ 133#endif /* SERIAL_IMX */
115 134
116static struct imxi2c_platform_data babbage_i2c_data = { 135static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
117 .bitrate = 100000, 136 .bitrate = 100000,
118}; 137};
119 138
@@ -171,6 +190,22 @@ static inline void babbage_usbhub_reset(void)
171 gpio_set_value(BABBAGE_USB_HUB_RESET, 1); 190 gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
172} 191}
173 192
193static inline void babbage_fec_reset(void)
194{
195 int ret;
196
197 /* reset FEC PHY */
198 ret = gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset");
199 if (ret) {
200 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
201 return;
202 }
203 gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0);
204 gpio_set_value(BABBAGE_FEC_PHY_RESET, 0);
205 msleep(1);
206 gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
207}
208
174/* This function is board specific as the bit mask for the plldiv will also 209/* This function is board specific as the bit mask for the plldiv will also
175be different for other Freescale SoCs, thus a common bitmask is not 210be different for other Freescale SoCs, thus a common bitmask is not
176possible and cannot get place in /plat-mxc/ehci.c.*/ 211possible and cannot get place in /plat-mxc/ehci.c.*/
@@ -178,7 +213,7 @@ static int initialize_otg_port(struct platform_device *pdev)
178{ 213{
179 u32 v; 214 u32 v;
180 void __iomem *usb_base; 215 void __iomem *usb_base;
181 u32 usbother_base; 216 void __iomem *usbother_base;
182 217
183 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); 218 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
184 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 219 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -196,7 +231,7 @@ static int initialize_usbh1_port(struct platform_device *pdev)
196{ 231{
197 u32 v; 232 u32 v;
198 void __iomem *usb_base; 233 void __iomem *usb_base;
199 u32 usbother_base; 234 void __iomem *usbother_base;
200 235
201 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); 236 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
202 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 237 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
@@ -250,10 +285,11 @@ static void __init mxc_board_init(void)
250 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, 285 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
251 ARRAY_SIZE(mx51babbage_pads)); 286 ARRAY_SIZE(mx51babbage_pads));
252 mxc_init_imx_uart(); 287 mxc_init_imx_uart();
253 platform_add_devices(devices, ARRAY_SIZE(devices)); 288 babbage_fec_reset();
289 imx51_add_fec(NULL);
254 290
255 mxc_register_device(&mxc_i2c_device0, &babbage_i2c_data); 291 imx51_add_imx_i2c(0, &babbage_i2c_data);
256 mxc_register_device(&mxc_i2c_device1, &babbage_i2c_data); 292 imx51_add_imx_i2c(1, &babbage_i2c_data);
257 mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data); 293 mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
258 294
259 if (otg_mode_host) 295 if (otg_mode_host)
@@ -281,9 +317,7 @@ static struct sys_timer mxc_timer = {
281 317
282MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") 318MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
283 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */ 319 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
284 .phys_io = MX51_AIPS1_BASE_ADDR, 320 .boot_params = MX51_PHYS_OFFSET + 0x100,
285 .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
286 .boot_params = PHYS_OFFSET + 0x100,
287 .map_io = mx51_map_io, 321 .map_io = mx51_map_io,
288 .init_irq = mx51_init_irq, 322 .init_irq = mx51_init_irq,
289 .init_machine = mxc_board_init, 323 .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
new file mode 100644
index 000000000000..6e623bda3ee7
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -0,0 +1,119 @@
1/*
2 * Copyright (C) 2010 Linaro Limited
3 *
4 * based on code from the following
5 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 * Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
7 * Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/gpio.h>
21#include <linux/delay.h>
22#include <linux/io.h>
23#include <linux/fsl_devices.h>
24
25#include <mach/common.h>
26#include <mach/hardware.h>
27#include <mach/iomux-mx51.h>
28#include <mach/i2c.h>
29#include <mach/mxc_ehci.h>
30
31#include <asm/irq.h>
32#include <asm/setup.h>
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/time.h>
36
37#include "devices-imx51.h"
38#include "devices.h"
39
40#define MX51_USB_PLL_DIV_24_MHZ 0x01
41
42static struct pad_desc mx51efikamx_pads[] = {
43 /* UART1 */
44 MX51_PAD_UART1_RXD__UART1_RXD,
45 MX51_PAD_UART1_TXD__UART1_TXD,
46 MX51_PAD_UART1_RTS__UART1_RTS,
47 MX51_PAD_UART1_CTS__UART1_CTS,
48};
49
50/* Serial ports */
51#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
52static const struct imxuart_platform_data uart_pdata = {
53 .flags = IMXUART_HAVE_RTSCTS,
54};
55
56static inline void mxc_init_imx_uart(void)
57{
58 imx51_add_imx_uart(0, &uart_pdata);
59 imx51_add_imx_uart(1, &uart_pdata);
60 imx51_add_imx_uart(2, &uart_pdata);
61}
62#else /* !SERIAL_IMX */
63static inline void mxc_init_imx_uart(void)
64{
65}
66#endif /* SERIAL_IMX */
67
68/* This function is board specific as the bit mask for the plldiv will also
69 * be different for other Freescale SoCs, thus a common bitmask is not
70 * possible and cannot get place in /plat-mxc/ehci.c.
71 */
72static int initialize_otg_port(struct platform_device *pdev)
73{
74 u32 v;
75 void __iomem *usb_base;
76 void __iomem *usbother_base;
77 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
78 usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
79
80 /* Set the PHY clock to 19.2MHz */
81 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
82 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
83 v |= MX51_USB_PLL_DIV_24_MHZ;
84 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
85 iounmap(usb_base);
86 return 0;
87}
88
89static struct mxc_usbh_platform_data dr_utmi_config = {
90 .init = initialize_otg_port,
91 .portsc = MXC_EHCI_UTMI_16BIT,
92 .flags = MXC_EHCI_INTERNAL_PHY,
93};
94
95static void __init mxc_board_init(void)
96{
97 mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
98 ARRAY_SIZE(mx51efikamx_pads));
99 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
100 mxc_init_imx_uart();
101}
102
103static void __init mx51_efikamx_timer_init(void)
104{
105 mx51_clocks_init(32768, 24000000, 22579200, 24576000);
106}
107
108static struct sys_timer mxc_timer = {
109 .init = mx51_efikamx_timer_init,
110};
111
112MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
113 /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
114 .boot_params = MX51_PHYS_OFFSET + 0x100,
115 .map_io = mx51_map_io,
116 .init_irq = mx51_init_irq,
117 .init_machine = mxc_board_init,
118 .timer = &mxc_timer,
119MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index 57c10a9926cc..f2aae92cf0e2 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -41,34 +41,66 @@ static struct clk usboh3_clk;
41 41
42#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ 42#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
43 43
44static int _clk_ccgr_enable(struct clk *clk) 44/* calculate best pre and post dividers to get the required divider */
45static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post,
46 u32 max_pre, u32 max_post)
45{ 47{
46 u32 reg; 48 if (div >= max_pre * max_post) {
49 *pre = max_pre;
50 *post = max_post;
51 } else if (div >= max_pre) {
52 u32 min_pre, temp_pre, old_err, err;
53 min_pre = DIV_ROUND_UP(div, max_post);
54 old_err = max_pre;
55 for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) {
56 err = div % temp_pre;
57 if (err == 0) {
58 *pre = temp_pre;
59 break;
60 }
61 err = temp_pre - err;
62 if (err < old_err) {
63 old_err = err;
64 *pre = temp_pre;
65 }
66 }
67 *post = DIV_ROUND_UP(div, *pre);
68 } else {
69 *pre = div;
70 *post = 1;
71 }
72}
73
74static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
75{
76 u32 reg = __raw_readl(clk->enable_reg);
77
78 reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
79 reg |= mode << clk->enable_shift;
47 80
48 reg = __raw_readl(clk->enable_reg);
49 reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift;
50 __raw_writel(reg, clk->enable_reg); 81 __raw_writel(reg, clk->enable_reg);
82}
51 83
84static int _clk_ccgr_enable(struct clk *clk)
85{
86 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON);
52 return 0; 87 return 0;
53} 88}
54 89
55static void _clk_ccgr_disable(struct clk *clk) 90static void _clk_ccgr_disable(struct clk *clk)
56{ 91{
57 u32 reg; 92 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF);
58 reg = __raw_readl(clk->enable_reg); 93}
59 reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
60 __raw_writel(reg, clk->enable_reg);
61 94
95static int _clk_ccgr_enable_inrun(struct clk *clk)
96{
97 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
98 return 0;
62} 99}
63 100
64static void _clk_ccgr_disable_inwait(struct clk *clk) 101static void _clk_ccgr_disable_inwait(struct clk *clk)
65{ 102{
66 u32 reg; 103 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
67
68 reg = __raw_readl(clk->enable_reg);
69 reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
70 reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift;
71 __raw_writel(reg, clk->enable_reg);
72} 104}
73 105
74/* 106/*
@@ -542,60 +574,60 @@ static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
542 return 0; 574 return 0;
543} 575}
544 576
545static unsigned long clk_uart_get_rate(struct clk *clk) 577#define clk_nfc_set_parent NULL
546{
547 u32 reg, prediv, podf;
548 unsigned long parent_rate;
549 578
550 parent_rate = clk_get_rate(clk->parent); 579static unsigned long clk_nfc_get_rate(struct clk *clk)
551 580{
552 reg = __raw_readl(MXC_CCM_CSCDR1); 581 unsigned long rate;
553 prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> 582 u32 reg, div;
554 MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1;
555 podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
556 MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
557 583
558 return parent_rate / (prediv * podf); 584 reg = __raw_readl(MXC_CCM_CBCDR);
585 div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
586 MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
587 rate = clk_get_rate(clk->parent) / div;
588 WARN_ON(rate == 0);
589 return rate;
559} 590}
560 591
561static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) 592static unsigned long clk_nfc_round_rate(struct clk *clk,
593 unsigned long rate)
562{ 594{
563 u32 reg, mux; 595 u32 div;
596 unsigned long parent_rate = clk_get_rate(clk->parent);
564 597
565 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, 598 if (!rate)
566 &lp_apm_clk); 599 return -EINVAL;
567 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK;
568 reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET;
569 __raw_writel(reg, MXC_CCM_CSCMR1);
570 600
571 return 0; 601 div = parent_rate / rate;
572}
573 602
574static unsigned long clk_usboh3_get_rate(struct clk *clk) 603 if (parent_rate % rate)
575{ 604 div++;
576 u32 reg, prediv, podf;
577 unsigned long parent_rate;
578 605
579 parent_rate = clk_get_rate(clk->parent); 606 if (div > 8)
607 return -EINVAL;
580 608
581 reg = __raw_readl(MXC_CCM_CSCDR1); 609 return parent_rate / div;
582 prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >>
583 MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1;
584 podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >>
585 MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1;
586 610
587 return parent_rate / (prediv * podf);
588} 611}
589 612
590static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent) 613static int clk_nfc_set_rate(struct clk *clk, unsigned long rate)
591{ 614{
592 u32 reg, mux; 615 u32 reg, div;
616
617 div = clk_get_rate(clk->parent) / rate;
618 if (div == 0)
619 div++;
620 if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8))
621 return -EINVAL;
622
623 reg = __raw_readl(MXC_CCM_CBCDR);
624 reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
625 reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
626 __raw_writel(reg, MXC_CCM_CBCDR);
593 627
594 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, 628 while (__raw_readl(MXC_CCM_CDHIPR) &
595 &lp_apm_clk); 629 MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
596 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK; 630 }
597 reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
598 __raw_writel(reg, MXC_CCM_CSCMR1);
599 631
600 return 0; 632 return 0;
601} 633}
@@ -620,6 +652,17 @@ static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
620 return ckih2_reference; 652 return ckih2_reference;
621} 653}
622 654
655static unsigned long clk_emi_slow_get_rate(struct clk *clk)
656{
657 u32 reg, div;
658
659 reg = __raw_readl(MXC_CCM_CBCDR);
660 div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
661 MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
662
663 return clk_get_rate(clk->parent) / div;
664}
665
623/* External high frequency clock */ 666/* External high frequency clock */
624static struct clk ckih_clk = { 667static struct clk ckih_clk = {
625 .get_rate = get_high_reference_clock_rate, 668 .get_rate = get_high_reference_clock_rate,
@@ -715,18 +758,6 @@ static struct clk ipg_perclk = {
715 .set_parent = _clk_ipg_per_set_parent, 758 .set_parent = _clk_ipg_per_set_parent,
716}; 759};
717 760
718static struct clk uart_root_clk = {
719 .parent = &pll2_sw_clk,
720 .get_rate = clk_uart_get_rate,
721 .set_parent = _clk_uart_set_parent,
722};
723
724static struct clk usboh3_clk = {
725 .parent = &pll2_sw_clk,
726 .get_rate = clk_usboh3_get_rate,
727 .set_parent = _clk_usboh3_set_parent,
728};
729
730static struct clk ahb_max_clk = { 761static struct clk ahb_max_clk = {
731 .parent = &ahb_clk, 762 .parent = &ahb_clk,
732 .enable_reg = MXC_CCM_CCGR0, 763 .enable_reg = MXC_CCM_CCGR0,
@@ -762,45 +793,183 @@ static struct clk kpp_clk = {
762 .id = 0, 793 .id = 0,
763}; 794};
764 795
765#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \ 796static struct clk emi_slow_clk = {
797 .parent = &pll2_sw_clk,
798 .enable_reg = MXC_CCM_CCGR5,
799 .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
800 .enable = _clk_ccgr_enable,
801 .disable = _clk_ccgr_disable_inwait,
802 .get_rate = clk_emi_slow_get_rate,
803};
804
805#define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s) \
766 static struct clk name = { \ 806 static struct clk name = { \
767 .id = i, \ 807 .id = i, \
768 .enable_reg = er, \ 808 .enable_reg = er, \
769 .enable_shift = es, \ 809 .enable_shift = es, \
770 .get_rate = gr, \ 810 .get_rate = pfx##_get_rate, \
771 .set_rate = sr, \ 811 .set_rate = pfx##_set_rate, \
812 .round_rate = pfx##_round_rate, \
813 .set_parent = pfx##_set_parent, \
772 .enable = _clk_ccgr_enable, \ 814 .enable = _clk_ccgr_enable, \
773 .disable = _clk_ccgr_disable, \ 815 .disable = _clk_ccgr_disable, \
774 .parent = p, \ 816 .parent = p, \
775 .secondary = s, \ 817 .secondary = s, \
776 } 818 }
777 819
778/* DEFINE_CLOCK(name, id, enable_reg, enable_shift, 820#define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s) \
779 get_rate, set_rate, parent, secondary); */ 821 static struct clk name = { \
822 .id = i, \
823 .enable_reg = er, \
824 .enable_shift = es, \
825 .get_rate = pfx##_get_rate, \
826 .set_rate = pfx##_set_rate, \
827 .set_parent = pfx##_set_parent, \
828 .enable = _clk_max_enable, \
829 .disable = _clk_max_disable, \
830 .parent = p, \
831 .secondary = s, \
832 }
833
834#define CLK_GET_RATE(name, nr, bitsname) \
835static unsigned long clk_##name##_get_rate(struct clk *clk) \
836{ \
837 u32 reg, pred, podf; \
838 \
839 reg = __raw_readl(MXC_CCM_CSCDR##nr); \
840 pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK) \
841 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
842 podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK) \
843 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
844 \
845 return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), \
846 (pred + 1) * (podf + 1)); \
847}
848
849#define CLK_SET_PARENT(name, nr, bitsname) \
850static int clk_##name##_set_parent(struct clk *clk, struct clk *parent) \
851{ \
852 u32 reg, mux; \
853 \
854 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, \
855 &pll3_sw_clk, &lp_apm_clk); \
856 reg = __raw_readl(MXC_CCM_CSCMR##nr) & \
857 ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK; \
858 reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET; \
859 __raw_writel(reg, MXC_CCM_CSCMR##nr); \
860 \
861 return 0; \
862}
863
864#define CLK_SET_RATE(name, nr, bitsname) \
865static int clk_##name##_set_rate(struct clk *clk, unsigned long rate) \
866{ \
867 u32 reg, div, parent_rate; \
868 u32 pre = 0, post = 0; \
869 \
870 parent_rate = clk_get_rate(clk->parent); \
871 div = parent_rate / rate; \
872 \
873 if ((parent_rate / div) != rate) \
874 return -EINVAL; \
875 \
876 __calc_pre_post_dividers(div, &pre, &post, \
877 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >> \
878 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1, \
879 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >> \
880 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\
881 \
882 /* Set sdhc1 clock divider */ \
883 reg = __raw_readl(MXC_CCM_CSCDR##nr) & \
884 ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK \
885 | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK); \
886 reg |= (post - 1) << \
887 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
888 reg |= (pre - 1) << \
889 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
890 __raw_writel(reg, MXC_CCM_CSCDR##nr); \
891 \
892 return 0; \
893}
894
895/* UART */
896CLK_GET_RATE(uart, 1, UART)
897CLK_SET_PARENT(uart, 1, UART)
898
899static struct clk uart_root_clk = {
900 .parent = &pll2_sw_clk,
901 .get_rate = clk_uart_get_rate,
902 .set_parent = clk_uart_set_parent,
903};
904
905/* USBOH3 */
906CLK_GET_RATE(usboh3, 1, USBOH3)
907CLK_SET_PARENT(usboh3, 1, USBOH3)
908
909static struct clk usboh3_clk = {
910 .parent = &pll2_sw_clk,
911 .get_rate = clk_usboh3_get_rate,
912 .set_parent = clk_usboh3_set_parent,
913};
914
915/* eCSPI */
916CLK_GET_RATE(ecspi, 2, CSPI)
917CLK_SET_PARENT(ecspi, 1, CSPI)
918
919static struct clk ecspi_main_clk = {
920 .parent = &pll3_sw_clk,
921 .get_rate = clk_ecspi_get_rate,
922 .set_parent = clk_ecspi_set_parent,
923};
924
925/* eSDHC */
926CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
927CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
928CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
929
930CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
931CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
932CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
933
934#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \
935 static struct clk name = { \
936 .id = i, \
937 .enable_reg = er, \
938 .enable_shift = es, \
939 .get_rate = gr, \
940 .set_rate = sr, \
941 .enable = e, \
942 .disable = d, \
943 .parent = p, \
944 .secondary = s, \
945 }
946
947#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \
948 DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
780 949
781/* Shared peripheral bus arbiter */ 950/* Shared peripheral bus arbiter */
782DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET, 951DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
783 NULL, NULL, &ipg_clk, NULL); 952 NULL, NULL, &ipg_clk, NULL);
784 953
785/* UART */ 954/* UART */
786DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
787 NULL, NULL, &uart_root_clk, NULL);
788DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
789 NULL, NULL, &uart_root_clk, NULL);
790DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
791 NULL, NULL, &uart_root_clk, NULL);
792DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET, 955DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
793 NULL, NULL, &ipg_clk, &aips_tz1_clk); 956 NULL, NULL, &ipg_clk, &aips_tz1_clk);
794DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET, 957DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
795 NULL, NULL, &ipg_clk, &aips_tz1_clk); 958 NULL, NULL, &ipg_clk, &aips_tz1_clk);
796DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET, 959DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
797 NULL, NULL, &ipg_clk, &spba_clk); 960 NULL, NULL, &ipg_clk, &spba_clk);
961DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
962 NULL, NULL, &uart_root_clk, &uart1_ipg_clk);
963DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
964 NULL, NULL, &uart_root_clk, &uart2_ipg_clk);
965DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
966 NULL, NULL, &uart_root_clk, &uart3_ipg_clk);
798 967
799/* GPT */ 968/* GPT */
800DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
801 NULL, NULL, &ipg_clk, NULL);
802DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, 969DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
803 NULL, NULL, &ipg_clk, NULL); 970 NULL, NULL, &ipg_clk, NULL);
971DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
972 NULL, NULL, &ipg_clk, &gpt_ipg_clk);
804 973
805/* I2C */ 974/* I2C */
806DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET, 975DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
@@ -814,6 +983,52 @@ DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
814DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, 983DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
815 NULL, NULL, &ipg_clk, NULL); 984 NULL, NULL, &ipg_clk, NULL);
816 985
986/* NFC */
987DEFINE_CLOCK_CCGR(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
988 clk_nfc, &emi_slow_clk, NULL);
989
990/* SSI */
991DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET,
992 NULL, NULL, &ipg_clk, NULL);
993DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET,
994 NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk);
995DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
996 NULL, NULL, &ipg_clk, NULL);
997DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
998 NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
999
1000/* eCSPI */
1001DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
1002 NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
1003 &ipg_clk, &spba_clk);
1004DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
1005 NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
1006DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
1007 NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
1008 &ipg_clk, &aips_tz2_clk);
1009DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
1010 NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
1011
1012/* CSPI */
1013DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
1014 NULL, NULL, &ipg_clk, &aips_tz2_clk);
1015DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
1016 NULL, NULL, &ipg_clk, &cspi_ipg_clk);
1017
1018/* SDMA */
1019DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET,
1020 NULL, NULL, &ahb_clk, NULL);
1021
1022/* eSDHC */
1023DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET,
1024 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1025DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
1026 clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
1027DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
1028 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1029DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
1030 clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
1031
817#define _REGISTER_CLOCK(d, n, c) \ 1032#define _REGISTER_CLOCK(d, n, c) \
818 { \ 1033 { \
819 .dev_id = d, \ 1034 .dev_id = d, \
@@ -837,6 +1052,18 @@ static struct clk_lookup lookups[] = {
837 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) 1052 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
838 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) 1053 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
839 _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk) 1054 _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
1055 _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
1056 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
1057 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
1058 _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
1059 _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
1060 _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
1061 _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
1062 _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
1063 _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
1064 _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
1065 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
1066 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
840}; 1067};
841 1068
842static void clk_tree_init(void) 1069static void clk_tree_init(void)
@@ -880,6 +1107,14 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
880 /* set the usboh3_clk parent to pll2_sw_clk */ 1107 /* set the usboh3_clk parent to pll2_sw_clk */
881 clk_set_parent(&usboh3_clk, &pll2_sw_clk); 1108 clk_set_parent(&usboh3_clk, &pll2_sw_clk);
882 1109
1110 /* Set SDHC parents to be PLL2 */
1111 clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
1112 clk_set_parent(&esdhc2_clk, &pll2_sw_clk);
1113
1114 /* set SDHC root clock as 166.25MHZ*/
1115 clk_set_rate(&esdhc1_clk, 166250000);
1116 clk_set_rate(&esdhc2_clk, 166250000);
1117
883 /* System timer */ 1118 /* System timer */
884 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), 1119 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
885 MX51_MXC_INT_GPT); 1120 MX51_MXC_INT_GPT);
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index 2d37785e3857..eaacb6e9b5d0 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -70,6 +70,25 @@ int mx51_revision(void)
70} 70}
71EXPORT_SYMBOL(mx51_revision); 71EXPORT_SYMBOL(mx51_revision);
72 72
73#ifdef CONFIG_NEON
74
75/*
76 * All versions of the silicon before Rev. 3 have broken NEON implementations.
77 * Dependent on link order - so the assumption is that vfp_init is called
78 * before us.
79 */
80static int __init mx51_neon_fixup(void)
81{
82 if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) {
83 elf_hwcap &= ~HWCAP_NEON;
84 pr_info("Turning off NEON support, detected broken NEON implementation\n");
85 }
86 return 0;
87}
88
89late_initcall(mx51_neon_fixup);
90#endif
91
73static int __init post_cpu_init(void) 92static int __init post_cpu_init(void)
74{ 93{
75 unsigned int reg; 94 unsigned int reg;
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
new file mode 100644
index 000000000000..5cc910e60538
--- /dev/null
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -0,0 +1,42 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/mx51.h>
10#include <mach/devices-common.h>
11
12extern const struct imx_fec_data imx51_fec_data __initconst;
13#define imx51_add_fec(pdata) \
14 imx_add_fec(&imx51_fec_data, pdata)
15
16extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst;
17#define imx51_add_imx_i2c(id, pdata) \
18 imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
19
20extern const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst;
21#define imx51_add_imx_ssi(id, pdata) \
22 imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
23
24extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst;
25#define imx51_add_imx_uart(id, pdata) \
26 imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
27
28extern const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst;
29#define imx51_add_mxc_nand(pdata) \
30 imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
31
32extern const struct imx_spi_imx_data imx51_cspi_data __initconst;
33#define imx51_add_cspi(pdata) \
34 imx_add_spi_imx(&imx51_cspi_data, pdata)
35
36extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst;
37#define imx51_add_ecspi(id, pdata) \
38 imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
39
40extern const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst;
41#define imx51_add_esdhc(id, pdata) \
42 imx_add_esdhc(&imx51_esdhc_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 1920ff4963b2..4c7be87a7c9d 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -17,120 +17,6 @@
17#include <mach/imx-uart.h> 17#include <mach/imx-uart.h>
18#include <mach/irqs.h> 18#include <mach/irqs.h>
19 19
20static struct resource uart0[] = {
21 {
22 .start = MX51_UART1_BASE_ADDR,
23 .end = MX51_UART1_BASE_ADDR + 0xfff,
24 .flags = IORESOURCE_MEM,
25 }, {
26 .start = MX51_MXC_INT_UART1,
27 .end = MX51_MXC_INT_UART1,
28 .flags = IORESOURCE_IRQ,
29 },
30};
31
32struct platform_device mxc_uart_device0 = {
33 .name = "imx-uart",
34 .id = 0,
35 .resource = uart0,
36 .num_resources = ARRAY_SIZE(uart0),
37};
38
39static struct resource uart1[] = {
40 {
41 .start = MX51_UART2_BASE_ADDR,
42 .end = MX51_UART2_BASE_ADDR + 0xfff,
43 .flags = IORESOURCE_MEM,
44 }, {
45 .start = MX51_MXC_INT_UART2,
46 .end = MX51_MXC_INT_UART2,
47 .flags = IORESOURCE_IRQ,
48 },
49};
50
51struct platform_device mxc_uart_device1 = {
52 .name = "imx-uart",
53 .id = 1,
54 .resource = uart1,
55 .num_resources = ARRAY_SIZE(uart1),
56};
57
58static struct resource uart2[] = {
59 {
60 .start = MX51_UART3_BASE_ADDR,
61 .end = MX51_UART3_BASE_ADDR + 0xfff,
62 .flags = IORESOURCE_MEM,
63 }, {
64 .start = MX51_MXC_INT_UART3,
65 .end = MX51_MXC_INT_UART3,
66 .flags = IORESOURCE_IRQ,
67 },
68};
69
70struct platform_device mxc_uart_device2 = {
71 .name = "imx-uart",
72 .id = 2,
73 .resource = uart2,
74 .num_resources = ARRAY_SIZE(uart2),
75};
76
77static struct resource mxc_fec_resources[] = {
78 {
79 .start = MX51_MXC_FEC_BASE_ADDR,
80 .end = MX51_MXC_FEC_BASE_ADDR + 0xfff,
81 .flags = IORESOURCE_MEM,
82 }, {
83 .start = MX51_MXC_INT_FEC,
84 .end = MX51_MXC_INT_FEC,
85 .flags = IORESOURCE_IRQ,
86 },
87};
88
89struct platform_device mxc_fec_device = {
90 .name = "fec",
91 .id = 0,
92 .num_resources = ARRAY_SIZE(mxc_fec_resources),
93 .resource = mxc_fec_resources,
94};
95
96static struct resource mxc_i2c0_resources[] = {
97 {
98 .start = MX51_I2C1_BASE_ADDR,
99 .end = MX51_I2C1_BASE_ADDR + SZ_4K - 1,
100 .flags = IORESOURCE_MEM,
101 }, {
102 .start = MX51_MXC_INT_I2C1,
103 .end = MX51_MXC_INT_I2C1,
104 .flags = IORESOURCE_IRQ,
105 },
106};
107
108struct platform_device mxc_i2c_device0 = {
109 .name = "imx-i2c",
110 .id = 0,
111 .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
112 .resource = mxc_i2c0_resources,
113};
114
115static struct resource mxc_i2c1_resources[] = {
116 {
117 .start = MX51_I2C2_BASE_ADDR,
118 .end = MX51_I2C2_BASE_ADDR + SZ_4K - 1,
119 .flags = IORESOURCE_MEM,
120 }, {
121 .start = MX51_MXC_INT_I2C2,
122 .end = MX51_MXC_INT_I2C2,
123 .flags = IORESOURCE_IRQ,
124 },
125};
126
127struct platform_device mxc_i2c_device1 = {
128 .name = "imx-i2c",
129 .id = 1,
130 .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
131 .resource = mxc_i2c1_resources,
132};
133
134static struct resource mxc_hsi2c_resources[] = { 20static struct resource mxc_hsi2c_resources[] = {
135 { 21 {
136 .start = MX51_HSI2C_DMA_BASE_ADDR, 22 .start = MX51_HSI2C_DMA_BASE_ADDR,
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index e509cfaad1d4..af1d07c0bbc1 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -1,12 +1,6 @@
1extern struct platform_device mxc_uart_device0;
2extern struct platform_device mxc_uart_device1;
3extern struct platform_device mxc_uart_device2;
4extern struct platform_device mxc_fec_device;
5extern struct platform_device mxc_usbdr_host_device; 1extern struct platform_device mxc_usbdr_host_device;
6extern struct platform_device mxc_usbh1_device; 2extern struct platform_device mxc_usbh1_device;
7extern struct platform_device mxc_usbdr_udc_device; 3extern struct platform_device mxc_usbdr_udc_device;
8extern struct platform_device mxc_wdt; 4extern struct platform_device mxc_wdt;
9extern struct platform_device mxc_i2c_device0;
10extern struct platform_device mxc_i2c_device1;
11extern struct platform_device mxc_hsi2c_device; 5extern struct platform_device mxc_hsi2c_device;
12extern struct platform_device mxc_keypad_device; 6extern struct platform_device mxc_keypad_device;
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
index ffa93d1d6ef8..a2e6e8c39d25 100644
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -30,6 +30,7 @@
30 30
31#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
32 32
33#include "devices-imx51.h"
33#include "devices.h" 34#include "devices.h"
34 35
35#define MBIMX51_TSC2007_GPIO (2*32 + 30) 36#define MBIMX51_TSC2007_GPIO (2*32 + 30)
@@ -112,9 +113,25 @@ static struct pad_desc mbimx51_pads[] = {
112 MX51_PAD_KEY_COL1__KEY_COL1, 113 MX51_PAD_KEY_COL1__KEY_COL1,
113 MX51_PAD_KEY_COL2__KEY_COL2, 114 MX51_PAD_KEY_COL2__KEY_COL2,
114 MX51_PAD_KEY_COL3__KEY_COL3, 115 MX51_PAD_KEY_COL3__KEY_COL3,
116
117 /* SD 1 */
118 MX51_PAD_SD1_CMD__SD1_CMD,
119 MX51_PAD_SD1_CLK__SD1_CLK,
120 MX51_PAD_SD1_DATA0__SD1_DATA0,
121 MX51_PAD_SD1_DATA1__SD1_DATA1,
122 MX51_PAD_SD1_DATA2__SD1_DATA2,
123 MX51_PAD_SD1_DATA3__SD1_DATA3,
124
125 /* SD 2 */
126 MX51_PAD_SD2_CMD__SD2_CMD,
127 MX51_PAD_SD2_CLK__SD2_CLK,
128 MX51_PAD_SD2_DATA0__SD2_DATA0,
129 MX51_PAD_SD2_DATA1__SD2_DATA1,
130 MX51_PAD_SD2_DATA2__SD2_DATA2,
131 MX51_PAD_SD2_DATA3__SD2_DATA3,
115}; 132};
116 133
117static struct imxuart_platform_data uart_pdata = { 134static const struct imxuart_platform_data uart_pdata __initconst = {
118 .flags = IMXUART_HAVE_RTSCTS, 135 .flags = IMXUART_HAVE_RTSCTS,
119}; 136};
120 137
@@ -158,9 +175,11 @@ struct tsc2007_platform_data tsc2007_data = {
158 175
159static struct i2c_board_info mbimx51_i2c_devices[] = { 176static struct i2c_board_info mbimx51_i2c_devices[] = {
160 { 177 {
161 I2C_BOARD_INFO("tsc2007", 0x48), 178 I2C_BOARD_INFO("tsc2007", 0x49),
162 .irq = MBIMX51_TSC2007_IRQ, 179 .irq = MBIMX51_TSC2007_IRQ,
163 .platform_data = &tsc2007_data, 180 .platform_data = &tsc2007_data,
181 }, {
182 I2C_BOARD_INFO("tlv320aic23", 0x1a),
164 }, 183 },
165}; 184};
166 185
@@ -172,8 +191,8 @@ void __init eukrea_mbimx51_baseboard_init(void)
172 mxc_iomux_v3_setup_multiple_pads(mbimx51_pads, 191 mxc_iomux_v3_setup_multiple_pads(mbimx51_pads,
173 ARRAY_SIZE(mbimx51_pads)); 192 ARRAY_SIZE(mbimx51_pads));
174 193
175 mxc_register_device(&mxc_uart_device1, NULL); 194 imx51_add_imx_uart(1, NULL);
176 mxc_register_device(&mxc_uart_device2, &uart_pdata); 195 imx51_add_imx_uart(2, &uart_pdata);
177 196
178 gpio_request(MBIMX51_LED0, "LED0"); 197 gpio_request(MBIMX51_LED0, "LED0");
179 gpio_direction_output(MBIMX51_LED0, 1); 198 gpio_direction_output(MBIMX51_LED0, 1);
@@ -197,4 +216,7 @@ void __init eukrea_mbimx51_baseboard_init(void)
197 set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING); 216 set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
198 i2c_register_board_info(1, mbimx51_i2c_devices, 217 i2c_register_board_info(1, mbimx51_i2c_devices,
199 ARRAY_SIZE(mbimx51_i2c_devices)); 218 ARRAY_SIZE(mbimx51_i2c_devices));
219
220 imx51_add_esdhc(0, NULL);
221 imx51_add_esdhc(1, NULL);
200} 222}
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
new file mode 100644
index 000000000000..2b48f5190830
--- /dev/null
+++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
@@ -0,0 +1,166 @@
1/*
2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm970-baseboard.c which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#include <linux/types.h>
23#include <linux/init.h>
24
25#include <linux/gpio.h>
26#include <linux/interrupt.h>
27#include <linux/irq.h>
28#include <linux/leds.h>
29#include <linux/platform_device.h>
30#include <linux/gpio_keys.h>
31#include <linux/input.h>
32#include <linux/i2c.h>
33
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/time.h>
37#include <asm/mach/map.h>
38
39#include <mach/hardware.h>
40#include <mach/common.h>
41#include <mach/imx-uart.h>
42#include <mach/iomux-mx51.h>
43#include <mach/audmux.h>
44
45#include "devices-imx51.h"
46#include "devices.h"
47
48#define MBIMXSD_GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, \
49 MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
50
51static struct pad_desc eukrea_mbimxsd_pads[] = {
52 /* LED */
53 MX51_PAD_NANDF_D10__GPIO_3_30,
54 /* SWITCH */
55 MBIMXSD_GPIO_3_31,
56 /* UART2 */
57 MX51_PAD_UART2_RXD__UART2_RXD,
58 MX51_PAD_UART2_TXD__UART2_TXD,
59 /* UART 3 */
60 MX51_PAD_UART3_RXD__UART3_RXD,
61 MX51_PAD_UART3_TXD__UART3_TXD,
62 MX51_PAD_KEY_COL4__UART3_RTS,
63 MX51_PAD_KEY_COL5__UART3_CTS,
64 /* SD */
65 MX51_PAD_SD1_CMD__SD1_CMD,
66 MX51_PAD_SD1_CLK__SD1_CLK,
67 MX51_PAD_SD1_DATA0__SD1_DATA0,
68 MX51_PAD_SD1_DATA1__SD1_DATA1,
69 MX51_PAD_SD1_DATA2__SD1_DATA2,
70 MX51_PAD_SD1_DATA3__SD1_DATA3,
71};
72
73#define GPIO_LED1 (2 * 32 + 30)
74#define GPIO_SWITCH1 (2 * 32 + 31)
75
76static struct gpio_led eukrea_mbimxsd_leds[] = {
77 {
78 .name = "led1",
79 .default_trigger = "heartbeat",
80 .active_low = 1,
81 .gpio = GPIO_LED1,
82 },
83};
84
85static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
86 .leds = eukrea_mbimxsd_leds,
87 .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
88};
89
90static struct platform_device eukrea_mbimxsd_leds_gpio = {
91 .name = "leds-gpio",
92 .id = -1,
93 .dev = {
94 .platform_data = &eukrea_mbimxsd_led_info,
95 },
96};
97
98static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
99 {
100 .gpio = GPIO_SWITCH1,
101 .code = BTN_0,
102 .desc = "BP1",
103 .active_low = 1,
104 .wakeup = 1,
105 },
106};
107
108static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
109 .buttons = eukrea_mbimxsd_gpio_buttons,
110 .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
111};
112
113static struct platform_device eukrea_mbimxsd_button_device = {
114 .name = "gpio-keys",
115 .id = -1,
116 .num_resources = 0,
117 .dev = {
118 .platform_data = &eukrea_mbimxsd_button_data,
119 }
120};
121
122static struct platform_device *platform_devices[] __initdata = {
123 &eukrea_mbimxsd_leds_gpio,
124 &eukrea_mbimxsd_button_device,
125};
126
127static const struct imxuart_platform_data uart_pdata __initconst = {
128 .flags = IMXUART_HAVE_RTSCTS,
129};
130
131static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
132 {
133 I2C_BOARD_INFO("tlv320aic23", 0x1a),
134 },
135};
136
137/*
138 * system init for baseboard usage. Will be called by cpuimx51sd init.
139 *
140 * Add platform devices present on this baseboard and init
141 * them from CPU side as far as required to use them later on
142 */
143void __init eukrea_mbimxsd51_baseboard_init(void)
144{
145 if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
146 ARRAY_SIZE(eukrea_mbimxsd_pads)))
147 printk(KERN_ERR "error setting mbimxsd pads !\n");
148
149 imx51_add_imx_uart(1, NULL);
150 imx51_add_imx_uart(2, &uart_pdata);
151
152 imx51_add_esdhc(0, NULL);
153
154 gpio_request(GPIO_LED1, "LED1");
155 gpio_direction_output(GPIO_LED1, 1);
156 gpio_free(GPIO_LED1);
157
158 gpio_request(GPIO_SWITCH1, "SWITCH1");
159 gpio_direction_input(GPIO_SWITCH1);
160 gpio_free(GPIO_SWITCH1);
161
162 i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
163 ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
164
165 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
166}
diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c
index 69816ba82930..395d83be8c98 100644
--- a/arch/arm/mach-mxc91231/magx-zn5.c
+++ b/arch/arm/mach-mxc91231/magx-zn5.c
@@ -53,8 +53,6 @@ struct sys_timer zn5_timer = {
53}; 53};
54 54
55MACHINE_START(MAGX_ZN5, "Motorola Zn5") 55MACHINE_START(MAGX_ZN5, "Motorola Zn5")
56 .phys_io = MXC91231_AIPS1_BASE_ADDR,
57 .io_pg_offst = ((MXC91231_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
58 .boot_params = MXC91231_PHYS_OFFSET + 0x100, 56 .boot_params = MXC91231_PHYS_OFFSET + 0x100,
59 .map_io = mxc91231_map_io, 57 .map_io = mxc91231_map_io,
60 .init_irq = mxc91231_init_irq, 58 .init_irq = mxc91231_init_irq,
diff --git a/arch/arm/mach-netx/include/mach/debug-macro.S b/arch/arm/mach-netx/include/mach/debug-macro.S
index e96339e71d88..56a915228180 100644
--- a/arch/arm/mach-netx/include/mach/debug-macro.S
+++ b/arch/arm/mach-netx/include/mach/debug-macro.S
@@ -13,12 +13,10 @@
13 13
14#include "hardware.h" 14#include "hardware.h"
15 15
16 .macro addruart, rx, tmp 16 .macro addruart, rp, rv
17 mrc p15, 0, \rx, c1, c0 17 mov \rp, #0x00000a00
18 tst \rx, #1 @ MMU enabled? 18 orr \rv, \rp, #io_p2v(0x00100000) @ virtual
19 moveq \rx, #0x00100000 @ physical 19 orr \rp, \rp, #0x00100000 @ physical
20 movne \rx, #io_p2v(0x00100000) @ virtual
21 orr \rx, \rx, #0x00000a00
22 .endm 20 .endm
23 21
24 .macro senduart,rd,rx 22 .macro senduart,rd,rx
diff --git a/arch/arm/mach-netx/include/mach/vmalloc.h b/arch/arm/mach-netx/include/mach/vmalloc.h
index 25d5cc676e0f..7cca3574308f 100644
--- a/arch/arm/mach-netx/include/mach/vmalloc.h
+++ b/arch/arm/mach-netx/include/mach/vmalloc.h
@@ -16,4 +16,4 @@
16 * along with this program; if not, write to the Free Software 16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */ 18 */
19#define VMALLOC_END (PAGE_OFFSET + 0x10000000) 19#define VMALLOC_END 0xd0000000
diff --git a/arch/arm/mach-netx/nxdb500.c b/arch/arm/mach-netx/nxdb500.c
index c9b174bc8ccf..ca8b203a3c99 100644
--- a/arch/arm/mach-netx/nxdb500.c
+++ b/arch/arm/mach-netx/nxdb500.c
@@ -200,8 +200,6 @@ static void __init nxdb500_init(void)
200} 200}
201 201
202MACHINE_START(NXDB500, "Hilscher nxdb500") 202MACHINE_START(NXDB500, "Hilscher nxdb500")
203 .phys_io = 0x00100000,
204 .io_pg_offst = (io_p2v(0x00100000) >> 18) & 0xfffc,
205 .boot_params = 0x80000100, 203 .boot_params = 0x80000100,
206 .map_io = netx_map_io, 204 .map_io = netx_map_io,
207 .init_irq = netx_init_irq, 205 .init_irq = netx_init_irq,
diff --git a/arch/arm/mach-netx/nxdkn.c b/arch/arm/mach-netx/nxdkn.c
index 15b54c62d60f..d775cbe07278 100644
--- a/arch/arm/mach-netx/nxdkn.c
+++ b/arch/arm/mach-netx/nxdkn.c
@@ -93,8 +93,6 @@ static void __init nxdkn_init(void)
93} 93}
94 94
95MACHINE_START(NXDKN, "Hilscher nxdkn") 95MACHINE_START(NXDKN, "Hilscher nxdkn")
96 .phys_io = 0x00100000,
97 .io_pg_offst = (io_p2v(0x00100000) >> 18) & 0xfffc,
98 .boot_params = 0x80000100, 96 .boot_params = 0x80000100,
99 .map_io = netx_map_io, 97 .map_io = netx_map_io,
100 .init_irq = netx_init_irq, 98 .init_irq = netx_init_irq,
diff --git a/arch/arm/mach-netx/nxeb500hmi.c b/arch/arm/mach-netx/nxeb500hmi.c
index 1061c01ff679..de369cd1dcbe 100644
--- a/arch/arm/mach-netx/nxeb500hmi.c
+++ b/arch/arm/mach-netx/nxeb500hmi.c
@@ -177,8 +177,6 @@ static void __init nxeb500hmi_init(void)
177} 177}
178 178
179MACHINE_START(NXEB500HMI, "Hilscher nxeb500hmi") 179MACHINE_START(NXEB500HMI, "Hilscher nxeb500hmi")
180 .phys_io = 0x00100000,
181 .io_pg_offst = (io_p2v(0x00100000) >> 18) & 0xfffc,
182 .boot_params = 0x80000100, 180 .boot_params = 0x80000100,
183 .map_io = netx_map_io, 181 .map_io = netx_map_io,
184 .init_irq = netx_init_irq, 182 .init_irq = netx_init_irq,
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index 841d459ad59d..139930350d93 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -276,8 +276,6 @@ static void __init nhk8815_platform_init(void)
276 276
277MACHINE_START(NOMADIK, "NHK8815") 277MACHINE_START(NOMADIK, "NHK8815")
278 /* Maintainer: ST MicroElectronics */ 278 /* Maintainer: ST MicroElectronics */
279 .phys_io = NOMADIK_UART0_BASE,
280 .io_pg_offst = (IO_ADDRESS(NOMADIK_UART0_BASE) >> 18) & 0xfffc,
281 .boot_params = 0x100, 279 .boot_params = 0x100,
282 .map_io = cpu8815_map_io, 280 .map_io = cpu8815_map_io,
283 .init_irq = cpu8815_init_irq, 281 .init_irq = cpu8815_init_irq,
diff --git a/arch/arm/mach-nomadik/include/mach/debug-macro.S b/arch/arm/mach-nomadik/include/mach/debug-macro.S
index 4f92acfba954..e7151b4b8889 100644
--- a/arch/arm/mach-nomadik/include/mach/debug-macro.S
+++ b/arch/arm/mach-nomadik/include/mach/debug-macro.S
@@ -10,13 +10,11 @@
10 * 10 *
11*/ 11*/
12 12
13 .macro addruart, rx, tmp 13 .macro addruart, rp, rv
14 mrc p15, 0, \rx, c1, c0 14 mov \rp, #0x00100000
15 tst \rx, #1 @ MMU enabled? 15 add \rp, \rp, #0x000fb000
16 moveq \rx, #0x10000000 @ physical base address 16 add \rv, \rp, #0xf0000000 @ virtual base
17 movne \rx, #0xf0000000 @ virtual base 17 add \rp, \rp, #0x10000000 @ physical base address
18 add \rx, \rx, #0x00100000
19 add \rx, \rx, #0x000fb000
20 .endm 18 .endm
21 19
22#include <asm/hardware/debug-pl01x.S> 20#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
index 5c934bdb7158..5a2acbdc3d67 100644
--- a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
@@ -12,11 +12,9 @@
12 12
13#include <mach/regs-board-a9m9750dev.h> 13#include <mach/regs-board-a9m9750dev.h>
14 14
15 .macro addruart, rx, tmp 15 .macro addruart, rp, rv
16 mrc p15, 0, \rx, c1, c0 16 ldr \rp, =NS9XXX_CSxSTAT_PHYS(0)
17 tst \rx, #1 17 ldr \rv, =io_p2v(NS9XXX_CSxSTAT_PHYS(0))
18 ldreq \rx, =NS9XXX_CSxSTAT_PHYS(0)
19 ldrne \rx, =io_p2v(NS9XXX_CSxSTAT_PHYS(0))
20 .endm 18 .endm
21 19
22#define UART_SHIFT 2 20#define UART_SHIFT 2
diff --git a/arch/arm/mach-nuc93x/mach-nuc932evb.c b/arch/arm/mach-nuc93x/mach-nuc932evb.c
index 9f79266f08e2..d70257042480 100644
--- a/arch/arm/mach-nuc93x/mach-nuc932evb.c
+++ b/arch/arm/mach-nuc93x/mach-nuc932evb.c
@@ -35,8 +35,6 @@ static void __init nuc932evb_init(void)
35 35
36MACHINE_START(NUC932EVB, "NUC932EVB") 36MACHINE_START(NUC932EVB, "NUC932EVB")
37 /* Maintainer: Wan ZongShun */ 37 /* Maintainer: Wan ZongShun */
38 .phys_io = NUC93X_PA_UART,
39 .io_pg_offst = (((u32)NUC93X_VA_UART) >> 18) & 0xfffc,
40 .boot_params = 0, 38 .boot_params = 0,
41 .map_io = nuc932evb_map_io, 39 .map_io = nuc932evb_map_io,
42 .init_irq = nuc93x_init_irq, 40 .init_irq = nuc93x_init_irq,
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 41992ab71961..73c86392fcd3 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -297,8 +297,6 @@ static void __init ams_delta_map_io(void)
297 297
298MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)") 298MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
299 /* Maintainer: Jonathan McDowell <noodles@earth.li> */ 299 /* Maintainer: Jonathan McDowell <noodles@earth.li> */
300 .phys_io = 0xfff00000,
301 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
302 .boot_params = 0x10000100, 300 .boot_params = 0x10000100,
303 .map_io = ams_delta_map_io, 301 .map_io = ams_delta_map_io,
304 .reserve = omap_reserve, 302 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 180ce79e5eac..149fdd32e127 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -386,8 +386,6 @@ static void __init omap_fsample_map_io(void)
386 386
387MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample") 387MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
388/* Maintainer: Brian Swetland <swetland@google.com> */ 388/* Maintainer: Brian Swetland <swetland@google.com> */
389 .phys_io = 0xfff00000,
390 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
391 .boot_params = 0x10000100, 389 .boot_params = 0x10000100,
392 .map_io = omap_fsample_map_io, 390 .map_io = omap_fsample_map_io,
393 .reserve = omap_reserve, 391 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index 93b9ab8fc3be..23f4ab9e2651 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -94,8 +94,6 @@ static void __init omap_generic_map_io(void)
94 94
95MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710") 95MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
96 /* Maintainer: Tony Lindgren <tony@atomide.com> */ 96 /* Maintainer: Tony Lindgren <tony@atomide.com> */
97 .phys_io = 0xfff00000,
98 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
99 .boot_params = 0x10000100, 97 .boot_params = 0x10000100,
100 .map_io = omap_generic_map_io, 98 .map_io = omap_generic_map_io,
101 .reserve = omap_reserve, 99 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index d2cda58bcc48..197adb49dc5a 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -458,8 +458,6 @@ static void __init h2_map_io(void)
458 458
459MACHINE_START(OMAP_H2, "TI-H2") 459MACHINE_START(OMAP_H2, "TI-H2")
460 /* Maintainer: Imre Deak <imre.deak@nokia.com> */ 460 /* Maintainer: Imre Deak <imre.deak@nokia.com> */
461 .phys_io = 0xfff00000,
462 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
463 .boot_params = 0x10000100, 461 .boot_params = 0x10000100,
464 .map_io = h2_map_io, 462 .map_io = h2_map_io,
465 .reserve = omap_reserve, 463 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index c2ef4ff846c7..9126e3e37b4a 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -446,8 +446,6 @@ static void __init h3_map_io(void)
446 446
447MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board") 447MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
448 /* Maintainer: Texas Instruments, Inc. */ 448 /* Maintainer: Texas Instruments, Inc. */
449 .phys_io = 0xfff00000,
450 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
451 .boot_params = 0x10000100, 449 .boot_params = 0x10000100,
452 .map_io = h3_map_io, 450 .map_io = h3_map_io,
453 .reserve = omap_reserve, 451 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 311899ff5ffc..86afb2952225 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -300,8 +300,6 @@ static void __init htcherald_init_irq(void)
300MACHINE_START(HERALD, "HTC Herald") 300MACHINE_START(HERALD, "HTC Herald")
301 /* Maintainer: Cory Maccarrone <darkstar6262@gmail.com> */ 301 /* Maintainer: Cory Maccarrone <darkstar6262@gmail.com> */
302 /* Maintainer: wing-linux.sourceforge.net */ 302 /* Maintainer: wing-linux.sourceforge.net */
303 .phys_io = 0xfff00000,
304 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
305 .boot_params = 0x10000100, 303 .boot_params = 0x10000100,
306 .map_io = htcherald_map_io, 304 .map_io = htcherald_map_io,
307 .reserve = omap_reserve, 305 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 3daf87ad2576..dc2b86fd66c1 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -459,8 +459,6 @@ static void __init innovator_map_io(void)
459 459
460MACHINE_START(OMAP_INNOVATOR, "TI-Innovator") 460MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
461 /* Maintainer: MontaVista Software, Inc. */ 461 /* Maintainer: MontaVista Software, Inc. */
462 .phys_io = 0xfff00000,
463 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
464 .boot_params = 0x10000100, 462 .boot_params = 0x10000100,
465 .map_io = innovator_map_io, 463 .map_io = innovator_map_io,
466 .reserve = omap_reserve, 464 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 51a4539aecf5..aa8375b2a0a3 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -262,8 +262,6 @@ static void __init omap_nokia770_map_io(void)
262} 262}
263 263
264MACHINE_START(NOKIA770, "Nokia 770") 264MACHINE_START(NOKIA770, "Nokia 770")
265 .phys_io = 0xfff00000,
266 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
267 .boot_params = 0x10000100, 265 .boot_params = 0x10000100,
268 .map_io = omap_nokia770_map_io, 266 .map_io = omap_nokia770_map_io,
269 .reserve = omap_reserve, 267 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 679740cc1e90..e9dd79149a8e 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -580,8 +580,6 @@ static void __init osk_map_io(void)
580 580
581MACHINE_START(OMAP_OSK, "TI-OSK") 581MACHINE_START(OMAP_OSK, "TI-OSK")
582 /* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */ 582 /* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */
583 .phys_io = 0xfff00000,
584 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
585 .boot_params = 0x10000100, 583 .boot_params = 0x10000100,
586 .map_io = osk_map_io, 584 .map_io = osk_map_io,
587 .reserve = omap_reserve, 585 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 782bb257a85d..f32738b1eb6b 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -285,8 +285,6 @@ static void __init omap_palmte_map_io(void)
285} 285}
286 286
287MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E") 287MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
288 .phys_io = 0xfff00000,
289 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
290 .boot_params = 0x10000100, 288 .boot_params = 0x10000100,
291 .map_io = omap_palmte_map_io, 289 .map_io = omap_palmte_map_io,
292 .reserve = omap_reserve, 290 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 0b35ef54a64f..ed1400a67f75 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -317,8 +317,6 @@ static void __init omap_palmtt_map_io(void)
317} 317}
318 318
319MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T") 319MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
320 .phys_io = 0xfff00000,
321 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
322 .boot_params = 0x10000100, 320 .boot_params = 0x10000100,
323 .map_io = omap_palmtt_map_io, 321 .map_io = omap_palmtt_map_io,
324 .reserve = omap_reserve, 322 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 66362903b6e2..d7a245cef9a4 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -338,8 +338,6 @@ omap_palmz71_map_io(void)
338} 338}
339 339
340MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71") 340MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
341 .phys_io = 0xfff00000,
342 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
343 .boot_params = 0x10000100, 341 .boot_params = 0x10000100,
344 .map_io = omap_palmz71_map_io, 342 .map_io = omap_palmz71_map_io,
345 .reserve = omap_reserve, 343 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 34ab354758b0..a8d16a255c18 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -347,8 +347,6 @@ static void __init omap_perseus2_map_io(void)
347 347
348MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2") 348MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
349 /* Maintainer: Kevin Hilman <kjh@hilman.org> */ 349 /* Maintainer: Kevin Hilman <kjh@hilman.org> */
350 .phys_io = 0xfff00000,
351 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
352 .boot_params = 0x10000100, 350 .boot_params = 0x10000100,
353 .map_io = omap_perseus2_map_io, 351 .map_io = omap_perseus2_map_io,
354 .reserve = omap_reserve, 352 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 2eb148b8de93..d25f59e5a773 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -419,8 +419,6 @@ static void __init omap_sx1_map_io(void)
419} 419}
420 420
421MACHINE_START(SX1, "OMAP310 based Siemens SX1") 421MACHINE_START(SX1, "OMAP310 based Siemens SX1")
422 .phys_io = 0xfff00000,
423 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
424 .boot_params = 0x10000100, 422 .boot_params = 0x10000100,
425 .map_io = omap_sx1_map_io, 423 .map_io = omap_sx1_map_io,
426 .reserve = omap_reserve, 424 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 6b3cf14bc757..f5992c239bcd 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -283,8 +283,6 @@ EXPORT_SYMBOL(voiceblue_wdt_ping);
283 283
284MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910") 284MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
285 /* Maintainer: Ladislav Michl <michl@2n.cz> */ 285 /* Maintainer: Ladislav Michl <michl@2n.cz> */
286 .phys_io = 0xfff00000,
287 .io_pg_offst = ((0xfef00000) >> 18) & 0xfffc,
288 .boot_params = 0x10000100, 286 .boot_params = 0x10000100,
289 .map_io = voiceblue_map_io, 287 .map_io = voiceblue_map_io,
290 .reserve = omap_reserve, 288 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S
index 671408eb4ab4..6a0fa0462365 100644
--- a/arch/arm/mach-omap1/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap1/include/mach/debug-macro.S
@@ -28,56 +28,58 @@ omap_uart_virt: .word 0x0
28 * the desired UART phys and virt addresses temporarily into 28 * the desired UART phys and virt addresses temporarily into
29 * the omap_uart_phys and omap_uart_virt above. 29 * the omap_uart_phys and omap_uart_virt above.
30 */ 30 */
31 .macro addruart, rx, tmp 31 .macro addruart, rp, rv
32 32
33 /* Use omap_uart_phys/virt if already configured */ 33 /* Use omap_uart_phys/virt if already configured */
349: mrc p15, 0, \rx, c1, c0 349: mrc p15, 0, \rp, c1, c0
35 tst \rx, #1 @ MMU enabled? 35 tst \rp, #1 @ MMU enabled?
36 ldreq \rx, =__virt_to_phys(omap_uart_phys) @ physical base address 36 ldreq \rp, =__virt_to_phys(omap_uart_phys) @ MMU not enabled
37 ldrne \rx, =omap_uart_virt @ virtual base 37 ldrne \rp, =omap_uart_phys @ MMU enabled
38 ldr \rx, [\rx, #0] 38 add \rv, \rp, #4 @ omap_uart_virt
39 cmp \rx, #0 @ is port configured? 39 ldr \rp, [\rp, #0]
40 ldr \rv, [\rv, #0]
41 cmp \rp, #0 @ is port configured?
42 cmpne \rv, #0
40 bne 99f @ already configured 43 bne 99f @ already configured
41 44
42 /* Check the debug UART configuration set in uncompress.h */ 45 /* Check the debug UART configuration set in uncompress.h */
43 mrc p15, 0, \rx, c1, c0 46 mrc p15, 0, \rp, c1, c0
44 tst \rx, #1 @ MMU enabled? 47 tst \rp, #1 @ MMU enabled?
45 ldreq \rx, =OMAP_UART_INFO 48 ldreq \rp, =OMAP_UART_INFO @ MMU not enabled
46 ldrne \rx, =__phys_to_virt(OMAP_UART_INFO) 49 ldrne \rp, =__phys_to_virt(OMAP_UART_INFO) @ MMU enabled
47 ldr \rx, [\rx, #0] 50 ldr \rp, [\rp, #0]
48 51
49 /* Select the UART to use based on the UART1 scratchpad value */ 52 /* Select the UART to use based on the UART1 scratchpad value */
5010: cmp \rx, #0 @ no port configured? 5310: cmp \rp, #0 @ no port configured?
51 beq 11f @ if none, try to use UART1 54 beq 11f @ if none, try to use UART1
52 cmp \rx, #OMAP1UART1 55 cmp \rp, #OMAP1UART1
53 beq 11f @ configure OMAP1UART1 56 beq 11f @ configure OMAP1UART1
54 cmp \rx, #OMAP1UART2 57 cmp \rp, #OMAP1UART2
55 beq 12f @ configure OMAP1UART2 58 beq 12f @ configure OMAP1UART2
56 cmp \rx, #OMAP1UART3 59 cmp \rp, #OMAP1UART3
57 beq 13f @ configure OMAP2UART3 60 beq 13f @ configure OMAP2UART3
58 61
59 /* Configure the UART offset from the phys/virt base */ 62 /* Configure the UART offset from the phys/virt base */
6011: mov \rx, #0x00fb0000 @ OMAP1UART1 6311: mov \rp, #0x00fb0000 @ OMAP1UART1
61 b 98f 64 b 98f
6212: mov \rx, #0x00fb0000 @ OMAP1UART1 6512: mov \rp, #0x00fb0000 @ OMAP1UART1
63 orr \rx, \rx, #0x00000800 @ OMAP1UART2 66 orr \rp, \rp, #0x00000800 @ OMAP1UART2
64 b 98f 67 b 98f
6513: mov \rx, #0x00fb0000 @ OMAP1UART1 6813: mov \rp, #0x00fb0000 @ OMAP1UART1
66 orr \rx, \rx, #0x00000800 @ OMAP1UART2 69 orr \rp, \rp, #0x00000800 @ OMAP1UART2
67 orr \rx, \rx, #0x00009000 @ OMAP1UART3 70 orr \rp, \rp, #0x00009000 @ OMAP1UART3
68 71
69 /* Store both phys and virt address for the uart */ 72 /* Store both phys and virt address for the uart */
7098: add \rx, \rx, #0xff000000 @ phys base 7398: add \rp, \rp, #0xff000000 @ phys base
71 mrc p15, 0, \tmp, c1, c0 74 mrc p15, 0, \rv, c1, c0
72 tst \tmp, #1 @ MMU enabled? 75 tst \rv, #1 @ MMU enabled?
73 ldreq \tmp, =__virt_to_phys(omap_uart_phys) 76 ldreq \rv, =__virt_to_phys(omap_uart_phys) @ MMU not enabled
74 ldrne \tmp, =omap_uart_phys 77 ldrne \rv, =omap_uart_phys @ MMU enabled
75 str \rx, [\tmp, #0] 78 str \rp, [\rv, #0]
76 sub \rx, \rx, #0xff000000 @ phys base 79 sub \rp, \rp, #0xff000000 @ phys base
77 add \rx, \rx, #0xfe000000 @ virt base 80 add \rp, \rp, #0xfe000000 @ virt base
78 ldreq \tmp, =__virt_to_phys(omap_uart_virt) 81 add \rv, \rv, #4 @ omap_uart_lsr
79 ldrne \tmp, =omap_uart_virt 82 str \rp, [\rv, #0]
80 str \rx, [\tmp, #0]
81 b 9b 83 b 9b
8299: 8499:
83 .endm 85 .endm
diff --git a/arch/arm/mach-omap1/include/mach/vmalloc.h b/arch/arm/mach-omap1/include/mach/vmalloc.h
index 1b2af14df151..b001f67d695b 100644
--- a/arch/arm/mach-omap1/include/mach/vmalloc.h
+++ b/arch/arm/mach-omap1/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20#define VMALLOC_END (PAGE_OFFSET + 0x18000000) 20#define VMALLOC_END 0xd8000000
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 8538e4131d27..b857ce484510 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -253,8 +253,6 @@ static void __init omap_2430sdp_map_io(void)
253 253
254MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") 254MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
255 /* Maintainer: Syed Khasim - Texas Instruments Inc */ 255 /* Maintainer: Syed Khasim - Texas Instruments Inc */
256 .phys_io = 0x48000000,
257 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
258 .boot_params = 0x80000100, 256 .boot_params = 0x80000100,
259 .map_io = omap_2430sdp_map_io, 257 .map_io = omap_2430sdp_map_io,
260 .reserve = omap_reserve, 258 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 67b95b5f1a2f..a5b095cf2adc 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -817,8 +817,6 @@ static void __init omap_3430sdp_init(void)
817 817
818MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") 818MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
819 /* Maintainer: Syed Khasim - Texas Instruments Inc */ 819 /* Maintainer: Syed Khasim - Texas Instruments Inc */
820 .phys_io = 0x48000000,
821 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
822 .boot_params = 0x80000100, 820 .boot_params = 0x80000100,
823 .map_io = omap3_map_io, 821 .map_io = omap3_map_io,
824 .reserve = omap_reserve, 822 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index b359c3f7bb39..fd27ac0860b0 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -217,8 +217,6 @@ static void __init omap_sdp_init(void)
217} 217}
218 218
219MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board") 219MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
220 .phys_io = 0x48000000,
221 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
222 .boot_params = 0x80000100, 220 .boot_params = 0x80000100,
223 .map_io = omap3_map_io, 221 .map_io = omap3_map_io,
224 .reserve = omap_reserve, 222 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 9447644774c2..0b6a65f3a10a 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -458,8 +458,6 @@ static void __init omap_4430sdp_map_io(void)
458 458
459MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") 459MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
460 /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */ 460 /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
461 .phys_io = 0x48000000,
462 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
463 .boot_params = 0x80000100, 461 .boot_params = 0x80000100,
464 .map_io = omap_4430sdp_map_io, 462 .map_io = omap_4430sdp_map_io,
465 .reserve = omap_reserve, 463 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 4d0f58592864..f85c8da17e8b 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -462,8 +462,6 @@ static void __init am3517_evm_init(void)
462} 462}
463 463
464MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") 464MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
465 .phys_io = 0x48000000,
466 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
467 .boot_params = 0x80000100, 465 .boot_params = 0x80000100,
468 .map_io = omap3_map_io, 466 .map_io = omap3_map_io,
469 .reserve = omap_reserve, 467 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index c6421a72514a..68f07f5f441a 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -356,8 +356,6 @@ static void __init omap_apollon_map_io(void)
356 356
357MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon") 357MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
358 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */ 358 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
359 .phys_io = 0x48000000,
360 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
361 .boot_params = 0x80000100, 359 .boot_params = 0x80000100,
362 .map_io = omap_apollon_map_io, 360 .map_io = omap_apollon_map_io,
363 .reserve = omap_reserve, 361 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index e10bc109415c..934d9380c372 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -809,8 +809,6 @@ static void __init cm_t35_init(void)
809} 809}
810 810
811MACHINE_START(CM_T35, "Compulab CM-T35") 811MACHINE_START(CM_T35, "Compulab CM-T35")
812 .phys_io = 0x48000000,
813 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
814 .boot_params = 0x80000100, 812 .boot_params = 0x80000100,
815 .map_io = omap3_map_io, 813 .map_io = omap3_map_io,
816 .reserve = omap_reserve, 814 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index a07086d6a0b2..2205c20a4cdb 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -800,8 +800,6 @@ static void __init devkit8000_init(void)
800} 800}
801 801
802MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000") 802MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
803 .phys_io = 0x48000000,
804 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
805 .boot_params = 0x80000100, 803 .boot_params = 0x80000100,
806 .map_io = omap3_map_io, 804 .map_io = omap3_map_io,
807 .reserve = omap_reserve, 805 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 3482b99e8c86..69064b1c6a75 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -54,8 +54,6 @@ static void __init omap_generic_map_io(void)
54 54
55MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx") 55MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
56 /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */ 56 /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
57 .phys_io = 0x48000000,
58 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
59 .boot_params = 0x80000100, 57 .boot_params = 0x80000100,
60 .map_io = omap_generic_map_io, 58 .map_io = omap_generic_map_io,
61 .reserve = omap_reserve, 59 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index e09bd686389f..cc39fc866524 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -376,8 +376,6 @@ static void __init omap_h4_map_io(void)
376 376
377MACHINE_START(OMAP_H4, "OMAP2420 H4 board") 377MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
378 /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */ 378 /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
379 .phys_io = 0x48000000,
380 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
381 .boot_params = 0x80000100, 379 .boot_params = 0x80000100,
382 .map_io = omap_h4_map_io, 380 .map_io = omap_h4_map_io,
383 .reserve = omap_reserve, 381 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 175f04339761..b62a68ba069b 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -533,8 +533,6 @@ static void __init igep2_init(void)
533} 533}
534 534
535MACHINE_START(IGEP0020, "IGEP v2 board") 535MACHINE_START(IGEP0020, "IGEP v2 board")
536 .phys_io = 0x48000000,
537 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
538 .boot_params = 0x80000100, 536 .boot_params = 0x80000100,
539 .map_io = omap3_map_io, 537 .map_io = omap3_map_io,
540 .reserve = omap_reserve, 538 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 00d9b13b01c5..f28fd77bceb3 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -442,8 +442,6 @@ static void __init omap_ldp_init(void)
442} 442}
443 443
444MACHINE_START(OMAP_LDP, "OMAP LDP board") 444MACHINE_START(OMAP_LDP, "OMAP LDP board")
445 .phys_io = 0x48000000,
446 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
447 .boot_params = 0x80000100, 445 .boot_params = 0x80000100,
448 .map_io = omap3_map_io, 446 .map_io = omap3_map_io,
449 .reserve = omap_reserve, 447 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index a3e2b49aa39f..3f7966873507 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -674,8 +674,6 @@ static void __init n8x0_init_machine(void)
674} 674}
675 675
676MACHINE_START(NOKIA_N800, "Nokia N800") 676MACHINE_START(NOKIA_N800, "Nokia N800")
677 .phys_io = 0x48000000,
678 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
679 .boot_params = 0x80000100, 677 .boot_params = 0x80000100,
680 .map_io = n8x0_map_io, 678 .map_io = n8x0_map_io,
681 .reserve = omap_reserve, 679 .reserve = omap_reserve,
@@ -685,8 +683,6 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
685MACHINE_END 683MACHINE_END
686 684
687MACHINE_START(NOKIA_N810, "Nokia N810") 685MACHINE_START(NOKIA_N810, "Nokia N810")
688 .phys_io = 0x48000000,
689 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
690 .boot_params = 0x80000100, 686 .boot_params = 0x80000100,
691 .map_io = n8x0_map_io, 687 .map_io = n8x0_map_io,
692 .reserve = omap_reserve, 688 .reserve = omap_reserve,
@@ -696,8 +692,6 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
696MACHINE_END 692MACHINE_END
697 693
698MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") 694MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
699 .phys_io = 0x48000000,
700 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
701 .boot_params = 0x80000100, 695 .boot_params = 0x80000100,
702 .map_io = n8x0_map_io, 696 .map_io = n8x0_map_io,
703 .reserve = omap_reserve, 697 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 87969c7df652..9d9f5b881ee8 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -487,8 +487,6 @@ static void __init omap3_beagle_init(void)
487 487
488MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") 488MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
489 /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */ 489 /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
490 .phys_io = 0x48000000,
491 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
492 .boot_params = 0x80000100, 490 .boot_params = 0x80000100,
493 .map_io = omap3_map_io, 491 .map_io = omap3_map_io,
494 .reserve = omap_reserve, 492 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index f76d9c0a47a1..8936e4fba334 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -714,8 +714,6 @@ static void __init omap3_evm_init(void)
714 714
715MACHINE_START(OMAP3EVM, "OMAP3 EVM") 715MACHINE_START(OMAP3EVM, "OMAP3 EVM")
716 /* Maintainer: Syed Mohammed Khasim - Texas Instruments */ 716 /* Maintainer: Syed Mohammed Khasim - Texas Instruments */
717 .phys_io = 0x48000000,
718 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
719 .boot_params = 0x80000100, 717 .boot_params = 0x80000100,
720 .map_io = omap3_map_io, 718 .map_io = omap3_map_io,
721 .reserve = omap_reserve, 719 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index dd3af2be13be..b7d6df4e3cf9 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -717,8 +717,6 @@ static void __init omap3pandora_init(void)
717} 717}
718 718
719MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") 719MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
720 .phys_io = 0x48000000,
721 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
722 .boot_params = 0x80000100, 720 .boot_params = 0x80000100,
723 .map_io = omap3_map_io, 721 .map_io = omap3_map_io,
724 .reserve = omap_reserve, 722 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index bcd01d278c65..bc5ac83bd4cf 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -654,8 +654,6 @@ static void __init omap3_stalker_init(void)
654 654
655MACHINE_START(SBC3530, "OMAP3 STALKER") 655MACHINE_START(SBC3530, "OMAP3 STALKER")
656 /* Maintainer: Jason Lam -lzg@ema-tech.com */ 656 /* Maintainer: Jason Lam -lzg@ema-tech.com */
657 .phys_io = 0x48000000,
658 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
659 .boot_params = 0x80000100, 657 .boot_params = 0x80000100,
660 .map_io = omap3_map_io, 658 .map_io = omap3_map_io,
661 .init_irq = omap3_stalker_init_irq, 659 .init_irq = omap3_stalker_init_irq,
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 663c62d271e8..0e99ce584dbf 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -538,8 +538,6 @@ static void __init omap3_touchbook_init(void)
538 538
539MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") 539MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
540 /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */ 540 /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */
541 .phys_io = 0x48000000,
542 .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc,
543 .boot_params = 0x80000100, 541 .boot_params = 0x80000100,
544 .map_io = omap3_map_io, 542 .map_io = omap3_map_io,
545 .reserve = omap_reserve, 543 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index c03d1d56db56..db69bcadf4c7 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -294,8 +294,6 @@ static void __init omap4_panda_map_io(void)
294 294
295MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board") 295MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
296 /* Maintainer: David Anders - Texas Instruments Inc */ 296 /* Maintainer: David Anders - Texas Instruments Inc */
297 .phys_io = 0x48000000,
298 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
299 .boot_params = 0x80000100, 297 .boot_params = 0x80000100,
300 .map_io = omap4_panda_map_io, 298 .map_io = omap4_panda_map_io,
301 .init_irq = omap4_panda_init_irq, 299 .init_irq = omap4_panda_init_irq,
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 4c4843618350..5e528ca015a1 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -501,8 +501,6 @@ static void __init overo_init(void)
501} 501}
502 502
503MACHINE_START(OVERO, "Gumstix Overo") 503MACHINE_START(OVERO, "Gumstix Overo")
504 .phys_io = 0x48000000,
505 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
506 .boot_params = 0x80000100, 504 .boot_params = 0x80000100,
507 .map_io = omap3_map_io, 505 .map_io = omap3_map_io,
508 .reserve = omap_reserve, 506 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index a58e8cb1a7fc..36f2cf4efd57 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -150,8 +150,6 @@ static void __init rx51_map_io(void)
150 150
151MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") 151MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
152 /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */ 152 /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */
153 .phys_io = 0x48000000,
154 .io_pg_offst = ((0xfa000000) >> 18) & 0xfffc,
155 .boot_params = 0x80000100, 153 .boot_params = 0x80000100,
156 .map_io = rx51_map_io, 154 .map_io = rx51_map_io,
157 .reserve = omap_reserve, 155 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c
index 3ad9ecf7f5e2..24bbd0def64f 100644
--- a/arch/arm/mach-omap2/board-zoom2.c
+++ b/arch/arm/mach-omap2/board-zoom2.c
@@ -141,8 +141,6 @@ static void __init omap_zoom2_init(void)
141} 141}
142 142
143MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") 143MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
144 .phys_io = ZOOM_UART_BASE,
145 .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc,
146 .boot_params = 0x80000100, 144 .boot_params = 0x80000100,
147 .map_io = omap3_map_io, 145 .map_io = omap3_map_io,
148 .reserve = omap_reserve, 146 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c
index 6ca0b8341615..b2bb3ff971ac 100644
--- a/arch/arm/mach-omap2/board-zoom3.c
+++ b/arch/arm/mach-omap2/board-zoom3.c
@@ -123,8 +123,6 @@ static void __init omap_zoom_init(void)
123} 123}
124 124
125MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") 125MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
126 .phys_io = ZOOM_UART_BASE,
127 .io_pg_offst = (ZOOM_UART_VIRT >> 18) & 0xfffc,
128 .boot_params = 0x80000100, 126 .boot_params = 0x80000100,
129 .map_io = omap3_map_io, 127 .map_io = omap3_map_io,
130 .reserve = omap_reserve, 128 .reserve = omap_reserve,
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 09331bbbda52..6a4d4136002e 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -31,95 +31,94 @@ omap_uart_lsr: .word 0
31 * the desired UART phys and virt addresses temporarily into 31 * the desired UART phys and virt addresses temporarily into
32 * the omap_uart_phys and omap_uart_virt above. 32 * the omap_uart_phys and omap_uart_virt above.
33 */ 33 */
34 .macro addruart, rx, tmp 34 .macro addruart, rp, rv
35 35
36 /* Use omap_uart_phys/virt if already configured */ 36 /* Use omap_uart_phys/virt if already configured */
3710: mrc p15, 0, \rx, c1, c0 3710: mrc p15, 0, \rp, c1, c0
38 tst \rx, #1 @ MMU enabled? 38 tst \rp, #1 @ MMU enabled?
39 ldreq \rx, =__virt_to_phys(omap_uart_phys) @ physical base address 39 ldreq \rp, =__virt_to_phys(omap_uart_phys) @ MMU not enabled
40 ldrne \rx, =omap_uart_virt @ virtual base address 40 ldrne \rp, =omap_uart_phys @ MMU enabled
41 ldr \rx, [\rx, #0] 41 add \rv, \rp, #4 @ omap_uart_virt
42 cmp \rx, #0 @ is port configured? 42 ldr \rp, [\rp, #0]
43 ldr \rv, [\rv, #0]
44 cmp \rp, #0 @ is port configured?
45 cmpne \rv, #0
43 bne 99f @ already configured 46 bne 99f @ already configured
44 47
45 /* Check the debug UART configuration set in uncompress.h */ 48 /* Check the debug UART configuration set in uncompress.h */
46 mrc p15, 0, \rx, c1, c0 49 mrc p15, 0, \rp, c1, c0
47 tst \rx, #1 @ MMU enabled? 50 tst \rp, #1 @ MMU enabled?
48 ldreq \rx, =OMAP_UART_INFO 51 ldreq \rp, =OMAP_UART_INFO @ MMU not enabled
49 ldrne \rx, =__phys_to_virt(OMAP_UART_INFO) 52 ldrne \rp, =__phys_to_virt(OMAP_UART_INFO) @ MMU enabled
50 ldr \rx, [\rx, #0] 53 ldr \rp, [\rp, #0]
51 54
52 /* Select the UART to use based on the UART1 scratchpad value */ 55 /* Select the UART to use based on the UART1 scratchpad value */
53 cmp \rx, #0 @ no port configured? 56 cmp \rp, #0 @ no port configured?
54 beq 21f @ if none, try to use UART1 57 beq 21f @ if none, try to use UART1
55 cmp \rx, #OMAP2UART1 @ OMAP2/3/4UART1 58 cmp \rp, #OMAP2UART1 @ OMAP2/3/4UART1
56 beq 21f @ configure OMAP2/3/4UART1 59 beq 21f @ configure OMAP2/3/4UART1
57 cmp \rx, #OMAP2UART2 @ OMAP2/3/4UART2 60 cmp \rp, #OMAP2UART2 @ OMAP2/3/4UART2
58 beq 22f @ configure OMAP2/3/4UART2 61 beq 22f @ configure OMAP2/3/4UART2
59 cmp \rx, #OMAP2UART3 @ only on 24xx 62 cmp \rp, #OMAP2UART3 @ only on 24xx
60 beq 23f @ configure OMAP2UART3 63 beq 23f @ configure OMAP2UART3
61 cmp \rx, #OMAP3UART3 @ only on 34xx 64 cmp \rp, #OMAP3UART3 @ only on 34xx
62 beq 33f @ configure OMAP3UART3 65 beq 33f @ configure OMAP3UART3
63 cmp \rx, #OMAP4UART3 @ only on 44xx 66 cmp \rp, #OMAP4UART3 @ only on 44xx
64 beq 43f @ configure OMAP4UART3 67 beq 43f @ configure OMAP4UART3
65 cmp \rx, #OMAP3UART4 @ only on 36xx 68 cmp \rp, #OMAP3UART4 @ only on 36xx
66 beq 34f @ configure OMAP3UART4 69 beq 34f @ configure OMAP3UART4
67 cmp \rx, #OMAP4UART4 @ only on 44xx 70 cmp \rp, #OMAP4UART4 @ only on 44xx
68 beq 44f @ configure OMAP4UART4 71 beq 44f @ configure OMAP4UART4
69 cmp \rx, #ZOOM_UART @ only on zoom2/3 72 cmp \rp, #ZOOM_UART @ only on zoom2/3
70 beq 95f @ configure ZOOM_UART 73 beq 95f @ configure ZOOM_UART
71 74
72 /* Configure the UART offset from the phys/virt base */ 75 /* Configure the UART offset from the phys/virt base */
7321: mov \rx, #UART_OFFSET(OMAP2_UART1_BASE) @ omap2/3/4 7621: mov \rp, #UART_OFFSET(OMAP2_UART1_BASE) @ omap2/3/4
74 b 98f 77 b 98f
7522: mov \rx, #UART_OFFSET(OMAP2_UART2_BASE) @ omap2/3/4 7822: mov \rp, #UART_OFFSET(OMAP2_UART2_BASE) @ omap2/3/4
76 b 98f 79 b 98f
7723: mov \rx, #UART_OFFSET(OMAP2_UART3_BASE) 8023: mov \rp, #UART_OFFSET(OMAP2_UART3_BASE)
78 b 98f 81 b 98f
7933: mov \rx, #UART_OFFSET(OMAP3_UART1_BASE) 8233: mov \rp, #UART_OFFSET(OMAP3_UART1_BASE)
80 add \rx, \rx, #0x00fb0000 83 add \rp, \rp, #0x00fb0000
81 add \rx, \rx, #0x00006000 @ OMAP3_UART3_BASE 84 add \rp, \rp, #0x00006000 @ OMAP3_UART3_BASE
82 b 98f 85 b 98f
8334: mov \rx, #UART_OFFSET(OMAP3_UART1_BASE) 8634: mov \rp, #UART_OFFSET(OMAP3_UART1_BASE)
84 add \rx, \rx, #0x00fb0000 87 add \rp, \rp, #0x00fb0000
85 add \rx, \rx, #0x00028000 @ OMAP3_UART4_BASE 88 add \rp, \rp, #0x00028000 @ OMAP3_UART4_BASE
86 b 98f 89 b 98f
8743: mov \rx, #UART_OFFSET(OMAP4_UART3_BASE) 9043: mov \rp, #UART_OFFSET(OMAP4_UART3_BASE)
88 b 98f 91 b 98f
8944: mov \rx, #UART_OFFSET(OMAP4_UART4_BASE) 9244: mov \rp, #UART_OFFSET(OMAP4_UART4_BASE)
90 b 98f 93 b 98f
9195: ldr \rx, =ZOOM_UART_BASE 9495: ldr \rp, =ZOOM_UART_BASE
92 mrc p15, 0, \tmp, c1, c0 95 mrc p15, 0, \rv, c1, c0
93 tst \tmp, #1 @ MMU enabled? 96 tst \rv, #1 @ MMU enabled?
94 ldreq \tmp, =__virt_to_phys(omap_uart_phys) 97 ldreq \rv, =__virt_to_phys(omap_uart_phys) @ MMU not enabled
95 ldrne \tmp, =omap_uart_phys 98 ldrne \rv, =omap_uart_phys @ MMU enabled
96 str \rx, [\tmp, #0] 99 str \rp, [\rv, #0]
97 ldr \rx, =ZOOM_UART_VIRT 100 ldr \rp, =ZOOM_UART_VIRT
98 ldreq \tmp, =__virt_to_phys(omap_uart_virt) 101 add \rv, \rv, #4 @ omap_uart_virt
99 ldrne \tmp, =omap_uart_virt 102 str \rp, [\rv, #0]
100 str \rx, [\tmp, #0] 103 mov \rp, #(UART_LSR << ZOOM_PORT_SHIFT)
101 mov \rx, #(UART_LSR << ZOOM_PORT_SHIFT) 104 add \rv, \rv, #4 @ omap_uart_lsr
102 ldreq \tmp, =__virt_to_phys(omap_uart_lsr) 105 str \rp, [\rv, #0]
103 ldrne \tmp, =omap_uart_lsr
104 str \rx, [\tmp, #0]
105 b 10b 106 b 10b
106 107
107 /* Store both phys and virt address for the uart */ 108 /* Store both phys and virt address for the uart */
10898: add \rx, \rx, #0x48000000 @ phys base 10998: add \rp, \rp, #0x48000000 @ phys base
109 mrc p15, 0, \tmp, c1, c0 110 mrc p15, 0, \rv, c1, c0
110 tst \tmp, #1 @ MMU enabled? 111 tst \rv, #1 @ MMU enabled?
111 ldreq \tmp, =__virt_to_phys(omap_uart_phys) 112 ldreq \rv, =__virt_to_phys(omap_uart_phys) @ MMU not enabled
112 ldrne \tmp, =omap_uart_phys 113 ldrne \rv, =omap_uart_phys @ MMU enabled
113 str \rx, [\tmp, #0] 114 str \rp, [\rv, #0]
114 sub \rx, \rx, #0x48000000 @ phys base 115 sub \rp, \rp, #0x48000000 @ phys base
115 add \rx, \rx, #0xfa000000 @ virt base 116 add \rp, \rp, #0xfa000000 @ virt base
116 ldreq \tmp, =__virt_to_phys(omap_uart_virt) 117 add \rv, \rv, #4 @ omap_uart_virt
117 ldrne \tmp, =omap_uart_virt 118 str \rp, [\rv, #0]
118 str \rx, [\tmp, #0] 119 mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
119 mov \rx, #(UART_LSR << OMAP_PORT_SHIFT) 120 add \rv, \rv, #4 @ omap_uart_lsr
120 ldreq \tmp, =__virt_to_phys(omap_uart_lsr) 121 str \rp, [\rv, #0]
121 ldrne \tmp, =omap_uart_lsr
122 str \rx, [\tmp, #0]
123 122
124 b 10b 123 b 10b
12599: 12499:
@@ -131,9 +130,9 @@ omap_uart_lsr: .word 0
131 130
132 .macro busyuart,rd,rx 131 .macro busyuart,rd,rx
1331001: mrc p15, 0, \rd, c1, c0 1321001: mrc p15, 0, \rd, c1, c0
134 tst \rd, #1 @ MMU enabled? 133 tst \rd, #1 @ MMU enabled?
135 ldreq \rd, =__virt_to_phys(omap_uart_lsr) 134 ldreq \rd, =__virt_to_phys(omap_uart_lsr) @ MMU not enabled
136 ldrne \rd, =omap_uart_lsr 135 ldrne \rd, =omap_uart_lsr @ MMU enabled
137 ldr \rd, [\rd, #0] 136 ldr \rd, [\rd, #0]
138 ldrb \rd, [\rx, \rd] 137 ldrb \rd, [\rx, \rd]
139 and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE) 138 and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
diff --git a/arch/arm/mach-omap2/include/mach/vmalloc.h b/arch/arm/mach-omap2/include/mach/vmalloc.h
index 9ce9b6e8ad23..4da31e997efe 100644
--- a/arch/arm/mach-omap2/include/mach/vmalloc.h
+++ b/arch/arm/mach-omap2/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20#define VMALLOC_END (PAGE_OFFSET + 0x38000000) 20#define VMALLOC_END 0xf8000000
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index 7130904ad999..b1c451f5ee27 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -336,8 +336,6 @@ static void __init d2net_init(void)
336 336
337#ifdef CONFIG_MACH_D2NET 337#ifdef CONFIG_MACH_D2NET
338MACHINE_START(D2NET, "LaCie d2 Network") 338MACHINE_START(D2NET, "LaCie d2 Network")
339 .phys_io = ORION5X_REGS_PHYS_BASE,
340 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
341 .boot_params = 0x00000100, 339 .boot_params = 0x00000100,
342 .init_machine = d2net_init, 340 .init_machine = d2net_init,
343 .map_io = orion5x_map_io, 341 .map_io = orion5x_map_io,
@@ -349,8 +347,6 @@ MACHINE_END
349 347
350#ifdef CONFIG_MACH_BIGDISK 348#ifdef CONFIG_MACH_BIGDISK
351MACHINE_START(BIGDISK, "LaCie Big Disk Network") 349MACHINE_START(BIGDISK, "LaCie Big Disk Network")
352 .phys_io = ORION5X_REGS_PHYS_BASE,
353 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
354 .boot_params = 0x00000100, 350 .boot_params = 0x00000100,
355 .init_machine = d2net_init, 351 .init_machine = d2net_init,
356 .map_io = orion5x_map_io, 352 .map_io = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index d318bea2af91..df1083f5b6eb 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -358,8 +358,6 @@ static void __init db88f5281_init(void)
358 358
359MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") 359MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
360 /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */ 360 /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
361 .phys_io = ORION5X_REGS_PHYS_BASE,
362 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xfffc,
363 .boot_params = 0x00000100, 361 .boot_params = 0x00000100,
364 .init_machine = db88f5281_init, 362 .init_machine = db88f5281_init,
365 .map_io = orion5x_map_io, 363 .map_io = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index a47100d46a4e..3a7bc0e36982 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -730,8 +730,6 @@ static void __init dns323_init(void)
730/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ 730/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
731MACHINE_START(DNS323, "D-Link DNS-323") 731MACHINE_START(DNS323, "D-Link DNS-323")
732 /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */ 732 /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
733 .phys_io = ORION5X_REGS_PHYS_BASE,
734 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
735 .boot_params = 0x00000100, 733 .boot_params = 0x00000100,
736 .init_machine = dns323_init, 734 .init_machine = dns323_init,
737 .map_io = orion5x_map_io, 735 .map_io = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index b24ee0c2cd61..ba98459f44b0 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -251,8 +251,6 @@ static void __init edmini_v2_init(void)
251/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */ 251/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
252MACHINE_START(EDMINI_V2, "LaCie Ethernet Disk mini V2") 252MACHINE_START(EDMINI_V2, "LaCie Ethernet Disk mini V2")
253 /* Maintainer: Christopher Moore <moore@free.fr> */ 253 /* Maintainer: Christopher Moore <moore@free.fr> */
254 .phys_io = ORION5X_REGS_PHYS_BASE,
255 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
256 .boot_params = 0x00000100, 254 .boot_params = 0x00000100,
257 .init_machine = edmini_v2_init, 255 .init_machine = edmini_v2_init,
258 .map_io = orion5x_map_io, 256 .map_io = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/include/mach/debug-macro.S b/arch/arm/mach-orion5x/include/mach/debug-macro.S
index 91e0e39bb23f..5e3bf5b68aec 100644
--- a/arch/arm/mach-orion5x/include/mach/debug-macro.S
+++ b/arch/arm/mach-orion5x/include/mach/debug-macro.S
@@ -10,12 +10,11 @@
10 10
11#include <mach/orion5x.h> 11#include <mach/orion5x.h>
12 12
13 .macro addruart, rx, tmp 13 .macro addruart, rp, rv
14 mrc p15, 0, \rx, c1, c0 14 ldr \rp, =ORION5X_REGS_PHYS_BASE
15 tst \rx, #1 @ MMU enabled? 15 ldr \rv, =ORION5X_REGS_VIRT_BASE
16 ldreq \rx, =ORION5X_REGS_PHYS_BASE 16 orr \rp, \rp, #0x00012000
17 ldrne \rx, =ORION5X_REGS_VIRT_BASE 17 orr \rv, \rv, #0x00012000
18 orr \rx, \rx, #0x00012000
19 .endm 18 .endm
20 19
21#define UART_SHIFT 2 20#define UART_SHIFT 2
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index dfbb68df7b09..4be9aa08de69 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -379,8 +379,6 @@ static void __init kurobox_pro_init(void)
379#ifdef CONFIG_MACH_KUROBOX_PRO 379#ifdef CONFIG_MACH_KUROBOX_PRO
380MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") 380MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
381 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ 381 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
382 .phys_io = ORION5X_REGS_PHYS_BASE,
383 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
384 .boot_params = 0x00000100, 382 .boot_params = 0x00000100,
385 .init_machine = kurobox_pro_init, 383 .init_machine = kurobox_pro_init,
386 .map_io = orion5x_map_io, 384 .map_io = orion5x_map_io,
@@ -393,8 +391,6 @@ MACHINE_END
393#ifdef CONFIG_MACH_LINKSTATION_PRO 391#ifdef CONFIG_MACH_LINKSTATION_PRO
394MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live") 392MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live")
395 /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */ 393 /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
396 .phys_io = ORION5X_REGS_PHYS_BASE,
397 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
398 .boot_params = 0x00000100, 394 .boot_params = 0x00000100,
399 .init_machine = kurobox_pro_init, 395 .init_machine = kurobox_pro_init,
400 .map_io = orion5x_map_io, 396 .map_io = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index 8e569be6e2c7..437364b7168e 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -265,8 +265,6 @@ static void __init ls_hgl_init(void)
265 265
266MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL") 266MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL")
267 /* Maintainer: Zhu Qingsen <zhuqs@cn.fujistu.com> */ 267 /* Maintainer: Zhu Qingsen <zhuqs@cn.fujistu.com> */
268 .phys_io = ORION5X_REGS_PHYS_BASE,
269 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
270 .boot_params = 0x00000100, 268 .boot_params = 0x00000100,
271 .init_machine = ls_hgl_init, 269 .init_machine = ls_hgl_init,
272 .map_io = orion5x_map_io, 270 .map_io = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index c704f056de1e..ab9b0cf0a90b 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -267,8 +267,6 @@ static void __init lsmini_init(void)
267#ifdef CONFIG_MACH_LINKSTATION_MINI 267#ifdef CONFIG_MACH_LINKSTATION_MINI
268MACHINE_START(LINKSTATION_MINI, "Buffalo Linkstation Mini") 268MACHINE_START(LINKSTATION_MINI, "Buffalo Linkstation Mini")
269 /* Maintainer: Alexey Kopytko <alexey@kopytko.ru> */ 269 /* Maintainer: Alexey Kopytko <alexey@kopytko.ru> */
270 .phys_io = ORION5X_REGS_PHYS_BASE,
271 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
272 .boot_params = 0x00000100, 270 .boot_params = 0x00000100,
273 .init_machine = lsmini_init, 271 .init_machine = lsmini_init,
274 .map_io = orion5x_map_io, 272 .map_io = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 61c086b66723..2f0e16cd7e81 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -261,8 +261,6 @@ static void __init mss2_init(void)
261 261
262MACHINE_START(MSS2, "Maxtor Shared Storage II") 262MACHINE_START(MSS2, "Maxtor Shared Storage II")
263 /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */ 263 /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */
264 .phys_io = ORION5X_REGS_PHYS_BASE,
265 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
266 .boot_params = 0x00000100, 264 .boot_params = 0x00000100,
267 .init_machine = mss2_init, 265 .init_machine = mss2_init,
268 .map_io = orion5x_map_io, 266 .map_io = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index 97c9ccb2ac60..b3d90f25de9f 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -229,8 +229,6 @@ static void __init mv2120_init(void)
229/* Warning: HP uses a wrong mach-type (=526) in their bootloader */ 229/* Warning: HP uses a wrong mach-type (=526) in their bootloader */
230MACHINE_START(MV2120, "HP Media Vault mv2120") 230MACHINE_START(MV2120, "HP Media Vault mv2120")
231 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */ 231 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
232 .phys_io = ORION5X_REGS_PHYS_BASE,
233 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
234 .boot_params = 0x00000100, 232 .boot_params = 0x00000100,
235 .init_machine = mv2120_init, 233 .init_machine = mv2120_init,
236 .map_io = orion5x_map_io, 234 .map_io = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index 7bd6283476f9..d6665b31665f 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -419,8 +419,6 @@ static void __init net2big_init(void)
419 419
420/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */ 420/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
421MACHINE_START(NET2BIG, "LaCie 2Big Network") 421MACHINE_START(NET2BIG, "LaCie 2Big Network")
422 .phys_io = ORION5X_REGS_PHYS_BASE,
423 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
424 .boot_params = 0x00000100, 422 .boot_params = 0x00000100,
425 .init_machine = net2big_init, 423 .init_machine = net2big_init,
426 .map_io = orion5x_map_io, 424 .map_io = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 9c1ca41730ba..f4c26fd731f4 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -169,8 +169,6 @@ subsys_initcall(rd88f5181l_fxo_pci_init);
169 169
170MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design") 170MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design")
171 /* Maintainer: Nicolas Pitre <nico@marvell.com> */ 171 /* Maintainer: Nicolas Pitre <nico@marvell.com> */
172 .phys_io = ORION5X_REGS_PHYS_BASE,
173 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
174 .boot_params = 0x00000100, 172 .boot_params = 0x00000100,
175 .init_machine = rd88f5181l_fxo_init, 173 .init_machine = rd88f5181l_fxo_init,
176 .map_io = orion5x_map_io, 174 .map_io = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index ee1399ff0ced..b5942909bab0 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -181,8 +181,6 @@ subsys_initcall(rd88f5181l_ge_pci_init);
181 181
182MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design") 182MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
183 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ 183 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
184 .phys_io = ORION5X_REGS_PHYS_BASE,
185 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
186 .boot_params = 0x00000100, 184 .boot_params = 0x00000100,
187 .init_machine = rd88f5181l_ge_init, 185 .init_machine = rd88f5181l_ge_init,
188 .map_io = orion5x_map_io, 186 .map_io = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index a04f9e4b633a..165ed87029b2 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -305,8 +305,6 @@ static void __init rd88f5182_init(void)
305 305
306MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") 306MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
307 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ 307 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
308 .phys_io = ORION5X_REGS_PHYS_BASE,
309 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
310 .boot_params = 0x00000100, 308 .boot_params = 0x00000100,
311 .init_machine = rd88f5182_init, 309 .init_machine = rd88f5182_init,
312 .map_io = orion5x_map_io, 310 .map_io = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index 7737cf9a8f50..02ff45f3e2e3 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -123,8 +123,6 @@ subsys_initcall(rd88f6183ap_ge_pci_init);
123 123
124MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design") 124MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design")
125 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ 125 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
126 .phys_io = ORION5X_REGS_PHYS_BASE,
127 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
128 .boot_params = 0x00000100, 126 .boot_params = 0x00000100,
129 .init_machine = rd88f6183ap_ge_init, 127 .init_machine = rd88f6183ap_ge_init,
130 .map_io = orion5x_map_io, 128 .map_io = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 0b101d7d41c2..4403fae5ab0e 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -358,8 +358,6 @@ static void __init tsp2_init(void)
358 358
359MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live") 359MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live")
360 /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */ 360 /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */
361 .phys_io = ORION5X_REGS_PHYS_BASE,
362 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
363 .boot_params = 0x00000100, 361 .boot_params = 0x00000100,
364 .init_machine = tsp2_init, 362 .init_machine = tsp2_init,
365 .map_io = orion5x_map_io, 363 .map_io = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 9d6890514199..1e196129d763 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -322,8 +322,6 @@ static void __init qnap_ts209_init(void)
322 322
323MACHINE_START(TS209, "QNAP TS-109/TS-209") 323MACHINE_START(TS209, "QNAP TS-109/TS-209")
324 /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */ 324 /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
325 .phys_io = ORION5X_REGS_PHYS_BASE,
326 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
327 .boot_params = 0x00000100, 325 .boot_params = 0x00000100,
328 .init_machine = qnap_ts209_init, 326 .init_machine = qnap_ts209_init,
329 .map_io = orion5x_map_io, 327 .map_io = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index d85588ac7ef8..428af2046e36 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -311,8 +311,6 @@ static void __init qnap_ts409_init(void)
311 311
312MACHINE_START(TS409, "QNAP TS-409") 312MACHINE_START(TS409, "QNAP TS-409")
313 /* Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com> */ 313 /* Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com> */
314 .phys_io = ORION5X_REGS_PHYS_BASE,
315 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
316 .boot_params = 0x00000100, 314 .boot_params = 0x00000100,
317 .init_machine = qnap_ts409_init, 315 .init_machine = qnap_ts409_init,
318 .map_io = orion5x_map_io, 316 .map_io = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index 696b1a97f9e2..16f1bd5324be 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -550,8 +550,6 @@ static void __init ts78xx_init(void)
550 550
551MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC") 551MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
552 /* Maintainer: Alexander Clouter <alex@digriz.org.uk> */ 552 /* Maintainer: Alexander Clouter <alex@digriz.org.uk> */
553 .phys_io = ORION5X_REGS_PHYS_BASE,
554 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
555 .boot_params = 0x00000100, 553 .boot_params = 0x00000100,
556 .init_machine = ts78xx_init, 554 .init_machine = ts78xx_init,
557 .map_io = ts78xx_map_io, 555 .map_io = ts78xx_map_io,
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 69208217b220..7994d6ec08a8 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -172,8 +172,6 @@ subsys_initcall(wnr854t_pci_init);
172 172
173MACHINE_START(WNR854T, "Netgear WNR854T") 173MACHINE_START(WNR854T, "Netgear WNR854T")
174 /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */ 174 /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
175 .phys_io = ORION5X_REGS_PHYS_BASE,
176 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
177 .boot_params = 0x00000100, 175 .boot_params = 0x00000100,
178 .init_machine = wnr854t_init, 176 .init_machine = wnr854t_init,
179 .map_io = orion5x_map_io, 177 .map_io = orion5x_map_io,
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index f9f222ebb7ed..a5989b7eb53e 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -260,8 +260,6 @@ subsys_initcall(wrt350n_v2_pci_init);
260 260
261MACHINE_START(WRT350N_V2, "Linksys WRT350N v2") 261MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
262 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ 262 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
263 .phys_io = ORION5X_REGS_PHYS_BASE,
264 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
265 .boot_params = 0x00000100, 263 .boot_params = 0x00000100,
266 .init_machine = wrt350n_v2_init, 264 .init_machine = wrt350n_v2_init,
267 .map_io = orion5x_map_io, 265 .map_io = orion5x_map_io,
diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
index 45734bb880a8..63399755f199 100644
--- a/arch/arm/mach-pnx4008/core.c
+++ b/arch/arm/mach-pnx4008/core.c
@@ -264,8 +264,6 @@ extern struct sys_timer pnx4008_timer;
264 264
265MACHINE_START(PNX4008, "Philips PNX4008") 265MACHINE_START(PNX4008, "Philips PNX4008")
266 /* Maintainer: MontaVista Software Inc. */ 266 /* Maintainer: MontaVista Software Inc. */
267 .phys_io = 0x40090000,
268 .io_pg_offst = (0xf4090000 >> 18) & 0xfffc,
269 .boot_params = 0x80000100, 267 .boot_params = 0x80000100,
270 .map_io = pnx4008_map_io, 268 .map_io = pnx4008_map_io,
271 .init_irq = pnx4008_init_irq, 269 .init_irq = pnx4008_init_irq,
diff --git a/arch/arm/mach-pnx4008/include/mach/debug-macro.S b/arch/arm/mach-pnx4008/include/mach/debug-macro.S
index 6ca8bd30bf46..931afebaf064 100644
--- a/arch/arm/mach-pnx4008/include/mach/debug-macro.S
+++ b/arch/arm/mach-pnx4008/include/mach/debug-macro.S
@@ -11,12 +11,10 @@
11 * 11 *
12*/ 12*/
13 13
14 .macro addruart, rx, tmp 14 .macro addruart, rp, rv
15 mrc p15, 0, \rx, c1, c0 15 mov \rp, #0x00090000
16 tst \rx, #1 @ MMU enabled? 16 add \rv, \rp, #0xf4000000 @ virtual
17 mov \rx, #0x00090000 17 add \rp, \rp, #0x40000000 @ physical
18 addeq \rx, \rx, #0x40000000
19 addne \rx, \rx, #0xf4000000
20 .endm 18 .endm
21 19
22#define UART_SHIFT 2 20#define UART_SHIFT 2
diff --git a/arch/arm/mach-pnx4008/include/mach/vmalloc.h b/arch/arm/mach-pnx4008/include/mach/vmalloc.h
index 2ad398378aed..31b65ee07b0b 100644
--- a/arch/arm/mach-pnx4008/include/mach/vmalloc.h
+++ b/arch/arm/mach-pnx4008/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
17 * The vmalloc() routines leaves a hole of 4kB between each vmalloced 17 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
18 * area for the same reason. ;) 18 * area for the same reason. ;)
19 */ 19 */
20#define VMALLOC_END (PAGE_OFFSET + 0x10000000) 20#define VMALLOC_END 0xd0000000
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 7aefb9074852..dd235ecc9d6c 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -8,19 +8,16 @@ config ARCH_LUBBOCK
8 bool "Intel DBPXA250 Development Platform (aka Lubbock)" 8 bool "Intel DBPXA250 Development Platform (aka Lubbock)"
9 select PXA25x 9 select PXA25x
10 select SA1111 10 select SA1111
11 select PXA_HAVE_BOARD_IRQS
12 11
13config MACH_MAINSTONE 12config MACH_MAINSTONE
14 bool "Intel HCDDBBVA0 Development Platform (aka Mainstone)" 13 bool "Intel HCDDBBVA0 Development Platform (aka Mainstone)"
15 select PXA27x 14 select PXA27x
16 select HAVE_PWM 15 select HAVE_PWM
17 select PXA_HAVE_BOARD_IRQS
18 16
19config MACH_ZYLONITE 17config MACH_ZYLONITE
20 bool 18 bool
21 select PXA3xx 19 select PXA3xx
22 select HAVE_PWM 20 select HAVE_PWM
23 select PXA_HAVE_BOARD_IRQS
24 21
25config MACH_ZYLONITE300 22config MACH_ZYLONITE300
26 bool "PXA3xx Development Platform (aka Zylonite) PXA300/310" 23 bool "PXA3xx Development Platform (aka Zylonite) PXA300/310"
@@ -44,6 +41,10 @@ config MACH_TAVOREVB
44 select PXA3xx 41 select PXA3xx
45 select CPU_PXA930 42 select CPU_PXA930
46 43
44config MACH_TAVOREVB3
45 bool "PXA95x Development Platform (aka TavorEVB III)"
46 select CPU_PXA950
47
47config MACH_SAAR 48config MACH_SAAR
48 bool "PXA930 Handheld Platform (aka SAAR)" 49 bool "PXA930 Handheld Platform (aka SAAR)"
49 select PXA3xx 50 select PXA3xx
@@ -61,7 +62,6 @@ config ARCH_VIPER
61 select ISA 62 select ISA
62 select I2C_GPIO 63 select I2C_GPIO
63 select HAVE_PWM 64 select HAVE_PWM
64 select PXA_HAVE_BOARD_IRQS
65 select PXA_HAVE_ISA_IRQS 65 select PXA_HAVE_ISA_IRQS
66 select ARCOM_PCMCIA 66 select ARCOM_PCMCIA
67 67
@@ -69,7 +69,6 @@ config MACH_ARCOM_ZEUS
69 bool "Arcom/Eurotech ZEUS SBC" 69 bool "Arcom/Eurotech ZEUS SBC"
70 select PXA27x 70 select PXA27x
71 select ISA 71 select ISA
72 select PXA_HAVE_BOARD_IRQS
73 select PXA_HAVE_ISA_IRQS 72 select PXA_HAVE_ISA_IRQS
74 select ARCOM_PCMCIA 73 select ARCOM_PCMCIA
75 74
@@ -77,7 +76,6 @@ config MACH_BALLOON3
77 bool "Balloon 3 board" 76 bool "Balloon 3 board"
78 select PXA27x 77 select PXA27x
79 select IWMMXT 78 select IWMMXT
80 select PXA_HAVE_BOARD_IRQS
81 79
82config MACH_CSB726 80config MACH_CSB726
83 bool "Enable Cogent CSB726 System On a Module" 81 bool "Enable Cogent CSB726 System On a Module"
@@ -140,13 +138,11 @@ config MACH_INTELMOTE2
140 bool "Intel Mote 2 Platform" 138 bool "Intel Mote 2 Platform"
141 select PXA27x 139 select PXA27x
142 select IWMMXT 140 select IWMMXT
143 select PXA_HAVE_BOARD_IRQS
144 141
145config MACH_STARGATE2 142config MACH_STARGATE2
146 bool "Intel Stargate 2 Platform" 143 bool "Intel Stargate 2 Platform"
147 select PXA27x 144 select PXA27x
148 select IWMMXT 145 select IWMMXT
149 select PXA_HAVE_BOARD_IRQS
150 146
151config MACH_XCEP 147config MACH_XCEP
152 bool "Iskratel Electronics XCEP" 148 bool "Iskratel Electronics XCEP"
@@ -206,13 +202,11 @@ config MACH_LOGICPD_PXA270
206 bool "LogicPD PXA270 Card Engine Development Platform" 202 bool "LogicPD PXA270 Card Engine Development Platform"
207 select PXA27x 203 select PXA27x
208 select HAVE_PWM 204 select HAVE_PWM
209 select PXA_HAVE_BOARD_IRQS
210 205
211config MACH_PCM027 206config MACH_PCM027
212 bool "Phytec phyCORE-PXA270 CPU module (PCM-027)" 207 bool "Phytec phyCORE-PXA270 CPU module (PCM-027)"
213 select PXA27x 208 select PXA27x
214 select IWMMXT 209 select IWMMXT
215 select PXA_HAVE_BOARD_IRQS
216 210
217config MACH_PCM990_BASEBOARD 211config MACH_PCM990_BASEBOARD
218 bool "PHYTEC PCM-990 development board" 212 bool "PHYTEC PCM-990 development board"
@@ -247,7 +241,6 @@ config MACH_COLIBRI_PXA270_INCOME
247 depends on MACH_COLIBRI 241 depends on MACH_COLIBRI
248 select PXA27x 242 select PXA27x
249 select HAVE_PWM 243 select HAVE_PWM
250 select PXA_HAVE_BOARD_IRQS
251 244
252config MACH_COLIBRI300 245config MACH_COLIBRI300
253 bool "Toradex Colibri PXA300/310" 246 bool "Toradex Colibri PXA300/310"
@@ -274,7 +267,6 @@ config MACH_H4700
274 select PXA27x 267 select PXA27x
275 select IWMMXT 268 select IWMMXT
276 select HAVE_PWM 269 select HAVE_PWM
277 select PXA_HAVE_BOARD_IRQS
278 270
279config MACH_H5000 271config MACH_H5000
280 bool "HP iPAQ h5000" 272 bool "HP iPAQ h5000"
@@ -289,7 +281,6 @@ config MACH_MAGICIAN
289 select PXA27x 281 select PXA27x
290 select IWMMXT 282 select IWMMXT
291 select HAVE_PWM 283 select HAVE_PWM
292 select PXA_HAVE_BOARD_IRQS
293 284
294config MACH_MIOA701 285config MACH_MIOA701
295 bool "Mitac Mio A701 Support" 286 bool "Mitac Mio A701 Support"
@@ -307,7 +298,6 @@ config PXA_EZX
307 select PXA27x 298 select PXA27x
308 select IWMMXT 299 select IWMMXT
309 select HAVE_PWM 300 select HAVE_PWM
310 select PXA_HAVE_BOARD_IRQS
311 301
312config MACH_EZX_A780 302config MACH_EZX_A780
313 bool "Motorola EZX A780" 303 bool "Motorola EZX A780"
@@ -478,7 +468,6 @@ config MACH_POODLE
478 depends on PXA_SHARPSL 468 depends on PXA_SHARPSL
479 select PXA25x 469 select PXA25x
480 select SHARP_LOCOMO 470 select SHARP_LOCOMO
481 select PXA_HAVE_BOARD_IRQS
482 471
483config MACH_CORGI 472config MACH_CORGI
484 bool "Enable Sharp SL-C700 (Corgi) Support" 473 bool "Enable Sharp SL-C700 (Corgi) Support"
@@ -523,7 +512,6 @@ config MACH_TOSA
523 bool "Enable Sharp SL-6000x (Tosa) Support" 512 bool "Enable Sharp SL-6000x (Tosa) Support"
524 depends on PXA_SHARPSL 513 depends on PXA_SHARPSL
525 select PXA25x 514 select PXA25x
526 select PXA_HAVE_BOARD_IRQS
527 515
528config TOSA_BT 516config TOSA_BT
529 tristate "Control the state of built-in bluetooth chip on Sharp SL-6000" 517 tristate "Control the state of built-in bluetooth chip on Sharp SL-6000"
@@ -552,7 +540,6 @@ config MACH_ICONTROL
552config ARCH_PXA_ESERIES 540config ARCH_PXA_ESERIES
553 bool "PXA based Toshiba e-series PDAs" 541 bool "PXA based Toshiba e-series PDAs"
554 select PXA25x 542 select PXA25x
555 select PXA_HAVE_BOARD_IRQS
556 543
557config MACH_E330 544config MACH_E330
558 bool "Toshiba e330" 545 bool "Toshiba e330"
@@ -606,7 +593,6 @@ config MACH_ZIPIT2
606 bool "Zipit Z2 Handheld" 593 bool "Zipit Z2 Handheld"
607 select PXA27x 594 select PXA27x
608 select HAVE_PWM 595 select HAVE_PWM
609 select PXA_HAVE_BOARD_IRQS
610 596
611endmenu 597endmenu
612 598
@@ -643,6 +629,7 @@ config CPU_PXA300
643config CPU_PXA310 629config CPU_PXA310
644 bool 630 bool
645 select CPU_PXA300 631 select CPU_PXA300
632 select PXA310_ULPI if USB_ULPI
646 help 633 help
647 PXA310 (codename Monahans-LV) 634 PXA310 (codename Monahans-LV)
648 635
@@ -692,10 +679,10 @@ config SHARPSL_PM_MAX1111
692 select HWMON 679 select HWMON
693 select SENSORS_MAX1111 680 select SENSORS_MAX1111
694 681
695config PXA_HAVE_BOARD_IRQS 682config PXA_HAVE_ISA_IRQS
696 bool 683 bool
697 684
698config PXA_HAVE_ISA_IRQS 685config PXA310_ULPI
699 bool 686 bool
700 687
701endif 688endif
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 85c7fb324dbb..e2f89c2c6f49 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -18,7 +18,7 @@ endif
18# SoC-specific code 18# SoC-specific code
19obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa2xx.o pxa25x.o 19obj-$(CONFIG_PXA25x) += mfp-pxa2xx.o pxa2xx.o pxa25x.o
20obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa2xx.o pxa27x.o 20obj-$(CONFIG_PXA27x) += mfp-pxa2xx.o pxa2xx.o pxa27x.o
21obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o 21obj-$(CONFIG_PXA3xx) += mfp-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
22obj-$(CONFIG_CPU_PXA300) += pxa300.o 22obj-$(CONFIG_CPU_PXA300) += pxa300.o
23obj-$(CONFIG_CPU_PXA320) += pxa320.o 23obj-$(CONFIG_CPU_PXA320) += pxa320.o
24obj-$(CONFIG_CPU_PXA930) += pxa930.o 24obj-$(CONFIG_CPU_PXA930) += pxa930.o
@@ -32,6 +32,7 @@ obj-$(CONFIG_MACH_ZYLONITE300) += zylonite.o zylonite_pxa300.o
32obj-$(CONFIG_MACH_ZYLONITE320) += zylonite.o zylonite_pxa320.o 32obj-$(CONFIG_MACH_ZYLONITE320) += zylonite.o zylonite_pxa320.o
33obj-$(CONFIG_MACH_LITTLETON) += littleton.o 33obj-$(CONFIG_MACH_LITTLETON) += littleton.o
34obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o 34obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o
35obj-$(CONFIG_MACH_TAVOREVB3) += tavorevb3.o
35obj-$(CONFIG_MACH_SAAR) += saar.o 36obj-$(CONFIG_MACH_SAAR) += saar.o
36 37
37# 3rd Party Dev Platforms 38# 3rd Party Dev Platforms
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index 9041340fee1d..21e188901935 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -68,42 +68,6 @@ static unsigned long balloon3_pin_config[] __initdata = {
68 68
69 /* Reset, configured as GPIO wakeup source */ 69 /* Reset, configured as GPIO wakeup source */
70 GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, 70 GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
71
72 /* LEDs */
73 GPIO9_GPIO, /* NAND activity LED */
74 GPIO10_GPIO, /* Heartbeat LED */
75
76 /* AC97 */
77 GPIO28_AC97_BITCLK,
78 GPIO29_AC97_SDATA_IN_0,
79 GPIO30_AC97_SDATA_OUT,
80 GPIO31_AC97_SYNC,
81 GPIO113_AC97_nRESET,
82 GPIO95_GPIO,
83
84 /* MMC */
85 GPIO32_MMC_CLK,
86 GPIO92_MMC_DAT_0,
87 GPIO109_MMC_DAT_1,
88 GPIO110_MMC_DAT_2,
89 GPIO111_MMC_DAT_3,
90 GPIO112_MMC_CMD,
91
92 /* USB Host */
93 GPIO88_USBH1_PWR,
94 GPIO89_USBH1_PEN,
95
96 /* PC Card */
97 GPIO48_nPOE,
98 GPIO49_nPWE,
99 GPIO50_nPIOR,
100 GPIO51_nPIOW,
101 GPIO85_nPCE_1,
102 GPIO54_nPCE_2,
103 GPIO79_PSKTSEL,
104 GPIO55_nPREG,
105 GPIO56_nPWAIT,
106 GPIO57_nIOIS16,
107}; 71};
108 72
109/****************************************************************************** 73/******************************************************************************
@@ -132,6 +96,34 @@ int __init parse_balloon3_features(char *arg)
132early_param("balloon3_features", parse_balloon3_features); 96early_param("balloon3_features", parse_balloon3_features);
133 97
134/****************************************************************************** 98/******************************************************************************
99 * Compact Flash slot
100 ******************************************************************************/
101#if defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
102static unsigned long balloon3_cf_pin_config[] __initdata = {
103 GPIO48_nPOE,
104 GPIO49_nPWE,
105 GPIO50_nPIOR,
106 GPIO51_nPIOW,
107 GPIO85_nPCE_1,
108 GPIO54_nPCE_2,
109 GPIO79_PSKTSEL,
110 GPIO55_nPREG,
111 GPIO56_nPWAIT,
112 GPIO57_nIOIS16,
113};
114
115static void __init balloon3_cf_init(void)
116{
117 if (!balloon3_has(BALLOON3_FEATURE_CF))
118 return;
119
120 pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_cf_pin_config));
121}
122#else
123static inline void balloon3_cf_init(void) {}
124#endif
125
126/******************************************************************************
135 * NOR Flash 127 * NOR Flash
136 ******************************************************************************/ 128 ******************************************************************************/
137#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) 129#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
@@ -179,6 +171,15 @@ static inline void balloon3_nor_init(void) {}
179 ******************************************************************************/ 171 ******************************************************************************/
180#if defined(CONFIG_TOUCHSCREEN_UCB1400) || \ 172#if defined(CONFIG_TOUCHSCREEN_UCB1400) || \
181 defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE) 173 defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
174static unsigned long balloon3_ac97_pin_config[] __initdata = {
175 GPIO28_AC97_BITCLK,
176 GPIO29_AC97_SDATA_IN_0,
177 GPIO30_AC97_SDATA_OUT,
178 GPIO31_AC97_SYNC,
179 GPIO113_AC97_nRESET,
180 GPIO95_GPIO,
181};
182
182static struct ucb1400_pdata vpac270_ucb1400_pdata = { 183static struct ucb1400_pdata vpac270_ucb1400_pdata = {
183 .irq = IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ), 184 .irq = IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ),
184}; 185};
@@ -197,6 +198,7 @@ static void __init balloon3_ts_init(void)
197 if (!balloon3_has(BALLOON3_FEATURE_AUDIO)) 198 if (!balloon3_has(BALLOON3_FEATURE_AUDIO))
198 return; 199 return;
199 200
201 pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_ac97_pin_config));
200 pxa_set_ac97_info(NULL); 202 pxa_set_ac97_info(NULL);
201 platform_device_register(&balloon3_ucb1400_device); 203 platform_device_register(&balloon3_ucb1400_device);
202} 204}
@@ -208,6 +210,11 @@ static inline void balloon3_ts_init(void) {}
208 * Framebuffer 210 * Framebuffer
209 ******************************************************************************/ 211 ******************************************************************************/
210#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) 212#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
213static unsigned long balloon3_lcd_pin_config[] __initdata = {
214 GPIOxx_LCD_TFT_16BPP,
215 GPIO99_GPIO,
216};
217
211static struct pxafb_mode_info balloon3_lcd_modes[] = { 218static struct pxafb_mode_info balloon3_lcd_modes[] = {
212 { 219 {
213 .pixclock = 38000, 220 .pixclock = 38000,
@@ -242,6 +249,8 @@ static void __init balloon3_lcd_init(void)
242 if (!balloon3_has(BALLOON3_FEATURE_TOPPOLY)) 249 if (!balloon3_has(BALLOON3_FEATURE_TOPPOLY))
243 return; 250 return;
244 251
252 pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_lcd_pin_config));
253
245 ret = gpio_request(BALLOON3_GPIO_RUN_BACKLIGHT, "BKL-ON"); 254 ret = gpio_request(BALLOON3_GPIO_RUN_BACKLIGHT, "BKL-ON");
246 if (ret) { 255 if (ret) {
247 pr_err("Requesting BKL-ON GPIO failed!\n"); 256 pr_err("Requesting BKL-ON GPIO failed!\n");
@@ -271,6 +280,15 @@ static inline void balloon3_lcd_init(void) {}
271 * SD/MMC card controller 280 * SD/MMC card controller
272 ******************************************************************************/ 281 ******************************************************************************/
273#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) 282#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
283static unsigned long balloon3_mmc_pin_config[] __initdata = {
284 GPIO32_MMC_CLK,
285 GPIO92_MMC_DAT_0,
286 GPIO109_MMC_DAT_1,
287 GPIO110_MMC_DAT_2,
288 GPIO111_MMC_DAT_3,
289 GPIO112_MMC_CMD,
290};
291
274static struct pxamci_platform_data balloon3_mci_platform_data = { 292static struct pxamci_platform_data balloon3_mci_platform_data = {
275 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, 293 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
276 .gpio_card_detect = -1, 294 .gpio_card_detect = -1,
@@ -281,6 +299,7 @@ static struct pxamci_platform_data balloon3_mci_platform_data = {
281 299
282static void __init balloon3_mmc_init(void) 300static void __init balloon3_mmc_init(void)
283{ 301{
302 pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_mmc_pin_config));
284 pxa_set_mci_info(&balloon3_mci_platform_data); 303 pxa_set_mci_info(&balloon3_mci_platform_data);
285} 304}
286#else 305#else
@@ -339,6 +358,11 @@ static inline void balloon3_irda_init(void) {}
339 * USB Host 358 * USB Host
340 ******************************************************************************/ 359 ******************************************************************************/
341#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 360#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
361static unsigned long balloon3_uhc_pin_config[] __initdata = {
362 GPIO88_USBH1_PWR,
363 GPIO89_USBH1_PEN,
364};
365
342static struct pxaohci_platform_data balloon3_ohci_info = { 366static struct pxaohci_platform_data balloon3_ohci_info = {
343 .port_mode = PMM_PERPORT_MODE, 367 .port_mode = PMM_PERPORT_MODE,
344 .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW, 368 .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
@@ -348,6 +372,7 @@ static void __init balloon3_uhc_init(void)
348{ 372{
349 if (!balloon3_has(BALLOON3_FEATURE_OHCI)) 373 if (!balloon3_has(BALLOON3_FEATURE_OHCI))
350 return; 374 return;
375 pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_uhc_pin_config));
351 pxa_set_ohci_info(&balloon3_ohci_info); 376 pxa_set_ohci_info(&balloon3_ohci_info);
352} 377}
353#else 378#else
@@ -358,6 +383,11 @@ static inline void balloon3_uhc_init(void) {}
358 * LEDs 383 * LEDs
359 ******************************************************************************/ 384 ******************************************************************************/
360#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) 385#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
386static unsigned long balloon3_led_pin_config[] __initdata = {
387 GPIO9_GPIO, /* NAND activity LED */
388 GPIO10_GPIO, /* Heartbeat LED */
389};
390
361struct gpio_led balloon3_gpio_leds[] = { 391struct gpio_led balloon3_gpio_leds[] = {
362 { 392 {
363 .name = "balloon3:green:idle", 393 .name = "balloon3:green:idle",
@@ -436,6 +466,7 @@ static struct platform_device balloon3_pcf_leds = {
436 466
437static void __init balloon3_leds_init(void) 467static void __init balloon3_leds_init(void)
438{ 468{
469 pxa2xx_mfp_config(ARRAY_AND_SIZE(balloon3_led_pin_config));
439 platform_device_register(&balloon3_leds); 470 platform_device_register(&balloon3_leds);
440 platform_device_register(&balloon3_pcf_leds); 471 platform_device_register(&balloon3_pcf_leds);
441} 472}
@@ -757,6 +788,7 @@ static void __init balloon3_init(void)
757 balloon3_ts_init(); 788 balloon3_ts_init();
758 balloon3_udc_init(); 789 balloon3_udc_init();
759 balloon3_uhc_init(); 790 balloon3_uhc_init();
791 balloon3_cf_init();
760} 792}
761 793
762static struct map_desc balloon3_io_desc[] __initdata = { 794static struct map_desc balloon3_io_desc[] __initdata = {
@@ -776,9 +808,8 @@ static void __init balloon3_map_io(void)
776 808
777MACHINE_START(BALLOON3, "Balloon3") 809MACHINE_START(BALLOON3, "Balloon3")
778 /* Maintainer: Nick Bane. */ 810 /* Maintainer: Nick Bane. */
779 .phys_io = 0x40000000,
780 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
781 .map_io = balloon3_map_io, 811 .map_io = balloon3_map_io,
812 .nr_irqs = BALLOON3_NR_IRQS,
782 .init_irq = balloon3_init_irq, 813 .init_irq = balloon3_init_irq,
783 .timer = &pxa_timer, 814 .timer = &pxa_timer,
784 .init_machine = balloon3_init, 815 .init_machine = balloon3_init,
diff --git a/arch/arm/mach-pxa/capc7117.c b/arch/arm/mach-pxa/capc7117.c
index aae544631a8b..4bd7a3cda48c 100644
--- a/arch/arm/mach-pxa/capc7117.c
+++ b/arch/arm/mach-pxa/capc7117.c
@@ -148,9 +148,7 @@ static void __init capc7117_init(void)
148 148
149MACHINE_START(CAPC7117, 149MACHINE_START(CAPC7117,
150 "Embedian CAPC-7117 evaluation kit based on the MXM-8x10 CoM") 150 "Embedian CAPC-7117 evaluation kit based on the MXM-8x10 CoM")
151 .phys_io = 0x40000000,
152 .boot_params = 0xa0000100, 151 .boot_params = 0xa0000100,
153 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
154 .map_io = pxa_map_io, 152 .map_io = pxa_map_io,
155 .init_irq = pxa3xx_init_irq, 153 .init_irq = pxa3xx_init_irq,
156 .timer = &pxa_timer, 154 .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index bff6e78f033d..ac5598ce9724 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -33,6 +33,9 @@
33extern void cmx255_init(void); 33extern void cmx255_init(void);
34extern void cmx270_init(void); 34extern void cmx270_init(void);
35 35
36/* reserve IRQs for IT8152 */
37#define CMX2XX_NR_IRQS (IRQ_BOARD_START + 40)
38
36/* virtual addresses for statically mapped regions */ 39/* virtual addresses for statically mapped regions */
37#define CMX2XX_VIRT_BASE (0xe8000000) 40#define CMX2XX_VIRT_BASE (0xe8000000)
38#define CMX2XX_IT8152_VIRT (CMX2XX_VIRT_BASE) 41#define CMX2XX_IT8152_VIRT (CMX2XX_VIRT_BASE)
@@ -511,9 +514,8 @@ static void __init cmx2xx_map_io(void)
511 514
512MACHINE_START(ARMCORE, "Compulab CM-X2XX") 515MACHINE_START(ARMCORE, "Compulab CM-X2XX")
513 .boot_params = 0xa0000100, 516 .boot_params = 0xa0000100,
514 .phys_io = 0x40000000,
515 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
516 .map_io = cmx2xx_map_io, 517 .map_io = cmx2xx_map_io,
518 .nr_irqs = CMX2XX_NR_IRQS,
517 .init_irq = cmx2xx_init_irq, 519 .init_irq = cmx2xx_init_irq,
518 .timer = &pxa_timer, 520 .timer = &pxa_timer,
519 .init_machine = cmx2xx_init, 521 .init_machine = cmx2xx_init,
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index c70e6c2f4e7c..922b1075b9de 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -19,6 +19,7 @@
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/delay.h> 20#include <linux/delay.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/clk.h>
22 23
23#include <linux/gpio.h> 24#include <linux/gpio.h>
24#include <linux/dm9000.h> 25#include <linux/dm9000.h>
@@ -50,6 +51,7 @@
50#include <plat/i2c.h> 51#include <plat/i2c.h>
51#include <plat/pxa3xx_nand.h> 52#include <plat/pxa3xx_nand.h>
52#include <mach/audio.h> 53#include <mach/audio.h>
54#include <mach/pxa3xx-u2d.h>
53 55
54#include <asm/mach/map.h> 56#include <asm/mach/map.h>
55 57
@@ -68,6 +70,8 @@
68#define GPIO97_RTC_RD (97) 70#define GPIO97_RTC_RD (97)
69#define GPIO98_RTC_IO (98) 71#define GPIO98_RTC_IO (98)
70 72
73#define GPIO_ULPI_PHY_RST (127)
74
71static mfp_cfg_t cm_x3xx_mfp_cfg[] __initdata = { 75static mfp_cfg_t cm_x3xx_mfp_cfg[] __initdata = {
72 /* LCD */ 76 /* LCD */
73 GPIO54_LCD_LDD_0, 77 GPIO54_LCD_LDD_0,
@@ -472,6 +476,78 @@ static void __init cm_x300_init_mmc(void)
472static inline void cm_x300_init_mmc(void) {} 476static inline void cm_x300_init_mmc(void) {}
473#endif 477#endif
474 478
479#if defined(CONFIG_PXA310_ULPI)
480static struct clk *pout_clk;
481
482static int cm_x300_ulpi_phy_reset(void)
483{
484 int err;
485
486 /* reset the PHY */
487 err = gpio_request(GPIO_ULPI_PHY_RST, "ulpi reset");
488 if (err) {
489 pr_err("%s: failed to request ULPI reset GPIO: %d\n",
490 __func__, err);
491 return err;
492 }
493
494 gpio_direction_output(GPIO_ULPI_PHY_RST, 0);
495 msleep(10);
496 gpio_set_value(GPIO_ULPI_PHY_RST, 1);
497 msleep(10);
498
499 gpio_free(GPIO_ULPI_PHY_RST);
500
501 return 0;
502}
503
504static inline int cm_x300_u2d_init(struct device *dev)
505{
506 int err = 0;
507
508 if (cpu_is_pxa310()) {
509 /* CLK_POUT is connected to the ULPI PHY */
510 pout_clk = clk_get(NULL, "CLK_POUT");
511 if (IS_ERR(pout_clk)) {
512 err = PTR_ERR(pout_clk);
513 pr_err("%s: failed to get CLK_POUT: %d\n",
514 __func__, err);
515 return err;
516 }
517 clk_enable(pout_clk);
518
519 err = cm_x300_ulpi_phy_reset();
520 if (err) {
521 clk_disable(pout_clk);
522 clk_put(pout_clk);
523 }
524 }
525
526 return err;
527}
528
529static void cm_x300_u2d_exit(struct device *dev)
530{
531 if (cpu_is_pxa310()) {
532 clk_disable(pout_clk);
533 clk_put(pout_clk);
534 }
535}
536
537static struct pxa3xx_u2d_platform_data cm_x300_u2d_platform_data = {
538 .ulpi_mode = ULPI_SER_6PIN,
539 .init = cm_x300_u2d_init,
540 .exit = cm_x300_u2d_exit,
541};
542
543static void cm_x300_init_u2d(void)
544{
545 pxa3xx_set_u2d_info(&cm_x300_u2d_platform_data);
546}
547#else
548static inline void cm_x300_init_u2d(void) {}
549#endif
550
475#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 551#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
476static int cm_x300_ohci_init(struct device *dev) 552static int cm_x300_ohci_init(struct device *dev)
477{ 553{
@@ -754,6 +830,7 @@ static void __init cm_x300_init(void)
754 cm_x300_init_da9030(); 830 cm_x300_init_da9030();
755 cm_x300_init_dm9000(); 831 cm_x300_init_dm9000();
756 cm_x300_init_lcd(); 832 cm_x300_init_lcd();
833 cm_x300_init_u2d();
757 cm_x300_init_ohci(); 834 cm_x300_init_ohci();
758 cm_x300_init_mmc(); 835 cm_x300_init_mmc();
759 cm_x300_init_nand(); 836 cm_x300_init_nand();
@@ -779,9 +856,7 @@ static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag *tags,
779} 856}
780 857
781MACHINE_START(CM_X300, "CM-X300 module") 858MACHINE_START(CM_X300, "CM-X300 module")
782 .phys_io = 0x40000000,
783 .boot_params = 0xa0000100, 859 .boot_params = 0xa0000100,
784 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
785 .map_io = pxa_map_io, 860 .map_io = pxa_map_io,
786 .init_irq = pxa3xx_init_irq, 861 .init_irq = pxa3xx_init_irq,
787 .timer = &pxa_timer, 862 .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c
index 98673ac6efd0..bc045100ec15 100644
--- a/arch/arm/mach-pxa/colibri-pxa270.c
+++ b/arch/arm/mach-pxa/colibri-pxa270.c
@@ -207,8 +207,6 @@ static void __init colibri_pxa270_income_init(void)
207} 207}
208 208
209MACHINE_START(COLIBRI, "Toradex Colibri PXA270") 209MACHINE_START(COLIBRI, "Toradex Colibri PXA270")
210 .phys_io = 0x40000000,
211 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
212 .boot_params = COLIBRI_SDRAM_BASE + 0x100, 210 .boot_params = COLIBRI_SDRAM_BASE + 0x100,
213 .init_machine = colibri_pxa270_init, 211 .init_machine = colibri_pxa270_init,
214 .map_io = pxa_map_io, 212 .map_io = pxa_map_io,
@@ -217,8 +215,6 @@ MACHINE_START(COLIBRI, "Toradex Colibri PXA270")
217MACHINE_END 215MACHINE_END
218 216
219MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC") 217MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC")
220 .phys_io = 0x40000000,
221 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
222 .boot_params = 0xa0000100, 218 .boot_params = 0xa0000100,
223 .init_machine = colibri_pxa270_income_init, 219 .init_machine = colibri_pxa270_income_init,
224 .map_io = pxa_map_io, 220 .map_io = pxa_map_io,
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
index 40b6ac2de876..a70b256591e6 100644
--- a/arch/arm/mach-pxa/colibri-pxa300.c
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -186,8 +186,6 @@ void __init colibri_pxa300_init(void)
186} 186}
187 187
188MACHINE_START(COLIBRI300, "Toradex Colibri PXA300") 188MACHINE_START(COLIBRI300, "Toradex Colibri PXA300")
189 .phys_io = 0x40000000,
190 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
191 .boot_params = COLIBRI_SDRAM_BASE + 0x100, 189 .boot_params = COLIBRI_SDRAM_BASE + 0x100,
192 .init_machine = colibri_pxa300_init, 190 .init_machine = colibri_pxa300_init,
193 .map_io = pxa_map_io, 191 .map_io = pxa_map_io,
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
index 99e850d84710..ca5f29e2e9cd 100644
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -255,8 +255,6 @@ void __init colibri_pxa320_init(void)
255} 255}
256 256
257MACHINE_START(COLIBRI320, "Toradex Colibri PXA320") 257MACHINE_START(COLIBRI320, "Toradex Colibri PXA320")
258 .phys_io = 0x40000000,
259 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
260 .boot_params = COLIBRI_SDRAM_BASE + 0x100, 258 .boot_params = COLIBRI_SDRAM_BASE + 0x100,
261 .init_machine = colibri_pxa320_init, 259 .init_machine = colibri_pxa320_init,
262 .map_io = pxa_map_io, 260 .map_io = pxa_map_io,
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 3fb0fc099080..821229acabe6 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -720,8 +720,6 @@ static void __init fixup_corgi(struct machine_desc *desc,
720 720
721#ifdef CONFIG_MACH_CORGI 721#ifdef CONFIG_MACH_CORGI
722MACHINE_START(CORGI, "SHARP Corgi") 722MACHINE_START(CORGI, "SHARP Corgi")
723 .phys_io = 0x40000000,
724 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
725 .fixup = fixup_corgi, 723 .fixup = fixup_corgi,
726 .map_io = pxa_map_io, 724 .map_io = pxa_map_io,
727 .init_irq = pxa25x_init_irq, 725 .init_irq = pxa25x_init_irq,
@@ -732,8 +730,6 @@ MACHINE_END
732 730
733#ifdef CONFIG_MACH_SHEPHERD 731#ifdef CONFIG_MACH_SHEPHERD
734MACHINE_START(SHEPHERD, "SHARP Shepherd") 732MACHINE_START(SHEPHERD, "SHARP Shepherd")
735 .phys_io = 0x40000000,
736 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
737 .fixup = fixup_corgi, 733 .fixup = fixup_corgi,
738 .map_io = pxa_map_io, 734 .map_io = pxa_map_io,
739 .init_irq = pxa25x_init_irq, 735 .init_irq = pxa25x_init_irq,
@@ -744,8 +740,6 @@ MACHINE_END
744 740
745#ifdef CONFIG_MACH_HUSKY 741#ifdef CONFIG_MACH_HUSKY
746MACHINE_START(HUSKY, "SHARP Husky") 742MACHINE_START(HUSKY, "SHARP Husky")
747 .phys_io = 0x40000000,
748 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
749 .fixup = fixup_corgi, 743 .fixup = fixup_corgi,
750 .map_io = pxa_map_io, 744 .map_io = pxa_map_io,
751 .init_irq = pxa25x_init_irq, 745 .init_irq = pxa25x_init_irq,
diff --git a/arch/arm/mach-pxa/cpufreq-pxa3xx.c b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
index 0a0d0fe99220..88fbec05ec50 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa3xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
@@ -159,7 +159,7 @@ static int pxa3xx_cpufreq_verify(struct cpufreq_policy *policy)
159 159
160static unsigned int pxa3xx_cpufreq_get(unsigned int cpu) 160static unsigned int pxa3xx_cpufreq_get(unsigned int cpu)
161{ 161{
162 return get_clk_frequency_khz(0); 162 return pxa3xx_get_clk_frequency_khz(0);
163} 163}
164 164
165static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy, 165static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy,
@@ -212,7 +212,8 @@ static int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
212 policy->cpuinfo.min_freq = 104000; 212 policy->cpuinfo.min_freq = 104000;
213 policy->cpuinfo.max_freq = (cpu_is_pxa320()) ? 806000 : 624000; 213 policy->cpuinfo.max_freq = (cpu_is_pxa320()) ? 806000 : 624000;
214 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */ 214 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
215 policy->cur = policy->min = policy->max = get_clk_frequency_khz(0); 215 policy->max = pxa3xx_get_clk_frequency_khz(0);
216 policy->cur = policy->min = policy->max;
216 217
217 if (cpu_is_pxa300() || cpu_is_pxa310()) 218 if (cpu_is_pxa300() || cpu_is_pxa310())
218 ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa300_freqs)); 219 ret = setup_freqs_table(policy, ARRAY_AND_SIZE(pxa300_freqs));
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c
index 91fd4fea6a54..57cacaff194d 100644
--- a/arch/arm/mach-pxa/csb726.c
+++ b/arch/arm/mach-pxa/csb726.c
@@ -272,9 +272,7 @@ static void __init csb726_init(void)
272} 272}
273 273
274MACHINE_START(CSB726, "Cogent CSB726") 274MACHINE_START(CSB726, "Cogent CSB726")
275 .phys_io = 0x40000000,
276 .boot_params = 0xa0000100, 275 .boot_params = 0xa0000100,
277 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
278 .map_io = pxa_map_io, 276 .map_io = pxa_map_io,
279 .init_irq = pxa27x_init_irq, 277 .init_irq = pxa27x_init_irq,
280 .init_machine = csb726_init, 278 .init_machine = csb726_init,
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 65447dc736c2..08b410343870 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -6,11 +6,12 @@
6 6
7#include <asm/pmu.h> 7#include <asm/pmu.h>
8#include <mach/udc.h> 8#include <mach/udc.h>
9#include <mach/pxa3xx-u2d.h>
9#include <mach/pxafb.h> 10#include <mach/pxafb.h>
10#include <mach/mmc.h> 11#include <mach/mmc.h>
11#include <mach/irda.h> 12#include <mach/irda.h>
12#include <mach/ohci.h> 13#include <mach/ohci.h>
13#include <mach/pxa27x_keypad.h> 14#include <plat/pxa27x_keypad.h>
14#include <mach/pxa2xx_spi.h> 15#include <mach/pxa2xx_spi.h>
15#include <mach/camera.h> 16#include <mach/camera.h>
16#include <mach/audio.h> 17#include <mach/audio.h>
@@ -134,6 +135,33 @@ struct platform_device pxa27x_device_udc = {
134 } 135 }
135}; 136};
136 137
138#ifdef CONFIG_PXA3xx
139static struct resource pxa3xx_u2d_resources[] = {
140 [0] = {
141 .start = 0x54100000,
142 .end = 0x54100fff,
143 .flags = IORESOURCE_MEM,
144 },
145 [1] = {
146 .start = IRQ_USB2,
147 .end = IRQ_USB2,
148 .flags = IORESOURCE_IRQ,
149 },
150};
151
152struct platform_device pxa3xx_device_u2d = {
153 .name = "pxa3xx-u2d",
154 .id = -1,
155 .resource = pxa3xx_u2d_resources,
156 .num_resources = ARRAY_SIZE(pxa3xx_u2d_resources),
157};
158
159void __init pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info)
160{
161 pxa_register_device(&pxa3xx_device_u2d, info);
162}
163#endif /* CONFIG_PXA3xx */
164
137static struct resource pxafb_resources[] = { 165static struct resource pxafb_resources[] = {
138 [0] = { 166 [0] = {
139 .start = 0x44000000, 167 .start = 0x44000000,
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index 50353ea49ba4..715e8bd02e24 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -4,6 +4,7 @@ extern struct platform_device pxa3xx_device_mci2;
4extern struct platform_device pxa3xx_device_mci3; 4extern struct platform_device pxa3xx_device_mci3;
5extern struct platform_device pxa25x_device_udc; 5extern struct platform_device pxa25x_device_udc;
6extern struct platform_device pxa27x_device_udc; 6extern struct platform_device pxa27x_device_udc;
7extern struct platform_device pxa3xx_device_u2d;
7extern struct platform_device pxa_device_fb; 8extern struct platform_device pxa_device_fb;
8extern struct platform_device pxa_device_ffuart; 9extern struct platform_device pxa_device_ffuart;
9extern struct platform_device pxa_device_btuart; 10extern struct platform_device pxa_device_btuart;
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 0517c17978f3..ab48bb81b570 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -43,7 +43,7 @@
43#include <mach/pxafb.h> 43#include <mach/pxafb.h>
44#include <mach/ohci.h> 44#include <mach/ohci.h>
45#include <mach/mmc.h> 45#include <mach/mmc.h>
46#include <mach/pxa27x_keypad.h> 46#include <plat/pxa27x_keypad.h>
47#include <plat/i2c.h> 47#include <plat/i2c.h>
48#include <mach/camera.h> 48#include <mach/camera.h>
49#include <mach/pxa2xx_spi.h> 49#include <mach/pxa2xx_spi.h>
@@ -1301,8 +1301,6 @@ static void __init em_x270_init(void)
1301 1301
1302MACHINE_START(EM_X270, "Compulab EM-X270") 1302MACHINE_START(EM_X270, "Compulab EM-X270")
1303 .boot_params = 0xa0000100, 1303 .boot_params = 0xa0000100,
1304 .phys_io = 0x40000000,
1305 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
1306 .map_io = pxa_map_io, 1304 .map_io = pxa_map_io,
1307 .init_irq = pxa27x_init_irq, 1305 .init_irq = pxa27x_init_irq,
1308 .timer = &pxa_timer, 1306 .timer = &pxa_timer,
@@ -1311,8 +1309,6 @@ MACHINE_END
1311 1309
1312MACHINE_START(EXEDA, "Compulab eXeda") 1310MACHINE_START(EXEDA, "Compulab eXeda")
1313 .boot_params = 0xa0000100, 1311 .boot_params = 0xa0000100,
1314 .phys_io = 0x40000000,
1315 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
1316 .map_io = pxa_map_io, 1312 .map_io = pxa_map_io,
1317 .init_irq = pxa27x_init_irq, 1313 .init_irq = pxa27x_init_irq,
1318 .timer = &pxa_timer, 1314 .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 349212a1cbd3..b25690ccadc4 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -29,6 +29,7 @@
29 29
30#include <mach/pxa25x.h> 30#include <mach/pxa25x.h>
31#include <mach/eseries-gpio.h> 31#include <mach/eseries-gpio.h>
32#include <mach/eseries-irq.h>
32#include <mach/audio.h> 33#include <mach/audio.h>
33#include <mach/pxafb.h> 34#include <mach/pxafb.h>
34#include <mach/udc.h> 35#include <mach/udc.h>
@@ -179,10 +180,9 @@ static void __init e330_init(void)
179 180
180MACHINE_START(E330, "Toshiba e330") 181MACHINE_START(E330, "Toshiba e330")
181 /* Maintainer: Ian Molton (spyro@f2s.com) */ 182 /* Maintainer: Ian Molton (spyro@f2s.com) */
182 .phys_io = 0x40000000,
183 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
184 .boot_params = 0xa0000100, 183 .boot_params = 0xa0000100,
185 .map_io = pxa_map_io, 184 .map_io = pxa_map_io,
185 .nr_irqs = ESERIES_NR_IRQS,
186 .init_irq = pxa25x_init_irq, 186 .init_irq = pxa25x_init_irq,
187 .fixup = eseries_fixup, 187 .fixup = eseries_fixup,
188 .init_machine = e330_init, 188 .init_machine = e330_init,
@@ -229,10 +229,9 @@ static void __init e350_init(void)
229 229
230MACHINE_START(E350, "Toshiba e350") 230MACHINE_START(E350, "Toshiba e350")
231 /* Maintainer: Ian Molton (spyro@f2s.com) */ 231 /* Maintainer: Ian Molton (spyro@f2s.com) */
232 .phys_io = 0x40000000,
233 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
234 .boot_params = 0xa0000100, 232 .boot_params = 0xa0000100,
235 .map_io = pxa_map_io, 233 .map_io = pxa_map_io,
234 .nr_irqs = ESERIES_NR_IRQS,
236 .init_irq = pxa25x_init_irq, 235 .init_irq = pxa25x_init_irq,
237 .fixup = eseries_fixup, 236 .fixup = eseries_fixup,
238 .init_machine = e350_init, 237 .init_machine = e350_init,
@@ -352,10 +351,9 @@ static void __init e400_init(void)
352 351
353MACHINE_START(E400, "Toshiba e400") 352MACHINE_START(E400, "Toshiba e400")
354 /* Maintainer: Ian Molton (spyro@f2s.com) */ 353 /* Maintainer: Ian Molton (spyro@f2s.com) */
355 .phys_io = 0x40000000,
356 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
357 .boot_params = 0xa0000100, 354 .boot_params = 0xa0000100,
358 .map_io = pxa_map_io, 355 .map_io = pxa_map_io,
356 .nr_irqs = ESERIES_NR_IRQS,
359 .init_irq = pxa25x_init_irq, 357 .init_irq = pxa25x_init_irq,
360 .fixup = eseries_fixup, 358 .fixup = eseries_fixup,
361 .init_machine = e400_init, 359 .init_machine = e400_init,
@@ -541,10 +539,9 @@ static void __init e740_init(void)
541 539
542MACHINE_START(E740, "Toshiba e740") 540MACHINE_START(E740, "Toshiba e740")
543 /* Maintainer: Ian Molton (spyro@f2s.com) */ 541 /* Maintainer: Ian Molton (spyro@f2s.com) */
544 .phys_io = 0x40000000,
545 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
546 .boot_params = 0xa0000100, 542 .boot_params = 0xa0000100,
547 .map_io = pxa_map_io, 543 .map_io = pxa_map_io,
544 .nr_irqs = ESERIES_NR_IRQS,
548 .init_irq = pxa25x_init_irq, 545 .init_irq = pxa25x_init_irq,
549 .fixup = eseries_fixup, 546 .fixup = eseries_fixup,
550 .init_machine = e740_init, 547 .init_machine = e740_init,
@@ -733,10 +730,9 @@ static void __init e750_init(void)
733 730
734MACHINE_START(E750, "Toshiba e750") 731MACHINE_START(E750, "Toshiba e750")
735 /* Maintainer: Ian Molton (spyro@f2s.com) */ 732 /* Maintainer: Ian Molton (spyro@f2s.com) */
736 .phys_io = 0x40000000,
737 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
738 .boot_params = 0xa0000100, 733 .boot_params = 0xa0000100,
739 .map_io = pxa_map_io, 734 .map_io = pxa_map_io,
735 .nr_irqs = ESERIES_NR_IRQS,
740 .init_irq = pxa25x_init_irq, 736 .init_irq = pxa25x_init_irq,
741 .fixup = eseries_fixup, 737 .fixup = eseries_fixup,
742 .init_machine = e750_init, 738 .init_machine = e750_init,
@@ -929,10 +925,9 @@ static void __init e800_init(void)
929 925
930MACHINE_START(E800, "Toshiba e800") 926MACHINE_START(E800, "Toshiba e800")
931 /* Maintainer: Ian Molton (spyro@f2s.com) */ 927 /* Maintainer: Ian Molton (spyro@f2s.com) */
932 .phys_io = 0x40000000,
933 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
934 .boot_params = 0xa0000100, 928 .boot_params = 0xa0000100,
935 .map_io = pxa_map_io, 929 .map_io = pxa_map_io,
930 .nr_irqs = ESERIES_NR_IRQS,
936 .init_irq = pxa25x_init_irq, 931 .init_irq = pxa25x_init_irq,
937 .fixup = eseries_fixup, 932 .fixup = eseries_fixup,
938 .init_machine = e800_init, 933 .init_machine = e800_init,
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index 626c82b13970..80a9352d43f3 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -32,12 +32,14 @@
32#include <mach/ohci.h> 32#include <mach/ohci.h>
33#include <plat/i2c.h> 33#include <plat/i2c.h>
34#include <mach/hardware.h> 34#include <mach/hardware.h>
35#include <mach/pxa27x_keypad.h> 35#include <plat/pxa27x_keypad.h>
36#include <mach/camera.h> 36#include <mach/camera.h>
37 37
38#include "devices.h" 38#include "devices.h"
39#include "generic.h" 39#include "generic.h"
40 40
41#define EZX_NR_IRQS (IRQ_BOARD_START + 24)
42
41#define GPIO12_A780_FLIP_LID 12 43#define GPIO12_A780_FLIP_LID 12
42#define GPIO15_A1200_FLIP_LID 15 44#define GPIO15_A1200_FLIP_LID 15
43#define GPIO15_A910_FLIP_LID 15 45#define GPIO15_A910_FLIP_LID 15
@@ -796,10 +798,9 @@ static void __init a780_init(void)
796} 798}
797 799
798MACHINE_START(EZX_A780, "Motorola EZX A780") 800MACHINE_START(EZX_A780, "Motorola EZX A780")
799 .phys_io = 0x40000000,
800 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
801 .boot_params = 0xa0000100, 801 .boot_params = 0xa0000100,
802 .map_io = pxa_map_io, 802 .map_io = pxa_map_io,
803 .nr_irqs = EZX_NR_IRQS,
803 .init_irq = pxa27x_init_irq, 804 .init_irq = pxa27x_init_irq,
804 .timer = &pxa_timer, 805 .timer = &pxa_timer,
805 .init_machine = a780_init, 806 .init_machine = a780_init,
@@ -862,10 +863,9 @@ static void __init e680_init(void)
862} 863}
863 864
864MACHINE_START(EZX_E680, "Motorola EZX E680") 865MACHINE_START(EZX_E680, "Motorola EZX E680")
865 .phys_io = 0x40000000,
866 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
867 .boot_params = 0xa0000100, 866 .boot_params = 0xa0000100,
868 .map_io = pxa_map_io, 867 .map_io = pxa_map_io,
868 .nr_irqs = EZX_NR_IRQS,
869 .init_irq = pxa27x_init_irq, 869 .init_irq = pxa27x_init_irq,
870 .timer = &pxa_timer, 870 .timer = &pxa_timer,
871 .init_machine = e680_init, 871 .init_machine = e680_init,
@@ -928,10 +928,9 @@ static void __init a1200_init(void)
928} 928}
929 929
930MACHINE_START(EZX_A1200, "Motorola EZX A1200") 930MACHINE_START(EZX_A1200, "Motorola EZX A1200")
931 .phys_io = 0x40000000,
932 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
933 .boot_params = 0xa0000100, 931 .boot_params = 0xa0000100,
934 .map_io = pxa_map_io, 932 .map_io = pxa_map_io,
933 .nr_irqs = EZX_NR_IRQS,
935 .init_irq = pxa27x_init_irq, 934 .init_irq = pxa27x_init_irq,
936 .timer = &pxa_timer, 935 .timer = &pxa_timer,
937 .init_machine = a1200_init, 936 .init_machine = a1200_init,
@@ -1120,10 +1119,9 @@ static void __init a910_init(void)
1120} 1119}
1121 1120
1122MACHINE_START(EZX_A910, "Motorola EZX A910") 1121MACHINE_START(EZX_A910, "Motorola EZX A910")
1123 .phys_io = 0x40000000,
1124 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
1125 .boot_params = 0xa0000100, 1122 .boot_params = 0xa0000100,
1126 .map_io = pxa_map_io, 1123 .map_io = pxa_map_io,
1124 .nr_irqs = EZX_NR_IRQS,
1127 .init_irq = pxa27x_init_irq, 1125 .init_irq = pxa27x_init_irq,
1128 .timer = &pxa_timer, 1126 .timer = &pxa_timer,
1129 .init_machine = a910_init, 1127 .init_machine = a910_init,
@@ -1186,10 +1184,9 @@ static void __init e6_init(void)
1186} 1184}
1187 1185
1188MACHINE_START(EZX_E6, "Motorola EZX E6") 1186MACHINE_START(EZX_E6, "Motorola EZX E6")
1189 .phys_io = 0x40000000,
1190 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
1191 .boot_params = 0xa0000100, 1187 .boot_params = 0xa0000100,
1192 .map_io = pxa_map_io, 1188 .map_io = pxa_map_io,
1189 .nr_irqs = EZX_NR_IRQS,
1193 .init_irq = pxa27x_init_irq, 1190 .init_irq = pxa27x_init_irq,
1194 .timer = &pxa_timer, 1191 .timer = &pxa_timer,
1195 .init_machine = e6_init, 1192 .init_machine = e6_init,
@@ -1226,10 +1223,9 @@ static void __init e2_init(void)
1226} 1223}
1227 1224
1228MACHINE_START(EZX_E2, "Motorola EZX E2") 1225MACHINE_START(EZX_E2, "Motorola EZX E2")
1229 .phys_io = 0x40000000,
1230 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
1231 .boot_params = 0xa0000100, 1226 .boot_params = 0xa0000100,
1232 .map_io = pxa_map_io, 1227 .map_io = pxa_map_io,
1228 .nr_irqs = EZX_NR_IRQS,
1233 .init_irq = pxa27x_init_irq, 1229 .init_irq = pxa27x_init_irq,
1234 .timer = &pxa_timer, 1230 .timer = &pxa_timer,
1235 .init_machine = e2_init, 1231 .init_machine = e2_init,
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index baabb3ce088e..6451e9c3a93f 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -66,8 +66,7 @@ unsigned int get_clk_frequency_khz(int info)
66 return pxa25x_get_clk_frequency_khz(info); 66 return pxa25x_get_clk_frequency_khz(info);
67 else if (cpu_is_pxa27x()) 67 else if (cpu_is_pxa27x())
68 return pxa27x_get_clk_frequency_khz(info); 68 return pxa27x_get_clk_frequency_khz(info);
69 else 69 return 0;
70 return pxa3xx_get_clk_frequency_khz(info);
71} 70}
72EXPORT_SYMBOL(get_clk_frequency_khz); 71EXPORT_SYMBOL(get_clk_frequency_khz);
73 72
@@ -80,8 +79,7 @@ unsigned int get_memclk_frequency_10khz(void)
80 return pxa25x_get_memclk_frequency_10khz(); 79 return pxa25x_get_memclk_frequency_10khz();
81 else if (cpu_is_pxa27x()) 80 else if (cpu_is_pxa27x())
82 return pxa27x_get_memclk_frequency_10khz(); 81 return pxa27x_get_memclk_frequency_10khz();
83 else 82 return 0;
84 return pxa3xx_get_memclk_frequency_10khz();
85} 83}
86EXPORT_SYMBOL(get_memclk_frequency_10khz); 84EXPORT_SYMBOL(get_memclk_frequency_10khz);
87 85
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index c6305c5b8a72..4b1ad2769ed7 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -54,11 +54,9 @@ static inline void pxa2xx_clear_reset_status(unsigned int mask) {}
54 54
55#ifdef CONFIG_PXA3xx 55#ifdef CONFIG_PXA3xx
56extern unsigned pxa3xx_get_clk_frequency_khz(int); 56extern unsigned pxa3xx_get_clk_frequency_khz(int);
57extern unsigned pxa3xx_get_memclk_frequency_10khz(void);
58extern void pxa3xx_clear_reset_status(unsigned int); 57extern void pxa3xx_clear_reset_status(unsigned int);
59#else 58#else
60#define pxa3xx_get_clk_frequency_khz(x) (0) 59#define pxa3xx_get_clk_frequency_khz(x) (0)
61#define pxa3xx_get_memclk_frequency_10khz() (0)
62static inline void pxa3xx_clear_reset_status(unsigned int mask) {} 60static inline void pxa3xx_clear_reset_status(unsigned int mask) {}
63#endif 61#endif
64 62
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index 96c345129135..1e2a9a13aec1 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -224,9 +224,7 @@ static void __init gumstix_init(void)
224} 224}
225 225
226MACHINE_START(GUMSTIX, "Gumstix") 226MACHINE_START(GUMSTIX, "Gumstix")
227 .phys_io = 0x40000000,
228 .boot_params = 0xa0000100, /* match u-boot bi_boot_params */ 227 .boot_params = 0xa0000100, /* match u-boot bi_boot_params */
229 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
230 .map_io = pxa_map_io, 228 .map_io = pxa_map_io,
231 .init_irq = pxa25x_init_irq, 229 .init_irq = pxa25x_init_irq,
232 .timer = &pxa_timer, 230 .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c
index c1cab0871c99..7057a1f46db4 100644
--- a/arch/arm/mach-pxa/h5000.c
+++ b/arch/arm/mach-pxa/h5000.c
@@ -201,8 +201,6 @@ static void __init h5000_init(void)
201} 201}
202 202
203MACHINE_START(H5400, "HP iPAQ H5000") 203MACHINE_START(H5400, "HP iPAQ H5000")
204 .phys_io = 0x40000000,
205 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
206 .boot_params = 0xa0000100, 204 .boot_params = 0xa0000100,
207 .map_io = pxa_map_io, 205 .map_io = pxa_map_io,
208 .init_irq = pxa25x_init_irq, 206 .init_irq = pxa25x_init_irq,
diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c
index f9a2e4b0f090..01b7f07ebad2 100644
--- a/arch/arm/mach-pxa/himalaya.c
+++ b/arch/arm/mach-pxa/himalaya.c
@@ -159,8 +159,6 @@ static void __init himalaya_init(void)
159 159
160 160
161MACHINE_START(HIMALAYA, "HTC Himalaya") 161MACHINE_START(HIMALAYA, "HTC Himalaya")
162 .phys_io = 0x40000000,
163 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
164 .boot_params = 0xa0000100, 162 .boot_params = 0xa0000100,
165 .map_io = pxa_map_io, 163 .map_io = pxa_map_io,
166 .init_irq = pxa25x_init_irq, 164 .init_irq = pxa25x_init_irq,
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 848c861dd23f..76d93a25bab6 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -870,10 +870,9 @@ static void __init hx4700_init(void)
870} 870}
871 871
872MACHINE_START(H4700, "HP iPAQ HX4700") 872MACHINE_START(H4700, "HP iPAQ HX4700")
873 .phys_io = 0x40000000,
874 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
875 .boot_params = 0xa0000100, 873 .boot_params = 0xa0000100,
876 .map_io = pxa_map_io, 874 .map_io = pxa_map_io,
875 .nr_irqs = HX4700_NR_IRQS,
877 .init_irq = pxa27x_init_irq, 876 .init_irq = pxa27x_init_irq,
878 .init_machine = hx4700_init, 877 .init_machine = hx4700_init,
879 .timer = &pxa_timer, 878 .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c
index 5ccb0ceff6c4..d51ee3d25e70 100644
--- a/arch/arm/mach-pxa/icontrol.c
+++ b/arch/arm/mach-pxa/icontrol.c
@@ -191,9 +191,7 @@ static void __init icontrol_init(void)
191} 191}
192 192
193MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM") 193MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM")
194 .phys_io = 0x40000000,
195 .boot_params = 0xa0000100, 194 .boot_params = 0xa0000100,
196 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
197 .map_io = pxa_map_io, 195 .map_io = pxa_map_io,
198 .init_irq = pxa3xx_init_irq, 196 .init_irq = pxa3xx_init_irq,
199 .timer = &pxa_timer, 197 .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index bc78c4dc0c66..e773dceeabc6 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -194,8 +194,6 @@ static void __init idp_map_io(void)
194 194
195MACHINE_START(PXA_IDP, "Vibren PXA255 IDP") 195MACHINE_START(PXA_IDP, "Vibren PXA255 IDP")
196 /* Maintainer: Vibren Technologies */ 196 /* Maintainer: Vibren Technologies */
197 .phys_io = 0x40000000,
198 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
199 .map_io = idp_map_io, 197 .map_io = idp_map_io,
200 .init_irq = pxa25x_init_irq, 198 .init_irq = pxa25x_init_irq,
201 .timer = &pxa_timer, 199 .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h
index eec92e6fd7cf..561562b4360b 100644
--- a/arch/arm/mach-pxa/include/mach/balloon3.h
+++ b/arch/arm/mach-pxa/include/mach/balloon3.h
@@ -174,6 +174,8 @@ enum balloon3_features {
174#define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ) 174#define BALLOON3_CODEC_IRQ IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ)
175#define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD) 175#define BALLOON3_S0_CD_IRQ IRQ_GPIO(BALLOON3_GPIO_S0_CD)
176 176
177#define BALLOON3_NR_IRQS (IRQ_BOARD_START + 4)
178
177extern int balloon3_has(enum balloon3_features feature); 179extern int balloon3_has(enum balloon3_features feature);
178 180
179#endif 181#endif
diff --git a/arch/arm/mach-pxa/include/mach/debug-macro.S b/arch/arm/mach-pxa/include/mach/debug-macro.S
index 01cf81393fe2..7d5c75125d65 100644
--- a/arch/arm/mach-pxa/include/mach/debug-macro.S
+++ b/arch/arm/mach-pxa/include/mach/debug-macro.S
@@ -13,12 +13,10 @@
13 13
14#include "hardware.h" 14#include "hardware.h"
15 15
16 .macro addruart, rx, tmp 16 .macro addruart, rp, rv
17 mrc p15, 0, \rx, c1, c0 17 mov \rp, #0x00100000
18 tst \rx, #1 @ MMU enabled? 18 orr \rv, \rp, #io_p2v(0x40000000) @ virtual
19 moveq \rx, #0x40000000 @ physical 19 orr \rp, \rp, #0x40000000 @ physical
20 movne \rx, #io_p2v(0x40000000) @ virtual
21 orr \rx, \rx, #0x00100000
22 .endm 20 .endm
23 21
24#define UART_SHIFT 2 22#define UART_SHIFT 2
diff --git a/arch/arm/mach-pxa/include/mach/eseries-irq.h b/arch/arm/mach-pxa/include/mach/eseries-irq.h
index f2a93d5e31d3..de292b269c63 100644
--- a/arch/arm/mach-pxa/include/mach/eseries-irq.h
+++ b/arch/arm/mach-pxa/include/mach/eseries-irq.h
@@ -25,3 +25,4 @@
25#define TMIO_SD_IRQ IRQ_TMIO(1) 25#define TMIO_SD_IRQ IRQ_TMIO(1)
26#define TMIO_USB_IRQ IRQ_TMIO(2) 26#define TMIO_USB_IRQ IRQ_TMIO(2)
27 27
28#define ESERIES_NR_IRQS (IRQ_BOARD_START + 16)
diff --git a/arch/arm/mach-pxa/include/mach/hx4700.h b/arch/arm/mach-pxa/include/mach/hx4700.h
index 9eaeed1f87f1..37408449ec25 100644
--- a/arch/arm/mach-pxa/include/mach/hx4700.h
+++ b/arch/arm/mach-pxa/include/mach/hx4700.h
@@ -17,6 +17,7 @@
17 17
18#define HX4700_ASIC3_GPIO_BASE NR_BUILTIN_GPIO 18#define HX4700_ASIC3_GPIO_BASE NR_BUILTIN_GPIO
19#define HX4700_EGPIO_BASE (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS) 19#define HX4700_EGPIO_BASE (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS)
20#define HX4700_NR_IRQS (IRQ_BOARD_START + 70)
20 21
21/* 22/*
22 * PXA GPIOs 23 * PXA GPIOs
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index ffc8314520f2..d372caa75dc7 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -117,48 +117,12 @@
117/* 117/*
118 * The following interrupts are for board specific purposes. Since 118 * The following interrupts are for board specific purposes. Since
119 * the kernel can only run on one machine at a time, we can re-use 119 * the kernel can only run on one machine at a time, we can re-use
120 * these. There will be 16 IRQs by default. If it is not enough, 120 * these.
121 * IRQ_BOARD_END is allowed be customized for each board, but keep 121 * By default, no board IRQ is reserved. It should be finished in
122 * the numbers within sensible limits and in descending order, so 122 * custom board since sparse IRQ is already enabled.
123 * when multiple config options are selected, the maximum will be
124 * used.
125 */ 123 */
126#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM) 124#define IRQ_BOARD_START (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM)
127 125
128#if defined(CONFIG_MACH_H4700)
129#define IRQ_BOARD_END (IRQ_BOARD_START + 70)
130#elif defined(CONFIG_MACH_ZYLONITE)
131#define IRQ_BOARD_END (IRQ_BOARD_START + 32)
132#elif defined(CONFIG_PXA_EZX)
133#define IRQ_BOARD_END (IRQ_BOARD_START + 23)
134#else
135#define IRQ_BOARD_END (IRQ_BOARD_START + 16)
136#endif
137
138/*
139 * Figure out the MAX IRQ number.
140 *
141 * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
142 * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1
143 * Otherwise, we have the standard IRQs only.
144 */
145#ifdef CONFIG_SA1111
146#define NR_IRQS (IRQ_BOARD_END + 55)
147#elif defined(CONFIG_PXA_HAVE_BOARD_IRQS)
148#define NR_IRQS (IRQ_BOARD_END)
149#else
150#define NR_IRQS (IRQ_BOARD_START) 126#define NR_IRQS (IRQ_BOARD_START)
151#endif
152
153/* add IT8152 IRQs beyond BOARD_END */
154#ifdef CONFIG_PCI_HOST_ITE8152
155#define IT8152_LAST_IRQ (IRQ_BOARD_END + 40)
156
157#if NR_IRQS < (IT8152_LAST_IRQ+1)
158#undef NR_IRQS
159#define NR_IRQS (IT8152_LAST_IRQ+1)
160#endif
161
162#endif /* CONFIG_PCI_HOST_ITE8152 */
163 127
164#endif /* __ASM_MACH_IRQS_H */ 128#endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-pxa/include/mach/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h
index 6c9b21c51322..2a5726c15e0e 100644
--- a/arch/arm/mach-pxa/include/mach/littleton.h
+++ b/arch/arm/mach-pxa/include/mach/littleton.h
@@ -10,4 +10,6 @@
10#define EXT0_GPIO_BASE (NR_BUILTIN_GPIO) 10#define EXT0_GPIO_BASE (NR_BUILTIN_GPIO)
11#define EXT0_GPIO(x) (EXT0_GPIO_BASE + (x)) 11#define EXT0_GPIO(x) (EXT0_GPIO_BASE + (x))
12 12
13#define LITTLETON_NR_IRQS (IRQ_BOARD_START + 8)
14
13#endif /* __ASM_ARCH_LITTLETON_H */ 15#endif /* __ASM_ARCH_LITTLETON_H */
diff --git a/arch/arm/mach-pxa/include/mach/lpd270.h b/arch/arm/mach-pxa/include/mach/lpd270.h
index 0e6440c81683..cd070092b6eb 100644
--- a/arch/arm/mach-pxa/include/mach/lpd270.h
+++ b/arch/arm/mach-pxa/include/mach/lpd270.h
@@ -38,5 +38,6 @@
38#define LPD270_USBC_IRQ LPD270_IRQ(2) 38#define LPD270_USBC_IRQ LPD270_IRQ(2)
39#define LPD270_ETHERNET_IRQ LPD270_IRQ(3) 39#define LPD270_ETHERNET_IRQ LPD270_IRQ(3)
40#define LPD270_AC97_IRQ LPD270_IRQ(4) 40#define LPD270_AC97_IRQ LPD270_IRQ(4)
41#define LPD270_NR_IRQS (IRQ_BOARD_START + 5)
41 42
42#endif 43#endif
diff --git a/arch/arm/mach-pxa/include/mach/lubbock.h b/arch/arm/mach-pxa/include/mach/lubbock.h
index a0d4247f08fc..2a086e8373eb 100644
--- a/arch/arm/mach-pxa/include/mach/lubbock.h
+++ b/arch/arm/mach-pxa/include/mach/lubbock.h
@@ -45,6 +45,9 @@
45#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */ 45#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */
46#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6) 46#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6)
47 47
48#define LUBBOCK_SA1111_IRQ_BASE (IRQ_BOARD_START + 16)
49#define LUBBOCK_NR_IRQS (IRQ_BOARD_START + 16 + 55)
50
48#ifndef __ASSEMBLY__ 51#ifndef __ASSEMBLY__
49extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set); 52extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set);
50#endif 53#endif
diff --git a/arch/arm/mach-pxa/include/mach/magician.h b/arch/arm/mach-pxa/include/mach/magician.h
index 20ef37d4a9a7..0a2efcf7947c 100644
--- a/arch/arm/mach-pxa/include/mach/magician.h
+++ b/arch/arm/mach-pxa/include/mach/magician.h
@@ -71,6 +71,8 @@
71#define IRQ_MAGICIAN_BT (IRQ_BOARD_START + 2) 71#define IRQ_MAGICIAN_BT (IRQ_BOARD_START + 2)
72#define IRQ_MAGICIAN_VBUS (IRQ_BOARD_START + 3) 72#define IRQ_MAGICIAN_VBUS (IRQ_BOARD_START + 3)
73 73
74#define MAGICIAN_NR_IRQS (IRQ_BOARD_START + 8)
75
74/* 76/*
75 * CPLD EGPIOs 77 * CPLD EGPIOs
76 */ 78 */
diff --git a/arch/arm/mach-pxa/include/mach/mainstone.h b/arch/arm/mach-pxa/include/mach/mainstone.h
index 86e623abd64d..4c2d11cd824d 100644
--- a/arch/arm/mach-pxa/include/mach/mainstone.h
+++ b/arch/arm/mach-pxa/include/mach/mainstone.h
@@ -134,4 +134,6 @@
134#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14) 134#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
135#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15) 135#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15)
136 136
137#define MAINSTONE_NR_IRQS (IRQ_BOARD_START + 16)
138
137#endif 139#endif
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
index 0d119d3b9221..04f7c97044f3 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h
@@ -69,6 +69,7 @@
69#define nBE0_GPIO_60 MFP_CFG(nBE0, AF0) 69#define nBE0_GPIO_60 MFP_CFG(nBE0, AF0)
70#define nBE1_GPIO_61 MFP_CFG(nBE1, AF0) 70#define nBE1_GPIO_61 MFP_CFG(nBE1, AF0)
71#define RDY_GPIO_62 MFP_CFG(RDY, AF0) 71#define RDY_GPIO_62 MFP_CFG(RDY, AF0)
72#define PMIC_INT_GPIO83 MFP_CFG_LPM(PMIC_INT, AF0, PULL_HIGH)
72 73
73/* Chip Select */ 74/* Chip Select */
74#define DF_nCS0_nCS2 MFP_CFG_LPM(DF_nCS0, AF3, PULL_HIGH) 75#define DF_nCS0_nCS2 MFP_CFG_LPM(DF_nCS0, AF3, PULL_HIGH)
@@ -92,6 +93,9 @@
92#define GPIO63_CI2C_SCL MFP_CFG_LPM(GPIO63, AF4, PULL_HIGH) 93#define GPIO63_CI2C_SCL MFP_CFG_LPM(GPIO63, AF4, PULL_HIGH)
93#define GPIO64_CI2C_SDA MFP_CFG_LPM(GPIO64, AF4, PULL_HIGH) 94#define GPIO64_CI2C_SDA MFP_CFG_LPM(GPIO64, AF4, PULL_HIGH)
94 95
96#define GPIO73_CI2C_SCL MFP_CFG_LPM(GPIO73, AF1, PULL_HIGH)
97#define GPIO74_CI2C_SDA MFP_CFG_LPM(GPIO74, AF1, PULL_HIGH)
98
95#define GPIO77_CI2C_SCL MFP_CFG_LPM(GPIO77, AF2, PULL_HIGH) 99#define GPIO77_CI2C_SCL MFP_CFG_LPM(GPIO77, AF2, PULL_HIGH)
96#define GPIO78_CI2C_SDA MFP_CFG_LPM(GPIO78, AF2, PULL_HIGH) 100#define GPIO78_CI2C_SDA MFP_CFG_LPM(GPIO78, AF2, PULL_HIGH)
97 101
@@ -345,6 +349,9 @@
345#define GPIO69_UART1_CTS MFP_CFG(GPIO69, AF2) 349#define GPIO69_UART1_CTS MFP_CFG(GPIO69, AF2)
346#define GPIO70_UART1_RTS MFP_CFG(GPIO70, AF2) 350#define GPIO70_UART1_RTS MFP_CFG(GPIO70, AF2)
347 351
352#define GPIO53_UART1_TXD MFP_CFG(GPIO53, AF2)
353#define GPIO54_UART1_RXD MFP_CFG(GPIO54, AF2)
354
348/* UART2 - BTUART */ 355/* UART2 - BTUART */
349#define GPIO91_UART2_RXD MFP_CFG(GPIO91, AF1) 356#define GPIO91_UART2_RXD MFP_CFG(GPIO91, AF1)
350#define GPIO92_UART2_TXD MFP_CFG(GPIO92, AF1) 357#define GPIO92_UART2_TXD MFP_CFG(GPIO92, AF1)
diff --git a/arch/arm/mach-pxa/include/mach/pcm027.h b/arch/arm/mach-pxa/include/mach/pcm027.h
index 04083263167e..4bac588478a8 100644
--- a/arch/arm/mach-pxa/include/mach/pcm027.h
+++ b/arch/arm/mach-pxa/include/mach/pcm027.h
@@ -30,6 +30,8 @@
30#define PCM027_MMCDET_IRQ PCM027_IRQ(2) 30#define PCM027_MMCDET_IRQ PCM027_IRQ(2)
31#define PCM027_PM_5V_IRQ PCM027_IRQ(3) 31#define PCM027_PM_5V_IRQ PCM027_IRQ(3)
32 32
33#define PCM027_NR_IRQS (IRQ_BOARD_START + 32)
34
33/* I2C RTC */ 35/* I2C RTC */
34#define PCM027_RTC_IRQ_GPIO 0 36#define PCM027_RTC_IRQ_GPIO 0
35#define PCM027_RTC_IRQ IRQ_GPIO(PCM027_RTC_IRQ_GPIO) 37#define PCM027_RTC_IRQ IRQ_GPIO(PCM027_RTC_IRQ_GPIO)
diff --git a/arch/arm/mach-pxa/include/mach/poodle.h b/arch/arm/mach-pxa/include/mach/poodle.h
index 0b3e6d051c64..83d1cfd00fc9 100644
--- a/arch/arm/mach-pxa/include/mach/poodle.h
+++ b/arch/arm/mach-pxa/include/mach/poodle.h
@@ -85,6 +85,8 @@
85#define POODLE_LOCOMO_GPIO_232VCC_ON LOCOMO_GPIO(12) 85#define POODLE_LOCOMO_GPIO_232VCC_ON LOCOMO_GPIO(12)
86#define POODLE_LOCOMO_GPIO_JK_B LOCOMO_GPIO(13) 86#define POODLE_LOCOMO_GPIO_JK_B LOCOMO_GPIO(13)
87 87
88#define POODLE_NR_IRQS (IRQ_BOARD_START + 4) /* 4 for LoCoMo */
89
88extern struct platform_device poodle_locomo_device; 90extern struct platform_device poodle_locomo_device;
89 91
90#endif /* __ASM_ARCH_POODLE_H */ 92#endif /* __ASM_ARCH_POODLE_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h b/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h
new file mode 100644
index 000000000000..9d82cb65ea56
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-u2d.h
@@ -0,0 +1,35 @@
1/*
2 * PXA3xx U2D header
3 *
4 * Copyright (C) 2010 CompuLab Ltd.
5 *
6 * Igor Grinberg <grinberg@compulab.co.il>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#ifndef __PXA310_U2D__
13#define __PXA310_U2D__
14
15#include <linux/usb/ulpi.h>
16
17struct pxa3xx_u2d_platform_data {
18
19#define ULPI_SER_6PIN (1 << 0)
20#define ULPI_SER_3PIN (1 << 1)
21 unsigned int ulpi_mode;
22
23 int (*init)(struct device *);
24 void (*exit)(struct device *);
25};
26
27
28/* Start PXA3xx U2D host */
29int pxa3xx_u2d_start_hc(struct usb_bus *host);
30/* Stop PXA3xx U2D host */
31void pxa3xx_u2d_stop_hc(struct usb_bus *host);
32
33extern void pxa3xx_set_u2d_info(struct pxa3xx_u2d_platform_data *info);
34
35#endif /* __PXA310_U2D__ */
diff --git a/arch/arm/mach-pxa/include/mach/tosa.h b/arch/arm/mach-pxa/include/mach/tosa.h
index 1bbd1f2e4beb..1272c4b56ceb 100644
--- a/arch/arm/mach-pxa/include/mach/tosa.h
+++ b/arch/arm/mach-pxa/include/mach/tosa.h
@@ -20,6 +20,7 @@
20/* Jacket Scoop */ 20/* Jacket Scoop */
21#define TOSA_SCOOP_PHYS (PXA_CS5_PHYS + 0x00800000) 21#define TOSA_SCOOP_PHYS (PXA_CS5_PHYS + 0x00800000)
22 22
23#define TOSA_NR_IRQS (IRQ_BOARD_START + TC6393XB_NR_IRQS)
23/* 24/*
24 * SCOOP2 internal GPIOs 25 * SCOOP2 internal GPIOs
25 */ 26 */
diff --git a/arch/arm/mach-pxa/include/mach/zeus.h b/arch/arm/mach-pxa/include/mach/zeus.h
index 6e119976003e..faa408ab7ad7 100644
--- a/arch/arm/mach-pxa/include/mach/zeus.h
+++ b/arch/arm/mach-pxa/include/mach/zeus.h
@@ -15,6 +15,8 @@
15#ifndef _MACH_ZEUS_H 15#ifndef _MACH_ZEUS_H
16#define _MACH_ZEUS_H 16#define _MACH_ZEUS_H
17 17
18#define ZEUS_NR_IRQS (IRQ_BOARD_START + 48)
19
18/* Physical addresses */ 20/* Physical addresses */
19#define ZEUS_FLASH_PHYS PXA_CS0_PHYS 21#define ZEUS_FLASH_PHYS PXA_CS0_PHYS
20#define ZEUS_ETH0_PHYS PXA_CS1_PHYS 22#define ZEUS_ETH0_PHYS PXA_CS1_PHYS
diff --git a/arch/arm/mach-pxa/include/mach/zylonite.h b/arch/arm/mach-pxa/include/mach/zylonite.h
index 9edf645368d6..ea24998b923c 100644
--- a/arch/arm/mach-pxa/include/mach/zylonite.h
+++ b/arch/arm/mach-pxa/include/mach/zylonite.h
@@ -5,6 +5,8 @@
5 5
6#define EXT_GPIO(x) (128 + (x)) 6#define EXT_GPIO(x) (128 + (x))
7 7
8#define ZYLONITE_NR_IRQS (IRQ_BOARD_START + 32)
9
8/* the following variables are processor specific and initialized 10/* the following variables are processor specific and initialized
9 * by the corresponding zylonite_pxa3xx_init() 11 * by the corresponding zylonite_pxa3xx_init()
10 */ 12 */
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 9b9046185b00..41aa89e35772 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -43,7 +43,7 @@
43#include <mach/pxafb.h> 43#include <mach/pxafb.h>
44#include <mach/mmc.h> 44#include <mach/mmc.h>
45#include <mach/pxa2xx_spi.h> 45#include <mach/pxa2xx_spi.h>
46#include <mach/pxa27x_keypad.h> 46#include <plat/pxa27x_keypad.h>
47#include <mach/littleton.h> 47#include <mach/littleton.h>
48#include <plat/i2c.h> 48#include <plat/i2c.h>
49#include <plat/pxa3xx_nand.h> 49#include <plat/pxa3xx_nand.h>
@@ -437,10 +437,9 @@ static void __init littleton_init(void)
437} 437}
438 438
439MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)") 439MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)")
440 .phys_io = 0x40000000,
441 .boot_params = 0xa0000100, 440 .boot_params = 0xa0000100,
442 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
443 .map_io = pxa_map_io, 441 .map_io = pxa_map_io,
442 .nr_irqs = LITTLETON_NR_IRQS,
444 .init_irq = pxa3xx_init_irq, 443 .init_irq = pxa3xx_init_irq,
445 .timer = &pxa_timer, 444 .timer = &pxa_timer,
446 .init_machine = littleton_init, 445 .init_machine = littleton_init,
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index d279507fc748..623af0232a54 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -505,10 +505,9 @@ static void __init lpd270_map_io(void)
505 505
506MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine") 506MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
507 /* Maintainer: Peter Barada */ 507 /* Maintainer: Peter Barada */
508 .phys_io = 0x40000000,
509 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
510 .boot_params = 0xa0000100, 508 .boot_params = 0xa0000100,
511 .map_io = lpd270_map_io, 509 .map_io = lpd270_map_io,
510 .nr_irqs = LPD270_NR_IRQS,
512 .init_irq = lpd270_init_irq, 511 .init_irq = lpd270_init_irq,
513 .timer = &pxa_timer, 512 .timer = &pxa_timer,
514 .init_machine = lpd270_init, 513 .init_machine = lpd270_init,
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 330c3282856e..1499493cd070 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -229,7 +229,7 @@ static struct resource sa1111_resources[] = {
229}; 229};
230 230
231static struct sa1111_platform_data sa1111_info = { 231static struct sa1111_platform_data sa1111_info = {
232 .irq_base = IRQ_BOARD_END, 232 .irq_base = LUBBOCK_SA1111_IRQ_BASE,
233}; 233};
234 234
235static struct platform_device sa1111_device = { 235static struct platform_device sa1111_device = {
@@ -557,9 +557,8 @@ static void __init lubbock_map_io(void)
557 557
558MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)") 558MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)")
559 /* Maintainer: MontaVista Software Inc. */ 559 /* Maintainer: MontaVista Software Inc. */
560 .phys_io = 0x40000000,
561 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
562 .map_io = lubbock_map_io, 560 .map_io = lubbock_map_io,
561 .nr_irqs = LUBBOCK_NR_IRQS,
563 .init_irq = lubbock_init_irq, 562 .init_irq = lubbock_init_irq,
564 .timer = &pxa_timer, 563 .timer = &pxa_timer,
565 .init_machine = lubbock_init, 564 .init_machine = lubbock_init,
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index e81dd0c8e40d..90663760307a 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -764,10 +764,9 @@ static void __init magician_init(void)
764 764
765 765
766MACHINE_START(MAGICIAN, "HTC Magician") 766MACHINE_START(MAGICIAN, "HTC Magician")
767 .phys_io = 0x40000000,
768 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
769 .boot_params = 0xa0000100, 767 .boot_params = 0xa0000100,
770 .map_io = pxa_map_io, 768 .map_io = pxa_map_io,
769 .nr_irqs = MAGICIAN_NR_IRQS,
771 .init_irq = pxa27x_init_irq, 770 .init_irq = pxa27x_init_irq,
772 .init_machine = magician_init, 771 .init_machine = magician_init,
773 .timer = &pxa_timer, 772 .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 5543c64da9ef..a980a5c93e49 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -50,7 +50,7 @@
50#include <mach/mmc.h> 50#include <mach/mmc.h>
51#include <mach/irda.h> 51#include <mach/irda.h>
52#include <mach/ohci.h> 52#include <mach/ohci.h>
53#include <mach/pxa27x_keypad.h> 53#include <plat/pxa27x_keypad.h>
54 54
55#include "generic.h" 55#include "generic.h"
56#include "devices.h" 56#include "devices.h"
@@ -624,10 +624,9 @@ static void __init mainstone_map_io(void)
624 624
625MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)") 625MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
626 /* Maintainer: MontaVista Software Inc. */ 626 /* Maintainer: MontaVista Software Inc. */
627 .phys_io = 0x40000000,
628 .boot_params = 0xa0000100, /* BLOB boot parameter setting */ 627 .boot_params = 0xa0000100, /* BLOB boot parameter setting */
629 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
630 .map_io = mainstone_map_io, 628 .map_io = mainstone_map_io,
629 .nr_irqs = MAINSTONE_NR_IRQS,
631 .init_irq = mainstone_init_irq, 630 .init_irq = mainstone_init_irq,
632 .timer = &pxa_timer, 631 .timer = &pxa_timer,
633 .init_machine = mainstone_init, 632 .init_machine = mainstone_init,
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index dc66942ef9ab..0c31fabfc7fd 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -45,7 +45,7 @@
45 45
46#include <mach/pxa27x.h> 46#include <mach/pxa27x.h>
47#include <mach/regs-rtc.h> 47#include <mach/regs-rtc.h>
48#include <mach/pxa27x_keypad.h> 48#include <plat/pxa27x_keypad.h>
49#include <mach/pxafb.h> 49#include <mach/pxafb.h>
50#include <mach/mmc.h> 50#include <mach/mmc.h>
51#include <mach/udc.h> 51#include <mach/udc.h>
@@ -819,8 +819,6 @@ static void mioa701_machine_exit(void)
819} 819}
820 820
821MACHINE_START(MIOA701, "MIO A701") 821MACHINE_START(MIOA701, "MIO A701")
822 .phys_io = 0x40000000,
823 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
824 .boot_params = 0xa0000100, 822 .boot_params = 0xa0000100,
825 .map_io = &pxa_map_io, 823 .map_io = &pxa_map_io,
826 .init_irq = &pxa27x_init_irq, 824 .init_irq = &pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c
index 6d4503927a76..116167aaba68 100644
--- a/arch/arm/mach-pxa/mp900.c
+++ b/arch/arm/mach-pxa/mp900.c
@@ -92,9 +92,7 @@ static void __init mp900c_init(void)
92 92
93/* Maintainer - Michael Petchkovsky <mkpetch@internode.on.net> */ 93/* Maintainer - Michael Petchkovsky <mkpetch@internode.on.net> */
94MACHINE_START(NEC_MP900, "MobilePro900/C") 94MACHINE_START(NEC_MP900, "MobilePro900/C")
95 .phys_io = 0x40000000,
96 .boot_params = 0xa0220100, 95 .boot_params = 0xa0220100,
97 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
98 .timer = &pxa_timer, 96 .timer = &pxa_timer,
99 .map_io = pxa_map_io, 97 .map_io = pxa_map_io,
100 .init_irq = pxa25x_init_irq, 98 .init_irq = pxa25x_init_irq,
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index 91038eeafe44..ce092c521e6d 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -39,7 +39,7 @@
39#include <mach/mmc.h> 39#include <mach/mmc.h>
40#include <mach/pxafb.h> 40#include <mach/pxafb.h>
41#include <mach/irda.h> 41#include <mach/irda.h>
42#include <mach/pxa27x_keypad.h> 42#include <plat/pxa27x_keypad.h>
43#include <mach/palmasoc.h> 43#include <mach/palmasoc.h>
44#include <mach/palm27x.h> 44#include <mach/palm27x.h>
45 45
@@ -343,8 +343,6 @@ static void __init palmld_init(void)
343} 343}
344 344
345MACHINE_START(PALMLD, "Palm LifeDrive") 345MACHINE_START(PALMLD, "Palm LifeDrive")
346 .phys_io = PALMLD_PHYS_IO_START,
347 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
348 .boot_params = 0xa0000100, 346 .boot_params = 0xa0000100,
349 .map_io = palmld_map_io, 347 .map_io = palmld_map_io,
350 .init_irq = pxa27x_init_irq, 348 .init_irq = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 1c281995f658..862da812cd10 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -39,7 +39,7 @@
39#include <mach/mmc.h> 39#include <mach/mmc.h>
40#include <mach/pxafb.h> 40#include <mach/pxafb.h>
41#include <mach/irda.h> 41#include <mach/irda.h>
42#include <mach/pxa27x_keypad.h> 42#include <plat/pxa27x_keypad.h>
43#include <mach/udc.h> 43#include <mach/udc.h>
44#include <mach/palmasoc.h> 44#include <mach/palmasoc.h>
45#include <mach/palm27x.h> 45#include <mach/palm27x.h>
@@ -202,8 +202,6 @@ static void __init palmt5_init(void)
202} 202}
203 203
204MACHINE_START(PALMT5, "Palm Tungsten|T5") 204MACHINE_START(PALMT5, "Palm Tungsten|T5")
205 .phys_io = PALMT5_PHYS_IO_START,
206 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
207 .boot_params = 0xa0000100, 205 .boot_params = 0xa0000100,
208 .map_io = pxa_map_io, 206 .map_io = pxa_map_io,
209 .reserve = palmt5_reserve, 207 .reserve = palmt5_reserve,
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c
index ce1104d1bc17..2131d5860919 100644
--- a/arch/arm/mach-pxa/palmtc.c
+++ b/arch/arm/mach-pxa/palmtc.c
@@ -412,9 +412,7 @@ static void __init palmtc_init(void)
412}; 412};
413 413
414MACHINE_START(PALMTC, "Palm Tungsten|C") 414MACHINE_START(PALMTC, "Palm Tungsten|C")
415 .phys_io = 0x40000000,
416 .boot_params = 0xa0000100, 415 .boot_params = 0xa0000100,
417 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
418 .map_io = pxa_map_io, 416 .map_io = pxa_map_io,
419 .init_irq = pxa25x_init_irq, 417 .init_irq = pxa25x_init_irq,
420 .timer = &pxa_timer, 418 .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index 93c11a0438d5..a9dae7bc35d9 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -373,8 +373,6 @@ static void __init palmte2_init(void)
373} 373}
374 374
375MACHINE_START(PALMTE2, "Palm Tungsten|E2") 375MACHINE_START(PALMTE2, "Palm Tungsten|E2")
376 .phys_io = 0x40000000,
377 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
378 .boot_params = 0xa0000100, 376 .boot_params = 0xa0000100,
379 .map_io = pxa_map_io, 377 .map_io = pxa_map_io,
380 .init_irq = pxa25x_init_irq, 378 .init_irq = pxa25x_init_irq,
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index 52defd5e42e5..00e2d7ba84ed 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -39,7 +39,7 @@
39#include <mach/mmc.h> 39#include <mach/mmc.h>
40#include <mach/pxafb.h> 40#include <mach/pxafb.h>
41#include <mach/irda.h> 41#include <mach/irda.h>
42#include <mach/pxa27x_keypad.h> 42#include <plat/pxa27x_keypad.h>
43#include <mach/udc.h> 43#include <mach/udc.h>
44#include <mach/ohci.h> 44#include <mach/ohci.h>
45#include <mach/pxa2xx-regs.h> 45#include <mach/pxa2xx-regs.h>
@@ -441,8 +441,6 @@ static void __init centro_init(void)
441} 441}
442 442
443MACHINE_START(TREO680, "Palm Treo 680") 443MACHINE_START(TREO680, "Palm Treo 680")
444 .phys_io = TREO_PHYS_IO_START,
445 .io_pg_offst = io_p2v(0x40000000),
446 .boot_params = 0xa0000100, 444 .boot_params = 0xa0000100,
447 .map_io = pxa_map_io, 445 .map_io = pxa_map_io,
448 .reserve = treo_reserve, 446 .reserve = treo_reserve,
@@ -452,8 +450,6 @@ MACHINE_START(TREO680, "Palm Treo 680")
452MACHINE_END 450MACHINE_END
453 451
454MACHINE_START(CENTRO, "Palm Centro 685") 452MACHINE_START(CENTRO, "Palm Centro 685")
455 .phys_io = TREO_PHYS_IO_START,
456 .io_pg_offst = io_p2v(0x40000000),
457 .boot_params = 0xa0000100, 453 .boot_params = 0xa0000100,
458 .map_io = pxa_map_io, 454 .map_io = pxa_map_io,
459 .reserve = treo_reserve, 455 .reserve = treo_reserve,
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 144dc2b6911f..d2060a1d1d68 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -43,7 +43,7 @@
43#include <mach/mmc.h> 43#include <mach/mmc.h>
44#include <mach/pxafb.h> 44#include <mach/pxafb.h>
45#include <mach/irda.h> 45#include <mach/irda.h>
46#include <mach/pxa27x_keypad.h> 46#include <plat/pxa27x_keypad.h>
47#include <mach/udc.h> 47#include <mach/udc.h>
48#include <mach/palmasoc.h> 48#include <mach/palmasoc.h>
49#include <mach/palm27x.h> 49#include <mach/palm27x.h>
@@ -363,8 +363,6 @@ static void __init palmtx_init(void)
363} 363}
364 364
365MACHINE_START(PALMTX, "Palm T|X") 365MACHINE_START(PALMTX, "Palm T|X")
366 .phys_io = PALMTX_PHYS_IO_START,
367 .io_pg_offst = io_p2v(0x40000000),
368 .boot_params = 0xa0000100, 366 .boot_params = 0xa0000100,
369 .map_io = palmtx_map_io, 367 .map_io = palmtx_map_io,
370 .init_irq = pxa27x_init_irq, 368 .init_irq = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index 87e4b1044e0b..af6203fbca9c 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -41,7 +41,7 @@
41#include <mach/mmc.h> 41#include <mach/mmc.h>
42#include <mach/pxafb.h> 42#include <mach/pxafb.h>
43#include <mach/irda.h> 43#include <mach/irda.h>
44#include <mach/pxa27x_keypad.h> 44#include <plat/pxa27x_keypad.h>
45#include <mach/udc.h> 45#include <mach/udc.h>
46#include <mach/palmasoc.h> 46#include <mach/palmasoc.h>
47#include <mach/palm27x.h> 47#include <mach/palm27x.h>
@@ -279,8 +279,6 @@ static void __init palmz72_init(void)
279} 279}
280 280
281MACHINE_START(PALMZ72, "Palm Zire72") 281MACHINE_START(PALMZ72, "Palm Zire72")
282 .phys_io = 0x40000000,
283 .io_pg_offst = io_p2v(0x40000000),
284 .boot_params = 0xa0000100, 282 .boot_params = 0xa0000100,
285 .map_io = pxa_map_io, 283 .map_io = pxa_map_io,
286 .init_irq = pxa27x_init_irq, 284 .init_irq = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index 2190af066470..c77e8f30a439 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -259,9 +259,8 @@ static void __init pcm027_map_io(void)
259MACHINE_START(PCM027, "Phytec Messtechnik GmbH phyCORE-PXA270") 259MACHINE_START(PCM027, "Phytec Messtechnik GmbH phyCORE-PXA270")
260 /* Maintainer: Pengutronix */ 260 /* Maintainer: Pengutronix */
261 .boot_params = 0xa0000100, 261 .boot_params = 0xa0000100,
262 .phys_io = 0x40000000,
263 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
264 .map_io = pcm027_map_io, 262 .map_io = pcm027_map_io,
263 .nr_irqs = PCM027_NR_IRQS,
265 .init_irq = pxa27x_init_irq, 264 .init_irq = pxa27x_init_irq,
266 .timer = &pxa_timer, 265 .timer = &pxa_timer,
267 .init_machine = pcm027_init, 266 .init_machine = pcm027_init,
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 55e8fcde0141..93a191c889df 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -465,10 +465,9 @@ static void __init fixup_poodle(struct machine_desc *desc,
465} 465}
466 466
467MACHINE_START(POODLE, "SHARP Poodle") 467MACHINE_START(POODLE, "SHARP Poodle")
468 .phys_io = 0x40000000,
469 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
470 .fixup = fixup_poodle, 468 .fixup = fixup_poodle,
471 .map_io = pxa_map_io, 469 .map_io = pxa_map_io,
470 .nr_irqs = POODLE_NR_IRQS, /* 4 for LoCoMo */
472 .init_irq = pxa25x_init_irq, 471 .init_irq = pxa25x_init_irq,
473 .timer = &pxa_timer, 472 .timer = &pxa_timer,
474 .init_machine = poodle_init, 473 .init_machine = poodle_init,
diff --git a/arch/arm/mach-pxa/pxa3xx-ulpi.c b/arch/arm/mach-pxa/pxa3xx-ulpi.c
new file mode 100644
index 000000000000..ce7168b233e2
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa3xx-ulpi.c
@@ -0,0 +1,400 @@
1/*
2 * linux/arch/arm/mach-pxa/pxa3xx-ulpi.c
3 *
4 * code specific to pxa3xx aka Monahans
5 *
6 * Copyright (C) 2010 CompuLab Ltd.
7 *
8 * 2010-13-07: Igor Grinberg <grinberg@compulab.co.il>
9 * initial version: pxa310 USB Host mode support
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/slab.h>
19#include <linux/device.h>
20#include <linux/platform_device.h>
21#include <linux/err.h>
22#include <linux/io.h>
23#include <linux/delay.h>
24#include <linux/clk.h>
25#include <linux/usb.h>
26#include <linux/usb/otg.h>
27
28#include <mach/hardware.h>
29#include <mach/regs-u2d.h>
30#include <mach/pxa3xx-u2d.h>
31
32struct pxa3xx_u2d_ulpi {
33 struct clk *clk;
34 void __iomem *mmio_base;
35
36 struct otg_transceiver *otg;
37 unsigned int ulpi_mode;
38};
39
40static struct pxa3xx_u2d_ulpi *u2d;
41
42static inline u32 u2d_readl(u32 reg)
43{
44 return __raw_readl(u2d->mmio_base + reg);
45}
46
47static inline void u2d_writel(u32 reg, u32 val)
48{
49 __raw_writel(val, u2d->mmio_base + reg);
50}
51
52#if defined(CONFIG_PXA310_ULPI)
53enum u2d_ulpi_phy_mode {
54 SYNCH = 0,
55 CARKIT = (1 << 0),
56 SER_3PIN = (1 << 1),
57 SER_6PIN = (1 << 2),
58 LOWPOWER = (1 << 3),
59};
60
61static inline enum u2d_ulpi_phy_mode pxa310_ulpi_get_phymode(void)
62{
63 return (u2d_readl(U2DOTGUSR) >> 28) & 0xF;
64}
65
66static int pxa310_ulpi_poll(void)
67{
68 int timeout = 50000;
69
70 while (timeout--) {
71 if (!(u2d_readl(U2DOTGUCR) & U2DOTGUCR_RUN))
72 return 0;
73
74 cpu_relax();
75 }
76
77 pr_warning("%s: ULPI access timed out!\n", __func__);
78
79 return -ETIMEDOUT;
80}
81
82static int pxa310_ulpi_read(struct otg_transceiver *otg, u32 reg)
83{
84 int err;
85
86 if (pxa310_ulpi_get_phymode() != SYNCH) {
87 pr_warning("%s: PHY is not in SYNCH mode!\n", __func__);
88 return -EBUSY;
89 }
90
91 u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | U2DOTGUCR_RNW | (reg << 16));
92 msleep(5);
93
94 err = pxa310_ulpi_poll();
95 if (err)
96 return err;
97
98 return u2d_readl(U2DOTGUCR) & U2DOTGUCR_RDATA;
99}
100
101static int pxa310_ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
102{
103 if (pxa310_ulpi_get_phymode() != SYNCH) {
104 pr_warning("%s: PHY is not in SYNCH mode!\n", __func__);
105 return -EBUSY;
106 }
107
108 u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | (reg << 16) | (val << 8));
109 msleep(5);
110
111 return pxa310_ulpi_poll();
112}
113
114struct otg_io_access_ops pxa310_ulpi_access_ops = {
115 .read = pxa310_ulpi_read,
116 .write = pxa310_ulpi_write,
117};
118
119static void pxa310_otg_transceiver_rtsm(void)
120{
121 u32 u2dotgcr;
122
123 /* put PHY to sync mode */
124 u2dotgcr = u2d_readl(U2DOTGCR);
125 u2dotgcr |= U2DOTGCR_RTSM | U2DOTGCR_UTMID;
126 u2d_writel(U2DOTGCR, u2dotgcr);
127 msleep(10);
128
129 /* setup OTG sync mode */
130 u2dotgcr = u2d_readl(U2DOTGCR);
131 u2dotgcr |= U2DOTGCR_ULAF;
132 u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF);
133 u2d_writel(U2DOTGCR, u2dotgcr);
134}
135
136static int pxa310_start_otg_host_transcvr(struct usb_bus *host)
137{
138 int err;
139
140 pxa310_otg_transceiver_rtsm();
141
142 err = otg_init(u2d->otg);
143 if (err) {
144 pr_err("OTG transceiver init failed");
145 return err;
146 }
147
148 err = otg_set_vbus(u2d->otg, 1);
149 if (err) {
150 pr_err("OTG transceiver VBUS set failed");
151 return err;
152 }
153
154 err = otg_set_host(u2d->otg, host);
155 if (err)
156 pr_err("OTG transceiver Host mode set failed");
157
158 return err;
159}
160
161static int pxa310_start_otg_hc(struct usb_bus *host)
162{
163 u32 u2dotgcr;
164 int err;
165
166 /* disable USB device controller */
167 u2d_writel(U2DCR, u2d_readl(U2DCR) & ~U2DCR_UDE);
168 u2d_writel(U2DOTGCR, u2d_readl(U2DOTGCR) | U2DOTGCR_UTMID);
169 u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F);
170
171 err = pxa310_start_otg_host_transcvr(host);
172 if (err)
173 return err;
174
175 /* set xceiver mode */
176 if (u2d->ulpi_mode & ULPI_IC_6PIN_SERIAL)
177 u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) & ~U2DP3CR_P2SS);
178 else if (u2d->ulpi_mode & ULPI_IC_3PIN_SERIAL)
179 u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) | U2DP3CR_P2SS);
180
181 /* start OTG host controller */
182 u2dotgcr = u2d_readl(U2DOTGCR) | U2DOTGCR_SMAF;
183 u2d_writel(U2DOTGCR, u2dotgcr & ~(U2DOTGCR_ULAF | U2DOTGCR_CKAF));
184
185 return 0;
186}
187
188static void pxa310_stop_otg_hc(void)
189{
190 pxa310_otg_transceiver_rtsm();
191
192 otg_set_host(u2d->otg, NULL);
193 otg_set_vbus(u2d->otg, 0);
194 otg_shutdown(u2d->otg);
195}
196
197static void pxa310_u2d_setup_otg_hc(void)
198{
199 u32 u2dotgcr;
200
201 u2dotgcr = u2d_readl(U2DOTGCR);
202 u2dotgcr |= U2DOTGCR_ULAF | U2DOTGCR_UTMID;
203 u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF);
204 u2d_writel(U2DOTGCR, u2dotgcr);
205 msleep(5);
206 u2d_writel(U2DOTGCR, u2dotgcr | U2DOTGCR_ULE);
207 msleep(5);
208 u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F);
209}
210
211static int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata)
212{
213 unsigned int ulpi_mode = ULPI_OTG_DRVVBUS;
214
215 if (pdata) {
216 if (pdata->ulpi_mode & ULPI_SER_6PIN)
217 ulpi_mode |= ULPI_IC_6PIN_SERIAL;
218 else if (pdata->ulpi_mode & ULPI_SER_3PIN)
219 ulpi_mode |= ULPI_IC_3PIN_SERIAL;
220 }
221
222 u2d->ulpi_mode = ulpi_mode;
223
224 u2d->otg = otg_ulpi_create(&pxa310_ulpi_access_ops, ulpi_mode);
225 if (!u2d->otg)
226 return -ENOMEM;
227
228 u2d->otg->io_priv = u2d->mmio_base;
229
230 return 0;
231}
232
233static void pxa310_otg_exit(void)
234{
235 kfree(u2d->otg);
236}
237#else
238static inline void pxa310_u2d_setup_otg_hc(void) {}
239static inline int pxa310_start_otg_hc(struct usb_bus *host)
240{
241 return 0;
242}
243static inline void pxa310_stop_otg_hc(void) {}
244static inline int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata)
245{
246 return 0;
247}
248static inline void pxa310_otg_exit(void) {}
249#endif /* CONFIG_PXA310_ULPI */
250
251int pxa3xx_u2d_start_hc(struct usb_bus *host)
252{
253 int err = 0;
254
255 /* In case the PXA3xx ULPI isn't used, do nothing. */
256 if (!u2d)
257 return 0;
258
259 clk_enable(u2d->clk);
260
261 if (cpu_is_pxa310()) {
262 pxa310_u2d_setup_otg_hc();
263 err = pxa310_start_otg_hc(host);
264 }
265
266 return err;
267}
268
269void pxa3xx_u2d_stop_hc(struct usb_bus *host)
270{
271 /* In case the PXA3xx ULPI isn't used, do nothing. */
272 if (!u2d)
273 return;
274
275 if (cpu_is_pxa310())
276 pxa310_stop_otg_hc();
277
278 clk_disable(u2d->clk);
279}
280
281static int pxa3xx_u2d_probe(struct platform_device *pdev)
282{
283 struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data;
284 struct resource *r;
285 int err;
286
287 u2d = kzalloc(sizeof(struct pxa3xx_u2d_ulpi), GFP_KERNEL);
288 if (!u2d) {
289 dev_err(&pdev->dev, "failed to allocate memory\n");
290 return -ENOMEM;
291 }
292
293 u2d->clk = clk_get(&pdev->dev, NULL);
294 if (IS_ERR(u2d->clk)) {
295 dev_err(&pdev->dev, "failed to get u2d clock\n");
296 err = PTR_ERR(u2d->clk);
297 goto err_free_mem;
298 }
299
300 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
301 if (!r) {
302 dev_err(&pdev->dev, "no IO memory resource defined\n");
303 err = -ENODEV;
304 goto err_put_clk;
305 }
306
307 r = request_mem_region(r->start, resource_size(r), pdev->name);
308 if (!r) {
309 dev_err(&pdev->dev, "failed to request memory resource\n");
310 err = -EBUSY;
311 goto err_put_clk;
312 }
313
314 u2d->mmio_base = ioremap(r->start, resource_size(r));
315 if (!u2d->mmio_base) {
316 dev_err(&pdev->dev, "ioremap() failed\n");
317 err = -ENODEV;
318 goto err_free_res;
319 }
320
321 if (pdata->init) {
322 err = pdata->init(&pdev->dev);
323 if (err)
324 goto err_free_io;
325 }
326
327 /* Only PXA310 U2D has OTG functionality */
328 if (cpu_is_pxa310()) {
329 err = pxa310_otg_init(pdata);
330 if (err)
331 goto err_free_plat;
332 }
333
334 platform_set_drvdata(pdev, &u2d);
335
336 return 0;
337
338err_free_plat:
339 if (pdata->exit)
340 pdata->exit(&pdev->dev);
341err_free_io:
342 iounmap(u2d->mmio_base);
343err_free_res:
344 release_mem_region(r->start, resource_size(r));
345err_put_clk:
346 clk_put(u2d->clk);
347err_free_mem:
348 kfree(u2d);
349 return err;
350}
351
352static int pxa3xx_u2d_remove(struct platform_device *pdev)
353{
354 struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data;
355 struct resource *r;
356
357 if (cpu_is_pxa310()) {
358 pxa310_stop_otg_hc();
359 pxa310_otg_exit();
360 }
361
362 if (pdata->exit)
363 pdata->exit(&pdev->dev);
364
365 platform_set_drvdata(pdev, NULL);
366 iounmap(u2d->mmio_base);
367 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
368 release_mem_region(r->start, resource_size(r));
369
370 clk_put(u2d->clk);
371
372 kfree(u2d);
373
374 return 0;
375}
376
377static struct platform_driver pxa3xx_u2d_ulpi_driver = {
378 .driver = {
379 .name = "pxa3xx-u2d",
380 .owner = THIS_MODULE,
381 },
382 .probe = pxa3xx_u2d_probe,
383 .remove = pxa3xx_u2d_remove,
384};
385
386static int pxa3xx_u2d_ulpi_init(void)
387{
388 return platform_driver_register(&pxa3xx_u2d_ulpi_driver);
389}
390module_init(pxa3xx_u2d_ulpi_init);
391
392static void __exit pxa3xx_u2d_ulpi_exit(void)
393{
394 platform_driver_unregister(&pxa3xx_u2d_ulpi_driver);
395}
396module_exit(pxa3xx_u2d_ulpi_exit);
397
398MODULE_DESCRIPTION("PXA3xx U2D ULPI driver");
399MODULE_AUTHOR("Igor Grinberg");
400MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index fa0014847c71..c85c3a7abd31 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -98,23 +98,6 @@ unsigned int pxa3xx_get_clk_frequency_khz(int info)
98 return CLK / 1000; 98 return CLK / 1000;
99} 99}
100 100
101/*
102 * Return the current static memory controller clock frequency
103 * in units of 10kHz
104 */
105unsigned int pxa3xx_get_memclk_frequency_10khz(void)
106{
107 unsigned long acsr;
108 unsigned int smcfs, clk = 0;
109
110 acsr = ACSR;
111
112 smcfs = (acsr >> 23) & 0x7;
113 clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
114
115 return (clk / 10000);
116}
117
118void pxa3xx_clear_reset_status(unsigned int mask) 101void pxa3xx_clear_reset_status(unsigned int mask)
119{ 102{
120 /* RESET_STATUS_* has a 1:1 mapping with ARSR */ 103 /* RESET_STATUS_* has a 1:1 mapping with ARSR */
@@ -265,7 +248,7 @@ static struct clk_lookup pxa3xx_clkregs[] = {
265 INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL), 248 INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
266 INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL), 249 INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
267 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL), 250 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
268 INIT_CLKREG(&clk_pxa3xx_u2d, NULL, "U2DCLK"), 251 INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
269 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL), 252 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
270 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL), 253 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
271 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL), 254 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c
index 064292008288..7d29dd3af79d 100644
--- a/arch/arm/mach-pxa/pxa930.c
+++ b/arch/arm/mach-pxa/pxa930.c
@@ -192,7 +192,7 @@ static struct mfp_addr_map pxa935_mfp_addr_map[] __initdata = {
192 192
193static int __init pxa930_init(void) 193static int __init pxa930_init(void)
194{ 194{
195 if (cpu_is_pxa930() || cpu_is_pxa935()) { 195 if (cpu_is_pxa930() || cpu_is_pxa935() || cpu_is_pxa950()) {
196 mfp_init_base(io_p2v(MFPR_BASE)); 196 mfp_init_base(io_p2v(MFPR_BASE));
197 mfp_init_addr(pxa930_mfp_addr_map); 197 mfp_init_addr(pxa930_mfp_addr_map);
198 } 198 }
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index 67e04f4e07c1..4121d03ea2c3 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -1083,8 +1083,6 @@ static void __init raumfeld_speaker_init(void)
1083 1083
1084#ifdef CONFIG_MACH_RAUMFELD_RC 1084#ifdef CONFIG_MACH_RAUMFELD_RC
1085MACHINE_START(RAUMFELD_RC, "Raumfeld Controller") 1085MACHINE_START(RAUMFELD_RC, "Raumfeld Controller")
1086 .phys_io = 0x40000000,
1087 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
1088 .boot_params = RAUMFELD_SDRAM_BASE + 0x100, 1086 .boot_params = RAUMFELD_SDRAM_BASE + 0x100,
1089 .init_machine = raumfeld_controller_init, 1087 .init_machine = raumfeld_controller_init,
1090 .map_io = pxa_map_io, 1088 .map_io = pxa_map_io,
@@ -1095,8 +1093,6 @@ MACHINE_END
1095 1093
1096#ifdef CONFIG_MACH_RAUMFELD_CONNECTOR 1094#ifdef CONFIG_MACH_RAUMFELD_CONNECTOR
1097MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector") 1095MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector")
1098 .phys_io = 0x40000000,
1099 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
1100 .boot_params = RAUMFELD_SDRAM_BASE + 0x100, 1096 .boot_params = RAUMFELD_SDRAM_BASE + 0x100,
1101 .init_machine = raumfeld_connector_init, 1097 .init_machine = raumfeld_connector_init,
1102 .map_io = pxa_map_io, 1098 .map_io = pxa_map_io,
@@ -1107,8 +1103,6 @@ MACHINE_END
1107 1103
1108#ifdef CONFIG_MACH_RAUMFELD_SPEAKER 1104#ifdef CONFIG_MACH_RAUMFELD_SPEAKER
1109MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker") 1105MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker")
1110 .phys_io = 0x40000000,
1111 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
1112 .boot_params = RAUMFELD_SDRAM_BASE + 0x100, 1106 .boot_params = RAUMFELD_SDRAM_BASE + 0x100,
1113 .init_machine = raumfeld_speaker_init, 1107 .init_machine = raumfeld_speaker_init,
1114 .map_io = pxa_map_io, 1108 .map_io = pxa_map_io,
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index 115b6f234bdd..4b521e045d75 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -596,9 +596,7 @@ static void __init saar_init(void)
596 596
597MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)") 597MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)")
598 /* Maintainer: Eric Miao <eric.miao@marvell.com> */ 598 /* Maintainer: Eric Miao <eric.miao@marvell.com> */
599 .phys_io = 0x40000000,
600 .boot_params = 0xa0000100, 599 .boot_params = 0xa0000100,
601 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
602 .map_io = pxa_map_io, 600 .map_io = pxa_map_io,
603 .init_irq = pxa3xx_init_irq, 601 .init_irq = pxa3xx_init_irq,
604 .timer = &pxa_timer, 602 .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 1cd99cb87bb1..f736119f1ebf 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -979,8 +979,6 @@ static void __init spitz_fixup(struct machine_desc *desc,
979 979
980#ifdef CONFIG_MACH_SPITZ 980#ifdef CONFIG_MACH_SPITZ
981MACHINE_START(SPITZ, "SHARP Spitz") 981MACHINE_START(SPITZ, "SHARP Spitz")
982 .phys_io = 0x40000000,
983 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
984 .fixup = spitz_fixup, 982 .fixup = spitz_fixup,
985 .map_io = pxa_map_io, 983 .map_io = pxa_map_io,
986 .init_irq = pxa27x_init_irq, 984 .init_irq = pxa27x_init_irq,
@@ -991,8 +989,6 @@ MACHINE_END
991 989
992#ifdef CONFIG_MACH_BORZOI 990#ifdef CONFIG_MACH_BORZOI
993MACHINE_START(BORZOI, "SHARP Borzoi") 991MACHINE_START(BORZOI, "SHARP Borzoi")
994 .phys_io = 0x40000000,
995 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
996 .fixup = spitz_fixup, 992 .fixup = spitz_fixup,
997 .map_io = pxa_map_io, 993 .map_io = pxa_map_io,
998 .init_irq = pxa27x_init_irq, 994 .init_irq = pxa27x_init_irq,
@@ -1003,8 +999,6 @@ MACHINE_END
1003 999
1004#ifdef CONFIG_MACH_AKITA 1000#ifdef CONFIG_MACH_AKITA
1005MACHINE_START(AKITA, "SHARP Akita") 1001MACHINE_START(AKITA, "SHARP Akita")
1006 .phys_io = 0x40000000,
1007 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
1008 .fixup = spitz_fixup, 1002 .fixup = spitz_fixup,
1009 .map_io = pxa_map_io, 1003 .map_io = pxa_map_io,
1010 .init_irq = pxa27x_init_irq, 1004 .init_irq = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index a654d1e6b38a..738adc1773fd 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -56,6 +56,8 @@
56#include "devices.h" 56#include "devices.h"
57#include "generic.h" 57#include "generic.h"
58 58
59#define STARGATE_NR_IRQS (IRQ_BOARD_START + 8)
60
59/* Bluetooth */ 61/* Bluetooth */
60#define SG2_BT_RESET 81 62#define SG2_BT_RESET 81
61 63
@@ -996,8 +998,6 @@ static void __init stargate2_init(void)
996 998
997#ifdef CONFIG_MACH_INTELMOTE2 999#ifdef CONFIG_MACH_INTELMOTE2
998MACHINE_START(INTELMOTE2, "IMOTE 2") 1000MACHINE_START(INTELMOTE2, "IMOTE 2")
999 .phys_io = 0x40000000,
1000 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
1001 .map_io = pxa_map_io, 1001 .map_io = pxa_map_io,
1002 .init_irq = pxa27x_init_irq, 1002 .init_irq = pxa27x_init_irq,
1003 .timer = &pxa_timer, 1003 .timer = &pxa_timer,
@@ -1008,9 +1008,8 @@ MACHINE_END
1008 1008
1009#ifdef CONFIG_MACH_STARGATE2 1009#ifdef CONFIG_MACH_STARGATE2
1010MACHINE_START(STARGATE2, "Stargate 2") 1010MACHINE_START(STARGATE2, "Stargate 2")
1011 .phys_io = 0x40000000,
1012 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
1013 .map_io = pxa_map_io, 1011 .map_io = pxa_map_io,
1012 .nr_irqs = STARGATE_NR_IRQS,
1014 .init_irq = pxa27x_init_irq, 1013 .init_irq = pxa27x_init_irq,
1015 .timer = &pxa_timer, 1014 .timer = &pxa_timer,
1016 .init_machine = stargate2_init, 1015 .init_machine = stargate2_init,
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index f02dcb5b4e97..2ea7545273ad 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -25,7 +25,7 @@
25 25
26#include <mach/pxa930.h> 26#include <mach/pxa930.h>
27#include <mach/pxafb.h> 27#include <mach/pxafb.h>
28#include <mach/pxa27x_keypad.h> 28#include <plat/pxa27x_keypad.h>
29 29
30#include "devices.h" 30#include "devices.h"
31#include "generic.h" 31#include "generic.h"
@@ -489,9 +489,7 @@ static void __init tavorevb_init(void)
489 489
490MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)") 490MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)")
491 /* Maintainer: Eric Miao <eric.miao@marvell.com> */ 491 /* Maintainer: Eric Miao <eric.miao@marvell.com> */
492 .phys_io = 0x40000000,
493 .boot_params = 0xa0000100, 492 .boot_params = 0xa0000100,
494 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
495 .map_io = pxa_map_io, 493 .map_io = pxa_map_io,
496 .init_irq = pxa3xx_init_irq, 494 .init_irq = pxa3xx_init_irq,
497 .timer = &pxa_timer, 495 .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/tavorevb3.c b/arch/arm/mach-pxa/tavorevb3.c
new file mode 100644
index 000000000000..dc3011697bbf
--- /dev/null
+++ b/arch/arm/mach-pxa/tavorevb3.c
@@ -0,0 +1,135 @@
1/*
2 * linux/arch/arm/mach-pxa/tavorevb3.c
3 *
4 * Support for the Marvell EVB3 Development Platform.
5 *
6 * Copyright: (C) Copyright 2008-2010 Marvell International Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * publishhed by the Free Software Foundation.
11 */
12
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/interrupt.h>
17#include <linux/i2c.h>
18#include <linux/gpio.h>
19#include <linux/mfd/88pm860x.h>
20
21#include <asm/mach-types.h>
22#include <asm/mach/arch.h>
23
24#include <mach/pxa930.h>
25
26#include <plat/i2c.h>
27
28#include "devices.h"
29#include "generic.h"
30
31#define TAVOREVB3_NR_IRQS (IRQ_BOARD_START + 24)
32
33static mfp_cfg_t evb3_mfp_cfg[] __initdata = {
34 /* UART */
35 GPIO53_UART1_TXD,
36 GPIO54_UART1_RXD,
37
38 /* PMIC */
39 PMIC_INT_GPIO83,
40};
41
42#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
43static struct pm860x_touch_pdata evb3_touch = {
44 .gpadc_prebias = 1,
45 .slot_cycle = 1,
46 .tsi_prebias = 6,
47 .pen_prebias = 16,
48 .pen_prechg = 2,
49 .res_x = 300,
50};
51
52static struct pm860x_backlight_pdata evb3_backlight[] = {
53 {
54 .id = PM8606_ID_BACKLIGHT,
55 .iset = PM8606_WLED_CURRENT(24),
56 .flags = PM8606_BACKLIGHT1,
57 },
58 {},
59};
60
61static struct pm860x_led_pdata evb3_led[] = {
62 {
63 .id = PM8606_ID_LED,
64 .iset = PM8606_LED_CURRENT(12),
65 .flags = PM8606_LED1_RED,
66 }, {
67 .id = PM8606_ID_LED,
68 .iset = PM8606_LED_CURRENT(12),
69 .flags = PM8606_LED1_GREEN,
70 }, {
71 .id = PM8606_ID_LED,
72 .iset = PM8606_LED_CURRENT(12),
73 .flags = PM8606_LED1_BLUE,
74 }, {
75 .id = PM8606_ID_LED,
76 .iset = PM8606_LED_CURRENT(12),
77 .flags = PM8606_LED2_RED,
78 }, {
79 .id = PM8606_ID_LED,
80 .iset = PM8606_LED_CURRENT(12),
81 .flags = PM8606_LED2_GREEN,
82 }, {
83 .id = PM8606_ID_LED,
84 .iset = PM8606_LED_CURRENT(12),
85 .flags = PM8606_LED2_BLUE,
86 },
87};
88
89static struct pm860x_platform_data evb3_pm8607_info = {
90 .touch = &evb3_touch,
91 .backlight = &evb3_backlight[0],
92 .led = &evb3_led[0],
93 .companion_addr = 0x10,
94 .irq_mode = 0,
95 .irq_base = IRQ_BOARD_START,
96
97 .i2c_port = GI2C_PORT,
98};
99
100static struct i2c_board_info evb3_i2c_info[] = {
101 {
102 .type = "88PM860x",
103 .addr = 0x34,
104 .platform_data = &evb3_pm8607_info,
105 .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)),
106 },
107};
108
109static void __init evb3_init_i2c(void)
110{
111 pxa_set_i2c_info(NULL);
112 i2c_register_board_info(0, ARRAY_AND_SIZE(evb3_i2c_info));
113}
114#else
115static inline void evb3_init_i2c(void) {}
116#endif
117
118static void __init evb3_init(void)
119{
120 /* initialize MFP configurations */
121 pxa3xx_mfp_config(ARRAY_AND_SIZE(evb3_mfp_cfg));
122
123 pxa_set_ffuart_info(NULL);
124
125 evb3_init_i2c();
126}
127
128MACHINE_START(TAVOREVB3, "PXA950 Evaluation Board (aka TavorEVB3)")
129 .boot_params = 0xa0000100,
130 .map_io = pxa_map_io,
131 .nr_irqs = TAVOREVB3_NR_IRQS,
132 .init_irq = pxa3xx_init_irq,
133 .timer = &pxa_timer,
134 .init_machine = evb3_init,
135MACHINE_END
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 83cc3a18c2e9..0ee1df49606d 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -952,10 +952,9 @@ static void __init fixup_tosa(struct machine_desc *desc,
952} 952}
953 953
954MACHINE_START(TOSA, "SHARP Tosa") 954MACHINE_START(TOSA, "SHARP Tosa")
955 .phys_io = 0x40000000,
956 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
957 .fixup = fixup_tosa, 955 .fixup = fixup_tosa,
958 .map_io = pxa_map_io, 956 .map_io = pxa_map_io,
957 .nr_irqs = TOSA_NR_IRQS,
959 .init_irq = pxa25x_init_irq, 958 .init_irq = pxa25x_init_irq,
960 .init_machine = tosa_init, 959 .init_machine = tosa_init,
961 .timer = &pxa_timer, 960 .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 0acff172ef22..565d062f51d5 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -555,8 +555,6 @@ static void __init trizeps4_map_io(void)
555 555
556MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module") 556MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module")
557 /* MAINTAINER("Jürgen Schindele") */ 557 /* MAINTAINER("Jürgen Schindele") */
558 .phys_io = 0x40000000,
559 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
560 .boot_params = TRIZEPS4_SDRAM_BASE + 0x100, 558 .boot_params = TRIZEPS4_SDRAM_BASE + 0x100,
561 .init_machine = trizeps4_init, 559 .init_machine = trizeps4_init,
562 .map_io = trizeps4_map_io, 560 .map_io = trizeps4_map_io,
@@ -566,8 +564,6 @@ MACHINE_END
566 564
567MACHINE_START(TRIZEPS4WL, "Keith und Koep Trizeps IV-WL module") 565MACHINE_START(TRIZEPS4WL, "Keith und Koep Trizeps IV-WL module")
568 /* MAINTAINER("Jürgen Schindele") */ 566 /* MAINTAINER("Jürgen Schindele") */
569 .phys_io = 0x40000000,
570 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
571 .boot_params = TRIZEPS4_SDRAM_BASE + 0x100, 567 .boot_params = TRIZEPS4_SDRAM_BASE + 0x100,
572 .init_machine = trizeps4_init, 568 .init_machine = trizeps4_init,
573 .map_io = trizeps4_map_io, 569 .map_io = trizeps4_map_io,
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index e90114a7e246..438fc9a5ed59 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -992,8 +992,6 @@ static void __init viper_map_io(void)
992 992
993MACHINE_START(VIPER, "Arcom/Eurotech VIPER SBC") 993MACHINE_START(VIPER, "Arcom/Eurotech VIPER SBC")
994 /* Maintainer: Marc Zyngier <maz@misterjones.org> */ 994 /* Maintainer: Marc Zyngier <maz@misterjones.org> */
995 .phys_io = 0x40000000,
996 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
997 .boot_params = 0xa0000100, 995 .boot_params = 0xa0000100,
998 .map_io = viper_map_io, 996 .map_io = viper_map_io,
999 .init_irq = viper_init_irq, 997 .init_irq = viper_init_irq,
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index 37d6173bbb66..f45ac0961778 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -718,8 +718,6 @@ static void __init vpac270_init(void)
718} 718}
719 719
720MACHINE_START(VPAC270, "Voipac PXA270") 720MACHINE_START(VPAC270, "Voipac PXA270")
721 .phys_io = 0x40000000,
722 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
723 .boot_params = 0xa0000100, 721 .boot_params = 0xa0000100,
724 .map_io = pxa_map_io, 722 .map_io = pxa_map_io,
725 .init_irq = pxa27x_init_irq, 723 .init_irq = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c
index d3b4e3f2e033..3260ce73d327 100644
--- a/arch/arm/mach-pxa/xcep.c
+++ b/arch/arm/mach-pxa/xcep.c
@@ -181,8 +181,6 @@ static void __init xcep_init(void)
181} 181}
182 182
183MACHINE_START(XCEP, "Iskratel XCEP") 183MACHINE_START(XCEP, "Iskratel XCEP")
184 .phys_io = 0x40000000,
185 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
186 .boot_params = 0xa0000100, 184 .boot_params = 0xa0000100,
187 .init_machine = xcep_init, 185 .init_machine = xcep_init,
188 .map_io = pxa_map_io, 186 .map_io = pxa_map_io,
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index f0d02288b4ca..fefde9848d82 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -37,7 +37,7 @@
37#include <mach/z2.h> 37#include <mach/z2.h>
38#include <mach/pxafb.h> 38#include <mach/pxafb.h>
39#include <mach/mmc.h> 39#include <mach/mmc.h>
40#include <mach/pxa27x_keypad.h> 40#include <plat/pxa27x_keypad.h>
41#include <mach/pxa2xx_spi.h> 41#include <mach/pxa2xx_spi.h>
42 42
43#include <plat/i2c.h> 43#include <plat/i2c.h>
@@ -703,9 +703,7 @@ static void __init z2_init(void)
703} 703}
704 704
705MACHINE_START(ZIPIT2, "Zipit Z2") 705MACHINE_START(ZIPIT2, "Zipit Z2")
706 .phys_io = 0x40000000,
707 .boot_params = 0xa0000100, 706 .boot_params = 0xa0000100,
708 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
709 .map_io = pxa_map_io, 707 .map_io = pxa_map_io,
710 .init_irq = pxa27x_init_irq, 708 .init_irq = pxa27x_init_irq,
711 .timer = &pxa_timer, 709 .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 03b9cb910e08..dea46a2d089b 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -900,10 +900,9 @@ static void __init zeus_map_io(void)
900 900
901MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS") 901MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
902 /* Maintainer: Marc Zyngier <maz@misterjones.org> */ 902 /* Maintainer: Marc Zyngier <maz@misterjones.org> */
903 .phys_io = 0x40000000,
904 .io_pg_offst = ((io_p2v(0x40000000) >> 18) & 0xfffc),
905 .boot_params = 0xa0000100, 903 .boot_params = 0xa0000100,
906 .map_io = zeus_map_io, 904 .map_io = zeus_map_io,
905 .nr_irqs = ZEUS_NR_IRQS,
907 .init_irq = zeus_init_irq, 906 .init_irq = zeus_init_irq,
908 .timer = &pxa_timer, 907 .timer = &pxa_timer,
909 .init_machine = zeus_init, 908 .init_machine = zeus_init,
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index c479cbecf784..f25fb6245bd7 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -30,7 +30,7 @@
30#include <mach/zylonite.h> 30#include <mach/zylonite.h>
31#include <mach/mmc.h> 31#include <mach/mmc.h>
32#include <mach/ohci.h> 32#include <mach/ohci.h>
33#include <mach/pxa27x_keypad.h> 33#include <plat/pxa27x_keypad.h>
34#include <plat/pxa3xx_nand.h> 34#include <plat/pxa3xx_nand.h>
35 35
36#include "devices.h" 36#include "devices.h"
@@ -411,10 +411,9 @@ static void __init zylonite_init(void)
411} 411}
412 412
413MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)") 413MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
414 .phys_io = 0x40000000,
415 .boot_params = 0xa0000100, 414 .boot_params = 0xa0000100,
416 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
417 .map_io = pxa_map_io, 415 .map_io = pxa_map_io,
416 .nr_irqs = ZYLONITE_NR_IRQS,
418 .init_irq = pxa3xx_init_irq, 417 .init_irq = pxa3xx_init_irq,
419 .timer = &pxa_timer, 418 .timer = &pxa_timer,
420 .init_machine = zylonite_init, 419 .init_machine = zylonite_init,
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 2fa38df28414..07c08151dfe6 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -259,6 +259,7 @@ struct mmci_platform_data realview_mmc0_plat_data = {
259 .status = realview_mmc_status, 259 .status = realview_mmc_status,
260 .gpio_wp = 17, 260 .gpio_wp = 17,
261 .gpio_cd = 16, 261 .gpio_cd = 16,
262 .cd_invert = true,
262}; 263};
263 264
264struct mmci_platform_data realview_mmc1_plat_data = { 265struct mmci_platform_data realview_mmc1_plat_data = {
@@ -266,6 +267,7 @@ struct mmci_platform_data realview_mmc1_plat_data = {
266 .status = realview_mmc_status, 267 .status = realview_mmc_status,
267 .gpio_wp = 19, 268 .gpio_wp = 19,
268 .gpio_cd = 18, 269 .gpio_cd = 18,
270 .cd_invert = true,
269}; 271};
270 272
271/* 273/*
diff --git a/arch/arm/mach-realview/include/mach/debug-macro.S b/arch/arm/mach-realview/include/mach/debug-macro.S
index 86622289b74e..90b687cbe04e 100644
--- a/arch/arm/mach-realview/include/mach/debug-macro.S
+++ b/arch/arm/mach-realview/include/mach/debug-macro.S
@@ -33,12 +33,10 @@
33#error "Unknown RealView platform" 33#error "Unknown RealView platform"
34#endif 34#endif
35 35
36 .macro addruart, rx, tmp 36 .macro addruart, rp, rv
37 mrc p15, 0, \rx, c1, c0 37 mov \rp, #DEBUG_LL_UART_OFFSET
38 tst \rx, #1 @ MMU enabled? 38 orr \rv, \rp, #0xfb000000 @ virtual base
39 moveq \rx, #0x10000000 39 orr \rp, \rp, #0x10000000 @ physical base
40 movne \rx, #0xfb000000 @ virtual base
41 orr \rx, \rx, #DEBUG_LL_UART_OFFSET
42 .endm 40 .endm
43 41
44#include <asm/hardware/debug-pl01x.S> 42#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
index dd53892d44a7..d3cd265cb058 100644
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ b/arch/arm/mach-realview/include/mach/smp.h
@@ -1,16 +1,8 @@
1#ifndef ASMARM_ARCH_SMP_H 1#ifndef ASMARM_ARCH_SMP_H
2#define ASMARM_ARCH_SMP_H 2#define ASMARM_ARCH_SMP_H
3 3
4
5#include <asm/hardware/gic.h> 4#include <asm/hardware/gic.h>
6 5#include <asm/smp_mpidr.h>
7#define hard_smp_processor_id() \
8 ({ \
9 unsigned int cpunum; \
10 __asm__("mrc p15, 0, %0, c0, c0, 5" \
11 : "=r" (cpunum)); \
12 cpunum &= 0x0F; \
13 })
14 6
15/* 7/*
16 * We use IRQ1 as the IPI 8 * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 991c1f8390e2..f2697106f809 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -486,8 +486,6 @@ static void __init realview_eb_init(void)
486 486
487MACHINE_START(REALVIEW_EB, "ARM-RealView EB") 487MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
488 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 488 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
489 .phys_io = REALVIEW_EB_UART0_BASE & SECTION_MASK,
490 .io_pg_offst = (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc,
491 .boot_params = PHYS_OFFSET + 0x00000100, 489 .boot_params = PHYS_OFFSET + 0x00000100,
492 .fixup = realview_fixup, 490 .fixup = realview_fixup,
493 .map_io = realview_eb_map_io, 491 .map_io = realview_eb_map_io,
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index d2be12eb829e..a4125619d71b 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -378,8 +378,6 @@ static void __init realview_pb1176_init(void)
378 378
379MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176") 379MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
380 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 380 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
381 .phys_io = REALVIEW_PB1176_UART0_BASE & SECTION_MASK,
382 .io_pg_offst = (IO_ADDRESS(REALVIEW_PB1176_UART0_BASE) >> 18) & 0xfffc,
383 .boot_params = PHYS_OFFSET + 0x00000100, 381 .boot_params = PHYS_OFFSET + 0x00000100,
384 .fixup = realview_pb1176_fixup, 382 .fixup = realview_pb1176_fixup,
385 .map_io = realview_pb1176_map_io, 383 .map_io = realview_pb1176_map_io,
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index d591bc00b86e..117b95b2ca15 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -381,8 +381,6 @@ static void __init realview_pb11mp_init(void)
381 381
382MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore") 382MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
383 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 383 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
384 .phys_io = REALVIEW_PB11MP_UART0_BASE & SECTION_MASK,
385 .io_pg_offst = (IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE) >> 18) & 0xfffc,
386 .boot_params = PHYS_OFFSET + 0x00000100, 384 .boot_params = PHYS_OFFSET + 0x00000100,
387 .fixup = realview_fixup, 385 .fixup = realview_fixup,
388 .map_io = realview_pb11mp_map_io, 386 .map_io = realview_pb11mp_map_io,
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 6c37621217bc..929b8dc12e81 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -331,8 +331,6 @@ static void __init realview_pba8_init(void)
331 331
332MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8") 332MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
333 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 333 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
334 .phys_io = REALVIEW_PBA8_UART0_BASE & SECTION_MASK,
335 .io_pg_offst = (IO_ADDRESS(REALVIEW_PBA8_UART0_BASE) >> 18) & 0xfffc,
336 .boot_params = PHYS_OFFSET + 0x00000100, 334 .boot_params = PHYS_OFFSET + 0x00000100,
337 .fixup = realview_fixup, 335 .fixup = realview_fixup,
338 .map_io = realview_pba8_map_io, 336 .map_io = realview_pba8_map_io,
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 9428eff0b116..b9f9e20031a7 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -417,8 +417,6 @@ static void __init realview_pbx_init(void)
417 417
418MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX") 418MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
419 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 419 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
420 .phys_io = REALVIEW_PBX_UART0_BASE & SECTION_MASK,
421 .io_pg_offst = (IO_ADDRESS(REALVIEW_PBX_UART0_BASE) >> 18) & 0xfffc,
422 .boot_params = PHYS_OFFSET + 0x00000100, 420 .boot_params = PHYS_OFFSET + 0x00000100,
423 .fixup = realview_pbx_fixup, 421 .fixup = realview_pbx_fixup,
424 .map_io = realview_pbx_map_io, 422 .map_io = realview_pbx_map_io,
diff --git a/arch/arm/mach-rpc/include/mach/debug-macro.S b/arch/arm/mach-rpc/include/mach/debug-macro.S
index 6fc8d66395dc..85effffdc2b2 100644
--- a/arch/arm/mach-rpc/include/mach/debug-macro.S
+++ b/arch/arm/mach-rpc/include/mach/debug-macro.S
@@ -11,13 +11,11 @@
11 * 11 *
12*/ 12*/
13 13
14 .macro addruart, rx, tmp 14 .macro addruart, rp, rv
15 mrc p15, 0, \rx, c1, c0 15 mov \rp, #0x00010000
16 tst \rx, #1 @ MMU enabled? 16 orr \rp, \rp, #0x00000fe0
17 moveq \rx, #0x03000000 17 orr \rv, \rp, #0xe0000000 @ virtual
18 movne \rx, #0xe0000000 18 orr \rp, \rp, #0x03000000 @ physical
19 orr \rx, \rx, #0x00010000
20 orr \rx, \rx, #0x00000fe0
21 .endm 19 .endm
22 20
23#define UART_SHIFT 2 21#define UART_SHIFT 2
diff --git a/arch/arm/mach-rpc/include/mach/vmalloc.h b/arch/arm/mach-rpc/include/mach/vmalloc.h
index 9a96fd69e705..3bcd86fadb81 100644
--- a/arch/arm/mach-rpc/include/mach/vmalloc.h
+++ b/arch/arm/mach-rpc/include/mach/vmalloc.h
@@ -7,4 +7,4 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10#define VMALLOC_END (PAGE_OFFSET + 0x1c000000) 10#define VMALLOC_END 0xdc000000
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index c7fc01e9d1f6..580b3c73d2c7 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -218,8 +218,6 @@ extern struct sys_timer ioc_timer;
218 218
219MACHINE_START(RISCPC, "Acorn-RiscPC") 219MACHINE_START(RISCPC, "Acorn-RiscPC")
220 /* Maintainer: Russell King */ 220 /* Maintainer: Russell King */
221 .phys_io = 0x03000000,
222 .io_pg_offst = ((0xe0000000) >> 18) & 0xfffc,
223 .boot_params = 0x10000100, 221 .boot_params = 0x10000100,
224 .reserve_lp0 = 1, 222 .reserve_lp0 = 1,
225 .reserve_lp1 = 1, 223 .reserve_lp1 = 1,
diff --git a/arch/arm/mach-s3c2410/include/mach/debug-macro.S b/arch/arm/mach-s3c2410/include/mach/debug-macro.S
index 0eef78b4a6ed..5882deaa56be 100644
--- a/arch/arm/mach-s3c2410/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c2410/include/mach/debug-macro.S
@@ -19,13 +19,12 @@
19#define S3C2410_UART1_OFF (0x4000) 19#define S3C2410_UART1_OFF (0x4000)
20#define SHIFT_2440TXF (14-9) 20#define SHIFT_2440TXF (14-9)
21 21
22 .macro addruart, rx, tmp 22 .macro addruart, rp, rv
23 mrc p15, 0, \rx, c1, c0 23 ldr \rp, = S3C24XX_PA_UART
24 tst \rx, #1 24 ldr \rv, = S3C24XX_VA_UART
25 ldreq \rx, = S3C24XX_PA_UART
26 ldrne \rx, = S3C24XX_VA_UART
27#if CONFIG_DEBUG_S3C_UART != 0 25#if CONFIG_DEBUG_S3C_UART != 0
28 add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART) 26 add \rp, \rp, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
27 add \rv, \rv, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
29#endif 28#endif
30 .endm 29 .endm
31 30
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index 34fc05a4244b..44440cbd7620 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -241,8 +241,6 @@ static void __init amlm5900_init(void)
241} 241}
242 242
243MACHINE_START(AML_M5900, "AML_M5900") 243MACHINE_START(AML_M5900, "AML_M5900")
244 .phys_io = S3C2410_PA_UART,
245 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
246 .boot_params = S3C2410_SDRAM_PA + 0x100, 244 .boot_params = S3C2410_SDRAM_PA + 0x100,
247 .map_io = amlm5900_map_io, 245 .map_io = amlm5900_map_io,
248 .init_irq = s3c24xx_init_irq, 246 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index c1f90f6fab42..2970ea9f7c2b 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -664,8 +664,6 @@ static void __init bast_init(void)
664 664
665MACHINE_START(BAST, "Simtec-BAST") 665MACHINE_START(BAST, "Simtec-BAST")
666 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ 666 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
667 .phys_io = S3C2410_PA_UART,
668 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
669 .boot_params = S3C2410_SDRAM_PA + 0x100, 667 .boot_params = S3C2410_SDRAM_PA + 0x100,
670 .map_io = bast_map_io, 668 .map_io = bast_map_io,
671 .init_irq = s3c24xx_init_irq, 669 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 3ba3bab139d0..98c5c9e81ee9 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -350,8 +350,6 @@ static void __init h1940_init(void)
350 350
351MACHINE_START(H1940, "IPAQ-H1940") 351MACHINE_START(H1940, "IPAQ-H1940")
352 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 352 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
353 .phys_io = S3C2410_PA_UART,
354 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
355 .boot_params = S3C2410_SDRAM_PA + 0x100, 353 .boot_params = S3C2410_SDRAM_PA + 0x100,
356 .map_io = h1940_map_io, 354 .map_io = h1940_map_io,
357 .reserve = h1940_reserve, 355 .reserve = h1940_reserve,
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 41f299d983eb..271b9aa6d40a 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -605,8 +605,6 @@ MACHINE_START(N30, "Acer-N30")
605 /* Maintainer: Christer Weinigel <christer@weinigel.se>, 605 /* Maintainer: Christer Weinigel <christer@weinigel.se>,
606 Ben Dooks <ben-linux@fluff.org> 606 Ben Dooks <ben-linux@fluff.org>
607 */ 607 */
608 .phys_io = S3C2410_PA_UART,
609 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
610 .boot_params = S3C2410_SDRAM_PA + 0x100, 608 .boot_params = S3C2410_SDRAM_PA + 0x100,
611 .timer = &s3c24xx_timer, 609 .timer = &s3c24xx_timer,
612 .init_machine = n30_init, 610 .init_machine = n30_init,
@@ -617,8 +615,6 @@ MACHINE_END
617MACHINE_START(N35, "Acer-N35") 615MACHINE_START(N35, "Acer-N35")
618 /* Maintainer: Christer Weinigel <christer@weinigel.se> 616 /* Maintainer: Christer Weinigel <christer@weinigel.se>
619 */ 617 */
620 .phys_io = S3C2410_PA_UART,
621 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
622 .boot_params = S3C2410_SDRAM_PA + 0x100, 618 .boot_params = S3C2410_SDRAM_PA + 0x100,
623 .timer = &s3c24xx_timer, 619 .timer = &s3c24xx_timer,
624 .init_machine = n30_init, 620 .init_machine = n30_init,
diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c
index d8c7f2efc1a7..0aa16cd5acbc 100644
--- a/arch/arm/mach-s3c2410/mach-otom.c
+++ b/arch/arm/mach-s3c2410/mach-otom.c
@@ -116,8 +116,6 @@ static void __init otom11_init(void)
116 116
117MACHINE_START(OTOM, "Nex Vision - Otom 1.1") 117MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
118 /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */ 118 /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */
119 .phys_io = S3C2410_PA_UART,
120 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
121 .boot_params = S3C2410_SDRAM_PA + 0x100, 119 .boot_params = S3C2410_SDRAM_PA + 0x100,
122 .map_io = otom11_map_io, 120 .map_io = otom11_map_io,
123 .init_machine = otom11_init, 121 .init_machine = otom11_init,
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index d0e87b6e2e0f..e8f49feef28c 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -362,8 +362,6 @@ static void __init qt2410_machine_init(void)
362} 362}
363 363
364MACHINE_START(QT2410, "QT2410") 364MACHINE_START(QT2410, "QT2410")
365 .phys_io = S3C2410_PA_UART,
366 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
367 .boot_params = S3C2410_SDRAM_PA + 0x100, 365 .boot_params = S3C2410_SDRAM_PA + 0x100,
368 .map_io = qt2410_map_io, 366 .map_io = qt2410_map_io,
369 .init_irq = s3c24xx_init_irq, 367 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c
index 452223042201..e17f03387aba 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2410.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2410.c
@@ -111,8 +111,6 @@ static void __init smdk2410_init(void)
111MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switch 111MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switch
112 * to SMDK2410 */ 112 * to SMDK2410 */
113 /* Maintainer: Jonas Dietsche */ 113 /* Maintainer: Jonas Dietsche */
114 .phys_io = S3C2410_PA_UART,
115 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
116 .boot_params = S3C2410_SDRAM_PA + 0x100, 114 .boot_params = S3C2410_SDRAM_PA + 0x100,
117 .map_io = smdk2410_map_io, 115 .map_io = smdk2410_map_io,
118 .init_irq = s3c24xx_init_irq, 116 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c
index 929164a8e9b1..a15d0621c22f 100644
--- a/arch/arm/mach-s3c2410/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c
@@ -152,8 +152,6 @@ static void __init tct_hammer_init(void)
152} 152}
153 153
154MACHINE_START(TCT_HAMMER, "TCT_HAMMER") 154MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
155 .phys_io = S3C2410_PA_UART,
156 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
157 .boot_params = S3C2410_SDRAM_PA + 0x100, 155 .boot_params = S3C2410_SDRAM_PA + 0x100,
158 .map_io = tct_hammer_map_io, 156 .map_io = tct_hammer_map_io,
159 .init_irq = s3c24xx_init_irq, 157 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index d540d79dd264..6ccce5a761b4 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -400,8 +400,6 @@ static void __init vr1000_init(void)
400 400
401MACHINE_START(VR1000, "Thorcom-VR1000") 401MACHINE_START(VR1000, "Thorcom-VR1000")
402 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ 402 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
403 .phys_io = S3C2410_PA_UART,
404 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
405 .boot_params = S3C2410_SDRAM_PA + 0x100, 403 .boot_params = S3C2410_SDRAM_PA + 0x100,
406 .map_io = vr1000_map_io, 404 .map_io = vr1000_map_io,
407 .init_machine = vr1000_init, 405 .init_machine = vr1000_init,
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 478f4b4606c2..923e01bdf017 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -675,8 +675,6 @@ static void __init jive_machine_init(void)
675 675
676MACHINE_START(JIVE, "JIVE") 676MACHINE_START(JIVE, "JIVE")
677 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 677 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
678 .phys_io = S3C2410_PA_UART,
679 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
680 .boot_params = S3C2410_SDRAM_PA + 0x100, 678 .boot_params = S3C2410_SDRAM_PA + 0x100,
681 679
682 .init_irq = s3c24xx_init_irq, 680 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index 054c9f92232a..8e5758bdd666 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -150,8 +150,6 @@ static void __init smdk2413_machine_init(void)
150 150
151MACHINE_START(S3C2413, "S3C2413") 151MACHINE_START(S3C2413, "S3C2413")
152 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 152 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
153 .phys_io = S3C2410_PA_UART,
154 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
155 .boot_params = S3C2410_SDRAM_PA + 0x100, 153 .boot_params = S3C2410_SDRAM_PA + 0x100,
156 154
157 .fixup = smdk2413_fixup, 155 .fixup = smdk2413_fixup,
@@ -163,8 +161,6 @@ MACHINE_END
163 161
164MACHINE_START(SMDK2412, "SMDK2412") 162MACHINE_START(SMDK2412, "SMDK2412")
165 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 163 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
166 .phys_io = S3C2410_PA_UART,
167 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
168 .boot_params = S3C2410_SDRAM_PA + 0x100, 164 .boot_params = S3C2410_SDRAM_PA + 0x100,
169 165
170 .fixup = smdk2413_fixup, 166 .fixup = smdk2413_fixup,
@@ -176,8 +172,6 @@ MACHINE_END
176 172
177MACHINE_START(SMDK2413, "SMDK2413") 173MACHINE_START(SMDK2413, "SMDK2413")
178 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 174 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
179 .phys_io = S3C2410_PA_UART,
180 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
181 .boot_params = S3C2410_SDRAM_PA + 0x100, 175 .boot_params = S3C2410_SDRAM_PA + 0x100,
182 176
183 .fixup = smdk2413_fixup, 177 .fixup = smdk2413_fixup,
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index f291ac25d312..83544ebe20ac 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -156,8 +156,6 @@ static void __init vstms_init(void)
156} 156}
157 157
158MACHINE_START(VSTMS, "VSTMS") 158MACHINE_START(VSTMS, "VSTMS")
159 .phys_io = S3C2410_PA_UART,
160 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
161 .boot_params = S3C2410_SDRAM_PA + 0x100, 159 .boot_params = S3C2410_SDRAM_PA + 0x100,
162 160
163 .fixup = vstms_fixup, 161 .fixup = vstms_fixup,
diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c
index 5fc3f67ef265..7fc366476d7e 100644
--- a/arch/arm/mach-s3c2416/mach-smdk2416.c
+++ b/arch/arm/mach-s3c2416/mach-smdk2416.c
@@ -195,8 +195,6 @@ static void __init smdk2416_machine_init(void)
195 195
196MACHINE_START(SMDK2416, "SMDK2416") 196MACHINE_START(SMDK2416, "SMDK2416")
197 /* Maintainer: Yauhen Kharuzhy <jekhor@gmail.com> */ 197 /* Maintainer: Yauhen Kharuzhy <jekhor@gmail.com> */
198 .phys_io = S3C2410_PA_UART,
199 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
200 .boot_params = S3C2410_SDRAM_PA + 0x100, 198 .boot_params = S3C2410_SDRAM_PA + 0x100,
201 199
202 .init_irq = s3c24xx_init_irq, 200 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index b73f78a9da5c..d7086788b1ff 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -498,8 +498,6 @@ static void __init anubis_init(void)
498 498
499MACHINE_START(ANUBIS, "Simtec-Anubis") 499MACHINE_START(ANUBIS, "Simtec-Anubis")
500 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ 500 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
501 .phys_io = S3C2410_PA_UART,
502 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
503 .boot_params = S3C2410_SDRAM_PA + 0x100, 501 .boot_params = S3C2410_SDRAM_PA + 0x100,
504 .map_io = anubis_map_io, 502 .map_io = anubis_map_io,
505 .init_machine = anubis_init, 503 .init_machine = anubis_init,
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index 84725791e6bf..e3810c86a5e6 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -233,8 +233,6 @@ static void __init at2440evb_init(void)
233 233
234 234
235MACHINE_START(AT2440EVB, "AT2440EVB") 235MACHINE_START(AT2440EVB, "AT2440EVB")
236 .phys_io = S3C2410_PA_UART,
237 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
238 .boot_params = S3C2410_SDRAM_PA + 0x100, 236 .boot_params = S3C2410_SDRAM_PA + 0x100,
239 .map_io = at2440evb_map_io, 237 .map_io = at2440evb_map_io,
240 .init_machine = at2440evb_init, 238 .init_machine = at2440evb_init,
diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c
index deaabe86741d..9f2c14ec7181 100644
--- a/arch/arm/mach-s3c2440/mach-gta02.c
+++ b/arch/arm/mach-s3c2440/mach-gta02.c
@@ -572,8 +572,6 @@ static void __init gta02_machine_init(void)
572 572
573MACHINE_START(NEO1973_GTA02, "GTA02") 573MACHINE_START(NEO1973_GTA02, "GTA02")
574 /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */ 574 /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */
575 .phys_io = S3C2410_PA_UART,
576 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
577 .boot_params = S3C2410_SDRAM_PA + 0x100, 575 .boot_params = S3C2410_SDRAM_PA + 0x100,
578 .map_io = gta02_map_io, 576 .map_io = gta02_map_io,
579 .init_irq = s3c24xx_init_irq, 577 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
index a76bcda210ad..f62bb4c793bd 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -691,8 +691,6 @@ static void __init mini2440_init(void)
691 691
692MACHINE_START(MINI2440, "MINI2440") 692MACHINE_START(MINI2440, "MINI2440")
693 /* Maintainer: Michel Pollet <buserror@gmail.com> */ 693 /* Maintainer: Michel Pollet <buserror@gmail.com> */
694 .phys_io = S3C2410_PA_UART,
695 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
696 .boot_params = S3C2410_SDRAM_PA + 0x100, 694 .boot_params = S3C2410_SDRAM_PA + 0x100,
697 .map_io = mini2440_map_io, 695 .map_io = mini2440_map_io,
698 .init_machine = mini2440_init, 696 .init_machine = mini2440_init,
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 3ff62de45fde..37dd306fb7dc 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -151,8 +151,6 @@ static void __init nexcoder_init(void)
151 151
152MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440") 152MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
153 /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */ 153 /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */
154 .phys_io = S3C2410_PA_UART,
155 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
156 .boot_params = S3C2410_SDRAM_PA + 0x100, 154 .boot_params = S3C2410_SDRAM_PA + 0x100,
157 .map_io = nexcoder_map_io, 155 .map_io = nexcoder_map_io,
158 .init_machine = nexcoder_init, 156 .init_machine = nexcoder_init,
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 319458da71a0..14dc67897757 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -455,8 +455,6 @@ static void __init osiris_init(void)
455 455
456MACHINE_START(OSIRIS, "Simtec-OSIRIS") 456MACHINE_START(OSIRIS, "Simtec-OSIRIS")
457 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ 457 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
458 .phys_io = S3C2410_PA_UART,
459 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
460 .boot_params = S3C2410_SDRAM_PA + 0x100, 458 .boot_params = S3C2410_SDRAM_PA + 0x100,
461 .map_io = osiris_map_io, 459 .map_io = osiris_map_io,
462 .init_irq = s3c24xx_init_irq, 460 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
index 142d1f921176..32019bd9db3b 100644
--- a/arch/arm/mach-s3c2440/mach-rx1950.c
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -580,8 +580,6 @@ static void __init rx1950_reserve(void)
580 580
581MACHINE_START(RX1950, "HP iPAQ RX1950") 581MACHINE_START(RX1950, "HP iPAQ RX1950")
582 /* Maintainers: Vasily Khoruzhick */ 582 /* Maintainers: Vasily Khoruzhick */
583 .phys_io = S3C2410_PA_UART,
584 .io_pg_offst = (((u32) S3C24XX_VA_UART) >> 18) & 0xfffc,
585 .boot_params = S3C2410_SDRAM_PA + 0x100, 583 .boot_params = S3C2410_SDRAM_PA + 0x100,
586 .map_io = rx1950_map_io, 584 .map_io = rx1950_map_io,
587 .reserve = rx1950_reserve, 585 .reserve = rx1950_reserve,
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index 6bb44f75a9ce..1472b1a5b2fb 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -218,8 +218,6 @@ static void __init rx3715_init_machine(void)
218 218
219MACHINE_START(RX3715, "IPAQ-RX3715") 219MACHINE_START(RX3715, "IPAQ-RX3715")
220 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 220 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
221 .phys_io = S3C2410_PA_UART,
222 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
223 .boot_params = S3C2410_SDRAM_PA + 0x100, 221 .boot_params = S3C2410_SDRAM_PA + 0x100,
224 .map_io = rx3715_map_io, 222 .map_io = rx3715_map_io,
225 .reserve = rx3715_reserve, 223 .reserve = rx3715_reserve,
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index df83276d85ae..eedfe0f11643 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -175,8 +175,6 @@ static void __init smdk2440_machine_init(void)
175 175
176MACHINE_START(S3C2440, "SMDK2440") 176MACHINE_START(S3C2440, "SMDK2440")
177 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 177 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
178 .phys_io = S3C2410_PA_UART,
179 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
180 .boot_params = S3C2410_SDRAM_PA + 0x100, 178 .boot_params = S3C2410_SDRAM_PA + 0x100,
181 179
182 .init_irq = s3c24xx_init_irq, 180 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
index 4c863d3a52f4..4337f0a9960d 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -132,8 +132,6 @@ static void __init smdk2443_machine_init(void)
132 132
133MACHINE_START(SMDK2443, "SMDK2443") 133MACHINE_START(SMDK2443, "SMDK2443")
134 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 134 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
135 .phys_io = S3C2410_PA_UART,
136 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
137 .boot_params = S3C2410_SDRAM_PA + 0x100, 135 .boot_params = S3C2410_SDRAM_PA + 0x100,
138 136
139 .init_irq = s3c24xx_init_irq, 137 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c24a0/include/mach/debug-macro.S b/arch/arm/mach-s3c24a0/include/mach/debug-macro.S
index 239476b81f3b..0c5a73805560 100644
--- a/arch/arm/mach-s3c24a0/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c24a0/include/mach/debug-macro.S
@@ -10,13 +10,12 @@
10#include <mach/map.h> 10#include <mach/map.h>
11#include <plat/regs-serial.h> 11#include <plat/regs-serial.h>
12 12
13 .macro addruart, rx, tmp 13 .macro addruart, rp, rv
14 mrc p15, 0, \rx, c1, c0 14 ldr \rp, = S3C24XX_PA_UART
15 tst \rx, #1 15 ldr \rv, = S3C24XX_VA_UART
16 ldreq \rx, = S3C24XX_PA_UART
17 ldrne \rx, = S3C24XX_VA_UART
18#if CONFIG_DEBUG_S3C_UART != 0 16#if CONFIG_DEBUG_S3C_UART != 0
19 add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART) 17 add \rp, \rp, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
18 add \rv, \rv, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
20#endif 19#endif
21 .endm 20 .endm
22 21
diff --git a/arch/arm/mach-s3c64xx/include/mach/debug-macro.S b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
index f9ab5d26052a..a29e70550c70 100644
--- a/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
@@ -21,13 +21,12 @@
21 * aligned and add in the offset when we load the value here. 21 * aligned and add in the offset when we load the value here.
22 */ 22 */
23 23
24 .macro addruart, rx, rtmp 24 .macro addruart, rp, rv
25 mrc p15, 0, \rx, c1, c0 25 ldr \rp, = S3C_PA_UART
26 tst \rx, #1 26 ldr \rv, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
27 ldreq \rx, = S3C_PA_UART
28 ldrne \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
29#if CONFIG_DEBUG_S3C_UART != 0 27#if CONFIG_DEBUG_S3C_UART != 0
30 add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) 28 add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
29 add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
31#endif 30#endif
32 .endm 31 .endm
33 32
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index 742dc87bd9c1..a53cf149476e 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -233,8 +233,6 @@ static void __init anw6410_machine_init(void)
233 233
234MACHINE_START(ANW6410, "A&W6410") 234MACHINE_START(ANW6410, "A&W6410")
235 /* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */ 235 /* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
236 .phys_io = S3C_PA_UART & 0xfff00000,
237 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
238 .boot_params = S3C64XX_PA_SDRAM + 0x100, 236 .boot_params = S3C64XX_PA_SDRAM + 0x100,
239 237
240 .init_irq = s3c6410_init_irq, 238 .init_irq = s3c6410_init_irq,
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index fba90229f0df..b2639582caca 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -265,8 +265,6 @@ static void __init hmt_machine_init(void)
265 265
266MACHINE_START(HMT, "Airgoo-HMT") 266MACHINE_START(HMT, "Airgoo-HMT")
267 /* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */ 267 /* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */
268 .phys_io = S3C_PA_UART & 0xfff00000,
269 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
270 .boot_params = S3C64XX_PA_SDRAM + 0x100, 268 .boot_params = S3C64XX_PA_SDRAM + 0x100,
271 .init_irq = s3c6410_init_irq, 269 .init_irq = s3c6410_init_irq,
272 .map_io = hmt_map_io, 270 .map_io = hmt_map_io,
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index bf65747ea68e..c4986498cd12 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -97,8 +97,6 @@ static void __init ncp_machine_init(void)
97 97
98MACHINE_START(NCP, "NCP") 98MACHINE_START(NCP, "NCP")
99 /* Maintainer: Samsung Electronics */ 99 /* Maintainer: Samsung Electronics */
100 .phys_io = S3C_PA_UART & 0xfff00000,
101 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
102 .boot_params = S3C64XX_PA_SDRAM + 0x100, 100 .boot_params = S3C64XX_PA_SDRAM + 0x100,
103 .init_irq = s3c6410_init_irq, 101 .init_irq = s3c6410_init_irq,
104 .map_io = ncp_map_io, 102 .map_io = ncp_map_io,
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index e130379ba0e8..4b4475da8ec6 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -141,8 +141,6 @@ static void __init real6410_machine_init(void)
141 141
142MACHINE_START(REAL6410, "REAL6410") 142MACHINE_START(REAL6410, "REAL6410")
143 /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */ 143 /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
144 .phys_io = S3C_PA_UART & 0xfff00000,
145 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
146 .boot_params = S3C64XX_PA_SDRAM + 0x100, 144 .boot_params = S3C64XX_PA_SDRAM + 0x100,
147 145
148 .init_irq = s3c6410_init_irq, 146 .init_irq = s3c6410_init_irq,
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index 3a9639bc3d9b..cb1ebeb08763 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -136,7 +136,7 @@ static struct platform_device smartq_usb_otg_vbus_dev = {
136 .dev.platform_data = &smartq_usb_otg_vbus_pdata, 136 .dev.platform_data = &smartq_usb_otg_vbus_pdata,
137}; 137};
138 138
139static int __init smartq_bl_init(struct device *dev) 139static int smartq_bl_init(struct device *dev)
140{ 140{
141 s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_SFN(2)); 141 s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_SFN(2));
142 142
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index a4d59b076e3d..3a3e5acde523 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -32,7 +32,7 @@
32 32
33#include "mach-smartq.h" 33#include "mach-smartq.h"
34 34
35static struct gpio_led smartq5_leds[] __initdata = { 35static struct gpio_led smartq5_leds[] = {
36 { 36 {
37 .name = "smartq5:green", 37 .name = "smartq5:green",
38 .active_low = 1, 38 .active_low = 1,
@@ -146,8 +146,6 @@ static void __init smartq5_machine_init(void)
146 146
147MACHINE_START(SMARTQ5, "SmartQ 5") 147MACHINE_START(SMARTQ5, "SmartQ 5")
148 /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */ 148 /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
149 .phys_io = S3C_PA_UART & 0xfff00000,
150 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
151 .boot_params = S3C64XX_PA_SDRAM + 0x100, 149 .boot_params = S3C64XX_PA_SDRAM + 0x100,
152 .init_irq = s3c6410_init_irq, 150 .init_irq = s3c6410_init_irq,
153 .map_io = smartq_map_io, 151 .map_io = smartq_map_io,
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index e50a7d781732..e65375877d53 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -32,7 +32,7 @@
32 32
33#include "mach-smartq.h" 33#include "mach-smartq.h"
34 34
35static struct gpio_led smartq7_leds[] __initdata = { 35static struct gpio_led smartq7_leds[] = {
36 { 36 {
37 .name = "smartq7:red", 37 .name = "smartq7:red",
38 .active_low = 1, 38 .active_low = 1,
@@ -162,8 +162,6 @@ static void __init smartq7_machine_init(void)
162 162
163MACHINE_START(SMARTQ7, "SmartQ 7") 163MACHINE_START(SMARTQ7, "SmartQ 7")
164 /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */ 164 /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
165 .phys_io = S3C_PA_UART & 0xfff00000,
166 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
167 .boot_params = S3C64XX_PA_SDRAM + 0x100, 165 .boot_params = S3C64XX_PA_SDRAM + 0x100,
168 .init_irq = s3c6410_init_irq, 166 .init_irq = s3c6410_init_irq,
169 .map_io = smartq_map_io, 167 .map_io = smartq_map_io,
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index 59916676d8d2..3cca642f1e6d 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -85,8 +85,6 @@ static void __init smdk6400_machine_init(void)
85 85
86MACHINE_START(SMDK6400, "SMDK6400") 86MACHINE_START(SMDK6400, "SMDK6400")
87 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 87 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
88 .phys_io = S3C_PA_UART & 0xfff00000,
89 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
90 .boot_params = S3C64XX_PA_SDRAM + 0x100, 88 .boot_params = S3C64XX_PA_SDRAM + 0x100,
91 89
92 .init_irq = s3c6400_init_irq, 90 .init_irq = s3c6400_init_irq,
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index d498219fff1b..ec8865c03a19 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -704,8 +704,6 @@ static void __init smdk6410_machine_init(void)
704 704
705MACHINE_START(SMDK6410, "SMDK6410") 705MACHINE_START(SMDK6410, "SMDK6410")
706 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 706 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
707 .phys_io = S3C_PA_UART & 0xfff00000,
708 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
709 .boot_params = S3C64XX_PA_SDRAM + 0x100, 707 .boot_params = S3C64XX_PA_SDRAM + 0x100,
710 708
711 .init_irq = s3c6410_init_irq, 709 .init_irq = s3c6410_init_irq,
diff --git a/arch/arm/mach-s5p6440/Kconfig b/arch/arm/mach-s5p6440/Kconfig
deleted file mode 100644
index 6a4af7f57584..000000000000
--- a/arch/arm/mach-s5p6440/Kconfig
+++ /dev/null
@@ -1,33 +0,0 @@
1# arch/arm/mach-s5p6440/Kconfig
2#
3# Copyright (c) 2009 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8if ARCH_S5P6440
9
10config CPU_S5P6440
11 bool
12 select S3C_PL330_DMA
13 help
14 Enable S5P6440 CPU support
15
16config S5P6440_SETUP_I2C1
17 bool
18 help
19 Common setup code for i2c bus 1.
20
21config MACH_SMDK6440
22 bool "SMDK6440"
23 select CPU_S5P6440
24 select S3C_DEV_I2C1
25 select S3C_DEV_RTC
26 select S3C_DEV_WDT
27 select SAMSUNG_DEV_ADC
28 select SAMSUNG_DEV_TS
29 select S5P6440_SETUP_I2C1
30 help
31 Machine support for the Samsung SMDK6440
32
33endif
diff --git a/arch/arm/mach-s5p6440/Makefile b/arch/arm/mach-s5p6440/Makefile
deleted file mode 100644
index c3fe4d3662a9..000000000000
--- a/arch/arm/mach-s5p6440/Makefile
+++ /dev/null
@@ -1,25 +0,0 @@
1# arch/arm/mach-s5p6440/Makefile
2#
3# Copyright (c) 2009 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8obj-y :=
9obj-m :=
10obj-n :=
11obj- :=
12
13# Core support for S5P6440 system
14
15obj-$(CONFIG_CPU_S5P6440) += cpu.o init.o clock.o gpio.o dma.o
16obj-$(CONFIG_CPU_S5P6440) += setup-i2c0.o
17
18# machine support
19
20obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o
21
22# device support
23obj-y += dev-audio.o
24obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
25obj-$(CONFIG_S5P6440_SETUP_I2C1) += setup-i2c1.o
diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c
deleted file mode 100644
index ca6e48dce777..000000000000
--- a/arch/arm/mach-s5p6440/clock.c
+++ /dev/null
@@ -1,846 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/clock.c
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/sysdev.h>
21#include <linux/io.h>
22
23#include <mach/hardware.h>
24#include <mach/map.h>
25
26#include <plat/cpu-freq.h>
27#include <mach/regs-clock.h>
28#include <plat/clock.h>
29#include <plat/cpu.h>
30#include <plat/clock-clksrc.h>
31#include <plat/s5p-clock.h>
32#include <plat/pll.h>
33#include <plat/s5p6440.h>
34
35/* APLL Mux output clock */
36static struct clksrc_clk clk_mout_apll = {
37 .clk = {
38 .name = "mout_apll",
39 .id = -1,
40 },
41 .sources = &clk_src_apll,
42 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
43};
44
45static int s5p6440_epll_enable(struct clk *clk, int enable)
46{
47 unsigned int ctrlbit = clk->ctrlbit;
48 unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
49
50 if (enable)
51 __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
52 else
53 __raw_writel(epll_con, S5P_EPLL_CON);
54
55 return 0;
56}
57
58static unsigned long s5p6440_epll_get_rate(struct clk *clk)
59{
60 return clk->rate;
61}
62
63static u32 epll_div[][5] = {
64 { 36000000, 0, 48, 1, 4 },
65 { 48000000, 0, 32, 1, 3 },
66 { 60000000, 0, 40, 1, 3 },
67 { 72000000, 0, 48, 1, 3 },
68 { 84000000, 0, 28, 1, 2 },
69 { 96000000, 0, 32, 1, 2 },
70 { 32768000, 45264, 43, 1, 4 },
71 { 45158000, 6903, 30, 1, 3 },
72 { 49152000, 50332, 32, 1, 3 },
73 { 67738000, 10398, 45, 1, 3 },
74 { 73728000, 9961, 49, 1, 3 }
75};
76
77static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
78{
79 unsigned int epll_con, epll_con_k;
80 unsigned int i;
81
82 if (clk->rate == rate) /* Return if nothing changed */
83 return 0;
84
85 epll_con = __raw_readl(S5P_EPLL_CON);
86 epll_con_k = __raw_readl(S5P_EPLL_CON_K);
87
88 epll_con_k &= ~(PLL90XX_KDIV_MASK);
89 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
90
91 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
92 if (epll_div[i][0] == rate) {
93 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
94 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
95 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
96 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
97 break;
98 }
99 }
100
101 if (i == ARRAY_SIZE(epll_div)) {
102 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
103 return -EINVAL;
104 }
105
106 __raw_writel(epll_con, S5P_EPLL_CON);
107 __raw_writel(epll_con_k, S5P_EPLL_CON_K);
108
109 clk->rate = rate;
110
111 return 0;
112}
113
114static struct clk_ops s5p6440_epll_ops = {
115 .get_rate = s5p6440_epll_get_rate,
116 .set_rate = s5p6440_epll_set_rate,
117};
118
119static struct clksrc_clk clk_mout_epll = {
120 .clk = {
121 .name = "mout_epll",
122 .id = -1,
123 },
124 .sources = &clk_src_epll,
125 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 2, .size = 1 },
126};
127
128static struct clksrc_clk clk_mout_mpll = {
129 .clk = {
130 .name = "mout_mpll",
131 .id = -1,
132 },
133 .sources = &clk_src_mpll,
134 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 },
135};
136
137enum perf_level {
138 L0 = 532*1000,
139 L1 = 266*1000,
140 L2 = 133*1000,
141};
142
143static const u32 clock_table[][3] = {
144 /*{ARM_CLK, DIVarm, DIVhclk}*/
145 {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P_CLKDIV0_HCLK_SHIFT)},
146 {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P_CLKDIV0_HCLK_SHIFT)},
147 {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P_CLKDIV0_HCLK_SHIFT)},
148};
149
150static unsigned long s5p6440_armclk_get_rate(struct clk *clk)
151{
152 unsigned long rate = clk_get_rate(clk->parent);
153 u32 clkdiv;
154
155 /* divisor mask starts at bit0, so no need to shift */
156 clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK;
157
158 return rate / (clkdiv + 1);
159}
160
161static unsigned long s5p6440_armclk_round_rate(struct clk *clk,
162 unsigned long rate)
163{
164 u32 iter;
165
166 for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
167 if (rate > clock_table[iter][0])
168 return clock_table[iter-1][0];
169 }
170
171 return clock_table[ARRAY_SIZE(clock_table) - 1][0];
172}
173
174static int s5p6440_armclk_set_rate(struct clk *clk, unsigned long rate)
175{
176 u32 round_tmp;
177 u32 iter;
178 u32 clk_div0_tmp;
179 u32 cur_rate = clk->ops->get_rate(clk);
180 unsigned long flags;
181
182 round_tmp = clk->ops->round_rate(clk, rate);
183 if (round_tmp == cur_rate)
184 return 0;
185
186
187 for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
188 if (round_tmp == clock_table[iter][0])
189 break;
190 }
191
192 if (iter >= ARRAY_SIZE(clock_table))
193 iter = ARRAY_SIZE(clock_table) - 1;
194
195 local_irq_save(flags);
196 if (cur_rate > round_tmp) {
197 /* Frequency Down */
198 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
199 clk_div0_tmp |= clock_table[iter][1];
200 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
201
202 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
203 ~(S5P_CLKDIV0_HCLK_MASK);
204 clk_div0_tmp |= clock_table[iter][2];
205 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
206
207
208 } else {
209 /* Frequency Up */
210 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
211 ~(S5P_CLKDIV0_HCLK_MASK);
212 clk_div0_tmp |= clock_table[iter][2];
213 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
214
215 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
216 clk_div0_tmp |= clock_table[iter][1];
217 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
218 }
219 local_irq_restore(flags);
220
221 clk->rate = clock_table[iter][0];
222
223 return 0;
224}
225
226static struct clk_ops s5p6440_clkarm_ops = {
227 .get_rate = s5p6440_armclk_get_rate,
228 .set_rate = s5p6440_armclk_set_rate,
229 .round_rate = s5p6440_armclk_round_rate,
230};
231
232static struct clksrc_clk clk_armclk = {
233 .clk = {
234 .name = "armclk",
235 .id = 1,
236 .parent = &clk_mout_apll.clk,
237 .ops = &s5p6440_clkarm_ops,
238 },
239 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 },
240};
241
242static struct clksrc_clk clk_dout_mpll = {
243 .clk = {
244 .name = "dout_mpll",
245 .id = -1,
246 .parent = &clk_mout_mpll.clk,
247 },
248 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 },
249};
250
251static struct clksrc_clk clk_hclk = {
252 .clk = {
253 .name = "clk_hclk",
254 .id = -1,
255 .parent = &clk_armclk.clk,
256 },
257 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 },
258};
259
260static struct clksrc_clk clk_pclk = {
261 .clk = {
262 .name = "clk_pclk",
263 .id = -1,
264 .parent = &clk_hclk.clk,
265 },
266 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 },
267};
268
269static struct clk *clkset_hclklow_list[] = {
270 &clk_mout_apll.clk,
271 &clk_mout_mpll.clk,
272};
273
274static struct clksrc_sources clkset_hclklow = {
275 .sources = clkset_hclklow_list,
276 .nr_sources = ARRAY_SIZE(clkset_hclklow_list),
277};
278
279static struct clksrc_clk clk_hclk_low = {
280 .clk = {
281 .name = "hclk_low",
282 .id = -1,
283 },
284 .sources = &clkset_hclklow,
285 .reg_src = { .reg = S5P_SYS_OTHERS, .shift = 6, .size = 1 },
286 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
287};
288
289static struct clksrc_clk clk_pclk_low = {
290 .clk = {
291 .name = "pclk_low",
292 .id = -1,
293 .parent = &clk_hclk_low.clk,
294 },
295 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
296};
297
298int s5p6440_clk48m_ctrl(struct clk *clk, int enable)
299{
300 unsigned long flags;
301 u32 val;
302
303 /* can't rely on clock lock, this register has other usages */
304 local_irq_save(flags);
305
306 val = __raw_readl(S5P_OTHERS);
307 if (enable)
308 val |= S5P_OTHERS_USB_SIG_MASK;
309 else
310 val &= ~S5P_OTHERS_USB_SIG_MASK;
311
312 __raw_writel(val, S5P_OTHERS);
313
314 local_irq_restore(flags);
315
316 return 0;
317}
318
319static int s5p6440_pclk_ctrl(struct clk *clk, int enable)
320{
321 return s5p_gatectrl(S5P_CLK_GATE_PCLK, clk, enable);
322}
323
324static int s5p6440_hclk0_ctrl(struct clk *clk, int enable)
325{
326 return s5p_gatectrl(S5P_CLK_GATE_HCLK0, clk, enable);
327}
328
329static int s5p6440_hclk1_ctrl(struct clk *clk, int enable)
330{
331 return s5p_gatectrl(S5P_CLK_GATE_HCLK1, clk, enable);
332}
333
334static int s5p6440_sclk_ctrl(struct clk *clk, int enable)
335{
336 return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable);
337}
338
339static int s5p6440_sclk1_ctrl(struct clk *clk, int enable)
340{
341 return s5p_gatectrl(S5P_CLK_GATE_SCLK1, clk, enable);
342}
343
344static int s5p6440_mem_ctrl(struct clk *clk, int enable)
345{
346 return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable);
347}
348
349/*
350 * The following clocks will be disabled during clock initialization. It is
351 * recommended to keep the following clocks disabled until the driver requests
352 * for enabling the clock.
353 */
354static struct clk init_clocks_disable[] = {
355 {
356 .name = "nand",
357 .id = -1,
358 .parent = &clk_hclk.clk,
359 .enable = s5p6440_mem_ctrl,
360 .ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON,
361 }, {
362 .name = "adc",
363 .id = -1,
364 .parent = &clk_pclk_low.clk,
365 .enable = s5p6440_pclk_ctrl,
366 .ctrlbit = S5P_CLKCON_PCLK_TSADC,
367 }, {
368 .name = "i2c",
369 .id = -1,
370 .parent = &clk_pclk_low.clk,
371 .enable = s5p6440_pclk_ctrl,
372 .ctrlbit = S5P_CLKCON_PCLK_IIC0,
373 }, {
374 .name = "i2s_v40",
375 .id = 0,
376 .parent = &clk_pclk_low.clk,
377 .enable = s5p6440_pclk_ctrl,
378 .ctrlbit = S5P_CLKCON_PCLK_IIS2,
379 }, {
380 .name = "spi",
381 .id = 0,
382 .parent = &clk_pclk_low.clk,
383 .enable = s5p6440_pclk_ctrl,
384 .ctrlbit = S5P_CLKCON_PCLK_SPI0,
385 }, {
386 .name = "spi",
387 .id = 1,
388 .parent = &clk_pclk_low.clk,
389 .enable = s5p6440_pclk_ctrl,
390 .ctrlbit = S5P_CLKCON_PCLK_SPI1,
391 }, {
392 .name = "sclk_spi_48",
393 .id = 0,
394 .parent = &clk_48m,
395 .enable = s5p6440_sclk_ctrl,
396 .ctrlbit = S5P_CLKCON_SCLK0_SPI0_48,
397 }, {
398 .name = "sclk_spi_48",
399 .id = 1,
400 .parent = &clk_48m,
401 .enable = s5p6440_sclk_ctrl,
402 .ctrlbit = S5P_CLKCON_SCLK0_SPI1_48,
403 }, {
404 .name = "mmc_48m",
405 .id = 0,
406 .parent = &clk_48m,
407 .enable = s5p6440_sclk_ctrl,
408 .ctrlbit = S5P_CLKCON_SCLK0_MMC0_48,
409 }, {
410 .name = "mmc_48m",
411 .id = 1,
412 .parent = &clk_48m,
413 .enable = s5p6440_sclk_ctrl,
414 .ctrlbit = S5P_CLKCON_SCLK0_MMC1_48,
415 }, {
416 .name = "mmc_48m",
417 .id = 2,
418 .parent = &clk_48m,
419 .enable = s5p6440_sclk_ctrl,
420 .ctrlbit = S5P_CLKCON_SCLK0_MMC2_48,
421 }, {
422 .name = "otg",
423 .id = -1,
424 .parent = &clk_hclk_low.clk,
425 .enable = s5p6440_hclk0_ctrl,
426 .ctrlbit = S5P_CLKCON_HCLK0_USB
427 }, {
428 .name = "post",
429 .id = -1,
430 .parent = &clk_hclk_low.clk,
431 .enable = s5p6440_hclk0_ctrl,
432 .ctrlbit = S5P_CLKCON_HCLK0_POST0
433 }, {
434 .name = "lcd",
435 .id = -1,
436 .parent = &clk_hclk_low.clk,
437 .enable = s5p6440_hclk1_ctrl,
438 .ctrlbit = S5P_CLKCON_HCLK1_DISPCON,
439 }, {
440 .name = "hsmmc",
441 .id = 0,
442 .parent = &clk_hclk_low.clk,
443 .enable = s5p6440_hclk0_ctrl,
444 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC0,
445 }, {
446 .name = "hsmmc",
447 .id = 1,
448 .parent = &clk_hclk_low.clk,
449 .enable = s5p6440_hclk0_ctrl,
450 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC1,
451 }, {
452 .name = "hsmmc",
453 .id = 2,
454 .parent = &clk_hclk_low.clk,
455 .enable = s5p6440_hclk0_ctrl,
456 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC2,
457 }, {
458 .name = "rtc",
459 .id = -1,
460 .parent = &clk_pclk_low.clk,
461 .enable = s5p6440_pclk_ctrl,
462 .ctrlbit = S5P_CLKCON_PCLK_RTC,
463 }, {
464 .name = "watchdog",
465 .id = -1,
466 .parent = &clk_pclk_low.clk,
467 .enable = s5p6440_pclk_ctrl,
468 .ctrlbit = S5P_CLKCON_PCLK_WDT,
469 }, {
470 .name = "timers",
471 .id = -1,
472 .parent = &clk_pclk_low.clk,
473 .enable = s5p6440_pclk_ctrl,
474 .ctrlbit = S5P_CLKCON_PCLK_PWM,
475 }, {
476 .name = "hclk_fimgvg",
477 .id = -1,
478 .parent = &clk_hclk.clk,
479 .enable = s5p6440_hclk1_ctrl,
480 .ctrlbit = (1 << 2),
481 }, {
482 .name = "tsi",
483 .id = -1,
484 .parent = &clk_hclk_low.clk,
485 .enable = s5p6440_hclk1_ctrl,
486 .ctrlbit = (1 << 0),
487 }, {
488 .name = "pclk_fimgvg",
489 .id = -1,
490 .parent = &clk_pclk.clk,
491 .enable = s5p6440_pclk_ctrl,
492 .ctrlbit = (1 << 31),
493 }, {
494 .name = "dmc0",
495 .id = -1,
496 .parent = &clk_pclk.clk,
497 .enable = s5p6440_pclk_ctrl,
498 .ctrlbit = (1 << 30),
499 }, {
500 .name = "etm",
501 .id = -1,
502 .parent = &clk_pclk.clk,
503 .enable = s5p6440_pclk_ctrl,
504 .ctrlbit = (1 << 29),
505 }, {
506 .name = "dsim",
507 .id = -1,
508 .parent = &clk_pclk_low.clk,
509 .enable = s5p6440_pclk_ctrl,
510 .ctrlbit = (1 << 28),
511 }, {
512 .name = "gps",
513 .id = -1,
514 .parent = &clk_pclk_low.clk,
515 .enable = s5p6440_pclk_ctrl,
516 .ctrlbit = (1 << 25),
517 }, {
518 .name = "pcm",
519 .id = -1,
520 .parent = &clk_pclk_low.clk,
521 .enable = s5p6440_pclk_ctrl,
522 .ctrlbit = (1 << 8),
523 }, {
524 .name = "irom",
525 .id = -1,
526 .parent = &clk_hclk.clk,
527 .enable = s5p6440_hclk0_ctrl,
528 .ctrlbit = (1 << 25),
529 }, {
530 .name = "dma",
531 .id = -1,
532 .parent = &clk_hclk_low.clk,
533 .enable = s5p6440_hclk0_ctrl,
534 .ctrlbit = (1 << 12),
535 }, {
536 .name = "2d",
537 .id = -1,
538 .parent = &clk_hclk.clk,
539 .enable = s5p6440_hclk0_ctrl,
540 .ctrlbit = (1 << 8),
541 },
542};
543
544/*
545 * The following clocks will be enabled during clock initialization.
546 */
547static struct clk init_clocks[] = {
548 {
549 .name = "gpio",
550 .id = -1,
551 .parent = &clk_pclk_low.clk,
552 .enable = s5p6440_pclk_ctrl,
553 .ctrlbit = S5P_CLKCON_PCLK_GPIO,
554 }, {
555 .name = "uart",
556 .id = 0,
557 .parent = &clk_pclk_low.clk,
558 .enable = s5p6440_pclk_ctrl,
559 .ctrlbit = S5P_CLKCON_PCLK_UART0,
560 }, {
561 .name = "uart",
562 .id = 1,
563 .parent = &clk_pclk_low.clk,
564 .enable = s5p6440_pclk_ctrl,
565 .ctrlbit = S5P_CLKCON_PCLK_UART1,
566 }, {
567 .name = "uart",
568 .id = 2,
569 .parent = &clk_pclk_low.clk,
570 .enable = s5p6440_pclk_ctrl,
571 .ctrlbit = S5P_CLKCON_PCLK_UART2,
572 }, {
573 .name = "uart",
574 .id = 3,
575 .parent = &clk_pclk_low.clk,
576 .enable = s5p6440_pclk_ctrl,
577 .ctrlbit = S5P_CLKCON_PCLK_UART3,
578 }, {
579 .name = "mem",
580 .id = -1,
581 .parent = &clk_hclk.clk,
582 .enable = s5p6440_hclk0_ctrl,
583 .ctrlbit = (1 << 21),
584 }, {
585 .name = "intc",
586 .id = -1,
587 .parent = &clk_hclk.clk,
588 .enable = s5p6440_hclk0_ctrl,
589 .ctrlbit = (1 << 1),
590 },
591};
592
593static struct clk clk_iis_cd_v40 = {
594 .name = "iis_cdclk_v40",
595 .id = -1,
596};
597
598static struct clk clk_pcm_cd = {
599 .name = "pcm_cdclk",
600 .id = -1,
601};
602
603static struct clk *clkset_group1_list[] = {
604 &clk_mout_epll.clk,
605 &clk_dout_mpll.clk,
606 &clk_fin_epll,
607};
608
609static struct clksrc_sources clkset_group1 = {
610 .sources = clkset_group1_list,
611 .nr_sources = ARRAY_SIZE(clkset_group1_list),
612};
613
614static struct clk *clkset_uart_list[] = {
615 &clk_mout_epll.clk,
616 &clk_dout_mpll.clk,
617};
618
619static struct clksrc_sources clkset_uart = {
620 .sources = clkset_uart_list,
621 .nr_sources = ARRAY_SIZE(clkset_uart_list),
622};
623
624static struct clk *clkset_audio_list[] = {
625 &clk_mout_epll.clk,
626 &clk_dout_mpll.clk,
627 &clk_fin_epll,
628 &clk_iis_cd_v40,
629 &clk_pcm_cd,
630};
631
632static struct clksrc_sources clkset_audio = {
633 .sources = clkset_audio_list,
634 .nr_sources = ARRAY_SIZE(clkset_audio_list),
635};
636
637static struct clksrc_clk clksrcs[] = {
638 {
639 .clk = {
640 .name = "mmc_bus",
641 .id = 0,
642 .ctrlbit = S5P_CLKCON_SCLK0_MMC0,
643 .enable = s5p6440_sclk_ctrl,
644 },
645 .sources = &clkset_group1,
646 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 },
647 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 },
648 }, {
649 .clk = {
650 .name = "mmc_bus",
651 .id = 1,
652 .ctrlbit = S5P_CLKCON_SCLK0_MMC1,
653 .enable = s5p6440_sclk_ctrl,
654 },
655 .sources = &clkset_group1,
656 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 },
657 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 },
658 }, {
659 .clk = {
660 .name = "mmc_bus",
661 .id = 2,
662 .ctrlbit = S5P_CLKCON_SCLK0_MMC2,
663 .enable = s5p6440_sclk_ctrl,
664 },
665 .sources = &clkset_group1,
666 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 },
667 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 },
668 }, {
669 .clk = {
670 .name = "uclk1",
671 .id = -1,
672 .ctrlbit = S5P_CLKCON_SCLK0_UART,
673 .enable = s5p6440_sclk_ctrl,
674 },
675 .sources = &clkset_uart,
676 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 13, .size = 1 },
677 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
678 }, {
679 .clk = {
680 .name = "spi_epll",
681 .id = 0,
682 .ctrlbit = S5P_CLKCON_SCLK0_SPI0,
683 .enable = s5p6440_sclk_ctrl,
684 },
685 .sources = &clkset_group1,
686 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 },
687 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
688 }, {
689 .clk = {
690 .name = "spi_epll",
691 .id = 1,
692 .ctrlbit = S5P_CLKCON_SCLK0_SPI1,
693 .enable = s5p6440_sclk_ctrl,
694 },
695 .sources = &clkset_group1,
696 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 },
697 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
698 }, {
699 .clk = {
700 .name = "sclk_post",
701 .id = -1,
702 .ctrlbit = (1 << 10),
703 .enable = s5p6440_sclk_ctrl,
704 },
705 .sources = &clkset_group1,
706 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 26, .size = 2 },
707 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
708 }, {
709 .clk = {
710 .name = "sclk_dispcon",
711 .id = -1,
712 .ctrlbit = (1 << 1),
713 .enable = s5p6440_sclk1_ctrl,
714 },
715 .sources = &clkset_group1,
716 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
717 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
718 }, {
719 .clk = {
720 .name = "sclk_fimgvg",
721 .id = -1,
722 .ctrlbit = (1 << 2),
723 .enable = s5p6440_sclk1_ctrl,
724 },
725 .sources = &clkset_group1,
726 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
727 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
728 }, {
729 .clk = {
730 .name = "sclk_audio2",
731 .id = -1,
732 .ctrlbit = (1 << 11),
733 .enable = s5p6440_sclk_ctrl,
734 },
735 .sources = &clkset_audio,
736 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 3 },
737 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 24, .size = 4 },
738 },
739};
740
741/* Clock initialisation code */
742static struct clksrc_clk *sysclks[] = {
743 &clk_mout_apll,
744 &clk_mout_epll,
745 &clk_mout_mpll,
746 &clk_dout_mpll,
747 &clk_armclk,
748 &clk_hclk,
749 &clk_pclk,
750 &clk_hclk_low,
751 &clk_pclk_low,
752};
753
754void __init_or_cpufreq s5p6440_setup_clocks(void)
755{
756 struct clk *xtal_clk;
757 unsigned long xtal;
758 unsigned long fclk;
759 unsigned long hclk;
760 unsigned long hclk_low;
761 unsigned long pclk;
762 unsigned long pclk_low;
763 unsigned long epll;
764 unsigned long apll;
765 unsigned long mpll;
766 unsigned int ptr;
767
768 /* Set S5P6440 functions for clk_fout_epll */
769 clk_fout_epll.enable = s5p6440_epll_enable;
770 clk_fout_epll.ops = &s5p6440_epll_ops;
771
772 clk_48m.enable = s5p6440_clk48m_ctrl;
773
774 xtal_clk = clk_get(NULL, "ext_xtal");
775 BUG_ON(IS_ERR(xtal_clk));
776
777 xtal = clk_get_rate(xtal_clk);
778 clk_put(xtal_clk);
779
780 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P_EPLL_CON),
781 __raw_readl(S5P_EPLL_CON_K));
782 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
783 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502);
784
785 clk_fout_mpll.rate = mpll;
786 clk_fout_epll.rate = epll;
787 clk_fout_apll.rate = apll;
788
789 printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
790 " E=%ld.%ldMHz\n",
791 print_mhz(apll), print_mhz(mpll), print_mhz(epll));
792
793 fclk = clk_get_rate(&clk_armclk.clk);
794 hclk = clk_get_rate(&clk_hclk.clk);
795 pclk = clk_get_rate(&clk_pclk.clk);
796 hclk_low = clk_get_rate(&clk_hclk_low.clk);
797 pclk_low = clk_get_rate(&clk_pclk_low.clk);
798
799 printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
800 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
801 print_mhz(hclk), print_mhz(hclk_low),
802 print_mhz(pclk), print_mhz(pclk_low));
803
804 clk_f.rate = fclk;
805 clk_h.rate = hclk;
806 clk_p.rate = pclk;
807
808 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
809 s3c_set_clksrc(&clksrcs[ptr], true);
810}
811
812static struct clk *clks[] __initdata = {
813 &clk_ext,
814 &clk_iis_cd_v40,
815 &clk_pcm_cd,
816};
817
818void __init s5p6440_register_clocks(void)
819{
820 struct clk *clkp;
821 int ret;
822 int ptr;
823
824 ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
825 if (ret > 0)
826 printk(KERN_ERR "Failed to register %u clocks\n", ret);
827
828 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
829 s3c_register_clksrc(sysclks[ptr], 1);
830
831 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
832 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
833
834 clkp = init_clocks_disable;
835 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
836
837 ret = s3c24xx_register_clock(clkp);
838 if (ret < 0) {
839 printk(KERN_ERR "Failed to register clock %s (%d)\n",
840 clkp->name, ret);
841 }
842 (clkp->enable)(clkp, 0);
843 }
844
845 s3c_pwmclk_init();
846}
diff --git a/arch/arm/mach-s5p6440/cpu.c b/arch/arm/mach-s5p6440/cpu.c
deleted file mode 100644
index ec592e866054..000000000000
--- a/arch/arm/mach-s5p6440/cpu.c
+++ /dev/null
@@ -1,117 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/cpu.c
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/interrupt.h>
14#include <linux/list.h>
15#include <linux/timer.h>
16#include <linux/init.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/sysdev.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22#include <linux/sched.h>
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/mach/irq.h>
27
28#include <asm/proc-fns.h>
29
30#include <mach/hardware.h>
31#include <mach/map.h>
32#include <asm/irq.h>
33
34#include <plat/regs-serial.h>
35#include <mach/regs-clock.h>
36
37#include <plat/cpu.h>
38#include <plat/devs.h>
39#include <plat/clock.h>
40#include <plat/s5p6440.h>
41#include <plat/adc-core.h>
42
43static void s5p6440_idle(void)
44{
45 unsigned long val;
46
47 if (!need_resched()) {
48 val = __raw_readl(S5P_PWR_CFG);
49 val &= ~(0x3<<5);
50 val |= (0x1<<5);
51 __raw_writel(val, S5P_PWR_CFG);
52
53 cpu_do_idle();
54 }
55 local_irq_enable();
56}
57
58/* s5p6440_map_io
59 *
60 * register the standard cpu IO areas
61*/
62
63void __init s5p6440_map_io(void)
64{
65 /* initialize any device information early */
66 s3c_adc_setname("s3c64xx-adc");
67}
68
69void __init s5p6440_init_clocks(int xtal)
70{
71 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
72
73 s3c24xx_register_baseclocks(xtal);
74 s5p_register_clocks(xtal);
75 s5p6440_register_clocks();
76 s5p6440_setup_clocks();
77}
78
79void __init s5p6440_init_irq(void)
80{
81 /* S5P6440 supports only 2 VIC */
82 u32 vic[2];
83
84 /*
85 * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
86 * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
87 */
88 vic[0] = 0xff800ae7;
89 vic[1] = 0xffbf23e5;
90
91 s5p_init_irq(vic, ARRAY_SIZE(vic));
92}
93
94struct sysdev_class s5p6440_sysclass = {
95 .name = "s5p6440-core",
96};
97
98static struct sys_device s5p6440_sysdev = {
99 .cls = &s5p6440_sysclass,
100};
101
102static int __init s5p6440_core_init(void)
103{
104 return sysdev_class_register(&s5p6440_sysclass);
105}
106
107core_initcall(s5p6440_core_init);
108
109int __init s5p6440_init(void)
110{
111 printk(KERN_INFO "S5P6440: Initializing architecture\n");
112
113 /* set idle function */
114 pm_idle = s5p6440_idle;
115
116 return sysdev_register(&s5p6440_sysdev);
117}
diff --git a/arch/arm/mach-s5p6440/dev-audio.c b/arch/arm/mach-s5p6440/dev-audio.c
deleted file mode 100644
index 3ca0d2b8275d..000000000000
--- a/arch/arm/mach-s5p6440/dev-audio.c
+++ /dev/null
@@ -1,127 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/dev-audio.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co. Ltd
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <plat/gpio-cfg.h>
16#include <plat/audio.h>
17
18#include <mach/map.h>
19#include <mach/dma.h>
20#include <mach/irqs.h>
21
22static int s5p6440_cfg_i2s(struct platform_device *pdev)
23{
24 /* configure GPIO for i2s port */
25 switch (pdev->id) {
26 case -1:
27 s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5));
28 s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5));
29 s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5));
30 s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5));
31 s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5));
32 s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5));
33 s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5));
34 break;
35
36 default:
37 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
38 return -EINVAL;
39 }
40
41 return 0;
42}
43
44static struct s3c_audio_pdata s3c_i2s_pdata = {
45 .cfg_gpio = s5p6440_cfg_i2s,
46};
47
48static struct resource s5p6440_iis0_resource[] = {
49 [0] = {
50 .start = S5P6440_PA_I2S,
51 .end = S5P6440_PA_I2S + 0x100 - 1,
52 .flags = IORESOURCE_MEM,
53 },
54 [1] = {
55 .start = DMACH_I2S0_TX,
56 .end = DMACH_I2S0_TX,
57 .flags = IORESOURCE_DMA,
58 },
59 [2] = {
60 .start = DMACH_I2S0_RX,
61 .end = DMACH_I2S0_RX,
62 .flags = IORESOURCE_DMA,
63 },
64};
65
66struct platform_device s5p6440_device_iis = {
67 .name = "s3c64xx-iis-v4",
68 .id = -1,
69 .num_resources = ARRAY_SIZE(s5p6440_iis0_resource),
70 .resource = s5p6440_iis0_resource,
71 .dev = {
72 .platform_data = &s3c_i2s_pdata,
73 },
74};
75
76/* PCM Controller platform_devices */
77
78static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
79{
80 switch (pdev->id) {
81 case 0:
82 s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2));
83 s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2));
84 s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2));
85 s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2));
86 s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2));
87 break;
88
89 default:
90 printk(KERN_DEBUG "Invalid PCM Controller number!");
91 return -EINVAL;
92 }
93
94 return 0;
95}
96
97static struct s3c_audio_pdata s3c_pcm_pdata = {
98 .cfg_gpio = s5p6440_pcm_cfg_gpio,
99};
100
101static struct resource s5p6440_pcm0_resource[] = {
102 [0] = {
103 .start = S5P6440_PA_PCM,
104 .end = S5P6440_PA_PCM + 0x100 - 1,
105 .flags = IORESOURCE_MEM,
106 },
107 [1] = {
108 .start = DMACH_PCM0_TX,
109 .end = DMACH_PCM0_TX,
110 .flags = IORESOURCE_DMA,
111 },
112 [2] = {
113 .start = DMACH_PCM0_RX,
114 .end = DMACH_PCM0_RX,
115 .flags = IORESOURCE_DMA,
116 },
117};
118
119struct platform_device s5p6440_device_pcm = {
120 .name = "samsung-pcm",
121 .id = 0,
122 .num_resources = ARRAY_SIZE(s5p6440_pcm0_resource),
123 .resource = s5p6440_pcm0_resource,
124 .dev = {
125 .platform_data = &s3c_pcm_pdata,
126 },
127};
diff --git a/arch/arm/mach-s5p6440/dev-spi.c b/arch/arm/mach-s5p6440/dev-spi.c
deleted file mode 100644
index 510af44d180c..000000000000
--- a/arch/arm/mach-s5p6440/dev-spi.c
+++ /dev/null
@@ -1,176 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/dev-spi.c
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <mach/dma.h>
16#include <mach/map.h>
17#include <mach/irqs.h>
18#include <mach/spi-clocks.h>
19
20#include <plat/s3c64xx-spi.h>
21#include <plat/gpio-cfg.h>
22
23static char *spi_src_clks[] = {
24 [S5P6440_SPI_SRCCLK_PCLK] = "pclk",
25 [S5P6440_SPI_SRCCLK_SCLK] = "spi_epll",
26};
27
28/* SPI Controller platform_devices */
29
30/* Since we emulate multi-cs capability, we do not touch the CS.
31 * The emulated CS is toggled by board specific mechanism, as it can
32 * be either some immediate GPIO or some signal out of some other
33 * chip in between ... or some yet another way.
34 * We simply do not assume anything about CS.
35 */
36static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
37{
38 switch (pdev->id) {
39 case 0:
40 s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2));
41 s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2));
42 s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2));
43 s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
44 s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
45 s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
46 break;
47
48 case 1:
49 s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2));
50 s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2));
51 s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2));
52 s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
53 s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
54 s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
55 break;
56
57 default:
58 dev_err(&pdev->dev, "Invalid SPI Controller number!");
59 return -EINVAL;
60 }
61
62 return 0;
63}
64
65static struct resource s5p6440_spi0_resource[] = {
66 [0] = {
67 .start = S5P6440_PA_SPI0,
68 .end = S5P6440_PA_SPI0 + 0x100 - 1,
69 .flags = IORESOURCE_MEM,
70 },
71 [1] = {
72 .start = DMACH_SPI0_TX,
73 .end = DMACH_SPI0_TX,
74 .flags = IORESOURCE_DMA,
75 },
76 [2] = {
77 .start = DMACH_SPI0_RX,
78 .end = DMACH_SPI0_RX,
79 .flags = IORESOURCE_DMA,
80 },
81 [3] = {
82 .start = IRQ_SPI0,
83 .end = IRQ_SPI0,
84 .flags = IORESOURCE_IRQ,
85 },
86};
87
88static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
89 .cfg_gpio = s5p6440_spi_cfg_gpio,
90 .fifo_lvl_mask = 0x1ff,
91 .rx_lvl_offset = 15,
92};
93
94static u64 spi_dmamask = DMA_BIT_MASK(32);
95
96struct platform_device s5p6440_device_spi0 = {
97 .name = "s3c64xx-spi",
98 .id = 0,
99 .num_resources = ARRAY_SIZE(s5p6440_spi0_resource),
100 .resource = s5p6440_spi0_resource,
101 .dev = {
102 .dma_mask = &spi_dmamask,
103 .coherent_dma_mask = DMA_BIT_MASK(32),
104 .platform_data = &s5p6440_spi0_pdata,
105 },
106};
107
108static struct resource s5p6440_spi1_resource[] = {
109 [0] = {
110 .start = S5P6440_PA_SPI1,
111 .end = S5P6440_PA_SPI1 + 0x100 - 1,
112 .flags = IORESOURCE_MEM,
113 },
114 [1] = {
115 .start = DMACH_SPI1_TX,
116 .end = DMACH_SPI1_TX,
117 .flags = IORESOURCE_DMA,
118 },
119 [2] = {
120 .start = DMACH_SPI1_RX,
121 .end = DMACH_SPI1_RX,
122 .flags = IORESOURCE_DMA,
123 },
124 [3] = {
125 .start = IRQ_SPI1,
126 .end = IRQ_SPI1,
127 .flags = IORESOURCE_IRQ,
128 },
129};
130
131static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
132 .cfg_gpio = s5p6440_spi_cfg_gpio,
133 .fifo_lvl_mask = 0x7f,
134 .rx_lvl_offset = 15,
135};
136
137struct platform_device s5p6440_device_spi1 = {
138 .name = "s3c64xx-spi",
139 .id = 1,
140 .num_resources = ARRAY_SIZE(s5p6440_spi1_resource),
141 .resource = s5p6440_spi1_resource,
142 .dev = {
143 .dma_mask = &spi_dmamask,
144 .coherent_dma_mask = DMA_BIT_MASK(32),
145 .platform_data = &s5p6440_spi1_pdata,
146 },
147};
148
149void __init s5p6440_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
150{
151 struct s3c64xx_spi_info *pd;
152
153 /* Reject invalid configuration */
154 if (!num_cs || src_clk_nr < 0
155 || src_clk_nr > S5P6440_SPI_SRCCLK_SCLK) {
156 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
157 return;
158 }
159
160 switch (cntrlr) {
161 case 0:
162 pd = &s5p6440_spi0_pdata;
163 break;
164 case 1:
165 pd = &s5p6440_spi1_pdata;
166 break;
167 default:
168 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
169 __func__, cntrlr);
170 return;
171 }
172
173 pd->num_cs = num_cs;
174 pd->src_clk_nr = src_clk_nr;
175 pd->src_clk_name = spi_src_clks[src_clk_nr];
176}
diff --git a/arch/arm/mach-s5p6440/include/mach/debug-macro.S b/arch/arm/mach-s5p6440/include/mach/debug-macro.S
deleted file mode 100644
index 1347d7f99079..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/debug-macro.S
+++ /dev/null
@@ -1,37 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/debug-macro.S
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11/* pull in the relevant register and map files. */
12
13#include <mach/map.h>
14#include <plat/regs-serial.h>
15
16 /* note, for the boot process to work we have to keep the UART
17 * virtual address aligned to an 1MiB boundary for the L1
18 * mapping the head code makes. We keep the UART virtual address
19 * aligned and add in the offset when we load the value here.
20 */
21
22 .macro addruart, rx, rtmp
23 mrc p15, 0, \rx, c1, c0
24 tst \rx, #1
25 ldreq \rx, = S3C_PA_UART
26 ldrne \rx, = S3C_VA_UART
27#if CONFIG_DEBUG_S3C_UART != 0
28 add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
29#endif
30 .endm
31
32/* include the reset of the code which will do the work, we're only
33 * compiling for a single cpu processor type so the default of s3c2440
34 * will be fine with us.
35 */
36
37#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5p6440/include/mach/gpio.h b/arch/arm/mach-s5p6440/include/mach/gpio.h
deleted file mode 100644
index 21783834f2a2..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/gpio.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/gpio.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16#define gpio_get_value __gpio_get_value
17#define gpio_set_value __gpio_set_value
18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq
20
21/* GPIO bank sizes */
22#define S5P6440_GPIO_A_NR (6)
23#define S5P6440_GPIO_B_NR (7)
24#define S5P6440_GPIO_C_NR (8)
25#define S5P6440_GPIO_F_NR (2)
26#define S5P6440_GPIO_G_NR (7)
27#define S5P6440_GPIO_H_NR (10)
28#define S5P6440_GPIO_I_NR (16)
29#define S5P6440_GPIO_J_NR (12)
30#define S5P6440_GPIO_N_NR (16)
31#define S5P6440_GPIO_P_NR (8)
32#define S5P6440_GPIO_R_NR (15)
33
34/* GPIO bank numbers */
35
36/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
37 * space for debugging purposes so that any accidental
38 * change from one gpio bank to another can be caught.
39*/
40#define S5P6440_GPIO_NEXT(__gpio) \
41 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
42
43enum s5p_gpio_number {
44 S5P6440_GPIO_A_START = 0,
45 S5P6440_GPIO_B_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_A),
46 S5P6440_GPIO_C_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_B),
47 S5P6440_GPIO_F_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_C),
48 S5P6440_GPIO_G_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_F),
49 S5P6440_GPIO_H_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_G),
50 S5P6440_GPIO_I_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_H),
51 S5P6440_GPIO_J_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_I),
52 S5P6440_GPIO_N_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_J),
53 S5P6440_GPIO_P_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_N),
54 S5P6440_GPIO_R_START = S5P6440_GPIO_NEXT(S5P6440_GPIO_P),
55};
56
57/* S5P6440 GPIO number definitions. */
58#define S5P6440_GPA(_nr) (S5P6440_GPIO_A_START + (_nr))
59#define S5P6440_GPB(_nr) (S5P6440_GPIO_B_START + (_nr))
60#define S5P6440_GPC(_nr) (S5P6440_GPIO_C_START + (_nr))
61#define S5P6440_GPF(_nr) (S5P6440_GPIO_F_START + (_nr))
62#define S5P6440_GPG(_nr) (S5P6440_GPIO_G_START + (_nr))
63#define S5P6440_GPH(_nr) (S5P6440_GPIO_H_START + (_nr))
64#define S5P6440_GPI(_nr) (S5P6440_GPIO_I_START + (_nr))
65#define S5P6440_GPJ(_nr) (S5P6440_GPIO_J_START + (_nr))
66#define S5P6440_GPN(_nr) (S5P6440_GPIO_N_START + (_nr))
67#define S5P6440_GPP(_nr) (S5P6440_GPIO_P_START + (_nr))
68#define S5P6440_GPR(_nr) (S5P6440_GPIO_R_START + (_nr))
69
70/* the end of the S5P6440 specific gpios */
71#define S5P6440_GPIO_END (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
72#define S3C_GPIO_END S5P6440_GPIO_END
73
74/* define the number of gpios we need to the one after the GPR() range */
75#define ARCH_NR_GPIOS (S5P6440_GPR(S5P6440_GPIO_R_NR) + \
76 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
77
78#include <asm-generic/gpio.h>
79
80#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/io.h b/arch/arm/mach-s5p6440/include/mach/io.h
deleted file mode 100644
index fa2d69cb1ad7..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/io.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* arch/arm/mach-s5p6440/include/mach/io.h
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben-linux@fluff.org>
5 *
6 * Default IO routines for S3C64XX based
7 */
8
9#ifndef __ASM_ARM_ARCH_IO_H
10#define __ASM_ARM_ARCH_IO_H
11
12/* No current ISA/PCI bus support. */
13#define __io(a) __typesafe_io(a)
14#define __mem_pci(a) (a)
15
16#define IO_SPACE_LIMIT (0xFFFFFFFF)
17
18#endif
diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h
deleted file mode 100644
index 6cc5cbc88ffb..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/map.h
+++ /dev/null
@@ -1,86 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/map.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17#include <plat/map-s5p.h>
18
19#define S5P6440_PA_CHIPID (0xE0000000)
20#define S5P_PA_CHIPID S5P6440_PA_CHIPID
21
22#define S5P6440_PA_SYSCON (0xE0100000)
23#define S5P6440_PA_CLK (S5P6440_PA_SYSCON + 0x0)
24#define S5P_PA_SYSCON S5P6440_PA_SYSCON
25
26#define S5P6440_PA_GPIO (0xE0308000)
27#define S5P_PA_GPIO S5P6440_PA_GPIO
28
29#define S5P6440_PA_VIC0 (0xE4000000)
30#define S5P_PA_VIC0 S5P6440_PA_VIC0
31
32#define S5P6440_PA_PDMA 0xE9000000
33
34#define S5P6440_PA_VIC1 (0xE4100000)
35#define S5P_PA_VIC1 S5P6440_PA_VIC1
36
37#define S5P6440_PA_TIMER (0xEA000000)
38#define S5P_PA_TIMER S5P6440_PA_TIMER
39
40#define S5P6440_PA_RTC (0xEA100000)
41
42#define S5P6440_PA_WDT (0xEA200000)
43#define S5P_PA_WDT S5P6440_PA_WDT
44
45#define S5P6440_PA_UART (0xEC000000)
46
47#define S5P_PA_UART0 (S5P6440_PA_UART + 0x0)
48#define S5P_PA_UART1 (S5P6440_PA_UART + 0x400)
49#define S5P_PA_UART2 (S5P6440_PA_UART + 0x800)
50#define S5P_PA_UART3 (S5P6440_PA_UART + 0xC00)
51
52#define S5P_SZ_UART SZ_256
53
54#define S5P6440_PA_IIC0 (0xEC104000)
55#define S5P6440_PA_IIC1 (0xEC20F000)
56
57#define S5P6440_PA_SPI0 0xEC400000
58#define S5P6440_PA_SPI1 0xEC500000
59
60#define S5P6440_PA_HSOTG (0xED100000)
61
62#define S5P6440_PA_HSMMC0 (0xED800000)
63#define S5P6440_PA_HSMMC1 (0xED900000)
64#define S5P6440_PA_HSMMC2 (0xEDA00000)
65
66#define S5P6440_PA_SDRAM (0x20000000)
67#define S5P_PA_SDRAM S5P6440_PA_SDRAM
68
69/* I2S */
70#define S5P6440_PA_I2S 0xF2000000
71
72/* PCM */
73#define S5P6440_PA_PCM 0xF2100000
74
75#define S5P6440_PA_ADC (0xF3000000)
76
77/* compatibiltiy defines. */
78#define S3C_PA_UART S5P6440_PA_UART
79#define S3C_PA_IIC S5P6440_PA_IIC0
80#define S3C_PA_RTC S5P6440_PA_RTC
81#define S3C_PA_IIC1 S5P6440_PA_IIC1
82#define S3C_PA_WDT S5P6440_PA_WDT
83
84#define SAMSUNG_PA_ADC S5P6440_PA_ADC
85
86#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-clock.h b/arch/arm/mach-s5p6440/include/mach/regs-clock.h
deleted file mode 100644
index c783ecc9f193..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/regs-clock.h
+++ /dev/null
@@ -1,130 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - Clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
19
20#define S5P_APLL_LOCK S5P_CLKREG(0x00)
21#define S5P_MPLL_LOCK S5P_CLKREG(0x04)
22#define S5P_EPLL_LOCK S5P_CLKREG(0x08)
23#define S5P_APLL_CON S5P_CLKREG(0x0C)
24#define S5P_MPLL_CON S5P_CLKREG(0x10)
25#define S5P_EPLL_CON S5P_CLKREG(0x14)
26#define S5P_EPLL_CON_K S5P_CLKREG(0x18)
27#define S5P_CLK_SRC0 S5P_CLKREG(0x1C)
28#define S5P_CLK_DIV0 S5P_CLKREG(0x20)
29#define S5P_CLK_DIV1 S5P_CLKREG(0x24)
30#define S5P_CLK_DIV2 S5P_CLKREG(0x28)
31#define S5P_CLK_OUT S5P_CLKREG(0x2C)
32#define S5P_CLK_GATE_HCLK0 S5P_CLKREG(0x30)
33#define S5P_CLK_GATE_PCLK S5P_CLKREG(0x34)
34#define S5P_CLK_GATE_SCLK0 S5P_CLKREG(0x38)
35#define S5P_CLK_GATE_MEM0 S5P_CLKREG(0x3C)
36#define S5P_CLK_DIV3 S5P_CLKREG(0x40)
37#define S5P_CLK_GATE_HCLK1 S5P_CLKREG(0x44)
38#define S5P_CLK_GATE_SCLK1 S5P_CLKREG(0x48)
39#define S5P_AHB_CON0 S5P_CLKREG(0x100)
40#define S5P_CLK_SRC1 S5P_CLKREG(0x10C)
41#define S5P_SWRESET S5P_CLKREG(0x114)
42#define S5P_SYS_ID S5P_CLKREG(0x118)
43#define S5P_SYS_OTHERS S5P_CLKREG(0x11C)
44#define S5P_MEM_CFG_STAT S5P_CLKREG(0x12C)
45#define S5P_PWR_CFG S5P_CLKREG(0x804)
46#define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0x808)
47#define S5P_NORMAL_CFG S5P_CLKREG(0x810)
48#define S5P_STOP_CFG S5P_CLKREG(0x814)
49#define S5P_SLEEP_CFG S5P_CLKREG(0x818)
50#define S5P_OSC_FREQ S5P_CLKREG(0x820)
51#define S5P_OSC_STABLE S5P_CLKREG(0x824)
52#define S5P_PWR_STABLE S5P_CLKREG(0x828)
53#define S5P_MTC_STABLE S5P_CLKREG(0x830)
54#define S5P_OTHERS S5P_CLKREG(0x900)
55#define S5P_RST_STAT S5P_CLKREG(0x904)
56#define S5P_WAKEUP_STAT S5P_CLKREG(0x908)
57#define S5P_SLPEN S5P_CLKREG(0x930)
58#define S5P_INFORM0 S5P_CLKREG(0xA00)
59#define S5P_INFORM1 S5P_CLKREG(0xA04)
60#define S5P_INFORM2 S5P_CLKREG(0xA08)
61#define S5P_INFORM3 S5P_CLKREG(0xA0C)
62
63/* CLKDIV0 */
64#define S5P_CLKDIV0_PCLK_MASK (0xf << 12)
65#define S5P_CLKDIV0_PCLK_SHIFT (12)
66#define S5P_CLKDIV0_HCLK_MASK (0xf << 8)
67#define S5P_CLKDIV0_HCLK_SHIFT (8)
68#define S5P_CLKDIV0_MPLL_MASK (0x1 << 4)
69#define S5P_CLKDIV0_ARM_MASK (0xf << 0)
70#define S5P_CLKDIV0_ARM_SHIFT (0)
71
72/* CLKDIV3 */
73#define S5P_CLKDIV3_PCLK_LOW_MASK (0xf << 12)
74#define S5P_CLKDIV3_PCLK_LOW_SHIFT (12)
75#define S5P_CLKDIV3_HCLK_LOW_MASK (0xf << 8)
76#define S5P_CLKDIV3_HCLK_LOW_SHIFT (8)
77
78/* HCLK0 GATE Registers */
79#define S5P_CLKCON_HCLK0_USB (1<<20)
80#define S5P_CLKCON_HCLK0_HSMMC2 (1<<19)
81#define S5P_CLKCON_HCLK0_HSMMC1 (1<<18)
82#define S5P_CLKCON_HCLK0_HSMMC0 (1<<17)
83#define S5P_CLKCON_HCLK0_POST0 (1<<5)
84
85/* HCLK1 GATE Registers */
86#define S5P_CLKCON_HCLK1_DISPCON (1<<1)
87
88/* PCLK GATE Registers */
89#define S5P_CLKCON_PCLK_IIS2 (1<<26)
90#define S5P_CLKCON_PCLK_SPI1 (1<<22)
91#define S5P_CLKCON_PCLK_SPI0 (1<<21)
92#define S5P_CLKCON_PCLK_GPIO (1<<18)
93#define S5P_CLKCON_PCLK_IIC0 (1<<17)
94#define S5P_CLKCON_PCLK_TSADC (1<<12)
95#define S5P_CLKCON_PCLK_PWM (1<<7)
96#define S5P_CLKCON_PCLK_RTC (1<<6)
97#define S5P_CLKCON_PCLK_WDT (1<<5)
98#define S5P_CLKCON_PCLK_UART3 (1<<4)
99#define S5P_CLKCON_PCLK_UART2 (1<<3)
100#define S5P_CLKCON_PCLK_UART1 (1<<2)
101#define S5P_CLKCON_PCLK_UART0 (1<<1)
102
103/* SCLK0 GATE Registers */
104#define S5P_CLKCON_SCLK0_MMC2_48 (1<<29)
105#define S5P_CLKCON_SCLK0_MMC1_48 (1<<28)
106#define S5P_CLKCON_SCLK0_MMC0_48 (1<<27)
107#define S5P_CLKCON_SCLK0_MMC2 (1<<26)
108#define S5P_CLKCON_SCLK0_MMC1 (1<<25)
109#define S5P_CLKCON_SCLK0_MMC0 (1<<24)
110#define S5P_CLKCON_SCLK0_SPI1_48 (1<<23)
111#define S5P_CLKCON_SCLK0_SPI0_48 (1<<22)
112#define S5P_CLKCON_SCLK0_SPI1 (1<<21)
113#define S5P_CLKCON_SCLK0_SPI0 (1<<20)
114#define S5P_CLKCON_SCLK0_UART (1<<5)
115
116/* SCLK1 GATE Registers */
117
118/* MEM0 GATE Registers */
119#define S5P_CLKCON_MEM0_HCLK_NFCON (1<<2)
120
121/*OTHERS Resgister */
122#define S5P_OTHERS_USB_SIG_MASK (1<<16)
123#define S5P_OTHERS_HCLK_LOW_SEL_MPLL (1<<6)
124
125/* Compatibility defines */
126#define ARM_CLK_DIV S5P_CLK_DIV0
127#define ARM_DIV_RATIO_SHIFT 0
128#define ARM_DIV_MASK (0xf << ARM_DIV_RATIO_SHIFT)
129
130#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/spi-clocks.h b/arch/arm/mach-s5p6440/include/mach/spi-clocks.h
deleted file mode 100644
index 5fbca50d1cfb..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/spi-clocks.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/spi-clocks.h
2 *
3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __S5P6440_PLAT_SPI_CLKS_H
12#define __S5P6440_PLAT_SPI_CLKS_H __FILE__
13
14#define S5P6440_SPI_SRCCLK_PCLK 0
15#define S5P6440_SPI_SRCCLK_SCLK 1
16
17#endif /* __S5P6440_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/uncompress.h b/arch/arm/mach-s5p6440/include/mach/uncompress.h
deleted file mode 100644
index 7c1f600d65c0..000000000000
--- a/arch/arm/mach-s5p6440/include/mach/uncompress.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/uncompress.h
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - uncompress code
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_UNCOMPRESS_H
14#define __ASM_ARCH_UNCOMPRESS_H
15
16#include <mach/map.h>
17#include <plat/uncompress.h>
18
19static void arch_detect_cpu(void)
20{
21 /* we do not need to do any cpu detection here at the moment. */
22}
23
24#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5p6440/init.c b/arch/arm/mach-s5p6440/init.c
deleted file mode 100644
index a1f3727e4021..000000000000
--- a/arch/arm/mach-s5p6440/init.c
+++ /dev/null
@@ -1,52 +0,0 @@
1/* linux/arch/arm/mach-s5p6440/init.c
2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P6440 - Init support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/init.h>
16#include <linux/serial_core.h>
17
18#include <plat/cpu.h>
19#include <plat/devs.h>
20#include <plat/s5p6440.h>
21#include <plat/regs-serial.h>
22
23static struct s3c24xx_uart_clksrc s5p6440_serial_clocks[] = {
24 [0] = {
25 .name = "pclk_low",
26 .divisor = 1,
27 .min_baud = 0,
28 .max_baud = 0,
29 },
30 [1] = {
31 .name = "uclk1",
32 .divisor = 1,
33 .min_baud = 0,
34 .max_baud = 0,
35 },
36};
37
38/* uart registration process */
39void __init s5p6440_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
40{
41 struct s3c2410_uartcfg *tcfg = cfg;
42 u32 ucnt;
43
44 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
45 if (!tcfg->clocks) {
46 tcfg->clocks = s5p6440_serial_clocks;
47 tcfg->clocks_size = ARRAY_SIZE(s5p6440_serial_clocks);
48 }
49 }
50
51 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
52}
diff --git a/arch/arm/mach-s5p6442/cpu.c b/arch/arm/mach-s5p6442/cpu.c
index 70ac681af72b..842af86bda6d 100644
--- a/arch/arm/mach-s5p6442/cpu.c
+++ b/arch/arm/mach-s5p6442/cpu.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5p6442/cpu.c 1/* linux/arch/arm/mach-s5p6442/cpu.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -48,10 +48,30 @@ static struct map_desc s5p6442_iodesc[] __initdata = {
48 .length = SZ_16K, 48 .length = SZ_16K,
49 .type = MT_DEVICE, 49 .type = MT_DEVICE,
50 }, { 50 }, {
51 .virtual = (unsigned long)S5P_VA_GPIO,
52 .pfn = __phys_to_pfn(S5P6442_PA_GPIO),
53 .length = SZ_4K,
54 .type = MT_DEVICE,
55 }, {
56 .virtual = (unsigned long)VA_VIC0,
57 .pfn = __phys_to_pfn(S5P6442_PA_VIC0),
58 .length = SZ_16K,
59 .type = MT_DEVICE,
60 }, {
61 .virtual = (unsigned long)VA_VIC1,
62 .pfn = __phys_to_pfn(S5P6442_PA_VIC1),
63 .length = SZ_16K,
64 .type = MT_DEVICE,
65 }, {
51 .virtual = (unsigned long)VA_VIC2, 66 .virtual = (unsigned long)VA_VIC2,
52 .pfn = __phys_to_pfn(S5P6442_PA_VIC2), 67 .pfn = __phys_to_pfn(S5P6442_PA_VIC2),
53 .length = SZ_16K, 68 .length = SZ_16K,
54 .type = MT_DEVICE, 69 .type = MT_DEVICE,
70 }, {
71 .virtual = (unsigned long)S3C_VA_UART,
72 .pfn = __phys_to_pfn(S3C_PA_UART),
73 .length = SZ_512K,
74 .type = MT_DEVICE,
55 } 75 }
56}; 76};
57 77
@@ -63,10 +83,11 @@ static void s5p6442_idle(void)
63 local_irq_enable(); 83 local_irq_enable();
64} 84}
65 85
66/* s5p6442_map_io 86/*
87 * s5p6442_map_io
67 * 88 *
68 * register the standard cpu IO areas 89 * register the standard cpu IO areas
69*/ 90 */
70 91
71void __init s5p6442_map_io(void) 92void __init s5p6442_map_io(void)
72{ 93{
diff --git a/arch/arm/mach-s5p6442/include/mach/debug-macro.S b/arch/arm/mach-s5p6442/include/mach/debug-macro.S
index bb6536147ffb..e2213205d780 100644
--- a/arch/arm/mach-s5p6442/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5p6442/include/mach/debug-macro.S
@@ -15,13 +15,12 @@
15#include <mach/map.h> 15#include <mach/map.h>
16#include <plat/regs-serial.h> 16#include <plat/regs-serial.h>
17 17
18 .macro addruart, rx, rtmp 18 .macro addruart, rp, rv
19 mrc p15, 0, \rx, c1, c0 19 ldr \rp, = S3C_PA_UART
20 tst \rx, #1 20 ldr \rv, = S3C_VA_UART
21 ldreq \rx, = S3C_PA_UART
22 ldrne \rx, = S3C_VA_UART
23#if CONFIG_DEBUG_S3C_UART != 0 21#if CONFIG_DEBUG_S3C_UART != 0
24 add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) 22 add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
23 add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
25#endif 24#endif
26 .endm 25 .endm
27 26
diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h
index 281d256faafb..31fb2e68d527 100644
--- a/arch/arm/mach-s5p6442/include/mach/map.h
+++ b/arch/arm/mach-s5p6442/include/mach/map.h
@@ -23,16 +23,10 @@
23#define S5P_PA_SYSCON S5P6442_PA_SYSCON 23#define S5P_PA_SYSCON S5P6442_PA_SYSCON
24 24
25#define S5P6442_PA_GPIO (0xE0200000) 25#define S5P6442_PA_GPIO (0xE0200000)
26#define S5P_PA_GPIO S5P6442_PA_GPIO
27 26
28#define S5P6442_PA_VIC0 (0xE4000000) 27#define S5P6442_PA_VIC0 (0xE4000000)
29#define S5P_PA_VIC0 S5P6442_PA_VIC0
30
31#define S5P6442_PA_VIC1 (0xE4100000) 28#define S5P6442_PA_VIC1 (0xE4100000)
32#define S5P_PA_VIC1 S5P6442_PA_VIC1
33
34#define S5P6442_PA_VIC2 (0xE4200000) 29#define S5P6442_PA_VIC2 (0xE4200000)
35#define S5P_PA_VIC2 S5P6442_PA_VIC2
36 30
37#define S5P6442_PA_MDMA 0xE8000000 31#define S5P6442_PA_MDMA 0xE8000000
38#define S5P6442_PA_PDMA 0xE9000000 32#define S5P6442_PA_PDMA 0xE9000000
diff --git a/arch/arm/mach-s5p6442/mach-smdk6442.c b/arch/arm/mach-s5p6442/mach-smdk6442.c
index 8d8d04272f85..819fd80d00af 100644
--- a/arch/arm/mach-s5p6442/mach-smdk6442.c
+++ b/arch/arm/mach-s5p6442/mach-smdk6442.c
@@ -83,8 +83,6 @@ static void __init smdk6442_machine_init(void)
83 83
84MACHINE_START(SMDK6442, "SMDK6442") 84MACHINE_START(SMDK6442, "SMDK6442")
85 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 85 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
86 .phys_io = S3C_PA_UART & 0xfff00000,
87 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
88 .boot_params = S5P_PA_SDRAM + 0x100, 86 .boot_params = S5P_PA_SDRAM + 0x100,
89 .init_irq = s5p6442_init_irq, 87 .init_irq = s5p6442_init_irq,
90 .map_io = smdk6442_map_io, 88 .map_io = smdk6442_map_io,
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
new file mode 100644
index 000000000000..fbcae9352022
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -0,0 +1,57 @@
1# arch/arm/mach-s5p64x0/Kconfig
2#
3# Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8if ARCH_S5P64X0
9
10config CPU_S5P6440
11 bool
12 select PLAT_S5P
13 select S3C_PL330_DMA
14 help
15 Enable S5P6440 CPU support
16
17config CPU_S5P6450
18 bool
19 select PLAT_S5P
20 select S3C_PL330_DMA
21 help
22 Enable S5P6450 CPU support
23
24config S5P64X0_SETUP_I2C1
25 bool
26 help
27 Common setup code for i2c bus 1.
28
29# machine support
30
31config MACH_SMDK6440
32 bool "SMDK6440"
33 select CPU_S5P6440
34 select S3C_DEV_I2C1
35 select S3C_DEV_RTC
36 select S3C_DEV_WDT
37 select S3C64XX_DEV_SPI
38 select SAMSUNG_DEV_ADC
39 select SAMSUNG_DEV_TS
40 select S5P64X0_SETUP_I2C1
41 help
42 Machine support for the Samsung SMDK6440
43
44config MACH_SMDK6450
45 bool "SMDK6450"
46 select CPU_S5P6450
47 select S3C_DEV_I2C1
48 select S3C_DEV_RTC
49 select S3C_DEV_WDT
50 select S3C64XX_DEV_SPI
51 select SAMSUNG_DEV_ADC
52 select SAMSUNG_DEV_TS
53 select S5P64X0_SETUP_I2C1
54 help
55 Machine support for the Samsung SMDK6450
56
57endif
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
new file mode 100644
index 000000000000..2655829e6bf8
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -0,0 +1,30 @@
1# arch/arm/mach-s5p64x0/Makefile
2#
3# Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4# http://www.samsung.com
5#
6# Licensed under GPLv2
7
8obj-y :=
9obj-m :=
10obj-n :=
11obj- :=
12
13# Core support for S5P64X0 system
14
15obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o
16obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o
17obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o gpio.o
18obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o
19
20# machine support
21
22obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o
23obj-$(CONFIG_MACH_SMDK6450) += mach-smdk6450.o
24
25# device support
26
27obj-y += dev-audio.o
28obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
29
30obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o
diff --git a/arch/arm/mach-s5p6440/Makefile.boot b/arch/arm/mach-s5p64x0/Makefile.boot
index ff90aa13bd67..ff90aa13bd67 100644
--- a/arch/arm/mach-s5p6440/Makefile.boot
+++ b/arch/arm/mach-s5p64x0/Makefile.boot
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
new file mode 100644
index 000000000000..f93dcd8b4d6a
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -0,0 +1,626 @@
1/* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P6440 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/sysdev.h>
21#include <linux/io.h>
22
23#include <mach/hardware.h>
24#include <mach/map.h>
25#include <mach/regs-clock.h>
26#include <mach/s5p64x0-clock.h>
27
28#include <plat/cpu-freq.h>
29#include <plat/clock.h>
30#include <plat/cpu.h>
31#include <plat/pll.h>
32#include <plat/s5p-clock.h>
33#include <plat/clock-clksrc.h>
34#include <plat/s5p6440.h>
35
36static u32 epll_div[][5] = {
37 { 36000000, 0, 48, 1, 4 },
38 { 48000000, 0, 32, 1, 3 },
39 { 60000000, 0, 40, 1, 3 },
40 { 72000000, 0, 48, 1, 3 },
41 { 84000000, 0, 28, 1, 2 },
42 { 96000000, 0, 32, 1, 2 },
43 { 32768000, 45264, 43, 1, 4 },
44 { 45158000, 6903, 30, 1, 3 },
45 { 49152000, 50332, 32, 1, 3 },
46 { 67738000, 10398, 45, 1, 3 },
47 { 73728000, 9961, 49, 1, 3 }
48};
49
50static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
51{
52 unsigned int epll_con, epll_con_k;
53 unsigned int i;
54
55 if (clk->rate == rate) /* Return if nothing changed */
56 return 0;
57
58 epll_con = __raw_readl(S5P64X0_EPLL_CON);
59 epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
60
61 epll_con_k &= ~(PLL90XX_KDIV_MASK);
62 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
63
64 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
65 if (epll_div[i][0] == rate) {
66 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
67 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
68 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
69 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
70 break;
71 }
72 }
73
74 if (i == ARRAY_SIZE(epll_div)) {
75 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
76 return -EINVAL;
77 }
78
79 __raw_writel(epll_con, S5P64X0_EPLL_CON);
80 __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
81
82 clk->rate = rate;
83
84 return 0;
85}
86
87static struct clk_ops s5p6440_epll_ops = {
88 .get_rate = s5p64x0_epll_get_rate,
89 .set_rate = s5p6440_epll_set_rate,
90};
91
92static struct clksrc_clk clk_hclk = {
93 .clk = {
94 .name = "clk_hclk",
95 .id = -1,
96 .parent = &clk_armclk.clk,
97 },
98 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
99};
100
101static struct clksrc_clk clk_pclk = {
102 .clk = {
103 .name = "clk_pclk",
104 .id = -1,
105 .parent = &clk_hclk.clk,
106 },
107 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
108};
109static struct clksrc_clk clk_hclk_low = {
110 .clk = {
111 .name = "clk_hclk_low",
112 .id = -1,
113 },
114 .sources = &clkset_hclk_low,
115 .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
116 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
117};
118
119static struct clksrc_clk clk_pclk_low = {
120 .clk = {
121 .name = "clk_pclk_low",
122 .id = -1,
123 .parent = &clk_hclk_low.clk,
124 },
125 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
126};
127
128/*
129 * The following clocks will be disabled during clock initialization. It is
130 * recommended to keep the following clocks disabled until the driver requests
131 * for enabling the clock.
132 */
133static struct clk init_clocks_disable[] = {
134 {
135 .name = "nand",
136 .id = -1,
137 .parent = &clk_hclk.clk,
138 .enable = s5p64x0_mem_ctrl,
139 .ctrlbit = (1 << 2),
140 }, {
141 .name = "post",
142 .id = -1,
143 .parent = &clk_hclk_low.clk,
144 .enable = s5p64x0_hclk0_ctrl,
145 .ctrlbit = (1 << 5)
146 }, {
147 .name = "2d",
148 .id = -1,
149 .parent = &clk_hclk.clk,
150 .enable = s5p64x0_hclk0_ctrl,
151 .ctrlbit = (1 << 8),
152 }, {
153 .name = "hsmmc",
154 .id = 0,
155 .parent = &clk_hclk_low.clk,
156 .enable = s5p64x0_hclk0_ctrl,
157 .ctrlbit = (1 << 17),
158 }, {
159 .name = "hsmmc",
160 .id = 1,
161 .parent = &clk_hclk_low.clk,
162 .enable = s5p64x0_hclk0_ctrl,
163 .ctrlbit = (1 << 18),
164 }, {
165 .name = "hsmmc",
166 .id = 2,
167 .parent = &clk_hclk_low.clk,
168 .enable = s5p64x0_hclk0_ctrl,
169 .ctrlbit = (1 << 19),
170 }, {
171 .name = "otg",
172 .id = -1,
173 .parent = &clk_hclk_low.clk,
174 .enable = s5p64x0_hclk0_ctrl,
175 .ctrlbit = (1 << 20)
176 }, {
177 .name = "irom",
178 .id = -1,
179 .parent = &clk_hclk.clk,
180 .enable = s5p64x0_hclk0_ctrl,
181 .ctrlbit = (1 << 25),
182 }, {
183 .name = "lcd",
184 .id = -1,
185 .parent = &clk_hclk_low.clk,
186 .enable = s5p64x0_hclk1_ctrl,
187 .ctrlbit = (1 << 1),
188 }, {
189 .name = "hclk_fimgvg",
190 .id = -1,
191 .parent = &clk_hclk.clk,
192 .enable = s5p64x0_hclk1_ctrl,
193 .ctrlbit = (1 << 2),
194 }, {
195 .name = "tsi",
196 .id = -1,
197 .parent = &clk_hclk_low.clk,
198 .enable = s5p64x0_hclk1_ctrl,
199 .ctrlbit = (1 << 0),
200 }, {
201 .name = "watchdog",
202 .id = -1,
203 .parent = &clk_pclk_low.clk,
204 .enable = s5p64x0_pclk_ctrl,
205 .ctrlbit = (1 << 5),
206 }, {
207 .name = "rtc",
208 .id = -1,
209 .parent = &clk_pclk_low.clk,
210 .enable = s5p64x0_pclk_ctrl,
211 .ctrlbit = (1 << 6),
212 }, {
213 .name = "timers",
214 .id = -1,
215 .parent = &clk_pclk_low.clk,
216 .enable = s5p64x0_pclk_ctrl,
217 .ctrlbit = (1 << 7),
218 }, {
219 .name = "pcm",
220 .id = -1,
221 .parent = &clk_pclk_low.clk,
222 .enable = s5p64x0_pclk_ctrl,
223 .ctrlbit = (1 << 8),
224 }, {
225 .name = "adc",
226 .id = -1,
227 .parent = &clk_pclk_low.clk,
228 .enable = s5p64x0_pclk_ctrl,
229 .ctrlbit = (1 << 12),
230 }, {
231 .name = "i2c",
232 .id = -1,
233 .parent = &clk_pclk_low.clk,
234 .enable = s5p64x0_pclk_ctrl,
235 .ctrlbit = (1 << 17),
236 }, {
237 .name = "spi",
238 .id = 0,
239 .parent = &clk_pclk_low.clk,
240 .enable = s5p64x0_pclk_ctrl,
241 .ctrlbit = (1 << 21),
242 }, {
243 .name = "spi",
244 .id = 1,
245 .parent = &clk_pclk_low.clk,
246 .enable = s5p64x0_pclk_ctrl,
247 .ctrlbit = (1 << 22),
248 }, {
249 .name = "gps",
250 .id = -1,
251 .parent = &clk_pclk_low.clk,
252 .enable = s5p64x0_pclk_ctrl,
253 .ctrlbit = (1 << 25),
254 }, {
255 .name = "i2s_v40",
256 .id = 0,
257 .parent = &clk_pclk_low.clk,
258 .enable = s5p64x0_pclk_ctrl,
259 .ctrlbit = (1 << 26),
260 }, {
261 .name = "dsim",
262 .id = -1,
263 .parent = &clk_pclk_low.clk,
264 .enable = s5p64x0_pclk_ctrl,
265 .ctrlbit = (1 << 28),
266 }, {
267 .name = "etm",
268 .id = -1,
269 .parent = &clk_pclk.clk,
270 .enable = s5p64x0_pclk_ctrl,
271 .ctrlbit = (1 << 29),
272 }, {
273 .name = "dmc0",
274 .id = -1,
275 .parent = &clk_pclk.clk,
276 .enable = s5p64x0_pclk_ctrl,
277 .ctrlbit = (1 << 30),
278 }, {
279 .name = "pclk_fimgvg",
280 .id = -1,
281 .parent = &clk_pclk.clk,
282 .enable = s5p64x0_pclk_ctrl,
283 .ctrlbit = (1 << 31),
284 }, {
285 .name = "sclk_spi_48",
286 .id = 0,
287 .parent = &clk_48m,
288 .enable = s5p64x0_sclk_ctrl,
289 .ctrlbit = (1 << 22),
290 }, {
291 .name = "sclk_spi_48",
292 .id = 1,
293 .parent = &clk_48m,
294 .enable = s5p64x0_sclk_ctrl,
295 .ctrlbit = (1 << 23),
296 }, {
297 .name = "mmc_48m",
298 .id = 0,
299 .parent = &clk_48m,
300 .enable = s5p64x0_sclk_ctrl,
301 .ctrlbit = (1 << 27),
302 }, {
303 .name = "mmc_48m",
304 .id = 1,
305 .parent = &clk_48m,
306 .enable = s5p64x0_sclk_ctrl,
307 .ctrlbit = (1 << 28),
308 }, {
309 .name = "mmc_48m",
310 .id = 2,
311 .parent = &clk_48m,
312 .enable = s5p64x0_sclk_ctrl,
313 .ctrlbit = (1 << 29),
314 },
315};
316
317/*
318 * The following clocks will be enabled during clock initialization.
319 */
320static struct clk init_clocks[] = {
321 {
322 .name = "intc",
323 .id = -1,
324 .parent = &clk_hclk.clk,
325 .enable = s5p64x0_hclk0_ctrl,
326 .ctrlbit = (1 << 1),
327 }, {
328 .name = "mem",
329 .id = -1,
330 .parent = &clk_hclk.clk,
331 .enable = s5p64x0_hclk0_ctrl,
332 .ctrlbit = (1 << 21),
333 }, {
334 .name = "dma",
335 .id = -1,
336 .parent = &clk_hclk_low.clk,
337 .enable = s5p64x0_hclk0_ctrl,
338 .ctrlbit = (1 << 12),
339 }, {
340 .name = "uart",
341 .id = 0,
342 .parent = &clk_pclk_low.clk,
343 .enable = s5p64x0_pclk_ctrl,
344 .ctrlbit = (1 << 1),
345 }, {
346 .name = "uart",
347 .id = 1,
348 .parent = &clk_pclk_low.clk,
349 .enable = s5p64x0_pclk_ctrl,
350 .ctrlbit = (1 << 2),
351 }, {
352 .name = "uart",
353 .id = 2,
354 .parent = &clk_pclk_low.clk,
355 .enable = s5p64x0_pclk_ctrl,
356 .ctrlbit = (1 << 3),
357 }, {
358 .name = "uart",
359 .id = 3,
360 .parent = &clk_pclk_low.clk,
361 .enable = s5p64x0_pclk_ctrl,
362 .ctrlbit = (1 << 4),
363 }, {
364 .name = "gpio",
365 .id = -1,
366 .parent = &clk_pclk_low.clk,
367 .enable = s5p64x0_pclk_ctrl,
368 .ctrlbit = (1 << 18),
369 },
370};
371
372static struct clk clk_iis_cd_v40 = {
373 .name = "iis_cdclk_v40",
374 .id = -1,
375};
376
377static struct clk clk_pcm_cd = {
378 .name = "pcm_cdclk",
379 .id = -1,
380};
381
382static struct clk *clkset_group1_list[] = {
383 &clk_mout_epll.clk,
384 &clk_dout_mpll.clk,
385 &clk_fin_epll,
386};
387
388static struct clksrc_sources clkset_group1 = {
389 .sources = clkset_group1_list,
390 .nr_sources = ARRAY_SIZE(clkset_group1_list),
391};
392
393static struct clk *clkset_uart_list[] = {
394 &clk_mout_epll.clk,
395 &clk_dout_mpll.clk,
396};
397
398static struct clksrc_sources clkset_uart = {
399 .sources = clkset_uart_list,
400 .nr_sources = ARRAY_SIZE(clkset_uart_list),
401};
402
403static struct clk *clkset_audio_list[] = {
404 &clk_mout_epll.clk,
405 &clk_dout_mpll.clk,
406 &clk_fin_epll,
407 &clk_iis_cd_v40,
408 &clk_pcm_cd,
409};
410
411static struct clksrc_sources clkset_audio = {
412 .sources = clkset_audio_list,
413 .nr_sources = ARRAY_SIZE(clkset_audio_list),
414};
415
416static struct clksrc_clk clksrcs[] = {
417 {
418 .clk = {
419 .name = "mmc_bus",
420 .id = 0,
421 .ctrlbit = (1 << 24),
422 .enable = s5p64x0_sclk_ctrl,
423 },
424 .sources = &clkset_group1,
425 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
426 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
427 }, {
428 .clk = {
429 .name = "mmc_bus",
430 .id = 1,
431 .ctrlbit = (1 << 25),
432 .enable = s5p64x0_sclk_ctrl,
433 },
434 .sources = &clkset_group1,
435 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
436 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
437 }, {
438 .clk = {
439 .name = "mmc_bus",
440 .id = 2,
441 .ctrlbit = (1 << 26),
442 .enable = s5p64x0_sclk_ctrl,
443 },
444 .sources = &clkset_group1,
445 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
446 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
447 }, {
448 .clk = {
449 .name = "uclk1",
450 .id = -1,
451 .ctrlbit = (1 << 5),
452 .enable = s5p64x0_sclk_ctrl,
453 },
454 .sources = &clkset_uart,
455 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
456 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
457 }, {
458 .clk = {
459 .name = "sclk_spi",
460 .id = 0,
461 .ctrlbit = (1 << 20),
462 .enable = s5p64x0_sclk_ctrl,
463 },
464 .sources = &clkset_group1,
465 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
466 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
467 }, {
468 .clk = {
469 .name = "sclk_spi",
470 .id = 1,
471 .ctrlbit = (1 << 21),
472 .enable = s5p64x0_sclk_ctrl,
473 },
474 .sources = &clkset_group1,
475 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
476 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
477 }, {
478 .clk = {
479 .name = "sclk_post",
480 .id = -1,
481 .ctrlbit = (1 << 10),
482 .enable = s5p64x0_sclk_ctrl,
483 },
484 .sources = &clkset_group1,
485 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
486 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
487 }, {
488 .clk = {
489 .name = "sclk_dispcon",
490 .id = -1,
491 .ctrlbit = (1 << 1),
492 .enable = s5p64x0_sclk1_ctrl,
493 },
494 .sources = &clkset_group1,
495 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
496 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
497 }, {
498 .clk = {
499 .name = "sclk_fimgvg",
500 .id = -1,
501 .ctrlbit = (1 << 2),
502 .enable = s5p64x0_sclk1_ctrl,
503 },
504 .sources = &clkset_group1,
505 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
506 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
507 }, {
508 .clk = {
509 .name = "sclk_audio2",
510 .id = -1,
511 .ctrlbit = (1 << 11),
512 .enable = s5p64x0_sclk_ctrl,
513 },
514 .sources = &clkset_audio,
515 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
516 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
517 },
518};
519
520/* Clock initialization code */
521static struct clksrc_clk *sysclks[] = {
522 &clk_mout_apll,
523 &clk_mout_epll,
524 &clk_mout_mpll,
525 &clk_dout_mpll,
526 &clk_armclk,
527 &clk_hclk,
528 &clk_pclk,
529 &clk_hclk_low,
530 &clk_pclk_low,
531};
532
533void __init_or_cpufreq s5p6440_setup_clocks(void)
534{
535 struct clk *xtal_clk;
536
537 unsigned long xtal;
538 unsigned long fclk;
539 unsigned long hclk;
540 unsigned long hclk_low;
541 unsigned long pclk;
542 unsigned long pclk_low;
543
544 unsigned long apll;
545 unsigned long mpll;
546 unsigned long epll;
547 unsigned int ptr;
548
549 /* Set S5P6440 functions for clk_fout_epll */
550
551 clk_fout_epll.enable = s5p64x0_epll_enable;
552 clk_fout_epll.ops = &s5p6440_epll_ops;
553
554 clk_48m.enable = s5p64x0_clk48m_ctrl;
555
556 xtal_clk = clk_get(NULL, "ext_xtal");
557 BUG_ON(IS_ERR(xtal_clk));
558
559 xtal = clk_get_rate(xtal_clk);
560 clk_put(xtal_clk);
561
562 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
563 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
564 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
565 __raw_readl(S5P64X0_EPLL_CON_K));
566
567 clk_fout_apll.rate = apll;
568 clk_fout_mpll.rate = mpll;
569 clk_fout_epll.rate = epll;
570
571 printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
572 " E=%ld.%ldMHz\n",
573 print_mhz(apll), print_mhz(mpll), print_mhz(epll));
574
575 fclk = clk_get_rate(&clk_armclk.clk);
576 hclk = clk_get_rate(&clk_hclk.clk);
577 pclk = clk_get_rate(&clk_pclk.clk);
578 hclk_low = clk_get_rate(&clk_hclk_low.clk);
579 pclk_low = clk_get_rate(&clk_pclk_low.clk);
580
581 printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
582 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
583 print_mhz(hclk), print_mhz(hclk_low),
584 print_mhz(pclk), print_mhz(pclk_low));
585
586 clk_f.rate = fclk;
587 clk_h.rate = hclk;
588 clk_p.rate = pclk;
589
590 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
591 s3c_set_clksrc(&clksrcs[ptr], true);
592}
593
594static struct clk *clks[] __initdata = {
595 &clk_ext,
596 &clk_iis_cd_v40,
597 &clk_pcm_cd,
598};
599
600void __init s5p6440_register_clocks(void)
601{
602 struct clk *clkp;
603 int ret;
604 int ptr;
605
606 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
607
608 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
609 s3c_register_clksrc(sysclks[ptr], 1);
610
611 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
612 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
613
614 clkp = init_clocks_disable;
615 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
616
617 ret = s3c24xx_register_clock(clkp);
618 if (ret < 0) {
619 printk(KERN_ERR "Failed to register clock %s (%d)\n",
620 clkp->name, ret);
621 }
622 (clkp->enable)(clkp, 0);
623 }
624
625 s3c_pwmclk_init();
626}
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
new file mode 100644
index 000000000000..f9afb05b217c
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -0,0 +1,655 @@
1/* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P6450 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/sysdev.h>
21#include <linux/io.h>
22
23#include <mach/hardware.h>
24#include <mach/map.h>
25#include <mach/regs-clock.h>
26#include <mach/s5p64x0-clock.h>
27
28#include <plat/cpu-freq.h>
29#include <plat/clock.h>
30#include <plat/cpu.h>
31#include <plat/pll.h>
32#include <plat/s5p-clock.h>
33#include <plat/clock-clksrc.h>
34#include <plat/s5p6450.h>
35
36static struct clksrc_clk clk_mout_dpll = {
37 .clk = {
38 .name = "mout_dpll",
39 .id = -1,
40 },
41 .sources = &clk_src_dpll,
42 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
43};
44
45static u32 epll_div[][5] = {
46 { 133000000, 27307, 55, 2, 2 },
47 { 100000000, 43691, 41, 2, 2 },
48 { 480000000, 0, 80, 2, 0 },
49};
50
51static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
52{
53 unsigned int epll_con, epll_con_k;
54 unsigned int i;
55
56 if (clk->rate == rate) /* Return if nothing changed */
57 return 0;
58
59 epll_con = __raw_readl(S5P64X0_EPLL_CON);
60 epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
61
62 epll_con_k &= ~(PLL90XX_KDIV_MASK);
63 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
64
65 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
66 if (epll_div[i][0] == rate) {
67 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
68 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
69 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
70 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
71 break;
72 }
73 }
74
75 if (i == ARRAY_SIZE(epll_div)) {
76 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
77 return -EINVAL;
78 }
79
80 __raw_writel(epll_con, S5P64X0_EPLL_CON);
81 __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
82
83 clk->rate = rate;
84
85 return 0;
86}
87
88static struct clk_ops s5p6450_epll_ops = {
89 .get_rate = s5p64x0_epll_get_rate,
90 .set_rate = s5p6450_epll_set_rate,
91};
92
93static struct clksrc_clk clk_dout_epll = {
94 .clk = {
95 .name = "dout_epll",
96 .id = -1,
97 .parent = &clk_mout_epll.clk,
98 },
99 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
100};
101
102static struct clksrc_clk clk_mout_hclk_sel = {
103 .clk = {
104 .name = "mout_hclk_sel",
105 .id = -1,
106 },
107 .sources = &clkset_hclk_low,
108 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
109};
110
111static struct clk *clkset_hclk_list[] = {
112 &clk_mout_hclk_sel.clk,
113 &clk_armclk.clk,
114};
115
116static struct clksrc_sources clkset_hclk = {
117 .sources = clkset_hclk_list,
118 .nr_sources = ARRAY_SIZE(clkset_hclk_list),
119};
120
121static struct clksrc_clk clk_hclk = {
122 .clk = {
123 .name = "clk_hclk",
124 .id = -1,
125 },
126 .sources = &clkset_hclk,
127 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
128 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
129};
130
131static struct clksrc_clk clk_pclk = {
132 .clk = {
133 .name = "clk_pclk",
134 .id = -1,
135 .parent = &clk_hclk.clk,
136 },
137 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
138};
139static struct clksrc_clk clk_dout_pwm_ratio0 = {
140 .clk = {
141 .name = "clk_dout_pwm_ratio0",
142 .id = -1,
143 .parent = &clk_mout_hclk_sel.clk,
144 },
145 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
146};
147
148static struct clksrc_clk clk_pclk_to_wdt_pwm = {
149 .clk = {
150 .name = "clk_pclk_to_wdt_pwm",
151 .id = -1,
152 .parent = &clk_dout_pwm_ratio0.clk,
153 },
154 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
155};
156
157static struct clksrc_clk clk_hclk_low = {
158 .clk = {
159 .name = "clk_hclk_low",
160 .id = -1,
161 },
162 .sources = &clkset_hclk_low,
163 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
164 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
165};
166
167static struct clksrc_clk clk_pclk_low = {
168 .clk = {
169 .name = "clk_pclk_low",
170 .id = -1,
171 .parent = &clk_hclk_low.clk,
172 },
173 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
174};
175
176/*
177 * The following clocks will be disabled during clock initialization. It is
178 * recommended to keep the following clocks disabled until the driver requests
179 * for enabling the clock.
180 */
181static struct clk init_clocks_disable[] = {
182 {
183 .name = "usbhost",
184 .id = -1,
185 .parent = &clk_hclk_low.clk,
186 .enable = s5p64x0_hclk0_ctrl,
187 .ctrlbit = (1 << 3),
188 }, {
189 .name = "hsmmc",
190 .id = 0,
191 .parent = &clk_hclk_low.clk,
192 .enable = s5p64x0_hclk0_ctrl,
193 .ctrlbit = (1 << 17),
194 }, {
195 .name = "hsmmc",
196 .id = 1,
197 .parent = &clk_hclk_low.clk,
198 .enable = s5p64x0_hclk0_ctrl,
199 .ctrlbit = (1 << 18),
200 }, {
201 .name = "hsmmc",
202 .id = 2,
203 .parent = &clk_hclk_low.clk,
204 .enable = s5p64x0_hclk0_ctrl,
205 .ctrlbit = (1 << 19),
206 }, {
207 .name = "usbotg",
208 .id = -1,
209 .parent = &clk_hclk_low.clk,
210 .enable = s5p64x0_hclk0_ctrl,
211 .ctrlbit = (1 << 20),
212 }, {
213 .name = "lcd",
214 .id = -1,
215 .parent = &clk_h,
216 .enable = s5p64x0_hclk1_ctrl,
217 .ctrlbit = (1 << 1),
218 }, {
219 .name = "watchdog",
220 .id = -1,
221 .parent = &clk_pclk_low.clk,
222 .enable = s5p64x0_pclk_ctrl,
223 .ctrlbit = (1 << 5),
224 }, {
225 .name = "adc",
226 .id = -1,
227 .parent = &clk_pclk_low.clk,
228 .enable = s5p64x0_pclk_ctrl,
229 .ctrlbit = (1 << 12),
230 }, {
231 .name = "i2c",
232 .id = 0,
233 .parent = &clk_pclk_low.clk,
234 .enable = s5p64x0_pclk_ctrl,
235 .ctrlbit = (1 << 17),
236 }, {
237 .name = "spi",
238 .id = 0,
239 .parent = &clk_pclk_low.clk,
240 .enable = s5p64x0_pclk_ctrl,
241 .ctrlbit = (1 << 21),
242 }, {
243 .name = "spi",
244 .id = 1,
245 .parent = &clk_pclk_low.clk,
246 .enable = s5p64x0_pclk_ctrl,
247 .ctrlbit = (1 << 22),
248 }, {
249 .name = "iis",
250 .id = -1,
251 .parent = &clk_pclk_low.clk,
252 .enable = s5p64x0_pclk_ctrl,
253 .ctrlbit = (1 << 26),
254 }, {
255 .name = "i2c",
256 .id = 1,
257 .parent = &clk_pclk_low.clk,
258 .enable = s5p64x0_pclk_ctrl,
259 .ctrlbit = (1 << 27),
260 }, {
261 .name = "dmc0",
262 .id = -1,
263 .parent = &clk_pclk.clk,
264 .enable = s5p64x0_pclk_ctrl,
265 .ctrlbit = (1 << 30),
266 }
267};
268
269/*
270 * The following clocks will be enabled during clock initialization.
271 */
272static struct clk init_clocks[] = {
273 {
274 .name = "intc",
275 .id = -1,
276 .parent = &clk_hclk.clk,
277 .enable = s5p64x0_hclk0_ctrl,
278 .ctrlbit = (1 << 1),
279 }, {
280 .name = "mem",
281 .id = -1,
282 .parent = &clk_hclk.clk,
283 .enable = s5p64x0_hclk0_ctrl,
284 .ctrlbit = (1 << 21),
285 }, {
286 .name = "dma",
287 .id = -1,
288 .parent = &clk_hclk_low.clk,
289 .enable = s5p64x0_hclk0_ctrl,
290 .ctrlbit = (1 << 12),
291 }, {
292 .name = "uart",
293 .id = 0,
294 .parent = &clk_pclk_low.clk,
295 .enable = s5p64x0_pclk_ctrl,
296 .ctrlbit = (1 << 1),
297 }, {
298 .name = "uart",
299 .id = 1,
300 .parent = &clk_pclk_low.clk,
301 .enable = s5p64x0_pclk_ctrl,
302 .ctrlbit = (1 << 2),
303 }, {
304 .name = "uart",
305 .id = 2,
306 .parent = &clk_pclk_low.clk,
307 .enable = s5p64x0_pclk_ctrl,
308 .ctrlbit = (1 << 3),
309 }, {
310 .name = "uart",
311 .id = 3,
312 .parent = &clk_pclk_low.clk,
313 .enable = s5p64x0_pclk_ctrl,
314 .ctrlbit = (1 << 4),
315 }, {
316 .name = "timers",
317 .id = -1,
318 .parent = &clk_pclk_to_wdt_pwm.clk,
319 .enable = s5p64x0_pclk_ctrl,
320 .ctrlbit = (1 << 7),
321 }, {
322 .name = "gpio",
323 .id = -1,
324 .parent = &clk_pclk_low.clk,
325 .enable = s5p64x0_pclk_ctrl,
326 .ctrlbit = (1 << 18),
327 },
328};
329
330static struct clk *clkset_uart_list[] = {
331 &clk_dout_epll.clk,
332 &clk_dout_mpll.clk,
333};
334
335static struct clksrc_sources clkset_uart = {
336 .sources = clkset_uart_list,
337 .nr_sources = ARRAY_SIZE(clkset_uart_list),
338};
339
340static struct clk *clkset_mali_list[] = {
341 &clk_mout_epll.clk,
342 &clk_mout_apll.clk,
343 &clk_mout_mpll.clk,
344};
345
346static struct clksrc_sources clkset_mali = {
347 .sources = clkset_mali_list,
348 .nr_sources = ARRAY_SIZE(clkset_mali_list),
349};
350
351static struct clk *clkset_group2_list[] = {
352 &clk_dout_epll.clk,
353 &clk_dout_mpll.clk,
354 &clk_ext_xtal_mux,
355};
356
357static struct clksrc_sources clkset_group2 = {
358 .sources = clkset_group2_list,
359 .nr_sources = ARRAY_SIZE(clkset_group2_list),
360};
361
362static struct clk *clkset_dispcon_list[] = {
363 &clk_dout_epll.clk,
364 &clk_dout_mpll.clk,
365 &clk_ext_xtal_mux,
366 &clk_mout_dpll.clk,
367};
368
369static struct clksrc_sources clkset_dispcon = {
370 .sources = clkset_dispcon_list,
371 .nr_sources = ARRAY_SIZE(clkset_dispcon_list),
372};
373
374static struct clk *clkset_hsmmc44_list[] = {
375 &clk_dout_epll.clk,
376 &clk_dout_mpll.clk,
377 &clk_ext_xtal_mux,
378 &s5p_clk_27m,
379 &clk_48m,
380};
381
382static struct clksrc_sources clkset_hsmmc44 = {
383 .sources = clkset_hsmmc44_list,
384 .nr_sources = ARRAY_SIZE(clkset_hsmmc44_list),
385};
386
387static struct clk *clkset_sclk_audio0_list[] = {
388 [0] = &clk_dout_epll.clk,
389 [1] = &clk_dout_mpll.clk,
390 [2] = &clk_ext_xtal_mux,
391 [3] = NULL,
392 [4] = NULL,
393};
394
395static struct clksrc_sources clkset_sclk_audio0 = {
396 .sources = clkset_sclk_audio0_list,
397 .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
398};
399
400static struct clksrc_clk clk_sclk_audio0 = {
401 .clk = {
402 .name = "audio-bus",
403 .id = -1,
404 .enable = s5p64x0_sclk_ctrl,
405 .ctrlbit = (1 << 8),
406 .parent = &clk_dout_epll.clk,
407 },
408 .sources = &clkset_sclk_audio0,
409 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
410 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
411};
412
413static struct clksrc_clk clksrcs[] = {
414 {
415 .clk = {
416 .name = "sclk_mmc",
417 .id = 0,
418 .ctrlbit = (1 << 24),
419 .enable = s5p64x0_sclk_ctrl,
420 },
421 .sources = &clkset_group2,
422 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
423 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
424 }, {
425 .clk = {
426 .name = "sclk_mmc",
427 .id = 1,
428 .ctrlbit = (1 << 25),
429 .enable = s5p64x0_sclk_ctrl,
430 },
431 .sources = &clkset_group2,
432 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
433 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
434 }, {
435 .clk = {
436 .name = "sclk_mmc",
437 .id = 2,
438 .ctrlbit = (1 << 26),
439 .enable = s5p64x0_sclk_ctrl,
440 },
441 .sources = &clkset_group2,
442 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
443 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
444 }, {
445 .clk = {
446 .name = "uclk1",
447 .id = -1,
448 .ctrlbit = (1 << 5),
449 .enable = s5p64x0_sclk_ctrl,
450 },
451 .sources = &clkset_uart,
452 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
453 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
454 }, {
455 .clk = {
456 .name = "sclk_spi",
457 .id = 0,
458 .ctrlbit = (1 << 20),
459 .enable = s5p64x0_sclk_ctrl,
460 },
461 .sources = &clkset_group2,
462 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
463 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
464 }, {
465 .clk = {
466 .name = "sclk_spi",
467 .id = 1,
468 .ctrlbit = (1 << 21),
469 .enable = s5p64x0_sclk_ctrl,
470 },
471 .sources = &clkset_group2,
472 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
473 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
474 }, {
475 .clk = {
476 .name = "sclk_fimc",
477 .id = -1,
478 .ctrlbit = (1 << 10),
479 .enable = s5p64x0_sclk_ctrl,
480 },
481 .sources = &clkset_group2,
482 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
483 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
484 }, {
485 .clk = {
486 .name = "aclk_mali",
487 .id = -1,
488 .ctrlbit = (1 << 2),
489 .enable = s5p64x0_sclk1_ctrl,
490 },
491 .sources = &clkset_mali,
492 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
493 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
494 }, {
495 .clk = {
496 .name = "sclk_2d",
497 .id = -1,
498 .ctrlbit = (1 << 12),
499 .enable = s5p64x0_sclk_ctrl,
500 },
501 .sources = &clkset_mali,
502 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
503 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 },
504 }, {
505 .clk = {
506 .name = "sclk_usi",
507 .id = -1,
508 .ctrlbit = (1 << 7),
509 .enable = s5p64x0_sclk_ctrl,
510 },
511 .sources = &clkset_group2,
512 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
513 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 },
514 }, {
515 .clk = {
516 .name = "sclk_camif",
517 .id = -1,
518 .ctrlbit = (1 << 6),
519 .enable = s5p64x0_sclk_ctrl,
520 },
521 .sources = &clkset_group2,
522 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
523 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 },
524 }, {
525 .clk = {
526 .name = "sclk_dispcon",
527 .id = -1,
528 .ctrlbit = (1 << 1),
529 .enable = s5p64x0_sclk1_ctrl,
530 },
531 .sources = &clkset_dispcon,
532 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
533 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
534 }, {
535 .clk = {
536 .name = "sclk_hsmmc44",
537 .id = -1,
538 .ctrlbit = (1 << 30),
539 .enable = s5p64x0_sclk_ctrl,
540 },
541 .sources = &clkset_hsmmc44,
542 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 },
543 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 },
544 },
545};
546
547/* Clock initialization code */
548static struct clksrc_clk *sysclks[] = {
549 &clk_mout_apll,
550 &clk_mout_epll,
551 &clk_dout_epll,
552 &clk_mout_mpll,
553 &clk_dout_mpll,
554 &clk_armclk,
555 &clk_mout_hclk_sel,
556 &clk_dout_pwm_ratio0,
557 &clk_pclk_to_wdt_pwm,
558 &clk_hclk,
559 &clk_pclk,
560 &clk_hclk_low,
561 &clk_pclk_low,
562 &clk_sclk_audio0,
563};
564
565void __init_or_cpufreq s5p6450_setup_clocks(void)
566{
567 struct clk *xtal_clk;
568
569 unsigned long xtal;
570 unsigned long fclk;
571 unsigned long hclk;
572 unsigned long hclk_low;
573 unsigned long pclk;
574 unsigned long pclk_low;
575
576 unsigned long apll;
577 unsigned long mpll;
578 unsigned long epll;
579 unsigned long dpll;
580 unsigned int ptr;
581
582 /* Set S5P6450 functions for clk_fout_epll */
583
584 clk_fout_epll.enable = s5p64x0_epll_enable;
585 clk_fout_epll.ops = &s5p6450_epll_ops;
586
587 clk_48m.enable = s5p64x0_clk48m_ctrl;
588
589 xtal_clk = clk_get(NULL, "ext_xtal");
590 BUG_ON(IS_ERR(xtal_clk));
591
592 xtal = clk_get_rate(xtal_clk);
593 clk_put(xtal_clk);
594
595 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
596 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
597 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
598 __raw_readl(S5P64X0_EPLL_CON_K));
599 dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON),
600 __raw_readl(S5P6450_DPLL_CON_K), pll_4650c);
601
602 clk_fout_apll.rate = apll;
603 clk_fout_mpll.rate = mpll;
604 clk_fout_epll.rate = epll;
605 clk_fout_dpll.rate = dpll;
606
607 printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
608 " E=%ld.%ldMHz, D=%ld.%ldMHz\n",
609 print_mhz(apll), print_mhz(mpll), print_mhz(epll),
610 print_mhz(dpll));
611
612 fclk = clk_get_rate(&clk_armclk.clk);
613 hclk = clk_get_rate(&clk_hclk.clk);
614 pclk = clk_get_rate(&clk_pclk.clk);
615 hclk_low = clk_get_rate(&clk_hclk_low.clk);
616 pclk_low = clk_get_rate(&clk_pclk_low.clk);
617
618 printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
619 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
620 print_mhz(hclk), print_mhz(hclk_low),
621 print_mhz(pclk), print_mhz(pclk_low));
622
623 clk_f.rate = fclk;
624 clk_h.rate = hclk;
625 clk_p.rate = pclk;
626
627 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
628 s3c_set_clksrc(&clksrcs[ptr], true);
629}
630
631void __init s5p6450_register_clocks(void)
632{
633 struct clk *clkp;
634 int ret;
635 int ptr;
636
637 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
638 s3c_register_clksrc(sysclks[ptr], 1);
639
640 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
641 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
642
643 clkp = init_clocks_disable;
644 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
645
646 ret = s3c24xx_register_clock(clkp);
647 if (ret < 0) {
648 printk(KERN_ERR "Failed to register clock %s (%d)\n",
649 clkp->name, ret);
650 }
651 (clkp->enable)(clkp, 0);
652 }
653
654 s3c_pwmclk_init();
655}
diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c
new file mode 100644
index 000000000000..523ba8039ac2
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/clock.c
@@ -0,0 +1,253 @@
1/* linux/arch/arm/mach-s5p64x0/clock.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/sysdev.h>
21#include <linux/io.h>
22
23#include <mach/hardware.h>
24#include <mach/map.h>
25#include <mach/regs-clock.h>
26
27#include <plat/cpu-freq.h>
28#include <plat/clock.h>
29#include <plat/cpu.h>
30#include <plat/pll.h>
31#include <plat/s5p-clock.h>
32#include <plat/clock-clksrc.h>
33#include <plat/s5p6440.h>
34#include <plat/s5p6450.h>
35
36struct clksrc_clk clk_mout_apll = {
37 .clk = {
38 .name = "mout_apll",
39 .id = -1,
40 },
41 .sources = &clk_src_apll,
42 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 0, .size = 1 },
43};
44
45struct clksrc_clk clk_mout_mpll = {
46 .clk = {
47 .name = "mout_mpll",
48 .id = -1,
49 },
50 .sources = &clk_src_mpll,
51 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 1, .size = 1 },
52};
53
54struct clksrc_clk clk_mout_epll = {
55 .clk = {
56 .name = "mout_epll",
57 .id = -1,
58 },
59 .sources = &clk_src_epll,
60 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 2, .size = 1 },
61};
62
63enum perf_level {
64 L0 = 532*1000,
65 L1 = 266*1000,
66 L2 = 133*1000,
67};
68
69static const u32 clock_table[][3] = {
70 /*{ARM_CLK, DIVarm, DIVhclk}*/
71 {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
72 {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
73 {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
74};
75
76int s5p64x0_epll_enable(struct clk *clk, int enable)
77{
78 unsigned int ctrlbit = clk->ctrlbit;
79 unsigned int epll_con = __raw_readl(S5P64X0_EPLL_CON) & ~ctrlbit;
80
81 if (enable)
82 __raw_writel(epll_con | ctrlbit, S5P64X0_EPLL_CON);
83 else
84 __raw_writel(epll_con, S5P64X0_EPLL_CON);
85
86 return 0;
87}
88
89unsigned long s5p64x0_epll_get_rate(struct clk *clk)
90{
91 return clk->rate;
92}
93
94unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
95{
96 unsigned long rate = clk_get_rate(clk->parent);
97 u32 clkdiv;
98
99 /* divisor mask starts at bit0, so no need to shift */
100 clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK;
101
102 return rate / (clkdiv + 1);
103}
104
105unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate)
106{
107 u32 iter;
108
109 for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
110 if (rate > clock_table[iter][0])
111 return clock_table[iter-1][0];
112 }
113
114 return clock_table[ARRAY_SIZE(clock_table) - 1][0];
115}
116
117int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
118{
119 u32 round_tmp;
120 u32 iter;
121 u32 clk_div0_tmp;
122 u32 cur_rate = clk->ops->get_rate(clk);
123 unsigned long flags;
124
125 round_tmp = clk->ops->round_rate(clk, rate);
126 if (round_tmp == cur_rate)
127 return 0;
128
129
130 for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
131 if (round_tmp == clock_table[iter][0])
132 break;
133 }
134
135 if (iter >= ARRAY_SIZE(clock_table))
136 iter = ARRAY_SIZE(clock_table) - 1;
137
138 local_irq_save(flags);
139 if (cur_rate > round_tmp) {
140 /* Frequency Down */
141 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
142 clk_div0_tmp |= clock_table[iter][1];
143 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
144
145 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
146 ~(S5P64X0_CLKDIV0_HCLK_MASK);
147 clk_div0_tmp |= clock_table[iter][2];
148 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
149
150
151 } else {
152 /* Frequency Up */
153 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
154 ~(S5P64X0_CLKDIV0_HCLK_MASK);
155 clk_div0_tmp |= clock_table[iter][2];
156 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
157
158 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
159 clk_div0_tmp |= clock_table[iter][1];
160 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
161 }
162 local_irq_restore(flags);
163
164 clk->rate = clock_table[iter][0];
165
166 return 0;
167}
168
169struct clk_ops s5p64x0_clkarm_ops = {
170 .get_rate = s5p64x0_armclk_get_rate,
171 .set_rate = s5p64x0_armclk_set_rate,
172 .round_rate = s5p64x0_armclk_round_rate,
173};
174
175struct clksrc_clk clk_armclk = {
176 .clk = {
177 .name = "armclk",
178 .id = 1,
179 .parent = &clk_mout_apll.clk,
180 .ops = &s5p64x0_clkarm_ops,
181 },
182 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 0, .size = 4 },
183};
184
185struct clksrc_clk clk_dout_mpll = {
186 .clk = {
187 .name = "dout_mpll",
188 .id = -1,
189 .parent = &clk_mout_mpll.clk,
190 },
191 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 },
192};
193
194struct clk *clkset_hclk_low_list[] = {
195 &clk_mout_apll.clk,
196 &clk_mout_mpll.clk,
197};
198
199struct clksrc_sources clkset_hclk_low = {
200 .sources = clkset_hclk_low_list,
201 .nr_sources = ARRAY_SIZE(clkset_hclk_low_list),
202};
203
204int s5p64x0_pclk_ctrl(struct clk *clk, int enable)
205{
206 return s5p_gatectrl(S5P64X0_CLK_GATE_PCLK, clk, enable);
207}
208
209int s5p64x0_hclk0_ctrl(struct clk *clk, int enable)
210{
211 return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK0, clk, enable);
212}
213
214int s5p64x0_hclk1_ctrl(struct clk *clk, int enable)
215{
216 return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK1, clk, enable);
217}
218
219int s5p64x0_sclk_ctrl(struct clk *clk, int enable)
220{
221 return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK0, clk, enable);
222}
223
224int s5p64x0_sclk1_ctrl(struct clk *clk, int enable)
225{
226 return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK1, clk, enable);
227}
228
229int s5p64x0_mem_ctrl(struct clk *clk, int enable)
230{
231 return s5p_gatectrl(S5P64X0_CLK_GATE_MEM0, clk, enable);
232}
233
234int s5p64x0_clk48m_ctrl(struct clk *clk, int enable)
235{
236 unsigned long flags;
237 u32 val;
238
239 /* can't rely on clock lock, this register has other usages */
240 local_irq_save(flags);
241
242 val = __raw_readl(S5P64X0_OTHERS);
243 if (enable)
244 val |= S5P64X0_OTHERS_USB_SIG_MASK;
245 else
246 val &= ~S5P64X0_OTHERS_USB_SIG_MASK;
247
248 __raw_writel(val, S5P64X0_OTHERS);
249
250 local_irq_restore(flags);
251
252 return 0;
253}
diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c
new file mode 100644
index 000000000000..b8d02eb4cf30
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/cpu.c
@@ -0,0 +1,209 @@
1/* linux/arch/arm/mach-s5p64x0/cpu.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/interrupt.h>
14#include <linux/list.h>
15#include <linux/timer.h>
16#include <linux/init.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/sysdev.h>
20#include <linux/serial_core.h>
21#include <linux/platform_device.h>
22#include <linux/sched.h>
23
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/mach/irq.h>
27#include <asm/proc-fns.h>
28#include <asm/irq.h>
29
30#include <mach/hardware.h>
31#include <mach/map.h>
32#include <mach/regs-clock.h>
33
34#include <plat/regs-serial.h>
35#include <plat/cpu.h>
36#include <plat/devs.h>
37#include <plat/clock.h>
38#include <plat/s5p6440.h>
39#include <plat/s5p6450.h>
40#include <plat/adc-core.h>
41
42/* Initial IO mappings */
43
44static struct map_desc s5p64x0_iodesc[] __initdata = {
45 {
46 .virtual = (unsigned long)S5P_VA_GPIO,
47 .pfn = __phys_to_pfn(S5P64X0_PA_GPIO),
48 .length = SZ_4K,
49 .type = MT_DEVICE,
50 }, {
51 .virtual = (unsigned long)VA_VIC0,
52 .pfn = __phys_to_pfn(S5P64X0_PA_VIC0),
53 .length = SZ_16K,
54 .type = MT_DEVICE,
55 }, {
56 .virtual = (unsigned long)VA_VIC1,
57 .pfn = __phys_to_pfn(S5P64X0_PA_VIC1),
58 .length = SZ_16K,
59 .type = MT_DEVICE,
60 },
61};
62
63static struct map_desc s5p6440_iodesc[] __initdata = {
64 {
65 .virtual = (unsigned long)S3C_VA_UART,
66 .pfn = __phys_to_pfn(S5P6440_PA_UART(0)),
67 .length = SZ_4K,
68 .type = MT_DEVICE,
69 },
70};
71
72static struct map_desc s5p6450_iodesc[] __initdata = {
73 {
74 .virtual = (unsigned long)S3C_VA_UART,
75 .pfn = __phys_to_pfn(S5P6450_PA_UART(0)),
76 .length = SZ_512K,
77 .type = MT_DEVICE,
78 }, {
79 .virtual = (unsigned long)S3C_VA_UART + SZ_512K,
80 .pfn = __phys_to_pfn(S5P6450_PA_UART(5)),
81 .length = SZ_4K,
82 .type = MT_DEVICE,
83 },
84};
85
86static void s5p64x0_idle(void)
87{
88 unsigned long val;
89
90 if (!need_resched()) {
91 val = __raw_readl(S5P64X0_PWR_CFG);
92 val &= ~(0x3 << 5);
93 val |= (0x1 << 5);
94 __raw_writel(val, S5P64X0_PWR_CFG);
95
96 cpu_do_idle();
97 }
98 local_irq_enable();
99}
100
101/*
102 * s5p64x0_map_io
103 *
104 * register the standard CPU IO areas
105 */
106
107void __init s5p6440_map_io(void)
108{
109 /* initialize any device information early */
110 s3c_adc_setname("s3c64xx-adc");
111
112 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
113 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
114}
115
116void __init s5p6450_map_io(void)
117{
118 /* initialize any device information early */
119 s3c_adc_setname("s3c64xx-adc");
120
121 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
122 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6440_iodesc));
123}
124
125/*
126 * s5p64x0_init_clocks
127 *
128 * register and setup the CPU clocks
129 */
130
131void __init s5p6440_init_clocks(int xtal)
132{
133 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
134
135 s3c24xx_register_baseclocks(xtal);
136 s5p_register_clocks(xtal);
137 s5p6440_register_clocks();
138 s5p6440_setup_clocks();
139}
140
141void __init s5p6450_init_clocks(int xtal)
142{
143 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
144
145 s3c24xx_register_baseclocks(xtal);
146 s5p_register_clocks(xtal);
147 s5p6450_register_clocks();
148 s5p6450_setup_clocks();
149}
150
151/*
152 * s5p64x0_init_irq
153 *
154 * register the CPU interrupts
155 */
156
157void __init s5p6440_init_irq(void)
158{
159 /* S5P6440 supports 2 VIC */
160 u32 vic[2];
161
162 /*
163 * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
164 * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
165 */
166 vic[0] = 0xff800ae7;
167 vic[1] = 0xffbf23e5;
168
169 s5p_init_irq(vic, ARRAY_SIZE(vic));
170}
171
172void __init s5p6450_init_irq(void)
173{
174 /* S5P6450 supports only 2 VIC */
175 u32 vic[2];
176
177 /*
178 * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
179 * VIC1 is missing IRQ VIC1[12, 14, 23]
180 */
181 vic[0] = 0xff9f1fff;
182 vic[1] = 0xff7fafff;
183
184 s5p_init_irq(vic, ARRAY_SIZE(vic));
185}
186
187struct sysdev_class s5p64x0_sysclass = {
188 .name = "s5p64x0-core",
189};
190
191static struct sys_device s5p64x0_sysdev = {
192 .cls = &s5p64x0_sysclass,
193};
194
195static int __init s5p64x0_core_init(void)
196{
197 return sysdev_class_register(&s5p64x0_sysclass);
198}
199core_initcall(s5p64x0_core_init);
200
201int __init s5p64x0_init(void)
202{
203 printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
204
205 /* set idle function */
206 pm_idle = s5p64x0_idle;
207
208 return sysdev_register(&s5p64x0_sysdev);
209}
diff --git a/arch/arm/mach-s5p64x0/dev-audio.c b/arch/arm/mach-s5p64x0/dev-audio.c
new file mode 100644
index 000000000000..fa097bd68ca4
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/dev-audio.c
@@ -0,0 +1,164 @@
1/* linux/arch/arm/mach-s5p64x0/dev-audio.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co. Ltd
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <plat/gpio-cfg.h>
16#include <plat/audio.h>
17
18#include <mach/map.h>
19#include <mach/dma.h>
20#include <mach/irqs.h>
21
22static int s5p6440_cfg_i2s(struct platform_device *pdev)
23{
24 /* configure GPIO for i2s port */
25 switch (pdev->id) {
26 case -1:
27 s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5));
28 s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5));
29 s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5));
30 s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5));
31 s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5));
32 s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5));
33 s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5));
34 break;
35
36 default:
37 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
38 return -EINVAL;
39 }
40
41 return 0;
42}
43
44static int s5p6450_cfg_i2s(struct platform_device *pdev)
45{
46 /* configure GPIO for i2s port */
47 switch (pdev->id) {
48 case -1:
49 s3c_gpio_cfgpin(S5P6450_GPB(4), S3C_GPIO_SFN(5));
50 s3c_gpio_cfgpin(S5P6450_GPR(4), S3C_GPIO_SFN(5));
51 s3c_gpio_cfgpin(S5P6450_GPR(5), S3C_GPIO_SFN(5));
52 s3c_gpio_cfgpin(S5P6450_GPR(6), S3C_GPIO_SFN(5));
53 s3c_gpio_cfgpin(S5P6450_GPR(7), S3C_GPIO_SFN(5));
54 s3c_gpio_cfgpin(S5P6450_GPR(8), S3C_GPIO_SFN(5));
55 s3c_gpio_cfgpin(S5P6450_GPR(13), S3C_GPIO_SFN(5));
56 s3c_gpio_cfgpin(S5P6450_GPR(14), S3C_GPIO_SFN(5));
57 break;
58
59 default:
60 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
61 return -EINVAL;
62 }
63
64 return 0;
65}
66
67static struct s3c_audio_pdata s5p6440_i2s_pdata = {
68 .cfg_gpio = s5p6440_cfg_i2s,
69};
70
71static struct s3c_audio_pdata s5p6450_i2s_pdata = {
72 .cfg_gpio = s5p6450_cfg_i2s,
73};
74
75static struct resource s5p64x0_iis0_resource[] = {
76 [0] = {
77 .start = S5P64X0_PA_I2S,
78 .end = S5P64X0_PA_I2S + 0x100 - 1,
79 .flags = IORESOURCE_MEM,
80 },
81 [1] = {
82 .start = DMACH_I2S0_TX,
83 .end = DMACH_I2S0_TX,
84 .flags = IORESOURCE_DMA,
85 },
86 [2] = {
87 .start = DMACH_I2S0_RX,
88 .end = DMACH_I2S0_RX,
89 .flags = IORESOURCE_DMA,
90 },
91};
92
93struct platform_device s5p6440_device_iis = {
94 .name = "s3c64xx-iis-v4",
95 .id = -1,
96 .num_resources = ARRAY_SIZE(s5p64x0_iis0_resource),
97 .resource = s5p64x0_iis0_resource,
98 .dev = {
99 .platform_data = &s5p6440_i2s_pdata,
100 },
101};
102
103struct platform_device s5p6450_device_iis0 = {
104 .name = "s3c64xx-iis-v4",
105 .id = -1,
106 .num_resources = ARRAY_SIZE(s5p64x0_iis0_resource),
107 .resource = s5p64x0_iis0_resource,
108 .dev = {
109 .platform_data = &s5p6450_i2s_pdata,
110 },
111};
112
113/* PCM Controller platform_devices */
114
115static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
116{
117 switch (pdev->id) {
118 case 0:
119 s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2));
120 s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2));
121 s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2));
122 s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2));
123 s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2));
124 break;
125
126 default:
127 printk(KERN_DEBUG "Invalid PCM Controller number!");
128 return -EINVAL;
129 }
130
131 return 0;
132}
133
134static struct s3c_audio_pdata s5p6440_pcm_pdata = {
135 .cfg_gpio = s5p6440_pcm_cfg_gpio,
136};
137
138static struct resource s5p6440_pcm0_resource[] = {
139 [0] = {
140 .start = S5P64X0_PA_PCM,
141 .end = S5P64X0_PA_PCM + 0x100 - 1,
142 .flags = IORESOURCE_MEM,
143 },
144 [1] = {
145 .start = DMACH_PCM0_TX,
146 .end = DMACH_PCM0_TX,
147 .flags = IORESOURCE_DMA,
148 },
149 [2] = {
150 .start = DMACH_PCM0_RX,
151 .end = DMACH_PCM0_RX,
152 .flags = IORESOURCE_DMA,
153 },
154};
155
156struct platform_device s5p6440_device_pcm = {
157 .name = "samsung-pcm",
158 .id = 0,
159 .num_resources = ARRAY_SIZE(s5p6440_pcm0_resource),
160 .resource = s5p6440_pcm0_resource,
161 .dev = {
162 .platform_data = &s5p6440_pcm_pdata,
163 },
164};
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
new file mode 100644
index 000000000000..5b69ec4c8af3
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/dev-spi.c
@@ -0,0 +1,232 @@
1/* linux/arch/arm/mach-s5p64x0/dev-spi.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/platform_device.h>
15#include <linux/dma-mapping.h>
16#include <linux/gpio.h>
17
18#include <mach/dma.h>
19#include <mach/map.h>
20#include <mach/irqs.h>
21#include <mach/regs-clock.h>
22#include <mach/spi-clocks.h>
23
24#include <plat/s3c64xx-spi.h>
25#include <plat/gpio-cfg.h>
26
27static char *s5p64x0_spi_src_clks[] = {
28 [S5P64X0_SPI_SRCCLK_PCLK] = "pclk",
29 [S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi",
30};
31
32/* SPI Controller platform_devices */
33
34/* Since we emulate multi-cs capability, we do not touch the CS.
35 * The emulated CS is toggled by board specific mechanism, as it can
36 * be either some immediate GPIO or some signal out of some other
37 * chip in between ... or some yet another way.
38 * We simply do not assume anything about CS.
39 */
40static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
41{
42 switch (pdev->id) {
43 case 0:
44 s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2));
45 s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2));
46 s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2));
47 s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP);
48 s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP);
49 s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP);
50 break;
51
52 case 1:
53 s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2));
54 s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2));
55 s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2));
56 s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP);
57 s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP);
58 s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP);
59 break;
60
61 default:
62 dev_err(&pdev->dev, "Invalid SPI Controller number!");
63 return -EINVAL;
64 }
65
66 return 0;
67}
68
69static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
70{
71 switch (pdev->id) {
72 case 0:
73 s3c_gpio_cfgpin(S5P6450_GPC(0), S3C_GPIO_SFN(2));
74 s3c_gpio_cfgpin(S5P6450_GPC(1), S3C_GPIO_SFN(2));
75 s3c_gpio_cfgpin(S5P6450_GPC(2), S3C_GPIO_SFN(2));
76 s3c_gpio_setpull(S5P6450_GPC(0), S3C_GPIO_PULL_UP);
77 s3c_gpio_setpull(S5P6450_GPC(1), S3C_GPIO_PULL_UP);
78 s3c_gpio_setpull(S5P6450_GPC(2), S3C_GPIO_PULL_UP);
79 break;
80
81 case 1:
82 s3c_gpio_cfgpin(S5P6450_GPC(4), S3C_GPIO_SFN(2));
83 s3c_gpio_cfgpin(S5P6450_GPC(5), S3C_GPIO_SFN(2));
84 s3c_gpio_cfgpin(S5P6450_GPC(6), S3C_GPIO_SFN(2));
85 s3c_gpio_setpull(S5P6450_GPC(4), S3C_GPIO_PULL_UP);
86 s3c_gpio_setpull(S5P6450_GPC(5), S3C_GPIO_PULL_UP);
87 s3c_gpio_setpull(S5P6450_GPC(6), S3C_GPIO_PULL_UP);
88 break;
89
90 default:
91 dev_err(&pdev->dev, "Invalid SPI Controller number!");
92 return -EINVAL;
93 }
94
95 return 0;
96}
97
98static struct resource s5p64x0_spi0_resource[] = {
99 [0] = {
100 .start = S5P64X0_PA_SPI0,
101 .end = S5P64X0_PA_SPI0 + 0x100 - 1,
102 .flags = IORESOURCE_MEM,
103 },
104 [1] = {
105 .start = DMACH_SPI0_TX,
106 .end = DMACH_SPI0_TX,
107 .flags = IORESOURCE_DMA,
108 },
109 [2] = {
110 .start = DMACH_SPI0_RX,
111 .end = DMACH_SPI0_RX,
112 .flags = IORESOURCE_DMA,
113 },
114 [3] = {
115 .start = IRQ_SPI0,
116 .end = IRQ_SPI0,
117 .flags = IORESOURCE_IRQ,
118 },
119};
120
121static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
122 .cfg_gpio = s5p6440_spi_cfg_gpio,
123 .fifo_lvl_mask = 0x1ff,
124 .rx_lvl_offset = 15,
125};
126
127static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
128 .cfg_gpio = s5p6450_spi_cfg_gpio,
129 .fifo_lvl_mask = 0x1ff,
130 .rx_lvl_offset = 15,
131};
132
133static u64 spi_dmamask = DMA_BIT_MASK(32);
134
135struct platform_device s5p64x0_device_spi0 = {
136 .name = "s3c64xx-spi",
137 .id = 0,
138 .num_resources = ARRAY_SIZE(s5p64x0_spi0_resource),
139 .resource = s5p64x0_spi0_resource,
140 .dev = {
141 .dma_mask = &spi_dmamask,
142 .coherent_dma_mask = DMA_BIT_MASK(32),
143 },
144};
145
146static struct resource s5p64x0_spi1_resource[] = {
147 [0] = {
148 .start = S5P64X0_PA_SPI1,
149 .end = S5P64X0_PA_SPI1 + 0x100 - 1,
150 .flags = IORESOURCE_MEM,
151 },
152 [1] = {
153 .start = DMACH_SPI1_TX,
154 .end = DMACH_SPI1_TX,
155 .flags = IORESOURCE_DMA,
156 },
157 [2] = {
158 .start = DMACH_SPI1_RX,
159 .end = DMACH_SPI1_RX,
160 .flags = IORESOURCE_DMA,
161 },
162 [3] = {
163 .start = IRQ_SPI1,
164 .end = IRQ_SPI1,
165 .flags = IORESOURCE_IRQ,
166 },
167};
168
169static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
170 .cfg_gpio = s5p6440_spi_cfg_gpio,
171 .fifo_lvl_mask = 0x7f,
172 .rx_lvl_offset = 15,
173};
174
175static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
176 .cfg_gpio = s5p6450_spi_cfg_gpio,
177 .fifo_lvl_mask = 0x7f,
178 .rx_lvl_offset = 15,
179};
180
181struct platform_device s5p64x0_device_spi1 = {
182 .name = "s3c64xx-spi",
183 .id = 1,
184 .num_resources = ARRAY_SIZE(s5p64x0_spi1_resource),
185 .resource = s5p64x0_spi1_resource,
186 .dev = {
187 .dma_mask = &spi_dmamask,
188 .coherent_dma_mask = DMA_BIT_MASK(32),
189 },
190};
191
192void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
193{
194 unsigned int id;
195 struct s3c64xx_spi_info *pd;
196
197 id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
198
199 /* Reject invalid configuration */
200 if (!num_cs || src_clk_nr < 0
201 || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
202 printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
203 return;
204 }
205
206 switch (cntrlr) {
207 case 0:
208 if (id == 0x50000)
209 pd = &s5p6450_spi0_pdata;
210 else
211 pd = &s5p6440_spi0_pdata;
212
213 s5p64x0_device_spi0.dev.platform_data = pd;
214 break;
215 case 1:
216 if (id == 0x50000)
217 pd = &s5p6450_spi1_pdata;
218 else
219 pd = &s5p6440_spi1_pdata;
220
221 s5p64x0_device_spi1.dev.platform_data = pd;
222 break;
223 default:
224 printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
225 __func__, cntrlr);
226 return;
227 }
228
229 pd->num_cs = num_cs;
230 pd->src_clk_nr = src_clk_nr;
231 pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];
232}
diff --git a/arch/arm/mach-s5p6440/dma.c b/arch/arm/mach-s5p64x0/dma.c
index 07606ad57519..29a8c2410049 100644
--- a/arch/arm/mach-s5p6440/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -1,4 +1,8 @@
1/* 1/* linux/arch/arm/mach-s5p64x0/dma.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd. 6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com> 7 * Jaswinder Singh <jassi.brar@samsung.com>
4 * 8 *
@@ -15,26 +19,25 @@
15 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */ 22*/
19 23
20#include <linux/platform_device.h> 24#include <linux/platform_device.h>
21#include <linux/dma-mapping.h> 25#include <linux/dma-mapping.h>
22 26
23#include <plat/devs.h>
24#include <plat/irqs.h>
25
26#include <mach/map.h> 27#include <mach/map.h>
27#include <mach/irqs.h> 28#include <mach/irqs.h>
29#include <mach/regs-clock.h>
28 30
31#include <plat/devs.h>
29#include <plat/s3c-pl330-pdata.h> 32#include <plat/s3c-pl330-pdata.h>
30 33
31static u64 dma_dmamask = DMA_BIT_MASK(32); 34static u64 dma_dmamask = DMA_BIT_MASK(32);
32 35
33static struct resource s5p6440_pdma_resource[] = { 36static struct resource s5p64x0_pdma_resource[] = {
34 [0] = { 37 [0] = {
35 .start = S5P6440_PA_PDMA, 38 .start = S5P64X0_PA_PDMA,
36 .end = S5P6440_PA_PDMA + SZ_4K, 39 .end = S5P64X0_PA_PDMA + SZ_4K,
37 .flags = IORESOURCE_MEM, 40 .flags = IORESOURCE_MEM,
38 }, 41 },
39 [1] = { 42 [1] = {
40 .start = IRQ_DMA0, 43 .start = IRQ_DMA0,
@@ -80,26 +83,67 @@ static struct s3c_pl330_platdata s5p6440_pdma_pdata = {
80 }, 83 },
81}; 84};
82 85
83static struct platform_device s5p6440_device_pdma = { 86static struct s3c_pl330_platdata s5p6450_pdma_pdata = {
87 .peri = {
88 [0] = DMACH_UART0_RX,
89 [1] = DMACH_UART0_TX,
90 [2] = DMACH_UART1_RX,
91 [3] = DMACH_UART1_TX,
92 [4] = DMACH_UART2_RX,
93 [5] = DMACH_UART2_TX,
94 [6] = DMACH_UART3_RX,
95 [7] = DMACH_UART3_TX,
96 [8] = DMACH_UART4_RX,
97 [9] = DMACH_UART4_TX,
98 [10] = DMACH_PCM0_TX,
99 [11] = DMACH_PCM0_RX,
100 [12] = DMACH_I2S0_TX,
101 [13] = DMACH_I2S0_RX,
102 [14] = DMACH_SPI0_TX,
103 [15] = DMACH_SPI0_RX,
104 [16] = DMACH_PCM1_TX,
105 [17] = DMACH_PCM1_RX,
106 [18] = DMACH_PCM2_TX,
107 [19] = DMACH_PCM2_RX,
108 [20] = DMACH_SPI1_TX,
109 [21] = DMACH_SPI1_RX,
110 [22] = DMACH_USI_TX,
111 [23] = DMACH_USI_RX,
112 [24] = DMACH_MAX,
113 [25] = DMACH_I2S1_TX,
114 [26] = DMACH_I2S1_RX,
115 [27] = DMACH_I2S2_TX,
116 [28] = DMACH_I2S2_RX,
117 [29] = DMACH_PWM,
118 [30] = DMACH_UART5_RX,
119 [31] = DMACH_UART5_TX,
120 },
121};
122
123static struct platform_device s5p64x0_device_pdma = {
84 .name = "s3c-pl330", 124 .name = "s3c-pl330",
85 .id = 1, 125 .id = 0,
86 .num_resources = ARRAY_SIZE(s5p6440_pdma_resource), 126 .num_resources = ARRAY_SIZE(s5p64x0_pdma_resource),
87 .resource = s5p6440_pdma_resource, 127 .resource = s5p64x0_pdma_resource,
88 .dev = { 128 .dev = {
89 .dma_mask = &dma_dmamask, 129 .dma_mask = &dma_dmamask,
90 .coherent_dma_mask = DMA_BIT_MASK(32), 130 .coherent_dma_mask = DMA_BIT_MASK(32),
91 .platform_data = &s5p6440_pdma_pdata,
92 }, 131 },
93}; 132};
94 133
95static struct platform_device *s5p6440_dmacs[] __initdata = { 134static int __init s5p64x0_dma_init(void)
96 &s5p6440_device_pdma,
97};
98
99static int __init s5p6440_dma_init(void)
100{ 135{
101 platform_add_devices(s5p6440_dmacs, ARRAY_SIZE(s5p6440_dmacs)); 136 unsigned int id;
137
138 id = __raw_readl(S5P64X0_SYS_ID) & 0xFF000;
139
140 if (id == 0x50000)
141 s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
142 else
143 s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
144
145 platform_device_register(&s5p64x0_device_pdma);
102 146
103 return 0; 147 return 0;
104} 148}
105arch_initcall(s5p6440_dma_init); 149arch_initcall(s5p64x0_dma_init);
diff --git a/arch/arm/mach-s5p6440/gpio.c b/arch/arm/mach-s5p64x0/gpio.c
index 8bf6e0ce51c9..39159dd5a29a 100644
--- a/arch/arm/mach-s5p6440/gpio.c
+++ b/arch/arm/mach-s5p64x0/gpio.c
@@ -1,14 +1,14 @@
1/* arch/arm/mach-s5p6440/gpio.c 1/* linux/arch/arm/mach-s5p64x0/gpio.c
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P6440 - GPIOlib support 6 * S5P64X0 - GPIOlib support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11*/
12 12
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/irq.h> 14#include <linux/irq.h>
@@ -22,26 +22,29 @@
22#include <plat/gpio-cfg.h> 22#include <plat/gpio-cfg.h>
23#include <plat/gpio-cfg-helpers.h> 23#include <plat/gpio-cfg-helpers.h>
24 24
25/* GPIO bank summary: 25/* To be implemented S5P6450 GPIO */
26* 26
27* Bank GPIOs Style SlpCon ExtInt Group 27/*
28* A 6 4Bit Yes 1 28 * S5P6440 GPIO bank summary:
29* B 7 4Bit Yes 1 29 *
30* C 8 4Bit Yes 2 30 * Bank GPIOs Style SlpCon ExtInt Group
31* F 2 2Bit Yes 4 [1] 31 * A 6 4Bit Yes 1
32* G 7 4Bit Yes 5 32 * B 7 4Bit Yes 1
33* H 10 4Bit[2] Yes 6 33 * C 8 4Bit Yes 2
34* I 16 2Bit Yes None 34 * F 2 2Bit Yes 4 [1]
35* J 12 2Bit Yes None 35 * G 7 4Bit Yes 5
36* N 16 2Bit No IRQ_EINT 36 * H 10 4Bit[2] Yes 6
37* P 8 2Bit Yes 8 37 * I 16 2Bit Yes None
38* R 15 4Bit[2] Yes 8 38 * J 12 2Bit Yes None
39* 39 * N 16 2Bit No IRQ_EINT
40* [1] BANKF pins 14,15 do not form part of the external interrupt sources 40 * P 8 2Bit Yes 8
41* [2] BANK has two control registers, GPxCON0 and GPxCON1 41 * R 15 4Bit[2] Yes 8
42*/ 42 *
43 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
44 * [2] BANK has two control registers, GPxCON0 and GPxCON1
45 */
43 46
44static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip, 47static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
45 unsigned int offset) 48 unsigned int offset)
46{ 49{
47 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); 50 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
@@ -77,7 +80,7 @@ static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
77 return 0; 80 return 0;
78} 81}
79 82
80static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip, 83static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
81 unsigned int offset, int value) 84 unsigned int offset, int value)
82{ 85{
83 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); 86 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
@@ -124,12 +127,11 @@ static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
124 return 0; 127 return 0;
125} 128}
126 129
127int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip, 130int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
128 unsigned int off, unsigned int cfg) 131 unsigned int off, unsigned int cfg)
129{ 132{
130 void __iomem *reg = chip->base; 133 void __iomem *reg = chip->base;
131 unsigned int shift; 134 unsigned int shift;
132 unsigned long flags;
133 u32 con; 135 u32 con;
134 136
135 switch (off) { 137 switch (off) {
@@ -155,26 +157,22 @@ int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
155 cfg <<= shift; 157 cfg <<= shift;
156 } 158 }
157 159
158 s3c_gpio_lock(chip, flags);
159
160 con = __raw_readl(reg); 160 con = __raw_readl(reg);
161 con &= ~(0xf << shift); 161 con &= ~(0xf << shift);
162 con |= cfg; 162 con |= cfg;
163 __raw_writel(con, reg); 163 __raw_writel(con, reg);
164 164
165 s3c_gpio_unlock(chip, flags);
166
167 return 0; 165 return 0;
168} 166}
169 167
170static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = { 168static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
171 { 169 {
172 .cfg_eint = 0, 170 .cfg_eint = 0,
173 }, { 171 }, {
174 .cfg_eint = 7, 172 .cfg_eint = 7,
175 }, { 173 }, {
176 .cfg_eint = 3, 174 .cfg_eint = 3,
177 .set_config = s5p6440_gpio_setcfg_4bit_rbank, 175 .set_config = s5p64x0_gpio_setcfg_4bit_rbank,
178 }, { 176 }, {
179 .cfg_eint = 0, 177 .cfg_eint = 0,
180 .set_config = s3c_gpio_setcfg_s3c24xx, 178 .set_config = s3c_gpio_setcfg_s3c24xx,
@@ -193,7 +191,7 @@ static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
193static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { 191static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
194 { 192 {
195 .base = S5P6440_GPA_BASE, 193 .base = S5P6440_GPA_BASE,
196 .config = &s5p6440_gpio_cfgs[1], 194 .config = &s5p64x0_gpio_cfgs[1],
197 .chip = { 195 .chip = {
198 .base = S5P6440_GPA(0), 196 .base = S5P6440_GPA(0),
199 .ngpio = S5P6440_GPIO_A_NR, 197 .ngpio = S5P6440_GPIO_A_NR,
@@ -201,7 +199,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
201 }, 199 },
202 }, { 200 }, {
203 .base = S5P6440_GPB_BASE, 201 .base = S5P6440_GPB_BASE,
204 .config = &s5p6440_gpio_cfgs[1], 202 .config = &s5p64x0_gpio_cfgs[1],
205 .chip = { 203 .chip = {
206 .base = S5P6440_GPB(0), 204 .base = S5P6440_GPB(0),
207 .ngpio = S5P6440_GPIO_B_NR, 205 .ngpio = S5P6440_GPIO_B_NR,
@@ -209,7 +207,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
209 }, 207 },
210 }, { 208 }, {
211 .base = S5P6440_GPC_BASE, 209 .base = S5P6440_GPC_BASE,
212 .config = &s5p6440_gpio_cfgs[1], 210 .config = &s5p64x0_gpio_cfgs[1],
213 .chip = { 211 .chip = {
214 .base = S5P6440_GPC(0), 212 .base = S5P6440_GPC(0),
215 .ngpio = S5P6440_GPIO_C_NR, 213 .ngpio = S5P6440_GPIO_C_NR,
@@ -217,7 +215,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
217 }, 215 },
218 }, { 216 }, {
219 .base = S5P6440_GPG_BASE, 217 .base = S5P6440_GPG_BASE,
220 .config = &s5p6440_gpio_cfgs[1], 218 .config = &s5p64x0_gpio_cfgs[1],
221 .chip = { 219 .chip = {
222 .base = S5P6440_GPG(0), 220 .base = S5P6440_GPG(0),
223 .ngpio = S5P6440_GPIO_G_NR, 221 .ngpio = S5P6440_GPIO_G_NR,
@@ -229,7 +227,7 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
229static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = { 227static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
230 { 228 {
231 .base = S5P6440_GPH_BASE + 0x4, 229 .base = S5P6440_GPH_BASE + 0x4,
232 .config = &s5p6440_gpio_cfgs[1], 230 .config = &s5p64x0_gpio_cfgs[1],
233 .chip = { 231 .chip = {
234 .base = S5P6440_GPH(0), 232 .base = S5P6440_GPH(0),
235 .ngpio = S5P6440_GPIO_H_NR, 233 .ngpio = S5P6440_GPIO_H_NR,
@@ -238,10 +236,10 @@ static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
238 }, 236 },
239}; 237};
240 238
241static struct s3c_gpio_chip gpio_rbank_4bit2[] = { 239static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
242 { 240 {
243 .base = S5P6440_GPR_BASE + 0x4, 241 .base = S5P6440_GPR_BASE + 0x4,
244 .config = &s5p6440_gpio_cfgs[2], 242 .config = &s5p64x0_gpio_cfgs[2],
245 .chip = { 243 .chip = {
246 .base = S5P6440_GPR(0), 244 .base = S5P6440_GPR(0),
247 .ngpio = S5P6440_GPIO_R_NR, 245 .ngpio = S5P6440_GPIO_R_NR,
@@ -253,7 +251,7 @@ static struct s3c_gpio_chip gpio_rbank_4bit2[] = {
253static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { 251static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
254 { 252 {
255 .base = S5P6440_GPF_BASE, 253 .base = S5P6440_GPF_BASE,
256 .config = &s5p6440_gpio_cfgs[5], 254 .config = &s5p64x0_gpio_cfgs[5],
257 .chip = { 255 .chip = {
258 .base = S5P6440_GPF(0), 256 .base = S5P6440_GPF(0),
259 .ngpio = S5P6440_GPIO_F_NR, 257 .ngpio = S5P6440_GPIO_F_NR,
@@ -261,7 +259,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
261 }, 259 },
262 }, { 260 }, {
263 .base = S5P6440_GPI_BASE, 261 .base = S5P6440_GPI_BASE,
264 .config = &s5p6440_gpio_cfgs[3], 262 .config = &s5p64x0_gpio_cfgs[3],
265 .chip = { 263 .chip = {
266 .base = S5P6440_GPI(0), 264 .base = S5P6440_GPI(0),
267 .ngpio = S5P6440_GPIO_I_NR, 265 .ngpio = S5P6440_GPIO_I_NR,
@@ -269,7 +267,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
269 }, 267 },
270 }, { 268 }, {
271 .base = S5P6440_GPJ_BASE, 269 .base = S5P6440_GPJ_BASE,
272 .config = &s5p6440_gpio_cfgs[3], 270 .config = &s5p64x0_gpio_cfgs[3],
273 .chip = { 271 .chip = {
274 .base = S5P6440_GPJ(0), 272 .base = S5P6440_GPJ(0),
275 .ngpio = S5P6440_GPIO_J_NR, 273 .ngpio = S5P6440_GPIO_J_NR,
@@ -277,7 +275,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
277 }, 275 },
278 }, { 276 }, {
279 .base = S5P6440_GPN_BASE, 277 .base = S5P6440_GPN_BASE,
280 .config = &s5p6440_gpio_cfgs[4], 278 .config = &s5p64x0_gpio_cfgs[4],
281 .chip = { 279 .chip = {
282 .base = S5P6440_GPN(0), 280 .base = S5P6440_GPN(0),
283 .ngpio = S5P6440_GPIO_N_NR, 281 .ngpio = S5P6440_GPIO_N_NR,
@@ -285,7 +283,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
285 }, 283 },
286 }, { 284 }, {
287 .base = S5P6440_GPP_BASE, 285 .base = S5P6440_GPP_BASE,
288 .config = &s5p6440_gpio_cfgs[5], 286 .config = &s5p64x0_gpio_cfgs[5],
289 .chip = { 287 .chip = {
290 .base = S5P6440_GPP(0), 288 .base = S5P6440_GPP(0),
291 .ngpio = S5P6440_GPIO_P_NR, 289 .ngpio = S5P6440_GPIO_P_NR,
@@ -294,7 +292,7 @@ static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
294 }, 292 },
295}; 293};
296 294
297void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips) 295void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
298{ 296{
299 for (; nr_chips > 0; nr_chips--, chipcfg++) { 297 for (; nr_chips > 0; nr_chips--, chipcfg++) {
300 if (!chipcfg->set_config) 298 if (!chipcfg->set_config)
@@ -308,13 +306,13 @@ void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
308 } 306 }
309} 307}
310 308
311static void __init s5p6440_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip, 309static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
312 int nr_chips) 310 int nr_chips)
313{ 311{
314 for (; nr_chips > 0; nr_chips--, chip++) { 312 for (; nr_chips > 0; nr_chips--, chip++) {
315 chip->chip.direction_input = s5p6440_gpiolib_rbank_4bit2_input; 313 chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
316 chip->chip.direction_output = 314 chip->chip.direction_output =
317 s5p6440_gpiolib_rbank_4bit2_output; 315 s5p64x0_gpiolib_rbank_4bit2_output;
318 s3c_gpiolib_add(chip); 316 s3c_gpiolib_add(chip);
319 } 317 }
320} 318}
@@ -324,8 +322,8 @@ static int __init s5p6440_gpiolib_init(void)
324 struct s3c_gpio_chip *chips = s5p6440_gpio_2bit; 322 struct s3c_gpio_chip *chips = s5p6440_gpio_2bit;
325 int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit); 323 int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit);
326 324
327 s5p6440_gpiolib_set_cfg(s5p6440_gpio_cfgs, 325 s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
328 ARRAY_SIZE(s5p6440_gpio_cfgs)); 326 ARRAY_SIZE(s5p64x0_gpio_cfgs));
329 327
330 for (; nr_chips > 0; nr_chips--, chips++) 328 for (; nr_chips > 0; nr_chips--, chips++)
331 s3c_gpiolib_add(chips); 329 s3c_gpiolib_add(chips);
@@ -336,8 +334,8 @@ static int __init s5p6440_gpiolib_init(void)
336 samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2, 334 samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
337 ARRAY_SIZE(s5p6440_gpio_4bit2)); 335 ARRAY_SIZE(s5p6440_gpio_4bit2));
338 336
339 s5p6440_gpio_add_rbank_4bit2(gpio_rbank_4bit2, 337 s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
340 ARRAY_SIZE(gpio_rbank_4bit2)); 338 ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
341 339
342 return 0; 340 return 0;
343} 341}
diff --git a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
new file mode 100644
index 000000000000..79b04e6a6f8e
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
@@ -0,0 +1,33 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11/* pull in the relevant register and map files. */
12
13#include <plat/map-base.h>
14#include <plat/map-s5p.h>
15
16#include <plat/regs-serial.h>
17
18 .macro addruart, rp, rv
19 mov \rp, #0xE0000000
20 orr \rp, \rp, #0x00100000
21 ldr \rp, [\rp, #0x118 ]
22 and \rp, \rp, #0xff000
23 teq \rp, #0x50000 @@ S5P6450
24 ldreq \rp, =0xEC800000
25 movne \rp, #0xEC000000 @@ S5P6440
26 ldrne \rv, = S3C_VA_UART
27#if CONFIG_DEBUG_S3C_UART != 0
28 add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
29 add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
30#endif
31 .endm
32
33#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5p6440/include/mach/dma.h b/arch/arm/mach-s5p64x0/include/mach/dma.h
index 81209eb1409b..81209eb1409b 100644
--- a/arch/arm/mach-s5p6440/include/mach/dma.h
+++ b/arch/arm/mach-s5p64x0/include/mach/dma.h
diff --git a/arch/arm/mach-s5p6440/include/mach/entry-macro.S b/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
index e65f1b967262..10b62b4f8211 100644
--- a/arch/arm/mach-s5p6440/include/mach/entry-macro.S
+++ b/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/entry-macro.S 1/* linux/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Low-level IRQ helper macros for the Samsung S5P6440 6 * Low-level IRQ helper macros for the Samsung S5P64X0
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/gpio.h b/arch/arm/mach-s5p64x0/include/mach/gpio.h
new file mode 100644
index 000000000000..5486c8f01f1d
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/gpio.h
@@ -0,0 +1,139 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/gpio.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16#define gpio_get_value __gpio_get_value
17#define gpio_set_value __gpio_set_value
18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq
20
21/* GPIO bank sizes */
22
23#define S5P6440_GPIO_A_NR (6)
24#define S5P6440_GPIO_B_NR (7)
25#define S5P6440_GPIO_C_NR (8)
26#define S5P6440_GPIO_F_NR (2)
27#define S5P6440_GPIO_G_NR (7)
28#define S5P6440_GPIO_H_NR (10)
29#define S5P6440_GPIO_I_NR (16)
30#define S5P6440_GPIO_J_NR (12)
31#define S5P6440_GPIO_N_NR (16)
32#define S5P6440_GPIO_P_NR (8)
33#define S5P6440_GPIO_R_NR (15)
34
35#define S5P6450_GPIO_A_NR (6)
36#define S5P6450_GPIO_B_NR (7)
37#define S5P6450_GPIO_C_NR (8)
38#define S5P6450_GPIO_D_NR (8)
39#define S5P6450_GPIO_F_NR (2)
40#define S5P6450_GPIO_G_NR (14)
41#define S5P6450_GPIO_H_NR (10)
42#define S5P6450_GPIO_I_NR (16)
43#define S5P6450_GPIO_J_NR (12)
44#define S5P6450_GPIO_K_NR (5)
45#define S5P6450_GPIO_N_NR (16)
46#define S5P6450_GPIO_P_NR (11)
47#define S5P6450_GPIO_Q_NR (14)
48#define S5P6450_GPIO_R_NR (15)
49#define S5P6450_GPIO_S_NR (8)
50
51/* GPIO bank numbers */
52
53/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
54 * space for debugging purposes so that any accidental
55 * change from one gpio bank to another can be caught.
56*/
57
58#define S5P64X0_GPIO_NEXT(__gpio) \
59 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
60
61enum s5p6440_gpio_number {
62 S5P6440_GPIO_A_START = 0,
63 S5P6440_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_A),
64 S5P6440_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_B),
65 S5P6440_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_C),
66 S5P6440_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_F),
67 S5P6440_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_G),
68 S5P6440_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_H),
69 S5P6440_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_I),
70 S5P6440_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_J),
71 S5P6440_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_N),
72 S5P6440_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_P),
73};
74
75enum s5p6450_gpio_number {
76 S5P6450_GPIO_A_START = 0,
77 S5P6450_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_A),
78 S5P6450_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_B),
79 S5P6450_GPIO_D_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_C),
80 S5P6450_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_D),
81 S5P6450_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_F),
82 S5P6450_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_G),
83 S5P6450_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_H),
84 S5P6450_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_I),
85 S5P6450_GPIO_K_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_J),
86 S5P6450_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_K),
87 S5P6450_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_N),
88 S5P6450_GPIO_Q_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_P),
89 S5P6450_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_Q),
90 S5P6450_GPIO_S_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_R),
91};
92
93/* GPIO number definitions */
94
95#define S5P6440_GPA(_nr) (S5P6440_GPIO_A_START + (_nr))
96#define S5P6440_GPB(_nr) (S5P6440_GPIO_B_START + (_nr))
97#define S5P6440_GPC(_nr) (S5P6440_GPIO_C_START + (_nr))
98#define S5P6440_GPF(_nr) (S5P6440_GPIO_F_START + (_nr))
99#define S5P6440_GPG(_nr) (S5P6440_GPIO_G_START + (_nr))
100#define S5P6440_GPH(_nr) (S5P6440_GPIO_H_START + (_nr))
101#define S5P6440_GPI(_nr) (S5P6440_GPIO_I_START + (_nr))
102#define S5P6440_GPJ(_nr) (S5P6440_GPIO_J_START + (_nr))
103#define S5P6440_GPN(_nr) (S5P6440_GPIO_N_START + (_nr))
104#define S5P6440_GPP(_nr) (S5P6440_GPIO_P_START + (_nr))
105#define S5P6440_GPR(_nr) (S5P6440_GPIO_R_START + (_nr))
106
107#define S5P6450_GPA(_nr) (S5P6450_GPIO_A_START + (_nr))
108#define S5P6450_GPB(_nr) (S5P6450_GPIO_B_START + (_nr))
109#define S5P6450_GPC(_nr) (S5P6450_GPIO_C_START + (_nr))
110#define S5P6450_GPD(_nr) (S5P6450_GPIO_D_START + (_nr))
111#define S5P6450_GPF(_nr) (S5P6450_GPIO_F_START + (_nr))
112#define S5P6450_GPG(_nr) (S5P6450_GPIO_G_START + (_nr))
113#define S5P6450_GPH(_nr) (S5P6450_GPIO_H_START + (_nr))
114#define S5P6450_GPI(_nr) (S5P6450_GPIO_I_START + (_nr))
115#define S5P6450_GPJ(_nr) (S5P6450_GPIO_J_START + (_nr))
116#define S5P6450_GPK(_nr) (S5P6450_GPIO_K_START + (_nr))
117#define S5P6450_GPN(_nr) (S5P6450_GPIO_N_START + (_nr))
118#define S5P6450_GPP(_nr) (S5P6450_GPIO_P_START + (_nr))
119#define S5P6450_GPQ(_nr) (S5P6450_GPIO_Q_START + (_nr))
120#define S5P6450_GPR(_nr) (S5P6450_GPIO_R_START + (_nr))
121#define S5P6450_GPS(_nr) (S5P6450_GPIO_S_START + (_nr))
122
123/* the end of the S5P64X0 specific gpios */
124
125#define S5P6440_GPIO_END (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
126#define S5P6450_GPIO_END (S5P6450_GPS(S5P6450_GPIO_S_NR) + 1)
127
128#define S5P64X0_GPIO_END (S5P6440_GPIO_END > S5P6450_GPIO_END ? \
129 S5P6440_GPIO_END : S5P6450_GPIO_END)
130
131#define S3C_GPIO_END S5P64X0_GPIO_END
132
133/* define the number of gpios we need to the one after the last GPIO range */
134
135#define ARCH_NR_GPIOS (S5P64X0_GPIO_END + CONFIG_SAMSUNG_GPIO_EXTRA)
136
137#include <asm-generic/gpio.h>
138
139#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/hardware.h b/arch/arm/mach-s5p64x0/include/mach/hardware.h
index be8b26e875db..d3e87996dd9a 100644
--- a/arch/arm/mach-s5p6440/include/mach/hardware.h
+++ b/arch/arm/mach-s5p64x0/include/mach/hardware.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/hardware.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/hardware.h
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P6440 - Hardware support 6 * S5P64X0 - Hardware support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/i2c.h b/arch/arm/mach-s5p64x0/include/mach/i2c.h
new file mode 100644
index 000000000000..887d25209e8e
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/i2c.h
@@ -0,0 +1,17 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/i2c.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 I2C configuration
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13extern void s5p6440_i2c0_cfg_gpio(struct platform_device *dev);
14extern void s5p6440_i2c1_cfg_gpio(struct platform_device *dev);
15
16extern void s5p6450_i2c0_cfg_gpio(struct platform_device *dev);
17extern void s5p6450_i2c1_cfg_gpio(struct platform_device *dev);
diff --git a/arch/arm/mach-s5p64x0/include/mach/io.h b/arch/arm/mach-s5p64x0/include/mach/io.h
new file mode 100644
index 000000000000..a3e095c02fb5
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/io.h
@@ -0,0 +1,25 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/io.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben-linux@fluff.org>
8 *
9 * Default IO routines for S5P64X0 based
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#ifndef __ASM_ARM_ARCH_IO_H
17#define __ASM_ARM_ARCH_IO_H
18
19/* No current ISA/PCI bus support. */
20#define __io(a) __typesafe_io(a)
21#define __mem_pci(a) (a)
22
23#define IO_SPACE_LIMIT (0xFFFFFFFF)
24
25#endif
diff --git a/arch/arm/mach-s5p6440/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
index 16a761270de1..513abffc7604 100644
--- a/arch/arm/mach-s5p6440/include/mach/irqs.h
+++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h
@@ -1,17 +1,17 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/irqs.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/irqs.h
2 * 2 *
3 * Copyright 2009 Samsung Electronics Co., Ltd. 3 * Copyright 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P6440 - IRQ definitions 6 * S5P64X0 - IRQ definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13#ifndef __ASM_ARCH_S5P_IRQS_H 13#ifndef __ASM_ARCH_IRQS_H
14#define __ASM_ARCH_S5P_IRQS_H __FILE__ 14#define __ASM_ARCH_IRQS_H __FILE__
15 15
16#include <plat/irqs.h> 16#include <plat/irqs.h>
17 17
@@ -20,10 +20,12 @@
20#define IRQ_EINT0_3 S5P_IRQ_VIC0(0) 20#define IRQ_EINT0_3 S5P_IRQ_VIC0(0)
21#define IRQ_EINT4_11 S5P_IRQ_VIC0(1) 21#define IRQ_EINT4_11 S5P_IRQ_VIC0(1)
22#define IRQ_RTC_TIC S5P_IRQ_VIC0(2) 22#define IRQ_RTC_TIC S5P_IRQ_VIC0(2)
23#define IRQ_IIS1 S5P_IRQ_VIC0(3) /* for only S5P6450 */
24#define IRQ_IIS2 S5P_IRQ_VIC0(4) /* for only S5P6450 */
23#define IRQ_IIC1 S5P_IRQ_VIC0(5) 25#define IRQ_IIC1 S5P_IRQ_VIC0(5)
24#define IRQ_I2SV40 S5P_IRQ_VIC0(6) 26#define IRQ_I2SV40 S5P_IRQ_VIC0(6)
25#define IRQ_GPS S5P_IRQ_VIC0(7) 27#define IRQ_GPS S5P_IRQ_VIC0(7) /* for only S5P6450 */
26#define IRQ_POST0 S5P_IRQ_VIC0(9) 28
27#define IRQ_2D S5P_IRQ_VIC0(11) 29#define IRQ_2D S5P_IRQ_VIC0(11)
28#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23) 30#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23)
29#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24) 31#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24)
@@ -39,22 +41,26 @@
39 41
40#define IRQ_EINT12_15 S5P_IRQ_VIC1(0) 42#define IRQ_EINT12_15 S5P_IRQ_VIC1(0)
41#define IRQ_PCM0 S5P_IRQ_VIC1(2) 43#define IRQ_PCM0 S5P_IRQ_VIC1(2)
44#define IRQ_PCM1 S5P_IRQ_VIC1(3) /* for only S5P6450 */
45#define IRQ_PCM2 S5P_IRQ_VIC1(4) /* for only S5P6450 */
42#define IRQ_UART0 S5P_IRQ_VIC1(5) 46#define IRQ_UART0 S5P_IRQ_VIC1(5)
43#define IRQ_UART1 S5P_IRQ_VIC1(6) 47#define IRQ_UART1 S5P_IRQ_VIC1(6)
44#define IRQ_UART2 S5P_IRQ_VIC1(7) 48#define IRQ_UART2 S5P_IRQ_VIC1(7)
45#define IRQ_UART3 S5P_IRQ_VIC1(8) 49#define IRQ_UART3 S5P_IRQ_VIC1(8)
46#define IRQ_DMA0 S5P_IRQ_VIC1(9) 50#define IRQ_DMA0 S5P_IRQ_VIC1(9)
51#define IRQ_UART4 S5P_IRQ_VIC1(10) /* S5P6450 */
52#define IRQ_UART5 S5P_IRQ_VIC1(11) /* S5P6450 */
47#define IRQ_NFC S5P_IRQ_VIC1(13) 53#define IRQ_NFC S5P_IRQ_VIC1(13)
54#define IRQ_USI S5P_IRQ_VIC1(15) /* S5P6450 */
48#define IRQ_SPI0 S5P_IRQ_VIC1(16) 55#define IRQ_SPI0 S5P_IRQ_VIC1(16)
49#define IRQ_SPI1 S5P_IRQ_VIC1(17) 56#define IRQ_SPI1 S5P_IRQ_VIC1(17)
57#define IRQ_HSMMC2 S5P_IRQ_VIC1(17) /* Shared */
50#define IRQ_IIC S5P_IRQ_VIC1(18) 58#define IRQ_IIC S5P_IRQ_VIC1(18)
51#define IRQ_DISPCON3 S5P_IRQ_VIC1(19) 59#define IRQ_DISPCON3 S5P_IRQ_VIC1(19)
52#define IRQ_FIMGVG S5P_IRQ_VIC1(20)
53#define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21) 60#define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21)
54#define IRQ_PMU S5P_IRQ_VIC1(23) 61#define IRQ_PMU S5P_IRQ_VIC1(23) /* S5P6440 */
55#define IRQ_HSMMC0 S5P_IRQ_VIC1(24) 62#define IRQ_HSMMC0 S5P_IRQ_VIC1(24)
56#define IRQ_HSMMC1 S5P_IRQ_VIC1(25) 63#define IRQ_HSMMC1 S5P_IRQ_VIC1(25)
57#define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */
58#define IRQ_OTG S5P_IRQ_VIC1(26) 64#define IRQ_OTG S5P_IRQ_VIC1(26)
59#define IRQ_DSI S5P_IRQ_VIC1(27) 65#define IRQ_DSI S5P_IRQ_VIC1(27)
60#define IRQ_RTC_ALARM S5P_IRQ_VIC1(28) 66#define IRQ_RTC_ALARM S5P_IRQ_VIC1(28)
@@ -63,6 +69,24 @@
63#define IRQ_TC IRQ_PENDN 69#define IRQ_TC IRQ_PENDN
64#define IRQ_ADC S5P_IRQ_VIC1(31) 70#define IRQ_ADC S5P_IRQ_VIC1(31)
65 71
72/* UART interrupts, S5P6450 has 5 UARTs */
73#define IRQ_S5P_UART_BASE4 (96)
74#define IRQ_S5P_UART_BASE5 (100)
75
76#define IRQ_S5P_UART_RX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_RXD)
77#define IRQ_S5P_UART_TX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_TXD)
78#define IRQ_S5P_UART_ERR4 (IRQ_S5P_UART_BASE4 + UART_IRQ_ERR)
79
80#define IRQ_S5P_UART_RX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_RXD)
81#define IRQ_S5P_UART_TX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_TXD)
82#define IRQ_S5P_UART_ERR5 (IRQ_S5P_UART_BASE5 + UART_IRQ_ERR)
83
84/* S3C compatibilty defines */
85#define IRQ_S3CUART_RX4 IRQ_S5P_UART_RX4
86#define IRQ_S3CUART_RX5 IRQ_S5P_UART_RX5
87
88/* S5P6450 EINT feature will be added */
89
66/* 90/*
67 * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined 91 * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined
68 * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place 92 * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place
@@ -115,4 +139,4 @@
115 139
116#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1) 140#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
117 141
118#endif /* __ASM_ARCH_S5P_IRQS_H */ 142#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
new file mode 100644
index 000000000000..31e534156e06
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -0,0 +1,83 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/map.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17#include <plat/map-s5p.h>
18
19#define S5P64X0_PA_SDRAM (0x20000000)
20
21#define S5P64X0_PA_CHIPID (0xE0000000)
22#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
23
24#define S5P64X0_PA_SYSCON (0xE0100000)
25#define S5P_PA_SYSCON S5P64X0_PA_SYSCON
26
27#define S5P64X0_PA_GPIO (0xE0308000)
28
29#define S5P64X0_PA_VIC0 (0xE4000000)
30#define S5P64X0_PA_VIC1 (0xE4100000)
31
32#define S5P64X0_PA_PDMA (0xE9000000)
33
34#define S5P64X0_PA_TIMER (0xEA000000)
35#define S5P_PA_TIMER S5P64X0_PA_TIMER
36
37#define S5P64X0_PA_RTC (0xEA100000)
38
39#define S5P64X0_PA_WDT (0xEA200000)
40
41#define S5P6440_PA_UART(x) (0xEC000000 + ((x) * S3C_UART_OFFSET))
42#define S5P6450_PA_UART(x) ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
43
44#define S5P_PA_UART0 S5P6450_PA_UART(0)
45#define S5P_PA_UART1 S5P6450_PA_UART(1)
46#define S5P_PA_UART2 S5P6450_PA_UART(2)
47#define S5P_PA_UART3 S5P6450_PA_UART(3)
48#define S5P_PA_UART4 S5P6450_PA_UART(4)
49#define S5P_PA_UART5 S5P6450_PA_UART(5)
50
51#define S5P_SZ_UART SZ_256
52
53#define S5P6440_PA_IIC0 (0xEC104000)
54#define S5P6440_PA_IIC1 (0xEC20F000)
55#define S5P6450_PA_IIC0 (0xEC100000)
56#define S5P6450_PA_IIC1 (0xEC200000)
57
58#define S5P64X0_PA_SPI0 (0xEC400000)
59#define S5P64X0_PA_SPI1 (0xEC500000)
60
61#define S5P64X0_PA_HSOTG (0xED100000)
62
63#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
64
65#define S5P64X0_PA_I2S (0xF2000000)
66
67#define S5P64X0_PA_PCM (0xF2100000)
68
69#define S5P64X0_PA_ADC (0xF3000000)
70
71/* compatibiltiy defines. */
72
73#define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0)
74#define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1)
75#define S3C_PA_HSMMC2 S5P64X0_PA_HSMMC(2)
76#define S3C_PA_IIC S5P6440_PA_IIC0
77#define S3C_PA_IIC1 S5P6440_PA_IIC1
78#define S3C_PA_RTC S5P64X0_PA_RTC
79#define S3C_PA_WDT S5P64X0_PA_WDT
80
81#define SAMSUNG_PA_ADC S5P64X0_PA_ADC
82
83#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/memory.h b/arch/arm/mach-s5p64x0/include/mach/memory.h
index d62910c71b56..1b036b0a24ce 100644
--- a/arch/arm/mach-s5p6440/include/mach/memory.h
+++ b/arch/arm/mach-s5p64x0/include/mach/memory.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/memory.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/memory.h
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P6440 - Memory definitions 6 * S5P64X0 - Memory definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -11,9 +11,9 @@
11*/ 11*/
12 12
13#ifndef __ASM_ARCH_MEMORY_H 13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H 14#define __ASM_ARCH_MEMORY_H __FILE__
15 15
16#define PHYS_OFFSET UL(0x20000000) 16#define PHYS_OFFSET UL(0x20000000)
17#define CONSISTENT_DMA_SIZE SZ_8M 17#define CONSISTENT_DMA_SIZE SZ_8M
18 18
19#endif /* __ASM_ARCH_MEMORY_H */ 19#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h b/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
index 6a2a02fdf12a..19fff8b701c0 100644
--- a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
+++ b/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
@@ -1,16 +1,14 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/pwm-clock.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/pwm-clock.h
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Copyright 2008 Openmoko, Inc. 6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics 7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk> 8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/ 9 * http://armlinux.simtec.co.uk/
10 * 10 *
11 * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h 11 * S5P64X0 - pwm clock and timer support
12 *
13 * S5P6440 - pwm clock and timer support
14 * 12 *
15 * This program is free software; you can redistribute it and/or modify 13 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as 14 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
new file mode 100644
index 000000000000..58e1bc813804
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
@@ -0,0 +1,63 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
19
20#define S5P64X0_APLL_CON S5P_CLKREG(0x0C)
21#define S5P64X0_MPLL_CON S5P_CLKREG(0x10)
22#define S5P64X0_EPLL_CON S5P_CLKREG(0x14)
23#define S5P64X0_EPLL_CON_K S5P_CLKREG(0x18)
24
25#define S5P64X0_CLK_SRC0 S5P_CLKREG(0x1C)
26
27#define S5P64X0_CLK_DIV0 S5P_CLKREG(0x20)
28#define S5P64X0_CLK_DIV1 S5P_CLKREG(0x24)
29#define S5P64X0_CLK_DIV2 S5P_CLKREG(0x28)
30
31#define S5P64X0_CLK_GATE_HCLK0 S5P_CLKREG(0x30)
32#define S5P64X0_CLK_GATE_PCLK S5P_CLKREG(0x34)
33#define S5P64X0_CLK_GATE_SCLK0 S5P_CLKREG(0x38)
34#define S5P64X0_CLK_GATE_MEM0 S5P_CLKREG(0x3C)
35
36#define S5P64X0_CLK_DIV3 S5P_CLKREG(0x40)
37
38#define S5P64X0_CLK_GATE_HCLK1 S5P_CLKREG(0x44)
39#define S5P64X0_CLK_GATE_SCLK1 S5P_CLKREG(0x48)
40
41#define S5P6450_DPLL_CON S5P_CLKREG(0x50)
42#define S5P6450_DPLL_CON_K S5P_CLKREG(0x54)
43
44#define S5P64X0_CLK_SRC1 S5P_CLKREG(0x10C)
45
46#define S5P64X0_SYS_ID S5P_CLKREG(0x118)
47#define S5P64X0_SYS_OTHERS S5P_CLKREG(0x11C)
48
49#define S5P64X0_PWR_CFG S5P_CLKREG(0x804)
50#define S5P64X0_OTHERS S5P_CLKREG(0x900)
51
52#define S5P64X0_CLKDIV0_HCLK_SHIFT (8)
53#define S5P64X0_CLKDIV0_HCLK_MASK (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
54
55#define S5P64X0_OTHERS_USB_SIG_MASK (1 << 16)
56
57/* Compatibility defines */
58
59#define ARM_CLK_DIV S5P64X0_CLK_DIV0
60#define ARM_DIV_RATIO_SHIFT 0
61#define ARM_DIV_MASK (0xF << ARM_DIV_RATIO_SHIFT)
62
63#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
index 82ff753913da..85f448e20a8b 100644
--- a/arch/arm/mach-s5p6440/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
@@ -1,21 +1,24 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/regs-gpio.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P6440 - GPIO register definitions 6 * S5P64X0 - GPIO register definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11*/
12 12
13#ifndef __ASM_ARCH_REGS_GPIO_H 13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__ 14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15 15
16#include <mach/map.h> 16#include <mach/map.h>
17 17
18/* Will be implemented S5P6442 GPIOlib */
19
18/* Base addresses for each of the banks */ 20/* Base addresses for each of the banks */
21
19#define S5P6440_GPA_BASE (S5P_VA_GPIO + 0x0000) 22#define S5P6440_GPA_BASE (S5P_VA_GPIO + 0x0000)
20#define S5P6440_GPB_BASE (S5P_VA_GPIO + 0x0020) 23#define S5P6440_GPB_BASE (S5P_VA_GPIO + 0x0020)
21#define S5P6440_GPC_BASE (S5P_VA_GPIO + 0x0040) 24#define S5P6440_GPC_BASE (S5P_VA_GPIO + 0x0040)
@@ -27,6 +30,7 @@
27#define S5P6440_GPN_BASE (S5P_VA_GPIO + 0x0830) 30#define S5P6440_GPN_BASE (S5P_VA_GPIO + 0x0830)
28#define S5P6440_GPP_BASE (S5P_VA_GPIO + 0x0160) 31#define S5P6440_GPP_BASE (S5P_VA_GPIO + 0x0160)
29#define S5P6440_GPR_BASE (S5P_VA_GPIO + 0x0290) 32#define S5P6440_GPR_BASE (S5P_VA_GPIO + 0x0290)
33
30#define S5P6440_EINT0CON0 (S5P_VA_GPIO + 0x900) 34#define S5P6440_EINT0CON0 (S5P_VA_GPIO + 0x900)
31#define S5P6440_EINT0FLTCON0 (S5P_VA_GPIO + 0x910) 35#define S5P6440_EINT0FLTCON0 (S5P_VA_GPIO + 0x910)
32#define S5P6440_EINT0FLTCON1 (S5P_VA_GPIO + 0x914) 36#define S5P6440_EINT0FLTCON1 (S5P_VA_GPIO + 0x914)
@@ -34,19 +38,23 @@
34#define S5P6440_EINT0PEND (S5P_VA_GPIO + 0x924) 38#define S5P6440_EINT0PEND (S5P_VA_GPIO + 0x924)
35 39
36/* for LCD */ 40/* for LCD */
41
37#define S5P6440_SPCON_LCD_SEL_RGB (1 << 0) 42#define S5P6440_SPCON_LCD_SEL_RGB (1 << 0)
38#define S5P6440_SPCON_LCD_SEL_MASK (3 << 0) 43#define S5P6440_SPCON_LCD_SEL_MASK (3 << 0)
39 44
40/* These set of macros are not really useful for the 45/*
41 * GPF/GPI/GPJ/GPN/GPP, 46 * These set of macros are not really useful for the
42 * useful for others set of GPIO's (4 bit) 47 * GPF/GPI/GPJ/GPN/GPP, useful for others set of GPIO's (4 bit)
43 */ 48 */
49
44#define S5P6440_GPIO_CONMASK(__gpio) (0xf << ((__gpio) * 4)) 50#define S5P6440_GPIO_CONMASK(__gpio) (0xf << ((__gpio) * 4))
45#define S5P6440_GPIO_INPUT(__gpio) (0x0 << ((__gpio) * 4)) 51#define S5P6440_GPIO_INPUT(__gpio) (0x0 << ((__gpio) * 4))
46#define S5P6440_GPIO_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) 52#define S5P6440_GPIO_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
47 53
48/* Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit) 54/*
49 * */ 55 * Use these macros for GPF/GPI/GPJ/GPN/GPP set of GPIO (2 bit)
56 */
57
50#define S5P6440_GPIO2_CONMASK(__gpio) (0x3 << ((__gpio) * 2)) 58#define S5P6440_GPIO2_CONMASK(__gpio) (0x3 << ((__gpio) * 2))
51#define S5P6440_GPIO2_INPUT(__gpio) (0x0 << ((__gpio) * 2)) 59#define S5P6440_GPIO2_INPUT(__gpio) (0x0 << ((__gpio) * 2))
52#define S5P6440_GPIO2_OUTPUT(__gpio) (0x1 << ((__gpio) * 2)) 60#define S5P6440_GPIO2_OUTPUT(__gpio) (0x1 << ((__gpio) * 2))
diff --git a/arch/arm/mach-s5p6440/include/mach/regs-irq.h b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
index a961f4beeb0c..4aaebdace55f 100644
--- a/arch/arm/mach-s5p6440/include/mach/regs-irq.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/regs-irq.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P6440 - IRQ register definitions 6 * S5P64X0 - IRQ register definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
new file mode 100644
index 000000000000..ff85b4b6e8d9
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
@@ -0,0 +1,46 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/s5p64x0-clock.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Header file for s5p64x0 clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_CLOCK_H
14#define __ASM_ARCH_CLOCK_H __FILE__
15
16#include <linux/clk.h>
17
18extern struct clksrc_clk clk_mout_apll;
19extern struct clksrc_clk clk_mout_mpll;
20extern struct clksrc_clk clk_mout_epll;
21
22extern int s5p64x0_epll_enable(struct clk *clk, int enable);
23extern unsigned long s5p64x0_epll_get_rate(struct clk *clk);
24
25extern unsigned long s5p64x0_armclk_get_rate(struct clk *clk);
26extern unsigned long s5p64x0_armclk_round_rate(struct clk *clk, unsigned long rate);
27extern int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate);
28
29extern struct clk_ops s5p64x0_clkarm_ops;
30
31extern struct clksrc_clk clk_armclk;
32extern struct clksrc_clk clk_dout_mpll;
33
34extern struct clk *clkset_hclk_low_list[];
35extern struct clksrc_sources clkset_hclk_low;
36
37extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable);
38extern int s5p64x0_hclk0_ctrl(struct clk *clk, int enable);
39extern int s5p64x0_hclk1_ctrl(struct clk *clk, int enable);
40extern int s5p64x0_sclk_ctrl(struct clk *clk, int enable);
41extern int s5p64x0_sclk1_ctrl(struct clk *clk, int enable);
42extern int s5p64x0_mem_ctrl(struct clk *clk, int enable);
43
44extern int s5p64x0_clk48m_ctrl(struct clk *clk, int enable);
45
46#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h b/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
new file mode 100644
index 000000000000..170a20a9643a
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
@@ -0,0 +1,20 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#ifndef __ASM_ARCH_SPI_CLKS_H
15#define __ASM_ARCH_SPI_CLKS_H __FILE__
16
17#define S5P64X0_SPI_SRCCLK_PCLK 0
18#define S5P64X0_SPI_SRCCLK_SCLK 1
19
20#endif /* __ASM_ARCH_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/system.h b/arch/arm/mach-s5p64x0/include/mach/system.h
index a359ee3fa510..60f57532c970 100644
--- a/arch/arm/mach-s5p6440/include/mach/system.h
+++ b/arch/arm/mach-s5p64x0/include/mach/system.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/system.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/system.h
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P6440 - system support header 6 * S5P64X0 - system support header
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p6440/include/mach/tick.h b/arch/arm/mach-s5p64x0/include/mach/tick.h
index 2f25c7f07970..00aa7f1d8e51 100644
--- a/arch/arm/mach-s5p6440/include/mach/tick.h
+++ b/arch/arm/mach-s5p64x0/include/mach/tick.h
@@ -1,9 +1,14 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/tick.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/tick.h
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P6440 - Timer tick support definitions 6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * http://armlinux.simtec.co.uk/
9 * Ben Dooks <ben@simtec.co.uk>
10 *
11 * S5P64X0 - Timer tick support definitions
7 * 12 *
8 * This program is free software; you can redistribute it and/or modify 13 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 14 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p6440/include/mach/timex.h b/arch/arm/mach-s5p64x0/include/mach/timex.h
index fb2e8cd40829..4b91faa195a8 100644
--- a/arch/arm/mach-s5p6440/include/mach/timex.h
+++ b/arch/arm/mach-s5p64x0/include/mach/timex.h
@@ -1,9 +1,12 @@
1/* arch/arm/mach-s3c64xx/include/mach/timex.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/timex.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
2 * 5 *
3 * Copyright (c) 2003-2005 Simtec Electronics 6 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 7 * Ben Dooks <ben@simtec.co.uk>
5 * 8 *
6 * S3C6400 - time parameters 9 * S5P64X0 - time parameters
7 * 10 *
8 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 12 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
new file mode 100644
index 000000000000..c65b229aab23
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
@@ -0,0 +1,212 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/uncompress.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - uncompress code
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_UNCOMPRESS_H
14#define __ASM_ARCH_UNCOMPRESS_H
15
16#include <mach/map.h>
17
18/*
19 * cannot use commonly <plat/uncompress.h>
20 * because uart base of S5P6440 and S5P6450 is different
21 */
22
23typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
24
25/* uart setup */
26
27static unsigned int fifo_mask;
28static unsigned int fifo_max;
29
30/* forward declerations */
31
32static void arch_detect_cpu(void);
33
34/* defines for UART registers */
35
36#include <plat/regs-serial.h>
37#include <plat/regs-watchdog.h>
38
39/* working in physical space... */
40#undef S3C2410_WDOGREG
41#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
42
43/* how many bytes we allow into the FIFO at a time in FIFO mode */
44#define FIFO_MAX (14)
45
46static unsigned long uart_base;
47
48static __inline__ void get_uart_base(void)
49{
50 unsigned int chipid;
51
52 chipid = *(const volatile unsigned int __force *) 0xE0100118;
53
54 uart_base = S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT;
55
56 if ((chipid & 0xff000) == 0x50000)
57 uart_base += 0xEC800000;
58 else
59 uart_base += 0xEC000000;
60}
61
62static __inline__ void uart_wr(unsigned int reg, unsigned int val)
63{
64 volatile unsigned int *ptr;
65
66 get_uart_base();
67 ptr = (volatile unsigned int *)(reg + uart_base);
68 *ptr = val;
69}
70
71static __inline__ unsigned int uart_rd(unsigned int reg)
72{
73 volatile unsigned int *ptr;
74
75 get_uart_base();
76 ptr = (volatile unsigned int *)(reg + uart_base);
77 return *ptr;
78}
79
80/*
81 * we can deal with the case the UARTs are being run
82 * in FIFO mode, so that we don't hold up our execution
83 * waiting for tx to happen...
84 */
85
86static void putc(int ch)
87{
88 if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
89 int level;
90
91 while (1) {
92 level = uart_rd(S3C2410_UFSTAT);
93 level &= fifo_mask;
94
95 if (level < fifo_max)
96 break;
97 }
98
99 } else {
100 /* not using fifos */
101
102 while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
103 barrier();
104 }
105
106 /* write byte to transmission register */
107 uart_wr(S3C2410_UTXH, ch);
108}
109
110static inline void flush(void)
111{
112}
113
114#define __raw_writel(d, ad) \
115 do { \
116 *((volatile unsigned int __force *)(ad)) = (d); \
117 } while (0)
118
119/*
120 * CONFIG_S3C_BOOT_WATCHDOG
121 *
122 * Simple boot-time watchdog setup, to reboot the system if there is
123 * any problem with the boot process
124 */
125
126#ifdef CONFIG_S3C_BOOT_WATCHDOG
127
128#define WDOG_COUNT (0xff00)
129
130static inline void arch_decomp_wdog(void)
131{
132 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
133}
134
135static void arch_decomp_wdog_start(void)
136{
137 __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
138 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
139 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
140}
141
142#else
143#define arch_decomp_wdog_start()
144#define arch_decomp_wdog()
145#endif
146
147#ifdef CONFIG_S3C_BOOT_ERROR_RESET
148
149static void arch_decomp_error(const char *x)
150{
151 putstr("\n\n");
152 putstr(x);
153 putstr("\n\n -- System resetting\n");
154
155 __raw_writel(0x4000, S3C2410_WTDAT);
156 __raw_writel(0x4000, S3C2410_WTCNT);
157 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
158
159 while(1);
160}
161
162#define arch_error arch_decomp_error
163#endif
164
165#ifdef CONFIG_S3C_BOOT_UART_FORCE_FIFO
166static inline void arch_enable_uart_fifo(void)
167{
168 u32 fifocon = uart_rd(S3C2410_UFCON);
169
170 if (!(fifocon & S3C2410_UFCON_FIFOMODE)) {
171 fifocon |= S3C2410_UFCON_RESETBOTH;
172 uart_wr(S3C2410_UFCON, fifocon);
173
174 /* wait for fifo reset to complete */
175 while (1) {
176 fifocon = uart_rd(S3C2410_UFCON);
177 if (!(fifocon & S3C2410_UFCON_RESETBOTH))
178 break;
179 }
180 }
181}
182#else
183#define arch_enable_uart_fifo() do { } while(0)
184#endif
185
186static void arch_decomp_setup(void)
187{
188 /*
189 * we may need to setup the uart(s) here if we are not running
190 * on an BAST... the BAST will have left the uarts configured
191 * after calling linux.
192 */
193
194 arch_detect_cpu();
195 arch_decomp_wdog_start();
196
197 /*
198 * Enable the UART FIFOs if they where not enabled and our
199 * configuration says we should turn them on.
200 */
201
202 arch_enable_uart_fifo();
203}
204
205
206
207static void arch_detect_cpu(void)
208{
209 /* we do not need to do any cpu detection here at the moment. */
210}
211
212#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/vmalloc.h b/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
index e3f0eebf5205..97a9df38f1cf 100644
--- a/arch/arm/mach-s5p6440/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
@@ -1,4 +1,7 @@
1/* arch/arm/mach-s5p6440/include/mach/vmalloc.h 1/* linux/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
2 * 5 *
3 * Copyright 2010 Ben Dooks <ben-linux@fluff.org> 6 * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
4 * 7 *
diff --git a/arch/arm/mach-s5p64x0/init.c b/arch/arm/mach-s5p64x0/init.c
new file mode 100644
index 000000000000..79833caf8165
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/init.c
@@ -0,0 +1,73 @@
1/* linux/arch/arm/mach-s5p64x0/init.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Init support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/init.h>
16#include <linux/serial_core.h>
17
18#include <mach/map.h>
19
20#include <plat/cpu.h>
21#include <plat/devs.h>
22#include <plat/s5p6440.h>
23#include <plat/s5p6450.h>
24#include <plat/regs-serial.h>
25
26static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
27 [0] = {
28 .name = "pclk_low",
29 .divisor = 1,
30 .min_baud = 0,
31 .max_baud = 0,
32 },
33 [1] = {
34 .name = "uclk1",
35 .divisor = 1,
36 .min_baud = 0,
37 .max_baud = 0,
38 },
39};
40
41/* uart registration process */
42
43void __init s5p64x0_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
44{
45 struct s3c2410_uartcfg *tcfg = cfg;
46 u32 ucnt;
47
48 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
49 if (!tcfg->clocks) {
50 tcfg->clocks = s5p64x0_serial_clocks;
51 tcfg->clocks_size = ARRAY_SIZE(s5p64x0_serial_clocks);
52 }
53 }
54}
55
56void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
57{
58 int uart;
59
60 for (uart = 0; uart < no; uart++) {
61 s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
62 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
63 }
64
65 s5p64x0_common_init_uarts(cfg, no);
66 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
67}
68
69void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
70{
71 s5p64x0_common_init_uarts(cfg, no);
72 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
73}
diff --git a/arch/arm/mach-s5p6440/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 9202aaac3b56..87c3f03c618c 100644
--- a/arch/arm/mach-s5p6440/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5p6440/mach-smdk6440.c 1/* linux/arch/arm/mach-s5p64x0/mach-smdk6440.c
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -21,21 +21,22 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/module.h> 22#include <linux/module.h>
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/gpio.h>
24 25
25#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
26#include <asm/mach/map.h> 27#include <asm/mach/map.h>
28#include <asm/irq.h>
29#include <asm/mach-types.h>
27 30
28#include <mach/hardware.h> 31#include <mach/hardware.h>
29#include <mach/map.h> 32#include <mach/map.h>
30 33#include <mach/regs-clock.h>
31#include <asm/irq.h> 34#include <mach/i2c.h>
32#include <asm/mach-types.h>
33 35
34#include <plat/regs-serial.h> 36#include <plat/regs-serial.h>
35 37#include <plat/gpio-cfg.h>
36#include <plat/s5p6440.h> 38#include <plat/s5p6440.h>
37#include <plat/clock.h> 39#include <plat/clock.h>
38#include <mach/regs-clock.h>
39#include <plat/devs.h> 40#include <plat/devs.h>
40#include <plat/cpu.h> 41#include <plat/cpu.h>
41#include <plat/iic.h> 42#include <plat/iic.h>
@@ -58,43 +59,60 @@
58 59
59static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = { 60static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
60 [0] = { 61 [0] = {
61 .hwport = 0, 62 .hwport = 0,
62 .flags = 0, 63 .flags = 0,
63 .ucon = SMDK6440_UCON_DEFAULT, 64 .ucon = SMDK6440_UCON_DEFAULT,
64 .ulcon = SMDK6440_ULCON_DEFAULT, 65 .ulcon = SMDK6440_ULCON_DEFAULT,
65 .ufcon = SMDK6440_UFCON_DEFAULT, 66 .ufcon = SMDK6440_UFCON_DEFAULT,
66 }, 67 },
67 [1] = { 68 [1] = {
68 .hwport = 1, 69 .hwport = 1,
69 .flags = 0, 70 .flags = 0,
70 .ucon = SMDK6440_UCON_DEFAULT, 71 .ucon = SMDK6440_UCON_DEFAULT,
71 .ulcon = SMDK6440_ULCON_DEFAULT, 72 .ulcon = SMDK6440_ULCON_DEFAULT,
72 .ufcon = SMDK6440_UFCON_DEFAULT, 73 .ufcon = SMDK6440_UFCON_DEFAULT,
73 }, 74 },
74 [2] = { 75 [2] = {
75 .hwport = 2, 76 .hwport = 2,
76 .flags = 0, 77 .flags = 0,
77 .ucon = SMDK6440_UCON_DEFAULT, 78 .ucon = SMDK6440_UCON_DEFAULT,
78 .ulcon = SMDK6440_ULCON_DEFAULT, 79 .ulcon = SMDK6440_ULCON_DEFAULT,
79 .ufcon = SMDK6440_UFCON_DEFAULT, 80 .ufcon = SMDK6440_UFCON_DEFAULT,
80 }, 81 },
81 [3] = { 82 [3] = {
82 .hwport = 3, 83 .hwport = 3,
83 .flags = 0, 84 .flags = 0,
84 .ucon = SMDK6440_UCON_DEFAULT, 85 .ucon = SMDK6440_UCON_DEFAULT,
85 .ulcon = SMDK6440_ULCON_DEFAULT, 86 .ulcon = SMDK6440_ULCON_DEFAULT,
86 .ufcon = SMDK6440_UFCON_DEFAULT, 87 .ufcon = SMDK6440_UFCON_DEFAULT,
87 }, 88 },
88}; 89};
89 90
90static struct platform_device *smdk6440_devices[] __initdata = { 91static struct platform_device *smdk6440_devices[] __initdata = {
91 &s5p6440_device_iis,
92 &s3c_device_adc, 92 &s3c_device_adc,
93 &s3c_device_rtc, 93 &s3c_device_rtc,
94 &s3c_device_i2c0, 94 &s3c_device_i2c0,
95 &s3c_device_i2c1, 95 &s3c_device_i2c1,
96 &s3c_device_ts, 96 &s3c_device_ts,
97 &s3c_device_wdt, 97 &s3c_device_wdt,
98 &s5p6440_device_iis,
99};
100
101static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
102 .flags = 0,
103 .slave_addr = 0x10,
104 .frequency = 100*1000,
105 .sda_delay = 100,
106 .cfg_gpio = s5p6440_i2c0_cfg_gpio,
107};
108
109static struct s3c2410_platform_i2c s5p6440_i2c1_data __initdata = {
110 .flags = 0,
111 .bus_num = 1,
112 .slave_addr = 0x10,
113 .frequency = 100*1000,
114 .sda_delay = 100,
115 .cfg_gpio = s5p6440_i2c1_cfg_gpio,
98}; 116};
99 117
100static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = { 118static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = {
@@ -113,7 +131,7 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
113 131
114static void __init smdk6440_map_io(void) 132static void __init smdk6440_map_io(void)
115{ 133{
116 s5p_init_io(NULL, 0, S5P_SYS_ID); 134 s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
117 s3c24xx_init_clocks(12000000); 135 s3c24xx_init_clocks(12000000);
118 s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs)); 136 s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs));
119} 137}
@@ -122,9 +140,8 @@ static void __init smdk6440_machine_init(void)
122{ 140{
123 s3c24xx_ts_set_platdata(&s3c_ts_platform); 141 s3c24xx_ts_set_platdata(&s3c_ts_platform);
124 142
125 /* I2C */ 143 s3c_i2c0_set_platdata(&s5p6440_i2c0_data);
126 s3c_i2c0_set_platdata(NULL); 144 s3c_i2c1_set_platdata(&s5p6440_i2c1_data);
127 s3c_i2c1_set_platdata(NULL);
128 i2c_register_board_info(0, smdk6440_i2c_devs0, 145 i2c_register_board_info(0, smdk6440_i2c_devs0,
129 ARRAY_SIZE(smdk6440_i2c_devs0)); 146 ARRAY_SIZE(smdk6440_i2c_devs0));
130 i2c_register_board_info(1, smdk6440_i2c_devs1, 147 i2c_register_board_info(1, smdk6440_i2c_devs1,
@@ -135,9 +152,7 @@ static void __init smdk6440_machine_init(void)
135 152
136MACHINE_START(SMDK6440, "SMDK6440") 153MACHINE_START(SMDK6440, "SMDK6440")
137 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 154 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
138 .phys_io = S3C_PA_UART & 0xfff00000, 155 .boot_params = S5P64X0_PA_SDRAM + 0x100,
139 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
140 .boot_params = S5P_PA_SDRAM + 0x100,
141 156
142 .init_irq = s5p6440_init_irq, 157 .init_irq = s5p6440_init_irq,
143 .map_io = smdk6440_map_io, 158 .map_io = smdk6440_map_io,
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
new file mode 100644
index 000000000000..d609f5af2b98
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -0,0 +1,180 @@
1/* linux/arch/arm/mach-s5p64x0/mach-smdk6450.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/interrupt.h>
14#include <linux/list.h>
15#include <linux/timer.h>
16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/i2c.h>
19#include <linux/serial_core.h>
20#include <linux/platform_device.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/clk.h>
24#include <linux/gpio.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/irq.h>
29#include <asm/mach-types.h>
30
31#include <mach/hardware.h>
32#include <mach/map.h>
33#include <mach/regs-clock.h>
34#include <mach/i2c.h>
35
36#include <plat/regs-serial.h>
37#include <plat/gpio-cfg.h>
38#include <plat/s5p6450.h>
39#include <plat/clock.h>
40#include <plat/devs.h>
41#include <plat/cpu.h>
42#include <plat/iic.h>
43#include <plat/pll.h>
44#include <plat/adc.h>
45#include <plat/ts.h>
46
47#define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
48 S3C2410_UCON_RXILEVEL | \
49 S3C2410_UCON_TXIRQMODE | \
50 S3C2410_UCON_RXIRQMODE | \
51 S3C2410_UCON_RXFIFO_TOI | \
52 S3C2443_UCON_RXERR_IRQEN)
53
54#define SMDK6450_ULCON_DEFAULT S3C2410_LCON_CS8
55
56#define SMDK6450_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
57 S3C2440_UFCON_TXTRIG16 | \
58 S3C2410_UFCON_RXTRIG8)
59
60static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
61 [0] = {
62 .hwport = 0,
63 .flags = 0,
64 .ucon = SMDK6450_UCON_DEFAULT,
65 .ulcon = SMDK6450_ULCON_DEFAULT,
66 .ufcon = SMDK6450_UFCON_DEFAULT,
67 },
68 [1] = {
69 .hwport = 1,
70 .flags = 0,
71 .ucon = SMDK6450_UCON_DEFAULT,
72 .ulcon = SMDK6450_ULCON_DEFAULT,
73 .ufcon = SMDK6450_UFCON_DEFAULT,
74 },
75 [2] = {
76 .hwport = 2,
77 .flags = 0,
78 .ucon = SMDK6450_UCON_DEFAULT,
79 .ulcon = SMDK6450_ULCON_DEFAULT,
80 .ufcon = SMDK6450_UFCON_DEFAULT,
81 },
82 [3] = {
83 .hwport = 3,
84 .flags = 0,
85 .ucon = SMDK6450_UCON_DEFAULT,
86 .ulcon = SMDK6450_ULCON_DEFAULT,
87 .ufcon = SMDK6450_UFCON_DEFAULT,
88 },
89#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
90 [4] = {
91 .hwport = 4,
92 .flags = 0,
93 .ucon = SMDK6450_UCON_DEFAULT,
94 .ulcon = SMDK6450_ULCON_DEFAULT,
95 .ufcon = SMDK6450_UFCON_DEFAULT,
96 },
97#endif
98#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
99 [5] = {
100 .hwport = 5,
101 .flags = 0,
102 .ucon = SMDK6450_UCON_DEFAULT,
103 .ulcon = SMDK6450_ULCON_DEFAULT,
104 .ufcon = SMDK6450_UFCON_DEFAULT,
105 },
106#endif
107};
108
109static struct platform_device *smdk6450_devices[] __initdata = {
110 &s3c_device_adc,
111 &s3c_device_rtc,
112 &s3c_device_i2c0,
113 &s3c_device_i2c1,
114 &s3c_device_ts,
115 &s3c_device_wdt,
116 &s5p6450_device_iis0,
117 /* s5p6450_device_spi0 will be added */
118};
119
120static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = {
121 .flags = 0,
122 .slave_addr = 0x10,
123 .frequency = 100*1000,
124 .sda_delay = 100,
125 .cfg_gpio = s5p6450_i2c0_cfg_gpio,
126};
127
128static struct s3c2410_platform_i2c s5p6450_i2c1_data __initdata = {
129 .flags = 0,
130 .bus_num = 1,
131 .slave_addr = 0x10,
132 .frequency = 100*1000,
133 .sda_delay = 100,
134 .cfg_gpio = s5p6450_i2c1_cfg_gpio,
135};
136
137static struct i2c_board_info smdk6450_i2c_devs0[] __initdata = {
138 { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung KS24C080C EEPROM */
139};
140
141static struct i2c_board_info smdk6450_i2c_devs1[] __initdata = {
142 { I2C_BOARD_INFO("24c128", 0x57), },/* Samsung S524AD0XD1 EEPROM */
143};
144
145static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
146 .delay = 10000,
147 .presc = 49,
148 .oversampling_shift = 2,
149};
150
151static void __init smdk6450_map_io(void)
152{
153 s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
154 s3c24xx_init_clocks(19200000);
155 s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs));
156}
157
158static void __init smdk6450_machine_init(void)
159{
160 s3c24xx_ts_set_platdata(&s3c_ts_platform);
161
162 s3c_i2c0_set_platdata(&s5p6450_i2c0_data);
163 s3c_i2c1_set_platdata(&s5p6450_i2c1_data);
164 i2c_register_board_info(0, smdk6450_i2c_devs0,
165 ARRAY_SIZE(smdk6450_i2c_devs0));
166 i2c_register_board_info(1, smdk6450_i2c_devs1,
167 ARRAY_SIZE(smdk6450_i2c_devs1));
168
169 platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
170}
171
172MACHINE_START(SMDK6450, "SMDK6450")
173 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
174 .boot_params = S5P64X0_PA_SDRAM + 0x100,
175
176 .init_irq = s5p6450_init_irq,
177 .map_io = smdk6450_map_io,
178 .init_machine = smdk6450_machine_init,
179 .timer = &s3c24xx_timer,
180MACHINE_END
diff --git a/arch/arm/mach-s5p6440/setup-i2c0.c b/arch/arm/mach-s5p64x0/setup-i2c0.c
index 2c99d14f7ac7..dc4cc65a5019 100644
--- a/arch/arm/mach-s5p6440/setup-i2c0.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c0.c
@@ -1,11 +1,11 @@
1/* linux/arch/arm/mach-s5p6440/setup-i2c0.c 1/* linux/arch/arm/mach-s5p64x0/setup-i2c0.c
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * I2C0 GPIO configuration. 6 * I2C0 GPIO configuration.
7 * 7 *
8 * Based on plat-s3c64xx/setup-i2c0.c 8 * Based on plat-s3c64x0/setup-i2c0.c
9 * 9 *
10 * This program is free software; you can redistribute it and/or modify 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
@@ -14,17 +14,29 @@
14 14
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/types.h> 16#include <linux/types.h>
17#include <linux/gpio.h>
17 18
18struct platform_device; /* don't need the contents */ 19struct platform_device; /* don't need the contents */
19 20
20#include <linux/gpio.h>
21#include <plat/gpio-cfg.h> 21#include <plat/gpio-cfg.h>
22#include <plat/iic.h> 22#include <plat/iic.h>
23 23
24void s3c_i2c0_cfg_gpio(struct platform_device *dev) 24#include <mach/i2c.h>
25
26void s5p6440_i2c0_cfg_gpio(struct platform_device *dev)
25{ 27{
26 s3c_gpio_cfgpin(S5P6440_GPB(5), S3C_GPIO_SFN(2)); 28 s3c_gpio_cfgpin(S5P6440_GPB(5), S3C_GPIO_SFN(2));
27 s3c_gpio_setpull(S5P6440_GPB(5), S3C_GPIO_PULL_UP); 29 s3c_gpio_setpull(S5P6440_GPB(5), S3C_GPIO_PULL_UP);
28 s3c_gpio_cfgpin(S5P6440_GPB(6), S3C_GPIO_SFN(2)); 30 s3c_gpio_cfgpin(S5P6440_GPB(6), S3C_GPIO_SFN(2));
29 s3c_gpio_setpull(S5P6440_GPB(6), S3C_GPIO_PULL_UP); 31 s3c_gpio_setpull(S5P6440_GPB(6), S3C_GPIO_PULL_UP);
30} 32}
33
34void s5p6450_i2c0_cfg_gpio(struct platform_device *dev)
35{
36 s3c_gpio_cfgpin(S5P6450_GPB(5), S3C_GPIO_SFN(2));
37 s3c_gpio_setpull(S5P6450_GPB(5), S3C_GPIO_PULL_UP);
38 s3c_gpio_cfgpin(S5P6450_GPB(6), S3C_GPIO_SFN(2));
39 s3c_gpio_setpull(S5P6450_GPB(6), S3C_GPIO_PULL_UP);
40}
41
42void s3c_i2c0_cfg_gpio(struct platform_device *dev) { }
diff --git a/arch/arm/mach-s5p6440/setup-i2c1.c b/arch/arm/mach-s5p64x0/setup-i2c1.c
index 9a1537f786e0..2edd7912f8e4 100644
--- a/arch/arm/mach-s5p6440/setup-i2c1.c
+++ b/arch/arm/mach-s5p64x0/setup-i2c1.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5p6440/setup-i2c1.c 1/* linux/arch/arm/mach-s5p64xx/setup-i2c1.c
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * I2C1 GPIO configuration. 6 * I2C1 GPIO configuration.
7 * 7 *
@@ -21,10 +21,22 @@ struct platform_device; /* don't need the contents */
21#include <plat/gpio-cfg.h> 21#include <plat/gpio-cfg.h>
22#include <plat/iic.h> 22#include <plat/iic.h>
23 23
24void s3c_i2c1_cfg_gpio(struct platform_device *dev) 24#include <mach/i2c.h>
25
26void s5p6440_i2c1_cfg_gpio(struct platform_device *dev)
25{ 27{
26 s3c_gpio_cfgpin(S5P6440_GPR(9), S3C_GPIO_SFN(6)); 28 s3c_gpio_cfgpin(S5P6440_GPR(9), S3C_GPIO_SFN(6));
27 s3c_gpio_setpull(S5P6440_GPR(9), S3C_GPIO_PULL_UP); 29 s3c_gpio_setpull(S5P6440_GPR(9), S3C_GPIO_PULL_UP);
28 s3c_gpio_cfgpin(S5P6440_GPR(10), S3C_GPIO_SFN(6)); 30 s3c_gpio_cfgpin(S5P6440_GPR(10), S3C_GPIO_SFN(6));
29 s3c_gpio_setpull(S5P6440_GPR(10), S3C_GPIO_PULL_UP); 31 s3c_gpio_setpull(S5P6440_GPR(10), S3C_GPIO_PULL_UP);
30} 32}
33
34void s5p6450_i2c1_cfg_gpio(struct platform_device *dev)
35{
36 s3c_gpio_cfgpin(S5P6450_GPR(9), S3C_GPIO_SFN(6));
37 s3c_gpio_setpull(S5P6450_GPR(9), S3C_GPIO_PULL_UP);
38 s3c_gpio_cfgpin(S5P6450_GPR(10), S3C_GPIO_SFN(6));
39 s3c_gpio_setpull(S5P6450_GPR(10), S3C_GPIO_PULL_UP);
40}
41
42void s3c_i2c1_cfg_gpio(struct platform_device *dev) { }
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index cd1afbce83e2..fd2708e7d8a9 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -1,5 +1,8 @@
1/* linux/arch/arm/mach-s5pc100/cpu.c 1/* linux/arch/arm/mach-s5pc100/cpu.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
3 * Copyright 2009 Samsung Electronics Co. 6 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com> 7 * Byungho Min <bhmin@samsung.com>
5 * 8 *
@@ -57,11 +60,31 @@ static struct map_desc s5pc100_iodesc[] __initdata = {
57 .length = SZ_16K, 60 .length = SZ_16K,
58 .type = MT_DEVICE, 61 .type = MT_DEVICE,
59 }, { 62 }, {
63 .virtual = (unsigned long)S5P_VA_GPIO,
64 .pfn = __phys_to_pfn(S5PC100_PA_GPIO),
65 .length = SZ_4K,
66 .type = MT_DEVICE,
67 }, {
68 .virtual = (unsigned long)VA_VIC0,
69 .pfn = __phys_to_pfn(S5PC100_PA_VIC0),
70 .length = SZ_16K,
71 .type = MT_DEVICE,
72 }, {
73 .virtual = (unsigned long)VA_VIC1,
74 .pfn = __phys_to_pfn(S5PC100_PA_VIC1),
75 .length = SZ_16K,
76 .type = MT_DEVICE,
77 }, {
60 .virtual = (unsigned long)VA_VIC2, 78 .virtual = (unsigned long)VA_VIC2,
61 .pfn = __phys_to_pfn(S5P_PA_VIC2), 79 .pfn = __phys_to_pfn(S5PC100_PA_VIC2),
62 .length = SZ_16K, 80 .length = SZ_16K,
63 .type = MT_DEVICE, 81 .type = MT_DEVICE,
64 }, { 82 }, {
83 .virtual = (unsigned long)S3C_VA_UART,
84 .pfn = __phys_to_pfn(S3C_PA_UART),
85 .length = SZ_512K,
86 .type = MT_DEVICE,
87 }, {
65 .virtual = (unsigned long)S5PC100_VA_OTHERS, 88 .virtual = (unsigned long)S5PC100_VA_OTHERS,
66 .pfn = __phys_to_pfn(S5PC100_PA_OTHERS), 89 .pfn = __phys_to_pfn(S5PC100_PA_OTHERS),
67 .length = SZ_4K, 90 .length = SZ_4K,
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
index 70e02e91ee3c..b2ba95ddf8e0 100644
--- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
@@ -22,13 +22,12 @@
22 * aligned and add in the offset when we load the value here. 22 * aligned and add in the offset when we load the value here.
23 */ 23 */
24 24
25 .macro addruart, rx, rtmp 25 .macro addruart, rp, rv
26 mrc p15, 0, \rx, c1, c0 26 ldr \rp, = S3C_PA_UART
27 tst \rx, #1 27 ldr \rv, = S3C_VA_UART
28 ldreq \rx, = S3C_PA_UART
29 ldrne \rx, = S3C_VA_UART
30#if CONFIG_DEBUG_S3C_UART != 0 28#if CONFIG_DEBUG_S3C_UART != 0
31 add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) 29 add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
30 add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
32#endif 31#endif
33 .endm 32 .endm
34 33
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 01b9134feff0..8751ef4a6804 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -44,19 +44,16 @@
44#define S5PC100_PA_OTHERS (0xE0200000) 44#define S5PC100_PA_OTHERS (0xE0200000)
45#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000) 45#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
46 46
47#define S5P_PA_GPIO (0xE0300000) 47#define S5PC100_PA_GPIO (0xE0300000)
48#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) 48#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000)
49 49
50/* Interrupt */ 50/* Interrupt */
51#define S5PC100_PA_VIC (0xE4000000) 51#define S5PC100_PA_VIC0 (0xE4000000)
52#define S5PC100_PA_VIC1 (0xE4100000)
53#define S5PC100_PA_VIC2 (0xE4200000)
52#define S5PC100_VA_VIC S3C_VA_IRQ 54#define S5PC100_VA_VIC S3C_VA_IRQ
53#define S5PC100_PA_VIC_OFFSET 0x100000
54#define S5PC100_VA_VIC_OFFSET 0x10000 55#define S5PC100_VA_VIC_OFFSET 0x10000
55#define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
56#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) 56#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
57#define S5P_PA_VIC0 S5PC1XX_PA_VIC(0)
58#define S5P_PA_VIC1 S5PC1XX_PA_VIC(1)
59#define S5P_PA_VIC2 S5PC1XX_PA_VIC(2)
60 57
61 58
62#define S5PC100_PA_ONENAND (0xE7100000) 59#define S5PC100_PA_ONENAND (0xE7100000)
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 020c3f98f81f..880fb075092c 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -235,8 +235,6 @@ static void __init smdkc100_machine_init(void)
235 235
236MACHINE_START(SMDKC100, "SMDKC100") 236MACHINE_START(SMDKC100, "SMDKC100")
237 /* Maintainer: Byungho Min <bhmin@samsung.com> */ 237 /* Maintainer: Byungho Min <bhmin@samsung.com> */
238 .phys_io = S3C_PA_UART & 0xfff00000,
239 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
240 .boot_params = S5P_PA_SDRAM + 0x100, 238 .boot_params = S5P_PA_SDRAM + 0x100,
241 .init_irq = s5pc100_init_irq, 239 .init_irq = s5pc100_init_irq,
242 .map_io = smdkc100_map_io, 240 .map_io = smdkc100_map_io,
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index d3a38955c741..5315fec3db86 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -53,11 +53,6 @@ config S5PV210_SETUP_SDHCI_GPIO
53 help 53 help
54 Common setup code for SDHCI gpio. 54 Common setup code for SDHCI gpio.
55 55
56config S5PC110_DEV_ONENAND
57 bool
58 help
59 Compile in platform device definition for OneNAND1 controller
60
61menu "S5PC110 Machines" 56menu "S5PC110 Machines"
62 57
63config MACH_AQUILA 58config MACH_AQUILA
@@ -71,7 +66,7 @@ config MACH_AQUILA
71 select S3C_DEV_HSMMC 66 select S3C_DEV_HSMMC
72 select S3C_DEV_HSMMC1 67 select S3C_DEV_HSMMC1
73 select S3C_DEV_HSMMC2 68 select S3C_DEV_HSMMC2
74 select S5PC110_DEV_ONENAND 69 select S5P_DEV_ONENAND
75 select S5PV210_SETUP_FB_24BPP 70 select S5PV210_SETUP_FB_24BPP
76 select S5PV210_SETUP_SDHCI 71 select S5PV210_SETUP_SDHCI
77 help 72 help
@@ -88,7 +83,7 @@ config MACH_GONI
88 select S3C_DEV_HSMMC 83 select S3C_DEV_HSMMC
89 select S3C_DEV_HSMMC1 84 select S3C_DEV_HSMMC1
90 select S3C_DEV_HSMMC2 85 select S3C_DEV_HSMMC2
91 select S5PC110_DEV_ONENAND 86 select S5P_DEV_ONENAND
92 select S5PV210_SETUP_FB_24BPP 87 select S5PV210_SETUP_FB_24BPP
93 select S5PV210_SETUP_SDHCI 88 select S5PV210_SETUP_SDHCI
94 help 89 help
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 05048c5aa4c6..704548912408 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -26,7 +26,6 @@ obj-$(CONFIG_MACH_GONI) += mach-goni.o
26 26
27obj-y += dev-audio.o 27obj-y += dev-audio.o
28obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o 28obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
29obj-$(CONFIG_S5PC110_DEV_ONENAND) += dev-onenand.o
30 29
31obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o 30obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o
32obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o 31obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 245b82b53df4..2f16bfc0a116 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv210/cpu.c 1/* linux/arch/arm/mach-s5pv210/cpu.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -51,6 +51,21 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
51 .length = SZ_4K, 51 .length = SZ_4K,
52 .type = MT_DEVICE, 52 .type = MT_DEVICE,
53 }, { 53 }, {
54 .virtual = (unsigned long)S5P_VA_GPIO,
55 .pfn = __phys_to_pfn(S5PV210_PA_GPIO),
56 .length = SZ_4K,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = (unsigned long)VA_VIC0,
60 .pfn = __phys_to_pfn(S5PV210_PA_VIC0),
61 .length = SZ_16K,
62 .type = MT_DEVICE,
63 }, {
64 .virtual = (unsigned long)VA_VIC1,
65 .pfn = __phys_to_pfn(S5PV210_PA_VIC1),
66 .length = SZ_16K,
67 .type = MT_DEVICE,
68 }, {
54 .virtual = (unsigned long)VA_VIC2, 69 .virtual = (unsigned long)VA_VIC2,
55 .pfn = __phys_to_pfn(S5PV210_PA_VIC2), 70 .pfn = __phys_to_pfn(S5PV210_PA_VIC2),
56 .length = SZ_16K, 71 .length = SZ_16K,
@@ -61,6 +76,11 @@ static struct map_desc s5pv210_iodesc[] __initdata = {
61 .length = SZ_16K, 76 .length = SZ_16K,
62 .type = MT_DEVICE, 77 .type = MT_DEVICE,
63 }, { 78 }, {
79 .virtual = (unsigned long)S3C_VA_UART,
80 .pfn = __phys_to_pfn(S3C_PA_UART),
81 .length = SZ_512K,
82 .type = MT_DEVICE,
83 }, {
64 .virtual = (unsigned long)S5P_VA_SROMC, 84 .virtual = (unsigned long)S5P_VA_SROMC,
65 .pfn = __phys_to_pfn(S5PV210_PA_SROMC), 85 .pfn = __phys_to_pfn(S5PV210_PA_SROMC),
66 .length = SZ_4K, 86 .length = SZ_4K,
diff --git a/arch/arm/mach-s5pv210/include/mach/debug-macro.S b/arch/arm/mach-s5pv210/include/mach/debug-macro.S
index 7872f5c3dfc2..169fe654a59e 100644
--- a/arch/arm/mach-s5pv210/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pv210/include/mach/debug-macro.S
@@ -21,13 +21,12 @@
21 * aligned and add in the offset when we load the value here. 21 * aligned and add in the offset when we load the value here.
22 */ 22 */
23 23
24 .macro addruart, rx, tmp 24 .macro addruart, rp, rv
25 mrc p15, 0, \rx, c1, c0 25 ldr \rp, = S3C_PA_UART
26 tst \rx, #1 26 ldr \rv, = S3C_VA_UART
27 ldreq \rx, = S3C_PA_UART
28 ldrne \rx, = S3C_VA_UART
29#if CONFIG_DEBUG_S3C_UART != 0 27#if CONFIG_DEBUG_S3C_UART != 0
30 add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) 28 add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
29 add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
31#endif 30#endif
32 .endm 31 .endm
33 32
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index dd4fb6bf14b5..bd9afd52466a 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -17,7 +17,10 @@
17#include <plat/map-s5p.h> 17#include <plat/map-s5p.h>
18 18
19#define S5PC110_PA_ONENAND (0xB0000000) 19#define S5PC110_PA_ONENAND (0xB0000000)
20#define S5P_PA_ONENAND S5PC110_PA_ONENAND
21
20#define S5PC110_PA_ONENAND_DMA (0xB0600000) 22#define S5PC110_PA_ONENAND_DMA (0xB0600000)
23#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
21 24
22#define S5PV210_PA_CHIPID (0xE0000000) 25#define S5PV210_PA_CHIPID (0xE0000000)
23#define S5P_PA_CHIPID S5PV210_PA_CHIPID 26#define S5P_PA_CHIPID S5PV210_PA_CHIPID
@@ -26,7 +29,6 @@
26#define S5P_PA_SYSCON S5PV210_PA_SYSCON 29#define S5P_PA_SYSCON S5PV210_PA_SYSCON
27 30
28#define S5PV210_PA_GPIO (0xE0200000) 31#define S5PV210_PA_GPIO (0xE0200000)
29#define S5P_PA_GPIO S5PV210_PA_GPIO
30 32
31/* SPI */ 33/* SPI */
32#define S5PV210_PA_SPI0 0xE1300000 34#define S5PV210_PA_SPI0 0xE1300000
@@ -72,16 +74,9 @@
72#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) 74#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
73 75
74#define S5PV210_PA_VIC0 (0xF2000000) 76#define S5PV210_PA_VIC0 (0xF2000000)
75#define S5P_PA_VIC0 S5PV210_PA_VIC0
76
77#define S5PV210_PA_VIC1 (0xF2100000) 77#define S5PV210_PA_VIC1 (0xF2100000)
78#define S5P_PA_VIC1 S5PV210_PA_VIC1
79
80#define S5PV210_PA_VIC2 (0xF2200000) 78#define S5PV210_PA_VIC2 (0xF2200000)
81#define S5P_PA_VIC2 S5PV210_PA_VIC2
82
83#define S5PV210_PA_VIC3 (0xF2300000) 79#define S5PV210_PA_VIC3 (0xF2300000)
84#define S5P_PA_VIC3 S5PV210_PA_VIC3
85 80
86#define S5PV210_PA_SDRAM (0x20000000) 81#define S5PV210_PA_SDRAM (0x20000000)
87#define S5P_PA_SDRAM S5PV210_PA_SDRAM 82#define S5P_PA_SDRAM S5PV210_PA_SDRAM
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 0dda8012d6b2..00883087363c 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -477,7 +477,7 @@ static struct platform_device *aquila_devices[] __initdata = {
477 &aquila_i2c_gpio_pmic, 477 &aquila_i2c_gpio_pmic,
478 &aquila_device_gpiokeys, 478 &aquila_device_gpiokeys,
479 &s3c_device_fb, 479 &s3c_device_fb,
480 &s5pc110_device_onenand, 480 &s5p_device_onenand,
481 &s3c_device_hsmmc0, 481 &s3c_device_hsmmc0,
482 &s3c_device_hsmmc1, 482 &s3c_device_hsmmc1,
483 &s3c_device_hsmmc2, 483 &s3c_device_hsmmc2,
@@ -516,8 +516,6 @@ MACHINE_START(AQUILA, "Aquila")
516 /* Maintainers: 516 /* Maintainers:
517 Marek Szyprowski <m.szyprowski@samsung.com> 517 Marek Szyprowski <m.szyprowski@samsung.com>
518 Kyungmin Park <kyungmin.park@samsung.com> */ 518 Kyungmin Park <kyungmin.park@samsung.com> */
519 .phys_io = S3C_PA_UART & 0xfff00000,
520 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
521 .boot_params = S5P_PA_SDRAM + 0x100, 519 .boot_params = S5P_PA_SDRAM + 0x100,
522 .init_irq = s5pv210_init_irq, 520 .init_irq = s5pv210_init_irq,
523 .map_io = aquila_map_io, 521 .map_io = aquila_map_io,
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 53754d7d364e..d9ecf57fc2a5 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -456,7 +456,7 @@ static void goni_setup_sdhci(void)
456 456
457static struct platform_device *goni_devices[] __initdata = { 457static struct platform_device *goni_devices[] __initdata = {
458 &s3c_device_fb, 458 &s3c_device_fb,
459 &s5pc110_device_onenand, 459 &s5p_device_onenand,
460 &goni_i2c_gpio_pmic, 460 &goni_i2c_gpio_pmic,
461 &goni_device_gpiokeys, 461 &goni_device_gpiokeys,
462 &s5p_device_fimc0, 462 &s5p_device_fimc0,
@@ -491,8 +491,6 @@ static void __init goni_machine_init(void)
491 491
492MACHINE_START(GONI, "GONI") 492MACHINE_START(GONI, "GONI")
493 /* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */ 493 /* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */
494 .phys_io = S3C_PA_UART & 0xfff00000,
495 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
496 .boot_params = S5P_PA_SDRAM + 0x100, 494 .boot_params = S5P_PA_SDRAM + 0x100,
497 .init_irq = s5pv210_init_irq, 495 .init_irq = s5pv210_init_irq,
498 .map_io = goni_map_io, 496 .map_io = goni_map_io,
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index 8211bb87c54b..cea9bca79d88 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -127,8 +127,6 @@ static void __init smdkc110_machine_init(void)
127 127
128MACHINE_START(SMDKC110, "SMDKC110") 128MACHINE_START(SMDKC110, "SMDKC110")
129 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 129 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
130 .phys_io = S3C_PA_UART & 0xfff00000,
131 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
132 .boot_params = S5P_PA_SDRAM + 0x100, 130 .boot_params = S5P_PA_SDRAM + 0x100,
133 .init_irq = s5pv210_init_irq, 131 .init_irq = s5pv210_init_irq,
134 .map_io = smdkc110_map_io, 132 .map_io = smdkc110_map_io,
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index fbbc0a3c3738..83189ae9da9a 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -165,8 +165,6 @@ static void __init smdkv210_machine_init(void)
165 165
166MACHINE_START(SMDKV210, "SMDKV210") 166MACHINE_START(SMDKV210, "SMDKV210")
167 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 167 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
168 .phys_io = S3C_PA_UART & 0xfff00000,
169 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
170 .boot_params = S5P_PA_SDRAM + 0x100, 168 .boot_params = S5P_PA_SDRAM + 0x100,
171 .init_irq = s5pv210_init_irq, 169 .init_irq = s5pv210_init_irq,
172 .map_io = smdkv210_map_io, 170 .map_io = smdkv210_map_io,
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
index e5b261a99ab2..4add39853ff9 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-s5pv310/cpu.c
@@ -31,9 +31,14 @@ extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
31/* Initial IO mappings */ 31/* Initial IO mappings */
32static struct map_desc s5pv310_iodesc[] __initdata = { 32static struct map_desc s5pv310_iodesc[] __initdata = {
33 { 33 {
34 .virtual = (unsigned long)S5P_VA_COREPERI_BASE, 34 .virtual = (unsigned long)S5P_VA_SYSRAM,
35 .pfn = __phys_to_pfn(S5PV310_PA_COREPERI), 35 .pfn = __phys_to_pfn(S5PV310_PA_SYSRAM),
36 .length = SZ_8K, 36 .length = SZ_4K,
37 .type = MT_DEVICE,
38 }, {
39 .virtual = (unsigned long)S5P_VA_CMU,
40 .pfn = __phys_to_pfn(S5PV310_PA_CMU),
41 .length = SZ_128K,
37 .type = MT_DEVICE, 42 .type = MT_DEVICE,
38 }, { 43 }, {
39 .virtual = (unsigned long)S5P_VA_COMBINER_BASE, 44 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
@@ -41,19 +46,24 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
41 .length = SZ_4K, 46 .length = SZ_4K,
42 .type = MT_DEVICE, 47 .type = MT_DEVICE,
43 }, { 48 }, {
49 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
50 .pfn = __phys_to_pfn(S5PV310_PA_COREPERI),
51 .length = SZ_8K,
52 .type = MT_DEVICE,
53 }, {
44 .virtual = (unsigned long)S5P_VA_L2CC, 54 .virtual = (unsigned long)S5P_VA_L2CC,
45 .pfn = __phys_to_pfn(S5PV310_PA_L2CC), 55 .pfn = __phys_to_pfn(S5PV310_PA_L2CC),
46 .length = SZ_4K, 56 .length = SZ_4K,
47 .type = MT_DEVICE, 57 .type = MT_DEVICE,
48 }, { 58 }, {
49 .virtual = (unsigned long)S5P_VA_SYSRAM, 59 .virtual = (unsigned long)S5P_VA_GPIO,
50 .pfn = __phys_to_pfn(S5PV310_PA_SYSRAM), 60 .pfn = __phys_to_pfn(S5PV310_PA_GPIO1),
51 .length = SZ_4K, 61 .length = SZ_4K,
52 .type = MT_DEVICE, 62 .type = MT_DEVICE,
53 }, { 63 }, {
54 .virtual = (unsigned long)S5P_VA_CMU, 64 .virtual = (unsigned long)S3C_VA_UART,
55 .pfn = __phys_to_pfn(S5PV310_PA_CMU), 65 .pfn = __phys_to_pfn(S3C_PA_UART),
56 .length = SZ_128K, 66 .length = SZ_512K,
57 .type = MT_DEVICE, 67 .type = MT_DEVICE,
58 }, 68 },
59}; 69};
diff --git a/arch/arm/mach-s5pv310/include/mach/debug-macro.S b/arch/arm/mach-s5pv310/include/mach/debug-macro.S
index 6fb3893486be..b0d920c474d3 100644
--- a/arch/arm/mach-s5pv310/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pv310/include/mach/debug-macro.S
@@ -20,13 +20,12 @@
20 * aligned and add in the offset when we load the value here. 20 * aligned and add in the offset when we load the value here.
21 */ 21 */
22 22
23 .macro addruart, rx, tmp 23 .macro addruart, rp, rv
24 mrc p15, 0, \rx, c1, c0 24 ldreq \rp, = S3C_PA_UART
25 tst \rx, #1 25 ldrne \rv, = S3C_VA_UART
26 ldreq \rx, = S3C_PA_UART
27 ldrne \rx, = S3C_VA_UART
28#if CONFIG_DEBUG_S3C_UART != 0 26#if CONFIG_DEBUG_S3C_UART != 0
29 add \rx, \rx, #(0x10000 * CONFIG_DEBUG_S3C_UART) 27 add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
28 add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
30#endif 29#endif
31 .endm 30 .endm
32 31
diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h
index 4cdedda6e652..471fc3bb199a 100644
--- a/arch/arm/mach-s5pv310/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv310/include/mach/irqs.h
@@ -68,6 +68,8 @@
68 68
69#define IRQ_IIC COMBINER_IRQ(27, 0) 69#define IRQ_IIC COMBINER_IRQ(27, 0)
70 70
71#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
72
71/* Set the default NR_IRQS */ 73/* Set the default NR_IRQS */
72 74
73#define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0) 75#define NR_IRQS COMBINER_IRQ(MAX_COMBINER_NR, 0)
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
index 213e1101a3b3..aff6d23624bb 100644
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -25,6 +25,12 @@
25 25
26#define S5PV310_PA_SYSRAM (0x02025000) 26#define S5PV310_PA_SYSRAM (0x02025000)
27 27
28#define S5PC210_PA_ONENAND (0x0C000000)
29#define S5P_PA_ONENAND S5PC210_PA_ONENAND
30
31#define S5PC210_PA_ONENAND_DMA (0x0C600000)
32#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
33
28#define S5PV310_PA_CHIPID (0x10000000) 34#define S5PV310_PA_CHIPID (0x10000000)
29#define S5P_PA_CHIPID S5PV310_PA_CHIPID 35#define S5P_PA_CHIPID S5PV310_PA_CHIPID
30 36
@@ -46,7 +52,6 @@
46#define S5PV310_PA_GPIO1 (0x11400000) 52#define S5PV310_PA_GPIO1 (0x11400000)
47#define S5PV310_PA_GPIO2 (0x11000000) 53#define S5PV310_PA_GPIO2 (0x11000000)
48#define S5PV310_PA_GPIO3 (0x03860000) 54#define S5PV310_PA_GPIO3 (0x03860000)
49#define S5P_PA_GPIO S5PV310_PA_GPIO1
50 55
51#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000)) 56#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
52 57
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h
index 990f3ba88a1f..b7ec252384f4 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-s5pv310/include/mach/smp.h
@@ -7,17 +7,10 @@
7#define ASM_ARCH_SMP_H __FILE__ 7#define ASM_ARCH_SMP_H __FILE__
8 8
9#include <asm/hardware/gic.h> 9#include <asm/hardware/gic.h>
10#include <asm/smp_mpidr.h>
10 11
11extern void __iomem *gic_cpu_base_addr; 12extern void __iomem *gic_cpu_base_addr;
12 13
13#define hard_smp_processor_id() \
14 ({ \
15 unsigned int cpunum; \
16 __asm__("mrc p15, 0, %0, c0, c0, 5" \
17 : "=r" (cpunum)); \
18 cpunum &= 0x03; \
19 })
20
21/* 14/*
22 * We use IRQ1 as the IPI 15 * We use IRQ1 as the IPI
23 */ 16 */
diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c
index 0d6ab77709d2..46215a14b3bb 100644
--- a/arch/arm/mach-s5pv310/mach-smdkv310.c
+++ b/arch/arm/mach-s5pv310/mach-smdkv310.c
@@ -82,8 +82,6 @@ static void __init smdkv310_machine_init(void)
82MACHINE_START(SMDKV310, "SMDKV310") 82MACHINE_START(SMDKV310, "SMDKV310")
83 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 83 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
84 /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */ 84 /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
85 .phys_io = S3C_PA_UART & 0xfff00000,
86 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
87 .boot_params = S5P_PA_SDRAM + 0x100, 85 .boot_params = S5P_PA_SDRAM + 0x100,
88 .init_irq = s5pv310_init_irq, 86 .init_irq = s5pv310_init_irq,
89 .map_io = smdkv310_map_io, 87 .map_io = smdkv310_map_io,
diff --git a/arch/arm/mach-s5pv310/mach-universal_c210.c b/arch/arm/mach-s5pv310/mach-universal_c210.c
index 2388cb947936..d7c2ec770f88 100644
--- a/arch/arm/mach-s5pv310/mach-universal_c210.c
+++ b/arch/arm/mach-s5pv310/mach-universal_c210.c
@@ -76,8 +76,6 @@ static void __init universal_machine_init(void)
76 76
77MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") 77MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
78 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */ 78 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
79 .phys_io = S3C_PA_UART & 0xfff00000,
80 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
81 .boot_params = S5P_PA_SDRAM + 0x100, 79 .boot_params = S5P_PA_SDRAM + 0x100,
82 .init_irq = s5pv310_init_irq, 80 .init_irq = s5pv310_init_irq,
83 .map_io = universal_map_io, 81 .map_io = universal_map_io,
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index 169e5b87dbff..5778274a8260 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -447,8 +447,6 @@ static void __init assabet_map_io(void)
447 447
448 448
449MACHINE_START(ASSABET, "Intel-Assabet") 449MACHINE_START(ASSABET, "Intel-Assabet")
450 .phys_io = 0x80000000,
451 .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc,
452 .boot_params = 0xc0000100, 450 .boot_params = 0xc0000100,
453 .fixup = fixup_assabet, 451 .fixup = fixup_assabet,
454 .map_io = assabet_map_io, 452 .map_io = assabet_map_io,
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c
index 259cb2c15fff..4f19ff868b00 100644
--- a/arch/arm/mach-sa1100/badge4.c
+++ b/arch/arm/mach-sa1100/badge4.c
@@ -302,8 +302,6 @@ static void __init badge4_map_io(void)
302} 302}
303 303
304MACHINE_START(BADGE4, "Hewlett-Packard Laboratories BadgePAD 4") 304MACHINE_START(BADGE4, "Hewlett-Packard Laboratories BadgePAD 4")
305 .phys_io = 0x80000000,
306 .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc,
307 .boot_params = 0xc0000100, 305 .boot_params = 0xc0000100,
308 .map_io = badge4_map_io, 306 .map_io = badge4_map_io,
309 .init_irq = sa1100_init_irq, 307 .init_irq = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index bc950ef418af..98d780608c7e 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -135,8 +135,6 @@ static void __init cerf_init(void)
135 135
136MACHINE_START(CERF, "Intrinsyc CerfBoard/CerfCube") 136MACHINE_START(CERF, "Intrinsyc CerfBoard/CerfCube")
137 /* Maintainer: support@intrinsyc.com */ 137 /* Maintainer: support@intrinsyc.com */
138 .phys_io = 0x80000000,
139 .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc,
140 .map_io = cerf_map_io, 138 .map_io = cerf_map_io,
141 .init_irq = cerf_init_irq, 139 .init_irq = cerf_init_irq,
142 .timer = &sa1100_timer, 140 .timer = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index 16e682d5dbb7..d43c5ef58eb6 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -379,8 +379,6 @@ static void __init collie_map_io(void)
379} 379}
380 380
381MACHINE_START(COLLIE, "Sharp-Collie") 381MACHINE_START(COLLIE, "Sharp-Collie")
382 .phys_io = 0x80000000,
383 .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc,
384 .map_io = collie_map_io, 382 .map_io = collie_map_io,
385 .init_irq = sa1100_init_irq, 383 .init_irq = sa1100_init_irq,
386 .timer = &sa1100_timer, 384 .timer = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/h3100.c b/arch/arm/mach-sa1100/h3100.c
index 0c7cea0dc013..03d7376cf8a0 100644
--- a/arch/arm/mach-sa1100/h3100.c
+++ b/arch/arm/mach-sa1100/h3100.c
@@ -84,8 +84,6 @@ static void __init h3100_mach_init(void)
84} 84}
85 85
86MACHINE_START(H3100, "Compaq iPAQ H3100") 86MACHINE_START(H3100, "Compaq iPAQ H3100")
87 .phys_io = 0x80000000,
88 .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc,
89 .boot_params = 0xc0000100, 87 .boot_params = 0xc0000100,
90 .map_io = h3100_map_io, 88 .map_io = h3100_map_io,
91 .init_irq = sa1100_init_irq, 89 .init_irq = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index af3b71459f8d..965f64a836f8 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -125,8 +125,6 @@ static void __init h3600_mach_init(void)
125} 125}
126 126
127MACHINE_START(H3600, "Compaq iPAQ H3600") 127MACHINE_START(H3600, "Compaq iPAQ H3600")
128 .phys_io = 0x80000000,
129 .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc,
130 .boot_params = 0xc0000100, 128 .boot_params = 0xc0000100,
131 .map_io = h3600_map_io, 129 .map_io = h3600_map_io,
132 .init_irq = sa1100_init_irq, 130 .init_irq = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c
index 51568dfc8e97..db5e434a17db 100644
--- a/arch/arm/mach-sa1100/hackkit.c
+++ b/arch/arm/mach-sa1100/hackkit.c
@@ -195,8 +195,6 @@ static void __init hackkit_init(void)
195 */ 195 */
196 196
197MACHINE_START(HACKKIT, "HackKit Cpu Board") 197MACHINE_START(HACKKIT, "HackKit Cpu Board")
198 .phys_io = 0x80000000,
199 .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc,
200 .boot_params = 0xc0000100, 198 .boot_params = 0xc0000100,
201 .map_io = hackkit_map_io, 199 .map_io = hackkit_map_io,
202 .init_irq = sa1100_init_irq, 200 .init_irq = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/include/mach/debug-macro.S b/arch/arm/mach-sa1100/include/mach/debug-macro.S
index 336adccea542..0cd0fc9635b6 100644
--- a/arch/arm/mach-sa1100/include/mach/debug-macro.S
+++ b/arch/arm/mach-sa1100/include/mach/debug-macro.S
@@ -12,33 +12,37 @@
12*/ 12*/
13#include <mach/hardware.h> 13#include <mach/hardware.h>
14 14
15 .macro addruart, rx, tmp 15 .macro addruart, rp, rv
16 mrc p15, 0, \rx, c1, c0 16 mrc p15, 0, \rp, c1, c0
17 tst \rx, #1 @ MMU enabled? 17 tst \rp, #1 @ MMU enabled?
18 moveq \rx, #0x80000000 @ physical base address 18 moveq \rp, #0x80000000 @ physical base address
19 movne \rx, #0xf8000000 @ virtual address 19 movne \rp, #0xf8000000 @ virtual address
20 20
21 @ We probe for the active serial port here, coherently with 21 @ We probe for the active serial port here, coherently with
22 @ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h. 22 @ the comment in arch/arm/mach-sa1100/include/mach/uncompress.h.
23 @ We assume r1 can be clobbered. 23 @ We assume r1 can be clobbered.
24 24
25 @ see if Ser3 is active 25 @ see if Ser3 is active
26 add \rx, \rx, #0x00050000 26 add \rp, \rp, #0x00050000
27 ldr r1, [\rx, #UTCR3] 27 ldr \rv, [\rp, #UTCR3]
28 tst r1, #UTCR3_TXE 28 tst \rv, #UTCR3_TXE
29 29
30 @ if Ser3 is inactive, then try Ser1 30 @ if Ser3 is inactive, then try Ser1
31 addeq \rx, \rx, #(0x00010000 - 0x00050000) 31 addeq \rp, \rp, #(0x00010000 - 0x00050000)
32 ldreq r1, [\rx, #UTCR3] 32 ldreq \rv, [\rp, #UTCR3]
33 tsteq r1, #UTCR3_TXE 33 tsteq \rv, #UTCR3_TXE
34 34
35 @ if Ser1 is inactive, then try Ser2 35 @ if Ser1 is inactive, then try Ser2
36 addeq \rx, \rx, #(0x00030000 - 0x00010000) 36 addeq \rp, \rp, #(0x00030000 - 0x00010000)
37 ldreq r1, [\rx, #UTCR3] 37 ldreq \rv, [\rp, #UTCR3]
38 tsteq r1, #UTCR3_TXE 38 tsteq \rv, #UTCR3_TXE
39
40 @ clear top bits, and generate both phys and virt addresses
41 lsl \rp, \rp, #8
42 lsr \rp, \rp, #8
43 orr \rv, \rp, #0xf8000000 @ virtual
44 orr \rp, \rp, #0x80000000 @ physical
39 45
40 @ if all ports are inactive, then there is nothing we can do
41 moveq pc, lr
42 .endm 46 .endm
43 47
44 .macro senduart,rd,rx 48 .macro senduart,rd,rx
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c
index d3ec620618f1..491ac9f20fb4 100644
--- a/arch/arm/mach-sa1100/jornada720.c
+++ b/arch/arm/mach-sa1100/jornada720.c
@@ -364,8 +364,6 @@ static void __init jornada720_mach_init(void)
364 364
365MACHINE_START(JORNADA720, "HP Jornada 720") 365MACHINE_START(JORNADA720, "HP Jornada 720")
366 /* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */ 366 /* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */
367 .phys_io = 0x80000000,
368 .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc,
369 .boot_params = 0xc0000100, 367 .boot_params = 0xc0000100,
370 .map_io = jornada720_map_io, 368 .map_io = jornada720_map_io,
371 .init_irq = sa1100_init_irq, 369 .init_irq = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index 68069d6dc07a..7b9556b59057 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -61,8 +61,6 @@ static void __init lart_map_io(void)
61} 61}
62 62
63MACHINE_START(LART, "LART") 63MACHINE_START(LART, "LART")
64 .phys_io = 0x80000000,
65 .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc,
66 .boot_params = 0xc0000100, 64 .boot_params = 0xc0000100,
67 .map_io = lart_map_io, 65 .map_io = lart_map_io,
68 .init_irq = sa1100_init_irq, 66 .init_irq = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c
index 1ccd6018d3a3..42b80400c100 100644
--- a/arch/arm/mach-sa1100/pleb.c
+++ b/arch/arm/mach-sa1100/pleb.c
@@ -146,8 +146,6 @@ static void __init pleb_map_io(void)
146} 146}
147 147
148MACHINE_START(PLEB, "PLEB") 148MACHINE_START(PLEB, "PLEB")
149 .phys_io = 0x80000000,
150 .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc,
151 .map_io = pleb_map_io, 149 .map_io = pleb_map_io,
152 .init_irq = sa1100_init_irq, 150 .init_irq = sa1100_init_irq,
153 .timer = &sa1100_timer, 151 .timer = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c
index 85e82bb73d7e..7917b2405579 100644
--- a/arch/arm/mach-sa1100/shannon.c
+++ b/arch/arm/mach-sa1100/shannon.c
@@ -82,8 +82,6 @@ static void __init shannon_map_io(void)
82} 82}
83 83
84MACHINE_START(SHANNON, "Shannon (AKA: Tuxscreen)") 84MACHINE_START(SHANNON, "Shannon (AKA: Tuxscreen)")
85 .phys_io = 0x80000000,
86 .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc,
87 .boot_params = 0xc0000100, 85 .boot_params = 0xc0000100,
88 .map_io = shannon_map_io, 86 .map_io = shannon_map_io,
89 .init_irq = sa1100_init_irq, 87 .init_irq = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index 49cfd64663ac..27692d0ffbe8 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -228,8 +228,6 @@ arch_initcall(simpad_init);
228 228
229MACHINE_START(SIMPAD, "Simpad") 229MACHINE_START(SIMPAD, "Simpad")
230 /* Maintainer: Holger Freyther */ 230 /* Maintainer: Holger Freyther */
231 .phys_io = 0x80000000,
232 .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc,
233 .boot_params = 0xc0000100, 231 .boot_params = 0xc0000100,
234 .map_io = simpad_map_io, 232 .map_io = simpad_map_io,
235 .init_irq = sa1100_init_irq, 233 .init_irq = sa1100_init_irq,
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 358d875ace14..5cf7f94c1f31 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -152,8 +152,6 @@ static struct sys_timer shark_timer = {
152 152
153MACHINE_START(SHARK, "Shark") 153MACHINE_START(SHARK, "Shark")
154 /* Maintainer: Alexander Schulz */ 154 /* Maintainer: Alexander Schulz */
155 .phys_io = 0x40000000,
156 .io_pg_offst = ((0xe0000000) >> 18) & 0xfffc,
157 .boot_params = 0x08003000, 155 .boot_params = 0x08003000,
158 .map_io = shark_map_io, 156 .map_io = shark_map_io,
159 .init_irq = shark_init_irq, 157 .init_irq = shark_init_irq,
diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S
index 5ea24d4d1ba6..a473f55dc71f 100644
--- a/arch/arm/mach-shark/include/mach/debug-macro.S
+++ b/arch/arm/mach-shark/include/mach/debug-macro.S
@@ -11,9 +11,10 @@
11 * 11 *
12*/ 12*/
13 13
14 .macro addruart, rx, tmp 14 .macro addruart, rp, rv
15 mov \rx, #0xe0000000 15 mov \rp, #0xe0000000
16 orr \rx, \rx, #0x000003f8 16 orr \rp, \rp, #0x000003f8
17 mov \rv, \rp
17 .endm 18 .endm
18 19
19 .macro senduart,rd,rx 20 .macro senduart,rd,rx
diff --git a/arch/arm/mach-shark/include/mach/vmalloc.h b/arch/arm/mach-shark/include/mach/vmalloc.h
index f6c6837c5451..8e845b6a7cb5 100644
--- a/arch/arm/mach-shark/include/mach/vmalloc.h
+++ b/arch/arm/mach-shark/include/mach/vmalloc.h
@@ -1,4 +1,4 @@
1/* 1/*
2 * arch/arm/mach-shark/include/mach/vmalloc.h 2 * arch/arm/mach-shark/include/mach/vmalloc.h
3 */ 3 */
4#define VMALLOC_END (PAGE_OFFSET + 0x10000000) 4#define VMALLOC_END 0xd0000000
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 95935c83c306..14923989ea05 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -1105,8 +1105,6 @@ static struct sys_timer ap4evb_timer = {
1105}; 1105};
1106 1106
1107MACHINE_START(AP4EVB, "ap4evb") 1107MACHINE_START(AP4EVB, "ap4evb")
1108 .phys_io = 0xe6000000,
1109 .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc,
1110 .map_io = ap4evb_map_io, 1108 .map_io = ap4evb_map_io,
1111 .init_irq = sh7372_init_irq, 1109 .init_irq = sh7372_init_irq,
1112 .init_machine = ap4evb_init, 1110 .init_machine = ap4evb_init,
diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c
index a5525901e91f..3b83d6320bec 100644
--- a/arch/arm/mach-shmobile/board-g3evm.c
+++ b/arch/arm/mach-shmobile/board-g3evm.c
@@ -365,8 +365,6 @@ static struct sys_timer g3evm_timer = {
365}; 365};
366 366
367MACHINE_START(G3EVM, "g3evm") 367MACHINE_START(G3EVM, "g3evm")
368 .phys_io = 0xe6000000,
369 .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc,
370 .map_io = g3evm_map_io, 368 .map_io = g3evm_map_io,
371 .init_irq = sh7367_init_irq, 369 .init_irq = sh7367_init_irq,
372 .init_machine = g3evm_init, 370 .init_machine = g3evm_init,
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index 2c3ff6f7f34c..5b3b582ef3f2 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -392,8 +392,6 @@ static struct sys_timer g4evm_timer = {
392}; 392};
393 393
394MACHINE_START(G4EVM, "g4evm") 394MACHINE_START(G4EVM, "g4evm")
395 .phys_io = 0xe6000000,
396 .io_pg_offst = ((0xe6000000) >> 18) & 0xfffc,
397 .map_io = g4evm_map_io, 395 .map_io = g4evm_map_io,
398 .init_irq = sh7377_init_irq, 396 .init_irq = sh7377_init_irq,
399 .init_machine = g4evm_init, 397 .init_machine = g4evm_init,
diff --git a/arch/arm/mach-stmp378x/stmp378x_devb.c b/arch/arm/mach-stmp378x/stmp378x_devb.c
index 90d8fe6f10fe..06158848afd9 100644
--- a/arch/arm/mach-stmp378x/stmp378x_devb.c
+++ b/arch/arm/mach-stmp378x/stmp378x_devb.c
@@ -324,8 +324,6 @@ static void __init stmp378x_devb_init(void)
324} 324}
325 325
326MACHINE_START(STMP378X, "STMP378X") 326MACHINE_START(STMP378X, "STMP378X")
327 .phys_io = 0x80000000,
328 .io_pg_offst = ((0xf0000000) >> 18) & 0xfffc,
329 .boot_params = 0x40000100, 327 .boot_params = 0x40000100,
330 .map_io = stmp378x_map_io, 328 .map_io = stmp378x_map_io,
331 .init_irq = stmp378x_init_irq, 329 .init_irq = stmp378x_init_irq,
diff --git a/arch/arm/mach-stmp37xx/stmp37xx_devb.c b/arch/arm/mach-stmp37xx/stmp37xx_devb.c
index 394f21ab59e6..311d8552d362 100644
--- a/arch/arm/mach-stmp37xx/stmp37xx_devb.c
+++ b/arch/arm/mach-stmp37xx/stmp37xx_devb.c
@@ -91,8 +91,6 @@ static void __init stmp37xx_devb_init(void)
91} 91}
92 92
93MACHINE_START(STMP37XX, "STMP37XX") 93MACHINE_START(STMP37XX, "STMP37XX")
94 .phys_io = 0x80000000,
95 .io_pg_offst = ((0xf0000000) >> 18) & 0xfffc,
96 .boot_params = 0x40000100, 94 .boot_params = 0x40000100,
97 .map_io = stmp37xx_map_io, 95 .map_io = stmp37xx_map_io,
98 .init_irq = stmp37xx_init_irq, 96 .init_irq = stmp37xx_init_irq,
diff --git a/arch/arm/mach-tcc8k/Kconfig b/arch/arm/mach-tcc8k/Kconfig
new file mode 100644
index 000000000000..ad86415d1577
--- /dev/null
+++ b/arch/arm/mach-tcc8k/Kconfig
@@ -0,0 +1,11 @@
1if ARCH_TCC8K
2
3comment "TCC8000 systems:"
4
5config MACH_TCC8000_SDK
6 bool "Telechips TCC8000-SDK development kit"
7 default y
8 help
9 Support for the Telechips TCC8000-SDK board.
10
11endif
diff --git a/arch/arm/mach-tcc8k/Makefile b/arch/arm/mach-tcc8k/Makefile
new file mode 100644
index 000000000000..9bacf31e49ba
--- /dev/null
+++ b/arch/arm/mach-tcc8k/Makefile
@@ -0,0 +1,9 @@
1#
2# Makefile for TCC8K boards and common files.
3#
4
5# Common support
6obj-y += clock.o irq.o time.o io.o devices.o
7
8# Board specific support
9obj-$(CONFIG_MACH_TCC8000_SDK) += board-tcc8000-sdk.o
diff --git a/arch/arm/mach-tcc8k/Makefile.boot b/arch/arm/mach-tcc8k/Makefile.boot
new file mode 100644
index 000000000000..f135c9deae10
--- /dev/null
+++ b/arch/arm/mach-tcc8k/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x20008000
2params_phys-y := 0x20000100
3initrd_phys-y := 0x20800000
diff --git a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
new file mode 100644
index 000000000000..7991415e666b
--- /dev/null
+++ b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
@@ -0,0 +1,62 @@
1/*
2 * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <linux/platform_device.h>
12
13#include <asm/mach-types.h>
14
15#include <asm/mach/arch.h>
16#include <asm/mach/map.h>
17#include <asm/mach/time.h>
18
19#include <mach/clock.h>
20
21#include "common.h"
22
23#define XI_FREQUENCY 12000000
24#define XTI_FREQUENCY 32768
25
26#ifdef CONFIG_MTD_NAND_TCC
27/* NAND */
28static struct tcc_nand_platform_data tcc8k_sdk_nand_data = {
29 .width = 1,
30 .hw_ecc = 0,
31};
32#endif
33
34static void __init tcc8k_init(void)
35{
36#ifdef CONFIG_MTD_NAND_TCC
37 tcc_nand_device.dev.platform_data = &tcc8k_sdk_nand_data;
38 platform_device_register(&tcc_nand_device);
39#endif
40}
41
42static void __init tcc8k_init_timer(void)
43{
44 tcc_clocks_init(XI_FREQUENCY, XTI_FREQUENCY);
45}
46
47static struct sys_timer tcc8k_timer = {
48 .init = tcc8k_init_timer,
49};
50
51static void __init tcc8k_map_io(void)
52{
53 tcc8k_map_common_io();
54}
55
56MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board")
57 .boot_params = PHYS_OFFSET + 0x00000100,
58 .map_io = tcc8k_map_io,
59 .init_irq = tcc8k_init_irq,
60 .init_machine = tcc8k_init,
61 .timer = &tcc8k_timer,
62MACHINE_END
diff --git a/arch/arm/mach-tcc8k/clock.c b/arch/arm/mach-tcc8k/clock.c
new file mode 100644
index 000000000000..ba32a15127ab
--- /dev/null
+++ b/arch/arm/mach-tcc8k/clock.c
@@ -0,0 +1,567 @@
1/*
2 * Lowlevel clock handling for Telechips TCC8xxx SoCs
3 *
4 * Copyright (C) 2010 by Hans J. Koch <hjk@linutronix.de>
5 *
6 * Licensed under the terms of the GPL v2
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/err.h>
12#include <linux/io.h>
13#include <linux/module.h>
14#include <linux/spinlock.h>
15
16#include <asm/clkdev.h>
17
18#include <mach/clock.h>
19#include <mach/irqs.h>
20#include <mach/tcc8k-regs.h>
21
22#include "common.h"
23
24#define BCLKCTR0 (CKC_BASE + BCLKCTR0_OFFS)
25#define BCLKCTR1 (CKC_BASE + BCLKCTR1_OFFS)
26
27#define ACLKREF (CKC_BASE + ACLKREF_OFFS)
28#define ACLKUART0 (CKC_BASE + ACLKUART0_OFFS)
29#define ACLKUART1 (CKC_BASE + ACLKUART1_OFFS)
30#define ACLKUART2 (CKC_BASE + ACLKUART2_OFFS)
31#define ACLKUART3 (CKC_BASE + ACLKUART3_OFFS)
32#define ACLKUART4 (CKC_BASE + ACLKUART4_OFFS)
33#define ACLKI2C (CKC_BASE + ACLKI2C_OFFS)
34#define ACLKADC (CKC_BASE + ACLKADC_OFFS)
35#define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS)
36#define ACLKLCD (CKC_BASE + ACLKLCD_OFFS)
37#define ACLKSDH0 (CKC_BASE + ACLKSDH0_OFFS)
38#define ACLKSDH1 (CKC_BASE + ACLKSDH1_OFFS)
39#define ACLKSPI0 (CKC_BASE + ACLKSPI0_OFFS)
40#define ACLKSPI1 (CKC_BASE + ACLKSPI1_OFFS)
41#define ACLKSPDIF (CKC_BASE + ACLKSPDIF_OFFS)
42#define ACLKC3DEC (CKC_BASE + ACLKC3DEC_OFFS)
43#define ACLKCAN0 (CKC_BASE + ACLKCAN0_OFFS)
44#define ACLKCAN1 (CKC_BASE + ACLKCAN1_OFFS)
45#define ACLKGSB0 (CKC_BASE + ACLKGSB0_OFFS)
46#define ACLKGSB1 (CKC_BASE + ACLKGSB1_OFFS)
47#define ACLKGSB2 (CKC_BASE + ACLKGSB2_OFFS)
48#define ACLKGSB3 (CKC_BASE + ACLKGSB3_OFFS)
49#define ACLKUSBH (CKC_BASE + ACLKUSBH_OFFS)
50#define ACLKTCT (CKC_BASE + ACLKTCT_OFFS)
51#define ACLKTCX (CKC_BASE + ACLKTCX_OFFS)
52#define ACLKTCZ (CKC_BASE + ACLKTCZ_OFFS)
53
54/* Crystal frequencies */
55static unsigned long xi_rate, xti_rate;
56
57static void __iomem *pll_cfg_addr(int pll)
58{
59 switch (pll) {
60 case 0: return (CKC_BASE + PLL0CFG_OFFS);
61 case 1: return (CKC_BASE + PLL1CFG_OFFS);
62 case 2: return (CKC_BASE + PLL2CFG_OFFS);
63 default:
64 BUG();
65 }
66}
67
68static int pll_enable(int pll, int enable)
69{
70 u32 reg;
71 void __iomem *addr = pll_cfg_addr(pll);
72
73 reg = __raw_readl(addr);
74 if (enable)
75 reg &= ~PLLxCFG_PD;
76 else
77 reg |= PLLxCFG_PD;
78
79 __raw_writel(reg, addr);
80 return 0;
81}
82
83static int xi_enable(int enable)
84{
85 u32 reg;
86
87 reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
88 if (enable)
89 reg |= CLKCTRL_XE;
90 else
91 reg &= ~CLKCTRL_XE;
92
93 __raw_writel(reg, CKC_BASE + CLKCTRL_OFFS);
94 return 0;
95}
96
97static int root_clk_enable(enum root_clks src)
98{
99 switch (src) {
100 case CLK_SRC_PLL0: return pll_enable(0, 1);
101 case CLK_SRC_PLL1: return pll_enable(1, 1);
102 case CLK_SRC_PLL2: return pll_enable(2, 1);
103 case CLK_SRC_XI: return xi_enable(1);
104 default:
105 BUG();
106 }
107 return 0;
108}
109
110static int root_clk_disable(enum root_clks root_src)
111{
112 switch (root_src) {
113 case CLK_SRC_PLL0: return pll_enable(0, 0);
114 case CLK_SRC_PLL1: return pll_enable(1, 0);
115 case CLK_SRC_PLL2: return pll_enable(2, 0);
116 case CLK_SRC_XI: return xi_enable(0);
117 default:
118 BUG();
119 }
120 return 0;
121}
122
123static int enable_clk(struct clk *clk)
124{
125 u32 reg;
126
127 if (clk->root_id != CLK_SRC_NOROOT)
128 return root_clk_enable(clk->root_id);
129
130 if (clk->aclkreg) {
131 reg = __raw_readl(clk->aclkreg);
132 reg |= ACLK_EN;
133 __raw_writel(reg, clk->aclkreg);
134 }
135 if (clk->bclkctr) {
136 reg = __raw_readl(clk->bclkctr);
137 reg |= 1 << clk->bclk_shift;
138 __raw_writel(reg, clk->bclkctr);
139 }
140 return 0;
141}
142
143static void disable_clk(struct clk *clk)
144{
145 u32 reg;
146
147 if (clk->root_id != CLK_SRC_NOROOT) {
148 root_clk_disable(clk->root_id);
149 return;
150 }
151
152 if (clk->bclkctr) {
153 reg = __raw_readl(clk->bclkctr);
154 reg &= ~(1 << clk->bclk_shift);
155 __raw_writel(reg, clk->bclkctr);
156 }
157 if (clk->aclkreg) {
158 reg = __raw_readl(clk->aclkreg);
159 reg &= ~ACLK_EN;
160 __raw_writel(reg, clk->aclkreg);
161 }
162}
163
164static unsigned long get_rate_pll(int pll)
165{
166 u32 reg;
167 unsigned long s, m, p;
168 void __iomem *addr = pll_cfg_addr(pll);
169
170 reg = __raw_readl(addr);
171 s = (reg >> 16) & 0x07;
172 m = (reg >> 8) & 0xff;
173 p = reg & 0x3f;
174
175 return (m * xi_rate) / (p * (1 << s));
176}
177
178static unsigned long get_rate_pll_div(int pll)
179{
180 u32 reg;
181 unsigned long div = 0;
182 void __iomem *addr;
183
184 switch (pll) {
185 case 0:
186 addr = CKC_BASE + CLKDIVC0_OFFS;
187 reg = __raw_readl(addr);
188 if (reg & CLKDIVC0_P0E)
189 div = (reg >> 24) & 0x3f;
190 break;
191 case 1:
192 addr = CKC_BASE + CLKDIVC0_OFFS;
193 reg = __raw_readl(addr);
194 if (reg & CLKDIVC0_P1E)
195 div = (reg >> 16) & 0x3f;
196 break;
197 case 2:
198 addr = CKC_BASE + CLKDIVC1_OFFS;
199 reg = __raw_readl(addr);
200 if (reg & CLKDIVC1_P2E)
201 div = __raw_readl(addr) & 0x3f;
202 break;
203 }
204 return get_rate_pll(pll) / (div + 1);
205}
206
207static unsigned long get_rate_xi_div(void)
208{
209 unsigned long div = 0;
210 u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
211
212 if (reg & CLKDIVC0_XE)
213 div = (reg >> 8) & 0x3f;
214
215 return xi_rate / (div + 1);
216}
217
218static unsigned long get_rate_xti_div(void)
219{
220 unsigned long div = 0;
221 u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
222
223 if (reg & CLKDIVC0_XTE)
224 div = reg & 0x3f;
225
226 return xti_rate / (div + 1);
227}
228
229static unsigned long root_clk_get_rate(enum root_clks src)
230{
231 switch (src) {
232 case CLK_SRC_PLL0: return get_rate_pll(0);
233 case CLK_SRC_PLL1: return get_rate_pll(1);
234 case CLK_SRC_PLL2: return get_rate_pll(2);
235 case CLK_SRC_PLL0DIV: return get_rate_pll_div(0);
236 case CLK_SRC_PLL1DIV: return get_rate_pll_div(1);
237 case CLK_SRC_PLL2DIV: return get_rate_pll_div(2);
238 case CLK_SRC_XI: return xi_rate;
239 case CLK_SRC_XTI: return xti_rate;
240 case CLK_SRC_XIDIV: return get_rate_xi_div();
241 case CLK_SRC_XTIDIV: return get_rate_xti_div();
242 default: return 0;
243 }
244}
245
246static unsigned long aclk_get_rate(struct clk *clk)
247{
248 u32 reg;
249 unsigned long div;
250 unsigned int src;
251
252 reg = __raw_readl(clk->aclkreg);
253 div = reg & 0x0fff;
254 src = (reg >> ACLK_SEL_SHIFT) & CLK_SRC_MASK;
255 return root_clk_get_rate(src) / (div + 1);
256}
257
258static unsigned long aclk_best_div(struct clk *clk, unsigned long rate)
259{
260 unsigned long div, src, freq, r1, r2;
261
262 src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
263 src &= CLK_SRC_MASK;
264 freq = root_clk_get_rate(src);
265 div = freq / rate + 1;
266 r1 = freq / div;
267 r2 = freq / (div + 1);
268 if (r2 >= rate)
269 return div + 1;
270 if ((rate - r2) < (r1 - rate))
271 return div + 1;
272
273 return div;
274}
275
276static unsigned long aclk_round_rate(struct clk *clk, unsigned long rate)
277{
278 unsigned int src;
279
280 src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
281 src &= CLK_SRC_MASK;
282
283 return root_clk_get_rate(src) / aclk_best_div(clk, rate);
284}
285
286static int aclk_set_rate(struct clk *clk, unsigned long rate)
287{
288 u32 reg;
289
290 reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK;
291 reg |= aclk_best_div(clk, rate);
292 return 0;
293}
294
295static unsigned long get_rate_sys(struct clk *clk)
296{
297 unsigned int src;
298
299 src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK;
300 return root_clk_get_rate(src);
301}
302
303static unsigned long get_rate_bus(struct clk *clk)
304{
305 unsigned int div;
306
307 div = (__raw_readl(CKC_BASE + CLKCTRL_OFFS) >> 4) & 0xff;
308 return get_rate_sys(clk) / (div + 1);
309}
310
311static unsigned long get_rate_cpu(struct clk *clk)
312{
313 unsigned int reg, div, fsys, fbus;
314
315 fbus = get_rate_bus(clk);
316 reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
317 if (reg & (1 << 29))
318 return fbus;
319 fsys = get_rate_sys(clk);
320 div = (reg >> 16) & 0x0f;
321 return fbus + ((fsys - fbus) * (div + 1)) / 16;
322}
323
324static unsigned long get_rate_root(struct clk *clk)
325{
326 return root_clk_get_rate(clk->root_id);
327}
328
329static int aclk_set_parent(struct clk *clock, struct clk *parent)
330{
331 u32 reg;
332
333 if (clock->parent == parent)
334 return 0;
335
336 clock->parent = parent;
337
338 if (!parent)
339 return 0;
340
341 if (parent->root_id == CLK_SRC_NOROOT)
342 return 0;
343 reg = __raw_readl(clock->aclkreg);
344 reg &= ~ACLK_SEL_MASK;
345 reg |= (parent->root_id << ACLK_SEL_SHIFT) & ACLK_SEL_MASK;
346 __raw_writel(reg, clock->aclkreg);
347
348 return 0;
349}
350
351#define DEFINE_ROOT_CLOCK(name, ri, p) \
352 static struct clk name = { \
353 .root_id = ri, \
354 .get_rate = get_rate_root, \
355 .enable = enable_clk, \
356 .disable = disable_clk, \
357 .parent = p, \
358 };
359
360#define DEFINE_SPECIAL_CLOCK(name, gr, p) \
361 static struct clk name = { \
362 .root_id = CLK_SRC_NOROOT, \
363 .get_rate = gr, \
364 .parent = p, \
365 };
366
367#define DEFINE_ACLOCK(name, bc, bs, ar) \
368 static struct clk name = { \
369 .root_id = CLK_SRC_NOROOT, \
370 .bclkctr = bc, \
371 .bclk_shift = bs, \
372 .aclkreg = ar, \
373 .get_rate = aclk_get_rate, \
374 .set_rate = aclk_set_rate, \
375 .round_rate = aclk_round_rate, \
376 .enable = enable_clk, \
377 .disable = disable_clk, \
378 .set_parent = aclk_set_parent, \
379 };
380
381#define DEFINE_BCLOCK(name, bc, bs, gr, p) \
382 static struct clk name = { \
383 .root_id = CLK_SRC_NOROOT, \
384 .bclkctr = bc, \
385 .bclk_shift = bs, \
386 .get_rate = gr, \
387 .enable = enable_clk, \
388 .disable = disable_clk, \
389 .parent = p, \
390 };
391
392DEFINE_ROOT_CLOCK(xi, CLK_SRC_XI, NULL)
393DEFINE_ROOT_CLOCK(xti, CLK_SRC_XTI, NULL)
394DEFINE_ROOT_CLOCK(xidiv, CLK_SRC_XIDIV, &xi)
395DEFINE_ROOT_CLOCK(xtidiv, CLK_SRC_XTIDIV, &xti)
396DEFINE_ROOT_CLOCK(pll0, CLK_SRC_PLL0, &xi)
397DEFINE_ROOT_CLOCK(pll1, CLK_SRC_PLL1, &xi)
398DEFINE_ROOT_CLOCK(pll2, CLK_SRC_PLL2, &xi)
399DEFINE_ROOT_CLOCK(pll0div, CLK_SRC_PLL0DIV, &pll0)
400DEFINE_ROOT_CLOCK(pll1div, CLK_SRC_PLL1DIV, &pll1)
401DEFINE_ROOT_CLOCK(pll2div, CLK_SRC_PLL2DIV, &pll2)
402
403/* The following 3 clocks are special and are initialized explicitly later */
404DEFINE_SPECIAL_CLOCK(sys, get_rate_sys, NULL)
405DEFINE_SPECIAL_CLOCK(bus, get_rate_bus, &sys)
406DEFINE_SPECIAL_CLOCK(cpu, get_rate_cpu, &sys)
407
408DEFINE_ACLOCK(tct, NULL, 0, ACLKTCT)
409DEFINE_ACLOCK(tcx, NULL, 0, ACLKTCX)
410DEFINE_ACLOCK(tcz, NULL, 0, ACLKTCZ)
411DEFINE_ACLOCK(ref, NULL, 0, ACLKREF)
412DEFINE_ACLOCK(uart0, BCLKCTR0, 5, ACLKUART0)
413DEFINE_ACLOCK(uart1, BCLKCTR0, 23, ACLKUART1)
414DEFINE_ACLOCK(uart2, BCLKCTR0, 6, ACLKUART2)
415DEFINE_ACLOCK(uart3, BCLKCTR0, 8, ACLKUART3)
416DEFINE_ACLOCK(uart4, BCLKCTR1, 6, ACLKUART4)
417DEFINE_ACLOCK(i2c, BCLKCTR0, 7, ACLKI2C)
418DEFINE_ACLOCK(adc, BCLKCTR0, 10, ACLKADC)
419DEFINE_ACLOCK(usbh0, BCLKCTR0, 11, ACLKUSBH)
420DEFINE_ACLOCK(lcd, BCLKCTR0, 13, ACLKLCD)
421DEFINE_ACLOCK(sd0, BCLKCTR0, 17, ACLKSDH0)
422DEFINE_ACLOCK(sd1, BCLKCTR1, 5, ACLKSDH1)
423DEFINE_ACLOCK(spi0, BCLKCTR0, 24, ACLKSPI0)
424DEFINE_ACLOCK(spi1, BCLKCTR0, 30, ACLKSPI1)
425DEFINE_ACLOCK(spdif, BCLKCTR1, 2, ACLKSPDIF)
426DEFINE_ACLOCK(c3dec, BCLKCTR1, 9, ACLKC3DEC)
427DEFINE_ACLOCK(can0, BCLKCTR1, 10, ACLKCAN0)
428DEFINE_ACLOCK(can1, BCLKCTR1, 11, ACLKCAN1)
429DEFINE_ACLOCK(gsb0, BCLKCTR1, 13, ACLKGSB0)
430DEFINE_ACLOCK(gsb1, BCLKCTR1, 14, ACLKGSB1)
431DEFINE_ACLOCK(gsb2, BCLKCTR1, 15, ACLKGSB2)
432DEFINE_ACLOCK(gsb3, BCLKCTR1, 16, ACLKGSB3)
433DEFINE_ACLOCK(usbh1, BCLKCTR1, 20, ACLKUSBH)
434
435DEFINE_BCLOCK(dai0, BCLKCTR0, 0, NULL, NULL)
436DEFINE_BCLOCK(pic, BCLKCTR0, 1, NULL, NULL)
437DEFINE_BCLOCK(tc, BCLKCTR0, 2, NULL, NULL)
438DEFINE_BCLOCK(gpio, BCLKCTR0, 3, NULL, NULL)
439DEFINE_BCLOCK(usbd, BCLKCTR0, 4, NULL, NULL)
440DEFINE_BCLOCK(ecc, BCLKCTR0, 9, NULL, NULL)
441DEFINE_BCLOCK(gdma0, BCLKCTR0, 12, NULL, NULL)
442DEFINE_BCLOCK(rtc, BCLKCTR0, 15, NULL, NULL)
443DEFINE_BCLOCK(nfc, BCLKCTR0, 16, NULL, NULL)
444DEFINE_BCLOCK(g2d, BCLKCTR0, 18, NULL, NULL)
445DEFINE_BCLOCK(gdma1, BCLKCTR0, 22, NULL, NULL)
446DEFINE_BCLOCK(mscl, BCLKCTR0, 25, NULL, NULL)
447DEFINE_BCLOCK(bdma, BCLKCTR1, 0, NULL, NULL)
448DEFINE_BCLOCK(adma0, BCLKCTR1, 1, NULL, NULL)
449DEFINE_BCLOCK(scfg, BCLKCTR1, 3, NULL, NULL)
450DEFINE_BCLOCK(cid, BCLKCTR1, 4, NULL, NULL)
451DEFINE_BCLOCK(dai1, BCLKCTR1, 7, NULL, NULL)
452DEFINE_BCLOCK(adma1, BCLKCTR1, 8, NULL, NULL)
453DEFINE_BCLOCK(gps, BCLKCTR1, 12, NULL, NULL)
454DEFINE_BCLOCK(gdma2, BCLKCTR1, 17, NULL, NULL)
455DEFINE_BCLOCK(gdma3, BCLKCTR1, 18, NULL, NULL)
456DEFINE_BCLOCK(ddrc, BCLKCTR1, 19, NULL, NULL)
457
458#define _REGISTER_CLOCK(d, n, c) \
459 { \
460 .dev_id = d, \
461 .con_id = n, \
462 .clk = &c, \
463 },
464
465static struct clk_lookup lookups[] = {
466 _REGISTER_CLOCK(NULL, "bus", bus)
467 _REGISTER_CLOCK(NULL, "cpu", cpu)
468 _REGISTER_CLOCK(NULL, "tct", tct)
469 _REGISTER_CLOCK(NULL, "tcx", tcx)
470 _REGISTER_CLOCK(NULL, "tcz", tcz)
471 _REGISTER_CLOCK(NULL, "ref", ref)
472 _REGISTER_CLOCK(NULL, "dai0", dai0)
473 _REGISTER_CLOCK(NULL, "pic", pic)
474 _REGISTER_CLOCK(NULL, "tc", tc)
475 _REGISTER_CLOCK(NULL, "gpio", gpio)
476 _REGISTER_CLOCK(NULL, "usbd", usbd)
477 _REGISTER_CLOCK("tcc-uart.0", NULL, uart0)
478 _REGISTER_CLOCK("tcc-uart.2", NULL, uart2)
479 _REGISTER_CLOCK("tcc-i2c", NULL, i2c)
480 _REGISTER_CLOCK("tcc-uart.3", NULL, uart3)
481 _REGISTER_CLOCK(NULL, "ecc", ecc)
482 _REGISTER_CLOCK(NULL, "adc", adc)
483 _REGISTER_CLOCK("tcc-usbh.0", "usb", usbh0)
484 _REGISTER_CLOCK(NULL, "gdma0", gdma0)
485 _REGISTER_CLOCK(NULL, "lcd", lcd)
486 _REGISTER_CLOCK(NULL, "rtc", rtc)
487 _REGISTER_CLOCK(NULL, "nfc", nfc)
488 _REGISTER_CLOCK("tcc-mmc.0", NULL, sd0)
489 _REGISTER_CLOCK(NULL, "g2d", g2d)
490 _REGISTER_CLOCK(NULL, "gdma1", gdma1)
491 _REGISTER_CLOCK("tcc-uart.1", NULL, uart1)
492 _REGISTER_CLOCK("tcc-spi.0", NULL, spi0)
493 _REGISTER_CLOCK(NULL, "mscl", mscl)
494 _REGISTER_CLOCK("tcc-spi.1", NULL, spi1)
495 _REGISTER_CLOCK(NULL, "bdma", bdma)
496 _REGISTER_CLOCK(NULL, "adma0", adma0)
497 _REGISTER_CLOCK(NULL, "spdif", spdif)
498 _REGISTER_CLOCK(NULL, "scfg", scfg)
499 _REGISTER_CLOCK(NULL, "cid", cid)
500 _REGISTER_CLOCK("tcc-mmc.1", NULL, sd1)
501 _REGISTER_CLOCK("tcc-uart.4", NULL, uart4)
502 _REGISTER_CLOCK(NULL, "dai1", dai1)
503 _REGISTER_CLOCK(NULL, "adma1", adma1)
504 _REGISTER_CLOCK(NULL, "c3dec", c3dec)
505 _REGISTER_CLOCK("tcc-can.0", NULL, can0)
506 _REGISTER_CLOCK("tcc-can.1", NULL, can1)
507 _REGISTER_CLOCK(NULL, "gps", gps)
508 _REGISTER_CLOCK("tcc-gsb.0", NULL, gsb0)
509 _REGISTER_CLOCK("tcc-gsb.1", NULL, gsb1)
510 _REGISTER_CLOCK("tcc-gsb.2", NULL, gsb2)
511 _REGISTER_CLOCK("tcc-gsb.3", NULL, gsb3)
512 _REGISTER_CLOCK(NULL, "gdma2", gdma2)
513 _REGISTER_CLOCK(NULL, "gdma3", gdma3)
514 _REGISTER_CLOCK(NULL, "ddrc", ddrc)
515 _REGISTER_CLOCK("tcc-usbh.1", "usb", usbh1)
516};
517
518static struct clk *root_clk_by_index(enum root_clks src)
519{
520 switch (src) {
521 case CLK_SRC_PLL0: return &pll0;
522 case CLK_SRC_PLL1: return &pll1;
523 case CLK_SRC_PLL2: return &pll2;
524 case CLK_SRC_PLL0DIV: return &pll0div;
525 case CLK_SRC_PLL1DIV: return &pll1div;
526 case CLK_SRC_PLL2DIV: return &pll2div;
527 case CLK_SRC_XI: return &xi;
528 case CLK_SRC_XTI: return &xti;
529 case CLK_SRC_XIDIV: return &xidiv;
530 case CLK_SRC_XTIDIV: return &xtidiv;
531 default: return NULL;
532 }
533}
534
535static void find_aclk_parent(struct clk *clk)
536{
537 unsigned int src;
538 struct clk *clock;
539
540 if (!clk->aclkreg)
541 return;
542
543 src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
544 src &= CLK_SRC_MASK;
545
546 clock = root_clk_by_index(src);
547 if (!clock)
548 return;
549
550 clk->parent = clock;
551 clk->set_parent = aclk_set_parent;
552}
553
554void __init tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq)
555{
556 int i;
557
558 xi_rate = xi_freq;
559 xti_rate = xti_freq;
560
561 /* fixup parents and add the clock */
562 for (i = 0; i < ARRAY_SIZE(lookups); i++) {
563 find_aclk_parent(lookups[i].clk);
564 clkdev_add(&lookups[i]);
565 }
566 tcc8k_timer_init(&tcz, (void __iomem *)TIMER_BASE, INT_TC32);
567}
diff --git a/arch/arm/mach-tcc8k/common.h b/arch/arm/mach-tcc8k/common.h
new file mode 100644
index 000000000000..705690add395
--- /dev/null
+++ b/arch/arm/mach-tcc8k/common.h
@@ -0,0 +1,15 @@
1#ifndef MACH_TCC8K_COMMON_H
2#define MACH_TCC8K_COMMON_H
3
4#include <linux/platform_device.h>
5
6extern struct platform_device tcc_nand_device;
7
8struct clk;
9
10extern void tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq);
11extern void tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq);
12extern void tcc8k_init_irq(void);
13extern void tcc8k_map_common_io(void);
14
15#endif
diff --git a/arch/arm/mach-tcc8k/devices.c b/arch/arm/mach-tcc8k/devices.c
new file mode 100644
index 000000000000..6722ad7c2836
--- /dev/null
+++ b/arch/arm/mach-tcc8k/devices.c
@@ -0,0 +1,239 @@
1/*
2 * linux/arch/arm/mach-tcc8k/devices.c
3 *
4 * Copyright (C) Telechips, Inc.
5 * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
6 *
7 * Licensed under the terms of GPL v2.
8 *
9 */
10
11#include <linux/dma-mapping.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16
17#include <asm/mach/map.h>
18
19#include <mach/tcc8k-regs.h>
20#include <mach/irqs.h>
21
22#include "common.h"
23
24static u64 tcc8k_dmamask = DMA_BIT_MASK(32);
25
26#ifdef CONFIG_MTD_NAND_TCC
27/* NAND controller */
28static struct resource tcc_nand_resources[] = {
29 {
30 .start = (resource_size_t)NFC_BASE,
31 .end = (resource_size_t)NFC_BASE + 0x7f,
32 .flags = IORESOURCE_MEM,
33 }, {
34 .start = INT_NFC,
35 .end = INT_NFC,
36 .flags = IORESOURCE_IRQ,
37 },
38};
39
40struct platform_device tcc_nand_device = {
41 .name = "tcc_nand",
42 .id = 0,
43 .num_resources = ARRAY_SIZE(tcc_nand_resources),
44 .resource = tcc_nand_resources,
45};
46#endif
47
48#ifdef CONFIG_MMC_TCC8K
49/* MMC controller */
50static struct resource tcc8k_mmc0_resource[] = {
51 {
52 .start = INT_SD0,
53 .end = INT_SD0,
54 .flags = IORESOURCE_IRQ,
55 },
56};
57
58static struct resource tcc8k_mmc1_resource[] = {
59 {
60 .start = INT_SD1,
61 .end = INT_SD1,
62 .flags = IORESOURCE_IRQ,
63 },
64};
65
66struct platform_device tcc8k_mmc0_device = {
67 .name = "tcc-mmc",
68 .id = 0,
69 .num_resources = ARRAY_SIZE(tcc8k_mmc0_resource),
70 .resource = tcc8k_mmc0_resource,
71 .dev = {
72 .dma_mask = &tcc8k_dmamask,
73 .coherent_dma_mask = DMA_BIT_MASK(32),
74 }
75};
76
77struct platform_device tcc8k_mmc1_device = {
78 .name = "tcc-mmc",
79 .id = 1,
80 .num_resources = ARRAY_SIZE(tcc8k_mmc1_resource),
81 .resource = tcc8k_mmc1_resource,
82 .dev = {
83 .dma_mask = &tcc8k_dmamask,
84 .coherent_dma_mask = DMA_BIT_MASK(32),
85 }
86};
87
88static inline void tcc8k_init_mmc(void)
89{
90 u32 reg = __raw_readl(GPIOPS_BASE + GPIOPS_FS1_OFFS);
91
92 reg |= GPIOPS_FS1_SDH0_BITS | GPIOPS_FS1_SDH1_BITS;
93 __raw_writel(reg, GPIOPS_BASE + GPIOPS_FS1_OFFS);
94
95 platform_device_register(&tcc8k_mmc0_device);
96 platform_device_register(&tcc8k_mmc1_device);
97}
98#else
99static inline void tcc8k_init_mmc(void) { }
100#endif
101
102#ifdef CONFIG_USB_OHCI_HCD
103static int tcc8k_ohci_init(struct device *dev)
104{
105 u32 reg;
106
107 /* Use GPIO PK19 as VBUS control output */
108 reg = __raw_readl(GPIOPK_BASE + GPIOPK_FS0_OFFS);
109 reg &= ~(1 << 19);
110 __raw_writel(reg, GPIOPK_BASE + GPIOPK_FS0_OFFS);
111 reg = __raw_readl(GPIOPK_BASE + GPIOPK_FS1_OFFS);
112 reg &= ~(1 << 19);
113 __raw_writel(reg, GPIOPK_BASE + GPIOPK_FS1_OFFS);
114
115 reg = __raw_readl(GPIOPK_BASE + GPIOPK_DOE_OFFS);
116 reg |= (1 << 19);
117 __raw_writel(reg, GPIOPK_BASE + GPIOPK_DOE_OFFS);
118 /* Turn on VBUS */
119 reg = __raw_readl(GPIOPK_BASE + GPIOPK_DAT_OFFS);
120 reg |= (1 << 19);
121 __raw_writel(reg, GPIOPK_BASE + GPIOPK_DAT_OFFS);
122
123 return 0;
124}
125
126static struct resource tcc8k_ohci0_resources[] = {
127 [0] = {
128 .start = (resource_size_t)USBH0_BASE,
129 .end = (resource_size_t)USBH0_BASE + 0x5c,
130 .flags = IORESOURCE_MEM,
131 },
132 [1] = {
133 .start = INT_USBH0,
134 .end = INT_USBH0,
135 .flags = IORESOURCE_IRQ,
136 }
137};
138
139static struct resource tcc8k_ohci1_resources[] = {
140 [0] = {
141 .start = (resource_size_t)USBH1_BASE,
142 .end = (resource_size_t)USBH1_BASE + 0x5c,
143 .flags = IORESOURCE_MEM,
144 },
145 [1] = {
146 .start = INT_USBH1,
147 .end = INT_USBH1,
148 .flags = IORESOURCE_IRQ,
149 }
150};
151
152static struct tccohci_platform_data tcc8k_ohci0_platform_data = {
153 .controller = 0,
154 .port_mode = PMM_PERPORT_MODE,
155 .init = tcc8k_ohci_init,
156};
157
158static struct tccohci_platform_data tcc8k_ohci1_platform_data = {
159 .controller = 1,
160 .port_mode = PMM_PERPORT_MODE,
161 .init = tcc8k_ohci_init,
162};
163
164static struct platform_device ohci0_device = {
165 .name = "tcc-ohci",
166 .id = 0,
167 .dev = {
168 .dma_mask = &tcc8k_dmamask,
169 .coherent_dma_mask = DMA_BIT_MASK(32),
170 .platform_data = &tcc8k_ohci0_platform_data,
171 },
172 .num_resources = ARRAY_SIZE(tcc8k_ohci0_resources),
173 .resource = tcc8k_ohci0_resources,
174};
175
176static struct platform_device ohci1_device = {
177 .name = "tcc-ohci",
178 .id = 1,
179 .dev = {
180 .dma_mask = &tcc8k_dmamask,
181 .coherent_dma_mask = DMA_BIT_MASK(32),
182 .platform_data = &tcc8k_ohci1_platform_data,
183 },
184 .num_resources = ARRAY_SIZE(tcc8k_ohci1_resources),
185 .resource = tcc8k_ohci1_resources,
186};
187
188static void __init tcc8k_init_usbhost(void)
189{
190 platform_device_register(&ohci0_device);
191 platform_device_register(&ohci1_device);
192}
193#else
194static void __init tcc8k_init_usbhost(void) { }
195#endif
196
197/* USB device controller*/
198#ifdef CONFIG_USB_GADGET_TCC8K
199static struct resource udc_resources[] = {
200 [0] = {
201 .start = INT_USBD,
202 .end = INT_USBD,
203 .flags = IORESOURCE_IRQ,
204 },
205 [1] = {
206 .start = INT_UDMA,
207 .end = INT_UDMA,
208 .flags = IORESOURCE_IRQ,
209 },
210};
211
212static struct platform_device tcc8k_udc_device = {
213 .name = "tcc-udc",
214 .id = 0,
215 .resource = udc_resources,
216 .num_resources = ARRAY_SIZE(udc_resources),
217 .dev = {
218 .dma_mask = &tcc8k_dmamask,
219 .coherent_dma_mask = DMA_BIT_MASK(32),
220 },
221};
222
223static void __init tcc8k_init_usb_gadget(void)
224{
225 platform_device_register(&tcc8k_udc_device);
226}
227#else
228static void __init tcc8k_init_usb_gadget(void) { }
229#endif /* CONFIG_USB_GADGET_TCC83X */
230
231static int __init tcc8k_init_devices(void)
232{
233 tcc8k_init_mmc();
234 tcc8k_init_usbhost();
235 tcc8k_init_usb_gadget();
236 return 0;
237}
238
239arch_initcall(tcc8k_init_devices);
diff --git a/arch/arm/mach-tcc8k/io.c b/arch/arm/mach-tcc8k/io.c
new file mode 100644
index 000000000000..9b39d7fa658f
--- /dev/null
+++ b/arch/arm/mach-tcc8k/io.c
@@ -0,0 +1,62 @@
1/*
2 * linux/arch/arm/mach-tcc8k/io.c
3 *
4 * (C) 2009 Hans J. Koch <hjk@linutronix.de>
5 *
6 * derived from TCC83xx io.c
7 * Copyright (C) Telechips, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/init.h>
15#include <linux/io.h>
16#include <linux/kernel.h>
17
18#include <asm/mach/map.h>
19
20#include <mach/tcc8k-regs.h>
21
22/*
23 * The machine specific code may provide the extra mapping besides the
24 * default mapping provided here.
25 */
26static struct map_desc tcc8k_io_desc[] __initdata = {
27 {
28 .virtual = (unsigned long)CS1_BASE_VIRT,
29 .pfn = __phys_to_pfn(CS1_BASE),
30 .length = CS1_SIZE,
31 .type = MT_DEVICE,
32 }, {
33 .virtual = (unsigned long)AHB_PERI_BASE_VIRT,
34 .pfn = __phys_to_pfn(AHB_PERI_BASE),
35 .length = AHB_PERI_SIZE,
36 .type = MT_DEVICE,
37 }, {
38 .virtual = (unsigned long)APB0_PERI_BASE_VIRT,
39 .pfn = __phys_to_pfn(APB0_PERI_BASE),
40 .length = APB0_PERI_SIZE,
41 .type = MT_DEVICE,
42 }, {
43 .virtual = (unsigned long)APB1_PERI_BASE_VIRT,
44 .pfn = __phys_to_pfn(APB1_PERI_BASE),
45 .length = APB1_PERI_SIZE,
46 .type = MT_DEVICE,
47 }, {
48 .virtual = (unsigned long)EXT_MEM_CTRL_BASE_VIRT,
49 .pfn = __phys_to_pfn(EXT_MEM_CTRL_BASE),
50 .length = EXT_MEM_CTRL_SIZE,
51 .type = MT_DEVICE,
52 },
53};
54
55/*
56 * Maps common IO regions for tcc8k.
57 *
58 */
59void __init tcc8k_map_common_io(void)
60{
61 iotable_init(tcc8k_io_desc, ARRAY_SIZE(tcc8k_io_desc));
62}
diff --git a/arch/arm/mach-tcc8k/irq.c b/arch/arm/mach-tcc8k/irq.c
new file mode 100644
index 000000000000..34575c4963f0
--- /dev/null
+++ b/arch/arm/mach-tcc8k/irq.c
@@ -0,0 +1,111 @@
1/*
2 * Copyright (C) Telechips, Inc.
3 * Copyright (C) 2009-2010 Hans J. Koch <hjk@linutronix.de>
4 *
5 * Licensed under the terms of the GNU GPL version 2.
6 */
7
8#include <linux/init.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11
12#include <asm/irq.h>
13#include <asm/mach/irq.h>
14
15#include <mach/tcc8k-regs.h>
16#include <mach/irqs.h>
17
18#include "common.h"
19
20/* Disable IRQ */
21static void tcc8000_mask_ack_irq0(unsigned int irq)
22{
23 PIC0_IEN &= ~(1 << irq);
24 PIC0_CREQ |= (1 << irq);
25}
26
27static void tcc8000_mask_ack_irq1(unsigned int irq)
28{
29 PIC1_IEN &= ~(1 << (irq - 32));
30 PIC1_CREQ |= (1 << (irq - 32));
31}
32
33static void tcc8000_mask_irq0(unsigned int irq)
34{
35 PIC0_IEN &= ~(1 << irq);
36}
37
38static void tcc8000_mask_irq1(unsigned int irq)
39{
40 PIC1_IEN &= ~(1 << (irq - 32));
41}
42
43static void tcc8000_ack_irq0(unsigned int irq)
44{
45 PIC0_CREQ |= (1 << irq);
46}
47
48static void tcc8000_ack_irq1(unsigned int irq)
49{
50 PIC1_CREQ |= (1 << (irq - 32));
51}
52
53/* Enable IRQ */
54static void tcc8000_unmask_irq0(unsigned int irq)
55{
56 PIC0_IEN |= (1 << irq);
57 PIC0_INTOEN |= (1 << irq);
58}
59
60static void tcc8000_unmask_irq1(unsigned int irq)
61{
62 PIC1_IEN |= (1 << (irq - 32));
63 PIC1_INTOEN |= (1 << (irq - 32));
64}
65
66static struct irq_chip tcc8000_irq_chip0 = {
67 .name = "tcc_irq0",
68 .mask = tcc8000_mask_irq0,
69 .ack = tcc8000_ack_irq0,
70 .mask_ack = tcc8000_mask_ack_irq0,
71 .unmask = tcc8000_unmask_irq0,
72};
73
74static struct irq_chip tcc8000_irq_chip1 = {
75 .name = "tcc_irq1",
76 .mask = tcc8000_mask_irq1,
77 .ack = tcc8000_ack_irq1,
78 .mask_ack = tcc8000_mask_ack_irq1,
79 .unmask = tcc8000_unmask_irq1,
80};
81
82void __init tcc8k_init_irq(void)
83{
84 int irqno;
85
86 /* Mask and clear all interrupts */
87 PIC0_IEN = 0x00000000;
88 PIC0_CREQ = 0xffffffff;
89 PIC1_IEN = 0x00000000;
90 PIC1_CREQ = 0xffffffff;
91
92 PIC0_MEN0 = 0x00000003;
93 PIC1_MEN1 = 0x00000003;
94 PIC1_MEN = 0x00000003;
95
96 /* let all IRQs be level triggered */
97 PIC0_TMODE = 0xffffffff;
98 PIC1_TMODE = 0xffffffff;
99 /* all IRQs are IRQs (not FIQs) */
100 PIC0_IRQSEL = 0xffffffff;
101 PIC1_IRQSEL = 0xffffffff;
102
103 for (irqno = 0; irqno < NR_IRQS; irqno++) {
104 if (irqno < 32)
105 set_irq_chip(irqno, &tcc8000_irq_chip0);
106 else
107 set_irq_chip(irqno, &tcc8000_irq_chip1);
108 set_irq_handler(irqno, handle_level_irq);
109 set_irq_flags(irqno, IRQF_VALID);
110 }
111}
diff --git a/arch/arm/mach-tcc8k/time.c b/arch/arm/mach-tcc8k/time.c
new file mode 100644
index 000000000000..78d06008841d
--- /dev/null
+++ b/arch/arm/mach-tcc8k/time.c
@@ -0,0 +1,149 @@
1/*
2 * TCC8000 system timer setup
3 *
4 * (C) 2009 Hans J. Koch <hjk@linutronix.de>
5 *
6 * Licensed under the terms of the GPL version 2.
7 *
8 */
9
10#include <linux/clk.h>
11#include <linux/clockchips.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/kernel.h>
17#include <linux/spinlock.h>
18
19#include <asm/mach/time.h>
20
21#include <mach/tcc8k-regs.h>
22#include <mach/irqs.h>
23
24#include "common.h"
25
26static void __iomem *timer_base;
27
28static cycle_t tcc_get_cycles(struct clocksource *cs)
29{
30 return __raw_readl(timer_base + TC32MCNT_OFFS);
31}
32
33static struct clocksource clocksource_tcc = {
34 .name = "tcc_tc32",
35 .rating = 200,
36 .read = tcc_get_cycles,
37 .mask = CLOCKSOURCE_MASK(32),
38 .shift = 28,
39 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
40};
41
42static int tcc_set_next_event(unsigned long evt,
43 struct clock_event_device *unused)
44{
45 unsigned long reg = __raw_readl(timer_base + TC32MCNT_OFFS);
46
47 __raw_writel(reg + evt, timer_base + TC32CMP0_OFFS);
48 return 0;
49}
50
51static void tcc_set_mode(enum clock_event_mode mode,
52 struct clock_event_device *evt)
53{
54 unsigned long tc32irq;
55
56 switch (mode) {
57 case CLOCK_EVT_MODE_ONESHOT:
58 tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
59 tc32irq |= TC32IRQ_IRQEN0;
60 __raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
61 break;
62 case CLOCK_EVT_MODE_SHUTDOWN:
63 case CLOCK_EVT_MODE_UNUSED:
64 tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
65 tc32irq &= ~TC32IRQ_IRQEN0;
66 __raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
67 break;
68 case CLOCK_EVT_MODE_PERIODIC:
69 case CLOCK_EVT_MODE_RESUME:
70 break;
71 }
72}
73
74static irqreturn_t tcc8k_timer_interrupt(int irq, void *dev_id)
75{
76 struct clock_event_device *evt = dev_id;
77
78 /* Acknowledge TC32 interrupt by reading TC32IRQ */
79 __raw_readl(timer_base + TC32IRQ_OFFS);
80
81 evt->event_handler(evt);
82
83 return IRQ_HANDLED;
84}
85
86static struct clock_event_device clockevent_tcc = {
87 .name = "tcc_timer1",
88 .features = CLOCK_EVT_FEAT_ONESHOT,
89 .shift = 32,
90 .set_mode = tcc_set_mode,
91 .set_next_event = tcc_set_next_event,
92 .rating = 200,
93};
94
95static struct irqaction tcc8k_timer_irq = {
96 .name = "TC32_timer",
97 .flags = IRQF_DISABLED | IRQF_TIMER,
98 .handler = tcc8k_timer_interrupt,
99 .dev_id = &clockevent_tcc,
100};
101
102static int __init tcc_clockevent_init(struct clk *clock)
103{
104 unsigned int c = clk_get_rate(clock);
105
106 clocksource_tcc.mult = clocksource_hz2mult(c,
107 clocksource_tcc.shift);
108 clocksource_register(&clocksource_tcc);
109
110 clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC,
111 clockevent_tcc.shift);
112 clockevent_tcc.max_delta_ns =
113 clockevent_delta2ns(0xfffffffe, &clockevent_tcc);
114 clockevent_tcc.min_delta_ns =
115 clockevent_delta2ns(0xff, &clockevent_tcc);
116
117 clockevent_tcc.cpumask = cpumask_of(0);
118
119 clockevents_register_device(&clockevent_tcc);
120
121 return 0;
122}
123
124void __init tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq)
125{
126 u32 reg;
127
128 timer_base = base;
129 tcc8k_timer_irq.irq = irq;
130
131 /* Enable clocks */
132 clk_enable(clock);
133
134 /* Initialize 32-bit timer */
135 reg = __raw_readl(timer_base + TC32EN_OFFS);
136 reg &= ~TC32EN_ENABLE; /* Disable timer */
137 __raw_writel(reg, timer_base + TC32EN_OFFS);
138 /* Free running timer, counting from 0 to 0xffffffff */
139 __raw_writel(0, timer_base + TC32EN_OFFS);
140 __raw_writel(0, timer_base + TC32LDV_OFFS);
141 reg = __raw_readl(timer_base + TC32IRQ_OFFS);
142 reg |= TC32IRQ_IRQEN0; /* irq at match with CMP0 */
143 __raw_writel(reg, timer_base + TC32IRQ_OFFS);
144
145 __raw_writel(TC32EN_ENABLE, timer_base + TC32EN_OFFS);
146
147 tcc_clockevent_init(clock);
148 setup_irq(irq, &tcc8k_timer_irq);
149}
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index 9e305de56be9..b9dbdb1289d0 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -115,8 +115,6 @@ static void __init tegra_harmony_init(void)
115 115
116MACHINE_START(HARMONY, "harmony") 116MACHINE_START(HARMONY, "harmony")
117 .boot_params = 0x00000100, 117 .boot_params = 0x00000100,
118 .phys_io = IO_APB_PHYS,
119 .io_pg_offst = ((IO_APB_VIRT) >> 18) & 0xfffc,
120 .fixup = tegra_harmony_fixup, 118 .fixup = tegra_harmony_fixup,
121 .init_irq = tegra_init_irq, 119 .init_irq = tegra_init_irq,
122 .init_machine = tegra_harmony_init, 120 .init_machine = tegra_harmony_init,
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
index 55a39564b43c..8ea3bffb4e00 100644
--- a/arch/arm/mach-tegra/include/mach/debug-macro.S
+++ b/arch/arm/mach-tegra/include/mach/debug-macro.S
@@ -20,24 +20,28 @@
20 20
21#include <mach/io.h> 21#include <mach/io.h>
22 22
23 .macro addruart,rx, tmp 23 .macro addruart, rp, rv
24 mrc p15, 0, \rx, c1, c0 24 ldreq \rp, =IO_APB_PHYS @ physical
25 tst \rx, #1 @ MMU enabled? 25 ldrne \rv, =IO_APB_VIRT @ virtual
26 ldreq \rx, =IO_APB_PHYS @ physical
27 ldrne \rx, =IO_APB_VIRT @ virtual
28#if defined(CONFIG_TEGRA_DEBUG_UART_NONE) 26#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
29#error "A debug UART must be selected in the kernel config to use DEBUG_LL" 27#error "A debug UART must be selected in the kernel config to use DEBUG_LL"
30#elif defined(CONFIG_TEGRA_DEBUG_UARTA) 28#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
31 orr \rx, \rx, #0x6000 29 orr \rp, \rp, #0x6000
30 orr \rv, \rv, #0x6000
32#elif defined(CONFIG_TEGRA_DEBUG_UARTB) 31#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
33 ldr \tmp, =0x6040 32 orr \rp, \rp, #0x6000
34 orr \rx, \rx, \tmp 33 orr \rp, \rp, #0x40
34 orr \rv, \rv, #0x6000
35 orr \rv, \rv, #0x40
35#elif defined(CONFIG_TEGRA_DEBUG_UARTC) 36#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
36 orr \rx, \rx, #0x6200 37 orr \rp, \rp, #0x6200
38 orr \rv, \rv, #0x6200
37#elif defined(CONFIG_TEGRA_DEBUG_UARTD) 39#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
38 orr \rx, \rx, #0x6300 40 orr \rp, \rp, #0x6300
41 orr \rv, \rv, #0x6300
39#elif defined(CONFIG_TEGRA_DEBUG_UARTE) 42#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
40 orr \rx, \rx, #0x6400 43 orr \rp, \rp, #0x6400
44 orr \rv, \rv, #0x6400
41#endif 45#endif
42 .endm 46 .endm
43 47
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
index 8b42dab79a70..e4a34a35a544 100644
--- a/arch/arm/mach-tegra/include/mach/smp.h
+++ b/arch/arm/mach-tegra/include/mach/smp.h
@@ -1,16 +1,8 @@
1#ifndef ASMARM_ARCH_SMP_H 1#ifndef ASMARM_ARCH_SMP_H
2#define ASMARM_ARCH_SMP_H 2#define ASMARM_ARCH_SMP_H
3 3
4
5#include <asm/hardware/gic.h> 4#include <asm/hardware/gic.h>
6 5#include <asm/smp_mpidr.h>
7#define hard_smp_processor_id() \
8 ({ \
9 unsigned int cpunum; \
10 __asm__("mrc p15, 0, %0, c0, c0, 5" \
11 : "=r" (cpunum)); \
12 cpunum &= 0x0F; \
13 })
14 6
15/* 7/*
16 * We use IRQ1 as the IPI 8 * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/mach-u300/include/mach/debug-macro.S
index 92c12420256f..df715707bead 100644
--- a/arch/arm/mach-u300/include/mach/debug-macro.S
+++ b/arch/arm/mach-u300/include/mach/debug-macro.S
@@ -10,13 +10,12 @@
10 */ 10 */
11#include <mach/hardware.h> 11#include <mach/hardware.h>
12 12
13 .macro addruart, rx, tmp 13 .macro addruart, rp, rv
14 /* If we move the address using MMU, use this. */ 14 /* If we move the address using MMU, use this. */
15 mrc p15, 0, \rx, c1, c0 15 ldr \rp, = U300_SLOW_PER_PHYS_BASE @ MMU off, physical address
16 tst \rx, #1 @ MMU enabled? 16 ldr \rv, = U300_SLOW_PER_VIRT_BASE @ MMU on, virtual address
17 ldreq \rx, = U300_SLOW_PER_PHYS_BASE @ MMU off, physical address 17 orr \rp, \rp, #0x00003000
18 ldrne \rx, = U300_SLOW_PER_VIRT_BASE @ MMU on, virtual address 18 orr \rv, \rv, #0x00003000
19 orr \rx, \rx, #0x00003000
20 .endm 19 .endm
21 20
22#include <asm/hardware/debug-pl01x.S> 21#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
index bfcda9820888..07c35a846424 100644
--- a/arch/arm/mach-u300/u300.c
+++ b/arch/arm/mach-u300/u300.c
@@ -61,8 +61,6 @@ static void __init u300_init_machine(void)
61 61
62MACHINE_START(U300, MACH_U300_STRING) 62MACHINE_START(U300, MACH_U300_STRING)
63 /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */ 63 /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
64 .phys_io = U300_AHB_PER_PHYS_BASE,
65 .io_pg_offst = ((U300_AHB_PER_VIRT_BASE) >> 18) & 0xfffc,
66 .boot_params = BOOT_PARAMS_OFFSET, 64 .boot_params = BOOT_PARAMS_OFFSET,
67 .map_io = u300_map_io, 65 .map_io = u300_map_io,
68 .reserve = u300_reserve, 66 .reserve = u300_reserve,
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 6625e5bbf4d6..2dd44a0b4615 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -21,9 +21,7 @@ config MACH_U8500_MOP
21 bool "U8500 Development platform" 21 bool "U8500 Development platform"
22 select UX500_SOC_DB8500 22 select UX500_SOC_DB8500
23 help 23 help
24 Include support for mop500 development platform 24 Include support for the mop500 development platform.
25 based on U8500 architecture. The platform is based
26 on early drop silicon version of 8500.
27 25
28config MACH_U5500 26config MACH_U5500
29 bool "U5500 Development platform" 27 bool "U5500 Development platform"
@@ -39,4 +37,18 @@ config UX500_DEBUG_UART
39 Choose the UART on which kernel low-level debug messages should be 37 Choose the UART on which kernel low-level debug messages should be
40 output. 38 output.
41 39
40config U5500_MODEM_IRQ
41 bool "Modem IRQ support"
42 depends on MACH_U5500
43 default y
44 help
45 Add support for handling IRQ:s from modem side
46
47config U5500_MBOX
48 bool "Mailbox support"
49 depends on MACH_U5500 && U5500_MODEM_IRQ
50 default y
51 help
52 Add support for U5500 mailbox communication with modem side
53
42endif 54endif
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 4556aea9c3c5..9e27a84433cb 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -4,8 +4,12 @@
4 4
5obj-y := clock.o cpu.o devices.o 5obj-y := clock.o cpu.o devices.o
6obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o devices-db5500.o 6obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o devices-db5500.o
7obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o 7obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o prcmu.o
8obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o 8obj-$(CONFIG_MACH_U8500_MOP) += board-mop500.o board-mop500-sdi.o
9obj-$(CONFIG_MACH_U5500) += board-u5500.o 9obj-$(CONFIG_MACH_U5500) += board-u5500.o
10obj-$(CONFIG_SMP) += platsmp.o headsmp.o 10obj-$(CONFIG_SMP) += platsmp.o headsmp.o
11obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
11obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o 12obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
13obj-$(CONFIG_REGULATOR_AB8500) += board-mop500-regulators.o
14obj-$(CONFIG_U5500_MODEM_IRQ) += modem_irq.o
15obj-$(CONFIG_U5500_MBOX) += mbox.o
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
new file mode 100644
index 000000000000..1187f1fc2e53
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -0,0 +1,101 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
6 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
7 *
8 * MOP500 board specific initialization for regulators
9 */
10#include <linux/kernel.h>
11#include <linux/regulator/machine.h>
12
13/* supplies to the display/camera */
14static struct regulator_init_data ab8500_vaux1_regulator = {
15 .constraints = {
16 .name = "V-DISPLAY",
17 .min_uV = 2500000,
18 .max_uV = 2900000,
19 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
20 REGULATOR_CHANGE_STATUS,
21 },
22};
23
24/* supplies to the on-board eMMC */
25static struct regulator_init_data ab8500_vaux2_regulator = {
26 .constraints = {
27 .name = "V-eMMC1",
28 .min_uV = 1100000,
29 .max_uV = 3300000,
30 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
31 REGULATOR_CHANGE_STATUS,
32 },
33};
34
35/* supply for VAUX3, supplies to SDcard slots */
36static struct regulator_init_data ab8500_vaux3_regulator = {
37 .constraints = {
38 .name = "V-MMC-SD",
39 .min_uV = 1100000,
40 .max_uV = 3300000,
41 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
42 REGULATOR_CHANGE_STATUS,
43 },
44};
45
46/* supply for tvout, gpadc, TVOUT LDO */
47static struct regulator_init_data ab8500_vtvout_init = {
48 .constraints = {
49 .name = "V-TVOUT",
50 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
51 },
52};
53
54/* supply for ab8500-vaudio, VAUDIO LDO */
55static struct regulator_init_data ab8500_vaudio_init = {
56 .constraints = {
57 .name = "V-AUD",
58 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
59 },
60};
61
62/* supply for v-anamic1 VAMic1-LDO */
63static struct regulator_init_data ab8500_vamic1_init = {
64 .constraints = {
65 .name = "V-AMIC1",
66 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
67 },
68};
69
70/* supply for v-amic2, VAMIC2 LDO, reuse constants for AMIC1 */
71static struct regulator_init_data ab8500_vamic2_init = {
72 .constraints = {
73 .name = "V-AMIC2",
74 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
75 },
76};
77
78/* supply for v-dmic, VDMIC LDO */
79static struct regulator_init_data ab8500_vdmic_init = {
80 .constraints = {
81 .name = "V-DMIC",
82 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
83 },
84};
85
86/* supply for v-intcore12, VINTCORE12 LDO */
87static struct regulator_init_data ab8500_vintcore_init = {
88 .constraints = {
89 .name = "V-INTCORE",
90 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
91 },
92};
93
94/* supply for U8500 CSI/DSI, VANA LDO */
95static struct regulator_init_data ab8500_vana_init = {
96 .constraints = {
97 .name = "V-CSI/DSI",
98 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
99 },
100};
101
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
new file mode 100644
index 000000000000..bac995665b58
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -0,0 +1,91 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Hanumath Prasad <hanumath.prasad@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/kernel.h>
9#include <linux/gpio.h>
10#include <linux/amba/bus.h>
11#include <linux/amba/mmci.h>
12#include <linux/mmc/host.h>
13#include <linux/platform_device.h>
14
15#include <plat/pincfg.h>
16#include <mach/devices.h>
17#include <mach/hardware.h>
18
19#include "pins-db8500.h"
20#include "board-mop500.h"
21
22static pin_cfg_t mop500_sdi_pins[] = {
23 /* SDI4 (on-board eMMC) */
24 GPIO197_MC4_DAT3,
25 GPIO198_MC4_DAT2,
26 GPIO199_MC4_DAT1,
27 GPIO200_MC4_DAT0,
28 GPIO201_MC4_CMD,
29 GPIO202_MC4_FBCLK,
30 GPIO203_MC4_CLK,
31 GPIO204_MC4_DAT7,
32 GPIO205_MC4_DAT6,
33 GPIO206_MC4_DAT5,
34 GPIO207_MC4_DAT4,
35};
36
37static pin_cfg_t mop500_sdi2_pins[] = {
38 /* SDI2 (POP eMMC) */
39 GPIO128_MC2_CLK,
40 GPIO129_MC2_CMD,
41 GPIO130_MC2_FBCLK,
42 GPIO131_MC2_DAT0,
43 GPIO132_MC2_DAT1,
44 GPIO133_MC2_DAT2,
45 GPIO134_MC2_DAT3,
46 GPIO135_MC2_DAT4,
47 GPIO136_MC2_DAT5,
48 GPIO137_MC2_DAT6,
49 GPIO138_MC2_DAT7,
50};
51
52/*
53 * SDI 2 (POP eMMC, not on DB8500ed)
54 */
55
56static struct mmci_platform_data mop500_sdi2_data = {
57 .ocr_mask = MMC_VDD_165_195,
58 .f_max = 100000000,
59 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
60 .gpio_cd = -1,
61 .gpio_wp = -1,
62};
63
64/*
65 * SDI 4 (on-board eMMC)
66 */
67
68static struct mmci_platform_data mop500_sdi4_data = {
69 .ocr_mask = MMC_VDD_29_30,
70 .f_max = 100000000,
71 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
72 MMC_CAP_MMC_HIGHSPEED,
73 .gpio_cd = -1,
74 .gpio_wp = -1,
75};
76
77void mop500_sdi_init(void)
78{
79 nmk_config_pins(mop500_sdi_pins, ARRAY_SIZE(mop500_sdi_pins));
80
81 u8500_sdi2_device.dev.platform_data = &mop500_sdi2_data;
82 u8500_sdi4_device.dev.platform_data = &mop500_sdi4_data;
83
84 if (!cpu_is_u8500ed()) {
85 nmk_config_pins(mop500_sdi2_pins, ARRAY_SIZE(mop500_sdi2_pins));
86 amba_device_register(&u8500_sdi2_device, &iomem_resource);
87 }
88
89 /* On-board eMMC */
90 amba_device_register(&u8500_sdi4_device, &iomem_resource);
91}
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 219ae0ca4eef..fcb587f825cc 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -28,8 +28,10 @@
28#include <mach/hardware.h> 28#include <mach/hardware.h>
29#include <mach/setup.h> 29#include <mach/setup.h>
30#include <mach/devices.h> 30#include <mach/devices.h>
31#include <mach/irqs.h>
31 32
32#include "pins-db8500.h" 33#include "pins-db8500.h"
34#include "board-mop500.h"
33 35
34static pin_cfg_t mop500_pins[] = { 36static pin_cfg_t mop500_pins[] = {
35 /* SSP0 */ 37 /* SSP0 */
@@ -69,9 +71,27 @@ static struct ab8500_platform_data ab8500_platdata = {
69 .irq_base = MOP500_AB8500_IRQ_BASE, 71 .irq_base = MOP500_AB8500_IRQ_BASE,
70}; 72};
71 73
72static struct spi_board_info u8500_spi_devices[] = { 74static struct resource ab8500_resources[] = {
75 [0] = {
76 .start = IRQ_AB8500,
77 .end = IRQ_AB8500,
78 .flags = IORESOURCE_IRQ
79 }
80};
81
82struct platform_device ab8500_device = {
83 .name = "ab8500-i2c",
84 .id = 0,
85 .dev = {
86 .platform_data = &ab8500_platdata,
87 },
88 .num_resources = 1,
89 .resource = ab8500_resources,
90};
91
92static struct spi_board_info ab8500_spi_devices[] = {
73 { 93 {
74 .modalias = "ab8500", 94 .modalias = "ab8500-spi",
75 .controller_data = &ab4500_chip_info, 95 .controller_data = &ab4500_chip_info,
76 .platform_data = &ab8500_platdata, 96 .platform_data = &ab8500_platdata,
77 .max_speed_hz = 12000000, 97 .max_speed_hz = 12000000,
@@ -157,14 +177,18 @@ static void __init u8500_init_machine(void)
157 177
158 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); 178 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
159 179
160 spi_register_board_info(u8500_spi_devices, 180 mop500_sdi_init();
161 ARRAY_SIZE(u8500_spi_devices)); 181
182 /* If HW is early drop (ED) or V1.0 then use SPI to access AB8500 */
183 if (cpu_is_u8500ed() || cpu_is_u8500v10())
184 spi_register_board_info(ab8500_spi_devices,
185 ARRAY_SIZE(ab8500_spi_devices));
186 else /* If HW is v.1.1 or later use I2C to access AB8500 */
187 platform_device_register(&ab8500_device);
162} 188}
163 189
164MACHINE_START(U8500, "ST-Ericsson MOP500 platform") 190MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
165 /* Maintainer: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> */ 191 /* Maintainer: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> */
166 .phys_io = U8500_UART2_BASE,
167 .io_pg_offst = (IO_ADDRESS(U8500_UART2_BASE) >> 18) & 0xfffc,
168 .boot_params = 0x100, 192 .boot_params = 0x100,
169 .map_io = u8500_map_io, 193 .map_io = u8500_map_io,
170 .init_irq = ux500_init_irq, 194 .init_irq = ux500_init_irq,
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
new file mode 100644
index 000000000000..2d240322fa6f
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -0,0 +1,12 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License (GPL) version 2
5 */
6
7#ifndef __BOARD_MOP500_H
8#define __BOARD_MOP500_H
9
10extern void mop500_sdi_init(void);
11
12#endif
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
index 4430e69cf538..1ca094a45e71 100644
--- a/arch/arm/mach-ux500/board-u5500.c
+++ b/arch/arm/mach-ux500/board-u5500.c
@@ -31,8 +31,6 @@ static void __init u5500_init_machine(void)
31} 31}
32 32
33MACHINE_START(U8500, "ST-Ericsson U5500 Platform") 33MACHINE_START(U8500, "ST-Ericsson U5500 Platform")
34 .phys_io = UX500_UART0_BASE,
35 .io_pg_offst = (IO_ADDRESS(UX500_UART0_BASE) >> 18) & 0xfffc,
36 .boot_params = 0x00000100, 34 .boot_params = 0x00000100,
37 .map_io = u5500_map_io, 35 .map_io = u5500_map_io,
38 .init_irq = ux500_init_irq, 36 .init_irq = ux500_init_irq,
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index e9278f6d67aa..2f87075e9d6f 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -14,6 +14,7 @@
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <mach/devices.h> 15#include <mach/devices.h>
16#include <mach/setup.h> 16#include <mach/setup.h>
17#include <mach/irqs.h>
17 18
18static struct map_desc u5500_io_desc[] __initdata = { 19static struct map_desc u5500_io_desc[] __initdata = {
19 __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K), 20 __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K),
@@ -24,6 +25,90 @@ static struct map_desc u5500_io_desc[] __initdata = {
24 __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K), 25 __IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K),
25}; 26};
26 27
28static struct resource mbox0_resources[] = {
29 {
30 .name = "mbox_peer",
31 .start = U5500_MBOX0_PEER_START,
32 .end = U5500_MBOX0_PEER_END,
33 .flags = IORESOURCE_MEM,
34 },
35 {
36 .name = "mbox_local",
37 .start = U5500_MBOX0_LOCAL_START,
38 .end = U5500_MBOX0_LOCAL_END,
39 .flags = IORESOURCE_MEM,
40 },
41 {
42 .name = "mbox_irq",
43 .start = MBOX_PAIR0_VIRT_IRQ,
44 .end = MBOX_PAIR0_VIRT_IRQ,
45 .flags = IORESOURCE_IRQ,
46 }
47};
48
49static struct resource mbox1_resources[] = {
50 {
51 .name = "mbox_peer",
52 .start = U5500_MBOX1_PEER_START,
53 .end = U5500_MBOX1_PEER_END,
54 .flags = IORESOURCE_MEM,
55 },
56 {
57 .name = "mbox_local",
58 .start = U5500_MBOX1_LOCAL_START,
59 .end = U5500_MBOX1_LOCAL_END,
60 .flags = IORESOURCE_MEM,
61 },
62 {
63 .name = "mbox_irq",
64 .start = MBOX_PAIR1_VIRT_IRQ,
65 .end = MBOX_PAIR1_VIRT_IRQ,
66 .flags = IORESOURCE_IRQ,
67 }
68};
69
70static struct resource mbox2_resources[] = {
71 {
72 .name = "mbox_peer",
73 .start = U5500_MBOX2_PEER_START,
74 .end = U5500_MBOX2_PEER_END,
75 .flags = IORESOURCE_MEM,
76 },
77 {
78 .name = "mbox_local",
79 .start = U5500_MBOX2_LOCAL_START,
80 .end = U5500_MBOX2_LOCAL_END,
81 .flags = IORESOURCE_MEM,
82 },
83 {
84 .name = "mbox_irq",
85 .start = MBOX_PAIR2_VIRT_IRQ,
86 .end = MBOX_PAIR2_VIRT_IRQ,
87 .flags = IORESOURCE_IRQ,
88 }
89};
90
91static struct platform_device mbox0_device = {
92 .id = 0,
93 .name = "mbox",
94 .resource = mbox0_resources,
95 .num_resources = ARRAY_SIZE(mbox0_resources),
96};
97
98static struct platform_device mbox1_device = {
99 .id = 1,
100 .name = "mbox",
101 .resource = mbox1_resources,
102 .num_resources = ARRAY_SIZE(mbox1_resources),
103};
104
105static struct platform_device mbox2_device = {
106 .id = 2,
107 .name = "mbox",
108 .resource = mbox2_resources,
109 .num_resources = ARRAY_SIZE(mbox2_resources),
110};
111
27static struct platform_device *u5500_platform_devs[] __initdata = { 112static struct platform_device *u5500_platform_devs[] __initdata = {
28 &u5500_gpio_devs[0], 113 &u5500_gpio_devs[0],
29 &u5500_gpio_devs[1], 114 &u5500_gpio_devs[1],
@@ -33,6 +118,9 @@ static struct platform_device *u5500_platform_devs[] __initdata = {
33 &u5500_gpio_devs[5], 118 &u5500_gpio_devs[5],
34 &u5500_gpio_devs[6], 119 &u5500_gpio_devs[6],
35 &u5500_gpio_devs[7], 120 &u5500_gpio_devs[7],
121 &mbox0_device,
122 &mbox1_device,
123 &mbox2_device,
36}; 124};
37 125
38void __init u5500_map_io(void) 126void __init u5500_map_io(void)
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index f21c444edd99..4acab7544b3c 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -38,10 +38,12 @@ static struct platform_device *platform_devs[] __initdata = {
38/* minimum static i/o mapping required to boot U8500 platforms */ 38/* minimum static i/o mapping required to boot U8500 platforms */
39static struct map_desc u8500_io_desc[] __initdata = { 39static struct map_desc u8500_io_desc[] __initdata = {
40 __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K), 40 __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
41 __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
41 __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K), 42 __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
42 __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K), 43 __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
43 __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K), 44 __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
44 __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K), 45 __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
46 __MEM_DEV_DESC(U8500_BOOT_ROM_BASE, SZ_1M),
45}; 47};
46 48
47static struct map_desc u8500ed_io_desc[] __initdata = { 49static struct map_desc u8500ed_io_desc[] __initdata = {
@@ -53,6 +55,69 @@ static struct map_desc u8500v1_io_desc[] __initdata = {
53 __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K), 55 __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
54}; 56};
55 57
58/*
59 * Functions to differentiate between later ASICs
60 * We look into the end of the ROM to locate the hardcoded ASIC ID.
61 * This is only needed to differentiate between minor revisions and
62 * process variants of an ASIC, the major revisions are encoded in
63 * the cpuid.
64 */
65#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOT_ROM_BASE + 0x1FFF4)
66#define U8500_ASIC_ID_LOC_V2 (U8500_BOOT_ROM_BASE + 0x1DBF4)
67#define U8500_ASIC_REV_ED 0x01
68#define U8500_ASIC_REV_V10 0xA0
69#define U8500_ASIC_REV_V11 0xA1
70#define U8500_ASIC_REV_V20 0xB0
71
72/**
73 * struct db8500_asic_id - fields of the ASIC ID
74 * @process: the manufacturing process, 0x40 is 40 nm
75 * 0x00 is "standard"
76 * @partnumber: hithereto 0x8500 for DB8500
77 * @revision: version code in the series
78 * This field definion is not formally defined but makes
79 * sense.
80 */
81struct db8500_asic_id {
82 u8 process;
83 u16 partnumber;
84 u8 revision;
85};
86
87/* This isn't going to change at runtime */
88static struct db8500_asic_id db8500_id;
89
90static void __init get_db8500_asic_id(void)
91{
92 u32 asicid;
93
94 if (cpu_is_u8500v1() || cpu_is_u8500ed())
95 asicid = readl(__io_address(U8500_ASIC_ID_LOC_ED_V1));
96 else if (cpu_is_u8500v2())
97 asicid = readl(__io_address(U8500_ASIC_ID_LOC_V2));
98 else
99 BUG();
100
101 db8500_id.process = (asicid >> 24);
102 db8500_id.partnumber = (asicid >> 16) & 0xFFFFU;
103 db8500_id.revision = asicid & 0xFFU;
104}
105
106bool cpu_is_u8500v10(void)
107{
108 return (db8500_id.revision == U8500_ASIC_REV_V10);
109}
110
111bool cpu_is_u8500v11(void)
112{
113 return (db8500_id.revision == U8500_ASIC_REV_V11);
114}
115
116bool cpu_is_u8500v20(void)
117{
118 return (db8500_id.revision == U8500_ASIC_REV_V20);
119}
120
56void __init u8500_map_io(void) 121void __init u8500_map_io(void)
57{ 122{
58 ux500_map_io(); 123 ux500_map_io();
@@ -63,6 +128,9 @@ void __init u8500_map_io(void)
63 iotable_init(u8500ed_io_desc, ARRAY_SIZE(u8500ed_io_desc)); 128 iotable_init(u8500ed_io_desc, ARRAY_SIZE(u8500ed_io_desc));
64 else 129 else
65 iotable_init(u8500v1_io_desc, ARRAY_SIZE(u8500v1_io_desc)); 130 iotable_init(u8500v1_io_desc, ARRAY_SIZE(u8500v1_io_desc));
131
132 /* Read out the ASIC ID as early as we can */
133 get_db8500_asic_id();
66} 134}
67 135
68/* 136/*
@@ -70,6 +138,20 @@ void __init u8500_map_io(void)
70 */ 138 */
71void __init u8500_init_devices(void) 139void __init u8500_init_devices(void)
72{ 140{
141 /* Display some ASIC boilerplate */
142 pr_info("DB8500: process: %02x, revision ID: 0x%02x\n",
143 db8500_id.process, db8500_id.revision);
144 if (cpu_is_u8500ed())
145 pr_info("DB8500: Early Drop (ED)\n");
146 else if (cpu_is_u8500v10())
147 pr_info("DB8500: version 1.0\n");
148 else if (cpu_is_u8500v11())
149 pr_info("DB8500: version 1.1\n");
150 else if (cpu_is_u8500v20())
151 pr_info("DB8500: version 2.0\n");
152 else
153 pr_warning("ASIC: UNKNOWN SILICON VERSION!\n");
154
73 ux500_init_devices(); 155 ux500_init_devices();
74 156
75 if (cpu_is_u8500ed()) 157 if (cpu_is_u8500ed())
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 9280d2561111..40032fecbc16 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -110,6 +110,82 @@ struct platform_device u8500_i2c4_device = {
110 .num_resources = ARRAY_SIZE(u8500_i2c4_resources), 110 .num_resources = ARRAY_SIZE(u8500_i2c4_resources),
111}; 111};
112 112
113/*
114 * SD/MMC
115 */
116
117struct amba_device u8500_sdi0_device = {
118 .dev = {
119 .init_name = "sdi0",
120 },
121 .res = {
122 .start = U8500_SDI0_BASE,
123 .end = U8500_SDI0_BASE + SZ_4K - 1,
124 .flags = IORESOURCE_MEM,
125 },
126 .irq = {IRQ_DB8500_SDMMC0, NO_IRQ},
127};
128
129struct amba_device u8500_sdi1_device = {
130 .dev = {
131 .init_name = "sdi1",
132 },
133 .res = {
134 .start = U8500_SDI1_BASE,
135 .end = U8500_SDI1_BASE + SZ_4K - 1,
136 .flags = IORESOURCE_MEM,
137 },
138 .irq = {IRQ_DB8500_SDMMC1, NO_IRQ},
139};
140
141struct amba_device u8500_sdi2_device = {
142 .dev = {
143 .init_name = "sdi2",
144 },
145 .res = {
146 .start = U8500_SDI2_BASE,
147 .end = U8500_SDI2_BASE + SZ_4K - 1,
148 .flags = IORESOURCE_MEM,
149 },
150 .irq = {IRQ_DB8500_SDMMC2, NO_IRQ},
151};
152
153struct amba_device u8500_sdi3_device = {
154 .dev = {
155 .init_name = "sdi3",
156 },
157 .res = {
158 .start = U8500_SDI3_BASE,
159 .end = U8500_SDI3_BASE + SZ_4K - 1,
160 .flags = IORESOURCE_MEM,
161 },
162 .irq = {IRQ_DB8500_SDMMC3, NO_IRQ},
163};
164
165struct amba_device u8500_sdi4_device = {
166 .dev = {
167 .init_name = "sdi4",
168 },
169 .res = {
170 .start = U8500_SDI4_BASE,
171 .end = U8500_SDI4_BASE + SZ_4K - 1,
172 .flags = IORESOURCE_MEM,
173 },
174 .irq = {IRQ_DB8500_SDMMC4, NO_IRQ},
175};
176
177struct amba_device u8500_sdi5_device = {
178 .dev = {
179 .init_name = "sdi5",
180 },
181 .res = {
182 .start = U8500_SDI5_BASE,
183 .end = U8500_SDI5_BASE + SZ_4K - 1,
184 .flags = IORESOURCE_MEM,
185 },
186 .irq = {IRQ_DB8500_SDMMC5, NO_IRQ},
187};
188
113static struct resource dma40_resources[] = { 189static struct resource dma40_resources[] = {
114 [0] = { 190 [0] = {
115 .start = U8500_DMA_BASE, 191 .start = U8500_DMA_BASE,
@@ -170,23 +246,23 @@ struct stedma40_chan_cfg dma40_memcpy_conf_log = {
170 * Mapping between destination event lines and physical device address. 246 * Mapping between destination event lines and physical device address.
171 * The event line is tied to a device and therefor the address is constant. 247 * The event line is tied to a device and therefor the address is constant.
172 */ 248 */
173static const dma_addr_t dma40_tx_map[STEDMA40_NR_DEV]; 249static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV];
174 250
175/* Mapping between source event lines and physical device address */ 251/* Mapping between source event lines and physical device address */
176static const dma_addr_t dma40_rx_map[STEDMA40_NR_DEV]; 252static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV];
177 253
178/* Reserved event lines for memcpy only */ 254/* Reserved event lines for memcpy only */
179static int dma40_memcpy_event[] = { 255static int dma40_memcpy_event[] = {
180 STEDMA40_MEMCPY_TX_0, 256 DB8500_DMA_MEMCPY_TX_0,
181 STEDMA40_MEMCPY_TX_1, 257 DB8500_DMA_MEMCPY_TX_1,
182 STEDMA40_MEMCPY_TX_2, 258 DB8500_DMA_MEMCPY_TX_2,
183 STEDMA40_MEMCPY_TX_3, 259 DB8500_DMA_MEMCPY_TX_3,
184 STEDMA40_MEMCPY_TX_4, 260 DB8500_DMA_MEMCPY_TX_4,
185 STEDMA40_MEMCPY_TX_5, 261 DB8500_DMA_MEMCPY_TX_5,
186}; 262};
187 263
188static struct stedma40_platform_data dma40_plat_data = { 264static struct stedma40_platform_data dma40_plat_data = {
189 .dev_len = STEDMA40_NR_DEV, 265 .dev_len = DB8500_DMA_NR_DEV,
190 .dev_rx = dma40_rx_map, 266 .dev_rx = dma40_rx_map,
191 .dev_tx = dma40_tx_map, 267 .dev_tx = dma40_tx_map,
192 .memcpy = dma40_memcpy_event, 268 .memcpy = dma40_memcpy_event,
diff --git a/arch/arm/mach-ux500/hotplug.c b/arch/arm/mach-ux500/hotplug.c
new file mode 100644
index 000000000000..b782a03024be
--- /dev/null
+++ b/arch/arm/mach-ux500/hotplug.c
@@ -0,0 +1,75 @@
1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * License Terms: GNU General Public License v2
6 * Based on ARM realview platform
7 *
8 * Author: Sundar Iyer <sundar.iyer@stericsson.com>
9 *
10 */
11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/smp.h>
14#include <linux/completion.h>
15
16#include <asm/cacheflush.h>
17
18extern volatile int pen_release;
19
20static DECLARE_COMPLETION(cpu_killed);
21
22static inline void platform_do_lowpower(unsigned int cpu)
23{
24 flush_cache_all();
25
26 /* we put the platform to just WFI */
27 for (;;) {
28 __asm__ __volatile__("dsb\n\t" "wfi\n\t"
29 : : : "memory");
30 if (pen_release == cpu) {
31 /*
32 * OK, proper wakeup, we're done
33 */
34 break;
35 }
36 }
37}
38
39int platform_cpu_kill(unsigned int cpu)
40{
41 return wait_for_completion_timeout(&cpu_killed, 5000);
42}
43
44/*
45 * platform-specific code to shutdown a CPU
46 *
47 * Called with IRQs disabled
48 */
49void platform_cpu_die(unsigned int cpu)
50{
51#ifdef DEBUG
52 unsigned int this_cpu = hard_smp_processor_id();
53
54 if (cpu != this_cpu) {
55 printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
56 this_cpu, cpu);
57 BUG();
58 }
59#endif
60
61 printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
62 complete(&cpu_killed);
63
64 /* directly enter low power state, skipping secure registers */
65 platform_do_lowpower(cpu);
66}
67
68int platform_cpu_disable(unsigned int cpu)
69{
70 /*
71 * we don't allow CPU 0 to be shutdown (it is still too special
72 * e.g. clock tick interrupts)
73 */
74 return cpu == 0 ? -EPERM : 0;
75}
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
index 545c80fc8024..3eafc0e24ba5 100644
--- a/arch/arm/mach-ux500/include/mach/db5500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -100,4 +100,18 @@
100#define U5500_GPIOBANK6_BASE (U5500_GPIO4_BASE + 0x80) 100#define U5500_GPIOBANK6_BASE (U5500_GPIO4_BASE + 0x80)
101#define U5500_GPIOBANK7_BASE (U5500_GPIO4_BASE + 0x100) 101#define U5500_GPIOBANK7_BASE (U5500_GPIO4_BASE + 0x100)
102 102
103#define U5500_MBOX_BASE (U5500_MODEM_BASE + 0xFFD1000)
104#define U5500_MBOX0_PEER_START (U5500_MBOX_BASE + 0x40)
105#define U5500_MBOX0_PEER_END (U5500_MBOX_BASE + 0x5F)
106#define U5500_MBOX0_LOCAL_START (U5500_MBOX_BASE + 0x60)
107#define U5500_MBOX0_LOCAL_END (U5500_MBOX_BASE + 0x7F)
108#define U5500_MBOX1_PEER_START (U5500_MBOX_BASE + 0x80)
109#define U5500_MBOX1_PEER_END (U5500_MBOX_BASE + 0x9F)
110#define U5500_MBOX1_LOCAL_START (U5500_MBOX_BASE + 0xA0)
111#define U5500_MBOX1_LOCAL_END (U5500_MBOX_BASE + 0xBF)
112#define U5500_MBOX2_PEER_START (U5500_MBOX_BASE + 0x00)
113#define U5500_MBOX2_PEER_END (U5500_MBOX_BASE + 0x1F)
114#define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20)
115#define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F)
116
103#endif 117#endif
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index f000218210c9..f07d0986409d 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -30,8 +30,6 @@
30#define U8500_ICN_BASE 0x81000000 30#define U8500_ICN_BASE 0x81000000
31 31
32#define U8500_BOOT_ROM_BASE 0x90000000 32#define U8500_BOOT_ROM_BASE 0x90000000
33/* ASIC ID is at 0xff4 offset within this region */
34#define U8500_ASIC_ID_BASE 0x9001F000
35 33
36#define U8500_PER6_BASE 0xa03c0000 34#define U8500_PER6_BASE 0xa03c0000
37#define U8500_PER5_BASE 0xa03e0000 35#define U8500_PER5_BASE 0xa03e0000
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
index c5203b7ea552..be7c0f14e310 100644
--- a/arch/arm/mach-ux500/include/mach/debug-macro.S
+++ b/arch/arm/mach-ux500/include/mach/debug-macro.S
@@ -18,11 +18,9 @@
18#define UX500_UART(n) __UX500_UART(n) 18#define UX500_UART(n) __UX500_UART(n)
19#define UART_BASE UX500_UART(CONFIG_UX500_DEBUG_UART) 19#define UART_BASE UX500_UART(CONFIG_UX500_DEBUG_UART)
20 20
21 .macro addruart, rx, tmp 21 .macro addruart, rp, rv
22 mrc p15, 0, \rx, c1, c0 22 ldr \rp, =UART_BASE @ no, physical address
23 tst \rx, #1 @ MMU enabled? 23 ldr \rv, =IO_ADDRESS(UART_BASE) @ yes, virtual address
24 ldreq \rx, =UART_BASE @ no, physical address
25 ldrne \rx, =IO_ADDRESS(UART_BASE) @ yes, virtual address
26 .endm 24 .endm
27 25
28#include <asm/hardware/debug-pl01x.S> 26#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
index c2b2f2574947..33a120c2e82e 100644
--- a/arch/arm/mach-ux500/include/mach/devices.h
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -27,6 +27,13 @@ extern struct platform_device u8500_i2c0_device;
27extern struct platform_device u8500_i2c4_device; 27extern struct platform_device u8500_i2c4_device;
28extern struct platform_device u8500_dma40_device; 28extern struct platform_device u8500_dma40_device;
29 29
30extern struct amba_device u8500_sdi0_device;
31extern struct amba_device u8500_sdi1_device;
32extern struct amba_device u8500_sdi2_device;
33extern struct amba_device u8500_sdi3_device;
34extern struct amba_device u8500_sdi4_device;
35extern struct amba_device u8500_sdi5_device;
36
30void dma40_u8500ed_fixup(void); 37void dma40_u8500ed_fixup(void);
31 38
32#endif 39#endif
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index 8656379a8309..32e883a8f2a2 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -104,16 +104,35 @@ static inline bool cpu_is_u8500(void)
104#endif 104#endif
105} 105}
106 106
107#define CPUID_DB8500ED 0x410fc090
108#define CPUID_DB8500V1 0x411fc091
109#define CPUID_DB8500V2 0x412fc091
110
107static inline bool cpu_is_u8500ed(void) 111static inline bool cpu_is_u8500ed(void)
108{ 112{
109 return cpu_is_u8500() && (read_cpuid_id() & 15) == 0; 113 return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500ED);
110} 114}
111 115
112static inline bool cpu_is_u8500v1(void) 116static inline bool cpu_is_u8500v1(void)
113{ 117{
114 return cpu_is_u8500() && (read_cpuid_id() & 15) == 1; 118 return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500V1);
119}
120
121static inline bool cpu_is_u8500v2(void)
122{
123 return cpu_is_u8500() && (read_cpuid_id() == CPUID_DB8500V2);
115} 124}
116 125
126#ifdef CONFIG_UX500_SOC_DB8500
127bool cpu_is_u8500v10(void);
128bool cpu_is_u8500v11(void);
129bool cpu_is_u8500v20(void);
130#else
131static inline bool cpu_is_u8500v10(void) { return false; }
132static inline bool cpu_is_u8500v11(void) { return false; }
133static inline bool cpu_is_u8500v20(void) { return false; }
134#endif
135
117static inline bool cpu_is_u5500(void) 136static inline bool cpu_is_u5500(void)
118{ 137{
119#ifdef CONFIG_UX500_SOC_DB5500 138#ifdef CONFIG_UX500_SOC_DB5500
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
index 6fbfe5e2065a..bfa123dbec3b 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-db5500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
@@ -61,6 +61,7 @@
61#define IRQ_DB5500_SDMMC0 (IRQ_SHPI_START + 60) 61#define IRQ_DB5500_SDMMC0 (IRQ_SHPI_START + 60)
62#define IRQ_DB5500_HSEM (IRQ_SHPI_START + 61) 62#define IRQ_DB5500_HSEM (IRQ_SHPI_START + 61)
63#define IRQ_DB5500_SBAG (IRQ_SHPI_START + 63) 63#define IRQ_DB5500_SBAG (IRQ_SHPI_START + 63)
64#define IRQ_DB5500_MODEM (IRQ_SHPI_START + 65)
64#define IRQ_DB5500_SPI1 (IRQ_SHPI_START + 96) 65#define IRQ_DB5500_SPI1 (IRQ_SHPI_START + 96)
65#define IRQ_DB5500_MSP2 (IRQ_SHPI_START + 98) 66#define IRQ_DB5500_MSP2 (IRQ_SHPI_START + 98)
66#define IRQ_DB5500_SRPTIMER (IRQ_SHPI_START + 101) 67#define IRQ_DB5500_SRPTIMER (IRQ_SHPI_START + 101)
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 10385bdc2b77..693aa57de88d 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -40,7 +40,8 @@
40#define IRQ_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33) 40#define IRQ_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33)
41#define IRQ_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34) 41#define IRQ_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34)
42#define IRQ_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35) 42#define IRQ_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35)
43#define IRQ_AB4500 (IRQ_SHPI_START + 40) 43#define IRQ_AB8500 (IRQ_SHPI_START + 40)
44#define IRQ_PRCMU (IRQ_SHPI_START + 47)
44#define IRQ_DISP (IRQ_SHPI_START + 48) 45#define IRQ_DISP (IRQ_SHPI_START + 48)
45#define IRQ_SiPI3 (IRQ_SHPI_START + 49) 46#define IRQ_SiPI3 (IRQ_SHPI_START + 49)
46#define IRQ_I2C4 (IRQ_SHPI_START + 51) 47#define IRQ_I2C4 (IRQ_SHPI_START + 51)
@@ -83,6 +84,19 @@
83#include <mach/irqs-board-mop500.h> 84#include <mach/irqs-board-mop500.h>
84#endif 85#endif
85 86
86#define NR_IRQS IRQ_BOARD_END 87/*
88 * After the board specific IRQ:s we reserve a range of IRQ:s in which virtual
89 * IRQ:s representing modem IRQ:s can be allocated
90 */
91#define IRQ_MODEM_EVENTS_BASE (IRQ_BOARD_END + 1)
92#define IRQ_MODEM_EVENTS_NBR 72
93#define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR)
94
95/* List of virtual IRQ:s that are allocated from the range above */
96#define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43)
97#define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45)
98#define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41)
99
100#define NR_IRQS IRQ_MODEM_EVENTS_END
87 101
88#endif /* ASM_ARCH_IRQS_H */ 102#endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ux500/include/mach/mbox.h b/arch/arm/mach-ux500/include/mach/mbox.h
new file mode 100644
index 000000000000..7f9da4d2fbda
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/mbox.h
@@ -0,0 +1,88 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
4 * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8#ifndef __INC_STE_MBOX_H
9#define __INC_STE_MBOX_H
10
11#define MBOX_BUF_SIZE 16
12#define MBOX_NAME_SIZE 8
13
14/**
15 * mbox_recv_cb_t - Definition of the mailbox callback.
16 * @mbox_msg: The mailbox message.
17 * @priv: The clients private data as specified in the call to mbox_setup.
18 *
19 * This function will be called upon reception of new mailbox messages.
20 */
21typedef void mbox_recv_cb_t (u32 mbox_msg, void *priv);
22
23/**
24 * struct mbox - Mailbox instance struct
25 * @list: Linked list head.
26 * @pdev: Pointer to device struct.
27 * @cb: Callback function. Will be called
28 * when new data is received.
29 * @client_data: Clients private data. Will be sent back
30 * in the callback function.
31 * @virtbase_peer: Virtual address for outgoing mailbox.
32 * @virtbase_local: Virtual address for incoming mailbox.
33 * @buffer: Then internal queue for outgoing messages.
34 * @name: Name of this mailbox.
35 * @buffer_available: Completion variable to achieve "blocking send".
36 * This variable will be signaled when there is
37 * internal buffer space available.
38 * @client_blocked: To keep track if any client is currently
39 * blocked.
40 * @lock: Spinlock to protect this mailbox instance.
41 * @write_index: Index in internal buffer to write to.
42 * @read_index: Index in internal buffer to read from.
43 * @allocated: Indicates whether this particular mailbox
44 * id has been allocated by someone.
45 */
46struct mbox {
47 struct list_head list;
48 struct platform_device *pdev;
49 mbox_recv_cb_t *cb;
50 void *client_data;
51 void __iomem *virtbase_peer;
52 void __iomem *virtbase_local;
53 u32 buffer[MBOX_BUF_SIZE];
54 char name[MBOX_NAME_SIZE];
55 struct completion buffer_available;
56 u8 client_blocked;
57 spinlock_t lock;
58 u8 write_index;
59 u8 read_index;
60 bool allocated;
61};
62
63/**
64 * mbox_setup - Set up a mailbox and return its instance.
65 * @mbox_id: The ID number of the mailbox. 0 or 1 for modem CPU,
66 * 2 for modem DSP.
67 * @mbox_cb: Pointer to the callback function to be called when a new message
68 * is received.
69 * @priv: Client user data which will be returned in the callback.
70 *
71 * Returns a mailbox instance to be specified in subsequent calls to mbox_send.
72 */
73struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv);
74
75/**
76 * mbox_send - Send a mailbox message.
77 * @mbox: Mailbox instance (returned by mbox_setup)
78 * @mbox_msg: The mailbox message to send.
79 * @block: Specifies whether this call will block until send is possible,
80 * or return an error if the mailbox buffer is full.
81 *
82 * Returns 0 on success or a negative error code on error. -ENOMEM indicates
83 * that the internal buffer is full and you have to try again later (or
84 * specify "block" in order to block until send is possible).
85 */
86int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block);
87
88#endif /*INC_STE_MBOX_H*/
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
new file mode 100644
index 000000000000..8885f39a6421
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
@@ -0,0 +1,91 @@
1/*
2 * Copyright (c) 2009 ST-Ericsson SA
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2
6 * as published by the Free Software Foundation.
7 */
8#ifndef __MACH_PRCMU_REGS_H
9#define __MACH_PRCMU_REGS_H
10
11#include <mach/hardware.h>
12
13#define _PRCMU_BASE IO_ADDRESS(U8500_PRCMU_BASE)
14
15#define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118)
16#define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114)
17#define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98)
18#define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0)
19#define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4)
20#define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0)
21#define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c)
22#define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308)
23
24/* ARM WFI Standby signal register */
25#define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130)
26#define PRCMU_IOCR (_PRCMU_BASE + 0x310)
27
28/* CPU mailbox registers */
29#define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc)
30#define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100)
31#define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104)
32
33/* Dual A9 core interrupt management unit registers */
34#define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328)
35#define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c)
36#define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c)
37#define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120)
38#define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124)
39#define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128)
40#define PRCM_POWER_STATE_VAL (_PRCMU_BASE + 0x25C)
41#define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260)
42#define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264)
43#define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268)
44#define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C)
45
46#define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334)
47#define ARM_WAKEUP_MODEM 0x1
48
49#define PRCM_ARM_IT1_CLEAR (_PRCMU_BASE + 0x48C)
50#define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494)
51#define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174)
52
53#define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148)
54#define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150)
55#define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158)
56#define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160)
57#define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168)
58#define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484)
59#define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488)
60#define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018)
61
62/* System reset register */
63#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228)
64
65/* Level shifter and clamp control registers */
66#define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420)
67#define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424)
68
69/* PRCMU clock/PLL/reset registers */
70#define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500)
71#define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504)
72#define PRCM_LCDCLK_MGT (_PRCMU_BASE + 0x044)
73#define PRCM_MCDECLK_MGT (_PRCMU_BASE + 0x064)
74#define PRCM_HDMICLK_MGT (_PRCMU_BASE + 0x058)
75#define PRCM_TVCLK_MGT (_PRCMU_BASE + 0x07c)
76#define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530)
77#define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C)
78#define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4)
79#define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8)
80
81/* ePOD and memory power signal control registers */
82#define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410)
83#define PRCM_SRAM_LS_SLEEP (_PRCMU_BASE + 0x304)
84
85/* Debug power control unit registers */
86#define PRCM_POWER_STATE_SET (_PRCMU_BASE + 0x254)
87
88/* Miscellaneous unit registers */
89#define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324)
90
91#endif /* __MACH_PRCMU__REGS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h
new file mode 100644
index 000000000000..549843ff6dbe
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu.h
@@ -0,0 +1,15 @@
1/*
2 * Copyright (C) STMicroelectronics 2009
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * License Terms: GNU General Public License v2
6 *
7 * PRCMU f/w APIs
8 */
9#ifndef __MACH_PRCMU_H
10#define __MACH_PRCMU_H
11
12int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
13int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
14
15#endif /* __MACH_PRCMU_H */
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
index e978dbd9e210..54bbe648bf58 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -38,4 +38,11 @@ extern struct sys_timer ux500_timer;
38 .type = MT_DEVICE, \ 38 .type = MT_DEVICE, \
39} 39}
40 40
41#define __MEM_DEV_DESC(x, sz) { \
42 .virtual = IO_ADDRESS(x), \
43 .pfn = __phys_to_pfn(x), \
44 .length = sz, \
45 .type = MT_MEMORY, \
46}
47
41#endif /* __ASM_ARCH_SETUP_H */ 48#endif /* __ASM_ARCH_SETUP_H */
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
index b59f7bc9725d..197e8417375e 100644
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ b/arch/arm/mach-ux500/include/mach/smp.h
@@ -10,18 +10,11 @@
10#define ASMARM_ARCH_SMP_H 10#define ASMARM_ARCH_SMP_H
11 11
12#include <asm/hardware/gic.h> 12#include <asm/hardware/gic.h>
13#include <asm/smp_mpidr.h>
13 14
14/* This is required to wakeup the secondary core */ 15/* This is required to wakeup the secondary core */
15extern void u8500_secondary_startup(void); 16extern void u8500_secondary_startup(void);
16 17
17#define hard_smp_processor_id() \
18 ({ \
19 unsigned int cpunum; \
20 __asm__("mrc p15, 0, %0, c0, c0, 5" \
21 : "=r" (cpunum)); \
22 cpunum &= 0x0F; \
23 })
24
25/* 18/*
26 * We use IRQ1 as the IPI 19 * We use IRQ1 as the IPI
27 */ 20 */
diff --git a/arch/arm/mach-ux500/mbox.c b/arch/arm/mach-ux500/mbox.c
new file mode 100644
index 000000000000..63435389c544
--- /dev/null
+++ b/arch/arm/mach-ux500/mbox.c
@@ -0,0 +1,567 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
4 * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8/*
9 * Mailbox nomenclature:
10 *
11 * APE MODEM
12 * mbox pairX
13 * ..........................
14 * . .
15 * . peer .
16 * . send ---- .
17 * . --> | | .
18 * . | | .
19 * . ---- .
20 * . .
21 * . local .
22 * . rec ---- .
23 * . | | <-- .
24 * . | | .
25 * . ---- .
26 * .........................
27 */
28
29#include <linux/init.h>
30#include <linux/module.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/spinlock.h>
34#include <linux/errno.h>
35#include <linux/io.h>
36#include <linux/irq.h>
37#include <linux/platform_device.h>
38#include <linux/debugfs.h>
39#include <linux/seq_file.h>
40#include <linux/completion.h>
41#include <mach/mbox.h>
42
43#define MBOX_NAME "mbox"
44
45#define MBOX_FIFO_DATA 0x000
46#define MBOX_FIFO_ADD 0x004
47#define MBOX_FIFO_REMOVE 0x008
48#define MBOX_FIFO_THRES_FREE 0x00C
49#define MBOX_FIFO_THRES_OCCUP 0x010
50#define MBOX_FIFO_STATUS 0x014
51
52#define MBOX_DISABLE_IRQ 0x4
53#define MBOX_ENABLE_IRQ 0x0
54#define MBOX_LATCH 1
55
56/* Global list of all mailboxes */
57static struct list_head mboxs = LIST_HEAD_INIT(mboxs);
58
59static struct mbox *get_mbox_with_id(u8 id)
60{
61 u8 i;
62 struct list_head *pos = &mboxs;
63 for (i = 0; i <= id; i++)
64 pos = pos->next;
65
66 return (struct mbox *) list_entry(pos, struct mbox, list);
67}
68
69int mbox_send(struct mbox *mbox, u32 mbox_msg, bool block)
70{
71 int res = 0;
72
73 spin_lock(&mbox->lock);
74
75 dev_dbg(&(mbox->pdev->dev),
76 "About to buffer 0x%X to mailbox 0x%X."
77 " ri = %d, wi = %d\n",
78 mbox_msg, (u32)mbox, mbox->read_index,
79 mbox->write_index);
80
81 /* Check if write buffer is full */
82 while (((mbox->write_index + 1) % MBOX_BUF_SIZE) == mbox->read_index) {
83 if (!block) {
84 dev_dbg(&(mbox->pdev->dev),
85 "Buffer full in non-blocking call! "
86 "Returning -ENOMEM!\n");
87 res = -ENOMEM;
88 goto exit;
89 }
90 spin_unlock(&mbox->lock);
91 dev_dbg(&(mbox->pdev->dev),
92 "Buffer full in blocking call! Sleeping...\n");
93 mbox->client_blocked = 1;
94 wait_for_completion(&mbox->buffer_available);
95 dev_dbg(&(mbox->pdev->dev),
96 "Blocking send was woken up! Trying again...\n");
97 spin_lock(&mbox->lock);
98 }
99
100 mbox->buffer[mbox->write_index] = mbox_msg;
101 mbox->write_index = (mbox->write_index + 1) % MBOX_BUF_SIZE;
102
103 /*
104 * Indicate that we want an IRQ as soon as there is a slot
105 * in the FIFO
106 */
107 writel(MBOX_ENABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
108
109exit:
110 spin_unlock(&mbox->lock);
111 return res;
112}
113EXPORT_SYMBOL(mbox_send);
114
115#if defined(CONFIG_DEBUG_FS)
116/*
117 * Expected input: <value> <nbr sends>
118 * Example: "echo 0xdeadbeef 4 > mbox-node" sends 0xdeadbeef 4 times
119 */
120static ssize_t mbox_write_fifo(struct device *dev,
121 struct device_attribute *attr,
122 const char *buf,
123 size_t count)
124{
125 unsigned long mbox_mess;
126 unsigned long nbr_sends;
127 unsigned long i;
128 char int_buf[16];
129 char *token;
130 char *val;
131
132 struct mbox *mbox = (struct mbox *) dev->platform_data;
133
134 strncpy((char *) &int_buf, buf, sizeof(int_buf));
135 token = (char *) &int_buf;
136
137 /* Parse message */
138 val = strsep(&token, " ");
139 if ((val == NULL) || (strict_strtoul(val, 16, &mbox_mess) != 0))
140 mbox_mess = 0xDEADBEEF;
141
142 val = strsep(&token, " ");
143 if ((val == NULL) || (strict_strtoul(val, 10, &nbr_sends) != 0))
144 nbr_sends = 1;
145
146 dev_dbg(dev, "Will write 0x%lX %ld times using data struct at 0x%X\n",
147 mbox_mess, nbr_sends, (u32) mbox);
148
149 for (i = 0; i < nbr_sends; i++)
150 mbox_send(mbox, mbox_mess, true);
151
152 return count;
153}
154
155static ssize_t mbox_read_fifo(struct device *dev,
156 struct device_attribute *attr,
157 char *buf)
158{
159 int mbox_value;
160 struct mbox *mbox = (struct mbox *) dev->platform_data;
161
162 if ((readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7) <= 0)
163 return sprintf(buf, "Mailbox is empty\n");
164
165 mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA);
166 writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE));
167
168 return sprintf(buf, "0x%X\n", mbox_value);
169}
170
171static DEVICE_ATTR(fifo, S_IWUGO | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
172
173static int mbox_show(struct seq_file *s, void *data)
174{
175 struct list_head *pos;
176 u8 mbox_index = 0;
177
178 list_for_each(pos, &mboxs) {
179 struct mbox *m =
180 (struct mbox *) list_entry(pos, struct mbox, list);
181 if (m == NULL) {
182 seq_printf(s,
183 "Unable to retrieve mailbox %d\n",
184 mbox_index);
185 continue;
186 }
187
188 spin_lock(&m->lock);
189 if ((m->virtbase_peer == NULL) || (m->virtbase_local == NULL)) {
190 seq_printf(s, "MAILBOX %d not setup or corrupt\n",
191 mbox_index);
192 spin_unlock(&m->lock);
193 continue;
194 }
195
196 seq_printf(s,
197 "===========================\n"
198 " MAILBOX %d\n"
199 " PEER MAILBOX DUMP\n"
200 "---------------------------\n"
201 "FIFO: 0x%X (%d)\n"
202 "Free Threshold: 0x%.2X (%d)\n"
203 "Occupied Threshold: 0x%.2X (%d)\n"
204 "Status: 0x%.2X (%d)\n"
205 " Free spaces (ot): %d (%d)\n"
206 " Occup spaces (ot): %d (%d)\n"
207 "===========================\n"
208 " LOCAL MAILBOX DUMP\n"
209 "---------------------------\n"
210 "FIFO: 0x%.X (%d)\n"
211 "Free Threshold: 0x%.2X (%d)\n"
212 "Occupied Threshold: 0x%.2X (%d)\n"
213 "Status: 0x%.2X (%d)\n"
214 " Free spaces (ot): %d (%d)\n"
215 " Occup spaces (ot): %d (%d)\n"
216 "===========================\n"
217 "write_index: %d\n"
218 "read_index : %d\n"
219 "===========================\n"
220 "\n",
221 mbox_index,
222 readl(m->virtbase_peer + MBOX_FIFO_DATA),
223 readl(m->virtbase_peer + MBOX_FIFO_DATA),
224 readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE),
225 readl(m->virtbase_peer + MBOX_FIFO_THRES_FREE),
226 readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP),
227 readl(m->virtbase_peer + MBOX_FIFO_THRES_OCCUP),
228 readl(m->virtbase_peer + MBOX_FIFO_STATUS),
229 readl(m->virtbase_peer + MBOX_FIFO_STATUS),
230 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 4) & 0x7,
231 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 7) & 0x1,
232 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 0) & 0x7,
233 (readl(m->virtbase_peer + MBOX_FIFO_STATUS) >> 3) & 0x1,
234 readl(m->virtbase_local + MBOX_FIFO_DATA),
235 readl(m->virtbase_local + MBOX_FIFO_DATA),
236 readl(m->virtbase_local + MBOX_FIFO_THRES_FREE),
237 readl(m->virtbase_local + MBOX_FIFO_THRES_FREE),
238 readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP),
239 readl(m->virtbase_local + MBOX_FIFO_THRES_OCCUP),
240 readl(m->virtbase_local + MBOX_FIFO_STATUS),
241 readl(m->virtbase_local + MBOX_FIFO_STATUS),
242 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 4) & 0x7,
243 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 7) & 0x1,
244 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 0) & 0x7,
245 (readl(m->virtbase_local + MBOX_FIFO_STATUS) >> 3) & 0x1,
246 m->write_index, m->read_index);
247 mbox_index++;
248 spin_unlock(&m->lock);
249 }
250
251 return 0;
252}
253
254static int mbox_open(struct inode *inode, struct file *file)
255{
256 return single_open(file, mbox_show, NULL);
257}
258
259static const struct file_operations mbox_operations = {
260 .owner = THIS_MODULE,
261 .open = mbox_open,
262 .read = seq_read,
263 .llseek = seq_lseek,
264 .release = single_release,
265};
266#endif
267
268static irqreturn_t mbox_irq(int irq, void *arg)
269{
270 u32 mbox_value;
271 int nbr_occup;
272 int nbr_free;
273 struct mbox *mbox = (struct mbox *) arg;
274
275 spin_lock(&mbox->lock);
276
277 dev_dbg(&(mbox->pdev->dev),
278 "mbox IRQ [%d] received. ri = %d, wi = %d\n",
279 irq, mbox->read_index, mbox->write_index);
280
281 /*
282 * Check if we have any outgoing messages, and if there is space for
283 * them in the FIFO.
284 */
285 if (mbox->read_index != mbox->write_index) {
286 /*
287 * Check by reading FREE for LOCAL since that indicates
288 * OCCUP for PEER
289 */
290 nbr_free = (readl(mbox->virtbase_local + MBOX_FIFO_STATUS)
291 >> 4) & 0x7;
292 dev_dbg(&(mbox->pdev->dev),
293 "Status indicates %d empty spaces in the FIFO!\n",
294 nbr_free);
295
296 while ((nbr_free > 0) &&
297 (mbox->read_index != mbox->write_index)) {
298 /* Write the message and latch it into the FIFO */
299 writel(mbox->buffer[mbox->read_index],
300 (mbox->virtbase_peer + MBOX_FIFO_DATA));
301 writel(MBOX_LATCH,
302 (mbox->virtbase_peer + MBOX_FIFO_ADD));
303 dev_dbg(&(mbox->pdev->dev),
304 "Wrote message 0x%X to addr 0x%X\n",
305 mbox->buffer[mbox->read_index],
306 (u32) (mbox->virtbase_peer + MBOX_FIFO_DATA));
307
308 nbr_free--;
309 mbox->read_index =
310 (mbox->read_index + 1) % MBOX_BUF_SIZE;
311 }
312
313 /*
314 * Check if we still want IRQ:s when there is free
315 * space to send
316 */
317 if (mbox->read_index != mbox->write_index) {
318 dev_dbg(&(mbox->pdev->dev),
319 "Still have messages to send, but FIFO full. "
320 "Request IRQ again!\n");
321 writel(MBOX_ENABLE_IRQ,
322 mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
323 } else {
324 dev_dbg(&(mbox->pdev->dev),
325 "No more messages to send. "
326 "Do not request IRQ again!\n");
327 writel(MBOX_DISABLE_IRQ,
328 mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
329 }
330
331 /*
332 * Check if we can signal any blocked clients that it is OK to
333 * start buffering again
334 */
335 if (mbox->client_blocked &&
336 (((mbox->write_index + 1) % MBOX_BUF_SIZE)
337 != mbox->read_index)) {
338 dev_dbg(&(mbox->pdev->dev),
339 "Waking up blocked client\n");
340 complete(&mbox->buffer_available);
341 mbox->client_blocked = 0;
342 }
343 }
344
345 /* Check if we have any incoming messages */
346 nbr_occup = readl(mbox->virtbase_local + MBOX_FIFO_STATUS) & 0x7;
347 if (nbr_occup == 0)
348 goto exit;
349
350 if (mbox->cb == NULL) {
351 dev_dbg(&(mbox->pdev->dev), "No receive callback registered, "
352 "leaving %d incoming messages in fifo!\n", nbr_occup);
353 goto exit;
354 }
355
356 /* Read and acknowledge the message */
357 mbox_value = readl(mbox->virtbase_local + MBOX_FIFO_DATA);
358 writel(MBOX_LATCH, (mbox->virtbase_local + MBOX_FIFO_REMOVE));
359
360 /* Notify consumer of new mailbox message */
361 dev_dbg(&(mbox->pdev->dev), "Calling callback for message 0x%X!\n",
362 mbox_value);
363 mbox->cb(mbox_value, mbox->client_data);
364
365exit:
366 dev_dbg(&(mbox->pdev->dev), "Exit mbox IRQ. ri = %d, wi = %d\n",
367 mbox->read_index, mbox->write_index);
368 spin_unlock(&mbox->lock);
369
370 return IRQ_HANDLED;
371}
372
373/* Setup is executed once for each mbox pair */
374struct mbox *mbox_setup(u8 mbox_id, mbox_recv_cb_t *mbox_cb, void *priv)
375{
376 struct resource *resource;
377 int irq;
378 int res;
379 struct mbox *mbox;
380
381 mbox = get_mbox_with_id(mbox_id);
382 if (mbox == NULL) {
383 dev_err(&(mbox->pdev->dev), "Incorrect mailbox id: %d!\n",
384 mbox_id);
385 goto exit;
386 }
387
388 /*
389 * Check if mailbox has been allocated to someone else,
390 * otherwise allocate it
391 */
392 if (mbox->allocated) {
393 dev_err(&(mbox->pdev->dev), "Mailbox number %d is busy!\n",
394 mbox_id);
395 mbox = NULL;
396 goto exit;
397 }
398 mbox->allocated = true;
399
400 dev_dbg(&(mbox->pdev->dev), "Initiating mailbox number %d: 0x%X...\n",
401 mbox_id, (u32)mbox);
402
403 mbox->client_data = priv;
404 mbox->cb = mbox_cb;
405
406 /* Get addr for peer mailbox and ioremap it */
407 resource = platform_get_resource_byname(mbox->pdev,
408 IORESOURCE_MEM,
409 "mbox_peer");
410 if (resource == NULL) {
411 dev_err(&(mbox->pdev->dev),
412 "Unable to retrieve mbox peer resource\n");
413 mbox = NULL;
414 goto exit;
415 }
416 dev_dbg(&(mbox->pdev->dev),
417 "Resource name: %s start: 0x%X, end: 0x%X\n",
418 resource->name, resource->start, resource->end);
419 mbox->virtbase_peer =
420 ioremap(resource->start, resource->end - resource->start);
421 if (!mbox->virtbase_peer) {
422 dev_err(&(mbox->pdev->dev), "Unable to ioremap peer mbox\n");
423 mbox = NULL;
424 goto exit;
425 }
426 dev_dbg(&(mbox->pdev->dev),
427 "ioremapped peer physical: (0x%X-0x%X) to virtual: 0x%X\n",
428 resource->start, resource->end, (u32) mbox->virtbase_peer);
429
430 /* Get addr for local mailbox and ioremap it */
431 resource = platform_get_resource_byname(mbox->pdev,
432 IORESOURCE_MEM,
433 "mbox_local");
434 if (resource == NULL) {
435 dev_err(&(mbox->pdev->dev),
436 "Unable to retrieve mbox local resource\n");
437 mbox = NULL;
438 goto exit;
439 }
440 dev_dbg(&(mbox->pdev->dev),
441 "Resource name: %s start: 0x%X, end: 0x%X\n",
442 resource->name, resource->start, resource->end);
443 mbox->virtbase_local =
444 ioremap(resource->start, resource->end - resource->start);
445 if (!mbox->virtbase_local) {
446 dev_err(&(mbox->pdev->dev), "Unable to ioremap local mbox\n");
447 mbox = NULL;
448 goto exit;
449 }
450 dev_dbg(&(mbox->pdev->dev),
451 "ioremapped local physical: (0x%X-0x%X) to virtual: 0x%X\n",
452 resource->start, resource->end, (u32) mbox->virtbase_peer);
453
454 init_completion(&mbox->buffer_available);
455 mbox->client_blocked = 0;
456
457 /* Get IRQ for mailbox and allocate it */
458 irq = platform_get_irq_byname(mbox->pdev, "mbox_irq");
459 if (irq < 0) {
460 dev_err(&(mbox->pdev->dev),
461 "Unable to retrieve mbox irq resource\n");
462 mbox = NULL;
463 goto exit;
464 }
465
466 dev_dbg(&(mbox->pdev->dev), "Allocating irq %d...\n", irq);
467 res = request_irq(irq, mbox_irq, 0, mbox->name, (void *) mbox);
468 if (res < 0) {
469 dev_err(&(mbox->pdev->dev),
470 "Unable to allocate mbox irq %d\n", irq);
471 mbox = NULL;
472 goto exit;
473 }
474
475 /* Set up mailbox to not launch IRQ on free space in mailbox */
476 writel(MBOX_DISABLE_IRQ, mbox->virtbase_peer + MBOX_FIFO_THRES_FREE);
477
478 /*
479 * Set up mailbox to launch IRQ on new message if we have
480 * a callback set. If not, do not raise IRQ, but keep message
481 * in FIFO for manual retrieval
482 */
483 if (mbox_cb != NULL)
484 writel(MBOX_ENABLE_IRQ,
485 mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP);
486 else
487 writel(MBOX_DISABLE_IRQ,
488 mbox->virtbase_local + MBOX_FIFO_THRES_OCCUP);
489
490#if defined(CONFIG_DEBUG_FS)
491 res = device_create_file(&(mbox->pdev->dev), &dev_attr_fifo);
492 if (res != 0)
493 dev_warn(&(mbox->pdev->dev),
494 "Unable to create mbox sysfs entry");
495
496 (void) debugfs_create_file("mbox", S_IFREG | S_IRUGO, NULL,
497 NULL, &mbox_operations);
498#endif
499
500 dev_info(&(mbox->pdev->dev),
501 "Mailbox driver with index %d initated!\n", mbox_id);
502
503exit:
504 return mbox;
505}
506EXPORT_SYMBOL(mbox_setup);
507
508
509int __init mbox_probe(struct platform_device *pdev)
510{
511 struct mbox local_mbox;
512 struct mbox *mbox;
513 int res = 0;
514 dev_dbg(&(pdev->dev), "Probing mailbox (pdev = 0x%X)...\n", (u32) pdev);
515
516 memset(&local_mbox, 0x0, sizeof(struct mbox));
517
518 /* Associate our mbox data with the platform device */
519 res = platform_device_add_data(pdev,
520 (void *) &local_mbox,
521 sizeof(struct mbox));
522 if (res != 0) {
523 dev_err(&(pdev->dev),
524 "Unable to allocate driver platform data!\n");
525 goto exit;
526 }
527
528 mbox = (struct mbox *) pdev->dev.platform_data;
529 mbox->pdev = pdev;
530 mbox->write_index = 0;
531 mbox->read_index = 0;
532
533 INIT_LIST_HEAD(&(mbox->list));
534 list_add_tail(&(mbox->list), &mboxs);
535
536 sprintf(mbox->name, "%s", MBOX_NAME);
537 spin_lock_init(&mbox->lock);
538
539 dev_info(&(pdev->dev), "Mailbox driver loaded\n");
540
541exit:
542 return res;
543}
544
545static struct platform_driver mbox_driver = {
546 .driver = {
547 .name = MBOX_NAME,
548 .owner = THIS_MODULE,
549 },
550};
551
552static int __init mbox_init(void)
553{
554 return platform_driver_probe(&mbox_driver, mbox_probe);
555}
556
557module_init(mbox_init);
558
559void __exit mbox_exit(void)
560{
561 platform_driver_unregister(&mbox_driver);
562}
563
564module_exit(mbox_exit);
565
566MODULE_LICENSE("GPL");
567MODULE_DESCRIPTION("MBOX driver");
diff --git a/arch/arm/mach-ux500/modem_irq.c b/arch/arm/mach-ux500/modem_irq.c
new file mode 100644
index 000000000000..3187f8871169
--- /dev/null
+++ b/arch/arm/mach-ux500/modem_irq.c
@@ -0,0 +1,139 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 * Author: Stefan Nilsson <stefan.xk.nilsson@stericsson.com> for ST-Ericsson.
4 * Author: Martin Persson <martin.persson@stericsson.com> for ST-Ericsson.
5 * License terms: GNU General Public License (GPL), version 2.
6 */
7
8#include <linux/module.h>
9#include <linux/kernel.h>
10#include <linux/irq.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/slab.h>
14
15#define MODEM_INTCON_BASE_ADDR 0xBFFD3000
16#define MODEM_INTCON_SIZE 0xFFF
17
18#define DEST_IRQ41_OFFSET 0x2A4
19#define DEST_IRQ43_OFFSET 0x2AC
20#define DEST_IRQ45_OFFSET 0x2B4
21
22#define PRIO_IRQ41_OFFSET 0x6A4
23#define PRIO_IRQ43_OFFSET 0x6AC
24#define PRIO_IRQ45_OFFSET 0x6B4
25
26#define ALLOW_IRQ_OFFSET 0x104
27
28#define MODEM_INTCON_CPU_NBR 0x1
29#define MODEM_INTCON_PRIO_HIGH 0x0
30
31#define MODEM_INTCON_ALLOW_IRQ41 0x0200
32#define MODEM_INTCON_ALLOW_IRQ43 0x0800
33#define MODEM_INTCON_ALLOW_IRQ45 0x2000
34
35#define MODEM_IRQ_REG_OFFSET 0x4
36
37struct modem_irq {
38 void __iomem *modem_intcon_base;
39};
40
41
42static void setup_modem_intcon(void __iomem *modem_intcon_base)
43{
44 /* IC_DESTINATION_BASE_ARRAY - Which CPU to receive the IRQ */
45 writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ41_OFFSET);
46 writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ43_OFFSET);
47 writel(MODEM_INTCON_CPU_NBR, modem_intcon_base + DEST_IRQ45_OFFSET);
48
49 /* IC_PRIORITY_BASE_ARRAY - IRQ priority in modem IRQ controller */
50 writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ41_OFFSET);
51 writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ43_OFFSET);
52 writel(MODEM_INTCON_PRIO_HIGH, modem_intcon_base + PRIO_IRQ45_OFFSET);
53
54 /* IC_ALLOW_ARRAY - IRQ enable */
55 writel(MODEM_INTCON_ALLOW_IRQ41 |
56 MODEM_INTCON_ALLOW_IRQ43 |
57 MODEM_INTCON_ALLOW_IRQ45,
58 modem_intcon_base + ALLOW_IRQ_OFFSET);
59}
60
61static irqreturn_t modem_cpu_irq_handler(int irq, void *data)
62{
63 int real_irq;
64 int virt_irq;
65 struct modem_irq *mi = (struct modem_irq *)data;
66
67 /* Read modem side IRQ number from modem IRQ controller */
68 real_irq = readl(mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET) & 0xFF;
69 virt_irq = IRQ_MODEM_EVENTS_BASE + real_irq;
70
71 pr_debug("modem_irq: Worker read addr 0x%X and got value 0x%X "
72 "which will be 0x%X (%d) which translates to "
73 "virtual IRQ 0x%X (%d)!\n",
74 (u32)mi->modem_intcon_base + MODEM_IRQ_REG_OFFSET,
75 real_irq,
76 real_irq & 0xFF,
77 real_irq & 0xFF,
78 virt_irq,
79 virt_irq);
80
81 if (virt_irq != 0)
82 generic_handle_irq(virt_irq);
83
84 pr_debug("modem_irq: Done handling virtual IRQ %d!\n", virt_irq);
85
86 return IRQ_HANDLED;
87}
88
89static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip)
90{
91 set_irq_chip(irq, modem_irq_chip);
92 set_irq_handler(irq, handle_simple_irq);
93 set_irq_flags(irq, IRQF_VALID);
94
95 pr_debug("modem_irq: Created virtual IRQ %d\n", irq);
96}
97
98static int modem_irq_init(void)
99{
100 int err;
101 static struct irq_chip modem_irq_chip;
102 struct modem_irq *mi;
103
104 pr_info("modem_irq: Set up IRQ handler for incoming modem IRQ %d\n",
105 IRQ_DB5500_MODEM);
106
107 mi = kmalloc(sizeof(struct modem_irq), GFP_KERNEL);
108 if (!mi) {
109 pr_err("modem_irq: Could not allocate device\n");
110 return -ENOMEM;
111 }
112
113 mi->modem_intcon_base =
114 ioremap(MODEM_INTCON_BASE_ADDR, MODEM_INTCON_SIZE);
115 pr_debug("modem_irq: ioremapped modem_intcon_base from "
116 "phy 0x%x to virt 0x%x\n", MODEM_INTCON_BASE_ADDR,
117 (u32)mi->modem_intcon_base);
118
119 setup_modem_intcon(mi->modem_intcon_base);
120
121 modem_irq_chip = dummy_irq_chip;
122 modem_irq_chip.name = "modem_irq";
123
124 /* Create the virtual IRQ:s needed */
125 create_virtual_irq(MBOX_PAIR0_VIRT_IRQ, &modem_irq_chip);
126 create_virtual_irq(MBOX_PAIR1_VIRT_IRQ, &modem_irq_chip);
127 create_virtual_irq(MBOX_PAIR2_VIRT_IRQ, &modem_irq_chip);
128
129 err = request_threaded_irq(IRQ_DB5500_MODEM, NULL,
130 modem_cpu_irq_handler, IRQF_ONESHOT,
131 "modem_irq", mi);
132 if (err)
133 pr_err("modem_irq: Could not register IRQ %d\n",
134 IRQ_DB5500_MODEM);
135
136 return 0;
137}
138
139arch_initcall(modem_irq_init);
diff --git a/arch/arm/mach-ux500/pins-db5500.h b/arch/arm/mach-ux500/pins-db5500.h
new file mode 100644
index 000000000000..bf50c21fe69d
--- /dev/null
+++ b/arch/arm/mach-ux500/pins-db5500.h
@@ -0,0 +1,620 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
6 */
7
8#ifndef __MACH_DB5500_PINS_H
9#define __MACH_DB5500_PINS_H
10
11#define GPIO0_GPIO PIN_CFG(0, GPIO)
12#define GPIO0_SM_CS3n PIN_CFG(0, ALT_A)
13
14#define GPIO1_GPIO PIN_CFG(1, GPIO)
15#define GPIO1_SM_A3 PIN_CFG(1, ALT_A)
16
17#define GPIO2_GPIO PIN_CFG(2, GPIO)
18#define GPIO2_SM_A4 PIN_CFG(2, ALT_A)
19#define GPIO2_SM_AVD PIN_CFG(2, ALT_B)
20
21#define GPIO3_GPIO PIN_CFG(3, GPIO)
22#define GPIO3_I2C1_SCL PIN_CFG(3, ALT_A)
23
24#define GPIO4_GPIO PIN_CFG(4, GPIO)
25#define GPIO4_I2C1_SDA PIN_CFG(4, ALT_A)
26
27#define GPIO5_GPIO PIN_CFG(5, GPIO)
28#define GPIO5_MC0_DAT0 PIN_CFG(5, ALT_A)
29#define GPIO5_SM_ADQ8 PIN_CFG(5, ALT_B)
30
31#define GPIO6_GPIO PIN_CFG(6, GPIO)
32#define GPIO6_MC0_DAT1 PIN_CFG(6, ALT_A)
33#define GPIO6_SM_ADQ0 PIN_CFG(6, ALT_B)
34
35#define GPIO7_GPIO PIN_CFG(7, GPIO)
36#define GPIO7_MC0_DAT2 PIN_CFG(7, ALT_A)
37#define GPIO7_SM_ADQ9 PIN_CFG(7, ALT_B)
38
39#define GPIO8_GPIO PIN_CFG(8, GPIO)
40#define GPIO8_MC0_DAT3 PIN_CFG(8, ALT_A)
41#define GPIO8_SM_ADQ1 PIN_CFG(8, ALT_B)
42
43#define GPIO9_GPIO PIN_CFG(9, GPIO)
44#define GPIO9_MC0_DAT4 PIN_CFG(9, ALT_A)
45#define GPIO9_SM_ADQ10 PIN_CFG(9, ALT_B)
46
47#define GPIO10_GPIO PIN_CFG(10, GPIO)
48#define GPIO10_MC0_DAT5 PIN_CFG(10, ALT_A)
49#define GPIO10_SM_ADQ2 PIN_CFG(10, ALT_B)
50
51#define GPIO11_GPIO PIN_CFG(11, GPIO)
52#define GPIO11_MC0_DAT6 PIN_CFG(11, ALT_A)
53#define GPIO11_SM_ADQ11 PIN_CFG(11, ALT_B)
54
55#define GPIO12_GPIO PIN_CFG(12, GPIO)
56#define GPIO12_MC0_DAT7 PIN_CFG(12, ALT_A)
57#define GPIO12_SM_ADQ3 PIN_CFG(12, ALT_B)
58
59#define GPIO13_GPIO PIN_CFG(13, GPIO)
60#define GPIO13_MC0_CMD PIN_CFG(13, ALT_A)
61#define GPIO13_SM_BUSY0n PIN_CFG(13, ALT_B)
62#define GPIO13_SM_WAIT0n PIN_CFG(13, ALT_C)
63
64#define GPIO14_GPIO PIN_CFG(14, GPIO)
65#define GPIO14_MC0_CLK PIN_CFG(14, ALT_A)
66#define GPIO14_SM_CS1n PIN_CFG(14, ALT_B)
67#define GPIO14_SM_CKO PIN_CFG(14, ALT_C)
68
69#define GPIO15_GPIO PIN_CFG(15, GPIO)
70#define GPIO15_SM_A5 PIN_CFG(15, ALT_A)
71#define GPIO15_SM_CLE PIN_CFG(15, ALT_B)
72
73#define GPIO16_GPIO PIN_CFG(16, GPIO)
74#define GPIO16_MC2_CMD PIN_CFG(16, ALT_A)
75#define GPIO16_SM_OEn PIN_CFG(16, ALT_B)
76
77#define GPIO17_GPIO PIN_CFG(17, GPIO)
78#define GPIO17_MC2_CLK PIN_CFG(17, ALT_A)
79#define GPIO17_SM_WEn PIN_CFG(17, ALT_B)
80
81#define GPIO18_GPIO PIN_CFG(18, GPIO)
82#define GPIO18_SM_A6 PIN_CFG(18, ALT_A)
83#define GPIO18_SM_ALE PIN_CFG(18, ALT_B)
84#define GPIO18_SM_AVDn PIN_CFG(18, ALT_C)
85
86#define GPIO19_GPIO PIN_CFG(19, GPIO)
87#define GPIO19_MC2_DAT1 PIN_CFG(19, ALT_A)
88#define GPIO19_SM_ADQ4 PIN_CFG(19, ALT_B)
89
90#define GPIO20_GPIO PIN_CFG(20, GPIO)
91#define GPIO20_MC2_DAT3 PIN_CFG(20, ALT_A)
92#define GPIO20_SM_ADQ5 PIN_CFG(20, ALT_B)
93
94#define GPIO21_GPIO PIN_CFG(21, GPIO)
95#define GPIO21_MC2_DAT5 PIN_CFG(21, ALT_A)
96#define GPIO21_SM_ADQ6 PIN_CFG(21, ALT_B)
97
98#define GPIO22_GPIO PIN_CFG(22, GPIO)
99#define GPIO22_MC2_DAT7 PIN_CFG(22, ALT_A)
100#define GPIO22_SM_ADQ7 PIN_CFG(22, ALT_B)
101
102#define GPIO23_GPIO PIN_CFG(23, GPIO)
103#define GPIO23_MC2_DAT0 PIN_CFG(23, ALT_A)
104#define GPIO23_SM_ADQ12 PIN_CFG(23, ALT_B)
105#define GPIO23_MC0_DAT1 PIN_CFG(23, ALT_C)
106
107#define GPIO24_GPIO PIN_CFG(24, GPIO)
108#define GPIO24_MC2_DAT2 PIN_CFG(24, ALT_A)
109#define GPIO24_SM_ADQ13 PIN_CFG(24, ALT_B)
110#define GPIO24_MC0_DAT3 PIN_CFG(24, ALT_C)
111
112#define GPIO25_GPIO PIN_CFG(25, GPIO)
113#define GPIO25_MC2_DAT4 PIN_CFG(25, ALT_A)
114#define GPIO25_SM_ADQ14 PIN_CFG(25, ALT_B)
115#define GPIO25_MC0_CMD PIN_CFG(25, ALT_C)
116
117#define GPIO26_GPIO PIN_CFG(26, GPIO)
118#define GPIO26_MC2_DAT6 PIN_CFG(26, ALT_A)
119#define GPIO26_SM_ADQ15 PIN_CFG(26, ALT_B)
120
121#define GPIO27_GPIO PIN_CFG(27, GPIO)
122#define GPIO27_SM_CS0n PIN_CFG(27, ALT_A)
123#define GPIO27_SM_PS0n PIN_CFG(27, ALT_B)
124
125#define GPIO28_GPIO PIN_CFG(28, GPIO)
126#define GPIO28_U0_TXD PIN_CFG(28, ALT_A)
127#define GPIO28_SM_A0 PIN_CFG(28, ALT_B)
128
129#define GPIO29_GPIO PIN_CFG(29, GPIO)
130#define GPIO29_U0_RXD PIN_CFG(29, ALT_A)
131#define GPIO29_SM_A1 PIN_CFG(29, ALT_B)
132#define GPIO29_PWM_0 PIN_CFG(29, ALT_C)
133
134#define GPIO30_GPIO PIN_CFG(30, GPIO)
135#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A)
136#define GPIO30_SM_A2 PIN_CFG(30, ALT_B)
137#define GPIO30_PWM_1 PIN_CFG(30, ALT_C)
138
139#define GPIO31_GPIO PIN_CFG(31, GPIO)
140#define GPIO31_MC0_DAT7 PIN_CFG(31, ALT_A)
141#define GPIO31_SM_CS2n PIN_CFG(31, ALT_B)
142#define GPIO31_PWM_2 PIN_CFG(31, ALT_C)
143
144#define GPIO32_GPIO PIN_CFG(32, GPIO)
145#define GPIO32_MSP0_TCK PIN_CFG(32, ALT_A)
146#define GPIO32_ACCI2S0_SCK PIN_CFG(32, ALT_B)
147
148#define GPIO33_GPIO PIN_CFG(33, GPIO)
149#define GPIO33_MSP0_TFS PIN_CFG(33, ALT_A)
150#define GPIO33_ACCI2S0_WS PIN_CFG(33, ALT_B)
151
152#define GPIO34_GPIO PIN_CFG(34, GPIO)
153#define GPIO34_MSP0_TXD PIN_CFG(34, ALT_A)
154#define GPIO34_ACCI2S0_DLD PIN_CFG(34, ALT_B)
155
156#define GPIO35_GPIO PIN_CFG(35, GPIO)
157#define GPIO35_MSP0_RXD PIN_CFG(35, ALT_A)
158#define GPIO35_ACCI2S0_ULD PIN_CFG(35, ALT_B)
159
160#define GPIO64_GPIO PIN_CFG(64, GPIO)
161#define GPIO64_USB_DAT0 PIN_CFG(64, ALT_A)
162#define GPIO64_U0_TXD PIN_CFG(64, ALT_B)
163
164#define GPIO65_GPIO PIN_CFG(65, GPIO)
165#define GPIO65_USB_DAT1 PIN_CFG(65, ALT_A)
166#define GPIO65_U0_RXD PIN_CFG(65, ALT_B)
167
168#define GPIO66_GPIO PIN_CFG(66, GPIO)
169#define GPIO66_USB_DAT2 PIN_CFG(66, ALT_A)
170
171#define GPIO67_GPIO PIN_CFG(67, GPIO)
172#define GPIO67_USB_DAT3 PIN_CFG(67, ALT_A)
173
174#define GPIO68_GPIO PIN_CFG(68, GPIO)
175#define GPIO68_USB_DAT4 PIN_CFG(68, ALT_A)
176
177#define GPIO69_GPIO PIN_CFG(69, GPIO)
178#define GPIO69_USB_DAT5 PIN_CFG(69, ALT_A)
179
180#define GPIO70_GPIO PIN_CFG(70, GPIO)
181#define GPIO70_USB_DAT6 PIN_CFG(70, ALT_A)
182
183#define GPIO71_GPIO PIN_CFG(71, GPIO)
184#define GPIO71_USB_DAT7 PIN_CFG(71, ALT_A)
185
186#define GPIO72_GPIO PIN_CFG(72, GPIO)
187#define GPIO72_USB_STP PIN_CFG(72, ALT_A)
188
189#define GPIO73_GPIO PIN_CFG(73, GPIO)
190#define GPIO73_USB_DIR PIN_CFG(73, ALT_A)
191
192#define GPIO74_GPIO PIN_CFG(74, GPIO)
193#define GPIO74_USB_NXT PIN_CFG(74, ALT_A)
194
195#define GPIO75_GPIO PIN_CFG(75, GPIO)
196#define GPIO75_USB_XCLK PIN_CFG(75, ALT_A)
197
198#define GPIO76_GPIO PIN_CFG(76, GPIO)
199
200#define GPIO77_GPIO PIN_CFG(77, GPIO)
201#define GPIO77_ACCTX_ON PIN_CFG(77, ALT_A)
202
203#define GPIO78_GPIO PIN_CFG(78, GPIO)
204#define GPIO78_IRQn PIN_CFG(78, ALT_A)
205
206#define GPIO79_GPIO PIN_CFG(79, GPIO)
207#define GPIO79_ACCSIM_Clk PIN_CFG(79, ALT_A)
208
209#define GPIO80_GPIO PIN_CFG(80, GPIO)
210#define GPIO80_ACCSIM_Da PIN_CFG(80, ALT_A)
211
212#define GPIO81_GPIO PIN_CFG(81, GPIO)
213#define GPIO81_ACCSIM_Reset PIN_CFG(81, ALT_A)
214
215#define GPIO82_GPIO PIN_CFG(82, GPIO)
216#define GPIO82_ACCSIM_DDir PIN_CFG(82, ALT_A)
217
218#define GPIO96_GPIO PIN_CFG(96, GPIO)
219#define GPIO96_MSP1_TCK PIN_CFG(96, ALT_A)
220#define GPIO96_PRCMU_DEBUG3 PIN_CFG(96, ALT_B)
221#define GPIO96_PRCMU_DEBUG7 PIN_CFG(96, ALT_C)
222
223#define GPIO97_GPIO PIN_CFG(97, GPIO)
224#define GPIO97_MSP1_TFS PIN_CFG(97, ALT_A)
225#define GPIO97_PRCMU_DEBUG2 PIN_CFG(97, ALT_B)
226#define GPIO97_PRCMU_DEBUG6 PIN_CFG(97, ALT_C)
227
228#define GPIO98_GPIO PIN_CFG(98, GPIO)
229#define GPIO98_MSP1_TXD PIN_CFG(98, ALT_A)
230#define GPIO98_PRCMU_DEBUG1 PIN_CFG(98, ALT_B)
231#define GPIO98_PRCMU_DEBUG5 PIN_CFG(98, ALT_C)
232
233#define GPIO99_GPIO PIN_CFG(99, GPIO)
234#define GPIO99_MSP1_RXD PIN_CFG(99, ALT_A)
235#define GPIO99_PRCMU_DEBUG0 PIN_CFG(99, ALT_B)
236#define GPIO99_PRCMU_DEBUG4 PIN_CFG(99, ALT_C)
237
238#define GPIO100_GPIO PIN_CFG(100, GPIO)
239#define GPIO100_I2C0_SCL PIN_CFG(100, ALT_A)
240
241#define GPIO101_GPIO PIN_CFG(101, GPIO)
242#define GPIO101_I2C0_SDA PIN_CFG(101, ALT_A)
243
244#define GPIO128_GPIO PIN_CFG(128, GPIO)
245#define GPIO128_KP_I0 PIN_CFG(128, ALT_A)
246#define GPIO128_BUSMON_D0 PIN_CFG(128, ALT_B)
247
248#define GPIO129_GPIO PIN_CFG(129, GPIO)
249#define GPIO129_KP_O0 PIN_CFG(129, ALT_A)
250#define GPIO129_BUSMON_D1 PIN_CFG(129, ALT_B)
251
252#define GPIO130_GPIO PIN_CFG(130, GPIO)
253#define GPIO130_KP_I1 PIN_CFG(130, ALT_A)
254#define GPIO130_BUSMON_D2 PIN_CFG(130, ALT_B)
255
256#define GPIO131_GPIO PIN_CFG(131, GPIO)
257#define GPIO131_KP_O1 PIN_CFG(131, ALT_A)
258#define GPIO131_BUSMON_D3 PIN_CFG(131, ALT_B)
259
260#define GPIO132_GPIO PIN_CFG(132, GPIO)
261#define GPIO132_KP_I2 PIN_CFG(132, ALT_A)
262#define GPIO132_ETM_D15 PIN_CFG(132, ALT_B)
263#define GPIO132_STMAPE_CLK PIN_CFG(132, ALT_C)
264
265#define GPIO133_GPIO PIN_CFG(133, GPIO)
266#define GPIO133_KP_O2 PIN_CFG(133, ALT_A)
267#define GPIO133_ETM_D14 PIN_CFG(133, ALT_B)
268#define GPIO133_U0_RXD PIN_CFG(133, ALT_C)
269
270#define GPIO134_GPIO PIN_CFG(134, GPIO)
271#define GPIO134_KP_I3 PIN_CFG(134, ALT_A)
272#define GPIO134_ETM_D13 PIN_CFG(134, ALT_B)
273#define GPIO134_STMAPE_DAT0 PIN_CFG(134, ALT_C)
274
275#define GPIO135_GPIO PIN_CFG(135, GPIO)
276#define GPIO135_KP_O3 PIN_CFG(135, ALT_A)
277#define GPIO135_ETM_D12 PIN_CFG(135, ALT_B)
278#define GPIO135_STMAPE_DAT1 PIN_CFG(135, ALT_C)
279
280#define GPIO136_GPIO PIN_CFG(136, GPIO)
281#define GPIO136_KP_I4 PIN_CFG(136, ALT_A)
282#define GPIO136_ETM_D11 PIN_CFG(136, ALT_B)
283#define GPIO136_STMAPE_DAT2 PIN_CFG(136, ALT_C)
284
285#define GPIO137_GPIO PIN_CFG(137, GPIO)
286#define GPIO137_KP_O4 PIN_CFG(137, ALT_A)
287#define GPIO137_ETM_D10 PIN_CFG(137, ALT_B)
288#define GPIO137_STMAPE_DAT3 PIN_CFG(137, ALT_C)
289
290#define GPIO138_GPIO PIN_CFG(138, GPIO)
291#define GPIO138_KP_I5 PIN_CFG(138, ALT_A)
292#define GPIO138_ETM_D9 PIN_CFG(138, ALT_B)
293#define GPIO138_U0_TXD PIN_CFG(138, ALT_C)
294
295#define GPIO139_GPIO PIN_CFG(139, GPIO)
296#define GPIO139_KP_O5 PIN_CFG(139, ALT_A)
297#define GPIO139_ETM_D8 PIN_CFG(139, ALT_B)
298#define GPIO139_BUSMON_D11 PIN_CFG(139, ALT_C)
299
300#define GPIO140_GPIO PIN_CFG(140, GPIO)
301#define GPIO140_KP_I6 PIN_CFG(140, ALT_A)
302#define GPIO140_ETM_D7 PIN_CFG(140, ALT_B)
303#define GPIO140_STMAPE_CLK PIN_CFG(140, ALT_C)
304
305#define GPIO141_GPIO PIN_CFG(141, GPIO)
306#define GPIO141_KP_O6 PIN_CFG(141, ALT_A)
307#define GPIO141_ETM_D6 PIN_CFG(141, ALT_B)
308#define GPIO141_U0_RXD PIN_CFG(141, ALT_C)
309
310#define GPIO142_GPIO PIN_CFG(142, GPIO)
311#define GPIO142_KP_I7 PIN_CFG(142, ALT_A)
312#define GPIO142_ETM_D5 PIN_CFG(142, ALT_B)
313#define GPIO142_STMAPE_DAT0 PIN_CFG(142, ALT_C)
314
315#define GPIO143_GPIO PIN_CFG(143, GPIO)
316#define GPIO143_KP_O7 PIN_CFG(143, ALT_A)
317#define GPIO143_ETM_D4 PIN_CFG(143, ALT_B)
318#define GPIO143_STMAPE_DAT1 PIN_CFG(143, ALT_C)
319
320#define GPIO144_GPIO PIN_CFG(144, GPIO)
321#define GPIO144_I2C3_SCL PIN_CFG(144, ALT_A)
322#define GPIO144_ETM_D3 PIN_CFG(144, ALT_B)
323#define GPIO144_STMAPE_DAT2 PIN_CFG(144, ALT_C)
324
325#define GPIO145_GPIO PIN_CFG(145, GPIO)
326#define GPIO145_I2C3_SDA PIN_CFG(145, ALT_A)
327#define GPIO145_ETM_D2 PIN_CFG(145, ALT_B)
328#define GPIO145_STMAPE_DAT3 PIN_CFG(145, ALT_C)
329
330#define GPIO146_GPIO PIN_CFG(146, GPIO)
331#define GPIO146_PWM_0 PIN_CFG(146, ALT_A)
332#define GPIO146_ETM_D1 PIN_CFG(146, ALT_B)
333
334#define GPIO147_GPIO PIN_CFG(147, GPIO)
335#define GPIO147_PWM_1 PIN_CFG(147, ALT_A)
336#define GPIO147_ETM_D0 PIN_CFG(147, ALT_B)
337
338#define GPIO148_GPIO PIN_CFG(148, GPIO)
339#define GPIO148_PWM_2 PIN_CFG(148, ALT_A)
340#define GPIO148_ETM_CLK PIN_CFG(148, ALT_B)
341
342#define GPIO160_GPIO PIN_CFG(160, GPIO)
343#define GPIO160_CLKOUT_REQn PIN_CFG(160, ALT_A)
344
345#define GPIO161_GPIO PIN_CFG(161, GPIO)
346#define GPIO161_CLKOUT_0 PIN_CFG(161, ALT_A)
347
348#define GPIO162_GPIO PIN_CFG(162, GPIO)
349#define GPIO162_CLKOUT_1 PIN_CFG(162, ALT_A)
350
351#define GPIO163_GPIO PIN_CFG(163, GPIO)
352
353#define GPIO164_GPIO PIN_CFG(164, GPIO)
354#define GPIO164_GPS_START PIN_CFG(164, ALT_A)
355
356#define GPIO165_GPIO PIN_CFG(165, GPIO)
357#define GPIO165_SPI1_CS2n PIN_CFG(165, ALT_A)
358#define GPIO165_U3_RXD PIN_CFG(165, ALT_B)
359#define GPIO165_BUSMON_D20 PIN_CFG(165, ALT_C)
360
361#define GPIO166_GPIO PIN_CFG(166, GPIO)
362#define GPIO166_SPI1_CS1n PIN_CFG(166, ALT_A)
363#define GPIO166_U3_TXD PIN_CFG(166, ALT_B)
364#define GPIO166_BUSMON_D21 PIN_CFG(166, ALT_C)
365
366#define GPIO167_GPIO PIN_CFG(167, GPIO)
367#define GPIO167_SPI1_CS0n PIN_CFG(167, ALT_A)
368#define GPIO167_U3_RTSn PIN_CFG(167, ALT_B)
369#define GPIO167_BUSMON_D22 PIN_CFG(167, ALT_C)
370
371#define GPIO168_GPIO PIN_CFG(168, GPIO)
372#define GPIO168_SPI1_RXD PIN_CFG(168, ALT_A)
373#define GPIO168_U3_CTSn PIN_CFG(168, ALT_B)
374#define GPIO168_BUSMON_D23 PIN_CFG(168, ALT_C)
375
376#define GPIO169_GPIO PIN_CFG(169, GPIO)
377#define GPIO169_SPI1_TXD PIN_CFG(169, ALT_A)
378#define GPIO169_DDR_RC PIN_CFG(169, ALT_B)
379#define GPIO169_BUSMON_D24 PIN_CFG(169, ALT_C)
380
381#define GPIO170_GPIO PIN_CFG(170, GPIO)
382#define GPIO170_SPI1_CLK PIN_CFG(170, ALT_A)
383
384#define GPIO171_GPIO PIN_CFG(171, GPIO)
385#define GPIO171_MC3_DAT0 PIN_CFG(171, ALT_A)
386#define GPIO171_SPI3_RXD PIN_CFG(171, ALT_B)
387#define GPIO171_BUSMON_D25 PIN_CFG(171, ALT_C)
388
389#define GPIO172_GPIO PIN_CFG(172, GPIO)
390#define GPIO172_MC3_DAT1 PIN_CFG(172, ALT_A)
391#define GPIO172_SPI3_CS1n PIN_CFG(172, ALT_B)
392#define GPIO172_BUSMON_D26 PIN_CFG(172, ALT_C)
393
394#define GPIO173_GPIO PIN_CFG(173, GPIO)
395#define GPIO173_MC3_DAT2 PIN_CFG(173, ALT_A)
396#define GPIO173_SPI3_CS2n PIN_CFG(173, ALT_B)
397#define GPIO173_BUSMON_D27 PIN_CFG(173, ALT_C)
398
399#define GPIO174_GPIO PIN_CFG(174, GPIO)
400#define GPIO174_MC3_DAT3 PIN_CFG(174, ALT_A)
401#define GPIO174_SPI3_CS0n PIN_CFG(174, ALT_B)
402#define GPIO174_BUSMON_D28 PIN_CFG(174, ALT_C)
403
404#define GPIO175_GPIO PIN_CFG(175, GPIO)
405#define GPIO175_MC3_CMD PIN_CFG(175, ALT_A)
406#define GPIO175_SPI3_TXD PIN_CFG(175, ALT_B)
407#define GPIO175_BUSMON_D29 PIN_CFG(175, ALT_C)
408
409#define GPIO176_GPIO PIN_CFG(176, GPIO)
410#define GPIO176_MC3_CLK PIN_CFG(176, ALT_A)
411#define GPIO176_SPI3_CLK PIN_CFG(176, ALT_B)
412
413#define GPIO177_GPIO PIN_CFG(177, GPIO)
414#define GPIO177_U2_RXD PIN_CFG(177, ALT_A)
415#define GPIO177_I2C3_SCL PIN_CFG(177, ALT_B)
416#define GPIO177_BUSMON_D30 PIN_CFG(177, ALT_C)
417
418#define GPIO178_GPIO PIN_CFG(178, GPIO)
419#define GPIO178_U2_TXD PIN_CFG(178, ALT_A)
420#define GPIO178_I2C3_SDA PIN_CFG(178, ALT_B)
421#define GPIO178_BUSMON_D31 PIN_CFG(178, ALT_C)
422
423#define GPIO179_GPIO PIN_CFG(179, GPIO)
424#define GPIO179_U2_CTSn PIN_CFG(179, ALT_A)
425#define GPIO179_U3_RXD PIN_CFG(179, ALT_B)
426#define GPIO179_BUSMON_D32 PIN_CFG(179, ALT_C)
427
428#define GPIO180_GPIO PIN_CFG(180, GPIO)
429#define GPIO180_U2_RTSn PIN_CFG(180, ALT_A)
430#define GPIO180_U3_TXD PIN_CFG(180, ALT_B)
431#define GPIO180_BUSMON_D33 PIN_CFG(180, ALT_C)
432
433#define GPIO185_GPIO PIN_CFG(185, GPIO)
434#define GPIO185_SPI3_CS2n PIN_CFG(185, ALT_A)
435#define GPIO185_MC4_DAT0 PIN_CFG(185, ALT_B)
436
437#define GPIO186_GPIO PIN_CFG(186, GPIO)
438#define GPIO186_SPI3_CS1n PIN_CFG(186, ALT_A)
439#define GPIO186_MC4_DAT1 PIN_CFG(186, ALT_B)
440
441#define GPIO187_GPIO PIN_CFG(187, GPIO)
442#define GPIO187_SPI3_CS0n PIN_CFG(187, ALT_A)
443#define GPIO187_MC4_DAT2 PIN_CFG(187, ALT_B)
444
445#define GPIO188_GPIO PIN_CFG(188, GPIO)
446#define GPIO188_SPI3_RXD PIN_CFG(188, ALT_A)
447#define GPIO188_MC4_DAT3 PIN_CFG(188, ALT_B)
448
449#define GPIO189_GPIO PIN_CFG(189, GPIO)
450#define GPIO189_SPI3_TXD PIN_CFG(189, ALT_A)
451#define GPIO189_MC4_CMD PIN_CFG(189, ALT_B)
452
453#define GPIO190_GPIO PIN_CFG(190, GPIO)
454#define GPIO190_SPI3_CLK PIN_CFG(190, ALT_A)
455#define GPIO190_MC4_CLK PIN_CFG(190, ALT_B)
456
457#define GPIO191_GPIO PIN_CFG(191, GPIO)
458#define GPIO191_MC1_DAT0 PIN_CFG(191, ALT_A)
459#define GPIO191_MC4_DAT4 PIN_CFG(191, ALT_B)
460#define GPIO191_STMAPE_DAT0 PIN_CFG(191, ALT_C)
461
462#define GPIO192_GPIO PIN_CFG(192, GPIO)
463#define GPIO192_MC1_DAT1 PIN_CFG(192, ALT_A)
464#define GPIO192_MC4_DAT5 PIN_CFG(192, ALT_B)
465#define GPIO192_STMAPE_DAT1 PIN_CFG(192, ALT_C)
466
467#define GPIO193_GPIO PIN_CFG(193, GPIO)
468#define GPIO193_MC1_DAT2 PIN_CFG(193, ALT_A)
469#define GPIO193_MC4_DAT6 PIN_CFG(193, ALT_B)
470#define GPIO193_STMAPE_DAT2 PIN_CFG(193, ALT_C)
471
472#define GPIO194_GPIO PIN_CFG(194, GPIO)
473#define GPIO194_MC1_DAT3 PIN_CFG(194, ALT_A)
474#define GPIO194_MC4_DAT7 PIN_CFG(194, ALT_B)
475#define GPIO194_STMAPE_DAT3 PIN_CFG(194, ALT_C)
476
477#define GPIO195_GPIO PIN_CFG(195, GPIO)
478#define GPIO195_MC1_CLK PIN_CFG(195, ALT_A)
479#define GPIO195_STMAPE_CLK PIN_CFG(195, ALT_B)
480#define GPIO195_BUSMON_CLK PIN_CFG(195, ALT_C)
481
482#define GPIO196_GPIO PIN_CFG(196, GPIO)
483#define GPIO196_MC1_CMD PIN_CFG(196, ALT_A)
484#define GPIO196_U0_RXD PIN_CFG(196, ALT_B)
485#define GPIO196_BUSMON_D38 PIN_CFG(196, ALT_C)
486
487#define GPIO197_GPIO PIN_CFG(197, GPIO)
488#define GPIO197_MC1_CMDDIR PIN_CFG(197, ALT_A)
489#define GPIO197_BUSMON_D39 PIN_CFG(197, ALT_B)
490
491#define GPIO198_GPIO PIN_CFG(198, GPIO)
492#define GPIO198_MC1_FBCLK PIN_CFG(198, ALT_A)
493
494#define GPIO199_GPIO PIN_CFG(199, GPIO)
495#define GPIO199_MC1_DAT0DIR PIN_CFG(199, ALT_A)
496#define GPIO199_BUSMON_D40 PIN_CFG(199, ALT_B)
497
498#define GPIO200_GPIO PIN_CFG(200, GPIO)
499#define GPIO200_U1_TXD PIN_CFG(200, ALT_A)
500#define GPIO200_ACCU0_RTSn PIN_CFG(200, ALT_B)
501
502#define GPIO201_GPIO PIN_CFG(201, GPIO)
503#define GPIO201_U1_RXD PIN_CFG(201, ALT_A)
504#define GPIO201_ACCU0_CTSn PIN_CFG(201, ALT_B)
505
506#define GPIO202_GPIO PIN_CFG(202, GPIO)
507#define GPIO202_U1_CTSn PIN_CFG(202, ALT_A)
508#define GPIO202_ACCU0_RXD PIN_CFG(202, ALT_B)
509
510#define GPIO203_GPIO PIN_CFG(203, GPIO)
511#define GPIO203_U1_RTSn PIN_CFG(203, ALT_A)
512#define GPIO203_ACCU0_TXD PIN_CFG(203, ALT_B)
513
514#define GPIO204_GPIO PIN_CFG(204, GPIO)
515#define GPIO204_SPI0_CS2n PIN_CFG(204, ALT_A)
516#define GPIO204_ACCGPIO_000 PIN_CFG(204, ALT_B)
517#define GPIO204_LCD_VSI1 PIN_CFG(204, ALT_C)
518
519#define GPIO205_GPIO PIN_CFG(205, GPIO)
520#define GPIO205_SPI0_CS1n PIN_CFG(205, ALT_A)
521#define GPIO205_ACCGPIO_001 PIN_CFG(205, ALT_B)
522#define GPIO205_LCD_D3 PIN_CFG(205, ALT_C)
523
524#define GPIO206_GPIO PIN_CFG(206, GPIO)
525#define GPIO206_SPI0_CS0n PIN_CFG(206, ALT_A)
526#define GPIO206_ACCGPIO_002 PIN_CFG(206, ALT_B)
527#define GPIO206_LCD_D2 PIN_CFG(206, ALT_C)
528
529#define GPIO207_GPIO PIN_CFG(207, GPIO)
530#define GPIO207_SPI0_RXD PIN_CFG(207, ALT_A)
531#define GPIO207_ACCGPIO_003 PIN_CFG(207, ALT_B)
532#define GPIO207_LCD_D1 PIN_CFG(207, ALT_C)
533
534#define GPIO208_GPIO PIN_CFG(208, GPIO)
535#define GPIO208_SPI0_TXD PIN_CFG(208, ALT_A)
536#define GPIO208_ACCGPIO_004 PIN_CFG(208, ALT_B)
537#define GPIO208_LCD_D0 PIN_CFG(208, ALT_C)
538
539#define GPIO209_GPIO PIN_CFG(209, GPIO)
540#define GPIO209_SPI0_CLK PIN_CFG(209, ALT_A)
541#define GPIO209_ACCGPIO_005 PIN_CFG(209, ALT_B)
542#define GPIO209_LCD_CLK PIN_CFG(209, ALT_C)
543
544#define GPIO210_GPIO PIN_CFG(210, GPIO)
545#define GPIO210_LCD_VSO PIN_CFG(210, ALT_A)
546#define GPIO210_PRCMU_PWRCTRL1 PIN_CFG(210, ALT_B)
547
548#define GPIO211_GPIO PIN_CFG(211, GPIO)
549#define GPIO211_LCD_VSI0 PIN_CFG(211, ALT_A)
550#define GPIO211_PRCMU_PWRCTRL2 PIN_CFG(211, ALT_B)
551
552#define GPIO212_GPIO PIN_CFG(212, GPIO)
553#define GPIO212_SPI2_CS2n PIN_CFG(212, ALT_A)
554#define GPIO212_LCD_HSO PIN_CFG(212, ALT_B)
555
556#define GPIO213_GPIO PIN_CFG(213, GPIO)
557#define GPIO213_SPI2_CS1n PIN_CFG(213, ALT_A)
558#define GPIO213_LCD_DE PIN_CFG(213, ALT_B)
559#define GPIO213_BUSMON_D16 PIN_CFG(213, ALT_C)
560
561#define GPIO214_GPIO PIN_CFG(214, GPIO)
562#define GPIO214_SPI2_CS0n PIN_CFG(214, ALT_A)
563#define GPIO214_LCD_D7 PIN_CFG(214, ALT_B)
564#define GPIO214_BUSMON_D17 PIN_CFG(214, ALT_C)
565
566#define GPIO215_GPIO PIN_CFG(215, GPIO)
567#define GPIO215_SPI2_RXD PIN_CFG(215, ALT_A)
568#define GPIO215_LCD_D6 PIN_CFG(215, ALT_B)
569#define GPIO215_BUSMON_D18 PIN_CFG(215, ALT_C)
570
571#define GPIO216_GPIO PIN_CFG(216, GPIO)
572#define GPIO216_SPI2_CLK PIN_CFG(216, ALT_A)
573#define GPIO216_LCD_D5 PIN_CFG(216, ALT_B)
574
575#define GPIO217_GPIO PIN_CFG(217, GPIO)
576#define GPIO217_SPI2_TXD PIN_CFG(217, ALT_A)
577#define GPIO217_LCD_D4 PIN_CFG(217, ALT_B)
578#define GPIO217_BUSMON_D19 PIN_CFG(217, ALT_C)
579
580#define GPIO218_GPIO PIN_CFG(218, GPIO)
581#define GPIO218_I2C2_SCL PIN_CFG(218, ALT_A)
582#define GPIO218_LCD_VSO PIN_CFG(218, ALT_B)
583
584#define GPIO219_GPIO PIN_CFG(219, GPIO)
585#define GPIO219_I2C2_SDA PIN_CFG(219, ALT_A)
586#define GPIO219_LCD_D3 PIN_CFG(219, ALT_B)
587
588#define GPIO220_GPIO PIN_CFG(220, GPIO)
589#define GPIO220_MSP2_TCK PIN_CFG(220, ALT_A)
590#define GPIO220_LCD_D2 PIN_CFG(220, ALT_B)
591
592#define GPIO221_GPIO PIN_CFG(221, GPIO)
593#define GPIO221_MSP2_TFS PIN_CFG(221, ALT_A)
594#define GPIO221_LCD_D1 PIN_CFG(221, ALT_B)
595
596#define GPIO222_GPIO PIN_CFG(222, GPIO)
597#define GPIO222_MSP2_TXD PIN_CFG(222, ALT_A)
598#define GPIO222_LCD_D0 PIN_CFG(222, ALT_B)
599
600#define GPIO223_GPIO PIN_CFG(223, GPIO)
601#define GPIO223_MSP2_RXD PIN_CFG(223, ALT_A)
602#define GPIO223_LCD_CLK PIN_CFG(223, ALT_B)
603
604#define GPIO224_GPIO PIN_CFG(224, GPIO)
605#define GPIO224_PRCMU_PWRCTRL0 PIN_CFG(224, ALT_A)
606#define GPIO224_LCD_VSI1 PIN_CFG(224, ALT_B)
607
608#define GPIO225_GPIO PIN_CFG(225, GPIO)
609#define GPIO225_PRCMU_PWRCTRL1 PIN_CFG(225, ALT_A)
610#define GPIO225_IRDA_RXD PIN_CFG(225, ALT_B)
611
612#define GPIO226_GPIO PIN_CFG(226, GPIO)
613#define GPIO226_PRCMU_PWRCTRL2 PIN_CFG(226, ALT_A)
614#define GPIO226_IRRC_DAT PIN_CFG(226, ALT_B)
615
616#define GPIO227_GPIO PIN_CFG(227, GPIO)
617#define GPIO227_IRRC_DAT PIN_CFG(227, ALT_A)
618#define GPIO227_IRDA_TXD PIN_CFG(227, ALT_B)
619
620#endif
diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h
index 9055d5d3233c..66f8761cc823 100644
--- a/arch/arm/mach-ux500/pins-db8500.h
+++ b/arch/arm/mach-ux500/pins-db8500.h
@@ -96,57 +96,57 @@
96#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C) 96#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C)
97 97
98#define GPIO18_GPIO PIN_CFG(18, GPIO) 98#define GPIO18_GPIO PIN_CFG(18, GPIO)
99#define GPIO18_MC0_CMDDIR PIN_CFG(18, ALT_A) 99#define GPIO18_MC0_CMDDIR PIN_CFG_PULL(18, ALT_A, UP)
100#define GPIO18_U2_RXD PIN_CFG(18, ALT_B) 100#define GPIO18_U2_RXD PIN_CFG(18, ALT_B)
101#define GPIO18_MS_IEP PIN_CFG(18, ALT_C) 101#define GPIO18_MS_IEP PIN_CFG(18, ALT_C)
102 102
103#define GPIO19_GPIO PIN_CFG(19, GPIO) 103#define GPIO19_GPIO PIN_CFG(19, GPIO)
104#define GPIO19_MC0_DAT0DIR PIN_CFG(19, ALT_A) 104#define GPIO19_MC0_DAT0DIR PIN_CFG_PULL(19, ALT_A, UP)
105#define GPIO19_U2_TXD PIN_CFG(19, ALT_B) 105#define GPIO19_U2_TXD PIN_CFG(19, ALT_B)
106#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C) 106#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C)
107 107
108#define GPIO20_GPIO PIN_CFG(20, GPIO) 108#define GPIO20_GPIO PIN_CFG(20, GPIO)
109#define GPIO20_MC0_DAT2DIR PIN_CFG(20, ALT_A) 109#define GPIO20_MC0_DAT2DIR PIN_CFG_PULL(20, ALT_A, UP)
110#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B) 110#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B)
111#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C) 111#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C)
112 112
113#define GPIO21_GPIO PIN_CFG(21, GPIO) 113#define GPIO21_GPIO PIN_CFG(21, GPIO)
114#define GPIO21_MC0_DAT31DIR PIN_CFG(21, ALT_A) 114#define GPIO21_MC0_DAT31DIR PIN_CFG_PULL(21, ALT_A, UP)
115#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B) 115#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B)
116#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C) 116#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C)
117 117
118#define GPIO22_GPIO PIN_CFG(22, GPIO) 118#define GPIO22_GPIO PIN_CFG(22, GPIO)
119#define GPIO22_MC0_FBCLK PIN_CFG(22, ALT_A) 119#define GPIO22_MC0_FBCLK PIN_CFG_PULL(22, ALT_A, UP)
120#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B) 120#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B)
121#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C) 121#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C)
122 122
123#define GPIO23_GPIO PIN_CFG(23, GPIO) 123#define GPIO23_GPIO PIN_CFG(23, GPIO)
124#define GPIO23_MC0_CLK PIN_CFG(23, ALT_A) 124#define GPIO23_MC0_CLK PIN_CFG_PULL(23, ALT_A, UP)
125#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B) 125#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B)
126#define GPIO23_MS_CLK PIN_CFG(23, ALT_C) 126#define GPIO23_MS_CLK PIN_CFG(23, ALT_C)
127 127
128#define GPIO24_GPIO PIN_CFG(24, GPIO) 128#define GPIO24_GPIO PIN_CFG(24, GPIO)
129#define GPIO24_MC0_CMD PIN_CFG(24, ALT_A) 129#define GPIO24_MC0_CMD PIN_CFG_PULL(24, ALT_A, UP)
130#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B) 130#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B)
131#define GPIO24_MS_BS PIN_CFG(24, ALT_C) 131#define GPIO24_MS_BS PIN_CFG(24, ALT_C)
132 132
133#define GPIO25_GPIO PIN_CFG(25, GPIO) 133#define GPIO25_GPIO PIN_CFG(25, GPIO)
134#define GPIO25_MC0_DAT0 PIN_CFG(25, ALT_A) 134#define GPIO25_MC0_DAT0 PIN_CFG_PULL(25, ALT_A, UP)
135#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B) 135#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B)
136#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C) 136#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C)
137 137
138#define GPIO26_GPIO PIN_CFG(26, GPIO) 138#define GPIO26_GPIO PIN_CFG(26, GPIO)
139#define GPIO26_MC0_DAT1 PIN_CFG(26, ALT_A) 139#define GPIO26_MC0_DAT1 PIN_CFG_PULL(26, ALT_A, UP)
140#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B) 140#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B)
141#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C) 141#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C)
142 142
143#define GPIO27_GPIO PIN_CFG(27, GPIO) 143#define GPIO27_GPIO PIN_CFG(27, GPIO)
144#define GPIO27_MC0_DAT2 PIN_CFG(27, ALT_A) 144#define GPIO27_MC0_DAT2 PIN_CFG_PULL(27, ALT_A, UP)
145#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B) 145#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B)
146#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C) 146#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C)
147 147
148#define GPIO28_GPIO PIN_CFG(28, GPIO) 148#define GPIO28_GPIO PIN_CFG(28, GPIO)
149#define GPIO28_MC0_DAT3 PIN_CFG(28, ALT_A) 149#define GPIO28_MC0_DAT3 PIN_CFG_PULL(28, ALT_A, UP)
150#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B) 150#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B)
151#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C) 151#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C)
152 152
@@ -357,48 +357,48 @@
357#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C) 357#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C)
358 358
359#define GPIO128_GPIO PIN_CFG(128, GPIO) 359#define GPIO128_GPIO PIN_CFG(128, GPIO)
360#define GPIO128_MC2_CLK PIN_CFG(128, ALT_A) 360#define GPIO128_MC2_CLK PIN_CFG_PULL(128, ALT_A, UP)
361#define GPIO128_SM_CKO PIN_CFG(128, ALT_B) 361#define GPIO128_SM_CKO PIN_CFG(128, ALT_B)
362 362
363#define GPIO129_GPIO PIN_CFG(129, GPIO) 363#define GPIO129_GPIO PIN_CFG(129, GPIO)
364#define GPIO129_MC2_CMD PIN_CFG(129, ALT_A) 364#define GPIO129_MC2_CMD PIN_CFG_PULL(129, ALT_A, UP)
365#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B) 365#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B)
366 366
367#define GPIO130_GPIO PIN_CFG(130, GPIO) 367#define GPIO130_GPIO PIN_CFG(130, GPIO)
368#define GPIO130_MC2_FBCLK PIN_CFG(130, ALT_A) 368#define GPIO130_MC2_FBCLK PIN_CFG_PULL(130, ALT_A, UP)
369#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B) 369#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B)
370#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C) 370#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C)
371 371
372#define GPIO131_GPIO PIN_CFG(131, GPIO) 372#define GPIO131_GPIO PIN_CFG(131, GPIO)
373#define GPIO131_MC2_DAT0 PIN_CFG(131, ALT_A) 373#define GPIO131_MC2_DAT0 PIN_CFG_PULL(131, ALT_A, UP)
374#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B) 374#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B)
375 375
376#define GPIO132_GPIO PIN_CFG(132, GPIO) 376#define GPIO132_GPIO PIN_CFG(132, GPIO)
377#define GPIO132_MC2_DAT1 PIN_CFG(132, ALT_A) 377#define GPIO132_MC2_DAT1 PIN_CFG_PULL(132, ALT_A, UP)
378#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B) 378#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B)
379 379
380#define GPIO133_GPIO PIN_CFG(133, GPIO) 380#define GPIO133_GPIO PIN_CFG(133, GPIO)
381#define GPIO133_MC2_DAT2 PIN_CFG(133, ALT_A) 381#define GPIO133_MC2_DAT2 PIN_CFG_PULL(133, ALT_A, UP)
382#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B) 382#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B)
383 383
384#define GPIO134_GPIO PIN_CFG(134, GPIO) 384#define GPIO134_GPIO PIN_CFG(134, GPIO)
385#define GPIO134_MC2_DAT3 PIN_CFG(134, ALT_A) 385#define GPIO134_MC2_DAT3 PIN_CFG_PULL(134, ALT_A, UP)
386#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B) 386#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B)
387 387
388#define GPIO135_GPIO PIN_CFG(135, GPIO) 388#define GPIO135_GPIO PIN_CFG(135, GPIO)
389#define GPIO135_MC2_DAT4 PIN_CFG(135, ALT_A) 389#define GPIO135_MC2_DAT4 PIN_CFG_PULL(135, ALT_A, UP)
390#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B) 390#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B)
391 391
392#define GPIO136_GPIO PIN_CFG(136, GPIO) 392#define GPIO136_GPIO PIN_CFG(136, GPIO)
393#define GPIO136_MC2_DAT5 PIN_CFG(136, ALT_A) 393#define GPIO136_MC2_DAT5 PIN_CFG_PULL(136, ALT_A, UP)
394#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B) 394#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B)
395 395
396#define GPIO137_GPIO PIN_CFG(137, GPIO) 396#define GPIO137_GPIO PIN_CFG(137, GPIO)
397#define GPIO137_MC2_DAT6 PIN_CFG(137, ALT_A) 397#define GPIO137_MC2_DAT6 PIN_CFG_PULL(137, ALT_A, UP)
398#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B) 398#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B)
399 399
400#define GPIO138_GPIO PIN_CFG(138, GPIO) 400#define GPIO138_GPIO PIN_CFG(138, GPIO)
401#define GPIO138_MC2_DAT7 PIN_CFG(138, ALT_A) 401#define GPIO138_MC2_DAT7 PIN_CFG_PULL(138, ALT_A, UP)
402#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B) 402#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B)
403 403
404#define GPIO139_GPIO PIN_CFG(139, GPIO) 404#define GPIO139_GPIO PIN_CFG(139, GPIO)
@@ -569,39 +569,39 @@
569#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A) 569#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A)
570 570
571#define GPIO197_GPIO PIN_CFG(197, GPIO) 571#define GPIO197_GPIO PIN_CFG(197, GPIO)
572#define GPIO197_MC4_DAT3 PIN_CFG(197, ALT_A) 572#define GPIO197_MC4_DAT3 PIN_CFG_PULL(197, ALT_A, UP)
573 573
574#define GPIO198_GPIO PIN_CFG(198, GPIO) 574#define GPIO198_GPIO PIN_CFG(198, GPIO)
575#define GPIO198_MC4_DAT2 PIN_CFG(198, ALT_A) 575#define GPIO198_MC4_DAT2 PIN_CFG_PULL(198, ALT_A, UP)
576 576
577#define GPIO199_GPIO PIN_CFG(199, GPIO) 577#define GPIO199_GPIO PIN_CFG(199, GPIO)
578#define GPIO199_MC4_DAT1 PIN_CFG(199, ALT_A) 578#define GPIO199_MC4_DAT1 PIN_CFG_PULL(199, ALT_A, UP)
579 579
580#define GPIO200_GPIO PIN_CFG(200, GPIO) 580#define GPIO200_GPIO PIN_CFG(200, GPIO)
581#define GPIO200_MC4_DAT0 PIN_CFG(200, ALT_A) 581#define GPIO200_MC4_DAT0 PIN_CFG_PULL(200, ALT_A, UP)
582 582
583#define GPIO201_GPIO PIN_CFG(201, GPIO) 583#define GPIO201_GPIO PIN_CFG(201, GPIO)
584#define GPIO201_MC4_CMD PIN_CFG(201, ALT_A) 584#define GPIO201_MC4_CMD PIN_CFG_PULL(201, ALT_A, UP)
585 585
586#define GPIO202_GPIO PIN_CFG(202, GPIO) 586#define GPIO202_GPIO PIN_CFG(202, GPIO)
587#define GPIO202_MC4_FBCLK PIN_CFG(202, ALT_A) 587#define GPIO202_MC4_FBCLK PIN_CFG_PULL(202, ALT_A, UP)
588#define GPIO202_PWL PIN_CFG(202, ALT_B) 588#define GPIO202_PWL PIN_CFG(202, ALT_B)
589#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C) 589#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C)
590 590
591#define GPIO203_GPIO PIN_CFG(203, GPIO) 591#define GPIO203_GPIO PIN_CFG(203, GPIO)
592#define GPIO203_MC4_CLK PIN_CFG(203, ALT_A) 592#define GPIO203_MC4_CLK PIN_CFG_PULL(203, ALT_A, UP)
593 593
594#define GPIO204_GPIO PIN_CFG(204, GPIO) 594#define GPIO204_GPIO PIN_CFG(204, GPIO)
595#define GPIO204_MC4_DAT7 PIN_CFG(204, ALT_A) 595#define GPIO204_MC4_DAT7 PIN_CFG_PULL(204, ALT_A, UP)
596 596
597#define GPIO205_GPIO PIN_CFG(205, GPIO) 597#define GPIO205_GPIO PIN_CFG(205, GPIO)
598#define GPIO205_MC4_DAT6 PIN_CFG(205, ALT_A) 598#define GPIO205_MC4_DAT6 PIN_CFG_PULL(205, ALT_A, UP)
599 599
600#define GPIO206_GPIO PIN_CFG(206, GPIO) 600#define GPIO206_GPIO PIN_CFG(206, GPIO)
601#define GPIO206_MC4_DAT5 PIN_CFG(206, ALT_A) 601#define GPIO206_MC4_DAT5 PIN_CFG_PULL(206, ALT_A, UP)
602 602
603#define GPIO207_GPIO PIN_CFG(207, GPIO) 603#define GPIO207_GPIO PIN_CFG(207, GPIO)
604#define GPIO207_MC4_DAT4 PIN_CFG(207, ALT_A) 604#define GPIO207_MC4_DAT4 PIN_CFG_PULL(207, ALT_A, UP)
605 605
606#define GPIO208_GPIO PIN_CFG(208, GPIO) 606#define GPIO208_GPIO PIN_CFG(208, GPIO)
607#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A) 607#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A)
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 438ef16aec90..9e4c678de785 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -78,6 +78,8 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
78 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); 78 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
79 outer_clean_range(__pa(&pen_release), __pa(&pen_release) + 1); 79 outer_clean_range(__pa(&pen_release), __pa(&pen_release) + 1);
80 80
81 smp_cross_call(cpumask_of(cpu));
82
81 timeout = jiffies + (1 * HZ); 83 timeout = jiffies + (1 * HZ);
82 while (time_before(jiffies, timeout)) { 84 while (time_before(jiffies, timeout)) {
83 if (pen_release == -1) 85 if (pen_release == -1)
diff --git a/arch/arm/mach-ux500/prcmu.c b/arch/arm/mach-ux500/prcmu.c
new file mode 100644
index 000000000000..293274d1342a
--- /dev/null
+++ b/arch/arm/mach-ux500/prcmu.c
@@ -0,0 +1,231 @@
1/*
2 * Copyright (C) ST Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
6 *
7 * U8500 PRCMU driver.
8 */
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/errno.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/mutex.h>
15#include <linux/completion.h>
16#include <linux/jiffies.h>
17#include <linux/bitops.h>
18#include <linux/interrupt.h>
19
20#include <mach/hardware.h>
21#include <mach/prcmu-regs.h>
22
23#define PRCMU_TCDM_BASE __io_address(U8500_PRCMU_TCDM_BASE)
24
25#define REQ_MB5 (PRCMU_TCDM_BASE + 0xE44)
26#define ACK_MB5 (PRCMU_TCDM_BASE + 0xDF4)
27
28#define REQ_MB5_I2C_SLAVE_OP (REQ_MB5)
29#define REQ_MB5_I2C_HW_BITS (REQ_MB5 + 1)
30#define REQ_MB5_I2C_REG (REQ_MB5 + 2)
31#define REQ_MB5_I2C_VAL (REQ_MB5 + 3)
32
33#define ACK_MB5_I2C_STATUS (ACK_MB5 + 1)
34#define ACK_MB5_I2C_VAL (ACK_MB5 + 3)
35
36#define I2C_WRITE(slave) ((slave) << 1)
37#define I2C_READ(slave) (((slave) << 1) | BIT(0))
38#define I2C_STOP_EN BIT(3)
39
40enum ack_mb5_status {
41 I2C_WR_OK = 0x01,
42 I2C_RD_OK = 0x02,
43};
44
45#define MBOX_BIT BIT
46#define NUM_MBOX 8
47
48static struct {
49 struct mutex lock;
50 struct completion work;
51 bool failed;
52 struct {
53 u8 status;
54 u8 value;
55 } ack;
56} mb5_transfer;
57
58/**
59 * prcmu_abb_read() - Read register value(s) from the ABB.
60 * @slave: The I2C slave address.
61 * @reg: The (start) register address.
62 * @value: The read out value(s).
63 * @size: The number of registers to read.
64 *
65 * Reads register value(s) from the ABB.
66 * @size has to be 1 for the current firmware version.
67 */
68int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
69{
70 int r;
71
72 if (size != 1)
73 return -EINVAL;
74
75 r = mutex_lock_interruptible(&mb5_transfer.lock);
76 if (r)
77 return r;
78
79 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
80 cpu_relax();
81
82 writeb(I2C_READ(slave), REQ_MB5_I2C_SLAVE_OP);
83 writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
84 writeb(reg, REQ_MB5_I2C_REG);
85
86 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
87 if (!wait_for_completion_timeout(&mb5_transfer.work,
88 msecs_to_jiffies(500))) {
89 pr_err("prcmu: prcmu_abb_read timed out.\n");
90 r = -EIO;
91 goto unlock_and_return;
92 }
93 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
94 if (!r)
95 *value = mb5_transfer.ack.value;
96
97unlock_and_return:
98 mutex_unlock(&mb5_transfer.lock);
99 return r;
100}
101EXPORT_SYMBOL(prcmu_abb_read);
102
103/**
104 * prcmu_abb_write() - Write register value(s) to the ABB.
105 * @slave: The I2C slave address.
106 * @reg: The (start) register address.
107 * @value: The value(s) to write.
108 * @size: The number of registers to write.
109 *
110 * Reads register value(s) from the ABB.
111 * @size has to be 1 for the current firmware version.
112 */
113int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
114{
115 int r;
116
117 if (size != 1)
118 return -EINVAL;
119
120 r = mutex_lock_interruptible(&mb5_transfer.lock);
121 if (r)
122 return r;
123
124
125 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
126 cpu_relax();
127
128 writeb(I2C_WRITE(slave), REQ_MB5_I2C_SLAVE_OP);
129 writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
130 writeb(reg, REQ_MB5_I2C_REG);
131 writeb(*value, REQ_MB5_I2C_VAL);
132
133 writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
134 if (!wait_for_completion_timeout(&mb5_transfer.work,
135 msecs_to_jiffies(500))) {
136 pr_err("prcmu: prcmu_abb_write timed out.\n");
137 r = -EIO;
138 goto unlock_and_return;
139 }
140 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
141
142unlock_and_return:
143 mutex_unlock(&mb5_transfer.lock);
144 return r;
145}
146EXPORT_SYMBOL(prcmu_abb_write);
147
148static void read_mailbox_0(void)
149{
150 writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR);
151}
152
153static void read_mailbox_1(void)
154{
155 writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR);
156}
157
158static void read_mailbox_2(void)
159{
160 writel(MBOX_BIT(2), PRCM_ARM_IT1_CLEAR);
161}
162
163static void read_mailbox_3(void)
164{
165 writel(MBOX_BIT(3), PRCM_ARM_IT1_CLEAR);
166}
167
168static void read_mailbox_4(void)
169{
170 writel(MBOX_BIT(4), PRCM_ARM_IT1_CLEAR);
171}
172
173static void read_mailbox_5(void)
174{
175 mb5_transfer.ack.status = readb(ACK_MB5_I2C_STATUS);
176 mb5_transfer.ack.value = readb(ACK_MB5_I2C_VAL);
177 complete(&mb5_transfer.work);
178 writel(MBOX_BIT(5), PRCM_ARM_IT1_CLEAR);
179}
180
181static void read_mailbox_6(void)
182{
183 writel(MBOX_BIT(6), PRCM_ARM_IT1_CLEAR);
184}
185
186static void read_mailbox_7(void)
187{
188 writel(MBOX_BIT(7), PRCM_ARM_IT1_CLEAR);
189}
190
191static void (* const read_mailbox[NUM_MBOX])(void) = {
192 read_mailbox_0,
193 read_mailbox_1,
194 read_mailbox_2,
195 read_mailbox_3,
196 read_mailbox_4,
197 read_mailbox_5,
198 read_mailbox_6,
199 read_mailbox_7
200};
201
202static irqreturn_t prcmu_irq_handler(int irq, void *data)
203{
204 u32 bits;
205 u8 n;
206
207 bits = (readl(PRCM_ARM_IT1_VAL) & (MBOX_BIT(NUM_MBOX) - 1));
208 if (unlikely(!bits))
209 return IRQ_NONE;
210
211 for (n = 0; bits; n++) {
212 if (bits & MBOX_BIT(n)) {
213 bits -= MBOX_BIT(n);
214 read_mailbox[n]();
215 }
216 }
217 return IRQ_HANDLED;
218}
219
220static int __init prcmu_init(void)
221{
222 mutex_init(&mb5_transfer.lock);
223 init_completion(&mb5_transfer.work);
224
225 /* Clean up the mailbox interrupts after pre-kernel code. */
226 writel((MBOX_BIT(NUM_MBOX) - 1), PRCM_ARM_IT1_CLEAR);
227
228 return request_irq(IRQ_PRCMU, prcmu_irq_handler, 0, "prcmu", NULL);
229}
230
231arch_initcall(prcmu_init);
diff --git a/arch/arm/mach-ux500/ste-dma40-db5500.h b/arch/arm/mach-ux500/ste-dma40-db5500.h
new file mode 100644
index 000000000000..cb2110c32858
--- /dev/null
+++ b/arch/arm/mach-ux500/ste-dma40-db5500.h
@@ -0,0 +1,135 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
6 *
7 * DB5500-SoC-specific configuration for DMA40
8 */
9
10#ifndef STE_DMA40_DB5500_H
11#define STE_DMA40_DB5500_H
12
13#define DB5500_DMA_NR_DEV 64
14
15enum dma_src_dev_type {
16 DB5500_DMA_DEV0_SPI0_RX = 0,
17 DB5500_DMA_DEV1_SPI1_RX = 1,
18 DB5500_DMA_DEV2_SPI2_RX = 2,
19 DB5500_DMA_DEV3_SPI3_RX = 3,
20 DB5500_DMA_DEV4_USB_OTG_IEP_1_9 = 4,
21 DB5500_DMA_DEV5_USB_OTG_IEP_2_10 = 5,
22 DB5500_DMA_DEV6_USB_OTG_IEP_3_11 = 6,
23 DB5500_DMA_DEV7_IRDA_RFS = 7,
24 DB5500_DMA_DEV8_IRDA_FIFO_RX = 8,
25 DB5500_DMA_DEV9_MSP0_RX = 9,
26 DB5500_DMA_DEV10_MSP1_RX = 10,
27 DB5500_DMA_DEV11_MSP2_RX = 11,
28 DB5500_DMA_DEV12_UART0_RX = 12,
29 DB5500_DMA_DEV13_UART1_RX = 13,
30 DB5500_DMA_DEV14_UART2_RX = 14,
31 DB5500_DMA_DEV15_UART3_RX = 15,
32 DB5500_DMA_DEV16_USB_OTG_IEP_8 = 16,
33 DB5500_DMA_DEV17_USB_OTG_IEP_1_9 = 17,
34 DB5500_DMA_DEV18_USB_OTG_IEP_2_10 = 18,
35 DB5500_DMA_DEV19_USB_OTG_IEP_3_11 = 19,
36 DB5500_DMA_DEV20_USB_OTG_IEP_4_12 = 20,
37 DB5500_DMA_DEV21_USB_OTG_IEP_5_13 = 21,
38 DB5500_DMA_DEV22_USB_OTG_IEP_6_14 = 22,
39 DB5500_DMA_DEV23_USB_OTG_IEP_7_15 = 23,
40 DB5500_DMA_DEV24_SDMMC0_RX = 24,
41 DB5500_DMA_DEV25_SDMMC1_RX = 25,
42 DB5500_DMA_DEV26_SDMMC2_RX = 26,
43 DB5500_DMA_DEV27_SDMMC3_RX = 27,
44 DB5500_DMA_DEV28_SDMMC4_RX = 28,
45 /* 29 - 32 not used */
46 DB5500_DMA_DEV33_SDMMC0_RX = 33,
47 DB5500_DMA_DEV34_SDMMC1_RX = 34,
48 DB5500_DMA_DEV35_SDMMC2_RX = 35,
49 DB5500_DMA_DEV36_SDMMC3_RX = 36,
50 DB5500_DMA_DEV37_SDMMC4_RX = 37,
51 DB5500_DMA_DEV38_USB_OTG_IEP_8 = 38,
52 DB5500_DMA_DEV39_USB_OTG_IEP_1_9 = 39,
53 DB5500_DMA_DEV40_USB_OTG_IEP_2_10 = 40,
54 DB5500_DMA_DEV41_USB_OTG_IEP_3_11 = 41,
55 DB5500_DMA_DEV42_USB_OTG_IEP_4_12 = 42,
56 DB5500_DMA_DEV43_USB_OTG_IEP_5_13 = 43,
57 DB5500_DMA_DEV44_USB_OTG_IEP_6_14 = 44,
58 DB5500_DMA_DEV45_USB_OTG_IEP_7_15 = 45,
59 /* 46 not used */
60 DB5500_DMA_DEV47_MCDE_RX = 47,
61 DB5500_DMA_DEV48_CRYPTO1_RX = 48,
62 /* 49, 50 not used */
63 DB5500_DMA_DEV49_I2C1_RX = 51,
64 DB5500_DMA_DEV50_I2C3_RX = 52,
65 DB5500_DMA_DEV51_I2C2_RX = 53,
66 /* 54 - 60 not used */
67 DB5500_DMA_DEV61_CRYPTO0_RX = 61,
68 /* 62, 63 not used */
69};
70
71enum dma_dest_dev_type {
72 DB5500_DMA_DEV0_SPI0_TX = 0,
73 DB5500_DMA_DEV1_SPI1_TX = 1,
74 DB5500_DMA_DEV2_SPI2_TX = 2,
75 DB5500_DMA_DEV3_SPI3_TX = 3,
76 DB5500_DMA_DEV4_USB_OTG_OEP_1_9 = 4,
77 DB5500_DMA_DEV5_USB_OTG_OEP_2_10 = 5,
78 DB5500_DMA_DEV6_USB_OTG_OEP_3_11 = 6,
79 DB5500_DMA_DEV7_IRRC_TX = 7,
80 DB5500_DMA_DEV8_IRDA_FIFO_TX = 8,
81 DB5500_DMA_DEV9_MSP0_TX = 9,
82 DB5500_DMA_DEV10_MSP1_TX = 10,
83 DB5500_DMA_DEV11_MSP2_TX = 11,
84 DB5500_DMA_DEV12_UART0_TX = 12,
85 DB5500_DMA_DEV13_UART1_TX = 13,
86 DB5500_DMA_DEV14_UART2_TX = 14,
87 DB5500_DMA_DEV15_UART3_TX = 15,
88 DB5500_DMA_DEV16_USB_OTG_OEP_8 = 16,
89 DB5500_DMA_DEV17_USB_OTG_OEP_1_9 = 17,
90 DB5500_DMA_DEV18_USB_OTG_OEP_2_10 = 18,
91 DB5500_DMA_DEV19_USB_OTG_OEP_3_11 = 19,
92 DB5500_DMA_DEV20_USB_OTG_OEP_4_12 = 20,
93 DB5500_DMA_DEV21_USB_OTG_OEP_5_13 = 21,
94 DB5500_DMA_DEV22_USB_OTG_OEP_6_14 = 22,
95 DB5500_DMA_DEV23_USB_OTG_OEP_7_15 = 23,
96 DB5500_DMA_DEV24_SDMMC0_TX = 24,
97 DB5500_DMA_DEV25_SDMMC1_TX = 25,
98 DB5500_DMA_DEV26_SDMMC2_TX = 26,
99 DB5500_DMA_DEV27_SDMMC3_TX = 27,
100 DB5500_DMA_DEV28_SDMMC4_TX = 28,
101 /* 29 - 31 not used */
102 DB5500_DMA_DEV32_FSMC_TX = 32,
103 DB5500_DMA_DEV33_SDMMC0_TX = 33,
104 DB5500_DMA_DEV34_SDMMC1_TX = 34,
105 DB5500_DMA_DEV35_SDMMC2_TX = 35,
106 DB5500_DMA_DEV36_SDMMC3_TX = 36,
107 DB5500_DMA_DEV37_SDMMC4_TX = 37,
108 DB5500_DMA_DEV38_USB_OTG_OEP_8 = 38,
109 DB5500_DMA_DEV39_USB_OTG_OEP_1_9 = 39,
110 DB5500_DMA_DEV40_USB_OTG_OEP_2_10 = 40,
111 DB5500_DMA_DEV41_USB_OTG_OEP_3_11 = 41,
112 DB5500_DMA_DEV42_USB_OTG_OEP_4_12 = 42,
113 DB5500_DMA_DEV43_USB_OTG_OEP_5_13 = 43,
114 DB5500_DMA_DEV44_USB_OTG_OEP_6_14 = 44,
115 DB5500_DMA_DEV45_USB_OTG_OEP_7_15 = 45,
116 /* 46 not used */
117 DB5500_DMA_DEV47_STM_TX = 47,
118 DB5500_DMA_DEV48_CRYPTO1_TX = 48,
119 DB5500_DMA_DEV49_CRYPTO1_TX_HASH1_TX = 49,
120 DB5500_DMA_DEV50_HASH1_TX = 50,
121 DB5500_DMA_DEV51_I2C1_TX = 51,
122 DB5500_DMA_DEV52_I2C3_TX = 52,
123 DB5500_DMA_DEV53_I2C2_TX = 53,
124 /* 54, 55 not used */
125 DB5500_DMA_MEMCPY_TX_1 = 56,
126 DB5500_DMA_MEMCPY_TX_2 = 57,
127 DB5500_DMA_MEMCPY_TX_3 = 58,
128 DB5500_DMA_MEMCPY_TX_4 = 59,
129 DB5500_DMA_MEMCPY_TX_5 = 60,
130 DB5500_DMA_DEV61_CRYPTO0_TX = 61,
131 DB5500_DMA_DEV62_CRYPTO0_TX_HASH0_TX = 62,
132 DB5500_DMA_DEV63_HASH0_TX = 63,
133};
134
135#endif
diff --git a/arch/arm/mach-ux500/ste-dma40-db8500.h b/arch/arm/mach-ux500/ste-dma40-db8500.h
index 9d9d3797b3b0..a616419bea76 100644
--- a/arch/arm/mach-ux500/ste-dma40-db8500.h
+++ b/arch/arm/mach-ux500/ste-dma40-db8500.h
@@ -10,145 +10,135 @@
10#ifndef STE_DMA40_DB8500_H 10#ifndef STE_DMA40_DB8500_H
11#define STE_DMA40_DB8500_H 11#define STE_DMA40_DB8500_H
12 12
13#define STEDMA40_NR_DEV 64 13#define DB8500_DMA_NR_DEV 64
14 14
15enum dma_src_dev_type { 15enum dma_src_dev_type {
16 STEDMA40_DEV_SPI0_RX = 0, 16 DB8500_DMA_DEV0_SPI0_RX = 0,
17 STEDMA40_DEV_SD_MMC0_RX = 1, 17 DB8500_DMA_DEV1_SD_MMC0_RX = 1,
18 STEDMA40_DEV_SD_MMC1_RX = 2, 18 DB8500_DMA_DEV2_SD_MMC1_RX = 2,
19 STEDMA40_DEV_SD_MMC2_RX = 3, 19 DB8500_DMA_DEV3_SD_MMC2_RX = 3,
20 STEDMA40_DEV_I2C1_RX = 4, 20 DB8500_DMA_DEV4_I2C1_RX = 4,
21 STEDMA40_DEV_I2C3_RX = 5, 21 DB8500_DMA_DEV5_I2C3_RX = 5,
22 STEDMA40_DEV_I2C2_RX = 6, 22 DB8500_DMA_DEV6_I2C2_RX = 6,
23 STEDMA40_DEV_I2C4_RX = 7, /* Only on V1 */ 23 DB8500_DMA_DEV7_I2C4_RX = 7, /* Only on V1 and later */
24 STEDMA40_DEV_SSP0_RX = 8, 24 DB8500_DMA_DEV8_SSP0_RX = 8,
25 STEDMA40_DEV_SSP1_RX = 9, 25 DB8500_DMA_DEV9_SSP1_RX = 9,
26 STEDMA40_DEV_MCDE_RX = 10, 26 DB8500_DMA_DEV10_MCDE_RX = 10,
27 STEDMA40_DEV_UART2_RX = 11, 27 DB8500_DMA_DEV11_UART2_RX = 11,
28 STEDMA40_DEV_UART1_RX = 12, 28 DB8500_DMA_DEV12_UART1_RX = 12,
29 STEDMA40_DEV_UART0_RX = 13, 29 DB8500_DMA_DEV13_UART0_RX = 13,
30 STEDMA40_DEV_MSP2_RX = 14, 30 DB8500_DMA_DEV14_MSP2_RX = 14,
31 STEDMA40_DEV_I2C0_RX = 15, 31 DB8500_DMA_DEV15_I2C0_RX = 15,
32 STEDMA40_DEV_USB_OTG_IEP_8 = 16, 32 DB8500_DMA_DEV16_USB_OTG_IEP_7_15 = 16,
33 STEDMA40_DEV_USB_OTG_IEP_1_9 = 17, 33 DB8500_DMA_DEV17_USB_OTG_IEP_6_14 = 17,
34 STEDMA40_DEV_USB_OTG_IEP_2_10 = 18, 34 DB8500_DMA_DEV18_USB_OTG_IEP_5_13 = 18,
35 STEDMA40_DEV_USB_OTG_IEP_3_11 = 19, 35 DB8500_DMA_DEV19_USB_OTG_IEP_4_12 = 19,
36 STEDMA40_DEV_SLIM0_CH0_RX_HSI_RX_CH0 = 20, 36 DB8500_DMA_DEV20_SLIM0_CH0_RX_HSI_RX_CH0 = 20,
37 STEDMA40_DEV_SLIM0_CH1_RX_HSI_RX_CH1 = 21, 37 DB8500_DMA_DEV21_SLIM0_CH1_RX_HSI_RX_CH1 = 21,
38 STEDMA40_DEV_SLIM0_CH2_RX_HSI_RX_CH2 = 22, 38 DB8500_DMA_DEV22_SLIM0_CH2_RX_HSI_RX_CH2 = 22,
39 STEDMA40_DEV_SLIM0_CH3_RX_HSI_RX_CH3 = 23, 39 DB8500_DMA_DEV23_SLIM0_CH3_RX_HSI_RX_CH3 = 23,
40 STEDMA40_DEV_SRC_SXA0_RX_TX = 24, 40 DB8500_DMA_DEV24_SRC_SXA0_RX_TX = 24,
41 STEDMA40_DEV_SRC_SXA1_RX_TX = 25, 41 DB8500_DMA_DEV25_SRC_SXA1_RX_TX = 25,
42 STEDMA40_DEV_SRC_SXA2_RX_TX = 26, 42 DB8500_DMA_DEV26_SRC_SXA2_RX_TX = 26,
43 STEDMA40_DEV_SRC_SXA3_RX_TX = 27, 43 DB8500_DMA_DEV27_SRC_SXA3_RX_TX = 27,
44 STEDMA40_DEV_SD_MM2_RX = 28, 44 DB8500_DMA_DEV28_SD_MM2_RX = 28,
45 STEDMA40_DEV_SD_MM0_RX = 29, 45 DB8500_DMA_DEV29_SD_MM0_RX = 29,
46 STEDMA40_DEV_MSP1_RX = 30, 46 DB8500_DMA_DEV30_MSP1_RX = 30,
47 /* 47 /* On DB8500v2, MSP3 RX replaces MSP1 RX */
48 * This channel is either SlimBus or MSP, 48 DB8500_DMA_DEV30_MSP3_RX = 30,
49 * never both at the same time. 49 DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX = 31,
50 */ 50 DB8500_DMA_DEV32_SD_MM1_RX = 32,
51 STEDMA40_SLIM0_CH0_RX = 31, 51 DB8500_DMA_DEV33_SPI2_RX = 33,
52 STEDMA40_DEV_MSP0_RX = 31, 52 DB8500_DMA_DEV34_I2C3_RX2 = 34,
53 STEDMA40_DEV_SD_MM1_RX = 32, 53 DB8500_DMA_DEV35_SPI1_RX = 35,
54 STEDMA40_DEV_SPI2_RX = 33, 54 DB8500_DMA_DEV36_USB_OTG_IEP_3_11 = 36,
55 STEDMA40_DEV_I2C3_RX2 = 34, 55 DB8500_DMA_DEV37_USB_OTG_IEP_2_10 = 37,
56 STEDMA40_DEV_SPI1_RX = 35, 56 DB8500_DMA_DEV38_USB_OTG_IEP_1_9 = 38,
57 STEDMA40_DEV_USB_OTG_IEP_4_12 = 36, 57 DB8500_DMA_DEV39_USB_OTG_IEP_8 = 39,
58 STEDMA40_DEV_USB_OTG_IEP_5_13 = 37, 58 DB8500_DMA_DEV40_SPI3_RX = 40,
59 STEDMA40_DEV_USB_OTG_IEP_6_14 = 38, 59 DB8500_DMA_DEV41_SD_MM3_RX = 41,
60 STEDMA40_DEV_USB_OTG_IEP_7_15 = 39, 60 DB8500_DMA_DEV42_SD_MM4_RX = 42,
61 STEDMA40_DEV_SPI3_RX = 40, 61 DB8500_DMA_DEV43_SD_MM5_RX = 43,
62 STEDMA40_DEV_SD_MM3_RX = 41, 62 DB8500_DMA_DEV44_SRC_SXA4_RX_TX = 44,
63 STEDMA40_DEV_SD_MM4_RX = 42, 63 DB8500_DMA_DEV45_SRC_SXA5_RX_TX = 45,
64 STEDMA40_DEV_SD_MM5_RX = 43, 64 DB8500_DMA_DEV46_SLIM0_CH8_RX_SRC_SXA6_RX_TX = 46,
65 STEDMA40_DEV_SRC_SXA4_RX_TX = 44, 65 DB8500_DMA_DEV47_SLIM0_CH9_RX_SRC_SXA7_RX_TX = 47,
66 STEDMA40_DEV_SRC_SXA5_RX_TX = 45, 66 DB8500_DMA_DEV48_CAC1_RX = 48,
67 STEDMA40_DEV_SRC_SXA6_RX_TX = 46, 67 /* 49, 50 and 51 are not used */
68 STEDMA40_DEV_SRC_SXA7_RX_TX = 47, 68 DB8500_DMA_DEV52_SLIM0_CH4_RX_HSI_RX_CH4 = 52,
69 STEDMA40_DEV_CAC1_RX = 48, 69 DB8500_DMA_DEV53_SLIM0_CH5_RX_HSI_RX_CH5 = 53,
70 /* RX channels 49 and 50 are unused */ 70 DB8500_DMA_DEV54_SLIM0_CH6_RX_HSI_RX_CH6 = 54,
71 STEDMA40_DEV_MSHC_RX = 51, 71 DB8500_DMA_DEV55_SLIM0_CH7_RX_HSI_RX_CH7 = 55,
72 STEDMA40_DEV_SLIM1_CH0_RX_HSI_RX_CH4 = 52, 72 /* 56, 57, 58, 59 and 60 are not used */
73 STEDMA40_DEV_SLIM1_CH1_RX_HSI_RX_CH5 = 53, 73 DB8500_DMA_DEV61_CAC0_RX = 61,
74 STEDMA40_DEV_SLIM1_CH2_RX_HSI_RX_CH6 = 54, 74 /* 62 and 63 are not used */
75 STEDMA40_DEV_SLIM1_CH3_RX_HSI_RX_CH7 = 55,
76 /* RX channels 56 thru 60 are unused */
77 STEDMA40_DEV_CAC0_RX = 61,
78 /* RX channels 62 and 63 are unused */
79}; 75};
80 76
81enum dma_dest_dev_type { 77enum dma_dest_dev_type {
82 STEDMA40_DEV_SPI0_TX = 0, 78 DB8500_DMA_DEV0_SPI0_TX = 0,
83 STEDMA40_DEV_SD_MMC0_TX = 1, 79 DB8500_DMA_DEV1_SD_MMC0_TX = 1,
84 STEDMA40_DEV_SD_MMC1_TX = 2, 80 DB8500_DMA_DEV2_SD_MMC1_TX = 2,
85 STEDMA40_DEV_SD_MMC2_TX = 3, 81 DB8500_DMA_DEV3_SD_MMC2_TX = 3,
86 STEDMA40_DEV_I2C1_TX = 4, 82 DB8500_DMA_DEV4_I2C1_TX = 4,
87 STEDMA40_DEV_I2C3_TX = 5, 83 DB8500_DMA_DEV5_I2C3_TX = 5,
88 STEDMA40_DEV_I2C2_TX = 6, 84 DB8500_DMA_DEV6_I2C2_TX = 6,
89 STEDMA50_DEV_I2C4_TX = 7, /* Only on V1 */ 85 DB8500_DMA_DEV7_I2C4_TX = 7, /* Only on V1 and later */
90 STEDMA40_DEV_SSP0_TX = 8, 86 DB8500_DMA_DEV8_SSP0_TX = 8,
91 STEDMA40_DEV_SSP1_TX = 9, 87 DB8500_DMA_DEV9_SSP1_TX = 9,
92 /* TX channel 10 is unused */ 88 /* 10 is not used*/
93 STEDMA40_DEV_UART2_TX = 11, 89 DB8500_DMA_DEV11_UART2_TX = 11,
94 STEDMA40_DEV_UART1_TX = 12, 90 DB8500_DMA_DEV12_UART1_TX = 12,
95 STEDMA40_DEV_UART0_TX= 13, 91 DB8500_DMA_DEV13_UART0_TX = 13,
96 STEDMA40_DEV_MSP2_TX = 14, 92 DB8500_DMA_DEV14_MSP2_TX = 14,
97 STEDMA40_DEV_I2C0_TX = 15, 93 DB8500_DMA_DEV15_I2C0_TX = 15,
98 STEDMA40_DEV_USB_OTG_OEP_8 = 16, 94 DB8500_DMA_DEV16_USB_OTG_OEP_7_15 = 16,
99 STEDMA40_DEV_USB_OTG_OEP_1_9 = 17, 95 DB8500_DMA_DEV17_USB_OTG_OEP_6_14 = 17,
100 STEDMA40_DEV_USB_OTG_OEP_2_10= 18, 96 DB8500_DMA_DEV18_USB_OTG_OEP_5_13 = 18,
101 STEDMA40_DEV_USB_OTG_OEP_3_11 = 19, 97 DB8500_DMA_DEV19_USB_OTG_OEP_4_12 = 19,
102 STEDMA40_DEV_SLIM0_CH0_TX_HSI_TX_CH0 = 20, 98 DB8500_DMA_DEV20_SLIM0_CH0_TX_HSI_TX_CH0 = 20,
103 STEDMA40_DEV_SLIM0_CH1_TX_HSI_TX_CH1 = 21, 99 DB8500_DMA_DEV21_SLIM0_CH1_TX_HSI_TX_CH1 = 21,
104 STEDMA40_DEV_SLIM0_CH2_TX_HSI_TX_CH2 = 22, 100 DB8500_DMA_DEV22_SLIM0_CH2_TX_HSI_TX_CH2 = 22,
105 STEDMA40_DEV_SLIM0_CH3_TX_HSI_TX_CH3 = 23, 101 DB8500_DMA_DEV23_SLIM0_CH3_TX_HSI_TX_CH3 = 23,
106 STEDMA40_DEV_DST_SXA0_RX_TX = 24, 102 DB8500_DMA_DEV24_DST_SXA0_RX_TX = 24,
107 STEDMA40_DEV_DST_SXA1_RX_TX = 25, 103 DB8500_DMA_DEV25_DST_SXA1_RX_TX = 25,
108 STEDMA40_DEV_DST_SXA2_RX_TX = 26, 104 DB8500_DMA_DEV26_DST_SXA2_RX_TX = 26,
109 STEDMA40_DEV_DST_SXA3_RX_TX = 27, 105 DB8500_DMA_DEV27_DST_SXA3_RX_TX = 27,
110 STEDMA40_DEV_SD_MM2_TX = 28, 106 DB8500_DMA_DEV28_SD_MM2_TX = 28,
111 STEDMA40_DEV_SD_MM0_TX = 29, 107 DB8500_DMA_DEV29_SD_MM0_TX = 29,
112 STEDMA40_DEV_MSP1_TX = 30, 108 DB8500_DMA_DEV30_MSP1_TX = 30,
113 /* 109 DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX = 31,
114 * This channel is either SlimBus or MSP, 110 DB8500_DMA_DEV32_SD_MM1_TX = 32,
115 * never both at the same time. 111 DB8500_DMA_DEV33_SPI2_TX = 33,
116 */ 112 DB8500_DMA_DEV34_I2C3_TX2 = 34,
117 STEDMA40_SLIM0_CH0_TX = 31, 113 DB8500_DMA_DEV35_SPI1_TX = 35,
118 STEDMA40_DEV_MSP0_TX = 31, 114 DB8500_DMA_DEV36_USB_OTG_OEP_3_11 = 36,
119 STEDMA40_DEV_SD_MM1_TX = 32, 115 DB8500_DMA_DEV37_USB_OTG_OEP_2_10 = 37,
120 STEDMA40_DEV_SPI2_TX = 33, 116 DB8500_DMA_DEV38_USB_OTG_OEP_1_9 = 38,
121 /* Secondary I2C3 channel */ 117 DB8500_DMA_DEV39_USB_OTG_OEP_8 = 39,
122 STEDMA40_DEV_I2C3_TX2 = 34, 118 DB8500_DMA_DEV40_SPI3_TX = 40,
123 STEDMA40_DEV_SPI1_TX = 35, 119 DB8500_DMA_DEV41_SD_MM3_TX = 41,
124 STEDMA40_DEV_USB_OTG_OEP_4_12 = 36, 120 DB8500_DMA_DEV42_SD_MM4_TX = 42,
125 STEDMA40_DEV_USB_OTG_OEP_5_13 = 37, 121 DB8500_DMA_DEV43_SD_MM5_TX = 43,
126 STEDMA40_DEV_USB_OTG_OEP_6_14 = 38, 122 DB8500_DMA_DEV44_DST_SXA4_RX_TX = 44,
127 STEDMA40_DEV_USB_OTG_OEP_7_15 = 39, 123 DB8500_DMA_DEV45_DST_SXA5_RX_TX = 45,
128 STEDMA40_DEV_SPI3_TX = 40, 124 DB8500_DMA_DEV46_SLIM0_CH8_TX_DST_SXA6_RX_TX = 46,
129 STEDMA40_DEV_SD_MM3_TX = 41, 125 DB8500_DMA_DEV47_SLIM0_CH9_TX_DST_SXA7_RX_TX = 47,
130 STEDMA40_DEV_SD_MM4_TX = 42, 126 DB8500_DMA_DEV48_CAC1_TX = 48,
131 STEDMA40_DEV_SD_MM5_TX = 43, 127 DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49,
132 STEDMA40_DEV_DST_SXA4_RX_TX = 44, 128 DB8500_DMA_DEV50_HAC1_TX = 50,
133 STEDMA40_DEV_DST_SXA5_RX_TX = 45, 129 DB8500_DMA_MEMCPY_TX_0 = 51,
134 STEDMA40_DEV_DST_SXA6_RX_TX = 46, 130 DB8500_DMA_DEV52_SLIM1_CH4_TX_HSI_TX_CH4 = 52,
135 STEDMA40_DEV_DST_SXA7_RX_TX = 47, 131 DB8500_DMA_DEV53_SLIM1_CH5_TX_HSI_TX_CH5 = 53,
136 STEDMA40_DEV_CAC1_TX = 48, 132 DB8500_DMA_DEV54_SLIM1_CH6_TX_HSI_TX_CH6 = 54,
137 STEDMA40_DEV_CAC1_TX_HAC1_TX = 49, 133 DB8500_DMA_DEV55_SLIM1_CH7_TX_HSI_TX_CH7 = 55,
138 STEDMA40_DEV_HAC1_TX = 50, 134 DB8500_DMA_MEMCPY_TX_1 = 56,
139 STEDMA40_MEMCPY_TX_0 = 51, 135 DB8500_DMA_MEMCPY_TX_2 = 57,
140 STEDMA40_DEV_SLIM1_CH0_TX_HSI_TX_CH4 = 52, 136 DB8500_DMA_MEMCPY_TX_3 = 58,
141 STEDMA40_DEV_SLIM1_CH1_TX_HSI_TX_CH5 = 53, 137 DB8500_DMA_MEMCPY_TX_4 = 59,
142 STEDMA40_DEV_SLIM1_CH2_TX_HSI_TX_CH6 = 54, 138 DB8500_DMA_MEMCPY_TX_5 = 60,
143 STEDMA40_DEV_SLIM1_CH3_TX_HSI_TX_CH7 = 55, 139 DB8500_DMA_DEV61_CAC0_TX = 61,
144 STEDMA40_MEMCPY_TX_1 = 56, 140 DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62,
145 STEDMA40_MEMCPY_TX_2 = 57, 141 DB8500_DMA_DEV63_HAC0_TX = 63,
146 STEDMA40_MEMCPY_TX_3 = 58,
147 STEDMA40_MEMCPY_TX_4 = 59,
148 STEDMA40_MEMCPY_TX_5 = 60,
149 STEDMA40_DEV_CAC0_TX = 61,
150 STEDMA40_DEV_CAC0_TX_HAC0_TX = 62,
151 STEDMA40_DEV_HAC0_TX = 63,
152}; 142};
153 143
154#endif 144#endif
diff --git a/arch/arm/mach-versatile/include/mach/debug-macro.S b/arch/arm/mach-versatile/include/mach/debug-macro.S
index 6fea7199c626..eb2cf7dc5c44 100644
--- a/arch/arm/mach-versatile/include/mach/debug-macro.S
+++ b/arch/arm/mach-versatile/include/mach/debug-macro.S
@@ -11,13 +11,11 @@
11 * 11 *
12*/ 12*/
13 13
14 .macro addruart, rx, tmp 14 .macro addruart, rp, rv
15 mrc p15, 0, \rx, c1, c0 15 mov \rp, #0x001F0000
16 tst \rx, #1 @ MMU enabled? 16 orr \rp, \rp, #0x00001000
17 moveq \rx, #0x10000000 17 orr \rv, \rp, #0xf1000000 @ virtual base
18 movne \rx, #0xf1000000 @ virtual base 18 orr \rp, \rp, #0x10000000 @ physical base
19 orr \rx, \rx, #0x001F0000
20 orr \rx, \rx, #0x00001000
21 .endm 19 .endm
22 20
23#include <asm/hardware/debug-pl01x.S> 21#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-versatile/include/mach/vmalloc.h b/arch/arm/mach-versatile/include/mach/vmalloc.h
index 427e3612db5d..ebd8a2543d3b 100644
--- a/arch/arm/mach-versatile/include/mach/vmalloc.h
+++ b/arch/arm/mach-versatile/include/mach/vmalloc.h
@@ -18,4 +18,4 @@
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 20 */
21#define VMALLOC_END (PAGE_OFFSET + 0x18000000) 21#define VMALLOC_END 0xd8000000
diff --git a/arch/arm/mach-versatile/versatile_ab.c b/arch/arm/mach-versatile/versatile_ab.c
index bb8ec7724f79..aa9730fb13bf 100644
--- a/arch/arm/mach-versatile/versatile_ab.c
+++ b/arch/arm/mach-versatile/versatile_ab.c
@@ -35,8 +35,6 @@
35 35
36MACHINE_START(VERSATILE_AB, "ARM-Versatile AB") 36MACHINE_START(VERSATILE_AB, "ARM-Versatile AB")
37 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 37 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
38 .phys_io = 0x101f1000,
39 .io_pg_offst = ((0xf11f1000) >> 18) & 0xfffc,
40 .boot_params = 0x00000100, 38 .boot_params = 0x00000100,
41 .map_io = versatile_map_io, 39 .map_io = versatile_map_io,
42 .init_irq = versatile_init_irq, 40 .init_irq = versatile_init_irq,
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 239cd30fc4f5..bf469642a3f8 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -108,8 +108,6 @@ static void __init versatile_pb_init(void)
108 108
109MACHINE_START(VERSATILE_PB, "ARM-Versatile PB") 109MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
110 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 110 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
111 .phys_io = 0x101f1000,
112 .io_pg_offst = ((0xf11f1000) >> 18) & 0xfffc,
113 .boot_params = 0x00000100, 111 .boot_params = 0x00000100,
114 .map_io = versatile_map_io, 112 .map_io = versatile_map_io,
115 .init_irq = versatile_init_irq, 113 .init_irq = versatile_init_irq,
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 71fb17349520..c2e405a9e025 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -245,8 +245,6 @@ static void __init ct_ca9x4_init(void)
245} 245}
246 246
247MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4") 247MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
248 .phys_io = V2M_UART0 & SECTION_MASK,
249 .io_pg_offst = (__MMIO_P2V(V2M_UART0) >> 18) & 0xfffc,
250 .boot_params = PHYS_OFFSET + 0x00000100, 248 .boot_params = PHYS_OFFSET + 0x00000100,
251 .map_io = ct_ca9x4_map_io, 249 .map_io = ct_ca9x4_map_io,
252 .init_irq = ct_ca9x4_init_irq, 250 .init_irq = ct_ca9x4_init_irq,
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S
index 5167e2aceeba..050d65e02a42 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -12,12 +12,10 @@
12 12
13#define DEBUG_LL_UART_OFFSET 0x00009000 13#define DEBUG_LL_UART_OFFSET 0x00009000
14 14
15 .macro addruart,rx,tmp 15 .macro addruart,rp,rv
16 mrc p15, 0, \rx, c1, c0 16 mov \rp, #DEBUG_LL_UART_OFFSET
17 tst \rx, #1 @ MMU enabled? 17 orr \rv, \rp, #0xf8000000 @ virtual base
18 moveq \rx, #0x10000000 18 orr \rp, \rp, #0x10000000 @ physical base
19 movne \rx, #0xf8000000 @ virtual base
20 orr \rx, \rx, #DEBUG_LL_UART_OFFSET
21 .endm 19 .endm
22 20
23#include <asm/hardware/debug-pl01x.S> 21#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h
index 72a9621ed087..5a6da4fd247e 100644
--- a/arch/arm/mach-vexpress/include/mach/smp.h
+++ b/arch/arm/mach-vexpress/include/mach/smp.h
@@ -2,14 +2,7 @@
2#define __MACH_SMP_H 2#define __MACH_SMP_H
3 3
4#include <asm/hardware/gic.h> 4#include <asm/hardware/gic.h>
5 5#include <asm/smp_mpidr.h>
6#define hard_smp_processor_id() \
7 ({ \
8 unsigned int cpunum; \
9 __asm__("mrc p15, 0, %0, c0, c0, 5" \
10 : "=r" (cpunum)); \
11 cpunum &= 0x0F; \
12 })
13 6
14/* 7/*
15 * We use IRQ1 as the IPI 8 * We use IRQ1 as the IPI
diff --git a/arch/arm/mach-w90x900/mach-nuc910evb.c b/arch/arm/mach-w90x900/mach-nuc910evb.c
index ec05bda946f3..30fccde94fb8 100644
--- a/arch/arm/mach-w90x900/mach-nuc910evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc910evb.c
@@ -34,8 +34,6 @@ static void __init nuc910evb_init(void)
34 34
35MACHINE_START(W90P910EVB, "W90P910EVB") 35MACHINE_START(W90P910EVB, "W90P910EVB")
36 /* Maintainer: Wan ZongShun */ 36 /* Maintainer: Wan ZongShun */
37 .phys_io = W90X900_PA_UART,
38 .io_pg_offst = (((u32)W90X900_VA_UART) >> 18) & 0xfffc,
39 .boot_params = 0, 37 .boot_params = 0,
40 .map_io = nuc910evb_map_io, 38 .map_io = nuc910evb_map_io,
41 .init_irq = nuc900_init_irq, 39 .init_irq = nuc900_init_irq,
diff --git a/arch/arm/mach-w90x900/mach-nuc950evb.c b/arch/arm/mach-w90x900/mach-nuc950evb.c
index 04d295f89eb0..590c99b96dc1 100644
--- a/arch/arm/mach-w90x900/mach-nuc950evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc950evb.c
@@ -37,8 +37,6 @@ static void __init nuc950evb_init(void)
37 37
38MACHINE_START(W90P950EVB, "W90P950EVB") 38MACHINE_START(W90P950EVB, "W90P950EVB")
39 /* Maintainer: Wan ZongShun */ 39 /* Maintainer: Wan ZongShun */
40 .phys_io = W90X900_PA_UART,
41 .io_pg_offst = (((u32)W90X900_VA_UART) >> 18) & 0xfffc,
42 .boot_params = 0, 40 .boot_params = 0,
43 .map_io = nuc950evb_map_io, 41 .map_io = nuc950evb_map_io,
44 .init_irq = nuc900_init_irq, 42 .init_irq = nuc900_init_irq,
diff --git a/arch/arm/mach-w90x900/mach-nuc960evb.c b/arch/arm/mach-w90x900/mach-nuc960evb.c
index e3a46f19f2bc..e09c645d61b6 100644
--- a/arch/arm/mach-w90x900/mach-nuc960evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc960evb.c
@@ -34,8 +34,6 @@ static void __init nuc960evb_init(void)
34 34
35MACHINE_START(W90N960EVB, "W90N960EVB") 35MACHINE_START(W90N960EVB, "W90N960EVB")
36 /* Maintainer: Wan ZongShun */ 36 /* Maintainer: Wan ZongShun */
37 .phys_io = W90X900_PA_UART,
38 .io_pg_offst = (((u32)W90X900_VA_UART) >> 18) & 0xfffc,
39 .boot_params = 0, 37 .boot_params = 0,
40 .map_io = nuc960evb_map_io, 38 .map_io = nuc960evb_map_io,
41 .init_irq = nuc900_init_irq, 39 .init_irq = nuc900_init_irq,
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 86aa689ef1aa..99fa688dfadd 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -21,18 +21,22 @@
21#define D_CACHE_LINE_SIZE 32 21#define D_CACHE_LINE_SIZE 32
22#define BTB_FLUSH_SIZE 8 22#define BTB_FLUSH_SIZE 8
23 23
24#ifdef CONFIG_ARM_ERRATA_411920
25/* 24/*
26 * Invalidate the entire I cache (this code is a workaround for the ARM1136 25 * v6_flush_icache_all()
27 * erratum 411920 - Invalidate Instruction Cache operation can fail. This 26 *
28 * erratum is present in 1136, 1156 and 1176. It does not affect the MPCore. 27 * Flush the whole I-cache.
29 * 28 *
30 * Registers: 29 * ARM1136 erratum 411920 - Invalidate Instruction Cache operation can fail.
31 * r0 - set to 0 30 * This erratum is present in 1136, 1156 and 1176. It does not affect the
32 * r1 - corrupted 31 * MPCore.
32 *
33 * Registers:
34 * r0 - set to 0
35 * r1 - corrupted
33 */ 36 */
34ENTRY(v6_icache_inval_all) 37ENTRY(v6_flush_icache_all)
35 mov r0, #0 38 mov r0, #0
39#ifdef CONFIG_ARM_ERRATA_411920
36 mrs r1, cpsr 40 mrs r1, cpsr
37 cpsid ifa @ disable interrupts 41 cpsid ifa @ disable interrupts
38 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
@@ -43,8 +47,11 @@ ENTRY(v6_icache_inval_all)
43 .rept 11 @ ARM Ltd recommends at least 47 .rept 11 @ ARM Ltd recommends at least
44 nop @ 11 NOPs 48 nop @ 11 NOPs
45 .endr 49 .endr
46 mov pc, lr 50#else
51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
47#endif 52#endif
53 mov pc, lr
54ENDPROC(v6_flush_icache_all)
48 55
49/* 56/*
50 * v6_flush_cache_all() 57 * v6_flush_cache_all()
@@ -60,7 +67,7 @@ ENTRY(v6_flush_kern_cache_all)
60#ifndef CONFIG_ARM_ERRATA_411920 67#ifndef CONFIG_ARM_ERRATA_411920
61 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 68 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
62#else 69#else
63 b v6_icache_inval_all 70 b v6_flush_icache_all
64#endif 71#endif
65#else 72#else
66 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 73 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
@@ -138,7 +145,7 @@ ENTRY(v6_coherent_user_range)
138#ifndef CONFIG_ARM_ERRATA_411920 145#ifndef CONFIG_ARM_ERRATA_411920
139 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 146 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
140#else 147#else
141 b v6_icache_inval_all 148 b v6_flush_icache_all
142#endif 149#endif
143#else 150#else
144 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 151 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
@@ -312,6 +319,7 @@ ENDPROC(v6_dma_unmap_area)
312 319
313 .type v6_cache_fns, #object 320 .type v6_cache_fns, #object
314ENTRY(v6_cache_fns) 321ENTRY(v6_cache_fns)
322 .long v6_flush_icache_all
315 .long v6_flush_kern_cache_all 323 .long v6_flush_kern_cache_all
316 .long v6_flush_user_cache_all 324 .long v6_flush_user_cache_all
317 .long v6_flush_user_cache_range 325 .long v6_flush_user_cache_range
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 37c8157e116e..a3ebf7a4f49b 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -18,6 +18,21 @@
18#include "proc-macros.S" 18#include "proc-macros.S"
19 19
20/* 20/*
21 * v7_flush_icache_all()
22 *
23 * Flush the whole I-cache.
24 *
25 * Registers:
26 * r0 - set to 0
27 */
28ENTRY(v7_flush_icache_all)
29 mov r0, #0
30 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
31 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
32 mov pc, lr
33ENDPROC(v7_flush_icache_all)
34
35/*
21 * v7_flush_dcache_all() 36 * v7_flush_dcache_all()
22 * 37 *
23 * Flush the whole D-cache. 38 * Flush the whole D-cache.
@@ -91,11 +106,8 @@ ENTRY(v7_flush_kern_cache_all)
91 THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) 106 THUMB( stmfd sp!, {r4-r7, r9-r11, lr} )
92 bl v7_flush_dcache_all 107 bl v7_flush_dcache_all
93 mov r0, #0 108 mov r0, #0
94#ifdef CONFIG_SMP 109 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
95 mcr p15, 0, r0, c7, c1, 0 @ invalidate I-cache inner shareable 110 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
96#else
97 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
98#endif
99 ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) 111 ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} )
100 THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) 112 THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} )
101 mov pc, lr 113 mov pc, lr
@@ -171,11 +183,8 @@ ENTRY(v7_coherent_user_range)
171 cmp r0, r1 183 cmp r0, r1
172 blo 1b 184 blo 1b
173 mov r0, #0 185 mov r0, #0
174#ifdef CONFIG_SMP 186 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable
175 mcr p15, 0, r0, c7, c1, 6 @ invalidate BTB Inner Shareable 187 ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB
176#else
177 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
178#endif
179 dsb 188 dsb
180 isb 189 isb
181 mov pc, lr 190 mov pc, lr
@@ -309,6 +318,7 @@ ENDPROC(v7_dma_unmap_area)
309 318
310 .type v7_cache_fns, #object 319 .type v7_cache_fns, #object
311ENTRY(v7_cache_fns) 320ENTRY(v7_cache_fns)
321 .long v7_flush_icache_all
312 .long v7_flush_kern_cache_all 322 .long v7_flush_kern_cache_all
313 .long v7_flush_user_cache_all 323 .long v7_flush_user_cache_all
314 .long v7_flush_user_cache_range 324 .long v7_flush_user_cache_range
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index 598c51ad5071..b8061519ce77 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -73,7 +73,7 @@ void v4_mc_copy_user_highpage(struct page *to, struct page *from,
73{ 73{
74 void *kto = kmap_atomic(to, KM_USER1); 74 void *kto = kmap_atomic(to, KM_USER1);
75 75
76 if (test_and_clear_bit(PG_dcache_dirty, &from->flags)) 76 if (!test_and_set_bit(PG_dcache_clean, &from->flags))
77 __flush_dcache_page(page_mapping(from), from); 77 __flush_dcache_page(page_mapping(from), from);
78 78
79 spin_lock(&minicache_lock); 79 spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index f55fa1044f72..bdba6c65c901 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -79,7 +79,7 @@ static void v6_copy_user_highpage_aliasing(struct page *to,
79 unsigned int offset = CACHE_COLOUR(vaddr); 79 unsigned int offset = CACHE_COLOUR(vaddr);
80 unsigned long kfrom, kto; 80 unsigned long kfrom, kto;
81 81
82 if (test_and_clear_bit(PG_dcache_dirty, &from->flags)) 82 if (!test_and_set_bit(PG_dcache_clean, &from->flags))
83 __flush_dcache_page(page_mapping(from), from); 83 __flush_dcache_page(page_mapping(from), from);
84 84
85 /* FIXME: not highmem safe */ 85 /* FIXME: not highmem safe */
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 9920c0ae2096..649bbcd325bf 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -95,7 +95,7 @@ void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
95{ 95{
96 void *kto = kmap_atomic(to, KM_USER1); 96 void *kto = kmap_atomic(to, KM_USER1);
97 97
98 if (test_and_clear_bit(PG_dcache_dirty, &from->flags)) 98 if (!test_and_set_bit(PG_dcache_clean, &from->flags))
99 __flush_dcache_page(page_mapping(from), from); 99 __flush_dcache_page(page_mapping(from), from);
100 100
101 spin_lock(&minicache_lock); 101 spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 4bc43e535d3b..e4dd0646e859 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -523,6 +523,12 @@ void ___dma_page_dev_to_cpu(struct page *page, unsigned long off,
523 outer_inv_range(paddr, paddr + size); 523 outer_inv_range(paddr, paddr + size);
524 524
525 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); 525 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
526
527 /*
528 * Mark the D-cache clean for this page to avoid extra flushing.
529 */
530 if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE)
531 set_bit(PG_dcache_clean, &page->flags);
526} 532}
527EXPORT_SYMBOL(___dma_page_dev_to_cpu); 533EXPORT_SYMBOL(___dma_page_dev_to_cpu);
528 534
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 9b906dec1ca1..8440d952ba6d 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -28,6 +28,7 @@
28 28
29static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE; 29static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
30 30
31#if __LINUX_ARM_ARCH__ < 6
31/* 32/*
32 * We take the easy way out of this problem - we make the 33 * We take the easy way out of this problem - we make the
33 * PTE uncacheable. However, we leave the write buffer on. 34 * PTE uncacheable. However, we leave the write buffer on.
@@ -141,7 +142,7 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma,
141 * a page table, or changing an existing PTE. Basically, there are two 142 * a page table, or changing an existing PTE. Basically, there are two
142 * things that we need to take care of: 143 * things that we need to take care of:
143 * 144 *
144 * 1. If PG_dcache_dirty is set for the page, we need to ensure 145 * 1. If PG_dcache_clean is not set for the page, we need to ensure
145 * that any cache entries for the kernels virtual memory 146 * that any cache entries for the kernels virtual memory
146 * range are written back to the page. 147 * range are written back to the page.
147 * 2. If we have multiple shared mappings of the same space in 148 * 2. If we have multiple shared mappings of the same space in
@@ -168,10 +169,8 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
168 return; 169 return;
169 170
170 mapping = page_mapping(page); 171 mapping = page_mapping(page);
171#ifndef CONFIG_SMP 172 if (!test_and_set_bit(PG_dcache_clean, &page->flags))
172 if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
173 __flush_dcache_page(mapping, page); 173 __flush_dcache_page(mapping, page);
174#endif
175 if (mapping) { 174 if (mapping) {
176 if (cache_is_vivt()) 175 if (cache_is_vivt())
177 make_coherent(mapping, vma, addr, ptep, pfn); 176 make_coherent(mapping, vma, addr, ptep, pfn);
@@ -179,6 +178,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
179 __flush_icache_all(); 178 __flush_icache_all();
180 } 179 }
181} 180}
181#endif /* __LINUX_ARM_ARCH__ < 6 */
182 182
183/* 183/*
184 * Check whether the write buffer has physical address aliasing 184 * Check whether the write buffer has physical address aliasing
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 23b0b03af5ea..1e21e125fe3a 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -581,6 +581,19 @@ static struct fsr_info ifsr_info[] = {
581 { do_bad, SIGBUS, 0, "unknown 31" }, 581 { do_bad, SIGBUS, 0, "unknown 31" },
582}; 582};
583 583
584void __init
585hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *),
586 int sig, int code, const char *name)
587{
588 if (nr < 0 || nr >= ARRAY_SIZE(ifsr_info))
589 BUG();
590
591 ifsr_info[nr].fn = fn;
592 ifsr_info[nr].sig = sig;
593 ifsr_info[nr].code = code;
594 ifsr_info[nr].name = name;
595}
596
584asmlinkage void __exception 597asmlinkage void __exception
585do_PrefetchAbort(unsigned long addr, unsigned int ifsr, struct pt_regs *regs) 598do_PrefetchAbort(unsigned long addr, unsigned int ifsr, struct pt_regs *regs)
586{ 599{
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index c6844cb9b508..391ffae75098 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -17,6 +17,7 @@
17#include <asm/smp_plat.h> 17#include <asm/smp_plat.h>
18#include <asm/system.h> 18#include <asm/system.h>
19#include <asm/tlbflush.h> 19#include <asm/tlbflush.h>
20#include <asm/smp_plat.h>
20 21
21#include "mm.h" 22#include "mm.h"
22 23
@@ -39,6 +40,18 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
39 : "cc"); 40 : "cc");
40} 41}
41 42
43static void flush_icache_alias(unsigned long pfn, unsigned long vaddr, unsigned long len)
44{
45 unsigned long colour = CACHE_COLOUR(vaddr);
46 unsigned long offset = vaddr & (PAGE_SIZE - 1);
47 unsigned long to;
48
49 set_pte_ext(TOP_PTE(ALIAS_FLUSH_START) + colour, pfn_pte(pfn, PAGE_KERNEL), 0);
50 to = ALIAS_FLUSH_START + (colour << PAGE_SHIFT) + offset;
51 flush_tlb_kernel_page(to);
52 flush_icache_range(to, to + len);
53}
54
42void flush_cache_mm(struct mm_struct *mm) 55void flush_cache_mm(struct mm_struct *mm)
43{ 56{
44 if (cache_is_vivt()) { 57 if (cache_is_vivt()) {
@@ -89,16 +102,16 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
89 if (vma->vm_flags & VM_EXEC && icache_is_vivt_asid_tagged()) 102 if (vma->vm_flags & VM_EXEC && icache_is_vivt_asid_tagged())
90 __flush_icache_all(); 103 __flush_icache_all();
91} 104}
105
92#else 106#else
93#define flush_pfn_alias(pfn,vaddr) do { } while (0) 107#define flush_pfn_alias(pfn,vaddr) do { } while (0)
108#define flush_icache_alias(pfn,vaddr,len) do { } while (0)
94#endif 109#endif
95 110
96#ifdef CONFIG_SMP
97static void flush_ptrace_access_other(void *args) 111static void flush_ptrace_access_other(void *args)
98{ 112{
99 __flush_icache_all(); 113 __flush_icache_all();
100} 114}
101#endif
102 115
103static 116static
104void flush_ptrace_access(struct vm_area_struct *vma, struct page *page, 117void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
@@ -118,15 +131,16 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
118 return; 131 return;
119 } 132 }
120 133
121 /* VIPT non-aliasing cache */ 134 /* VIPT non-aliasing D-cache */
122 if (vma->vm_flags & VM_EXEC) { 135 if (vma->vm_flags & VM_EXEC) {
123 unsigned long addr = (unsigned long)kaddr; 136 unsigned long addr = (unsigned long)kaddr;
124 __cpuc_coherent_kern_range(addr, addr + len); 137 if (icache_is_vipt_aliasing())
125#ifdef CONFIG_SMP 138 flush_icache_alias(page_to_pfn(page), uaddr, len);
139 else
140 __cpuc_coherent_kern_range(addr, addr + len);
126 if (cache_ops_need_broadcast()) 141 if (cache_ops_need_broadcast())
127 smp_call_function(flush_ptrace_access_other, 142 smp_call_function(flush_ptrace_access_other,
128 NULL, 1); 143 NULL, 1);
129#endif
130 } 144 }
131} 145}
132 146
@@ -215,6 +229,36 @@ static void __flush_dcache_aliases(struct address_space *mapping, struct page *p
215 flush_dcache_mmap_unlock(mapping); 229 flush_dcache_mmap_unlock(mapping);
216} 230}
217 231
232#if __LINUX_ARM_ARCH__ >= 6
233void __sync_icache_dcache(pte_t pteval)
234{
235 unsigned long pfn;
236 struct page *page;
237 struct address_space *mapping;
238
239 if (!pte_present_user(pteval))
240 return;
241 if (cache_is_vipt_nonaliasing() && !pte_exec(pteval))
242 /* only flush non-aliasing VIPT caches for exec mappings */
243 return;
244 pfn = pte_pfn(pteval);
245 if (!pfn_valid(pfn))
246 return;
247
248 page = pfn_to_page(pfn);
249 if (cache_is_vipt_aliasing())
250 mapping = page_mapping(page);
251 else
252 mapping = NULL;
253
254 if (!test_and_set_bit(PG_dcache_clean, &page->flags))
255 __flush_dcache_page(mapping, page);
256 /* pte_exec() already checked above for non-aliasing VIPT cache */
257 if (cache_is_vipt_nonaliasing() || pte_exec(pteval))
258 __flush_icache_all();
259}
260#endif
261
218/* 262/*
219 * Ensure cache coherency between kernel mapping and userspace mapping 263 * Ensure cache coherency between kernel mapping and userspace mapping
220 * of this page. 264 * of this page.
@@ -246,17 +290,16 @@ void flush_dcache_page(struct page *page)
246 290
247 mapping = page_mapping(page); 291 mapping = page_mapping(page);
248 292
249#ifndef CONFIG_SMP 293 if (!cache_ops_need_broadcast() &&
250 if (!PageHighMem(page) && mapping && !mapping_mapped(mapping)) 294 mapping && !mapping_mapped(mapping))
251 set_bit(PG_dcache_dirty, &page->flags); 295 clear_bit(PG_dcache_clean, &page->flags);
252 else 296 else {
253#endif
254 {
255 __flush_dcache_page(mapping, page); 297 __flush_dcache_page(mapping, page);
256 if (mapping && cache_is_vivt()) 298 if (mapping && cache_is_vivt())
257 __flush_dcache_aliases(mapping, page); 299 __flush_dcache_aliases(mapping, page);
258 else if (mapping) 300 else if (mapping)
259 __flush_icache_all(); 301 __flush_icache_all();
302 set_bit(PG_dcache_clean, &page->flags);
260 } 303 }
261} 304}
262EXPORT_SYMBOL(flush_dcache_page); 305EXPORT_SYMBOL(flush_dcache_page);
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 7185b00650fe..36c4553ffcce 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -277,7 +277,7 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
277 277
278 /* Register the kernel text, kernel data and initrd with memblock. */ 278 /* Register the kernel text, kernel data and initrd with memblock. */
279#ifdef CONFIG_XIP_KERNEL 279#ifdef CONFIG_XIP_KERNEL
280 memblock_reserve(__pa(_data), _end - _data); 280 memblock_reserve(__pa(_sdata), _end - _sdata);
281#else 281#else
282 memblock_reserve(__pa(_stext), _end - _stext); 282 memblock_reserve(__pa(_stext), _end - _stext);
283#endif 283#endif
@@ -545,7 +545,7 @@ void __init mem_init(void)
545 545
546 MLK_ROUNDUP(__init_begin, __init_end), 546 MLK_ROUNDUP(__init_begin, __init_end),
547 MLK_ROUNDUP(_text, _etext), 547 MLK_ROUNDUP(_text, _etext),
548 MLK_ROUNDUP(_data, _edata)); 548 MLK_ROUNDUP(_sdata, _edata));
549 549
550#undef MLK 550#undef MLK
551#undef MLM 551#undef MLM
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index 4f5b39687df5..b0a98305055c 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -144,3 +144,25 @@ int valid_mmap_phys_addr_range(unsigned long pfn, size_t size)
144{ 144{
145 return !(pfn + (size >> PAGE_SHIFT) > 0x00100000); 145 return !(pfn + (size >> PAGE_SHIFT) > 0x00100000);
146} 146}
147
148#ifdef CONFIG_STRICT_DEVMEM
149
150#include <linux/ioport.h>
151
152/*
153 * devmem_is_allowed() checks to see if /dev/mem access to a certain
154 * address is valid. The argument is a physical page number.
155 * We mimic x86 here by disallowing access to system RAM as well as
156 * device-exclusive MMIO regions. This effectively disable read()/write()
157 * on /dev/mem.
158 */
159int devmem_is_allowed(unsigned long pfn)
160{
161 if (iomem_is_exclusive(pfn << PAGE_SHIFT))
162 return 0;
163 if (!page_is_ram(pfn))
164 return 1;
165 return 0;
166}
167
168#endif
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index e8ed9dc461fe..c32f731d56d3 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -310,9 +310,8 @@ static void __init build_mem_type_table(void)
310 cachepolicy = CPOLICY_WRITEBACK; 310 cachepolicy = CPOLICY_WRITEBACK;
311 ecc_mask = 0; 311 ecc_mask = 0;
312 } 312 }
313#ifdef CONFIG_SMP 313 if (is_smp())
314 cachepolicy = CPOLICY_WRITEALLOC; 314 cachepolicy = CPOLICY_WRITEALLOC;
315#endif
316 315
317 /* 316 /*
318 * Strip out features not present on earlier architectures. 317 * Strip out features not present on earlier architectures.
@@ -406,13 +405,11 @@ static void __init build_mem_type_table(void)
406 cp = &cache_policies[cachepolicy]; 405 cp = &cache_policies[cachepolicy];
407 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; 406 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
408 407
409#ifndef CONFIG_SMP
410 /* 408 /*
411 * Only use write-through for non-SMP systems 409 * Only use write-through for non-SMP systems
412 */ 410 */
413 if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH) 411 if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
414 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte; 412 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
415#endif
416 413
417 /* 414 /*
418 * Enable CPU-specific coherency if supported. 415 * Enable CPU-specific coherency if supported.
@@ -436,22 +433,23 @@ static void __init build_mem_type_table(void)
436 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 433 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
437 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; 434 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
438 435
439#ifdef CONFIG_SMP 436 if (is_smp()) {
440 /* 437 /*
441 * Mark memory with the "shared" attribute for SMP systems 438 * Mark memory with the "shared" attribute
442 */ 439 * for SMP systems
443 user_pgprot |= L_PTE_SHARED; 440 */
444 kern_pgprot |= L_PTE_SHARED; 441 user_pgprot |= L_PTE_SHARED;
445 vecs_pgprot |= L_PTE_SHARED; 442 kern_pgprot |= L_PTE_SHARED;
446 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; 443 vecs_pgprot |= L_PTE_SHARED;
447 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; 444 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
448 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; 445 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
449 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; 446 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
450 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; 447 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
451 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; 448 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
452 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; 449 mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
453 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; 450 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
454#endif 451 mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
452 }
455 } 453 }
456 454
457 /* 455 /*
@@ -829,8 +827,7 @@ static void __init sanity_check_meminfo(void)
829 * rather difficult. 827 * rather difficult.
830 */ 828 */
831 reason = "with VIPT aliasing cache"; 829 reason = "with VIPT aliasing cache";
832#ifdef CONFIG_SMP 830 } else if (is_smp() && tlb_ops_need_broadcast()) {
833 } else if (tlb_ops_need_broadcast()) {
834 /* 831 /*
835 * kmap_high needs to occasionally flush TLB entries, 832 * kmap_high needs to occasionally flush TLB entries,
836 * however, if the TLB entries need to be broadcast 833 * however, if the TLB entries need to be broadcast
@@ -840,7 +837,6 @@ static void __init sanity_check_meminfo(void)
840 * (must not be called with irqs off) 837 * (must not be called with irqs off)
841 */ 838 */
842 reason = "without hardware TLB ops broadcasting"; 839 reason = "without hardware TLB ops broadcasting";
843#endif
844 } 840 }
845 if (reason) { 841 if (reason) {
846 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n", 842 printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 203a4e944d9e..a6f5f8475b96 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -430,7 +430,7 @@ ENTRY(cpu_arm1020_set_pte_ext)
430#endif /* CONFIG_MMU */ 430#endif /* CONFIG_MMU */
431 mov pc, lr 431 mov pc, lr
432 432
433 __INIT 433 __CPUINIT
434 434
435 .type __arm1020_setup, #function 435 .type __arm1020_setup, #function
436__arm1020_setup: 436__arm1020_setup:
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 1a511e765909..afc06b9c3133 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -412,7 +412,7 @@ ENTRY(cpu_arm1020e_set_pte_ext)
412#endif /* CONFIG_MMU */ 412#endif /* CONFIG_MMU */
413 mov pc, lr 413 mov pc, lr
414 414
415 __INIT 415 __CPUINIT
416 416
417 .type __arm1020e_setup, #function 417 .type __arm1020e_setup, #function
418__arm1020e_setup: 418__arm1020e_setup:
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 1ffa4eb9c34f..8915e0ba3fe5 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -394,7 +394,7 @@ ENTRY(cpu_arm1022_set_pte_ext)
394#endif /* CONFIG_MMU */ 394#endif /* CONFIG_MMU */
395 mov pc, lr 395 mov pc, lr
396 396
397 __INIT 397 __CPUINIT
398 398
399 .type __arm1022_setup, #function 399 .type __arm1022_setup, #function
400__arm1022_setup: 400__arm1022_setup:
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 5697c34b95b0..ff446c5d476f 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -384,7 +384,7 @@ ENTRY(cpu_arm1026_set_pte_ext)
384 mov pc, lr 384 mov pc, lr
385 385
386 386
387 __INIT 387 __CPUINIT
388 388
389 .type __arm1026_setup, #function 389 .type __arm1026_setup, #function
390__arm1026_setup: 390__arm1026_setup:
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 64e0b327c7c5..6a7be1863edd 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -238,7 +238,7 @@ ENTRY(cpu_arm7_reset)
238 mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc 238 mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc
239 mov pc, r0 239 mov pc, r0
240 240
241 __INIT 241 __CPUINIT
242 242
243 .type __arm6_setup, #function 243 .type __arm6_setup, #function
244__arm6_setup: mov r0, #0 244__arm6_setup: mov r0, #0
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 9d96824134fc..c285395f44b2 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -113,7 +113,7 @@ ENTRY(cpu_arm720_reset)
113 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 113 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
114 mov pc, r0 114 mov pc, r0
115 115
116 __INIT 116 __CPUINIT
117 117
118 .type __arm710_setup, #function 118 .type __arm710_setup, #function
119__arm710_setup: 119__arm710_setup:
diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index 6c1a9ab059ae..38b27dcba727 100644
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -55,7 +55,7 @@ ENTRY(cpu_arm740_reset)
55 mcr p15, 0, ip, c1, c0, 0 @ ctrl register 55 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
56 mov pc, r0 56 mov pc, r0
57 57
58 __INIT 58 __CPUINIT
59 59
60 .type __arm740_setup, #function 60 .type __arm740_setup, #function
61__arm740_setup: 61__arm740_setup:
diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index 6a850dbba22e..0c9786de20af 100644
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -46,7 +46,7 @@ ENTRY(cpu_arm7tdmi_proc_fin)
46ENTRY(cpu_arm7tdmi_reset) 46ENTRY(cpu_arm7tdmi_reset)
47 mov pc, r0 47 mov pc, r0
48 48
49 __INIT 49 __CPUINIT
50 50
51 .type __arm7tdmi_setup, #function 51 .type __arm7tdmi_setup, #function
52__arm7tdmi_setup: 52__arm7tdmi_setup:
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 86f80aa56216..fecf570939f3 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -375,7 +375,7 @@ ENTRY(cpu_arm920_set_pte_ext)
375#endif 375#endif
376 mov pc, lr 376 mov pc, lr
377 377
378 __INIT 378 __CPUINIT
379 379
380 .type __arm920_setup, #function 380 .type __arm920_setup, #function
381__arm920_setup: 381__arm920_setup:
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index f76ce9b62883..e3cbf87c9480 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -379,7 +379,7 @@ ENTRY(cpu_arm922_set_pte_ext)
379#endif /* CONFIG_MMU */ 379#endif /* CONFIG_MMU */
380 mov pc, lr 380 mov pc, lr
381 381
382 __INIT 382 __CPUINIT
383 383
384 .type __arm922_setup, #function 384 .type __arm922_setup, #function
385__arm922_setup: 385__arm922_setup:
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 657bd3f7c153..572424c867b5 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -428,7 +428,7 @@ ENTRY(cpu_arm925_set_pte_ext)
428#endif /* CONFIG_MMU */ 428#endif /* CONFIG_MMU */
429 mov pc, lr 429 mov pc, lr
430 430
431 __INIT 431 __CPUINIT
432 432
433 .type __arm925_setup, #function 433 .type __arm925_setup, #function
434__arm925_setup: 434__arm925_setup:
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 73f1f3c68910..63d168b4ebe6 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -389,7 +389,7 @@ ENTRY(cpu_arm926_set_pte_ext)
389#endif 389#endif
390 mov pc, lr 390 mov pc, lr
391 391
392 __INIT 392 __CPUINIT
393 393
394 .type __arm926_setup, #function 394 .type __arm926_setup, #function
395__arm926_setup: 395__arm926_setup:
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index fffb061a45a5..f6a62822418e 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -264,7 +264,7 @@ ENTRY(arm940_cache_fns)
264 .long arm940_dma_unmap_area 264 .long arm940_dma_unmap_area
265 .long arm940_dma_flush_range 265 .long arm940_dma_flush_range
266 266
267 __INIT 267 __CPUINIT
268 268
269 .type __arm940_setup, #function 269 .type __arm940_setup, #function
270__arm940_setup: 270__arm940_setup:
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 249a6053760a..ea2e7f2eb95b 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -317,7 +317,7 @@ ENTRY(cpu_arm946_dcache_clean_area)
317 mcr p15, 0, r0, c7, c10, 4 @ drain WB 317 mcr p15, 0, r0, c7, c10, 4 @ drain WB
318 mov pc, lr 318 mov pc, lr
319 319
320 __INIT 320 __CPUINIT
321 321
322 .type __arm946_setup, #function 322 .type __arm946_setup, #function
323__arm946_setup: 323__arm946_setup:
diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index db475667fac2..db67e3134d7a 100644
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -46,7 +46,7 @@ ENTRY(cpu_arm9tdmi_proc_fin)
46ENTRY(cpu_arm9tdmi_reset) 46ENTRY(cpu_arm9tdmi_reset)
47 mov pc, r0 47 mov pc, r0
48 48
49 __INIT 49 __CPUINIT
50 50
51 .type __arm9tdmi_setup, #function 51 .type __arm9tdmi_setup, #function
52__arm9tdmi_setup: 52__arm9tdmi_setup:
diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S
index 7803fdf70029..7c9ad621f0e6 100644
--- a/arch/arm/mm/proc-fa526.S
+++ b/arch/arm/mm/proc-fa526.S
@@ -134,7 +134,7 @@ ENTRY(cpu_fa526_set_pte_ext)
134#endif 134#endif
135 mov pc, lr 135 mov pc, lr
136 136
137 __INIT 137 __CPUINIT
138 138
139 .type __fa526_setup, #function 139 .type __fa526_setup, #function
140__fa526_setup: 140__fa526_setup:
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index b304d0104a4e..578da69200cf 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -494,7 +494,7 @@ ENTRY(cpu_feroceon_set_pte_ext)
494#endif 494#endif
495 mov pc, lr 495 mov pc, lr
496 496
497 __INIT 497 __CPUINIT
498 498
499 .type __feroceon_setup, #function 499 .type __feroceon_setup, #function
500__feroceon_setup: 500__feroceon_setup:
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index 5f6892fcc167..4458ee6aa713 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -338,7 +338,7 @@ ENTRY(cpu_mohawk_set_pte_ext)
338 mcr p15, 0, r0, c7, c10, 4 @ drain WB 338 mcr p15, 0, r0, c7, c10, 4 @ drain WB
339 mov pc, lr 339 mov pc, lr
340 340
341 __INIT 341 __CPUINIT
342 342
343 .type __mohawk_setup, #function 343 .type __mohawk_setup, #function
344__mohawk_setup: 344__mohawk_setup:
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index a201eb04b5e1..5aa8d59c2e85 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -156,7 +156,7 @@ ENTRY(cpu_sa110_set_pte_ext)
156#endif 156#endif
157 mov pc, lr 157 mov pc, lr
158 158
159 __INIT 159 __CPUINIT
160 160
161 .type __sa110_setup, #function 161 .type __sa110_setup, #function
162__sa110_setup: 162__sa110_setup:
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 7ddc4805bf97..2ac4e6f10713 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -169,7 +169,7 @@ ENTRY(cpu_sa1100_set_pte_ext)
169#endif 169#endif
170 mov pc, lr 170 mov pc, lr
171 171
172 __INIT 172 __CPUINIT
173 173
174 .type __sa1100_setup, #function 174 .type __sa1100_setup, #function
175__sa1100_setup: 175__sa1100_setup:
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 22aac8515196..59a7e1ffe7bc 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -30,13 +30,10 @@
30#define TTB_RGN_WT (2 << 3) 30#define TTB_RGN_WT (2 << 3)
31#define TTB_RGN_WB (3 << 3) 31#define TTB_RGN_WB (3 << 3)
32 32
33#ifndef CONFIG_SMP 33#define TTB_FLAGS_UP TTB_RGN_WBWA
34#define TTB_FLAGS TTB_RGN_WBWA 34#define PMD_FLAGS_UP PMD_SECT_WB
35#define PMD_FLAGS PMD_SECT_WB 35#define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S
36#else 36#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
37#define TTB_FLAGS TTB_RGN_WBWA|TTB_S
38#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S
39#endif
40 37
41ENTRY(cpu_v6_proc_init) 38ENTRY(cpu_v6_proc_init)
42 mov pc, lr 39 mov pc, lr
@@ -97,7 +94,8 @@ ENTRY(cpu_v6_switch_mm)
97#ifdef CONFIG_MMU 94#ifdef CONFIG_MMU
98 mov r2, #0 95 mov r2, #0
99 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 96 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
100 orr r0, r0, #TTB_FLAGS 97 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
98 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
101 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 99 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
102 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer 100 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
103 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 101 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
@@ -137,7 +135,7 @@ cpu_pj4_name:
137 135
138 .align 136 .align
139 137
140 __INIT 138 __CPUINIT
141 139
142/* 140/*
143 * __v6_setup 141 * __v6_setup
@@ -156,9 +154,11 @@ cpu_pj4_name:
156 */ 154 */
157__v6_setup: 155__v6_setup:
158#ifdef CONFIG_SMP 156#ifdef CONFIG_SMP
159 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode 157 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode
158 ALT_UP(nop)
160 orr r0, r0, #0x20 159 orr r0, r0, #0x20
161 mcr p15, 0, r0, c1, c0, 1 160 ALT_SMP(mcr p15, 0, r0, c1, c0, 1)
161 ALT_UP(nop)
162#endif 162#endif
163 163
164 mov r0, #0 164 mov r0, #0
@@ -169,7 +169,8 @@ __v6_setup:
169#ifdef CONFIG_MMU 169#ifdef CONFIG_MMU
170 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs 170 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
171 mcr p15, 0, r0, c2, c0, 2 @ TTB control register 171 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
172 orr r4, r4, #TTB_FLAGS 172 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
173 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
173 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 174 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
174#endif /* CONFIG_MMU */ 175#endif /* CONFIG_MMU */
175 adr r5, v6_crval 176 adr r5, v6_crval
@@ -192,6 +193,8 @@ __v6_setup:
192v6_crval: 193v6_crval:
193 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c 194 crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
194 195
196 __INITDATA
197
195 .type v6_processor_functions, #object 198 .type v6_processor_functions, #object
196ENTRY(v6_processor_functions) 199ENTRY(v6_processor_functions)
197 .word v6_early_abort 200 .word v6_early_abort
@@ -205,6 +208,8 @@ ENTRY(v6_processor_functions)
205 .word cpu_v6_set_pte_ext 208 .word cpu_v6_set_pte_ext
206 .size v6_processor_functions, . - v6_processor_functions 209 .size v6_processor_functions, . - v6_processor_functions
207 210
211 .section ".rodata"
212
208 .type cpu_arch_name, #object 213 .type cpu_arch_name, #object
209cpu_arch_name: 214cpu_arch_name:
210 .asciz "armv6" 215 .asciz "armv6"
@@ -225,10 +230,16 @@ cpu_elf_name:
225__v6_proc_info: 230__v6_proc_info:
226 .long 0x0007b000 231 .long 0x0007b000
227 .long 0x0007f000 232 .long 0x0007f000
228 .long PMD_TYPE_SECT | \ 233 ALT_SMP(.long \
234 PMD_TYPE_SECT | \
229 PMD_SECT_AP_WRITE | \ 235 PMD_SECT_AP_WRITE | \
230 PMD_SECT_AP_READ | \ 236 PMD_SECT_AP_READ | \
231 PMD_FLAGS 237 PMD_FLAGS_SMP)
238 ALT_UP(.long \
239 PMD_TYPE_SECT | \
240 PMD_SECT_AP_WRITE | \
241 PMD_SECT_AP_READ | \
242 PMD_FLAGS_UP)
232 .long PMD_TYPE_SECT | \ 243 .long PMD_TYPE_SECT | \
233 PMD_SECT_XN | \ 244 PMD_SECT_XN | \
234 PMD_SECT_AP_WRITE | \ 245 PMD_SECT_AP_WRITE | \
@@ -249,10 +260,16 @@ __v6_proc_info:
249__pj4_v6_proc_info: 260__pj4_v6_proc_info:
250 .long 0x560f5810 261 .long 0x560f5810
251 .long 0xff0ffff0 262 .long 0xff0ffff0
252 .long PMD_TYPE_SECT | \ 263 ALT_SMP(.long \
264 PMD_TYPE_SECT | \
265 PMD_SECT_AP_WRITE | \
266 PMD_SECT_AP_READ | \
267 PMD_FLAGS_SMP)
268 ALT_UP(.long \
269 PMD_TYPE_SECT | \
253 PMD_SECT_AP_WRITE | \ 270 PMD_SECT_AP_WRITE | \
254 PMD_SECT_AP_READ | \ 271 PMD_SECT_AP_READ | \
255 PMD_FLAGS 272 PMD_FLAGS_UP)
256 .long PMD_TYPE_SECT | \ 273 .long PMD_TYPE_SECT | \
257 PMD_SECT_XN | \ 274 PMD_SECT_XN | \
258 PMD_SECT_AP_WRITE | \ 275 PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 197f21bed5e9..53cbe2225153 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -30,15 +30,13 @@
30#define TTB_IRGN_WT ((1 << 0) | (0 << 6)) 30#define TTB_IRGN_WT ((1 << 0) | (0 << 6))
31#define TTB_IRGN_WB ((1 << 0) | (1 << 6)) 31#define TTB_IRGN_WB ((1 << 0) | (1 << 6))
32 32
33#ifndef CONFIG_SMP
34/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ 33/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
35#define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB 34#define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB
36#define PMD_FLAGS PMD_SECT_WB 35#define PMD_FLAGS_UP PMD_SECT_WB
37#else 36
38/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ 37/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
39#define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA 38#define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
40#define PMD_FLAGS PMD_SECT_WBWA|PMD_SECT_S 39#define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S
41#endif
42 40
43ENTRY(cpu_v7_proc_init) 41ENTRY(cpu_v7_proc_init)
44 mov pc, lr 42 mov pc, lr
@@ -105,7 +103,8 @@ ENTRY(cpu_v7_switch_mm)
105#ifdef CONFIG_MMU 103#ifdef CONFIG_MMU
106 mov r2, #0 104 mov r2, #0
107 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 105 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
108 orr r0, r0, #TTB_FLAGS 106 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
107 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
109#ifdef CONFIG_ARM_ERRATA_430973 108#ifdef CONFIG_ARM_ERRATA_430973
110 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
111#endif 110#endif
@@ -169,7 +168,7 @@ cpu_v7_name:
169 .ascii "ARMv7 Processor" 168 .ascii "ARMv7 Processor"
170 .align 169 .align
171 170
172 __INIT 171 __CPUINIT
173 172
174/* 173/*
175 * __v7_setup 174 * __v7_setup
@@ -188,7 +187,8 @@ cpu_v7_name:
188 */ 187 */
189__v7_ca9mp_setup: 188__v7_ca9mp_setup:
190#ifdef CONFIG_SMP 189#ifdef CONFIG_SMP
191 mrc p15, 0, r0, c1, c0, 1 190 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
191 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
192 tst r0, #(1 << 6) @ SMP/nAMP mode enabled? 192 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
193 orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and 193 orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and
194 mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting 194 mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
@@ -270,7 +270,8 @@ __v7_setup:
270#ifdef CONFIG_MMU 270#ifdef CONFIG_MMU
271 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 271 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
272 mcr p15, 0, r10, c2, c0, 2 @ TTB control register 272 mcr p15, 0, r10, c2, c0, 2 @ TTB control register
273 orr r4, r4, #TTB_FLAGS 273 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
274 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
274 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 275 mcr p15, 0, r4, c2, c0, 1 @ load TTB1
275 mov r10, #0x1f @ domains 0, 1 = manager 276 mov r10, #0x1f @ domains 0, 1 = manager
276 mcr p15, 0, r10, c3, c0, 0 @ load domain access register 277 mcr p15, 0, r10, c3, c0, 0 @ load domain access register
@@ -332,6 +333,8 @@ v7_crval:
332__v7_setup_stack: 333__v7_setup_stack:
333 .space 4 * 11 @ 11 registers 334 .space 4 * 11 @ 11 registers
334 335
336 __INITDATA
337
335 .type v7_processor_functions, #object 338 .type v7_processor_functions, #object
336ENTRY(v7_processor_functions) 339ENTRY(v7_processor_functions)
337 .word v7_early_abort 340 .word v7_early_abort
@@ -345,6 +348,8 @@ ENTRY(v7_processor_functions)
345 .word cpu_v7_set_pte_ext 348 .word cpu_v7_set_pte_ext
346 .size v7_processor_functions, . - v7_processor_functions 349 .size v7_processor_functions, . - v7_processor_functions
347 350
351 .section ".rodata"
352
348 .type cpu_arch_name, #object 353 .type cpu_arch_name, #object
349cpu_arch_name: 354cpu_arch_name:
350 .asciz "armv7" 355 .asciz "armv7"
@@ -362,10 +367,16 @@ cpu_elf_name:
362__v7_ca9mp_proc_info: 367__v7_ca9mp_proc_info:
363 .long 0x410fc090 @ Required ID value 368 .long 0x410fc090 @ Required ID value
364 .long 0xff0ffff0 @ Mask for ID 369 .long 0xff0ffff0 @ Mask for ID
365 .long PMD_TYPE_SECT | \ 370 ALT_SMP(.long \
371 PMD_TYPE_SECT | \
366 PMD_SECT_AP_WRITE | \ 372 PMD_SECT_AP_WRITE | \
367 PMD_SECT_AP_READ | \ 373 PMD_SECT_AP_READ | \
368 PMD_FLAGS 374 PMD_FLAGS_SMP)
375 ALT_UP(.long \
376 PMD_TYPE_SECT | \
377 PMD_SECT_AP_WRITE | \
378 PMD_SECT_AP_READ | \
379 PMD_FLAGS_UP)
369 .long PMD_TYPE_SECT | \ 380 .long PMD_TYPE_SECT | \
370 PMD_SECT_XN | \ 381 PMD_SECT_XN | \
371 PMD_SECT_AP_WRITE | \ 382 PMD_SECT_AP_WRITE | \
@@ -388,10 +399,16 @@ __v7_ca9mp_proc_info:
388__v7_proc_info: 399__v7_proc_info:
389 .long 0x000f0000 @ Required ID value 400 .long 0x000f0000 @ Required ID value
390 .long 0x000f0000 @ Mask for ID 401 .long 0x000f0000 @ Mask for ID
391 .long PMD_TYPE_SECT | \ 402 ALT_SMP(.long \
403 PMD_TYPE_SECT | \
404 PMD_SECT_AP_WRITE | \
405 PMD_SECT_AP_READ | \
406 PMD_FLAGS_SMP)
407 ALT_UP(.long \
408 PMD_TYPE_SECT | \
392 PMD_SECT_AP_WRITE | \ 409 PMD_SECT_AP_WRITE | \
393 PMD_SECT_AP_READ | \ 410 PMD_SECT_AP_READ | \
394 PMD_FLAGS 411 PMD_FLAGS_UP)
395 .long PMD_TYPE_SECT | \ 412 .long PMD_TYPE_SECT | \
396 PMD_SECT_XN | \ 413 PMD_SECT_XN | \
397 PMD_SECT_AP_WRITE | \ 414 PMD_SECT_AP_WRITE | \
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 361a51e49030..cad07e403044 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -404,7 +404,7 @@ ENTRY(cpu_xsc3_set_pte_ext)
404 404
405 .align 405 .align
406 406
407 __INIT 407 __CPUINIT
408 408
409 .type __xsc3_setup, #function 409 .type __xsc3_setup, #function
410__xsc3_setup: 410__xsc3_setup:
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 14075979bcba..cb245edb2c2b 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -506,7 +506,7 @@ ENTRY(cpu_xscale_set_pte_ext)
506 506
507 .align 507 .align
508 508
509 __INIT 509 __CPUINIT
510 510
511 .type __xscale_setup, #function 511 .type __xscale_setup, #function
512__xscale_setup: 512__xscale_setup:
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index f3f288a9546d..53cd5b454673 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -13,6 +13,7 @@
13 */ 13 */
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/linkage.h> 15#include <linux/linkage.h>
16#include <asm/assembler.h>
16#include <asm/asm-offsets.h> 17#include <asm/asm-offsets.h>
17#include <asm/page.h> 18#include <asm/page.h>
18#include <asm/tlbflush.h> 19#include <asm/tlbflush.h>
@@ -41,20 +42,15 @@ ENTRY(v7wbi_flush_user_tlb_range)
41 orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA 42 orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
42 mov r1, r1, lsl #PAGE_SHIFT 43 mov r1, r1, lsl #PAGE_SHIFT
431: 441:
44#ifdef CONFIG_SMP 45 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
45 mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable) 46 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
46#else 47
47 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA
48#endif
49 add r0, r0, #PAGE_SZ 48 add r0, r0, #PAGE_SZ
50 cmp r0, r1 49 cmp r0, r1
51 blo 1b 50 blo 1b
52 mov ip, #0 51 mov ip, #0
53#ifdef CONFIG_SMP 52 ALT_SMP(mcr p15, 0, ip, c7, c1, 6) @ flush BTAC/BTB Inner Shareable
54 mcr p15, 0, ip, c7, c1, 6 @ flush BTAC/BTB Inner Shareable 53 ALT_UP(mcr p15, 0, ip, c7, c5, 6) @ flush BTAC/BTB
55#else
56 mcr p15, 0, ip, c7, c5, 6 @ flush BTAC/BTB
57#endif
58 dsb 54 dsb
59 mov pc, lr 55 mov pc, lr
60ENDPROC(v7wbi_flush_user_tlb_range) 56ENDPROC(v7wbi_flush_user_tlb_range)
@@ -74,20 +70,14 @@ ENTRY(v7wbi_flush_kern_tlb_range)
74 mov r0, r0, lsl #PAGE_SHIFT 70 mov r0, r0, lsl #PAGE_SHIFT
75 mov r1, r1, lsl #PAGE_SHIFT 71 mov r1, r1, lsl #PAGE_SHIFT
761: 721:
77#ifdef CONFIG_SMP 73 ALT_SMP(mcr p15, 0, r0, c8, c3, 1) @ TLB invalidate U MVA (shareable)
78 mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable) 74 ALT_UP(mcr p15, 0, r0, c8, c7, 1) @ TLB invalidate U MVA
79#else
80 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA
81#endif
82 add r0, r0, #PAGE_SZ 75 add r0, r0, #PAGE_SZ
83 cmp r0, r1 76 cmp r0, r1
84 blo 1b 77 blo 1b
85 mov r2, #0 78 mov r2, #0
86#ifdef CONFIG_SMP 79 ALT_SMP(mcr p15, 0, r2, c7, c1, 6) @ flush BTAC/BTB Inner Shareable
87 mcr p15, 0, r2, c7, c1, 6 @ flush BTAC/BTB Inner Shareable 80 ALT_UP(mcr p15, 0, r2, c7, c5, 6) @ flush BTAC/BTB
88#else
89 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
90#endif
91 dsb 81 dsb
92 isb 82 isb
93 mov pc, lr 83 mov pc, lr
@@ -99,5 +89,6 @@ ENDPROC(v7wbi_flush_kern_tlb_range)
99ENTRY(v7wbi_tlb_fns) 89ENTRY(v7wbi_tlb_fns)
100 .long v7wbi_flush_user_tlb_range 90 .long v7wbi_flush_user_tlb_range
101 .long v7wbi_flush_kern_tlb_range 91 .long v7wbi_flush_kern_tlb_range
102 .long v7wbi_tlb_flags 92 ALT_SMP(.long v7wbi_tlb_flags_smp)
93 ALT_UP(.long v7wbi_tlb_flags_up)
103 .size v7wbi_tlb_fns, . - v7wbi_tlb_fns 94 .size v7wbi_tlb_fns, . - v7wbi_tlb_fns
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 6785db4179b8..64e3a64520e0 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -92,6 +92,18 @@ config MXC_DEBUG_BOARD
92 data/address de-multiplexing and decode, signal level shift, 92 data/address de-multiplexing and decode, signal level shift,
93 interrupt control and various board functions. 93 interrupt control and various board functions.
94 94
95config HAVE_EPIT
96 bool
97
98config MXC_USE_EPIT
99 bool "Use EPIT instead of GPT"
100 depends on HAVE_EPIT
101 help
102 Use EPIT as the system timer on systems that have it. Normally you
103 don't have a reason to do so as the EPIT has the same features and
104 uses the same clocks as the GPT. Anyway, on some systems the GPT
105 may be in use for other purposes.
106
95config MXC_ULPI 107config MXC_ULPI
96 bool 108 bool
97 109
@@ -110,4 +122,8 @@ config ARCH_MXC_AUDMUX_V1
110config ARCH_MXC_AUDMUX_V2 122config ARCH_MXC_AUDMUX_V2
111 bool 123 bool
112 124
125config IRAM_ALLOC
126 bool
127 select GENERIC_ALLOCATOR
128
113endif 129endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 78d405ed8616..06875b4dd70f 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -10,9 +10,11 @@ obj-$(CONFIG_MXC_TZIC) += tzic.o
10 10
11obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o 11obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
12obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o 12obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
13obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
13obj-$(CONFIG_MXC_PWM) += pwm.o 14obj-$(CONFIG_MXC_PWM) += pwm.o
14obj-$(CONFIG_USB_EHCI_MXC) += ehci.o 15obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
15obj-$(CONFIG_MXC_ULPI) += ulpi.o 16obj-$(CONFIG_MXC_ULPI) += ulpi.o
17obj-$(CONFIG_MXC_USE_EPIT) += epit.o
16obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o 18obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
17obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o 19obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
18obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o 20obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index f9e7cdbd0005..62920490c0d6 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -186,7 +186,13 @@ EXPORT_SYMBOL_GPL(mxc_audmux_v2_configure_port);
186static int mxc_audmux_v2_init(void) 186static int mxc_audmux_v2_init(void)
187{ 187{
188 int ret; 188 int ret;
189 189#if defined(CONFIG_ARCH_MX5)
190 if (cpu_is_mx51()) {
191 audmux_base = MX51_IO_ADDRESS(MX51_AUDMUX_BASE_ADDR);
192 ret = 0;
193 return ret;
194 }
195#endif
190#if defined(CONFIG_ARCH_MX3) 196#if defined(CONFIG_ARCH_MX3)
191 if (cpu_is_mx31()) 197 if (cpu_is_mx31())
192 audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR); 198 audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR);
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index 9ab784b776f9..404799487f17 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -1,3 +1,10 @@
1config IMX_HAVE_PLATFORM_ESDHC
2 bool
3
4config IMX_HAVE_PLATFORM_FEC
5 bool
6 default y if ARCH_MX25 || SOC_IMX27 || ARCH_MX35 || ARCH_MX51
7
1config IMX_HAVE_PLATFORM_FLEXCAN 8config IMX_HAVE_PLATFORM_FLEXCAN
2 select HAVE_CAN_FLEXCAN 9 select HAVE_CAN_FLEXCAN
3 bool 10 bool
@@ -5,6 +12,9 @@ config IMX_HAVE_PLATFORM_FLEXCAN
5config IMX_HAVE_PLATFORM_IMX_I2C 12config IMX_HAVE_PLATFORM_IMX_I2C
6 bool 13 bool
7 14
15config IMX_HAVE_PLATFORM_IMX_SSI
16 bool
17
8config IMX_HAVE_PLATFORM_IMX_UART 18config IMX_HAVE_PLATFORM_IMX_UART
9 bool 19 bool
10 20
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index 347da5161f7e..0a3c1f089413 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -1,8 +1,9 @@
1ifdef CONFIG_CAN_FLEXCAN 1obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC) += platform-esdhc.o
2# the ifdef can be removed once the flexcan driver has been merged 2obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o
3obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o 3obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
4endif 4obj-y += platform-imx-dma.o
5obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o 5obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
6obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
6obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o 7obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
7obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o 8obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
8obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o 9obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o
diff --git a/arch/arm/plat-mxc/devices/platform-esdhc.c b/arch/arm/plat-mxc/devices/platform-esdhc.c
new file mode 100644
index 000000000000..2605bfa0dfb0
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-esdhc.c
@@ -0,0 +1,71 @@
1/*
2 * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11#include <mach/esdhc.h>
12
13#define imx_esdhc_imx_data_entry_single(soc, _id, hwid) \
14 { \
15 .id = _id, \
16 .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \
17 .irq = soc ## _INT_ESDHC ## hwid, \
18 }
19
20#define imx_esdhc_imx_data_entry(soc, id, hwid) \
21 [id] = imx_esdhc_imx_data_entry_single(soc, id, hwid)
22
23#ifdef CONFIG_ARCH_MX25
24const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst = {
25#define imx25_esdhc_data_entry(_id, _hwid) \
26 imx_esdhc_imx_data_entry(MX25, _id, _hwid)
27 imx25_esdhc_data_entry(0, 1),
28 imx25_esdhc_data_entry(1, 2),
29};
30#endif /* ifdef CONFIG_ARCH_MX25 */
31
32#ifdef CONFIG_ARCH_MX35
33const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst = {
34#define imx35_esdhc_data_entry(_id, _hwid) \
35 imx_esdhc_imx_data_entry(MX35, _id, _hwid)
36 imx35_esdhc_data_entry(0, 1),
37 imx35_esdhc_data_entry(1, 2),
38 imx35_esdhc_data_entry(2, 3),
39};
40#endif /* ifdef CONFIG_ARCH_MX35 */
41
42#ifdef CONFIG_ARCH_MX51
43const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst = {
44#define imx51_esdhc_data_entry(_id, _hwid) \
45 imx_esdhc_imx_data_entry(MX51, _id, _hwid)
46 imx51_esdhc_data_entry(0, 1),
47 imx51_esdhc_data_entry(1, 2),
48 imx51_esdhc_data_entry(2, 3),
49 imx51_esdhc_data_entry(3, 4),
50};
51#endif /* ifdef CONFIG_ARCH_MX51 */
52
53struct platform_device *__init imx_add_esdhc(
54 const struct imx_esdhc_imx_data *data,
55 const struct esdhc_platform_data *pdata)
56{
57 struct resource res[] = {
58 {
59 .start = data->iobase,
60 .end = data->iobase + SZ_16K - 1,
61 .flags = IORESOURCE_MEM,
62 }, {
63 .start = data->irq,
64 .end = data->irq,
65 .flags = IORESOURCE_IRQ,
66 },
67 };
68
69 return imx_add_platform_device("sdhci-esdhc-imx", data->id, res,
70 ARRAY_SIZE(res), pdata, sizeof(*pdata));
71}
diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c
new file mode 100644
index 000000000000..11d087f4e219
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-fec.c
@@ -0,0 +1,58 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/hardware.h>
11#include <mach/devices-common.h>
12
13#define imx_fec_data_entry_single(soc) \
14 { \
15 .iobase = soc ## _FEC_BASE_ADDR, \
16 .irq = soc ## _INT_FEC, \
17 }
18
19#ifdef CONFIG_ARCH_MX25
20const struct imx_fec_data imx25_fec_data __initconst =
21 imx_fec_data_entry_single(MX25);
22#endif /* ifdef CONFIG_ARCH_MX25 */
23
24#ifdef CONFIG_SOC_IMX27
25const struct imx_fec_data imx27_fec_data __initconst =
26 imx_fec_data_entry_single(MX27);
27#endif /* ifdef CONFIG_SOC_IMX27 */
28
29#ifdef CONFIG_ARCH_MX35
30const struct imx_fec_data imx35_fec_data __initconst =
31 imx_fec_data_entry_single(MX35);
32#endif
33
34#ifdef CONFIG_ARCH_MX51
35const struct imx_fec_data imx51_fec_data __initconst =
36 imx_fec_data_entry_single(MX51);
37#endif
38
39struct platform_device *__init imx_add_fec(
40 const struct imx_fec_data *data,
41 const struct fec_platform_data *pdata)
42{
43 struct resource res[] = {
44 {
45 .start = data->iobase,
46 .end = data->iobase + SZ_4K,
47 .flags = IORESOURCE_MEM,
48 }, {
49 .start = data->irq,
50 .end = data->irq,
51 .flags = IORESOURCE_IRQ,
52 },
53 };
54
55 return imx_add_platform_device("fec", 0 /* -1? */,
56 res, ARRAY_SIZE(res),
57 pdata, sizeof(*pdata));
58}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c
new file mode 100644
index 000000000000..02d989018059
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c
@@ -0,0 +1,129 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <linux/compiler.h>
10#include <linux/err.h>
11#include <linux/init.h>
12
13#include <mach/hardware.h>
14#include <mach/devices-common.h>
15#ifdef SDMA_IS_MERGED
16#include <mach/sdma.h>
17#else
18struct sdma_platform_data {
19 int sdma_version;
20 char *cpu_name;
21 int to_version;
22};
23#endif
24
25struct imx_imx_sdma_data {
26 resource_size_t iobase;
27 resource_size_t irq;
28 struct sdma_platform_data pdata;
29};
30
31#define imx_imx_sdma_data_entry_single(soc, _sdma_version, _cpu_name, _to_version)\
32 { \
33 .iobase = soc ## _SDMA ## _BASE_ADDR, \
34 .irq = soc ## _INT_SDMA, \
35 .pdata = { \
36 .sdma_version = _sdma_version, \
37 .cpu_name = _cpu_name, \
38 .to_version = _to_version, \
39 }, \
40 }
41
42#ifdef CONFIG_ARCH_MX25
43const struct imx_imx_sdma_data imx25_imx_sdma_data __initconst =
44 imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0);
45#endif /* ifdef CONFIG_ARCH_MX25 */
46
47#ifdef CONFIG_ARCH_MX31
48struct imx_imx_sdma_data imx31_imx_sdma_data __initdata =
49 imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0);
50#endif /* ifdef CONFIG_ARCH_MX31 */
51
52#ifdef CONFIG_ARCH_MX35
53struct imx_imx_sdma_data imx35_imx_sdma_data __initdata =
54 imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0);
55#endif /* ifdef CONFIG_ARCH_MX35 */
56
57#ifdef CONFIG_ARCH_MX51
58const struct imx_imx_sdma_data imx51_imx_sdma_data __initconst =
59 imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 0);
60#endif /* ifdef CONFIG_ARCH_MX51 */
61
62static struct platform_device __init __maybe_unused *imx_add_imx_sdma(
63 const struct imx_imx_sdma_data *data)
64{
65 struct resource res[] = {
66 {
67 .start = data->iobase,
68 .end = data->iobase + SZ_4K - 1,
69 .flags = IORESOURCE_MEM,
70 }, {
71 .start = data->irq,
72 .end = data->irq,
73 .flags = IORESOURCE_IRQ,
74 },
75 };
76
77 return imx_add_platform_device("imx-sdma", -1,
78 res, ARRAY_SIZE(res),
79 &data->pdata, sizeof(data->pdata));
80}
81
82static struct platform_device __init __maybe_unused *imx_add_imx_dma(void)
83{
84 return imx_add_platform_device("imx-dma", -1, NULL, 0, NULL, 0);
85}
86
87static int __init imxXX_add_imx_dma(void)
88{
89 struct platform_device *ret;
90
91#if defined(CONFIG_SOC_IMX21) || defined(CONFIG_SOC_IMX27)
92 if (cpu_is_mx21() || cpu_is_mx27())
93 ret = imx_add_imx_dma();
94 else
95#endif
96
97#if defined(CONFIG_ARCH_MX25)
98 if (cpu_is_mx25())
99 ret = imx_add_imx_sdma(&imx25_imx_sdma_data);
100 else
101#endif
102
103#if defined(CONFIG_ARCH_MX31)
104 if (cpu_is_mx31()) {
105 imx31_imx_sdma_data.pdata.to_version = mx31_revision() >> 4;
106 ret = imx_add_imx_sdma(&imx31_imx_sdma_data);
107 } else
108#endif
109
110#if defined(CONFIG_ARCH_MX35)
111 if (cpu_is_mx35()) {
112 imx35_imx_sdma_data.pdata.to_version = mx35_revision() >> 4;
113 ret = imx_add_imx_sdma(&imx35_imx_sdma_data);
114 } else
115#endif
116
117#if defined(CONFIG_ARCH_MX51)
118 if (cpu_is_mx51())
119 ret = imx_add_imx_sdma(&imx51_imx_sdma_data);
120 else
121#endif
122 ret = ERR_PTR(-ENODEV);
123
124 if (IS_ERR(ret))
125 return PTR_ERR(ret);
126
127 return 0;
128}
129arch_initcall(imxXX_add_imx_dma);
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
index d0af9f7d8aed..679588453aad 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -6,24 +6,95 @@
6 * the terms of the GNU General Public License version 2 as published by the 6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation. 7 * Free Software Foundation.
8 */ 8 */
9#include <mach/hardware.h>
9#include <mach/devices-common.h> 10#include <mach/devices-common.h>
10 11
11struct platform_device *__init imx_add_imx_i2c(int id, 12#define imx_imx_i2c_data_entry_single(soc, _id, _hwid, _size) \
12 resource_size_t iobase, resource_size_t iosize, int irq, 13 { \
14 .id = _id, \
15 .iobase = soc ## _I2C ## _hwid ## _BASE_ADDR, \
16 .iosize = _size, \
17 .irq = soc ## _INT_I2C ## _hwid, \
18 }
19
20#define imx_imx_i2c_data_entry(soc, _id, _hwid, _size) \
21 [_id] = imx_imx_i2c_data_entry_single(soc, _id, _hwid, _size)
22
23#ifdef CONFIG_SOC_IMX1
24const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst =
25 imx_imx_i2c_data_entry_single(MX1, 0, , SZ_4K);
26#endif /* ifdef CONFIG_SOC_IMX1 */
27
28#ifdef CONFIG_SOC_IMX21
29const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst =
30 imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K);
31#endif /* ifdef CONFIG_SOC_IMX21 */
32
33#ifdef CONFIG_ARCH_MX25
34const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = {
35#define imx25_imx_i2c_data_entry(_id, _hwid) \
36 imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K)
37 imx25_imx_i2c_data_entry(0, 1),
38 imx25_imx_i2c_data_entry(1, 2),
39 imx25_imx_i2c_data_entry(2, 3),
40};
41#endif /* ifdef CONFIG_ARCH_MX25 */
42
43#ifdef CONFIG_SOC_IMX27
44const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
45#define imx27_imx_i2c_data_entry(_id, _hwid) \
46 imx_imx_i2c_data_entry(MX27, _id, _hwid, SZ_4K)
47 imx27_imx_i2c_data_entry(0, 1),
48 imx27_imx_i2c_data_entry(1, 2),
49};
50#endif /* ifdef CONFIG_SOC_IMX27 */
51
52#ifdef CONFIG_ARCH_MX31
53const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = {
54#define imx31_imx_i2c_data_entry(_id, _hwid) \
55 imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K)
56 imx31_imx_i2c_data_entry(0, 1),
57 imx31_imx_i2c_data_entry(1, 2),
58 imx31_imx_i2c_data_entry(2, 3),
59};
60#endif /* ifdef CONFIG_ARCH_MX31 */
61
62#ifdef CONFIG_ARCH_MX35
63const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
64#define imx35_imx_i2c_data_entry(_id, _hwid) \
65 imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K)
66 imx35_imx_i2c_data_entry(0, 1),
67 imx35_imx_i2c_data_entry(1, 2),
68 imx35_imx_i2c_data_entry(2, 3),
69};
70#endif /* ifdef CONFIG_ARCH_MX35 */
71
72#ifdef CONFIG_ARCH_MX51
73const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
74#define imx51_imx_i2c_data_entry(_id, _hwid) \
75 imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K)
76 imx51_imx_i2c_data_entry(0, 1),
77 imx51_imx_i2c_data_entry(1, 2),
78};
79#endif /* ifdef CONFIG_ARCH_MX51 */
80
81struct platform_device *__init imx_add_imx_i2c(
82 const struct imx_imx_i2c_data *data,
13 const struct imxi2c_platform_data *pdata) 83 const struct imxi2c_platform_data *pdata)
14{ 84{
15 struct resource res[] = { 85 struct resource res[] = {
16 { 86 {
17 .start = iobase, 87 .start = data->iobase,
18 .end = iobase + iosize - 1, 88 .end = data->iobase + data->iosize - 1,
19 .flags = IORESOURCE_MEM, 89 .flags = IORESOURCE_MEM,
20 }, { 90 }, {
21 .start = irq, 91 .start = data->irq,
22 .end = irq, 92 .end = data->irq,
23 .flags = IORESOURCE_IRQ, 93 .flags = IORESOURCE_IRQ,
24 }, 94 },
25 }; 95 };
26 96
27 return imx_add_platform_device("imx-i2c", id, res, ARRAY_SIZE(res), 97 return imx_add_platform_device("imx-i2c", data->id,
98 res, ARRAY_SIZE(res),
28 pdata, sizeof(*pdata)); 99 pdata, sizeof(*pdata));
29} 100}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
new file mode 100644
index 000000000000..38a7a0b8f2f1
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
@@ -0,0 +1,107 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_imx_ssi_data_entry(soc, _id, _hwid, _size) \
13 [_id] = { \
14 .id = _id, \
15 .iobase = soc ## _SSI ## _hwid ## _BASE_ADDR, \
16 .iosize = _size, \
17 .irq = soc ## _INT_SSI ## _hwid, \
18 .dmatx0 = soc ## _DMA_REQ_SSI ## _hwid ## _TX0, \
19 .dmarx0 = soc ## _DMA_REQ_SSI ## _hwid ## _RX0, \
20 .dmatx1 = soc ## _DMA_REQ_SSI ## _hwid ## _TX1, \
21 .dmarx1 = soc ## _DMA_REQ_SSI ## _hwid ## _RX1, \
22 }
23
24#ifdef CONFIG_SOC_IMX21
25const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = {
26#define imx21_imx_ssi_data_entry(_id, _hwid) \
27 imx_imx_ssi_data_entry(MX21, _id, _hwid, SZ_4K)
28 imx21_imx_ssi_data_entry(0, 1),
29 imx21_imx_ssi_data_entry(1, 2),
30};
31#endif /* ifdef CONFIG_SOC_IMX21 */
32
33#ifdef CONFIG_ARCH_MX25
34const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = {
35#define imx25_imx_ssi_data_entry(_id, _hwid) \
36 imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K)
37 imx25_imx_ssi_data_entry(0, 1),
38 imx25_imx_ssi_data_entry(1, 2),
39};
40#endif /* ifdef CONFIG_ARCH_MX25 */
41
42#ifdef CONFIG_SOC_IMX27
43const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = {
44#define imx27_imx_ssi_data_entry(_id, _hwid) \
45 imx_imx_ssi_data_entry(MX27, _id, _hwid, SZ_4K)
46 imx27_imx_ssi_data_entry(0, 1),
47 imx27_imx_ssi_data_entry(1, 2),
48};
49#endif /* ifdef CONFIG_SOC_IMX27 */
50
51#ifdef CONFIG_ARCH_MX31
52const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = {
53#define imx31_imx_ssi_data_entry(_id, _hwid) \
54 imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K)
55 imx31_imx_ssi_data_entry(0, 1),
56 imx31_imx_ssi_data_entry(1, 2),
57};
58#endif /* ifdef CONFIG_ARCH_MX31 */
59
60#ifdef CONFIG_ARCH_MX35
61const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = {
62#define imx35_imx_ssi_data_entry(_id, _hwid) \
63 imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K)
64 imx35_imx_ssi_data_entry(0, 1),
65 imx35_imx_ssi_data_entry(1, 2),
66};
67#endif /* ifdef CONFIG_ARCH_MX35 */
68
69#ifdef CONFIG_ARCH_MX51
70const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = {
71#define imx51_imx_ssi_data_entry(_id, _hwid) \
72 imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K)
73 imx51_imx_ssi_data_entry(0, 1),
74 imx51_imx_ssi_data_entry(1, 2),
75};
76#endif /* ifdef CONFIG_ARCH_MX51 */
77
78struct platform_device *__init imx_add_imx_ssi(
79 const struct imx_imx_ssi_data *data,
80 const struct imx_ssi_platform_data *pdata)
81{
82 struct resource res[] = {
83 {
84 .start = data->iobase,
85 .end = data->iobase + data->iosize - 1,
86 .flags = IORESOURCE_MEM,
87 }, {
88 .start = data->irq,
89 .end = data->irq,
90 .flags = IORESOURCE_IRQ,
91 },
92#define DMARES(_name) { \
93 .name = #_name, \
94 .start = data->dma ## _name, \
95 .end = data->dma ## _name, \
96 .flags = IORESOURCE_DMA, \
97}
98 DMARES(tx0),
99 DMARES(rx0),
100 DMARES(tx1),
101 DMARES(rx1),
102 };
103
104 return imx_add_platform_device("imx-ssi", data->id,
105 res, ARRAY_SIZE(res),
106 pdata, sizeof(*pdata));
107}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c
index fa3dff1433e8..2039640adf27 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-uart.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c
@@ -6,55 +6,148 @@
6 * the terms of the GNU General Public License version 2 as published by the 6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation. 7 * Free Software Foundation.
8 */ 8 */
9#include <mach/hardware.h>
9#include <mach/devices-common.h> 10#include <mach/devices-common.h>
10 11
11struct platform_device *__init imx_add_imx_uart_3irq(int id, 12#define imx_imx_uart_3irq_data_entry(soc, _id, _hwid, _size) \
12 resource_size_t iobase, resource_size_t iosize, 13 [_id] = { \
13 resource_size_t irqrx, resource_size_t irqtx, 14 .id = _id, \
14 resource_size_t irqrts, 15 .iobase = soc ## _UART ## _hwid ## _BASE_ADDR, \
16 .iosize = _size, \
17 .irqrx = soc ## _INT_UART ## _hwid ## RX, \
18 .irqtx = soc ## _INT_UART ## _hwid ## TX, \
19 .irqrts = soc ## _INT_UART ## _hwid ## RTS, \
20 }
21
22#define imx_imx_uart_1irq_data_entry(soc, _id, _hwid, _size) \
23 [_id] = { \
24 .id = _id, \
25 .iobase = soc ## _UART ## _hwid ## _BASE_ADDR, \
26 .iosize = _size, \
27 .irq = soc ## _INT_UART ## _hwid, \
28 }
29
30#ifdef CONFIG_SOC_IMX1
31const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst = {
32#define imx1_imx_uart_data_entry(_id, _hwid) \
33 imx_imx_uart_3irq_data_entry(MX1, _id, _hwid, 0xd0)
34 imx1_imx_uart_data_entry(0, 1),
35 imx1_imx_uart_data_entry(1, 2),
36};
37#endif /* ifdef CONFIG_SOC_IMX1 */
38
39#ifdef CONFIG_SOC_IMX21
40const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = {
41#define imx21_imx_uart_data_entry(_id, _hwid) \
42 imx_imx_uart_1irq_data_entry(MX21, _id, _hwid, SZ_4K)
43 imx21_imx_uart_data_entry(0, 1),
44 imx21_imx_uart_data_entry(1, 2),
45 imx21_imx_uart_data_entry(2, 3),
46 imx21_imx_uart_data_entry(3, 4),
47};
48#endif
49
50#ifdef CONFIG_ARCH_MX25
51const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = {
52#define imx25_imx_uart_data_entry(_id, _hwid) \
53 imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K)
54 imx25_imx_uart_data_entry(0, 1),
55 imx25_imx_uart_data_entry(1, 2),
56 imx25_imx_uart_data_entry(2, 3),
57 imx25_imx_uart_data_entry(3, 4),
58 imx25_imx_uart_data_entry(4, 5),
59};
60#endif /* ifdef CONFIG_ARCH_MX25 */
61
62#ifdef CONFIG_SOC_IMX27
63const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = {
64#define imx27_imx_uart_data_entry(_id, _hwid) \
65 imx_imx_uart_1irq_data_entry(MX27, _id, _hwid, SZ_4K)
66 imx27_imx_uart_data_entry(0, 1),
67 imx27_imx_uart_data_entry(1, 2),
68 imx27_imx_uart_data_entry(2, 3),
69 imx27_imx_uart_data_entry(3, 4),
70 imx27_imx_uart_data_entry(4, 5),
71 imx27_imx_uart_data_entry(5, 6),
72};
73#endif /* ifdef CONFIG_SOC_IMX27 */
74
75#ifdef CONFIG_ARCH_MX31
76const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = {
77#define imx31_imx_uart_data_entry(_id, _hwid) \
78 imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K)
79 imx31_imx_uart_data_entry(0, 1),
80 imx31_imx_uart_data_entry(1, 2),
81 imx31_imx_uart_data_entry(2, 3),
82 imx31_imx_uart_data_entry(3, 4),
83 imx31_imx_uart_data_entry(4, 5),
84};
85#endif /* ifdef CONFIG_ARCH_MX31 */
86
87#ifdef CONFIG_ARCH_MX35
88const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
89#define imx35_imx_uart_data_entry(_id, _hwid) \
90 imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K)
91 imx35_imx_uart_data_entry(0, 1),
92 imx35_imx_uart_data_entry(1, 2),
93 imx35_imx_uart_data_entry(2, 3),
94};
95#endif /* ifdef CONFIG_ARCH_MX35 */
96
97#ifdef CONFIG_ARCH_MX51
98const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = {
99#define imx51_imx_uart_data_entry(_id, _hwid) \
100 imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K)
101 imx51_imx_uart_data_entry(0, 1),
102 imx51_imx_uart_data_entry(1, 2),
103 imx51_imx_uart_data_entry(2, 3),
104};
105#endif /* ifdef CONFIG_ARCH_MX51 */
106
107struct platform_device *__init imx_add_imx_uart_3irq(
108 const struct imx_imx_uart_3irq_data *data,
15 const struct imxuart_platform_data *pdata) 109 const struct imxuart_platform_data *pdata)
16{ 110{
17 struct resource res[] = { 111 struct resource res[] = {
18 { 112 {
19 .start = iobase, 113 .start = data->iobase,
20 .end = iobase + iosize - 1, 114 .end = data->iobase + data->iosize - 1,
21 .flags = IORESOURCE_MEM, 115 .flags = IORESOURCE_MEM,
22 }, { 116 }, {
23 .start = irqrx, 117 .start = data->irqrx,
24 .end = irqrx, 118 .end = data->irqrx,
25 .flags = IORESOURCE_IRQ, 119 .flags = IORESOURCE_IRQ,
26 }, { 120 }, {
27 .start = irqtx, 121 .start = data->irqtx,
28 .end = irqtx, 122 .end = data->irqtx,
29 .flags = IORESOURCE_IRQ, 123 .flags = IORESOURCE_IRQ,
30 }, { 124 }, {
31 .start = irqrts, 125 .start = data->irqrts,
32 .end = irqrx, 126 .end = data->irqrx,
33 .flags = IORESOURCE_IRQ, 127 .flags = IORESOURCE_IRQ,
34 }, 128 },
35 }; 129 };
36 130
37 return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res), 131 return imx_add_platform_device("imx-uart", data->id, res,
38 pdata, sizeof(*pdata)); 132 ARRAY_SIZE(res), pdata, sizeof(*pdata));
39} 133}
40 134
41struct platform_device *__init imx_add_imx_uart_1irq(int id, 135struct platform_device *__init imx_add_imx_uart_1irq(
42 resource_size_t iobase, resource_size_t iosize, 136 const struct imx_imx_uart_1irq_data *data,
43 resource_size_t irq,
44 const struct imxuart_platform_data *pdata) 137 const struct imxuart_platform_data *pdata)
45{ 138{
46 struct resource res[] = { 139 struct resource res[] = {
47 { 140 {
48 .start = iobase, 141 .start = data->iobase,
49 .end = iobase + iosize - 1, 142 .end = data->iobase + data->iosize - 1,
50 .flags = IORESOURCE_MEM, 143 .flags = IORESOURCE_MEM,
51 }, { 144 }, {
52 .start = irq, 145 .start = data->irq,
53 .end = irq, 146 .end = data->irq,
54 .flags = IORESOURCE_IRQ, 147 .flags = IORESOURCE_IRQ,
55 }, 148 },
56 }; 149 };
57 150
58 return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res), 151 return imx_add_platform_device("imx-uart", data->id, res, ARRAY_SIZE(res),
59 pdata, sizeof(*pdata)); 152 pdata, sizeof(*pdata));
60} 153}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
index 1c286418d123..3fdcc32e3d67 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c
+++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
@@ -7,38 +7,77 @@
7 * Free Software Foundation. 7 * Free Software Foundation.
8 */ 8 */
9#include <asm/sizes.h> 9#include <asm/sizes.h>
10#include <mach/hardware.h>
10#include <mach/devices-common.h> 11#include <mach/devices-common.h>
11 12
12static struct platform_device *__init imx_add_mxc_nand(resource_size_t iobase, 13#define imx_mxc_nand_data_entry_single(soc, _size) \
13 int irq, const struct mxc_nand_platform_data *pdata, 14 { \
14 resource_size_t iosize) 15 .iobase = soc ## _NFC_BASE_ADDR, \
16 .iosize = _size, \
17 .irq = soc ## _INT_NFC \
18 }
19
20#define imx_mxc_nandv3_data_entry_single(soc, _size) \
21 { \
22 .id = -1, \
23 .iobase = soc ## _NFC_BASE_ADDR, \
24 .iosize = _size, \
25 .axibase = soc ## _NFC_AXI_BASE_ADDR, \
26 .irq = soc ## _INT_NFC \
27 }
28
29#ifdef CONFIG_SOC_IMX21
30const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst =
31 imx_mxc_nand_data_entry_single(MX21, SZ_4K);
32#endif /* ifdef CONFIG_SOC_IMX21 */
33
34#ifdef CONFIG_ARCH_MX25
35const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst =
36 imx_mxc_nand_data_entry_single(MX25, SZ_8K);
37#endif /* ifdef CONFIG_ARCH_MX25 */
38
39#ifdef CONFIG_SOC_IMX27
40const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst =
41 imx_mxc_nand_data_entry_single(MX27, SZ_4K);
42#endif /* ifdef CONFIG_SOC_IMX27 */
43
44#ifdef CONFIG_ARCH_MX31
45const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst =
46 imx_mxc_nand_data_entry_single(MX31, SZ_4K);
47#endif
48
49#ifdef CONFIG_ARCH_MX35
50const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst =
51 imx_mxc_nand_data_entry_single(MX35, SZ_8K);
52#endif
53
54#ifdef CONFIG_ARCH_MX51
55const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst =
56 imx_mxc_nandv3_data_entry_single(MX51, SZ_16K);
57#endif
58
59struct platform_device *__init imx_add_mxc_nand(
60 const struct imx_mxc_nand_data *data,
61 const struct mxc_nand_platform_data *pdata)
15{ 62{
16 static int id = 0; 63 /* AXI has to come first, that's how the mxc_nand driver expect it */
17
18 struct resource res[] = { 64 struct resource res[] = {
19 { 65 {
20 .start = iobase, 66 .start = data->axibase,
21 .end = iobase + iosize - 1, 67 .end = data->axibase + SZ_16K - 1,
22 .flags = IORESOURCE_MEM, 68 .flags = IORESOURCE_MEM,
23 }, { 69 }, {
24 .start = irq, 70 .start = data->iobase,
25 .end = irq, 71 .end = data->iobase + data->iosize - 1,
72 .flags = IORESOURCE_MEM,
73 }, {
74 .start = data->irq,
75 .end = data->irq,
26 .flags = IORESOURCE_IRQ, 76 .flags = IORESOURCE_IRQ,
27 }, 77 },
28 }; 78 };
29 79 return imx_add_platform_device("mxc_nand", data->id,
30 return imx_add_platform_device("mxc_nand", id++, res, ARRAY_SIZE(res), 80 res + !data->axibase,
81 ARRAY_SIZE(res) - !data->axibase,
31 pdata, sizeof(*pdata)); 82 pdata, sizeof(*pdata));
32} 83}
33
34struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
35 int irq, const struct mxc_nand_platform_data *pdata)
36{
37 return imx_add_mxc_nand(iobase, irq, pdata, SZ_4K);
38}
39
40struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
41 int irq, const struct mxc_nand_platform_data *pdata)
42{
43 return imx_add_mxc_nand(iobase, irq, pdata, SZ_8K);
44}
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index 2831a6d3eb4b..e48340ec331e 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -6,25 +6,96 @@
6 * the terms of the GNU General Public License version 2 as published by the 6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation. 7 * Free Software Foundation.
8 */ 8 */
9#include <asm/sizes.h> 9#include <mach/hardware.h>
10#include <mach/devices-common.h> 10#include <mach/devices-common.h>
11 11
12struct platform_device *__init imx_add_spi_imx(int id, 12#define imx_spi_imx_data_entry_single(soc, type, _devid, _id, hwid, _size) \
13 resource_size_t iobase, resource_size_t iosize, int irq, 13 { \
14 .devid = _devid, \
15 .id = _id, \
16 .iobase = soc ## _ ## type ## hwid ## _BASE_ADDR, \
17 .iosize = _size, \
18 .irq = soc ## _INT_ ## type ## hwid, \
19 }
20
21#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size) \
22 [id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size)
23
24#ifdef CONFIG_SOC_IMX21
25const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
26#define imx21_cspi_data_entry(_id, _hwid) \
27 imx_spi_imx_data_entry(MX21, CSPI, "imx21-cspi", _id, _hwid, SZ_4K)
28 imx21_cspi_data_entry(0, 1),
29 imx21_cspi_data_entry(1, 2),
30#endif
31
32#ifdef CONFIG_ARCH_MX25
33const struct imx_spi_imx_data imx25_cspi_data[] __initconst = {
34#define imx25_cspi_data_entry(_id, _hwid) \
35 imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K)
36 imx25_cspi_data_entry(0, 1),
37 imx25_cspi_data_entry(1, 2),
38 imx25_cspi_data_entry(2, 3),
39};
40#endif /* ifdef CONFIG_ARCH_MX25 */
41
42#ifdef CONFIG_SOC_IMX27
43const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
44#define imx27_cspi_data_entry(_id, _hwid) \
45 imx_spi_imx_data_entry(MX27, CSPI, "imx27-cspi", _id, _hwid, SZ_4K)
46 imx27_cspi_data_entry(0, 1),
47 imx27_cspi_data_entry(1, 2),
48 imx27_cspi_data_entry(2, 3),
49};
50#endif /* ifdef CONFIG_SOC_IMX27 */
51
52#ifdef CONFIG_ARCH_MX31
53const struct imx_spi_imx_data imx31_cspi_data[] __initconst = {
54#define imx31_cspi_data_entry(_id, _hwid) \
55 imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K)
56 imx31_cspi_data_entry(0, 1),
57 imx31_cspi_data_entry(1, 2),
58 imx31_cspi_data_entry(2, 3),
59};
60#endif /* ifdef CONFIG_ARCH_MX31 */
61
62#ifdef CONFIG_ARCH_MX35
63const struct imx_spi_imx_data imx35_cspi_data[] __initconst = {
64#define imx35_cspi_data_entry(_id, _hwid) \
65 imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K)
66 imx35_cspi_data_entry(0, 1),
67 imx35_cspi_data_entry(1, 2),
68};
69#endif /* ifdef CONFIG_ARCH_MX35 */
70
71#ifdef CONFIG_ARCH_MX51
72const struct imx_spi_imx_data imx51_cspi_data __initconst =
73 imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K);
74
75const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
76#define imx51_ecspi_data_entry(_id, _hwid) \
77 imx_spi_imx_data_entry(MX51, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K)
78 imx51_ecspi_data_entry(0, 1),
79 imx51_ecspi_data_entry(1, 2),
80};
81#endif /* ifdef CONFIG_ARCH_MX51 */
82
83struct platform_device *__init imx_add_spi_imx(
84 const struct imx_spi_imx_data *data,
14 const struct spi_imx_master *pdata) 85 const struct spi_imx_master *pdata)
15{ 86{
16 struct resource res[] = { 87 struct resource res[] = {
17 { 88 {
18 .start = iobase, 89 .start = data->iobase,
19 .end = iobase + iosize - 1, 90 .end = data->iobase + data->iosize - 1,
20 .flags = IORESOURCE_MEM, 91 .flags = IORESOURCE_MEM,
21 }, { 92 }, {
22 .start = irq, 93 .start = data->irq,
23 .end = irq, 94 .end = data->irq,
24 .flags = IORESOURCE_IRQ, 95 .flags = IORESOURCE_IRQ,
25 }, 96 },
26 }; 97 };
27 98
28 return imx_add_platform_device("spi_imx", id, res, ARRAY_SIZE(res), 99 return imx_add_platform_device(data->devid, data->id,
29 pdata, sizeof(*pdata)); 100 res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
30} 101}
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 35a064ff02ba..9915607683de 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -249,8 +249,8 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
249#ifdef CONFIG_ARCH_MX51 249#ifdef CONFIG_ARCH_MX51
250 if (cpu_is_mx51()) { 250 if (cpu_is_mx51()) {
251 void __iomem *usb_base; 251 void __iomem *usb_base;
252 u32 usbotg_base; 252 void __iomem *usbotg_base;
253 u32 usbother_base; 253 void __iomem *usbother_base;
254 int ret = 0; 254 int ret = 0;
255 255
256 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); 256 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c
new file mode 100644
index 000000000000..ee9582f4972e
--- /dev/null
+++ b/arch/arm/plat-mxc/epit.c
@@ -0,0 +1,242 @@
1/*
2 * linux/arch/arm/plat-mxc/epit.c
3 *
4 * Copyright (C) 2010 Sascha Hauer <s.hauer@pengutronix.de>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#define EPITCR 0x00
22#define EPITSR 0x04
23#define EPITLR 0x08
24#define EPITCMPR 0x0c
25#define EPITCNR 0x10
26
27#define EPITCR_EN (1 << 0)
28#define EPITCR_ENMOD (1 << 1)
29#define EPITCR_OCIEN (1 << 2)
30#define EPITCR_RLD (1 << 3)
31#define EPITCR_PRESC(x) (((x) & 0xfff) << 4)
32#define EPITCR_SWR (1 << 16)
33#define EPITCR_IOVW (1 << 17)
34#define EPITCR_DBGEN (1 << 18)
35#define EPITCR_WAITEN (1 << 19)
36#define EPITCR_RES (1 << 20)
37#define EPITCR_STOPEN (1 << 21)
38#define EPITCR_OM_DISCON (0 << 22)
39#define EPITCR_OM_TOGGLE (1 << 22)
40#define EPITCR_OM_CLEAR (2 << 22)
41#define EPITCR_OM_SET (3 << 22)
42#define EPITCR_CLKSRC_OFF (0 << 24)
43#define EPITCR_CLKSRC_PERIPHERAL (1 << 24)
44#define EPITCR_CLKSRC_REF_HIGH (1 << 24)
45#define EPITCR_CLKSRC_REF_LOW (3 << 24)
46
47#define EPITSR_OCIF (1 << 0)
48
49#include <linux/interrupt.h>
50#include <linux/irq.h>
51#include <linux/clockchips.h>
52#include <linux/clk.h>
53
54#include <mach/hardware.h>
55#include <asm/mach/time.h>
56#include <mach/common.h>
57
58static struct clock_event_device clockevent_epit;
59static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
60
61static void __iomem *timer_base;
62
63static inline void epit_irq_disable(void)
64{
65 u32 val;
66
67 val = __raw_readl(timer_base + EPITCR);
68 val &= ~EPITCR_OCIEN;
69 __raw_writel(val, timer_base + EPITCR);
70}
71
72static inline void epit_irq_enable(void)
73{
74 u32 val;
75
76 val = __raw_readl(timer_base + EPITCR);
77 val |= EPITCR_OCIEN;
78 __raw_writel(val, timer_base + EPITCR);
79}
80
81static void epit_irq_acknowledge(void)
82{
83 __raw_writel(EPITSR_OCIF, timer_base + EPITSR);
84}
85
86static cycle_t epit_read(struct clocksource *cs)
87{
88 return 0 - __raw_readl(timer_base + EPITCNR);
89}
90
91static struct clocksource clocksource_epit = {
92 .name = "epit",
93 .rating = 200,
94 .read = epit_read,
95 .mask = CLOCKSOURCE_MASK(32),
96 .shift = 20,
97 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
98};
99
100static int __init epit_clocksource_init(struct clk *timer_clk)
101{
102 unsigned int c = clk_get_rate(timer_clk);
103
104 clocksource_epit.mult = clocksource_hz2mult(c,
105 clocksource_epit.shift);
106 clocksource_register(&clocksource_epit);
107
108 return 0;
109}
110
111/* clock event */
112
113static int epit_set_next_event(unsigned long evt,
114 struct clock_event_device *unused)
115{
116 unsigned long tcmp;
117
118 tcmp = __raw_readl(timer_base + EPITCNR);
119
120 __raw_writel(tcmp - evt, timer_base + EPITCMPR);
121
122 return 0;
123}
124
125static void epit_set_mode(enum clock_event_mode mode,
126 struct clock_event_device *evt)
127{
128 unsigned long flags;
129
130 /*
131 * The timer interrupt generation is disabled at least
132 * for enough time to call epit_set_next_event()
133 */
134 local_irq_save(flags);
135
136 /* Disable interrupt in GPT module */
137 epit_irq_disable();
138
139 if (mode != clockevent_mode) {
140 /* Set event time into far-far future */
141
142 /* Clear pending interrupt */
143 epit_irq_acknowledge();
144 }
145
146 /* Remember timer mode */
147 clockevent_mode = mode;
148 local_irq_restore(flags);
149
150 switch (mode) {
151 case CLOCK_EVT_MODE_PERIODIC:
152 printk(KERN_ERR "epit_set_mode: Periodic mode is not "
153 "supported for i.MX EPIT\n");
154 break;
155 case CLOCK_EVT_MODE_ONESHOT:
156 /*
157 * Do not put overhead of interrupt enable/disable into
158 * epit_set_next_event(), the core has about 4 minutes
159 * to call epit_set_next_event() or shutdown clock after
160 * mode switching
161 */
162 local_irq_save(flags);
163 epit_irq_enable();
164 local_irq_restore(flags);
165 break;
166 case CLOCK_EVT_MODE_SHUTDOWN:
167 case CLOCK_EVT_MODE_UNUSED:
168 case CLOCK_EVT_MODE_RESUME:
169 /* Left event sources disabled, no more interrupts appear */
170 break;
171 }
172}
173
174/*
175 * IRQ handler for the timer
176 */
177static irqreturn_t epit_timer_interrupt(int irq, void *dev_id)
178{
179 struct clock_event_device *evt = &clockevent_epit;
180
181 epit_irq_acknowledge();
182
183 evt->event_handler(evt);
184
185 return IRQ_HANDLED;
186}
187
188static struct irqaction epit_timer_irq = {
189 .name = "i.MX EPIT Timer Tick",
190 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
191 .handler = epit_timer_interrupt,
192};
193
194static struct clock_event_device clockevent_epit = {
195 .name = "epit",
196 .features = CLOCK_EVT_FEAT_ONESHOT,
197 .shift = 32,
198 .set_mode = epit_set_mode,
199 .set_next_event = epit_set_next_event,
200 .rating = 200,
201};
202
203static int __init epit_clockevent_init(struct clk *timer_clk)
204{
205 unsigned int c = clk_get_rate(timer_clk);
206
207 clockevent_epit.mult = div_sc(c, NSEC_PER_SEC,
208 clockevent_epit.shift);
209 clockevent_epit.max_delta_ns =
210 clockevent_delta2ns(0xfffffffe, &clockevent_epit);
211 clockevent_epit.min_delta_ns =
212 clockevent_delta2ns(0x800, &clockevent_epit);
213
214 clockevent_epit.cpumask = cpumask_of(0);
215
216 clockevents_register_device(&clockevent_epit);
217
218 return 0;
219}
220
221void __init epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
222{
223 clk_enable(timer_clk);
224
225 timer_base = base;
226
227 /*
228 * Initialise to a known state (all timers off, and timing reset)
229 */
230 __raw_writel(0x0, timer_base + EPITCR);
231
232 __raw_writel(0xffffffff, timer_base + EPITLR);
233 __raw_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN,
234 timer_base + EPITCR);
235
236 /* init and register the timer to the framework */
237 epit_clocksource_init(timer_clk);
238 epit_clockevent_init(timer_clk);
239
240 /* Make irqs happen */
241 setup_irq(irq, &epit_timer_irq);
242}
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 57ec4a896a5d..9d38da077edb 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -235,7 +235,7 @@ static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
235 unsigned long flags; 235 unsigned long flags;
236 236
237 spin_lock_irqsave(&port->lock, flags); 237 spin_lock_irqsave(&port->lock, flags);
238 l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset); 238 l = (__raw_readl(reg) & (~(1 << offset))) | (!!value << offset);
239 __raw_writel(l, reg); 239 __raw_writel(l, reg);
240 spin_unlock_irqrestore(&port->lock, flags); 240 spin_unlock_irqrestore(&port->lock, flags);
241} 241}
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
new file mode 100644
index 000000000000..94b60dd47137
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
@@ -0,0 +1,33 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
12#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
13
14#include <mach/hardware.h>
15
16/*
17 * These symbols are used by drivers/net/cs89x0.c.
18 * This is ugly as hell, but we have to provide them until
19 * someone fixed the driver.
20 */
21
22/* Base address of PBC controller */
23#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
24/* Offsets for the PBC Controller register */
25
26/* Ethernet Controller IO base address */
27#define PBC_CS8900A_IOBASE 0x020000
28
29#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
30
31#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
32
33#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 2941472582d2..7a1e1f89ff09 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -32,6 +32,7 @@ extern void mx31_init_irq(void);
32extern void mx35_init_irq(void); 32extern void mx35_init_irq(void);
33extern void mx51_init_irq(void); 33extern void mx51_init_irq(void);
34extern void mxc91231_init_irq(void); 34extern void mxc91231_init_irq(void);
35extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
35extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); 36extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
36extern int mx1_clocks_init(unsigned long fref); 37extern int mx1_clocks_init(unsigned long fref);
37extern int mx21_clocks_init(unsigned long lref, unsigned long fref); 38extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 25606409aabc..d56213fb901b 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -62,11 +62,9 @@
62#define UART_PADDR MXC91231_UART2_BASE_ADDR 62#define UART_PADDR MXC91231_UART2_BASE_ADDR
63#define UART_VADDR MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR) 63#define UART_VADDR MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR)
64#endif 64#endif
65 .macro addruart, rx, tmp 65 .macro addruart, rp, rv
66 mrc p15, 0, \rx, c1, c0 66 ldr \rp, =UART_PADDR @ physical
67 tst \rx, #1 @ MMU enabled? 67 ldr \rv, =UART_VADDR @ virtual
68 ldreq \rx, =UART_PADDR @ physical
69 ldrne \rx, =UART_VADDR @ virtual
70 .endm 68 .endm
71 69
72 .macro senduart,rd,rx 70 .macro senduart,rd,rx
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index c5f68c587309..86d7575a564d 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -14,47 +14,105 @@ struct platform_device *imx_add_platform_device(const char *name, int id,
14 const struct resource *res, unsigned int num_resources, 14 const struct resource *res, unsigned int num_resources,
15 const void *data, size_t size_data); 15 const void *data, size_t size_data);
16 16
17#if defined (CONFIG_CAN_FLEXCAN) || defined (CONFIG_CAN_FLEXCAN_MODULE) 17#include <linux/fec.h>
18struct imx_fec_data {
19 resource_size_t iobase;
20 resource_size_t irq;
21};
22struct platform_device *__init imx_add_fec(
23 const struct imx_fec_data *data,
24 const struct fec_platform_data *pdata);
25
18#include <linux/can/platform/flexcan.h> 26#include <linux/can/platform/flexcan.h>
19struct platform_device *__init imx_add_flexcan(int id, 27struct platform_device *__init imx_add_flexcan(int id,
20 resource_size_t iobase, resource_size_t iosize, 28 resource_size_t iobase, resource_size_t iosize,
21 resource_size_t irq, 29 resource_size_t irq,
22 const struct flexcan_platform_data *pdata); 30 const struct flexcan_platform_data *pdata);
23#else
24/* the ifdef can be removed once the flexcan driver has been merged */
25struct flexcan_platform_data;
26static inline struct platform_device *__init imx_add_flexcan(int id,
27 resource_size_t iobase, resource_size_t iosize,
28 resource_size_t irq,
29 const struct flexcan_platform_data *pdata)
30{
31 return NULL;
32}
33#endif
34 31
35#include <mach/i2c.h> 32#include <mach/i2c.h>
36struct platform_device *__init imx_add_imx_i2c(int id, 33struct imx_imx_i2c_data {
37 resource_size_t iobase, resource_size_t iosize, int irq, 34 int id;
35 resource_size_t iobase;
36 resource_size_t iosize;
37 resource_size_t irq;
38};
39struct platform_device *__init imx_add_imx_i2c(
40 const struct imx_imx_i2c_data *data,
38 const struct imxi2c_platform_data *pdata); 41 const struct imxi2c_platform_data *pdata);
39 42
43#include <mach/ssi.h>
44struct imx_imx_ssi_data {
45 int id;
46 resource_size_t iobase;
47 resource_size_t iosize;
48 resource_size_t irq;
49 resource_size_t dmatx0;
50 resource_size_t dmarx0;
51 resource_size_t dmatx1;
52 resource_size_t dmarx1;
53};
54struct platform_device *__init imx_add_imx_ssi(
55 const struct imx_imx_ssi_data *data,
56 const struct imx_ssi_platform_data *pdata);
57
40#include <mach/imx-uart.h> 58#include <mach/imx-uart.h>
41struct platform_device *__init imx_add_imx_uart_3irq(int id, 59struct imx_imx_uart_3irq_data {
42 resource_size_t iobase, resource_size_t iosize, 60 int id;
43 resource_size_t irqrx, resource_size_t irqtx, 61 resource_size_t iobase;
44 resource_size_t irqrts, 62 resource_size_t iosize;
63 resource_size_t irqrx;
64 resource_size_t irqtx;
65 resource_size_t irqrts;
66};
67struct platform_device *__init imx_add_imx_uart_3irq(
68 const struct imx_imx_uart_3irq_data *data,
45 const struct imxuart_platform_data *pdata); 69 const struct imxuart_platform_data *pdata);
46struct platform_device *__init imx_add_imx_uart_1irq(int id, 70
47 resource_size_t iobase, resource_size_t iosize, 71struct imx_imx_uart_1irq_data {
48 resource_size_t irq, 72 int id;
73 resource_size_t iobase;
74 resource_size_t iosize;
75 resource_size_t irq;
76};
77struct platform_device *__init imx_add_imx_uart_1irq(
78 const struct imx_imx_uart_1irq_data *data,
49 const struct imxuart_platform_data *pdata); 79 const struct imxuart_platform_data *pdata);
50 80
51#include <mach/mxc_nand.h> 81#include <mach/mxc_nand.h>
52struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase, 82struct imx_mxc_nand_data {
53 int irq, const struct mxc_nand_platform_data *pdata); 83 /*
54struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase, 84 * id is traditionally 0, but -1 is more appropriate. We use -1 for new
55 int irq, const struct mxc_nand_platform_data *pdata); 85 * machines but don't change existing devices as the nand device usually
86 * appears in the kernel command line to pass its partitioning.
87 */
88 int id;
89 resource_size_t iobase;
90 resource_size_t iosize;
91 resource_size_t axibase;
92 resource_size_t irq;
93};
94struct platform_device *__init imx_add_mxc_nand(
95 const struct imx_mxc_nand_data *data,
96 const struct mxc_nand_platform_data *pdata);
56 97
57#include <mach/spi.h> 98#include <mach/spi.h>
58struct platform_device *__init imx_add_spi_imx(int id, 99struct imx_spi_imx_data {
59 resource_size_t iobase, resource_size_t iosize, int irq, 100 const char *devid;
101 int id;
102 resource_size_t iobase;
103 resource_size_t iosize;
104 int irq;
105};
106struct platform_device *__init imx_add_spi_imx(
107 const struct imx_spi_imx_data *data,
60 const struct spi_imx_master *pdata); 108 const struct spi_imx_master *pdata);
109
110#include <mach/esdhc.h>
111struct imx_esdhc_imx_data {
112 int id;
113 resource_size_t iobase;
114 resource_size_t irq;
115};
116struct platform_device *__init imx_add_esdhc(
117 const struct imx_esdhc_imx_data *data,
118 const struct esdhc_platform_data *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/esdhc.h b/arch/arm/plat-mxc/include/mach/esdhc.h
new file mode 100644
index 000000000000..a48a9aaa56b1
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/esdhc.h
@@ -0,0 +1,16 @@
1/*
2 * Copyright 2010 Wolfram Sang <w.sang@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; version 2
7 * of the License.
8 */
9
10#ifndef __ASM_ARCH_IMX_ESDHC_H
11#define __ASM_ARCH_IMX_ESDHC_H
12
13struct esdhc_platform_data {
14 unsigned int wp_gpio; /* write protect pin */
15};
16#endif /* __ASM_ARCH_IMX_ESDHC_H */
diff --git a/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
index 656acb45d434..a21d3313f994 100644
--- a/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
+++ b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
@@ -28,19 +28,22 @@
28 * its own devices, it calls baseboard's init function. 28 * its own devices, it calls baseboard's init function.
29 * TODO: Add your own baseboard init function and call it from 29 * TODO: Add your own baseboard init function and call it from
30 * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init() 30 * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init()
31 * eukrea_cpuimx35_init() or eukrea_cpuimx51_init(). 31 * eukrea_cpuimx35_init() eukrea_cpuimx51_init()
32 * or eukrea_cpuimx51sd_init().
32 * 33 *
33 * This example here is for the development board. Refer 34 * This example here is for the development board. Refer
34 * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25 35 * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25
35 * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27 36 * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27
36 * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35 37 * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35
37 * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51 38 * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51
39 * mach-mx5/eukrea_mbimxsd-baseboard.c for cpuimx51sd
38 */ 40 */
39 41
40extern void eukrea_mbimxsd25_baseboard_init(void); 42extern void eukrea_mbimxsd25_baseboard_init(void);
41extern void eukrea_mbimx27_baseboard_init(void); 43extern void eukrea_mbimx27_baseboard_init(void);
42extern void eukrea_mbimxsd35_baseboard_init(void); 44extern void eukrea_mbimxsd35_baseboard_init(void);
43extern void eukrea_mbimx51_baseboard_init(void); 45extern void eukrea_mbimx51_baseboard_init(void);
46extern void eukrea_mbimxsd51_baseboard_init(void);
44 47
45#endif 48#endif
46 49
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index 21bfa46785bb..e46b1c2836d4 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -45,6 +45,18 @@ typedef enum iomux_config {
45 PAD_CTL_PKE | PAD_CTL_HYS) 45 PAD_CTL_PKE | PAD_CTL_HYS)
46#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \ 46#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
47 PAD_CTL_SRE_FAST) 47 PAD_CTL_SRE_FAST)
48#define MX51_ECSPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
49 PAD_CTL_SRE_FAST)
50#define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \
51 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_SRE_FAST | \
52 PAD_CTL_DVS)
53
54#define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
55 PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS)
56#define MX51_PAD_CTRL_2 (PAD_CTL_HYS | PAD_CTL_PKE)
57#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
58#define MX51_PAD_CTRL_4 (PAD_CTL_DVS | PAD_CTL_HYS | PAD_CTL_PKE)
59#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
48 60
49/* 61/*
50 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> 62 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
@@ -106,14 +118,20 @@ typedef enum iomux_config {
106#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) 118#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL)
107#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) 119#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL)
108#define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) 120#define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL)
121#define MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0x0d4, 3, 0x0, 0, MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
109#define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) 122#define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL)
123#define MX51_PAD_EIM_EB3__FEC_RDAT1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x0, 0, MX51_PAD_CTRL_2)
110#define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) 124#define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL)
111#define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) 125#define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL)
112#define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) 126#define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL)
113#define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) 127#define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL)
128#define MX51_PAD_EIM_CS2__FEC_RDAT2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x0, 0, MX51_PAD_CTRL_2)
114#define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) 129#define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL)
130#define MX51_PAD_EIM_CS3__FEC_RDAT3 IOMUX_PAD(0x480, 0x0ec, 3, 0x0, 0, MX51_PAD_CTRL_2)
115#define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) 131#define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL)
132#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x0, 0, MX51_PAD_CTRL_2)
116#define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) 133#define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL)
134#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x0, 0, MX51_PAD_CTRL_2)
117#define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) 135#define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL)
118#define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0x0FC, 1, 0x0, 0, NO_PAD_CTRL) 136#define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0x0FC, 1, 0x0, 0, NO_PAD_CTRL)
119#define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) 137#define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
@@ -126,18 +144,32 @@ typedef enum iomux_config {
126#define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) 144#define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
127#define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) 145#define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
128#define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) 146#define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
147#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL)
148#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x0, 0, MX51_PAD_CTRL_2)
129#define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) 149#define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
150#define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL)
151#define MX51_PAD_NANDF_RB3__FEC_RXCLK IOMUX_PAD(0x504, 0x128, 1, 0x0, 0, MX51_PAD_CTRL_2)
152#define MX51_PAD_NANDF_RB6__FEC_RDAT0 IOMUX_PAD(0x5DC, 0x134, 1, 0x0, 0, MX51_PAD_CTRL_4)
153#define MX51_PAD_NANDF_RB7__FEC_TDAT0 IOMUX_PAD(0x5E0, 0x138, 1, 0x0, 0, MX51_PAD_CTRL_5)
130#define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) 154#define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
131#define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) 155#define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
132#define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) 156#define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
133#define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) 157#define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
158#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0, 0, MX51_PAD_CTRL_5)
134#define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) 159#define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
160#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13C, 2, 0x0, 0, MX51_PAD_CTRL_5)
135#define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) 161#define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
162#define MX51_PAD_NANDF_CS4__FEC_TDAT1 IOMUX_PAD(0x528, 0x140, 2, 0x0, 0, MX51_PAD_CTRL_5)
136#define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) 163#define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
164#define MX51_PAD_NANDF_CS5__FEC_TDAT2 IOMUX_PAD(0x52C, 0x144, 2, 0x0, 0, MX51_PAD_CTRL_5)
137#define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) 165#define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
166#define MX51_PAD_NANDF_CS6__FEC_TDAT3 IOMUX_PAD(0x530, 0x148, 2, 0x0, 0, MX51_PAD_CTRL_5)
138#define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) 167#define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
168#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14C, 1, 0x0, 0, MX51_PAD_CTRL_5)
139#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) 169#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
170#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0, 0, MX51_PAD_CTRL_4)
140#define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) 171#define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
172#define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53C, 0x154, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL)
141#define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) 173#define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
142#define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) 174#define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
143#define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) 175#define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
@@ -185,15 +217,25 @@ typedef enum iomux_config {
185#define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) 217#define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL)
186#define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) 218#define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
187#define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) 219#define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL)
220#define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL)
188#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) 221#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
222#define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL)
189#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) 223#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
224#define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL)
190#define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) 225#define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
226#define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL)
191#define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) 227#define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
228#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL)
192#define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) 229#define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
230#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL)
193#define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) 231#define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
232#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL)
194#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) 233#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
234#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL)
195#define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) 235#define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
236#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL)
196#define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) 237#define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
238#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL)
197#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) 239#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
198#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) 240#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
199#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) 241#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
@@ -236,14 +278,14 @@ typedef enum iomux_config {
236#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 278#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
237#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 279#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, MX51_USBH1_PAD_CTRL)
238#define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) 280#define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
239#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL) 281#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x978, 1, NO_PAD_CTRL)
240#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) 282#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x97c, 1, NO_PAD_CTRL)
241#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL) 283#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x980, 1, NO_PAD_CTRL)
242#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL) 284#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x984, 1, NO_PAD_CTRL)
243#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL) 285#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x988, 1, NO_PAD_CTRL)
244#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL) 286#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x98c, 1, NO_PAD_CTRL)
245#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL) 287#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x990, 1, NO_PAD_CTRL)
246#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL) 288#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x994, 1, NO_PAD_CTRL)
247#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) 289#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
248#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) 290#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
249#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) 291#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
@@ -294,32 +336,50 @@ typedef enum iomux_config {
294#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) 336#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
295#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) 337#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
296#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) 338#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
297#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL) 339#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, IOMUX_CONFIG_SION, 0x0, 0, \
298#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL) 340 MX51_SDHCI_PAD_CTRL)
299#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL) 341#define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79C, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL)
300#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL) 342#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, IOMUX_CONFIG_SION, 0x0, 0, \
301#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL) 343 MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
302#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL) 344#define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7A0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL)
303#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL) 345#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, IOMUX_CONFIG_SION, 0x0, 0, \
304#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL) 346 MX51_SDHCI_PAD_CTRL)
305#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL) 347#define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7A4, 0x39C, 1, 0x8d8, 2, NO_PAD_CTRL)
306#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL) 348#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, IOMUX_CONFIG_SION, 0x0, 0, \
307#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL) 349 MX51_SDHCI_PAD_CTRL)
308#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL) 350#define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7A8, 0x3A0, 1, 0x8d4, 2, NO_PAD_CTRL)
309#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL) 351#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, IOMUX_CONFIG_SION, 0x0, 0, \
310#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL) 352 MX51_SDHCI_PAD_CTRL)
311#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL) 353#define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7AC, 0x3A4, 1, 0x8e4, 2, NO_PAD_CTRL)
354#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, IOMUX_CONFIG_SION, 0x0, 0, \
355 MX51_SDHCI_PAD_CTRL)
356#define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7B0, 0x3A8, 1, 0x8e8, 2, NO_PAD_CTRL)
357#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, IOMUX_CONFIG_SION, 0x0, 1, \
358 MX51_SDHCI_PAD_CTRL)
359#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, IOMUX_CONFIG_SION, 0x0, 0, \
360 MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS)
361#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, IOMUX_CONFIG_SION, 0x0, 0, \
362 MX51_SDHCI_PAD_CTRL)
363#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, IOMUX_CONFIG_SION, 0x0, 0, \
364 MX51_SDHCI_PAD_CTRL)
365#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, IOMUX_CONFIG_SION, 0x0, 0, \
366 MX51_SDHCI_PAD_CTRL)
367#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, IOMUX_CONFIG_SION, 0x0, 0, \
368 MX51_SDHCI_PAD_CTRL)
369#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
370#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
371#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
312#define MX51_PAD_GPIO_1_2__I2C2_SCL IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \ 372#define MX51_PAD_GPIO_1_2__I2C2_SCL IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \
313 0x9b8, 3, MX51_I2C_PAD_CTRL) 373 0x9b8, 3, MX51_I2C_PAD_CTRL)
314#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL) 374#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
315#define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \ 375#define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \
316 0x9bc, 3, MX51_I2C_PAD_CTRL) 376 0x9bc, 3, MX51_I2C_PAD_CTRL)
317#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) 377#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
318#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) 378#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
319#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) 379#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
320#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) 380#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
321#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) 381#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
322#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, MX51_GPIO_PAD_CTRL) 382#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
323#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) 383#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL)
324 384
325#endif /* __MACH_IOMUX_MX51_H__ */ 385#endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iram.h b/arch/arm/plat-mxc/include/mach/iram.h
new file mode 100644
index 000000000000..022690c33702
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iram.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19#include <linux/errno.h>
20
21#ifdef CONFIG_IRAM_ALLOC
22
23int __init iram_init(unsigned long base, unsigned long size);
24void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr);
25void iram_free(unsigned long dma_addr, unsigned int size);
26
27#else
28
29static inline int __init iram_init(unsigned long base, unsigned long size)
30{
31 return -ENOMEM;
32}
33
34static inline void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
35{
36 return NULL;
37}
38
39static inline void iram_free(unsigned long base, unsigned long size) {}
40
41#endif
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index ed98b9c9f389..8bc59720b6e4 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -120,7 +120,7 @@
120#define MX21_INT_GPT1 26 120#define MX21_INT_GPT1 26
121#define MX21_INT_WDOG 27 121#define MX21_INT_WDOG 27
122#define MX21_INT_PCMCIA 28 122#define MX21_INT_PCMCIA 28
123#define MX21_INT_NANDFC 29 123#define MX21_INT_NFC 29
124#define MX21_INT_BMI 30 124#define MX21_INT_BMI 30
125#define MX21_INT_CSI 31 125#define MX21_INT_CSI 31
126#define MX21_INT_DMACH0 32 126#define MX21_INT_DMACH0 32
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 4a6f800990f8..cf46a45b0d4e 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -50,8 +50,11 @@
50#define MX25_SSI1_BASE_ADDR 0x50034000 50#define MX25_SSI1_BASE_ADDR 0x50034000
51#define MX25_NFC_BASE_ADDR 0xbb000000 51#define MX25_NFC_BASE_ADDR 0xbb000000
52#define MX25_DRYICE_BASE_ADDR 0x53ffc000 52#define MX25_DRYICE_BASE_ADDR 0x53ffc000
53#define MX25_ESDHC1_BASE_ADDR 0x53fb4000
54#define MX25_ESDHC2_BASE_ADDR 0x53fb8000
53#define MX25_LCDC_BASE_ADDR 0x53fbc000 55#define MX25_LCDC_BASE_ADDR 0x53fbc000
54#define MX25_KPP_BASE_ADDR 0x43fa8000 56#define MX25_KPP_BASE_ADDR 0x43fa8000
57#define MX25_SDMA_BASE_ADDR 0x53fd4000
55#define MX25_OTG_BASE_ADDR 0x53ff4000 58#define MX25_OTG_BASE_ADDR 0x53ff4000
56#define MX25_CSI_BASE_ADDR 0x53ff8000 59#define MX25_CSI_BASE_ADDR 0x53ff8000
57 60
@@ -59,6 +62,8 @@
59#define MX25_INT_I2C1 3 62#define MX25_INT_I2C1 3
60#define MX25_INT_I2C2 4 63#define MX25_INT_I2C2 4
61#define MX25_INT_UART4 5 64#define MX25_INT_UART4 5
65#define MX25_INT_ESDHC2 8
66#define MX25_INT_ESDHC1 9
62#define MX25_INT_I2C3 10 67#define MX25_INT_I2C3 10
63#define MX25_INT_SSI2 11 68#define MX25_INT_SSI2 11
64#define MX25_INT_SSI1 12 69#define MX25_INT_SSI1 12
@@ -69,7 +74,8 @@
69#define MX25_INT_KPP 24 74#define MX25_INT_KPP 24
70#define MX25_INT_DRYICE 25 75#define MX25_INT_DRYICE 25
71#define MX25_INT_UART2 32 76#define MX25_INT_UART2 32
72#define MX25_INT_NANDFC 33 77#define MX25_INT_NFC 33
78#define MX25_INT_SDMA 34
73#define MX25_INT_LCDC 39 79#define MX25_INT_LCDC 39
74#define MX25_INT_UART5 40 80#define MX25_INT_UART5 40
75#define MX25_INT_CAN1 43 81#define MX25_INT_CAN1 43
@@ -77,4 +83,13 @@
77#define MX25_INT_UART1 45 83#define MX25_INT_UART1 45
78#define MX25_INT_FEC 57 84#define MX25_INT_FEC 57
79 85
86#define MX25_DMA_REQ_SSI2_RX1 22
87#define MX25_DMA_REQ_SSI2_TX1 23
88#define MX25_DMA_REQ_SSI2_RX0 24
89#define MX25_DMA_REQ_SSI2_TX0 25
90#define MX25_DMA_REQ_SSI1_RX1 26
91#define MX25_DMA_REQ_SSI1_TX1 27
92#define MX25_DMA_REQ_SSI1_RX0 28
93#define MX25_DMA_REQ_SSI1_TX0 29
94
80#endif /* ifndef __MACH_MX25_H__ */ 95#endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index a8ab2e02a8ca..2237ba2e5351 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -167,7 +167,7 @@ static inline void mx27_setup_weimcs(size_t cs,
167#define MX27_INT_GPT1 26 167#define MX27_INT_GPT1 26
168#define MX27_INT_WDOG 27 168#define MX27_INT_WDOG 27
169#define MX27_INT_PCMCIA 28 169#define MX27_INT_PCMCIA 28
170#define MX27_INT_NANDFC 29 170#define MX27_INT_NFC 29
171#define MX27_INT_ATA 30 171#define MX27_INT_ATA 30
172#define MX27_INT_CSI 31 172#define MX27_INT_CSI 31
173#define MX27_INT_DMACH0 32 173#define MX27_INT_DMACH0 32
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index afee3ab9d62e..03e2afabc9fc 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -168,7 +168,7 @@ static inline void mx31_setup_weimcs(size_t cs,
168#define MX31_INT_POWER_FAIL 30 168#define MX31_INT_POWER_FAIL 30
169#define MX31_INT_CCM_DVFS 31 169#define MX31_INT_CCM_DVFS 31
170#define MX31_INT_UART2 32 170#define MX31_INT_UART2 32
171#define MX31_INT_NANDFC 33 171#define MX31_INT_NFC 33
172#define MX31_INT_SDMA 34 172#define MX31_INT_SDMA 34
173#define MX31_INT_USB1 35 173#define MX31_INT_USB1 35
174#define MX31_INT_USB2 36 174#define MX31_INT_USB2 36
@@ -197,6 +197,15 @@ static inline void mx31_setup_weimcs(size_t cs,
197#define MX31_INT_EXT_WDOG 62 197#define MX31_INT_EXT_WDOG 62
198#define MX31_INT_EXT_TV 63 198#define MX31_INT_EXT_TV 63
199 199
200#define MX31_DMA_REQ_SSI2_RX1 22
201#define MX31_DMA_REQ_SSI2_TX1 23
202#define MX31_DMA_REQ_SSI2_RX0 24
203#define MX31_DMA_REQ_SSI2_TX0 25
204#define MX31_DMA_REQ_SSI1_RX1 26
205#define MX31_DMA_REQ_SSI1_TX1 27
206#define MX31_DMA_REQ_SSI1_RX0 28
207#define MX31_DMA_REQ_SSI1_TX0 29
208
200#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ 209#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */
201 210
202/* silicon revisions specific to i.MX31 */ 211/* silicon revisions specific to i.MX31 */
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index af3038c12e39..ff905cb32458 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -1,5 +1,6 @@
1#ifndef __MACH_MX35_H__ 1#ifndef __MACH_MX35_H__
2#define __MACH_MX35_H__ 2#define __MACH_MX35_H__
3
3/* 4/*
4 * IRAM 5 * IRAM
5 */ 6 */
@@ -52,6 +53,9 @@
52#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000) 53#define MX35_GPIO3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xa4000)
53#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000) 54#define MX35_SCC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xac000)
54#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000) 55#define MX35_RNGA_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb0000)
56#define MX35_ESDHC1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb4000)
57#define MX35_ESDHC2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xb8000)
58#define MX35_ESDHC3_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xbc000)
55#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000) 59#define MX35_IPU_CTRL_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc0000)
56#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000) 60#define MX35_AUDMUX_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xc4000)
57#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000) 61#define MX35_GPIO1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xcc000)
@@ -63,6 +67,8 @@
63#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000) 67#define MX35_CAN1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe4000)
64#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) 68#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
65#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) 69#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
70#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000)
71
66#define MX35_OTG_BASE_ADDR 0x53ff4000 72#define MX35_OTG_BASE_ADDR 0x53ff4000
67 73
68#define MX35_ROMP_BASE_ADDR 0x60000000 74#define MX35_ROMP_BASE_ADDR 0x60000000
@@ -122,9 +128,9 @@
122#define MX35_INT_I2C3 3 128#define MX35_INT_I2C3 3
123#define MX35_INT_I2C2 4 129#define MX35_INT_I2C2 4
124#define MX35_INT_RTIC 6 130#define MX35_INT_RTIC 6
125#define MX35_INT_MMC_SDHC1 7 131#define MX35_INT_ESDHC1 7
126#define MX35_INT_MMC_SDHC2 8 132#define MX35_INT_ESDHC2 8
127#define MX35_INT_MMC_SDHC3 9 133#define MX35_INT_ESDHC3 9
128#define MX35_INT_I2C1 10 134#define MX35_INT_I2C1 10
129#define MX35_INT_SSI1 11 135#define MX35_INT_SSI1 11
130#define MX35_INT_SSI2 12 136#define MX35_INT_SSI2 12
@@ -145,7 +151,7 @@
145#define MX35_INT_GPT 29 151#define MX35_INT_GPT 29
146#define MX35_INT_POWER_FAIL 30 152#define MX35_INT_POWER_FAIL 30
147#define MX35_INT_UART2 32 153#define MX35_INT_UART2 32
148#define MX35_INT_NANDFC 33 154#define MX35_INT_NFC 33
149#define MX35_INT_SDMA 34 155#define MX35_INT_SDMA 34
150#define MX35_INT_USBHS 35 156#define MX35_INT_USBHS 35
151#define MX35_INT_USBOTG 37 157#define MX35_INT_USBOTG 37
@@ -173,22 +179,18 @@
173#define MX35_INT_EXT_WDOG 62 179#define MX35_INT_EXT_WDOG 62
174#define MX35_INT_EXT_TV 63 180#define MX35_INT_EXT_TV 63
175 181
182#define MX35_DMA_REQ_SSI2_RX1 22
183#define MX35_DMA_REQ_SSI2_TX1 23
184#define MX35_DMA_REQ_SSI2_RX0 24
185#define MX35_DMA_REQ_SSI2_TX0 25
186#define MX35_DMA_REQ_SSI1_RX1 26
187#define MX35_DMA_REQ_SSI1_TX1 27
188#define MX35_DMA_REQ_SSI1_RX0 28
189#define MX35_DMA_REQ_SSI1_TX0 29
190
176#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */ 191#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */
177 192
178/* silicon revisions specific to i.MX31 */ 193#define MX35_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0
179#define MX35_CHIP_REV_1_0 0x10
180#define MX35_CHIP_REV_1_1 0x11
181#define MX35_CHIP_REV_1_2 0x12
182#define MX35_CHIP_REV_1_3 0x13
183#define MX35_CHIP_REV_2_0 0x20
184#define MX35_CHIP_REV_2_1 0x21
185#define MX35_CHIP_REV_2_2 0x22
186#define MX35_CHIP_REV_2_3 0x23
187#define MX35_CHIP_REV_3_0 0x30
188#define MX35_CHIP_REV_3_1 0x31
189#define MX35_CHIP_REV_3_2 0x32
190
191#define MX35_SYSTEM_REV_MIN MX35_CHIP_REV_1_0
192#define MX35_SYSTEM_REV_NUM 3 194#define MX35_SYSTEM_REV_NUM 3
193 195
194#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS 196#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 7a356de385f5..d1bd26d7b8a6 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -240,7 +240,7 @@
240 240
241#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ 241#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */
242 242
243/* silicon revisions specific to i.MX31 */ 243/* silicon revisions specific to i.MX31 and i.MX35 */
244#define MX3x_CHIP_REV_1_0 0x10 244#define MX3x_CHIP_REV_1_0 0x10
245#define MX3x_CHIP_REV_1_1 0x11 245#define MX3x_CHIP_REV_1_1 0x11
246#define MX3x_CHIP_REV_1_2 0x12 246#define MX3x_CHIP_REV_1_2 0x12
@@ -267,6 +267,14 @@ static inline int mx31_revision(void)
267{ 267{
268 return mx31_cpu_rev; 268 return mx31_cpu_rev;
269} 269}
270
271extern unsigned int mx35_cpu_rev;
272extern void mx35_read_cpu_rev(void);
273
274static inline int mx35_revision(void)
275{
276 return mx35_cpu_rev;
277}
270#endif 278#endif
271 279
272#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS 280#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
@@ -389,19 +397,6 @@ static inline int mx31_revision(void)
389#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG 397#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
390#define MXC_INT_EXT_TV MX3x_INT_EXT_TV 398#define MXC_INT_EXT_TV MX3x_INT_EXT_TV
391#define PROD_SIGNATURE MX3x_PROD_SIGNATURE 399#define PROD_SIGNATURE MX3x_PROD_SIGNATURE
392#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0
393#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1
394#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2
395#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3
396#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0
397#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1
398#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2
399#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3
400#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0
401#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1
402#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2
403#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN
404#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM
405#endif 400#endif
406 401
407#endif /* ifndef __MACH_MX3x_H__ */ 402#endif /* ifndef __MACH_MX3x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 5aad344d5651..2af7a1056fc1 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -1,5 +1,5 @@
1#ifndef __ASM_ARCH_MXC_MX51_H__ 1#ifndef __MACH_MX51_H__
2#define __ASM_ARCH_MXC_MX51_H__ 2#define __MACH_MX51_H__
3 3
4/* 4/*
5 * MX51 memory map: 5 * MX51 memory map:
@@ -7,24 +7,23 @@
7 * 7 *
8 * Virt Phys Size What 8 * Virt Phys Size What
9 * --------------------------------------------------------------------------- 9 * ---------------------------------------------------------------------------
10 * FA3E0000 1FFE0000 128K IRAM (SCCv2 RAM) 10 * fa3e0000 1ffe0000 128K IRAM (SCCv2 RAM)
11 * 30000000 256M GPU 11 * 30000000 256M GPU
12 * 40000000 512M IPU 12 * 40000000 512M IPU
13 * FA200000 60000000 1M DEBUG 13 * fa200000 60000000 1M DEBUG
14 * FB100000 70000000 1M SPBA 0 14 * fb100000 70000000 1M SPBA 0
15 * FB000000 73F00000 1M AIPS 1 15 * fb000000 73f00000 1M AIPS 1
16 * FB200000 83F00000 1M AIPS 2 16 * fb200000 83f00000 1M AIPS 2
17 * 8FFFC000 16K TZIC (interrupt controller) 17 * 8fffc000 16K TZIC (interrupt controller)
18 * 90000000 256M CSD0 SDRAM/DDR 18 * 90000000 256M CSD0 SDRAM/DDR
19 * A0000000 256M CSD1 SDRAM/DDR 19 * a0000000 256M CSD1 SDRAM/DDR
20 * B0000000 128M CS0 Flash 20 * b0000000 128M CS0 Flash
21 * B8000000 128M CS1 Flash 21 * b8000000 128M CS1 Flash
22 * C0000000 128M CS2 Flash 22 * c0000000 128M CS2 Flash
23 * C8000000 64M CS3 Flash 23 * c8000000 64M CS3 Flash
24 * CC000000 32M CS4 SRAM 24 * cc000000 32M CS4 SRAM
25 * CE000000 32M CS5 SRAM 25 * ce000000 32M CS5 SRAM
26 * CFFF0000 64K NFC (NAND Flash AXI) 26 * cfff0000 64K NFC (NAND Flash AXI)
27 *
28 */ 27 */
29 28
30/* 29/*
@@ -36,65 +35,151 @@
36/* 35/*
37 * IRAM 36 * IRAM
38 */ 37 */
39#define MX51_IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ 38#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */
40#define MX51_IRAM_BASE_ADDR_VIRT 0xFA3E0000 39#define MX51_IRAM_BASE_ADDR_VIRT 0xfa3e0000
41#define MX51_IRAM_PARTITIONS 16 40#define MX51_IRAM_PARTITIONS 16
42#define MX51_IRAM_PARTITIONS_TO1 12
43#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ 41#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
44 42
43#define MX51_GPU_BASE_ADDR 0x20000000
44#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
45#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
46
47#define MX51_DEBUG_BASE_ADDR 0x60000000
48#define MX51_DEBUG_BASE_ADDR_VIRT 0xfa200000
49#define MX51_DEBUG_SIZE SZ_1M
50
51#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000)
52#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x02000)
53#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x03000)
54#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x04000)
55#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x05000)
56#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x06000)
57#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x07000)
58#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x08000)
59
45/* 60/*
46 * NFC 61 * SPBA global module enabled #0
47 */ 62 */
48#define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */ 63#define MX51_SPBA0_BASE_ADDR 0x70000000
49#define MX51_NFC_AXI_SIZE SZ_64K 64#define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000
65#define MX51_SPBA0_SIZE SZ_1M
66
67#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000)
68#define MX51_ESDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x08000)
69#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0c000)
70#define MX51_ECSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x10000)
71#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x14000)
72#define MX51_ESDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x20000)
73#define MX51_ESDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x24000)
74#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x28000)
75#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x30000)
76#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x34000)
77#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x38000)
78#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x3c000)
50 79
51/* 80/*
52 * Graphics Memory of GPU 81 * AIPS 1
53 */ 82 */
54#define MX51_GPU_BASE_ADDR 0x20000000 83#define MX51_AIPS1_BASE_ADDR 0x73f00000
55#define MX51_GPU2D_BASE_ADDR 0xD0000000 84#define MX51_AIPS1_BASE_ADDR_VIRT 0xfb000000
85#define MX51_AIPS1_SIZE SZ_1M
86
87#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000)
88#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x84000)
89#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x88000)
90#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000)
91#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000)
92#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000)
93#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000)
94#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000)
95#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000)
96#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000)
97#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa8000)
98#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xac000)
99#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb0000)
100#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb4000)
101#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xb8000)
102#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xbc000)
103#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xc0000)
104#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd0000)
105#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd4000)
106#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xd8000)
56 107
57#define MX51_TZIC_BASE_ADDR_TO1 0x8FFFC000 108/*
58#define MX51_TZIC_BASE_ADDR 0xE0000000 109 * AIPS 2
110 */
111#define MX51_AIPS2_BASE_ADDR 0x83f00000
112#define MX51_AIPS2_BASE_ADDR_VIRT 0xfb200000
113#define MX51_AIPS2_SIZE SZ_1M
59 114
60#define MX51_DEBUG_BASE_ADDR 0x60000000 115#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000)
61#define MX51_DEBUG_BASE_ADDR_VIRT 0xFA200000 116#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x84000)
62#define MX51_DEBUG_SIZE SZ_1M 117#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x88000)
63#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00001000) 118#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x94000)
64#define MX51_ETM_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00002000) 119#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x98000)
65#define MX51_TPIU_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00003000) 120#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x9c000)
66#define MX51_CTI0_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00004000) 121#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa0000)
67#define MX51_CTI1_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00005000) 122#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa4000)
68#define MX51_CTI2_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00006000) 123#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xa8000)
69#define MX51_CTI3_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00007000) 124#define MX51_ECSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xac000)
70#define MX51_CORTEX_DBG_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x00008000) 125#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb0000)
126#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb4000)
127#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xb8000)
128#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xbc000)
129#define MX51_CSPI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc0000)
130#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc4000)
131#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xc8000)
132#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xcc000)
133#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd0000)
134#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd8000)
135#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xd9000)
136#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xda000)
137#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdb000)
138#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdbf00)
139#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000)
140#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000)
141#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000)
142#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000)
143#define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000)
144#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000)
145#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000)
146#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf8000)
147
148#define MX51_CSD0_BASE_ADDR 0x90000000
149#define MX51_CSD1_BASE_ADDR 0xa0000000
150#define MX51_CS0_BASE_ADDR 0xb0000000
151#define MX51_CS1_BASE_ADDR 0xb8000000
152#define MX51_CS2_BASE_ADDR 0xc0000000
153#define MX51_CS3_BASE_ADDR 0xc8000000
154#define MX51_CS4_BASE_ADDR 0xcc000000
155#define MX51_CS5_BASE_ADDR 0xce000000
71 156
72/* 157/*
73 * SPBA global module enabled #0 158 * NFC
74 */ 159 */
75#define MX51_SPBA0_BASE_ADDR 0x70000000 160#define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 /* NAND flash AXI */
76#define MX51_SPBA0_BASE_ADDR_VIRT 0xFB100000 161#define MX51_NFC_AXI_SIZE SZ_64K
77#define MX51_SPBA0_SIZE SZ_1M 162
163#define MX51_GPU2D_BASE_ADDR 0xd0000000
164#define MX51_TZIC_BASE_ADDR 0xe0000000
78 165
79#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000) 166#define MX51_IO_ADDRESS(x) ( \
80#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000) 167 IMX_IO_ADDRESS(x, MX51_IRAM) ?: \
81#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000) 168 IMX_IO_ADDRESS(x, MX51_DEBUG) ?: \
82#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000) 169 IMX_IO_ADDRESS(x, MX51_SPBA0) ?: \
83#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000) 170 IMX_IO_ADDRESS(x, MX51_AIPS1) ?: \
84#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000) 171 IMX_IO_ADDRESS(x, MX51_AIPS2))
85#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000) 172
86#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00028000) 173/* This is currently used in <mach/debug-macro.S>, but should go away */
87#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00030000) 174#define MX51_AIPS1_IO_ADDRESS(x) \
88#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00034000) 175 (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
89#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00038000)
90#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000)
91 176
92/* 177/*
93 * defines for SPBA modules 178 * defines for SPBA modules
94 */ 179 */
95#define MX51_SPBA_SDHC1 0x04 180#define MX51_SPBA_SDHC1 0x04
96#define MX51_SPBA_SDHC2 0x08 181#define MX51_SPBA_SDHC2 0x08
97#define MX51_SPBA_UART3 0x0C 182#define MX51_SPBA_UART3 0x0c
98#define MX51_SPBA_CSPI1 0x10 183#define MX51_SPBA_CSPI1 0x10
99#define MX51_SPBA_SSI2 0x14 184#define MX51_SPBA_SSI2 0x14
100#define MX51_SPBA_SDHC3 0x20 185#define MX51_SPBA_SDHC3 0x20
@@ -103,35 +188,7 @@
103#define MX51_SPBA_ATA 0x30 188#define MX51_SPBA_ATA 0x30
104#define MX51_SPBA_SLIM 0x34 189#define MX51_SPBA_SLIM 0x34
105#define MX51_SPBA_HSI2C 0x38 190#define MX51_SPBA_HSI2C 0x38
106#define MX51_SPBA_CTRL 0x3C 191#define MX51_SPBA_CTRL 0x3c
107
108/*
109 * AIPS 1
110 */
111#define MX51_AIPS1_BASE_ADDR 0x73F00000
112#define MX51_AIPS1_BASE_ADDR_VIRT 0xFB000000
113#define MX51_AIPS1_SIZE SZ_1M
114
115#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00080000)
116#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00084000)
117#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00088000)
118#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0008C000)
119#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00090000)
120#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00094000)
121#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00098000)
122#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0009C000)
123#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A0000)
124#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A4000)
125#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A8000)
126#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000AC000)
127#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B0000)
128#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B4000)
129#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B8000)
130#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000BC000)
131#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000C0000)
132#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D0000)
133#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D4000)
134#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D8000)
135 192
136/* 193/*
137 * Defines for modules using static and dynamic DMA channels 194 * Defines for modules using static and dynamic DMA channels
@@ -164,282 +221,186 @@
164#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL 221#define MX51_MXC_DMA_CHANNEL_ATA_TX MXC_DMA_DYNAMIC_CHANNEL
165#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL 222#define MX51_MXC_DMA_CHANNEL_MEMORY MXC_DMA_DYNAMIC_CHANNEL
166 223
167/*
168 * AIPS 2
169 */
170#define MX51_AIPS2_BASE_ADDR 0x83F00000
171#define MX51_AIPS2_BASE_ADDR_VIRT 0xFB200000
172#define MX51_AIPS2_SIZE SZ_1M
173
174#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00080000)
175#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00084000)
176#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00088000)
177#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00094000)
178#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00098000)
179#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x0009C000)
180#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A0000)
181#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000)
182#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A8000)
183#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000)
184#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B0000)
185#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B4000)
186#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B8000)
187#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000BC000)
188#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000)
189#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C4000)
190#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C8000)
191#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000CC000)
192#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D0000)
193#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D8000)
194#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D9000)
195#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DA000)
196#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DB000)
197#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DBF00)
198#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000)
199#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E0000)
200#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E4000)
201#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E8000)
202#define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000EC000)
203#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F0000)
204#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F4000)
205#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000)
206
207/*
208 * Memory regions and CS
209 */
210#define MX51_GPU_CTRL_BASE_ADDR 0x30000000
211#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
212#define MX51_CSD0_BASE_ADDR 0x90000000
213#define MX51_CSD1_BASE_ADDR 0xA0000000
214#define MX51_CS0_BASE_ADDR 0xB0000000
215#define MX51_CS1_BASE_ADDR 0xB8000000
216#define MX51_CS2_BASE_ADDR 0xC0000000
217#define MX51_CS3_BASE_ADDR 0xC8000000
218#define MX51_CS4_BASE_ADDR 0xCC000000
219#define MX51_CS5_BASE_ADDR 0xCE000000
220
221/* Does given address belongs to the specified memory region? */
222#define ADDRESS_IN_REGION(addr, start, size) \
223 (((addr) >= (start)) && ((addr) < (start)+(size)))
224
225/* Does given address belongs to the specified named `module'? */
226#define MX51_IS_MODULE(addr, module) \
227 ADDRESS_IN_REGION(addr, MX51_ ## module ## _BASE_ADDR, \
228 MX51_ ## module ## _SIZE)
229/*
230 * This macro defines the physical to virtual address mapping for all the
231 * peripheral modules. It is used by passing in the physical address as x
232 * and returning the virtual address. If the physical address is not mapped,
233 * it returns 0xDEADBEEF
234 */
235
236#define MX51_IO_ADDRESS(x) \
237 (void __iomem *) \
238 (MX51_IS_MODULE(x, IRAM) ? MX51_IRAM_IO_ADDRESS(x) : \
239 MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \
240 MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \
241 MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \
242 MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
243 0xDEADBEEF)
244
245/*
246 * define the address mapping macros: in physical address order
247 */
248#define MX51_IRAM_IO_ADDRESS(x) \
249 (((x) - MX51_IRAM_BASE_ADDR) + MX51_IRAM_BASE_ADDR_VIRT)
250
251#define MX51_DEBUG_IO_ADDRESS(x) \
252 (((x) - MX51_DEBUG_BASE_ADDR) + MX51_DEBUG_BASE_ADDR_VIRT)
253
254#define MX51_SPBA0_IO_ADDRESS(x) \
255 (((x) - MX51_SPBA0_BASE_ADDR) + MX51_SPBA0_BASE_ADDR_VIRT)
256
257#define MX51_AIPS1_IO_ADDRESS(x) \
258 (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
259
260#define MX51_AIPS2_IO_ADDRESS(x) \
261 (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT)
262
263#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0 224#define MX51_IS_MEM_DEVICE_NONSHARED(x) 0
264 225
265/* 226/*
266 * DMA request assignments 227 * DMA request assignments
267 */ 228 */
268#define MX51_DMA_REQ_SSI3_TX1 47 229#define MX51_DMA_REQ_VPU 0
269#define MX51_DMA_REQ_SSI3_RX1 46 230#define MX51_DMA_REQ_GPC 1
270#define MX51_DMA_REQ_SPDIF 45 231#define MX51_DMA_REQ_ATA_RX 2
271#define MX51_DMA_REQ_UART3_TX 44 232#define MX51_DMA_REQ_ATA_TX 3
272#define MX51_DMA_REQ_UART3_RX 43 233#define MX51_DMA_REQ_ATA_TX_END 4
273#define MX51_DMA_REQ_SLIM_B_TX 42 234#define MX51_DMA_REQ_SLIM_B 5
274#define MX51_DMA_REQ_SDHC4 41 235#define MX51_DMA_REQ_CSPI1_RX 6
275#define MX51_DMA_REQ_SDHC3 40 236#define MX51_DMA_REQ_CSPI1_TX 7
276#define MX51_DMA_REQ_CSPI_TX 39 237#define MX51_DMA_REQ_CSPI2_RX 8
277#define MX51_DMA_REQ_CSPI_RX 38 238#define MX51_DMA_REQ_CSPI2_TX 9
278#define MX51_DMA_REQ_SSI3_TX2 37 239#define MX51_DMA_REQ_HS_I2C_TX 10
279#define MX51_DMA_REQ_IPU 36 240#define MX51_DMA_REQ_HS_I2C_RX 11
280#define MX51_DMA_REQ_SSI3_RX2 35 241#define MX51_DMA_REQ_FIRI_RX 12
281#define MX51_DMA_REQ_EPIT2 34 242#define MX51_DMA_REQ_FIRI_TX 13
282#define MX51_DMA_REQ_CTI2_1 33 243#define MX51_DMA_REQ_EXTREQ1 14
283#define MX51_DMA_REQ_EMI_WR 32 244#define MX51_DMA_REQ_GPU 15
284#define MX51_DMA_REQ_CTI2_0 31 245#define MX51_DMA_REQ_UART2_RX 16
285#define MX51_DMA_REQ_EMI_RD 30 246#define MX51_DMA_REQ_UART2_TX 17
286#define MX51_DMA_REQ_SSI1_TX1 29 247#define MX51_DMA_REQ_UART1_RX 18
287#define MX51_DMA_REQ_SSI1_RX1 28 248#define MX51_DMA_REQ_UART1_TX 19
288#define MX51_DMA_REQ_SSI1_TX2 27 249#define MX51_DMA_REQ_SDHC1 20
289#define MX51_DMA_REQ_SSI1_RX2 26 250#define MX51_DMA_REQ_SDHC2 21
290#define MX51_DMA_REQ_SSI2_TX1 25 251#define MX51_DMA_REQ_SSI2_RX1 22
291#define MX51_DMA_REQ_SSI2_RX1 24 252#define MX51_DMA_REQ_SSI2_TX1 23
292#define MX51_DMA_REQ_SSI2_TX2 23 253#define MX51_DMA_REQ_SSI2_RX0 24
293#define MX51_DMA_REQ_SSI2_RX2 22 254#define MX51_DMA_REQ_SSI2_TX0 25
294#define MX51_DMA_REQ_SDHC2 21 255#define MX51_DMA_REQ_SSI1_RX1 26
295#define MX51_DMA_REQ_SDHC1 20 256#define MX51_DMA_REQ_SSI1_TX1 27
296#define MX51_DMA_REQ_UART1_TX 19 257#define MX51_DMA_REQ_SSI1_RX0 28
297#define MX51_DMA_REQ_UART1_RX 18 258#define MX51_DMA_REQ_SSI1_TX0 29
298#define MX51_DMA_REQ_UART2_TX 17 259#define MX51_DMA_REQ_EMI_RD 30
299#define MX51_DMA_REQ_UART2_RX 16 260#define MX51_DMA_REQ_CTI2_0 31
300#define MX51_DMA_REQ_GPU 15 261#define MX51_DMA_REQ_EMI_WR 32
301#define MX51_DMA_REQ_EXTREQ1 14 262#define MX51_DMA_REQ_CTI2_1 33
302#define MX51_DMA_REQ_FIRI_TX 13 263#define MX51_DMA_REQ_EPIT2 34
303#define MX51_DMA_REQ_FIRI_RX 12 264#define MX51_DMA_REQ_SSI3_RX2 35
304#define MX51_DMA_REQ_HS_I2C_RX 11 265#define MX51_DMA_REQ_IPU 36
305#define MX51_DMA_REQ_HS_I2C_TX 10 266#define MX51_DMA_REQ_SSI3_TX2 37
306#define MX51_DMA_REQ_CSPI2_TX 9 267#define MX51_DMA_REQ_CSPI_RX 38
307#define MX51_DMA_REQ_CSPI2_RX 8 268#define MX51_DMA_REQ_CSPI_TX 39
308#define MX51_DMA_REQ_CSPI1_TX 7 269#define MX51_DMA_REQ_SDHC3 40
309#define MX51_DMA_REQ_CSPI1_RX 6 270#define MX51_DMA_REQ_SDHC4 41
310#define MX51_DMA_REQ_SLIM_B 5 271#define MX51_DMA_REQ_SLIM_B_TX 42
311#define MX51_DMA_REQ_ATA_TX_END 4 272#define MX51_DMA_REQ_UART3_RX 43
312#define MX51_DMA_REQ_ATA_TX 3 273#define MX51_DMA_REQ_UART3_TX 44
313#define MX51_DMA_REQ_ATA_RX 2 274#define MX51_DMA_REQ_SPDIF 45
314#define MX51_DMA_REQ_GPC 1 275#define MX51_DMA_REQ_SSI3_RX1 46
315#define MX51_DMA_REQ_VPU 0 276#define MX51_DMA_REQ_SSI3_TX1 47
316 277
317/* 278/*
318 * Interrupt numbers 279 * Interrupt numbers
319 */ 280 */
320#define MX51_MXC_INT_BASE 0 281#define MX51_MXC_INT_BASE 0
321#define MX51_MXC_INT_RESV0 0 282#define MX51_MXC_INT_RESV0 0
322#define MX51_MXC_INT_MMC_SDHC1 1 283#define MX51_INT_ESDHC1 1
323#define MX51_MXC_INT_MMC_SDHC2 2 284#define MX51_INT_ESDHC2 2
324#define MX51_MXC_INT_MMC_SDHC3 3 285#define MX51_INT_ESDHC3 3
325#define MX51_MXC_INT_MMC_SDHC4 4 286#define MX51_INT_ESDHC4 4
326#define MX51_MXC_INT_RESV5 5 287#define MX51_MXC_INT_RESV5 5
327#define MX51_MXC_INT_SDMA 6 288#define MX51_INT_SDMA 6
328#define MX51_MXC_INT_IOMUX 7 289#define MX51_MXC_INT_IOMUX 7
329#define MX51_MXC_INT_NFC 8 290#define MX51_INT_NFC 8
330#define MX51_MXC_INT_VPU 9 291#define MX51_MXC_INT_VPU 9
331#define MX51_MXC_INT_IPU_ERR 10 292#define MX51_MXC_INT_IPU_ERR 10
332#define MX51_MXC_INT_IPU_SYN 11 293#define MX51_MXC_INT_IPU_SYN 11
333#define MX51_MXC_INT_GPU 12 294#define MX51_MXC_INT_GPU 12
334#define MX51_MXC_INT_RESV13 13 295#define MX51_MXC_INT_RESV13 13
335#define MX51_MXC_INT_USB_H1 14 296#define MX51_MXC_INT_USB_H1 14
336#define MX51_MXC_INT_EMI 15 297#define MX51_MXC_INT_EMI 15
337#define MX51_MXC_INT_USB_H2 16 298#define MX51_MXC_INT_USB_H2 16
338#define MX51_MXC_INT_USB_H3 17 299#define MX51_MXC_INT_USB_H3 17
339#define MX51_MXC_INT_USB_OTG 18 300#define MX51_MXC_INT_USB_OTG 18
340#define MX51_MXC_INT_SAHARA_H0 19 301#define MX51_MXC_INT_SAHARA_H0 19
341#define MX51_MXC_INT_SAHARA_H1 20 302#define MX51_MXC_INT_SAHARA_H1 20
342#define MX51_MXC_INT_SCC_SMN 21 303#define MX51_MXC_INT_SCC_SMN 21
343#define MX51_MXC_INT_SCC_STZ 22 304#define MX51_MXC_INT_SCC_STZ 22
344#define MX51_MXC_INT_SCC_SCM 23 305#define MX51_MXC_INT_SCC_SCM 23
345#define MX51_MXC_INT_SRTC_NTZ 24 306#define MX51_MXC_INT_SRTC_NTZ 24
346#define MX51_MXC_INT_SRTC_TZ 25 307#define MX51_MXC_INT_SRTC_TZ 25
347#define MX51_MXC_INT_RTIC 26 308#define MX51_MXC_INT_RTIC 26
348#define MX51_MXC_INT_CSU 27 309#define MX51_MXC_INT_CSU 27
349#define MX51_MXC_INT_SLIM_B 28 310#define MX51_MXC_INT_SLIM_B 28
350#define MX51_MXC_INT_SSI1 29 311#define MX51_INT_SSI1 29
351#define MX51_MXC_INT_SSI2 30 312#define MX51_INT_SSI2 30
352#define MX51_MXC_INT_UART1 31 313#define MX51_INT_UART1 31
353#define MX51_MXC_INT_UART2 32 314#define MX51_INT_UART2 32
354#define MX51_MXC_INT_UART3 33 315#define MX51_INT_UART3 33
355#define MX51_MXC_INT_RESV34 34 316#define MX51_MXC_INT_RESV34 34
356#define MX51_MXC_INT_RESV35 35 317#define MX51_MXC_INT_RESV35 35
357#define MX51_MXC_INT_CSPI1 36 318#define MX51_INT_ECSPI1 36
358#define MX51_MXC_INT_CSPI2 37 319#define MX51_INT_ECSPI2 37
359#define MX51_MXC_INT_CSPI 38 320#define MX51_INT_CSPI 38
360#define MX51_MXC_INT_GPT 39 321#define MX51_MXC_INT_GPT 39
361#define MX51_MXC_INT_EPIT1 40 322#define MX51_MXC_INT_EPIT1 40
362#define MX51_MXC_INT_EPIT2 41 323#define MX51_MXC_INT_EPIT2 41
363#define MX51_MXC_INT_GPIO1_INT7 42 324#define MX51_MXC_INT_GPIO1_INT7 42
364#define MX51_MXC_INT_GPIO1_INT6 43 325#define MX51_MXC_INT_GPIO1_INT6 43
365#define MX51_MXC_INT_GPIO1_INT5 44 326#define MX51_MXC_INT_GPIO1_INT5 44
366#define MX51_MXC_INT_GPIO1_INT4 45 327#define MX51_MXC_INT_GPIO1_INT4 45
367#define MX51_MXC_INT_GPIO1_INT3 46 328#define MX51_MXC_INT_GPIO1_INT3 46
368#define MX51_MXC_INT_GPIO1_INT2 47 329#define MX51_MXC_INT_GPIO1_INT2 47
369#define MX51_MXC_INT_GPIO1_INT1 48 330#define MX51_MXC_INT_GPIO1_INT1 48
370#define MX51_MXC_INT_GPIO1_INT0 49 331#define MX51_MXC_INT_GPIO1_INT0 49
371#define MX51_MXC_INT_GPIO1_LOW 50 332#define MX51_MXC_INT_GPIO1_LOW 50
372#define MX51_MXC_INT_GPIO1_HIGH 51 333#define MX51_MXC_INT_GPIO1_HIGH 51
373#define MX51_MXC_INT_GPIO2_LOW 52 334#define MX51_MXC_INT_GPIO2_LOW 52
374#define MX51_MXC_INT_GPIO2_HIGH 53 335#define MX51_MXC_INT_GPIO2_HIGH 53
375#define MX51_MXC_INT_GPIO3_LOW 54 336#define MX51_MXC_INT_GPIO3_LOW 54
376#define MX51_MXC_INT_GPIO3_HIGH 55 337#define MX51_MXC_INT_GPIO3_HIGH 55
377#define MX51_MXC_INT_GPIO4_LOW 56 338#define MX51_MXC_INT_GPIO4_LOW 56
378#define MX51_MXC_INT_GPIO4_HIGH 57 339#define MX51_MXC_INT_GPIO4_HIGH 57
379#define MX51_MXC_INT_WDOG1 58 340#define MX51_MXC_INT_WDOG1 58
380#define MX51_MXC_INT_WDOG2 59 341#define MX51_MXC_INT_WDOG2 59
381#define MX51_MXC_INT_KPP 60 342#define MX51_MXC_INT_KPP 60
382#define MX51_MXC_INT_PWM1 61 343#define MX51_MXC_INT_PWM1 61
383#define MX51_MXC_INT_I2C1 62 344#define MX51_INT_I2C1 62
384#define MX51_MXC_INT_I2C2 63 345#define MX51_INT_I2C2 63
385#define MX51_MXC_INT_HS_I2C 64 346#define MX51_MXC_INT_HS_I2C 64
386#define MX51_MXC_INT_RESV65 65 347#define MX51_MXC_INT_RESV65 65
387#define MX51_MXC_INT_RESV66 66 348#define MX51_MXC_INT_RESV66 66
388#define MX51_MXC_INT_SIM_IPB 67 349#define MX51_MXC_INT_SIM_IPB 67
389#define MX51_MXC_INT_SIM_DAT 68 350#define MX51_MXC_INT_SIM_DAT 68
390#define MX51_MXC_INT_IIM 69 351#define MX51_MXC_INT_IIM 69
391#define MX51_MXC_INT_ATA 70 352#define MX51_MXC_INT_ATA 70
392#define MX51_MXC_INT_CCM1 71 353#define MX51_MXC_INT_CCM1 71
393#define MX51_MXC_INT_CCM2 72 354#define MX51_MXC_INT_CCM2 72
394#define MX51_MXC_INT_GPC1 73 355#define MX51_MXC_INT_GPC1 73
395#define MX51_MXC_INT_GPC2 74 356#define MX51_MXC_INT_GPC2 74
396#define MX51_MXC_INT_SRC 75 357#define MX51_MXC_INT_SRC 75
397#define MX51_MXC_INT_NM 76 358#define MX51_MXC_INT_NM 76
398#define MX51_MXC_INT_PMU 77 359#define MX51_MXC_INT_PMU 77
399#define MX51_MXC_INT_CTI_IRQ 78 360#define MX51_MXC_INT_CTI_IRQ 78
400#define MX51_MXC_INT_CTI1_TG0 79 361#define MX51_MXC_INT_CTI1_TG0 79
401#define MX51_MXC_INT_CTI1_TG1 80 362#define MX51_MXC_INT_CTI1_TG1 80
402#define MX51_MXC_INT_MCG_ERR 81 363#define MX51_MXC_INT_MCG_ERR 81
403#define MX51_MXC_INT_MCG_TMR 82 364#define MX51_MXC_INT_MCG_TMR 82
404#define MX51_MXC_INT_MCG_FUNC 83 365#define MX51_MXC_INT_MCG_FUNC 83
405#define MX51_MXC_INT_GPU2_IRQ 84 366#define MX51_MXC_INT_GPU2_IRQ 84
406#define MX51_MXC_INT_GPU2_BUSY 85 367#define MX51_MXC_INT_GPU2_BUSY 85
407#define MX51_MXC_INT_RESV86 86 368#define MX51_MXC_INT_RESV86 86
408#define MX51_MXC_INT_FEC 87 369#define MX51_INT_FEC 87
409#define MX51_MXC_INT_OWIRE 88 370#define MX51_MXC_INT_OWIRE 88
410#define MX51_MXC_INT_CTI1_TG2 89 371#define MX51_MXC_INT_CTI1_TG2 89
411#define MX51_MXC_INT_SJC 90 372#define MX51_MXC_INT_SJC 90
412#define MX51_MXC_INT_SPDIF 91 373#define MX51_MXC_INT_SPDIF 91
413#define MX51_MXC_INT_TVE 92 374#define MX51_MXC_INT_TVE 92
414#define MX51_MXC_INT_FIRI 93 375#define MX51_MXC_INT_FIRI 93
415#define MX51_MXC_INT_PWM2 94 376#define MX51_MXC_INT_PWM2 94
416#define MX51_MXC_INT_SLIM_EXP 95 377#define MX51_MXC_INT_SLIM_EXP 95
417#define MX51_MXC_INT_SSI3 96 378#define MX51_MXC_INT_SSI3 96
418#define MX51_MXC_INT_EMI_BOOT 97 379#define MX51_MXC_INT_EMI_BOOT 97
419#define MX51_MXC_INT_CTI1_TG3 98 380#define MX51_MXC_INT_CTI1_TG3 98
420#define MX51_MXC_INT_SMC_RX 99 381#define MX51_MXC_INT_SMC_RX 99
421#define MX51_MXC_INT_VPU_IDLE 100 382#define MX51_MXC_INT_VPU_IDLE 100
422#define MX51_MXC_INT_EMI_NFC 101 383#define MX51_MXC_INT_EMI_NFC 101
423#define MX51_MXC_INT_GPU_IDLE 102 384#define MX51_MXC_INT_GPU_IDLE 102
424 385
425/* silicon revisions specific to i.MX51 */ 386/* silicon revisions specific to i.MX51 */
426#define MX51_CHIP_REV_1_0 0x10 387#define MX51_CHIP_REV_1_0 0x10
427#define MX51_CHIP_REV_1_1 0x11 388#define MX51_CHIP_REV_1_1 0x11
428#define MX51_CHIP_REV_1_2 0x12 389#define MX51_CHIP_REV_1_2 0x12
429#define MX51_CHIP_REV_1_3 0x13 390#define MX51_CHIP_REV_1_3 0x13
430#define MX51_CHIP_REV_2_0 0x20 391#define MX51_CHIP_REV_2_0 0x20
431#define MX51_CHIP_REV_2_1 0x21 392#define MX51_CHIP_REV_2_1 0x21
432#define MX51_CHIP_REV_2_2 0x22 393#define MX51_CHIP_REV_2_2 0x22
433#define MX51_CHIP_REV_2_3 0x23 394#define MX51_CHIP_REV_2_3 0x23
434#define MX51_CHIP_REV_3_0 0x30 395#define MX51_CHIP_REV_3_0 0x30
435#define MX51_CHIP_REV_3_1 0x31 396#define MX51_CHIP_REV_3_1 0x31
436#define MX51_CHIP_REV_3_2 0x32 397#define MX51_CHIP_REV_3_2 0x32
437
438/* Mandatory defines used globally */
439 398
440#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 399#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
441
442extern int mx51_revision(void); 400extern int mx51_revision(void);
443#endif 401#endif
444 402
445#endif /* __ASM_ARCH_MXC_MX51_H__ */ 403/* tape-out 1 defines */
404#define MX51_TZIC_BASE_ADDR_TO1 0x8fffc000
405
406#endif /* ifndef __MACH_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index 4acd1143a9bd..95be51bfe9a9 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright (C) 1999 ARM Limited 2 * Copyright (C) 1999 ARM Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd 3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 4 * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -28,8 +28,34 @@ static inline void arch_idle(void)
28 mxc91231_prepare_idle(); 28 mxc91231_prepare_idle();
29 } 29 }
30#endif 30#endif
31 31 /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */
32 cpu_do_idle(); 32 if (cpu_is_mx31() || cpu_is_mx35()) {
33 unsigned long reg = 0;
34 __asm__ __volatile__(
35 /* disable I and D cache */
36 "mrc p15, 0, %0, c1, c0, 0\n"
37 "bic %0, %0, #0x00001000\n"
38 "bic %0, %0, #0x00000004\n"
39 "mcr p15, 0, %0, c1, c0, 0\n"
40 /* invalidate I cache */
41 "mov %0, #0\n"
42 "mcr p15, 0, %0, c7, c5, 0\n"
43 /* clear and invalidate D cache */
44 "mov %0, #0\n"
45 "mcr p15, 0, %0, c7, c14, 0\n"
46 /* WFI */
47 "mov %0, #0\n"
48 "mcr p15, 0, %0, c7, c0, 4\n"
49 "nop\n" "nop\n" "nop\n" "nop\n"
50 "nop\n" "nop\n" "nop\n"
51 /* enable I and D cache */
52 "mrc p15, 0, %0, c1, c0, 0\n"
53 "orr %0, %0, #0x00001000\n"
54 "orr %0, %0, #0x00000004\n"
55 "mcr p15, 0, %0, c1, c0, 0\n"
56 : "=r" (reg));
57 } else
58 cpu_do_idle();
33} 59}
34 60
35void arch_reset(char mode, const char *cmd); 61void arch_reset(char mode, const char *cmd);
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index d9bd37e4667a..9dd9c2085aad 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -99,6 +99,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
99 uart_base = MX3X_UART2_BASE_ADDR; 99 uart_base = MX3X_UART2_BASE_ADDR;
100 break; 100 break;
101 case MACH_TYPE_MX51_BABBAGE: 101 case MACH_TYPE_MX51_BABBAGE:
102 case MACH_TYPE_EUKREA_CPUIMX51SD:
102 uart_base = MX51_UART1_BASE_ADDR; 103 uart_base = MX51_UART1_BASE_ADDR;
103 break; 104 break;
104 default: 105 default:
diff --git a/arch/arm/plat-mxc/iram_alloc.c b/arch/arm/plat-mxc/iram_alloc.c
new file mode 100644
index 000000000000..074c3869626a
--- /dev/null
+++ b/arch/arm/plat-mxc/iram_alloc.c
@@ -0,0 +1,73 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/kernel.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/spinlock.h>
24#include <linux/genalloc.h>
25#include <mach/iram.h>
26
27static unsigned long iram_phys_base;
28static void __iomem *iram_virt_base;
29static struct gen_pool *iram_pool;
30
31static inline void __iomem *iram_phys_to_virt(unsigned long p)
32{
33 return iram_virt_base + (p - iram_phys_base);
34}
35
36void __iomem *iram_alloc(unsigned int size, unsigned long *dma_addr)
37{
38 if (!iram_pool)
39 return NULL;
40
41 *dma_addr = gen_pool_alloc(iram_pool, size);
42 pr_debug("iram alloc - %dB@0x%lX\n", size, *dma_addr);
43 if (!*dma_addr)
44 return NULL;
45 return iram_phys_to_virt(*dma_addr);
46}
47EXPORT_SYMBOL(iram_alloc);
48
49void iram_free(unsigned long addr, unsigned int size)
50{
51 if (!iram_pool)
52 return;
53
54 gen_pool_free(iram_pool, addr, size);
55}
56EXPORT_SYMBOL(iram_free);
57
58int __init iram_init(unsigned long base, unsigned long size)
59{
60 iram_phys_base = base;
61
62 iram_pool = gen_pool_create(PAGE_SHIFT, -1);
63 if (!iram_pool)
64 return -ENOMEM;
65
66 gen_pool_add(iram_pool, base, size, -1);
67 iram_virt_base = ioremap(iram_phys_base, size);
68 if (!iram_virt_base)
69 return -EIO;
70
71 pr_debug("i.MX IRAM pool: %ld KB@0x%p\n", size / 1024, iram_virt_base);
72 return 0;
73}
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index 977c8f9a07a2..85e6fd212a41 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -102,6 +102,22 @@ static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
102 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); 102 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
103} 103}
104 104
105static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
106 unsigned offset, int val)
107{
108 if (val)
109 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
110 else
111 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
112}
113
114static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
115 unsigned offset, int val)
116{
117 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
118 __nmk_gpio_set_output(nmk_chip, offset, val);
119}
120
105static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, 121static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
106 pin_cfg_t cfg) 122 pin_cfg_t cfg)
107{ 123{
@@ -118,20 +134,29 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
118 [3] /* illegal */ = "??" 134 [3] /* illegal */ = "??"
119 }; 135 };
120 static const char *slpmnames[] = { 136 static const char *slpmnames[] = {
121 [NMK_GPIO_SLPM_INPUT] = "input", 137 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
122 [NMK_GPIO_SLPM_NOCHANGE] = "no-change", 138 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
123 }; 139 };
124 140
125 int pin = PIN_NUM(cfg); 141 int pin = PIN_NUM(cfg);
126 int pull = PIN_PULL(cfg); 142 int pull = PIN_PULL(cfg);
127 int af = PIN_ALT(cfg); 143 int af = PIN_ALT(cfg);
128 int slpm = PIN_SLPM(cfg); 144 int slpm = PIN_SLPM(cfg);
145 int output = PIN_DIR(cfg);
146 int val = PIN_VAL(cfg);
129 147
130 dev_dbg(nmk_chip->chip.dev, "pin %d: af %s, pull %s, slpm %s\n", 148 dev_dbg(nmk_chip->chip.dev, "pin %d: af %s, pull %s, slpm %s (%s%s)\n",
131 pin, afnames[af], pullnames[pull], slpmnames[slpm]); 149 pin, afnames[af], pullnames[pull], slpmnames[slpm],
150 output ? "output " : "input",
151 output ? (val ? "high" : "low") : "");
152
153 if (output)
154 __nmk_gpio_make_output(nmk_chip, offset, val);
155 else {
156 __nmk_gpio_make_input(nmk_chip, offset);
157 __nmk_gpio_set_pull(nmk_chip, offset, pull);
158 }
132 159
133 __nmk_gpio_make_input(nmk_chip, offset);
134 __nmk_gpio_set_pull(nmk_chip, offset, pull);
135 __nmk_gpio_set_slpm(nmk_chip, offset, slpm); 160 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
136 __nmk_gpio_set_mode(nmk_chip, offset, af); 161 __nmk_gpio_set_mode(nmk_chip, offset, af);
137} 162}
@@ -200,6 +225,10 @@ EXPORT_SYMBOL(nmk_config_pins);
200 * changed to an input (with pullup/down enabled) in sleep and deep sleep. If 225 * changed to an input (with pullup/down enabled) in sleep and deep sleep. If
201 * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was 226 * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was
202 * configured even when in sleep and deep sleep. 227 * configured even when in sleep and deep sleep.
228 *
229 * On DB8500v2 onwards, this setting loses the previous meaning and instead
230 * indicates if wakeup detection is enabled on the pin. Note that
231 * enable_irq_wake() will automatically enable wakeup detection.
203 */ 232 */
204int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) 233int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
205{ 234{
@@ -367,7 +396,27 @@ static void nmk_gpio_irq_unmask(unsigned int irq)
367 396
368static int nmk_gpio_irq_set_wake(unsigned int irq, unsigned int on) 397static int nmk_gpio_irq_set_wake(unsigned int irq, unsigned int on)
369{ 398{
370 return nmk_gpio_irq_modify(irq, WAKE, on); 399 struct nmk_gpio_chip *nmk_chip;
400 unsigned long flags;
401 int gpio;
402
403 gpio = NOMADIK_IRQ_TO_GPIO(irq);
404 nmk_chip = get_irq_chip_data(irq);
405 if (!nmk_chip)
406 return -EINVAL;
407
408 spin_lock_irqsave(&nmk_chip->lock, flags);
409#ifdef CONFIG_ARCH_U8500
410 if (cpu_is_u8500v2()) {
411 __nmk_gpio_set_slpm(nmk_chip, gpio,
412 on ? NMK_GPIO_SLPM_WAKEUP_ENABLE
413 : NMK_GPIO_SLPM_WAKEUP_DISABLE);
414 }
415#endif
416 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
417 spin_unlock_irqrestore(&nmk_chip->lock, flags);
418
419 return 0;
371} 420}
372 421
373static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type) 422static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
@@ -495,12 +544,8 @@ static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
495{ 544{
496 struct nmk_gpio_chip *nmk_chip = 545 struct nmk_gpio_chip *nmk_chip =
497 container_of(chip, struct nmk_gpio_chip, chip); 546 container_of(chip, struct nmk_gpio_chip, chip);
498 u32 bit = 1 << offset;
499 547
500 if (val) 548 __nmk_gpio_set_output(nmk_chip, offset, val);
501 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
502 else
503 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
504} 549}
505 550
506static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, 551static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
@@ -509,8 +554,7 @@ static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
509 struct nmk_gpio_chip *nmk_chip = 554 struct nmk_gpio_chip *nmk_chip =
510 container_of(chip, struct nmk_gpio_chip, chip); 555 container_of(chip, struct nmk_gpio_chip, chip);
511 556
512 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); 557 __nmk_gpio_make_output(nmk_chip, offset, val);
513 nmk_gpio_set_output(chip, offset, val);
514 558
515 return 0; 559 return 0;
516} 560}
@@ -534,7 +578,7 @@ static struct gpio_chip nmk_gpio_template = {
534 .can_sleep = 0, 578 .can_sleep = 0,
535}; 579};
536 580
537static int __init nmk_gpio_probe(struct platform_device *dev) 581static int __devinit nmk_gpio_probe(struct platform_device *dev)
538{ 582{
539 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; 583 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
540 struct nmk_gpio_chip *nmk_chip; 584 struct nmk_gpio_chip *nmk_chip;
diff --git a/arch/arm/plat-nomadik/include/plat/gpio.h b/arch/arm/plat-nomadik/include/plat/gpio.h
index aba355101f49..67b113d639d8 100644
--- a/arch/arm/plat-nomadik/include/plat/gpio.h
+++ b/arch/arm/plat-nomadik/include/plat/gpio.h
@@ -65,7 +65,9 @@ enum nmk_gpio_pull {
65/* Sleep mode */ 65/* Sleep mode */
66enum nmk_gpio_slpm { 66enum nmk_gpio_slpm {
67 NMK_GPIO_SLPM_INPUT, 67 NMK_GPIO_SLPM_INPUT,
68 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
68 NMK_GPIO_SLPM_NOCHANGE, 69 NMK_GPIO_SLPM_NOCHANGE,
70 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
69}; 71};
70 72
71extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode); 73extern int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode);
diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h
index 7eed11c1038d..8c5ae3f2acf8 100644
--- a/arch/arm/plat-nomadik/include/plat/pincfg.h
+++ b/arch/arm/plat-nomadik/include/plat/pincfg.h
@@ -19,12 +19,16 @@
19 * bit 9..10 - Alternate Function Selection 19 * bit 9..10 - Alternate Function Selection
20 * bit 11..12 - Pull up/down state 20 * bit 11..12 - Pull up/down state
21 * bit 13 - Sleep mode behaviour 21 * bit 13 - Sleep mode behaviour
22 * bit 14 - (sleep mode) Direction
23 * bit 15 - (sleep mode) Value (if output)
22 * 24 *
23 * to facilitate the definition, the following macros are provided 25 * to facilitate the definition, the following macros are provided
24 * 26 *
25 * PIN_CFG_DEFAULT - default config (0): 27 * PIN_CFG_DEFAULT - default config (0):
26 * pull up/down = disabled 28 * pull up/down = disabled
27 * sleep mode = input 29 * sleep mode = input/wakeup
30 * (sleep mode) direction = input
31 * (sleep mode) value = low
28 * 32 *
29 * PIN_CFG - default config with alternate function 33 * PIN_CFG - default config with alternate function
30 * PIN_CFG_PULL - default config with alternate function and pull up/down 34 * PIN_CFG_PULL - default config with alternate function and pull up/down
@@ -53,8 +57,36 @@ typedef unsigned long pin_cfg_t;
53#define PIN_SLPM_SHIFT 13 57#define PIN_SLPM_SHIFT 13
54#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT) 58#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
55#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT) 59#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
56#define PIN_SLPM_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT) 60#define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
57#define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT) 61#define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
62/* These two replace the above in DB8500v2+ */
63#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
64#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
65
66#define PIN_DIR_SHIFT 14
67#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
68#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
69#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
70#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
71
72#define PIN_VAL_SHIFT 15
73#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
74#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
75#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
76#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
77
78/* Shortcuts. Use these instead of separate DIR and VAL. */
79#define PIN_INPUT PIN_DIR_INPUT
80#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
81#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
82
83/*
84 * These are the same as the ones above, but should make more sense to the
85 * reader when seen along with a setting a pin to AF mode.
86 */
87#define PIN_SLPM_INPUT PIN_INPUT
88#define PIN_SLPM_OUTPUT_LOW PIN_OUTPUT_LOW
89#define PIN_SLPM_OUTPUT_HIGH PIN_OUTPUT_HIGH
58 90
59#define PIN_CFG_DEFAULT (PIN_PULL_NONE | PIN_SLPM_INPUT) 91#define PIN_CFG_DEFAULT (PIN_PULL_NONE | PIN_SLPM_INPUT)
60 92
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index 5177a9c5a25a..ecd6a488c497 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -18,6 +18,7 @@
18#define OMAP_ARCH_SMP_H 18#define OMAP_ARCH_SMP_H
19 19
20#include <asm/hardware/gic.h> 20#include <asm/hardware/gic.h>
21#include <asm/smp_mpidr.h>
21 22
22/* Needed for secondary core boot */ 23/* Needed for secondary core boot */
23extern void omap_secondary_startup(void); 24extern void omap_secondary_startup(void);
@@ -33,15 +34,4 @@ static inline void smp_cross_call(const struct cpumask *mask)
33 gic_raise_softirq(mask, 1); 34 gic_raise_softirq(mask, 1);
34} 35}
35 36
36/*
37 * Read MPIDR: Multiprocessor affinity register
38 */
39#define hard_smp_processor_id() \
40 ({ \
41 unsigned int cpunum; \
42 __asm__("mrc p15, 0, %0, c0, c0, 5" \
43 : "=r" (cpunum)); \
44 cpunum &= 0x0F; \
45 })
46
47#endif 37#endif
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
index 7b4eadc6df3a..abcc36eb1242 100644
--- a/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h
+++ b/arch/arm/plat-pxa/include/plat/pxa27x_keypad.h
@@ -25,6 +25,13 @@
25 * 25 *
26 * 4. matrix key and direct key will use the same debounce_interval by 26 * 4. matrix key and direct key will use the same debounce_interval by
27 * default, which should be sufficient in most cases 27 * default, which should be sufficient in most cases
28 *
29 * pxa168 keypad platform specific parameter
30 *
31 * NOTE:
32 * clear_wakeup_event callback is a workaround required to clear the
33 * keypad interrupt. The keypad wake must be cleared in addition to
34 * reading the MI/DI bits in the KPC register.
28 */ 35 */
29struct pxa27x_keypad_platform_data { 36struct pxa27x_keypad_platform_data {
30 37
@@ -52,6 +59,9 @@ struct pxa27x_keypad_platform_data {
52 59
53 /* key debounce interval */ 60 /* key debounce interval */
54 unsigned int debounce_interval; 61 unsigned int debounce_interval;
62
63 /* clear wakeup event requirement for pxa168 */
64 void (*clear_wakeup_event)(void);
55}; 65};
56 66
57extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info); 67extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info);
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index c6a855db2fb6..25960966af7c 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -7,7 +7,7 @@
7 7
8config PLAT_S5P 8config PLAT_S5P
9 bool 9 bool
10 depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5PV310) 10 depends on (ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5PV310)
11 default y 11 default y
12 select ARM_VIC if !ARCH_S5PV310 12 select ARM_VIC if !ARCH_S5PV310
13 select ARM_GIC if ARCH_S5PV310 13 select ARM_GIC if ARCH_S5PV310
@@ -30,7 +30,7 @@ config S5P_EXT_INT
30 bool 30 bool
31 help 31 help
32 Use the external interrupts (other than GPIO interrupts.) 32 Use the external interrupts (other than GPIO interrupts.)
33 Note: Do not choose this for S5P6440. 33 Note: Do not choose this for S5P6440 and S5P6450.
34 34
35config S5P_DEV_FIMC0 35config S5P_DEV_FIMC0
36 bool 36 bool
@@ -46,3 +46,8 @@ config S5P_DEV_FIMC2
46 bool 46 bool
47 help 47 help
48 Compile in platform device definitions for FIMC controller 2 48 Compile in platform device definitions for FIMC controller 2
49
50config S5P_DEV_ONENAND
51 bool
52 help
53 Compile in platform device definition for OneNAND controller
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index b2e029673950..f3e917e27da8 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o
24obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o 24obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o
25obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o 25obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o
26obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o 26obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o
27obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index b5e255265f20..8aaf4e6b60c3 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -74,6 +74,13 @@ struct clk clk_fout_epll = {
74 .ctrlbit = (1 << 31), 74 .ctrlbit = (1 << 31),
75}; 75};
76 76
77/* DPLL clock output */
78struct clk clk_fout_dpll = {
79 .name = "fout_dpll",
80 .id = -1,
81 .ctrlbit = (1 << 31),
82};
83
77/* VPLL clock output */ 84/* VPLL clock output */
78struct clk clk_fout_vpll = { 85struct clk clk_fout_vpll = {
79 .name = "fout_vpll", 86 .name = "fout_vpll",
@@ -122,6 +129,17 @@ struct clksrc_sources clk_src_epll = {
122 .nr_sources = ARRAY_SIZE(clk_src_epll_list), 129 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
123}; 130};
124 131
132/* Possible clock sources for DPLL Mux */
133static struct clk *clk_src_dpll_list[] = {
134 [0] = &clk_fin_dpll,
135 [1] = &clk_fout_dpll,
136};
137
138struct clksrc_sources clk_src_dpll = {
139 .sources = clk_src_dpll_list,
140 .nr_sources = ARRAY_SIZE(clk_src_dpll_list),
141};
142
125struct clk clk_vpll = { 143struct clk clk_vpll = {
126 .name = "vpll", 144 .name = "vpll",
127 .id = -1, 145 .id = -1,
@@ -145,6 +163,7 @@ static struct clk *s5p_clks[] __initdata = {
145 &clk_fout_apll, 163 &clk_fout_apll,
146 &clk_fout_mpll, 164 &clk_fout_mpll,
147 &clk_fout_epll, 165 &clk_fout_epll,
166 &clk_fout_dpll,
148 &clk_fout_vpll, 167 &clk_fout_vpll,
149 &clk_arm, 168 &clk_arm,
150 &clk_vpll, 169 &clk_vpll,
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index b07a078fd284..74f7f5a5446c 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -19,6 +19,7 @@
19#include <plat/cpu.h> 19#include <plat/cpu.h>
20#include <plat/s5p6440.h> 20#include <plat/s5p6440.h>
21#include <plat/s5p6442.h> 21#include <plat/s5p6442.h>
22#include <plat/s5p6450.h>
22#include <plat/s5pc100.h> 23#include <plat/s5pc100.h>
23#include <plat/s5pv210.h> 24#include <plat/s5pv210.h>
24#include <plat/s5pv310.h> 25#include <plat/s5pv310.h>
@@ -27,6 +28,7 @@
27 28
28static const char name_s5p6440[] = "S5P6440"; 29static const char name_s5p6440[] = "S5P6440";
29static const char name_s5p6442[] = "S5P6442"; 30static const char name_s5p6442[] = "S5P6442";
31static const char name_s5p6450[] = "S5P6450";
30static const char name_s5pc100[] = "S5PC100"; 32static const char name_s5pc100[] = "S5PC100";
31static const char name_s5pv210[] = "S5PV210/S5PC110"; 33static const char name_s5pv210[] = "S5PV210/S5PC110";
32static const char name_s5pv310[] = "S5PV310"; 34static const char name_s5pv310[] = "S5PV310";
@@ -38,7 +40,7 @@ static struct cpu_table cpu_ids[] __initdata = {
38 .map_io = s5p6440_map_io, 40 .map_io = s5p6440_map_io,
39 .init_clocks = s5p6440_init_clocks, 41 .init_clocks = s5p6440_init_clocks,
40 .init_uarts = s5p6440_init_uarts, 42 .init_uarts = s5p6440_init_uarts,
41 .init = s5p6440_init, 43 .init = s5p64x0_init,
42 .name = name_s5p6440, 44 .name = name_s5p6440,
43 }, { 45 }, {
44 .idcode = 0x36442000, 46 .idcode = 0x36442000,
@@ -49,6 +51,14 @@ static struct cpu_table cpu_ids[] __initdata = {
49 .init = s5p6442_init, 51 .init = s5p6442_init,
50 .name = name_s5p6442, 52 .name = name_s5p6442,
51 }, { 53 }, {
54 .idcode = 0x36450000,
55 .idmask = 0xffffff00,
56 .map_io = s5p6450_map_io,
57 .init_clocks = s5p6450_init_clocks,
58 .init_uarts = s5p6450_init_uarts,
59 .init = s5p64x0_init,
60 .name = name_s5p6450,
61 }, {
52 .idcode = 0x43100000, 62 .idcode = 0x43100000,
53 .idmask = 0xfffff000, 63 .idmask = 0xfffff000,
54 .map_io = s5pc100_map_io, 64 .map_io = s5pc100_map_io,
@@ -89,33 +99,11 @@ static struct map_desc s5p_iodesc[] __initdata = {
89 .length = SZ_64K, 99 .length = SZ_64K,
90 .type = MT_DEVICE, 100 .type = MT_DEVICE,
91 }, { 101 }, {
92 .virtual = (unsigned long)S3C_VA_UART,
93 .pfn = __phys_to_pfn(S3C_PA_UART),
94 .length = SZ_512K,
95 .type = MT_DEVICE,
96#ifdef CONFIG_ARM_VIC
97 }, {
98 .virtual = (unsigned long)VA_VIC0,
99 .pfn = __phys_to_pfn(S5P_PA_VIC0),
100 .length = SZ_16K,
101 .type = MT_DEVICE,
102 }, {
103 .virtual = (unsigned long)VA_VIC1,
104 .pfn = __phys_to_pfn(S5P_PA_VIC1),
105 .length = SZ_16K,
106 .type = MT_DEVICE,
107#endif
108 }, {
109 .virtual = (unsigned long)S3C_VA_TIMER, 102 .virtual = (unsigned long)S3C_VA_TIMER,
110 .pfn = __phys_to_pfn(S5P_PA_TIMER), 103 .pfn = __phys_to_pfn(S5P_PA_TIMER),
111 .length = SZ_16K, 104 .length = SZ_16K,
112 .type = MT_DEVICE, 105 .type = MT_DEVICE,
113 }, { 106 }, {
114 .virtual = (unsigned long)S5P_VA_GPIO,
115 .pfn = __phys_to_pfn(S5P_PA_GPIO),
116 .length = SZ_4K,
117 .type = MT_DEVICE,
118 }, {
119 .virtual = (unsigned long)S3C_VA_WATCHDOG, 107 .virtual = (unsigned long)S3C_VA_WATCHDOG,
120 .pfn = __phys_to_pfn(S3C_PA_WDT), 108 .pfn = __phys_to_pfn(S3C_PA_WDT),
121 .length = SZ_4K, 109 .length = SZ_4K,
diff --git a/arch/arm/mach-s5pv210/dev-onenand.c b/arch/arm/plat-s5p/dev-onenand.c
index f8ede33ee82b..6db926202caa 100644
--- a/arch/arm/mach-s5pv210/dev-onenand.c
+++ b/arch/arm/plat-s5p/dev-onenand.c
@@ -1,10 +1,12 @@
1/* 1/* linux/arch/arm/plat-s5p/dev-onenand.c
2 * linux/arch/arm/mach-s5pv210/dev-onenand.c 2 *
3 * Copyright 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
3 * 5 *
4 * Copyright (c) 2008-2010 Samsung Electronics 6 * Copyright (c) 2008-2010 Samsung Electronics
5 * Kyungmin Park <kyungmin.park@samsung.com> 7 * Kyungmin Park <kyungmin.park@samsung.com>
6 * 8 *
7 * S5PC110 series device definition for OneNAND devices 9 * S5P series device definition for OneNAND devices
8 * 10 *
9 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 12 * it under the terms of the GNU General Public License version 2 as
@@ -19,15 +21,15 @@
19#include <mach/irqs.h> 21#include <mach/irqs.h>
20#include <mach/map.h> 22#include <mach/map.h>
21 23
22static struct resource s5pc110_onenand_resources[] = { 24static struct resource s5p_onenand_resources[] = {
23 [0] = { 25 [0] = {
24 .start = S5PC110_PA_ONENAND, 26 .start = S5P_PA_ONENAND,
25 .end = S5PC110_PA_ONENAND + SZ_128K - 1, 27 .end = S5P_PA_ONENAND + SZ_128K - 1,
26 .flags = IORESOURCE_MEM, 28 .flags = IORESOURCE_MEM,
27 }, 29 },
28 [1] = { 30 [1] = {
29 .start = S5PC110_PA_ONENAND_DMA, 31 .start = S5P_PA_ONENAND_DMA,
30 .end = S5PC110_PA_ONENAND_DMA + SZ_8K - 1, 32 .end = S5P_PA_ONENAND_DMA + SZ_8K - 1,
31 .flags = IORESOURCE_MEM, 33 .flags = IORESOURCE_MEM,
32 }, 34 },
33 [2] = { 35 [2] = {
@@ -37,19 +39,19 @@ static struct resource s5pc110_onenand_resources[] = {
37 }, 39 },
38}; 40};
39 41
40struct platform_device s5pc110_device_onenand = { 42struct platform_device s5p_device_onenand = {
41 .name = "s5pc110-onenand", 43 .name = "s5pc110-onenand",
42 .id = -1, 44 .id = -1,
43 .num_resources = ARRAY_SIZE(s5pc110_onenand_resources), 45 .num_resources = ARRAY_SIZE(s5p_onenand_resources),
44 .resource = s5pc110_onenand_resources, 46 .resource = s5p_onenand_resources,
45}; 47};
46 48
47void s5pc110_onenand_set_platdata(struct onenand_platform_data *pdata) 49void s5p_onenand_set_platdata(struct onenand_platform_data *pdata)
48{ 50{
49 struct onenand_platform_data *pd; 51 struct onenand_platform_data *pd;
50 52
51 pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL); 53 pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL);
52 if (!pd) 54 if (!pd)
53 printk(KERN_ERR "%s: no memory for platform data\n", __func__); 55 printk(KERN_ERR "%s: no memory for platform data\n", __func__);
54 s5pc110_device_onenand.dev.platform_data = pd; 56 s5p_device_onenand.dev.platform_data = pd;
55} 57}
diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-s5p/dev-uart.c
index a89331ef4ae1..6a7342886171 100644
--- a/arch/arm/plat-s5p/dev-uart.c
+++ b/arch/arm/plat-s5p/dev-uart.c
@@ -119,6 +119,56 @@ static struct resource s5p_uart3_resource[] = {
119#endif 119#endif
120}; 120};
121 121
122static struct resource s5p_uart4_resource[] = {
123#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
124 [0] = {
125 .start = S5P_PA_UART4,
126 .end = S5P_PA_UART4 + S5P_SZ_UART,
127 .flags = IORESOURCE_MEM,
128 },
129 [1] = {
130 .start = IRQ_S5P_UART_RX4,
131 .end = IRQ_S5P_UART_RX4,
132 .flags = IORESOURCE_IRQ,
133 },
134 [2] = {
135 .start = IRQ_S5P_UART_TX4,
136 .end = IRQ_S5P_UART_TX4,
137 .flags = IORESOURCE_IRQ,
138 },
139 [3] = {
140 .start = IRQ_S5P_UART_ERR4,
141 .end = IRQ_S5P_UART_ERR4,
142 .flags = IORESOURCE_IRQ,
143 },
144#endif
145};
146
147static struct resource s5p_uart5_resource[] = {
148#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
149 [0] = {
150 .start = S5P_PA_UART5,
151 .end = S5P_PA_UART5 + S5P_SZ_UART,
152 .flags = IORESOURCE_MEM,
153 },
154 [1] = {
155 .start = IRQ_S5P_UART_RX5,
156 .end = IRQ_S5P_UART_RX5,
157 .flags = IORESOURCE_IRQ,
158 },
159 [2] = {
160 .start = IRQ_S5P_UART_TX5,
161 .end = IRQ_S5P_UART_TX5,
162 .flags = IORESOURCE_IRQ,
163 },
164 [3] = {
165 .start = IRQ_S5P_UART_ERR5,
166 .end = IRQ_S5P_UART_ERR5,
167 .flags = IORESOURCE_IRQ,
168 },
169#endif
170};
171
122struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = { 172struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = {
123 [0] = { 173 [0] = {
124 .resources = s5p_uart0_resource, 174 .resources = s5p_uart0_resource,
@@ -136,4 +186,12 @@ struct s3c24xx_uart_resources s5p_uart_resources[] __initdata = {
136 .resources = s5p_uart3_resource, 186 .resources = s5p_uart3_resource,
137 .nr_resources = ARRAY_SIZE(s5p_uart3_resource), 187 .nr_resources = ARRAY_SIZE(s5p_uart3_resource),
138 }, 188 },
189 [4] = {
190 .resources = s5p_uart4_resource,
191 .nr_resources = ARRAY_SIZE(s5p_uart4_resource),
192 },
193 [5] = {
194 .resources = s5p_uart5_resource,
195 .nr_resources = ARRAY_SIZE(s5p_uart5_resource),
196 },
139}; 197};
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h
index 4e8fe08cb70d..bf28fadee7ae 100644
--- a/arch/arm/plat-s5p/include/plat/pll.h
+++ b/arch/arm/plat-s5p/include/plat/pll.h
@@ -47,6 +47,7 @@ static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
47} 47}
48 48
49#define PLL46XX_KDIV_MASK (0xFFFF) 49#define PLL46XX_KDIV_MASK (0xFFFF)
50#define PLL4650C_KDIV_MASK (0xFFF)
50#define PLL46XX_MDIV_MASK (0x1FF) 51#define PLL46XX_MDIV_MASK (0x1FF)
51#define PLL46XX_PDIV_MASK (0x3F) 52#define PLL46XX_PDIV_MASK (0x3F)
52#define PLL46XX_SDIV_MASK (0x7) 53#define PLL46XX_SDIV_MASK (0x7)
@@ -57,6 +58,7 @@ static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
57enum pll46xx_type_t { 58enum pll46xx_type_t {
58 pll_4600, 59 pll_4600,
59 pll_4650, 60 pll_4650,
61 pll_4650c,
60}; 62};
61 63
62static inline unsigned long s5p_get_pll46xx(unsigned long baseclk, 64static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
@@ -72,6 +74,11 @@ static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
72 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK; 74 sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
73 kdiv = pll_con1 & PLL46XX_KDIV_MASK; 75 kdiv = pll_con1 & PLL46XX_KDIV_MASK;
74 76
77 if (pll_type == pll_4650c)
78 kdiv = pll_con1 & PLL4650C_KDIV_MASK;
79 else
80 kdiv = pll_con1 & PLL46XX_KDIV_MASK;
81
75 tmp = baseclk; 82 tmp = baseclk;
76 83
77 if (pll_type == pll_4600) { 84 if (pll_type == pll_4600) {
diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h
index 09418b1101fe..17036c898409 100644
--- a/arch/arm/plat-s5p/include/plat/s5p-clock.h
+++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h
@@ -1,7 +1,7 @@
1/* linux/arch/arm/plat-s5p/include/plat/s5p-clock.h 1/* linux/arch/arm/plat-s5p/include/plat/s5p-clock.h
2 * 2 *
3 * Copyright 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Header file for s5p clock support 6 * Header file for s5p clock support
7 * 7 *
@@ -20,6 +20,7 @@
20#define clk_fin_apll clk_ext_xtal_mux 20#define clk_fin_apll clk_ext_xtal_mux
21#define clk_fin_mpll clk_ext_xtal_mux 21#define clk_fin_mpll clk_ext_xtal_mux
22#define clk_fin_epll clk_ext_xtal_mux 22#define clk_fin_epll clk_ext_xtal_mux
23#define clk_fin_dpll clk_ext_xtal_mux
23#define clk_fin_vpll clk_ext_xtal_mux 24#define clk_fin_vpll clk_ext_xtal_mux
24#define clk_fin_hpll clk_ext_xtal_mux 25#define clk_fin_hpll clk_ext_xtal_mux
25 26
@@ -30,6 +31,7 @@ extern struct clk s5p_clk_27m;
30extern struct clk clk_fout_apll; 31extern struct clk clk_fout_apll;
31extern struct clk clk_fout_mpll; 32extern struct clk clk_fout_mpll;
32extern struct clk clk_fout_epll; 33extern struct clk clk_fout_epll;
34extern struct clk clk_fout_dpll;
33extern struct clk clk_fout_vpll; 35extern struct clk clk_fout_vpll;
34extern struct clk clk_arm; 36extern struct clk clk_arm;
35extern struct clk clk_vpll; 37extern struct clk clk_vpll;
@@ -37,8 +39,8 @@ extern struct clk clk_vpll;
37extern struct clksrc_sources clk_src_apll; 39extern struct clksrc_sources clk_src_apll;
38extern struct clksrc_sources clk_src_mpll; 40extern struct clksrc_sources clk_src_mpll;
39extern struct clksrc_sources clk_src_epll; 41extern struct clksrc_sources clk_src_epll;
42extern struct clksrc_sources clk_src_dpll;
40 43
41extern int s5p6440_clk48m_ctrl(struct clk *clk, int enable);
42extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable); 44extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
43 45
44#endif /* __ASM_PLAT_S5P_CLOCK_H */ 46#endif /* __ASM_PLAT_S5P_CLOCK_H */
diff --git a/arch/arm/plat-s5p/include/plat/s5p6440.h b/arch/arm/plat-s5p/include/plat/s5p6440.h
index a4cd75afeb3b..528585d2cafc 100644
--- a/arch/arm/plat-s5p/include/plat/s5p6440.h
+++ b/arch/arm/plat-s5p/include/plat/s5p6440.h
@@ -12,24 +12,23 @@
12 12
13 /* Common init code for S5P6440 related SoCs */ 13 /* Common init code for S5P6440 related SoCs */
14 14
15extern void s5p6440_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
16extern void s5p6440_register_clocks(void); 15extern void s5p6440_register_clocks(void);
17extern void s5p6440_setup_clocks(void); 16extern void s5p6440_setup_clocks(void);
18 17
19#ifdef CONFIG_CPU_S5P6440 18#ifdef CONFIG_CPU_S5P6440
20 19
21extern int s5p6440_init(void); 20extern int s5p64x0_init(void);
22extern void s5p6440_init_irq(void); 21extern void s5p6440_init_irq(void);
23extern void s5p6440_map_io(void); 22extern void s5p6440_map_io(void);
24extern void s5p6440_init_clocks(int xtal); 23extern void s5p6440_init_clocks(int xtal);
25 24
26#define s5p6440_init_uarts s5p6440_common_init_uarts 25extern void s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no);
27 26
28#else 27#else
29#define s5p6440_init_clocks NULL 28#define s5p6440_init_clocks NULL
30#define s5p6440_init_uarts NULL 29#define s5p6440_init_uarts NULL
31#define s5p6440_map_io NULL 30#define s5p6440_map_io NULL
32#define s5p6440_init NULL 31#define s5p64x0_init NULL
33#endif 32#endif
34 33
35/* S5P6440 timer */ 34/* S5P6440 timer */
diff --git a/arch/arm/plat-s5p/include/plat/s5p6450.h b/arch/arm/plat-s5p/include/plat/s5p6450.h
new file mode 100644
index 000000000000..640a41c26be3
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/s5p6450.h
@@ -0,0 +1,36 @@
1/* arch/arm/plat-s5p/include/plat/s5p6450.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Header file for s5p6450 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for S5P6450 related SoCs */
14
15extern void s5p6450_register_clocks(void);
16extern void s5p6450_setup_clocks(void);
17
18#ifdef CONFIG_CPU_S5P6450
19
20extern int s5p64x0_init(void);
21extern void s5p6450_init_irq(void);
22extern void s5p6450_map_io(void);
23extern void s5p6450_init_clocks(int xtal);
24
25extern void s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no);
26
27#else
28#define s5p6450_init_clocks NULL
29#define s5p6450_init_uarts NULL
30#define s5p6450_map_io NULL
31#define s5p64x0_init NULL
32#endif
33
34/* S5P6450 timer */
35
36extern struct sys_timer s5p6450_timer;
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 6412933d6fbb..9addb3dfb4bc 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -79,7 +79,7 @@ extern struct sysdev_class s3c2442_sysclass;
79extern struct sysdev_class s3c2443_sysclass; 79extern struct sysdev_class s3c2443_sysclass;
80extern struct sysdev_class s3c6410_sysclass; 80extern struct sysdev_class s3c6410_sysclass;
81extern struct sysdev_class s3c64xx_sysclass; 81extern struct sysdev_class s3c64xx_sysclass;
82extern struct sysdev_class s5p6440_sysclass; 82extern struct sysdev_class s5p64x0_sysclass;
83extern struct sysdev_class s5p6442_sysclass; 83extern struct sysdev_class s5p6442_sysclass;
84extern struct sysdev_class s5pv210_sysclass; 84extern struct sysdev_class s5pv210_sysclass;
85 85
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 85f6f23a510f..7d448e138792 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -67,13 +67,15 @@ extern struct platform_device s5pv210_device_spi0;
67extern struct platform_device s5pv210_device_spi1; 67extern struct platform_device s5pv210_device_spi1;
68extern struct platform_device s5p6440_device_spi0; 68extern struct platform_device s5p6440_device_spi0;
69extern struct platform_device s5p6440_device_spi1; 69extern struct platform_device s5p6440_device_spi1;
70extern struct platform_device s5p6450_device_spi0;
71extern struct platform_device s5p6450_device_spi1;
70 72
71extern struct platform_device s3c_device_hwmon; 73extern struct platform_device s3c_device_hwmon;
72 74
73extern struct platform_device s3c_device_nand; 75extern struct platform_device s3c_device_nand;
74extern struct platform_device s3c_device_onenand; 76extern struct platform_device s3c_device_onenand;
75extern struct platform_device s3c64xx_device_onenand1; 77extern struct platform_device s3c64xx_device_onenand1;
76extern struct platform_device s5pc110_device_onenand; 78extern struct platform_device s5p_device_onenand;
77 79
78extern struct platform_device s3c_device_usbgadget; 80extern struct platform_device s3c_device_usbgadget;
79extern struct platform_device s3c_device_usb_hsotg; 81extern struct platform_device s3c_device_usb_hsotg;
@@ -95,6 +97,9 @@ extern struct platform_device s5p6442_device_spi;
95extern struct platform_device s5p6440_device_pcm; 97extern struct platform_device s5p6440_device_pcm;
96extern struct platform_device s5p6440_device_iis; 98extern struct platform_device s5p6440_device_iis;
97 99
100extern struct platform_device s5p6450_device_iis0;
101extern struct platform_device s5p6450_device_pcm0;
102
98extern struct platform_device s5pc100_device_ac97; 103extern struct platform_device s5pc100_device_ac97;
99extern struct platform_device s5pc100_device_pcm0; 104extern struct platform_device s5pc100_device_pcm0;
100extern struct platform_device s5pc100_device_pcm1; 105extern struct platform_device s5pc100_device_pcm1;
diff --git a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
index 5fe6721b57f7..810744213120 100644
--- a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
@@ -32,6 +32,12 @@ enum dma_ch {
32 DMACH_UART2_TX, 32 DMACH_UART2_TX,
33 DMACH_UART3_RX, 33 DMACH_UART3_RX,
34 DMACH_UART3_TX, 34 DMACH_UART3_TX,
35 DMACH_UART4_RX,
36 DMACH_UART4_TX,
37 DMACH_UART5_RX,
38 DMACH_UART5_TX,
39 DMACH_USI_RX,
40 DMACH_USI_TX,
35 DMACH_IRDA, 41 DMACH_IRDA,
36 DMACH_I2S0_RX, 42 DMACH_I2S0_RX,
37 DMACH_I2S0_TX, 43 DMACH_I2S0_TX,
@@ -64,6 +70,20 @@ enum dma_ch {
64 DMACH_MSM_REQ2, 70 DMACH_MSM_REQ2,
65 DMACH_MSM_REQ1, 71 DMACH_MSM_REQ1,
66 DMACH_MSM_REQ0, 72 DMACH_MSM_REQ0,
73 DMACH_SLIMBUS0_RX,
74 DMACH_SLIMBUS0_TX,
75 DMACH_SLIMBUS0AUX_RX,
76 DMACH_SLIMBUS0AUX_TX,
77 DMACH_SLIMBUS1_RX,
78 DMACH_SLIMBUS1_TX,
79 DMACH_SLIMBUS2_RX,
80 DMACH_SLIMBUS2_TX,
81 DMACH_SLIMBUS3_RX,
82 DMACH_SLIMBUS3_TX,
83 DMACH_SLIMBUS4_RX,
84 DMACH_SLIMBUS4_TX,
85 DMACH_SLIMBUS5_RX,
86 DMACH_SLIMBUS5_TX,
67 /* END Marker, also used to denote a reserved channel */ 87 /* END Marker, also used to denote a reserved channel */
68 DMACH_MAX, 88 DMACH_MAX,
69}; 89};
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index b226f7405e6b..ff1a561b326e 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -68,7 +68,7 @@ struct s3c64xx_spi_info {
68extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 68extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
69extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 69extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
70extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 70extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
71extern void s5p6440_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 71extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
72extern void s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 72extern void s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
73 73
74#endif /* __S3C64XX_PLAT_SPI_H */ 74#endif /* __S3C64XX_PLAT_SPI_H */
diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S
index 37fa593884ee..e91270e4f640 100644
--- a/arch/arm/plat-spear/include/plat/debug-macro.S
+++ b/arch/arm/plat-spear/include/plat/debug-macro.S
@@ -14,11 +14,9 @@
14#include <linux/amba/serial.h> 14#include <linux/amba/serial.h>
15#include <mach/spear.h> 15#include <mach/spear.h>
16 16
17 .macro addruart, rx 17 .macro addruart, rp, rv
18 mrc p15, 0, \rx, c1, c0 18 mov \rp, #SPEAR_DBG_UART_BASE @ Physical base
19 tst \rx, #1 @ MMU enabled? 19 mov \rv, #VA_SPEAR_DBG_UART_BASE @ Virtual base
20 moveq \rx, #SPEAR_DBG_UART_BASE @ Physical base
21 movne \rx, #VA_SPEAR_DBG_UART_BASE @ Virtual base
22 .endm 20 .endm
23 21
24 .macro senduart, rd, rx 22 .macro senduart, rd, rx
diff --git a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
index 1b9348bf0e49..d3a0985c9681 100644
--- a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
+++ b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
@@ -16,13 +16,10 @@
16 * http://www.gnu.org/copyleft/gpl.html 16 * http://www.gnu.org/copyleft/gpl.html
17 */ 17 */
18 18
19 .macro addruart, rx, tmp 19 .macro addruart, rp, rv
20 mrc p15, 0, \rx, c1, c0 20 mov \rp, #0x00070000
21 tst \rx, #1 @ MMU enabled? 21 add \rv, \rp, #0xf0000000 @ virtual base
22 moveq \rx, #0x80000000 @ physical base address 22 add \rp, \rp, #0x80000000 @ physical base
23 addeq \rx, \rx, #0x00070000
24 movne \rx, #0xf0000000 @ virtual base
25 addne \rx, \rx, #0x00070000
26 .endm 23 .endm
27 24
28 .macro senduart,rd,rx 25 .macro senduart,rd,rx
diff --git a/arch/arm/plat-tcc/Kconfig b/arch/arm/plat-tcc/Kconfig
new file mode 100644
index 000000000000..1bf499570f42
--- /dev/null
+++ b/arch/arm/plat-tcc/Kconfig
@@ -0,0 +1,20 @@
1if ARCH_TCC_926
2
3menu "Telechips ARM926-based CPUs"
4
5choice
6 prompt "Telechips CPU type:"
7 default ARCH_TCC8K
8
9config ARCH_TCC8K
10 bool TCC8000
11 select USB_ARCH_HAS_OHCI
12 help
13 Support for Telechips TCC8000 systems
14
15endchoice
16
17source "arch/arm/mach-tcc8k/Kconfig"
18
19endmenu
20endif
diff --git a/arch/arm/plat-tcc/Makefile b/arch/arm/plat-tcc/Makefile
new file mode 100644
index 000000000000..eceabc869b8f
--- /dev/null
+++ b/arch/arm/plat-tcc/Makefile
@@ -0,0 +1,3 @@
1# "Telechips Platform Common Modules"
2
3obj-y := clock.o system.o
diff --git a/arch/arm/plat-tcc/clock.c b/arch/arm/plat-tcc/clock.c
new file mode 100644
index 000000000000..f3ced10d5271
--- /dev/null
+++ b/arch/arm/plat-tcc/clock.c
@@ -0,0 +1,179 @@
1/*
2 * Clock framework for Telechips SoCs
3 * Based on arch/arm/plat-mxc/clock.c
4 *
5 * Copyright (C) 2004 - 2005 Nokia corporation
6 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
7 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
8 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
9 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
10 * Copyright 2010 Hans J. Koch, hjk@linutronix.de
11 *
12 * Licensed under the terms of the GPL v2.
13 */
14
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/errno.h>
18#include <linux/module.h>
19#include <linux/mutex.h>
20#include <linux/string.h>
21
22#include <mach/clock.h>
23#include <mach/hardware.h>
24
25static DEFINE_MUTEX(clocks_mutex);
26
27/*-------------------------------------------------------------------------
28 * Standard clock functions defined in include/linux/clk.h
29 *-------------------------------------------------------------------------*/
30
31static void __clk_disable(struct clk *clk)
32{
33 BUG_ON(clk->refcount == 0);
34
35 if (!(--clk->refcount) && clk->disable) {
36 /* Unconditionally disable the clock in hardware */
37 clk->disable(clk);
38 /* recursively disable parents */
39 if (clk->parent)
40 __clk_disable(clk->parent);
41 }
42}
43
44static int __clk_enable(struct clk *clk)
45{
46 int ret = 0;
47
48 if (clk->refcount++ == 0 && clk->enable) {
49 if (clk->parent)
50 ret = __clk_enable(clk->parent);
51 if (ret)
52 return ret;
53 else
54 return clk->enable(clk);
55 }
56
57 return 0;
58}
59
60/* This function increments the reference count on the clock and enables the
61 * clock if not already enabled. The parent clock tree is recursively enabled
62 */
63int clk_enable(struct clk *clk)
64{
65 int ret = 0;
66
67 if (!clk)
68 return -EINVAL;
69
70 mutex_lock(&clocks_mutex);
71 ret = __clk_enable(clk);
72 mutex_unlock(&clocks_mutex);
73
74 return ret;
75}
76EXPORT_SYMBOL_GPL(clk_enable);
77
78/* This function decrements the reference count on the clock and disables
79 * the clock when reference count is 0. The parent clock tree is
80 * recursively disabled
81 */
82void clk_disable(struct clk *clk)
83{
84 if (!clk)
85 return;
86
87 mutex_lock(&clocks_mutex);
88 __clk_disable(clk);
89 mutex_unlock(&clocks_mutex);
90}
91EXPORT_SYMBOL_GPL(clk_disable);
92
93/* Retrieve the *current* clock rate. If the clock itself
94 * does not provide a special calculation routine, ask
95 * its parent and so on, until one is able to return
96 * a valid clock rate
97 */
98unsigned long clk_get_rate(struct clk *clk)
99{
100 if (!clk)
101 return 0UL;
102
103 if (clk->get_rate)
104 return clk->get_rate(clk);
105
106 return clk_get_rate(clk->parent);
107}
108EXPORT_SYMBOL_GPL(clk_get_rate);
109
110/* Round the requested clock rate to the nearest supported
111 * rate that is less than or equal to the requested rate.
112 * This is dependent on the clock's current parent.
113 */
114long clk_round_rate(struct clk *clk, unsigned long rate)
115{
116 if (!clk)
117 return 0;
118 if (!clk->round_rate)
119 return 0;
120
121 return clk->round_rate(clk, rate);
122}
123EXPORT_SYMBOL_GPL(clk_round_rate);
124
125/* Set the clock to the requested clock rate. The rate must
126 * match a supported rate exactly based on what clk_round_rate returns
127 */
128int clk_set_rate(struct clk *clk, unsigned long rate)
129{
130 int ret = -EINVAL;
131
132 if (!clk)
133 return ret;
134 if (!clk->set_rate || !rate)
135 return ret;
136
137 mutex_lock(&clocks_mutex);
138 ret = clk->set_rate(clk, rate);
139 mutex_unlock(&clocks_mutex);
140
141 return ret;
142}
143EXPORT_SYMBOL_GPL(clk_set_rate);
144
145/* Set the clock's parent to another clock source */
146int clk_set_parent(struct clk *clk, struct clk *parent)
147{
148 struct clk *old;
149 int ret = -EINVAL;
150
151 if (!clk)
152 return ret;
153 if (!clk->set_parent || !parent)
154 return ret;
155
156 mutex_lock(&clocks_mutex);
157 old = clk->parent;
158 if (clk->refcount)
159 __clk_enable(parent);
160 ret = clk->set_parent(clk, parent);
161 if (ret)
162 old = parent;
163 if (clk->refcount)
164 __clk_disable(old);
165 mutex_unlock(&clocks_mutex);
166
167 return ret;
168}
169EXPORT_SYMBOL_GPL(clk_set_parent);
170
171/* Retrieve the clock's parent clock source */
172struct clk *clk_get_parent(struct clk *clk)
173{
174 if (!clk)
175 return NULL;
176
177 return clk->parent;
178}
179EXPORT_SYMBOL_GPL(clk_get_parent);
diff --git a/arch/arm/plat-tcc/include/mach/clkdev.h b/arch/arm/plat-tcc/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_MACH_CLKDEV_H
2#define __ASM_MACH_CLKDEV_H
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do { } while (0)
6
7#endif
diff --git a/arch/arm/plat-tcc/include/mach/clock.h b/arch/arm/plat-tcc/include/mach/clock.h
new file mode 100644
index 000000000000..a12f58ad71a8
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/clock.h
@@ -0,0 +1,48 @@
1/*
2 * Low level clock header file for Telechips TCC architecture
3 * (C) 2010 Hans J. Koch <hjk@linutronix.de>
4 *
5 * Licensed under the GPL v2.
6 */
7
8#ifndef __ASM_ARCH_TCC_CLOCK_H__
9#define __ASM_ARCH_TCC_CLOCK_H__
10
11#ifndef __ASSEMBLY__
12
13struct clk {
14 struct clk *parent;
15 /* id number of a root clock, 0 for normal clocks */
16 int root_id;
17 /* Reference count of clock enable/disable */
18 int refcount;
19 /* Address of associated BCLKCTRx register. Must be set. */
20 void __iomem *bclkctr;
21 /* Bit position for BCLKCTRx. Must be set. */
22 int bclk_shift;
23 /* Address of ACLKxxx register, if any. */
24 void __iomem *aclkreg;
25 /* get the current clock rate (always a fresh value) */
26 unsigned long (*get_rate) (struct clk *);
27 /* Function ptr to set the clock to a new rate. The rate must match a
28 supported rate returned from round_rate. Leave blank if clock is not
29 programmable */
30 int (*set_rate) (struct clk *, unsigned long);
31 /* Function ptr to round the requested clock rate to the nearest
32 supported rate that is less than or equal to the requested rate. */
33 unsigned long (*round_rate) (struct clk *, unsigned long);
34 /* Function ptr to enable the clock. Leave blank if clock can not
35 be gated. */
36 int (*enable) (struct clk *);
37 /* Function ptr to disable the clock. Leave blank if clock can not
38 be gated. */
39 void (*disable) (struct clk *);
40 /* Function ptr to set the parent clock of the clock. */
41 int (*set_parent) (struct clk *, struct clk *);
42};
43
44int clk_register(struct clk *clk);
45void clk_unregister(struct clk *clk);
46
47#endif /* __ASSEMBLY__ */
48#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/arch/arm/plat-tcc/include/mach/debug-macro.S b/arch/arm/plat-tcc/include/mach/debug-macro.S
new file mode 100644
index 000000000000..7662f736e42b
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/debug-macro.S
@@ -0,0 +1,32 @@
1/*
2 * Copyright (C) 1994-1999 Russell King
3 * Copyright (C) 2008-2009 Telechips
4 * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12 .macro addruart, rp, rv
13 moveq \rp, #0x90000000 @ physical base address
14 movne \rv, #0xF1000000 @ virtual base
15 orr \rp, \rp, #0x00007000 @ UART0
16 orr \rv, \rv, #0x00007000 @ UART0
17 .endm
18
19 .macro senduart,rd,rx
20 strb \rd, [\rx, #0x44]
21 .endm
22
23 .macro waituart,rd,rx
24 .endm
25
26 .macro busyuart,rd,rx
271001:
28 ldr \rd, [\rx, #0x14]
29 tst \rd, #0x20
30
31 beq 1001b
32 .endm
diff --git a/arch/arm/plat-tcc/include/mach/entry-macro.S b/arch/arm/plat-tcc/include/mach/entry-macro.S
new file mode 100644
index 000000000000..748f401e4b6d
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/entry-macro.S
@@ -0,0 +1,68 @@
1/*
2 * include/asm-arm/arch-tcc83x/entry-macro.S
3 *
4 * Author : <linux@telechips.com>
5 * Created: June 10, 2008
6 * Description: Low-level IRQ helper macros for Telechips-based platforms
7 *
8 * Copyright (C) 2008-2009 Telechips
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <mach/hardware.h>
16#include <mach/irqs.h>
17
18 .macro disable_fiq
19 .endm
20
21 .macro get_irqnr_preamble, base, tmp
22 .endm
23
24 .macro arch_ret_to_user, tmp1, tmp2
25 .endm
26
27 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
28
29 ldr \base, =0xF2003000 @ base address of PIC registers
30
31 @@ read MREQ register of PIC0
32
33 mov \irqnr, #0
34 ldr \irqstat, [\base, #0x00000014 ] @ lower 32 interrupts
35 cmp \irqstat, #0
36 bne 1001f
37
38 @@ read MREQ register of PIC1
39
40 ldr \irqstat, [\base, #0x00000094] @ upper 32 interrupts
41 cmp \irqstat, #0
42 beq 1002f
43 mov \irqnr, #0x20
44
451001:
46 movs \tmp, \irqstat, lsl #16
47 movne \irqstat, \tmp
48 addeq \irqnr, \irqnr, #16
49
50 movs \tmp, \irqstat, lsl #8
51 movne \irqstat, \tmp
52 addeq \irqnr, \irqnr, #8
53
54 movs \tmp, \irqstat, lsl #4
55 movne \irqstat, \tmp
56 addeq \irqnr, \irqnr, #4
57
58 movs \tmp, \irqstat, lsl #2
59 movne \irqstat, \tmp
60 addeq \irqnr, \irqnr, #2
61
62 movs \tmp, \irqstat, lsl #1
63 addeq \irqnr, \irqnr, #1
64 orrs \base, \base, #1
651002:
66 @@ exit here, Z flag unset if IRQ
67
68 .endm
diff --git a/arch/arm/plat-tcc/include/mach/hardware.h b/arch/arm/plat-tcc/include/mach/hardware.h
new file mode 100644
index 000000000000..e70d126ccaf3
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/hardware.h
@@ -0,0 +1,43 @@
1/*
2 * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
3 * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
4 * and Dirk Behme <dirk.behme@de.bosch.com>
5 * Rewritten by: <linux@telechips.com>
6 * Description: Hardware definitions for TCC8300 processors and boards
7 *
8 * Copyright (C) 2001 RidgeRun, Inc.
9 * Copyright (C) 2008-2009 Telechips
10 *
11 * Modifications for mainline (C) 2009 Hans J. Koch <hjk@linutronix.de>
12 *
13 * Licensed under the terms of the GNU Pulic License version 2.
14 */
15
16#ifndef __ASM_ARCH_TCC_HARDWARE_H
17#define __ASM_ARCH_TCC_HARDWARE_H
18
19#include <asm/sizes.h>
20#ifndef __ASSEMBLER__
21#include <asm/types.h>
22#endif
23#include <mach/io.h>
24
25/*
26 * ----------------------------------------------------------------------------
27 * Clocks
28 * ----------------------------------------------------------------------------
29 */
30#define CLKGEN_REG_BASE 0xfffece00
31#define ARM_CKCTL (CLKGEN_REG_BASE + 0x0)
32#define ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4)
33#define ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8)
34#define ARM_EWUPCT (CLKGEN_REG_BASE + 0xC)
35#define ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10)
36#define ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14)
37#define ARM_SYSST (CLKGEN_REG_BASE + 0x18)
38#define ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24)
39
40/* DPLL control registers */
41#define DPLL_CTL 0xfffecf00
42
43#endif /* __ASM_ARCH_TCC_HARDWARE_H */
diff --git a/arch/arm/plat-tcc/include/mach/io.h b/arch/arm/plat-tcc/include/mach/io.h
new file mode 100644
index 000000000000..3e911d3ea0f1
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/io.h
@@ -0,0 +1,23 @@
1/*
2 * IO definitions for TCC8000 processors and boards
3 *
4 * Copyright (C) 1997-1999 Russell King
5 * Copyright (C) 2008-2009 Telechips
6 * Copyright (C) 2010 Hans J. Koch <hjk@linutronix.de>
7 *
8 * Licensed under the terms of the GNU Public License version 2.
9 */
10
11#ifndef __ASM_ARM_ARCH_IO_H
12#define __ASM_ARM_ARCH_IO_H
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16/*
17 * We don't actually have real ISA nor PCI buses, but there is so many
18 * drivers out there that might just work if we fake them...
19 */
20#define __io(a) __typesafe_io(a)
21#define __mem_pci(a) (a)
22
23#endif
diff --git a/arch/arm/plat-tcc/include/mach/irqs.h b/arch/arm/plat-tcc/include/mach/irqs.h
new file mode 100644
index 000000000000..da863894d498
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/irqs.h
@@ -0,0 +1,83 @@
1/*
2 * IRQ definitions for TCC8xxx
3 *
4 * Copyright (C) 2008-2009 Telechips
5 * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
6 *
7 * Licensed under the terms of the GPL v2.
8 *
9 */
10
11#ifndef __ASM_ARCH_TCC_IRQS_H
12#define __ASM_ARCH_TCC_IRQS_H
13
14#define NR_IRQS 64
15
16/* PIC0 interrupts */
17#define INT_ADMA1 0
18#define INT_BDMA 1
19#define INT_ADMA0 2
20#define INT_GDMA1 3
21#define INT_I2S0RX 4
22#define INT_I2S0TX 5
23#define INT_TC 6
24#define INT_UART0 7
25#define INT_USBD 8
26#define INT_SPI0TX 9
27#define INT_UDMA 10
28#define INT_LIRQ 11
29#define INT_GDMA2 12
30#define INT_GDMA0 13
31#define INT_TC32 14
32#define INT_LCD 15
33#define INT_ADC 16
34#define INT_I2C 17
35#define INT_RTCP 18
36#define INT_RTCA 19
37#define INT_NFC 20
38#define INT_SD0 21
39#define INT_GSB0 22
40#define INT_PK 23
41#define INT_USBH0 24
42#define INT_USBH1 25
43#define INT_G2D 26
44#define INT_ECC 27
45#define INT_SPI0RX 28
46#define INT_UART1 29
47#define INT_MSCL 30
48#define INT_GSB1 31
49/* PIC1 interrupts */
50#define INT_E0 32
51#define INT_E1 33
52#define INT_E2 34
53#define INT_E3 35
54#define INT_E4 36
55#define INT_E5 37
56#define INT_E6 38
57#define INT_E7 39
58#define INT_UART2 40
59#define INT_UART3 41
60#define INT_SPI1TX 42
61#define INT_SPI1RX 43
62#define INT_GSB2 44
63#define INT_SPDIF 45
64#define INT_CDIF 46
65#define INT_VBON 47
66#define INT_VBOFF 48
67#define INT_SD1 49
68#define INT_UART4 50
69#define INT_GDMA3 51
70#define INT_I2S1RX 52
71#define INT_I2S1TX 53
72#define INT_CAN0 54
73#define INT_CAN1 55
74#define INT_GSB3 56
75#define INT_KRST 57
76#define INT_UNUSED 58
77#define INT_SD0D3 59
78#define INT_SD1D3 60
79#define INT_GPS0 61
80#define INT_GPS1 62
81#define INT_GPS2 63
82
83#endif /* ASM_ARCH_TCC_IRQS_H */
diff --git a/arch/arm/plat-tcc/include/mach/memory.h b/arch/arm/plat-tcc/include/mach/memory.h
new file mode 100644
index 000000000000..cd91ba8a670b
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/memory.h
@@ -0,0 +1,18 @@
1/*
2 * Copyright (C) 1999 ARM Limited
3 * Copyright (C) 2000 RidgeRun, Inc.
4 * Copyright (C) 2008-2009 Telechips
5 * Copyright (C) 2010 Hans J. Koch <hjk@linutronix.de>
6 *
7 * Licensed under the terms of the GPL v2.
8 */
9
10#ifndef __ASM_ARCH_MEMORY_H
11#define __ASM_ARCH_MEMORY_H
12
13/*
14 * Physical DRAM offset.
15 */
16#define PHYS_OFFSET UL(0x20000000)
17
18#endif
diff --git a/arch/arm/plat-tcc/include/mach/system.h b/arch/arm/plat-tcc/include/mach/system.h
new file mode 100644
index 000000000000..909e6035d843
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/system.h
@@ -0,0 +1,31 @@
1/*
2 * Author: <linux@telechips.com>
3 * Created: June 10, 2008
4 * Description: LINUX SYSTEM FUNCTIONS for TCC83x
5 *
6 * Copyright (C) 2008-2009 Telechips
7 *
8 * Licensed under the terms of the GPL v2.
9 *
10 */
11
12#ifndef __ASM_ARCH_SYSTEM_H
13#define __ASM_ARCH_SYSTEM_H
14#include <linux/clk.h>
15
16#include <asm/mach-types.h>
17#include <mach/hardware.h>
18
19extern void plat_tcc_reboot(void);
20
21static inline void arch_idle(void)
22{
23 cpu_do_idle();
24}
25
26static inline void arch_reset(char mode, const char *cmd)
27{
28 plat_tcc_reboot();
29}
30
31#endif
diff --git a/arch/arm/plat-tcc/include/mach/tcc8k-regs.h b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h
new file mode 100644
index 000000000000..1d9428295332
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h
@@ -0,0 +1,807 @@
1/*
2 * Telechips TCC8000 register definitions
3 *
4 * (C) 2009 Hans J. Koch <hjk@linutronix.de>
5 *
6 * Licensed under the terms of the GPLv2.
7 */
8
9#ifndef TCC8K_REGS_H
10#define TCC8K_REGS_H
11
12#include <linux/types.h>
13
14#define EXT_SDRAM_BASE 0x20000000
15#define INT_SRAM_BASE 0x30000000
16#define INT_SRAM_SIZE SZ_32K
17#define CS0_BASE 0x40000000
18#define CS1_BASE 0x50000000
19#define CS1_SIZE SZ_64K
20#define CS2_BASE 0x60000000
21#define CS3_BASE 0x70000000
22#define AHB_PERI_BASE 0x80000000
23#define AHB_PERI_SIZE SZ_64K
24#define APB0_PERI_BASE 0x90000000
25#define APB0_PERI_SIZE SZ_128K
26#define APB1_PERI_BASE 0x98000000
27#define APB1_PERI_SIZE SZ_128K
28#define DATA_TCM_BASE 0xa0000000
29#define DATA_TCM_SIZE SZ_8K
30#define EXT_MEM_CTRL_BASE 0xf0000000
31#define EXT_MEM_CTRL_SIZE SZ_4K
32
33#define CS1_BASE_VIRT (void __iomem *)0xf7000000
34#define AHB_PERI_BASE_VIRT (void __iomem *)0xf4000000
35#define APB0_PERI_BASE_VIRT (void __iomem *)0xf1000000
36#define APB1_PERI_BASE_VIRT (void __iomem *)0xf2000000
37#define EXT_MEM_CTRL_BASE_VIRT (void __iomem *)0xf3000000
38#define INT_SRAM_BASE_VIRT (void __iomem *)0xf5000000
39#define DATA_TCM_BASE_VIRT (void __iomem *)0xf6000000
40
41#define __REG(x) (*((volatile u32 *)(x)))
42
43/* USB Device Controller Registers */
44#define UDC_BASE (AHB_PERI_BASE_VIRT + 0x8000)
45#define UDC_BASE_PHYS (AHB_PERI_BASE + 0x8000)
46
47#define UDC_IR_OFFS 0x00
48#define UDC_EIR_OFFS 0x04
49#define UDC_EIER_OFFS 0x08
50#define UDC_FAR_OFFS 0x0c
51#define UDC_FNR_OFFS 0x10
52#define UDC_EDR_OFFS 0x14
53#define UDC_RT_OFFS 0x18
54#define UDC_SSR_OFFS 0x1c
55#define UDC_SCR_OFFS 0x20
56#define UDC_EP0SR_OFFS 0x24
57#define UDC_EP0CR_OFFS 0x28
58
59#define UDC_ESR_OFFS 0x2c
60#define UDC_ECR_OFFS 0x30
61#define UDC_BRCR_OFFS 0x34
62#define UDC_BWCR_OFFS 0x38
63#define UDC_MPR_OFFS 0x3c
64#define UDC_DCR_OFFS 0x40
65#define UDC_DTCR_OFFS 0x44
66#define UDC_DFCR_OFFS 0x48
67#define UDC_DTTCR1_OFFS 0x4c
68#define UDC_DTTCR2_OFFS 0x50
69#define UDC_ESR2_OFFS 0x54
70
71#define UDC_SCR2_OFFS 0x58
72#define UDC_EP0BUF_OFFS 0x60
73#define UDC_EP1BUF_OFFS 0x64
74#define UDC_EP2BUF_OFFS 0x68
75#define UDC_EP3BUF_OFFS 0x6c
76#define UDC_PLICR_OFFS 0xa0
77#define UDC_PCR_OFFS 0xa4
78
79#define UDC_UPCR0_OFFS 0xc8
80#define UDC_UPCR1_OFFS 0xcc
81#define UDC_UPCR2_OFFS 0xd0
82#define UDC_UPCR3_OFFS 0xd4
83
84/* Bits in UDC_EIR */
85#define UDC_EIR_EP0I (1 << 0)
86#define UDC_EIR_EP1I (1 << 1)
87#define UDC_EIR_EP2I (1 << 2)
88#define UDC_EIR_EP3I (1 << 3)
89#define UDC_EIR_EPI_MASK 0x0f
90
91/* Bits in UDC_EIER */
92#define UDC_EIER_EP0IE (1 << 0)
93#define UDC_EIER_EP1IE (1 << 1)
94#define UDC_EIER_EP2IE (1 << 2)
95#define UDC_EIER_EP3IE (1 << 3)
96
97/* Bits in UDC_FNR */
98#define UDC_FNR_FN_MASK 0x7ff
99#define UDC_FNR_SM (1 << 13)
100#define UDC_FNR_FTL (1 << 14)
101
102/* Bits in UDC_SSR */
103#define UDC_SSR_HFRES (1 << 0)
104#define UDC_SSR_HFSUSP (1 << 1)
105#define UDC_SSR_HFRM (1 << 2)
106#define UDC_SSR_SDE (1 << 3)
107#define UDC_SSR_HSP (1 << 4)
108#define UDC_SSR_DM (1 << 5)
109#define UDC_SSR_DP (1 << 6)
110#define UDC_SSR_TBM (1 << 7)
111#define UDC_SSR_VBON (1 << 8)
112#define UDC_SSR_VBOFF (1 << 9)
113#define UDC_SSR_EOERR (1 << 10)
114#define UDC_SSR_DCERR (1 << 11)
115#define UDC_SSR_TCERR (1 << 12)
116#define UDC_SSR_BSERR (1 << 13)
117#define UDC_SSR_TMERR (1 << 14)
118#define UDC_SSR_BAERR (1 << 15)
119
120/* Bits in UDC_SCR */
121#define UDC_SCR_HRESE (1 << 0)
122#define UDC_SCR_HSSPE (1 << 1)
123#define UDC_SCR_RRDE (1 << 5)
124#define UDC_SCR_SPDEN (1 << 6)
125#define UDC_SCR_DIEN (1 << 12)
126
127/* Bits in UDC_EP0SR */
128#define UDC_EP0SR_RSR (1 << 0)
129#define UDC_EP0SR_TST (1 << 1)
130#define UDC_EP0SR_SHT (1 << 4)
131#define UDC_EP0SR_LWO (1 << 6)
132
133/* Bits in UDC_EP0CR */
134#define UDC_EP0CR_ESS (1 << 1)
135
136/* Bits in UDC_ESR */
137#define UDC_ESR_RPS (1 << 0)
138#define UDC_ESR_TPS (1 << 1)
139#define UDC_ESR_LWO (1 << 4)
140#define UDC_ESR_FFS (1 << 6)
141
142/* Bits in UDC_ECR */
143#define UDC_ECR_ESS (1 << 1)
144#define UDC_ECR_CDP (1 << 2)
145
146#define UDC_ECR_FLUSH (1 << 6)
147#define UDC_ECR_DUEN (1 << 7)
148
149/* Bits in UDC_UPCR0 */
150#define UDC_UPCR0_VBD (1 << 1)
151#define UDC_UPCR0_VBDS (1 << 6)
152#define UDC_UPCR0_RCD_12 (0x0 << 9)
153#define UDC_UPCR0_RCD_24 (0x1 << 9)
154#define UDC_UPCR0_RCD_48 (0x2 << 9)
155#define UDC_UPCR0_RCS_EXT (0x1 << 11)
156#define UDC_UPCR0_RCS_XTAL (0x0 << 11)
157
158/* Bits in UDC_UPCR1 */
159#define UDC_UPCR1_CDT(x) ((x) << 0)
160#define UDC_UPCR1_OTGT(x) ((x) << 3)
161#define UDC_UPCR1_SQRXT(x) ((x) << 8)
162#define UDC_UPCR1_TXFSLST(x) ((x) << 12)
163
164/* Bits in UDC_UPCR2 */
165#define UDC_UPCR2_TP (1 << 0)
166#define UDC_UPCR2_TXRT(x) ((x) << 2)
167#define UDC_UPCR2_TXVRT(x) ((x) << 5)
168#define UDC_UPCR2_OPMODE(x) ((x) << 9)
169#define UDC_UPCR2_XCVRSEL(x) ((x) << 12)
170#define UDC_UPCR2_TM (1 << 14)
171
172/* USB Host Controller registers */
173#define USBH0_BASE (AHB_PERI_BASE_VIRT + 0xb000)
174#define USBH1_BASE (AHB_PERI_BASE_VIRT + 0xb800)
175
176#define OHCI_INT_ENABLE_OFFS 0x10
177
178#define RH_DESCRIPTOR_A_OFFS 0x48
179#define RH_DESCRIPTOR_B_OFFS 0x4c
180
181#define USBHTCFG0_OFFS 0x100
182#define USBHHCFG0_OFFS 0x104
183#define USBHHCFG1_OFFS 0x104
184
185/* DMA controller registers */
186#define DMAC0_BASE (AHB_PERI_BASE + 0x4000)
187#define DMAC1_BASE (AHB_PERI_BASE + 0xa000)
188#define DMAC2_BASE (AHB_PERI_BASE + 0x4800)
189#define DMAC3_BASE (AHB_PERI_BASE + 0xa800)
190
191#define DMAC_CH_OFFSET(ch) (ch * 0x30)
192
193#define ST_SADR_OFFS 0x00
194#define SPARAM_OFFS 0x04
195#define C_SADR_OFFS 0x0c
196#define ST_DADR_OFFS 0x10
197#define DPARAM_OFFS 0x14
198#define C_DADR_OFFS 0x1c
199#define HCOUNT_OFFS 0x20
200#define CHCTRL_OFFS 0x24
201#define RPTCTRL_OFFS 0x28
202#define EXTREQ_A_OFFS 0x2c
203
204/* Bits in CHCTRL register */
205#define CHCTRL_EN (1 << 0)
206
207#define CHCTRL_IEN (1 << 2)
208#define CHCTRL_FLAG (1 << 3)
209#define CHCTRL_WSIZE8 (0 << 4)
210#define CHCTRL_WSIZE16 (1 << 4)
211#define CHCTRL_WSIZE32 (2 << 4)
212
213#define CHCTRL_BSIZE1 (0 << 6)
214#define CHCTRL_BSIZE2 (1 << 6)
215#define CHCTRL_BSIZE4 (2 << 6)
216#define CHCTRL_BSIZE8 (3 << 6)
217
218#define CHCTRL_TYPE_SINGLE_E (0 << 8)
219#define CHCTRL_TYPE_HW (1 << 8)
220#define CHCTRL_TYPE_SW (2 << 8)
221#define CHCTRL_TYPE_SINGLE_L (3 << 8)
222
223#define CHCTRL_BST (1 << 10)
224
225/* Use DMA controller 0, channel 2 for USB */
226#define USB_DMA_BASE (DMAC0_BASE + DMAC_CH_OFFSET(2))
227
228/* NAND flash controller registers */
229#define NFC_BASE (AHB_PERI_BASE_VIRT + 0xd000)
230#define NFC_BASE_PHYS (AHB_PERI_BASE + 0xd000)
231
232#define NFC_CMD_OFFS 0x00
233#define NFC_LADDR_OFFS 0x04
234#define NFC_BADDR_OFFS 0x08
235#define NFC_SADDR_OFFS 0x0c
236#define NFC_WDATA_OFFS 0x10
237#define NFC_LDATA_OFFS 0x20
238#define NFC_SDATA_OFFS 0x40
239#define NFC_CTRL_OFFS 0x50
240#define NFC_PSTART_OFFS 0x54
241#define NFC_RSTART_OFFS 0x58
242#define NFC_DSIZE_OFFS 0x5c
243#define NFC_IREQ_OFFS 0x60
244#define NFC_RST_OFFS 0x64
245#define NFC_CTRL1_OFFS 0x68
246#define NFC_MDATA_OFFS 0x70
247
248#define NFC_WDATA_PHYS_ADDR (NFC_BASE_PHYS + NFC_WDATA_OFFS)
249
250/* Bits in NFC_CTRL */
251#define NFC_CTRL_BHLD_MASK (0xf << 0)
252#define NFC_CTRL_BPW_MASK (0xf << 4)
253#define NFC_CTRL_BSTP_MASK (0xf << 8)
254#define NFC_CTRL_CADDR_MASK (0x7 << 12)
255#define NFC_CTRL_CADDR_1 (0x0 << 12)
256#define NFC_CTRL_CADDR_2 (0x1 << 12)
257#define NFC_CTRL_CADDR_3 (0x2 << 12)
258#define NFC_CTRL_CADDR_4 (0x3 << 12)
259#define NFC_CTRL_CADDR_5 (0x4 << 12)
260#define NFC_CTRL_MSK (1 << 15)
261#define NFC_CTRL_PSIZE256 (0 << 16)
262#define NFC_CTRL_PSIZE512 (1 << 16)
263#define NFC_CTRL_PSIZE1024 (2 << 16)
264#define NFC_CTRL_PSIZE2048 (3 << 16)
265#define NFC_CTRL_PSIZE4096 (4 << 16)
266#define NFC_CTRL_PSIZE_MASK (7 << 16)
267#define NFC_CTRL_BSIZE1 (0 << 19)
268#define NFC_CTRL_BSIZE2 (1 << 19)
269#define NFC_CTRL_BSIZE4 (2 << 19)
270#define NFC_CTRL_BSIZE8 (3 << 19)
271#define NFC_CTRL_BSIZE_MASK (3 << 19)
272#define NFC_CTRL_RDY (1 << 21)
273#define NFC_CTRL_CS0SEL (1 << 22)
274#define NFC_CTRL_CS1SEL (1 << 23)
275#define NFC_CTRL_CS2SEL (1 << 24)
276#define NFC_CTRL_CS3SEL (1 << 25)
277#define NFC_CTRL_CSMASK (0xf << 22)
278#define NFC_CTRL_BW (1 << 26)
279#define NFC_CTRL_FS (1 << 27)
280#define NFC_CTRL_DEN (1 << 28)
281#define NFC_CTRL_READ_IEN (1 << 29)
282#define NFC_CTRL_PROG_IEN (1 << 30)
283#define NFC_CTRL_RDY_IEN (1 << 31)
284
285/* Bits in NFC_IREQ */
286#define NFC_IREQ_IRQ0 (1 << 0)
287#define NFC_IREQ_IRQ1 (1 << 1)
288#define NFC_IREQ_IRQ2 (1 << 2)
289
290#define NFC_IREQ_FLAG0 (1 << 4)
291#define NFC_IREQ_FLAG1 (1 << 5)
292#define NFC_IREQ_FLAG2 (1 << 6)
293
294/* MMC controller registers */
295#define MMC0_BASE (AHB_PERI_BASE_VIRT + 0xe000)
296#define MMC1_BASE (AHB_PERI_BASE_VIRT + 0xe800)
297
298/* UART base addresses */
299
300#define UART0_BASE (APB0_PERI_BASE_VIRT + 0x07000)
301#define UART0_BASE_PHYS (APB0_PERI_BASE + 0x07000)
302#define UART1_BASE (APB0_PERI_BASE_VIRT + 0x08000)
303#define UART1_BASE_PHYS (APB0_PERI_BASE + 0x08000)
304#define UART2_BASE (APB0_PERI_BASE_VIRT + 0x09000)
305#define UART2_BASE_PHYS (APB0_PERI_BASE + 0x09000)
306#define UART3_BASE (APB0_PERI_BASE_VIRT + 0x0a000)
307#define UART3_BASE_PHYS (APB0_PERI_BASE + 0x0a000)
308#define UART4_BASE (APB0_PERI_BASE_VIRT + 0x15000)
309#define UART4_BASE_PHYS (APB0_PERI_BASE + 0x15000)
310
311#define UART_BASE UART0_BASE
312#define UART_BASE_PHYS UART0_BASE_PHYS
313
314/* ECC controller */
315#define ECC_CTR_BASE (APB0_PERI_BASE_VIRT + 0xd000)
316
317#define ECC_CTRL_OFFS 0x00
318#define ECC_BASE_OFFS 0x04
319#define ECC_MASK_OFFS 0x08
320#define ECC_CLEAR_OFFS 0x0c
321#define ECC4_0_OFFS 0x10
322#define ECC4_1_OFFS 0x14
323
324#define ECC_EADDR0_OFFS 0x50
325
326#define ECC_ERRNUM_OFFS 0x90
327#define ECC_IREQ_OFFS 0x94
328
329/* Bits in ECC_CTRL */
330#define ECC_CTRL_ECC4_DIEN (1 << 28)
331#define ECC_CTRL_ECC8_DIEN (1 << 29)
332#define ECC_CTRL_ECC12_DIEN (1 << 30)
333#define ECC_CTRL_ECC_DISABLE 0x0
334#define ECC_CTRL_ECC_SLC_ENC 0x8
335#define ECC_CTRL_ECC_SLC_DEC 0x9
336#define ECC_CTRL_ECC4_ENC 0xa
337#define ECC_CTRL_ECC4_DEC 0xb
338#define ECC_CTRL_ECC8_ENC 0xc
339#define ECC_CTRL_ECC8_DEC 0xd
340#define ECC_CTRL_ECC12_ENC 0xe
341#define ECC_CTRL_ECC12_DEC 0xf
342
343/* Bits in ECC_IREQ */
344#define ECC_IREQ_E4DI (1 << 4)
345
346#define ECC_IREQ_E4DF (1 << 20)
347#define ECC_IREQ_E4EF (1 << 21)
348
349/* Interrupt controller */
350
351#define PIC0_BASE (APB1_PERI_BASE_VIRT + 0x3000)
352#define PIC0_BASE_PHYS (APB1_PERI_BASE + 0x3000)
353
354#define PIC0_IEN_OFFS 0x00
355#define PIC0_CREQ_OFFS 0x04
356#define PIC0_IREQ_OFFS 0x08
357#define PIC0_IRQSEL_OFFS 0x0c
358#define PIC0_SRC_OFFS 0x10
359#define PIC0_MREQ_OFFS 0x14
360#define PIC0_TSTREQ_OFFS 0x18
361#define PIC0_POL_OFFS 0x1c
362#define PIC0_IRQ_OFFS 0x20
363#define PIC0_FIQ_OFFS 0x24
364#define PIC0_MIRQ_OFFS 0x28
365#define PIC0_MFIQ_OFFS 0x2c
366#define PIC0_TMODE_OFFS 0x30
367#define PIC0_SYNC_OFFS 0x34
368#define PIC0_WKUP_OFFS 0x38
369#define PIC0_TMODEA_OFFS 0x3c
370#define PIC0_INTOEN_OFFS 0x40
371#define PIC0_MEN0_OFFS 0x44
372#define PIC0_MEN_OFFS 0x48
373
374#define PIC0_IEN __REG(PIC0_BASE + PIC0_IEN_OFFS)
375#define PIC0_IEN_PHYS __REG(PIC0_BASE_PHYS + PIC0_IEN_OFFS)
376#define PIC0_CREQ __REG(PIC0_BASE + PIC0_CREQ_OFFS)
377#define PIC0_CREQ_PHYS __REG(PIC0_BASE_PHYS + PIC0_CREQ_OFFS)
378#define PIC0_IREQ __REG(PIC0_BASE + PIC0_IREQ_OFFS)
379#define PIC0_IRQSEL __REG(PIC0_BASE + PIC0_IRQSEL_OFFS)
380#define PIC0_IRQSEL_PHYS __REG(PIC0_BASE_PHYS + PIC0_IRQSEL_OFFS)
381#define PIC0_SRC __REG(PIC0_BASE + PIC0_SRC_OFFS)
382#define PIC0_MREQ __REG(PIC0_BASE + PIC0_MREQ_OFFS)
383#define PIC0_TSTREQ __REG(PIC0_BASE + PIC0_TSTREQ_OFFS)
384#define PIC0_POL __REG(PIC0_BASE + PIC0_POL_OFFS)
385#define PIC0_IRQ __REG(PIC0_BASE + PIC0_IRQ_OFFS)
386#define PIC0_FIQ __REG(PIC0_BASE + PIC0_FIQ_OFFS)
387#define PIC0_MIRQ __REG(PIC0_BASE + PIC0_MIRQ_OFFS)
388#define PIC0_MFIQ __REG(PIC0_BASE + PIC0_MFIQ_OFFS)
389#define PIC0_TMODE __REG(PIC0_BASE + PIC0_TMODE_OFFS)
390#define PIC0_TMODE_PHYS __REG(PIC0_BASE_PHYS + PIC0_TMODE_OFFS)
391#define PIC0_SYNC __REG(PIC0_BASE + PIC0_SYNC_OFFS)
392#define PIC0_WKUP __REG(PIC0_BASE + PIC0_WKUP_OFFS)
393#define PIC0_TMODEA __REG(PIC0_BASE + PIC0_TMODEA_OFFS)
394#define PIC0_INTOEN __REG(PIC0_BASE + PIC0_INTOEN_OFFS)
395#define PIC0_MEN0 __REG(PIC0_BASE + PIC0_MEN0_OFFS)
396#define PIC0_MEN __REG(PIC0_BASE + PIC0_MEN_OFFS)
397
398#define PIC1_BASE (APB1_PERI_BASE_VIRT + 0x3080)
399
400#define PIC1_IEN_OFFS 0x00
401#define PIC1_CREQ_OFFS 0x04
402#define PIC1_IREQ_OFFS 0x08
403#define PIC1_IRQSEL_OFFS 0x0c
404#define PIC1_SRC_OFFS 0x10
405#define PIC1_MREQ_OFFS 0x14
406#define PIC1_TSTREQ_OFFS 0x18
407#define PIC1_POL_OFFS 0x1c
408#define PIC1_IRQ_OFFS 0x20
409#define PIC1_FIQ_OFFS 0x24
410#define PIC1_MIRQ_OFFS 0x28
411#define PIC1_MFIQ_OFFS 0x2c
412#define PIC1_TMODE_OFFS 0x30
413#define PIC1_SYNC_OFFS 0x34
414#define PIC1_WKUP_OFFS 0x38
415#define PIC1_TMODEA_OFFS 0x3c
416#define PIC1_INTOEN_OFFS 0x40
417#define PIC1_MEN1_OFFS 0x44
418#define PIC1_MEN_OFFS 0x48
419
420#define PIC1_IEN __REG(PIC1_BASE + PIC1_IEN_OFFS)
421#define PIC1_CREQ __REG(PIC1_BASE + PIC1_CREQ_OFFS)
422#define PIC1_IREQ __REG(PIC1_BASE + PIC1_IREQ_OFFS)
423#define PIC1_IRQSEL __REG(PIC1_BASE + PIC1_IRQSEL_OFFS)
424#define PIC1_SRC __REG(PIC1_BASE + PIC1_SRC_OFFS)
425#define PIC1_MREQ __REG(PIC1_BASE + PIC1_MREQ_OFFS)
426#define PIC1_TSTREQ __REG(PIC1_BASE + PIC1_TSTREQ_OFFS)
427#define PIC1_POL __REG(PIC1_BASE + PIC1_POL_OFFS)
428#define PIC1_IRQ __REG(PIC1_BASE + PIC1_IRQ_OFFS)
429#define PIC1_FIQ __REG(PIC1_BASE + PIC1_FIQ_OFFS)
430#define PIC1_MIRQ __REG(PIC1_BASE + PIC1_MIRQ_OFFS)
431#define PIC1_MFIQ __REG(PIC1_BASE + PIC1_MFIQ_OFFS)
432#define PIC1_TMODE __REG(PIC1_BASE + PIC1_TMODE_OFFS)
433#define PIC1_SYNC __REG(PIC1_BASE + PIC1_SYNC_OFFS)
434#define PIC1_WKUP __REG(PIC1_BASE + PIC1_WKUP_OFFS)
435#define PIC1_TMODEA __REG(PIC1_BASE + PIC1_TMODEA_OFFS)
436#define PIC1_INTOEN __REG(PIC1_BASE + PIC1_INTOEN_OFFS)
437#define PIC1_MEN1 __REG(PIC1_BASE + PIC1_MEN1_OFFS)
438#define PIC1_MEN __REG(PIC1_BASE + PIC1_MEN_OFFS)
439
440/* Timer registers */
441#define TIMER_BASE (APB1_PERI_BASE_VIRT + 0x4000)
442#define TIMER_BASE_PHYS (APB1_PERI_BASE + 0x4000)
443
444#define TWDCFG_OFFS 0x70
445
446#define TC32EN_OFFS 0x80
447#define TC32LDV_OFFS 0x84
448#define TC32CMP0_OFFS 0x88
449#define TC32CMP1_OFFS 0x8c
450#define TC32PCNT_OFFS 0x90
451#define TC32MCNT_OFFS 0x94
452#define TC32IRQ_OFFS 0x98
453
454/* Bits in TC32EN */
455#define TC32EN_PRESCALE_MASK 0x00ffffff
456#define TC32EN_ENABLE (1 << 24)
457#define TC32EN_LOADZERO (1 << 25)
458#define TC32EN_STOPMODE (1 << 26)
459#define TC32EN_LDM0 (1 << 28)
460#define TC32EN_LDM1 (1 << 29)
461
462/* Bits in TC32IRQ */
463#define TC32IRQ_MSTAT_MASK 0x0000001f
464#define TC32IRQ_RSTAT_MASK (0x1f << 8)
465#define TC32IRQ_IRQEN0 (1 << 16)
466#define TC32IRQ_IRQEN1 (1 << 17)
467#define TC32IRQ_IRQEN2 (1 << 18)
468#define TC32IRQ_IRQEN3 (1 << 19)
469#define TC32IRQ_IRQEN4 (1 << 20)
470#define TC32IRQ_RSYNC (1 << 30)
471#define TC32IRQ_IRQCLR (1 << 31)
472
473/* GPIO registers */
474#define GPIOPD_BASE (APB1_PERI_BASE_VIRT + 0x5000)
475
476#define GPIOPD_DAT_OFFS 0x00
477#define GPIOPD_DOE_OFFS 0x04
478#define GPIOPD_FS0_OFFS 0x08
479#define GPIOPD_FS1_OFFS 0x0c
480#define GPIOPD_FS2_OFFS 0x10
481#define GPIOPD_RPU_OFFS 0x30
482#define GPIOPD_RPD_OFFS 0x34
483#define GPIOPD_DV0_OFFS 0x38
484#define GPIOPD_DV1_OFFS 0x3c
485
486#define GPIOPS_BASE (APB1_PERI_BASE_VIRT + 0x5000)
487
488#define GPIOPS_DAT_OFFS 0x40
489#define GPIOPS_DOE_OFFS 0x44
490#define GPIOPS_FS0_OFFS 0x48
491#define GPIOPS_FS1_OFFS 0x4c
492#define GPIOPS_FS2_OFFS 0x50
493#define GPIOPS_FS3_OFFS 0x54
494#define GPIOPS_RPU_OFFS 0x70
495#define GPIOPS_RPD_OFFS 0x74
496#define GPIOPS_DV0_OFFS 0x78
497#define GPIOPS_DV1_OFFS 0x7c
498
499#define GPIOPS_FS1_SDH0_BITS 0x000000ff
500#define GPIOPS_FS1_SDH1_BITS 0x0000ff00
501
502#define GPIOPU_BASE (APB1_PERI_BASE_VIRT + 0x5000)
503
504#define GPIOPU_DAT_OFFS 0x80
505#define GPIOPU_DOE_OFFS 0x84
506#define GPIOPU_FS0_OFFS 0x88
507#define GPIOPU_FS1_OFFS 0x8c
508#define GPIOPU_FS2_OFFS 0x90
509#define GPIOPU_RPU_OFFS 0xb0
510#define GPIOPU_RPD_OFFS 0xb4
511#define GPIOPU_DV0_OFFS 0xb8
512#define GPIOPU_DV1_OFFS 0xbc
513
514#define GPIOPU_FS0_TXD0 (1 << 0)
515#define GPIOPU_FS0_RXD0 (1 << 1)
516#define GPIOPU_FS0_CTS0 (1 << 2)
517#define GPIOPU_FS0_RTS0 (1 << 3)
518#define GPIOPU_FS0_TXD1 (1 << 4)
519#define GPIOPU_FS0_RXD1 (1 << 5)
520#define GPIOPU_FS0_CTS1 (1 << 6)
521#define GPIOPU_FS0_RTS1 (1 << 7)
522#define GPIOPU_FS0_TXD2 (1 << 8)
523#define GPIOPU_FS0_RXD2 (1 << 9)
524#define GPIOPU_FS0_CTS2 (1 << 10)
525#define GPIOPU_FS0_RTS2 (1 << 11)
526#define GPIOPU_FS0_TXD3 (1 << 12)
527#define GPIOPU_FS0_RXD3 (1 << 13)
528#define GPIOPU_FS0_CTS3 (1 << 14)
529#define GPIOPU_FS0_RTS3 (1 << 15)
530#define GPIOPU_FS0_TXD4 (1 << 16)
531#define GPIOPU_FS0_RXD4 (1 << 17)
532#define GPIOPU_FS0_CTS4 (1 << 18)
533#define GPIOPU_FS0_RTS4 (1 << 19)
534
535#define GPIOFC_BASE (APB1_PERI_BASE_VIRT + 0x5000)
536
537#define GPIOFC_DAT_OFFS 0xc0
538#define GPIOFC_DOE_OFFS 0xc4
539#define GPIOFC_FS0_OFFS 0xc8
540#define GPIOFC_FS1_OFFS 0xcc
541#define GPIOFC_FS2_OFFS 0xd0
542#define GPIOFC_FS3_OFFS 0xd4
543#define GPIOFC_RPU_OFFS 0xf0
544#define GPIOFC_RPD_OFFS 0xf4
545#define GPIOFC_DV0_OFFS 0xf8
546#define GPIOFC_DV1_OFFS 0xfc
547
548#define GPIOFD_BASE (APB1_PERI_BASE_VIRT + 0x5000)
549
550#define GPIOFD_DAT_OFFS 0x100
551#define GPIOFD_DOE_OFFS 0x104
552#define GPIOFD_FS0_OFFS 0x108
553#define GPIOFD_FS1_OFFS 0x10c
554#define GPIOFD_FS2_OFFS 0x110
555#define GPIOFD_RPU_OFFS 0x130
556#define GPIOFD_RPD_OFFS 0x134
557#define GPIOFD_DV0_OFFS 0x138
558#define GPIOFD_DV1_OFFS 0x13c
559
560#define GPIOLC_BASE (APB1_PERI_BASE_VIRT + 0x5000)
561
562#define GPIOLC_DAT_OFFS 0x140
563#define GPIOLC_DOE_OFFS 0x144
564#define GPIOLC_FS0_OFFS 0x148
565#define GPIOLC_FS1_OFFS 0x14c
566#define GPIOLC_RPU_OFFS 0x170
567#define GPIOLC_RPD_OFFS 0x174
568#define GPIOLC_DV0_OFFS 0x178
569#define GPIOLC_DV1_OFFS 0x17c
570
571#define GPIOLD_BASE (APB1_PERI_BASE_VIRT + 0x5000)
572
573#define GPIOLD_DAT_OFFS 0x180
574#define GPIOLD_DOE_OFFS 0x184
575#define GPIOLD_FS0_OFFS 0x188
576#define GPIOLD_FS1_OFFS 0x18c
577#define GPIOLD_FS2_OFFS 0x190
578#define GPIOLD_RPU_OFFS 0x1b0
579#define GPIOLD_RPD_OFFS 0x1b4
580#define GPIOLD_DV0_OFFS 0x1b8
581#define GPIOLD_DV1_OFFS 0x1bc
582
583#define GPIOAD_BASE (APB1_PERI_BASE_VIRT + 0x5000)
584
585#define GPIOAD_DAT_OFFS 0x1c0
586#define GPIOAD_DOE_OFFS 0x1c4
587#define GPIOAD_FS0_OFFS 0x1c8
588#define GPIOAD_RPU_OFFS 0x1f0
589#define GPIOAD_RPD_OFFS 0x1f4
590#define GPIOAD_DV0_OFFS 0x1f8
591#define GPIOAD_DV1_OFFS 0x1fc
592
593#define GPIOXC_BASE (APB1_PERI_BASE_VIRT + 0x5000)
594
595#define GPIOXC_DAT_OFFS 0x200
596#define GPIOXC_DOE_OFFS 0x204
597#define GPIOXC_FS0_OFFS 0x208
598#define GPIOXC_RPU_OFFS 0x230
599#define GPIOXC_RPD_OFFS 0x234
600#define GPIOXC_DV0_OFFS 0x238
601#define GPIOXC_DV1_OFFS 0x23c
602
603#define GPIOXC_FS0 __REG(GPIOXC_BASE + GPIOXC_FS0_OFFS)
604
605#define GPIOXC_FS0_CS0 (1 << 26)
606#define GPIOXC_FS0_CS1 (1 << 27)
607
608#define GPIOXD_BASE (APB1_PERI_BASE_VIRT + 0x5000)
609
610#define GPIOXD_DAT_OFFS 0x240
611#define GPIOXD_FS0_OFFS 0x248
612#define GPIOXD_RPU_OFFS 0x270
613#define GPIOXD_RPD_OFFS 0x274
614#define GPIOXD_DV0_OFFS 0x278
615#define GPIOXD_DV1_OFFS 0x27c
616
617#define GPIOPK_BASE (APB1_PERI_BASE_VIRT + 0x1c000)
618
619#define GPIOPK_RST_OFFS 0x008
620#define GPIOPK_DAT_OFFS 0x100
621#define GPIOPK_DOE_OFFS 0x104
622#define GPIOPK_FS0_OFFS 0x108
623#define GPIOPK_FS1_OFFS 0x10c
624#define GPIOPK_FS2_OFFS 0x110
625#define GPIOPK_IRQST_OFFS 0x210
626#define GPIOPK_IRQEN_OFFS 0x214
627#define GPIOPK_IRQPOL_OFFS 0x218
628#define GPIOPK_IRQTM0_OFFS 0x21c
629#define GPIOPK_IRQTM1_OFFS 0x220
630#define GPIOPK_CTL_OFFS 0x22c
631
632#define PMGPIO_BASE (APB1_PERI_BASE_VIRT + 0x10000)
633#define BACKUP_RAM_BASE PMGPIO_BASE
634
635#define PMGPIO_DAT_OFFS 0x800
636#define PMGPIO_DOE_OFFS 0x804
637#define PMGPIO_FS0_OFFS 0x808
638#define PMGPIO_RPU_OFFS 0x810
639#define PMGPIO_RPD_OFFS 0x814
640#define PMGPIO_DV0_OFFS 0x818
641#define PMGPIO_DV1_OFFS 0x81c
642#define PMGPIO_EE0_OFFS 0x820
643#define PMGPIO_EE1_OFFS 0x824
644#define PMGPIO_CTL_OFFS 0x828
645#define PMGPIO_DI_OFFS 0x82c
646#define PMGPIO_STR_OFFS 0x830
647#define PMGPIO_STF_OFFS 0x834
648#define PMGPIO_POL_OFFS 0x838
649#define PMGPIO_APB_OFFS 0x800
650
651/* Clock controller registers */
652#define CKC_BASE ((void __iomem *)(APB1_PERI_BASE_VIRT + 0x6000))
653
654#define CLKCTRL_OFFS 0x00
655#define PLL0CFG_OFFS 0x04
656#define PLL1CFG_OFFS 0x08
657#define CLKDIVC0_OFFS 0x0c
658
659#define BCLKCTR0_OFFS 0x14
660#define SWRESET0_OFFS 0x18
661
662#define BCLKCTR1_OFFS 0x60
663#define SWRESET1_OFFS 0x64
664#define PWDCTL_OFFS 0x68
665#define PLL2CFG_OFFS 0x6c
666#define CLKDIVC1_OFFS 0x70
667
668#define ACLKREF_OFFS 0x80
669#define ACLKI2C_OFFS 0x84
670#define ACLKSPI0_OFFS 0x88
671#define ACLKSPI1_OFFS 0x8c
672#define ACLKUART0_OFFS 0x90
673#define ACLKUART1_OFFS 0x94
674#define ACLKUART2_OFFS 0x98
675#define ACLKUART3_OFFS 0x9c
676#define ACLKUART4_OFFS 0xa0
677#define ACLKTCT_OFFS 0xa4
678#define ACLKTCX_OFFS 0xa8
679#define ACLKTCZ_OFFS 0xac
680#define ACLKADC_OFFS 0xb0
681#define ACLKDAI0_OFFS 0xb4
682#define ACLKDAI1_OFFS 0xb8
683#define ACLKLCD_OFFS 0xbc
684#define ACLKSPDIF_OFFS 0xc0
685#define ACLKUSBH_OFFS 0xc4
686#define ACLKSDH0_OFFS 0xc8
687#define ACLKSDH1_OFFS 0xcc
688#define ACLKC3DEC_OFFS 0xd0
689#define ACLKEXT_OFFS 0xd4
690#define ACLKCAN0_OFFS 0xd8
691#define ACLKCAN1_OFFS 0xdc
692#define ACLKGSB0_OFFS 0xe0
693#define ACLKGSB1_OFFS 0xe4
694#define ACLKGSB2_OFFS 0xe8
695#define ACLKGSB3_OFFS 0xec
696
697#define PLLxCFG_PD (1 << 31)
698
699/* CLKCTRL bits */
700#define CLKCTRL_XE (1 << 31)
701
702/* CLKDIVCx bits */
703#define CLKDIVC0_XTE (1 << 7)
704#define CLKDIVC0_XE (1 << 15)
705#define CLKDIVC0_P1E (1 << 23)
706#define CLKDIVC0_P0E (1 << 31)
707
708#define CLKDIVC1_P2E (1 << 7)
709
710/* BCLKCTR0 clock bits */
711#define BCLKCTR0_USBD (1 << 4)
712#define BCLKCTR0_ECC (1 << 9)
713#define BCLKCTR0_USBH0 (1 << 11)
714#define BCLKCTR0_NFC (1 << 16)
715
716/* BCLKCTR1 clock bits */
717#define BCLKCTR1_USBH1 (1 << 20)
718
719/* SWRESET0 bits */
720#define SWRESET0_USBD (1 << 4)
721#define SWRESET0_USBH0 (1 << 11)
722
723/* SWRESET1 bits */
724#define SWRESET1_USBH1 (1 << 20)
725
726/* System clock sources.
727 * Note: These are the clock sources that serve as parents for
728 * all other clocks. They have no parents themselves.
729 *
730 * These values are used for struct clk->root_id. All clocks
731 * that are not system clock sources have this value set to
732 * CLK_SRC_NOROOT.
733 * The values for system clocks start with CLK_SRC_PLL0 == 0
734 * because this gives us exactly the values needed for the lower
735 * 4 bits of ACLK_* registers. Therefore, CLK_SRC_NOROOT is
736 * defined as -1 to not disturb the order.
737 */
738enum root_clks {
739 CLK_SRC_NOROOT = -1,
740 CLK_SRC_PLL0 = 0,
741 CLK_SRC_PLL1,
742 CLK_SRC_PLL0DIV,
743 CLK_SRC_PLL1DIV,
744 CLK_SRC_XI,
745 CLK_SRC_XIDIV,
746 CLK_SRC_XTI,
747 CLK_SRC_XTIDIV,
748 CLK_SRC_PLL2,
749 CLK_SRC_PLL2DIV,
750 CLK_SRC_PK0,
751 CLK_SRC_PK1,
752 CLK_SRC_PK2,
753 CLK_SRC_PK3,
754 CLK_SRC_PK4,
755 CLK_SRC_48MHZ
756};
757
758#define CLK_SRC_MASK 0xf
759
760/* Bits in ACLK* registers */
761#define ACLK_EN (1 << 28)
762#define ACLK_SEL_SHIFT 24
763#define ACLK_SEL_MASK 0x0f000000
764#define ACLK_DIV_MASK 0x00000fff
765
766/* System configuration registers */
767
768#define SCFG_BASE (APB1_PERI_BASE_VIRT + 0x13000)
769
770#define BMI_OFFS 0x00
771#define AHBCON0_OFFS 0x04
772#define APBPWE_OFFS 0x08
773#define DTCMWAIT_OFFS 0x0c
774#define ECCSEL_OFFS 0x10
775#define AHBCON1_OFFS 0x14
776#define SDHCFG_OFFS 0x18
777#define REMAP_OFFS 0x20
778#define LCDSIAE_OFFS 0x24
779#define XMCCFG_OFFS 0xe0
780#define IMCCFG_OFFS 0xe4
781
782/* Values for ECCSEL */
783#define ECCSEL_EXTMEM 0x0
784#define ECCSEL_DTCM 0x1
785#define ECCSEL_INT_SRAM 0x2
786#define ECCSEL_AHB 0x3
787
788/* Bits in XMCCFG */
789#define XMCCFG_NFCE (1 << 1)
790#define XMCCFG_FDXD (1 << 2)
791
792/* External memory controller registers */
793
794#define EMC_BASE EXT_MEM_CTRL_BASE
795
796#define SDCFG_OFFS 0x00
797#define SDFSM_OFFS 0x04
798#define MCFG_OFFS 0x08
799
800#define CSCFG0_OFFS 0x10
801#define CSCFG1_OFFS 0x14
802#define CSCFG2_OFFS 0x18
803#define CSCFG3_OFFS 0x1c
804
805#define MCFG_SDEN (1 << 4)
806
807#endif /* TCC8K_REGS_H */
diff --git a/arch/arm/plat-tcc/include/mach/timex.h b/arch/arm/plat-tcc/include/mach/timex.h
new file mode 100644
index 000000000000..057acbe651d9
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/timex.h
@@ -0,0 +1,5 @@
1/*
2 * A definition needed by arch core code.
3 *
4 */
5#define CLOCK_TICK_RATE (HZ * 100000UL)
diff --git a/arch/arm/plat-tcc/include/mach/uncompress.h b/arch/arm/plat-tcc/include/mach/uncompress.h
new file mode 100644
index 000000000000..7a3e33a27a30
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/uncompress.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
3 *
4 * This file is licensed under the terms of the GPL version 2.
5 */
6
7#include <linux/serial_reg.h>
8#include <linux/types.h>
9
10#include <mach/tcc8k-regs.h>
11
12unsigned int system_rev;
13
14#define ID_MASK 0x7fff
15
16static void putc(int c)
17{
18 u32 *uart_lsr = (u32 *)(UART_BASE_PHYS + (UART_LSR << 2));
19 u32 *uart_tx = (u32 *)(UART_BASE_PHYS + (UART_TX << 2));
20
21 while (!(*uart_lsr & UART_LSR_THRE))
22 barrier();
23 *uart_tx = c;
24}
25
26static inline void flush(void)
27{
28}
29
30/*
31 * nothing to do
32 */
33#define arch_decomp_setup()
34#define arch_decomp_wdog()
diff --git a/arch/arm/plat-tcc/include/mach/vmalloc.h b/arch/arm/plat-tcc/include/mach/vmalloc.h
new file mode 100644
index 000000000000..99414d9c2b94
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/vmalloc.h
@@ -0,0 +1,10 @@
1/*
2 * Author: <linux@telechips.com>
3 * Created: June 10, 2008
4 *
5 * Copyright (C) 2000 Russell King.
6 * Copyright (C) 2008-2009 Telechips
7 *
8 * Licensed under the terms of the GPL v2.
9 */
10#define VMALLOC_END 0xf0000000UL
diff --git a/arch/arm/plat-tcc/system.c b/arch/arm/plat-tcc/system.c
new file mode 100644
index 000000000000..cc208fae3e7a
--- /dev/null
+++ b/arch/arm/plat-tcc/system.c
@@ -0,0 +1,25 @@
1/*
2 * System functions for Telechips TCCxxxx SoCs
3 *
4 * Copyright (C) Hans J. Koch <hjk@linutronix.de>
5 *
6 * Licensed under the terms of the GPL v2.
7 *
8 */
9
10#include <linux/io.h>
11
12#include <mach/tcc8k-regs.h>
13
14/* System reboot */
15void plat_tcc_reboot(void)
16{
17 /* Make sure clocks are on */
18 __raw_writel(0xffffffff, CKC_BASE + BCLKCTR0_OFFS);
19
20 /* Enable watchdog reset */
21 __raw_writel(0x49, TIMER_BASE + TWDCFG_OFFS);
22 /* Wait for reset */
23 while(1)
24 ;
25}