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authorBen Dooks <ben-linux@fluff.org>2010-05-20 05:51:31 -0400
committerBen Dooks <ben-linux@fluff.org>2010-05-20 05:51:31 -0400
commitd48562abe29ceee66a6aad7b565b021ddd7f598a (patch)
tree5f70539f7c3bc90ec9ec0f53c5105e45f8f508f9 /arch/arm
parent0df04f820b7ca5204329d1c235e509648fa8008d (diff)
parenta73e3e6f8f5847c00edb9dd7aab19d005a3d6e5c (diff)
ARM: Merge for-2635-4/s5pc1xx-removal
Merge branch 'for-2635-4/s5pc1xx-removal' into for-2635-4/partial1
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig9
-rw-r--r--arch/arm/Makefile3
-rw-r--r--arch/arm/mach-s5pc100/Kconfig25
-rw-r--r--arch/arm/mach-s5pc100/Makefile6
-rw-r--r--arch/arm/mach-s5pc100/cpu.c56
-rw-r--r--arch/arm/mach-s5pc100/gpiolib.c36
-rw-r--r--arch/arm/mach-s5pc100/include/mach/debug-macro.S6
-rw-r--r--arch/arm/mach-s5pc100/include/mach/entry-macro.S8
-rw-r--r--arch/arm/mach-s5pc100/include/mach/gpio.h7
-rw-r--r--arch/arm/mach-s5pc100/include/mach/irqs.h99
-rw-r--r--arch/arm/mach-s5pc100/include/mach/map.h156
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-clock.h6
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-gpio.h37
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-irq.h7
-rw-r--r--arch/arm/mach-s5pc100/include/mach/system.h9
-rw-r--r--arch/arm/mach-s5pc100/include/mach/tick.h4
-rw-r--r--arch/arm/mach-s5pc100/init.c (renamed from arch/arm/plat-s5pc1xx/s5pc100-init.c)7
-rw-r--r--arch/arm/mach-s5pc100/irq-gpio.c (renamed from arch/arm/plat-s5pc1xx/irq-gpio.c)78
-rw-r--r--arch/arm/mach-s5pc100/mach-smdkc100.c54
-rw-r--r--arch/arm/mach-s5pc100/setup-sdhci-gpio.c (renamed from arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c)4
-rw-r--r--arch/arm/plat-s5p/Kconfig2
-rw-r--r--arch/arm/plat-s5p/cpu.c10
-rw-r--r--arch/arm/plat-s5p/include/plat/s5pc100.h33
-rw-r--r--arch/arm/plat-s5pc1xx/Kconfig47
-rw-r--r--arch/arm/plat-s5pc1xx/Makefile26
-rw-r--r--arch/arm/plat-s5pc1xx/clock.c709
-rw-r--r--arch/arm/plat-s5pc1xx/cpu.c122
-rw-r--r--arch/arm/plat-s5pc1xx/dev-uart.c145
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h44
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/irqs.h198
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/pll.h38
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/regs-clock.h252
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/regs-power.h84
-rw-r--r--arch/arm/plat-s5pc1xx/include/plat/s5pc100.h64
-rw-r--r--arch/arm/plat-s5pc1xx/irq-eint.c281
-rw-r--r--arch/arm/plat-s5pc1xx/irq.c75
-rw-r--r--arch/arm/plat-s5pc1xx/s5pc100-clock.c876
-rw-r--r--arch/arm/plat-samsung/Kconfig2
38 files changed, 376 insertions, 3249 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3f8718fc4050..1cb098f6950b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -699,14 +699,14 @@ config ARCH_S5P6442
699 help 699 help
700 Samsung S5P6442 CPU based systems 700 Samsung S5P6442 CPU based systems
701 701
702config ARCH_S5PC1XX 702config ARCH_S5PC100
703 bool "Samsung S5PC1XX" 703 bool "Samsung S5PC100"
704 select GENERIC_GPIO 704 select GENERIC_GPIO
705 select HAVE_CLK 705 select HAVE_CLK
706 select CPU_V7 706 select CPU_V7
707 select ARM_L1_CACHE_SHIFT_6 707 select ARM_L1_CACHE_SHIFT_6
708 help 708 help
709 Samsung S5PC1XX series based systems 709 Samsung S5PC100 series based systems
710 710
711config ARCH_S5PV210 711config ARCH_S5PV210
712 bool "Samsung S5PV210/S5PC110" 712 bool "Samsung S5PV210/S5PC110"
@@ -890,7 +890,6 @@ source "arch/arm/mach-sa1100/Kconfig"
890source "arch/arm/plat-samsung/Kconfig" 890source "arch/arm/plat-samsung/Kconfig"
891source "arch/arm/plat-s3c24xx/Kconfig" 891source "arch/arm/plat-s3c24xx/Kconfig"
892source "arch/arm/plat-s5p/Kconfig" 892source "arch/arm/plat-s5p/Kconfig"
893source "arch/arm/plat-s5pc1xx/Kconfig"
894 893
895if ARCH_S3C2410 894if ARCH_S3C2410
896source "arch/arm/mach-s3c2400/Kconfig" 895source "arch/arm/mach-s3c2400/Kconfig"
@@ -909,9 +908,7 @@ source "arch/arm/mach-s5p6440/Kconfig"
909 908
910source "arch/arm/mach-s5p6442/Kconfig" 909source "arch/arm/mach-s5p6442/Kconfig"
911 910
912if ARCH_S5PC1XX
913source "arch/arm/mach-s5pc100/Kconfig" 911source "arch/arm/mach-s5pc100/Kconfig"
914endif
915 912
916source "arch/arm/mach-s5pv210/Kconfig" 913source "arch/arm/mach-s5pv210/Kconfig"
917 914
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 9505a70bfc0a..f7cb6d495484 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -167,7 +167,7 @@ machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
167machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx 167machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx
168machine-$(CONFIG_ARCH_S5P6440) := s5p6440 168machine-$(CONFIG_ARCH_S5P6440) := s5p6440
169machine-$(CONFIG_ARCH_S5P6442) := s5p6442 169machine-$(CONFIG_ARCH_S5P6442) := s5p6442
170machine-$(CONFIG_ARCH_S5PC1XX) := s5pc100 170machine-$(CONFIG_ARCH_S5PC100) := s5pc100
171machine-$(CONFIG_ARCH_S5PV210) := s5pv210 171machine-$(CONFIG_ARCH_S5PV210) := s5pv210
172machine-$(CONFIG_ARCH_SA1100) := sa1100 172machine-$(CONFIG_ARCH_SA1100) := sa1100
173machine-$(CONFIG_ARCH_SHARK) := shark 173machine-$(CONFIG_ARCH_SHARK) := shark
@@ -192,7 +192,6 @@ plat-$(CONFIG_PLAT_NOMADIK) := nomadik
192plat-$(CONFIG_PLAT_ORION) := orion 192plat-$(CONFIG_PLAT_ORION) := orion
193plat-$(CONFIG_PLAT_PXA) := pxa 193plat-$(CONFIG_PLAT_PXA) := pxa
194plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx samsung 194plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx samsung
195plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx samsung
196plat-$(CONFIG_PLAT_S5P) := s5p samsung 195plat-$(CONFIG_PLAT_S5P) := s5p samsung
197 196
198ifeq ($(CONFIG_ARCH_EBSA110),y) 197ifeq ($(CONFIG_ARCH_EBSA110),y)
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 8593337784e1..2eb949771dbc 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -5,10 +5,12 @@
5 5
6# Configuration options for the S5PC100 CPU 6# Configuration options for the S5PC100 CPU
7 7
8if ARCH_S5PC100
9
8config CPU_S5PC100 10config CPU_S5PC100
9 bool 11 bool
10 select CPU_S5PC100_INIT 12 select PLAT_S5P
11 select CPU_S5PC100_CLOCK 13 select S5P_EXT_INT
12 help 14 help
13 Enable S5PC100 CPU support 15 Enable S5PC100 CPU support
14 16
@@ -17,17 +19,22 @@ config S5PC100_SETUP_FB_24BPP
17 help 19 help
18 Common setup code for S5PC1XX with an 24bpp RGB display helper. 20 Common setup code for S5PC1XX with an 24bpp RGB display helper.
19 21
20config S5PC100_SETUP_SDHCI
21 bool
22 select S5PC1XX_SETUP_SDHCI_GPIO
23 help
24 Internal helper functions for S5PC100 based SDHCI systems
25
26config S5PC100_SETUP_I2C1 22config S5PC100_SETUP_I2C1
27 bool 23 bool
28 help 24 help
29 Common setup code for i2c bus 1. 25 Common setup code for i2c bus 1.
30 26
27config S5PC100_SETUP_SDHCI
28 bool
29 select S5PC100_SETUP_SDHCI_GPIO
30 help
31 Internal helper functions for S5PC100 based SDHCI systems
32
33config S5PC100_SETUP_SDHCI_GPIO
34 bool
35 help
36 Common setup code for SDHCI gpio.
37
31config MACH_SMDKC100 38config MACH_SMDKC100
32 bool "SMDKC100" 39 bool "SMDKC100"
33 select CPU_S5PC100 40 select CPU_S5PC100
@@ -41,3 +48,5 @@ config MACH_SMDKC100
41 select S5PC100_SETUP_SDHCI 48 select S5PC100_SETUP_SDHCI
42 help 49 help
43 Machine support for the Samsung SMDKC100 50 Machine support for the Samsung SMDKC100
51
52endif
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index 373bc546eae8..6e3f57c39c97 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -11,14 +11,16 @@ obj- :=
11 11
12# Core support for S5PC100 system 12# Core support for S5PC100 system
13 13
14obj-$(CONFIG_CPU_S5PC100) += cpu.o gpiolib.o 14obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o gpiolib.o irq-gpio.o
15obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o 15obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o
16 16
17# Helper and device support 17# Helper and device support
18 18
19obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o 19obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o
20obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o 20obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
21obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o 21obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o
22obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
22 23
23# machine support 24# machine support
25
24obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o 26obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index d79e7574a852..d424a9fda034 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -22,47 +22,53 @@
22#include <linux/serial_core.h> 22#include <linux/serial_core.h>
23#include <linux/platform_device.h> 23#include <linux/platform_device.h>
24 24
25#include <asm/proc-fns.h>
26
27#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
28#include <asm/mach/map.h> 26#include <asm/mach/map.h>
29#include <asm/mach/irq.h> 27#include <asm/mach/irq.h>
30 28
29#include <asm/proc-fns.h>
30
31#include <mach/hardware.h> 31#include <mach/hardware.h>
32#include <mach/map.h> 32#include <mach/map.h>
33#include <asm/irq.h> 33#include <asm/irq.h>
34 34
35#include <plat/cpu-freq.h>
36#include <plat/regs-serial.h> 35#include <plat/regs-serial.h>
37#include <plat/regs-power.h> 36#include <mach/regs-clock.h>
38 37
39#include <plat/cpu.h> 38#include <plat/cpu.h>
40#include <plat/devs.h> 39#include <plat/devs.h>
41#include <plat/clock.h> 40#include <plat/clock.h>
42#include <plat/sdhci.h>
43#include <plat/iic-core.h> 41#include <plat/iic-core.h>
42#include <plat/sdhci.h>
44#include <plat/s5pc100.h> 43#include <plat/s5pc100.h>
45 44
46/* Initial IO mappings */ 45/* Initial IO mappings */
47 46
48static struct map_desc s5pc100_iodesc[] __initdata = { 47static struct map_desc s5pc100_iodesc[] __initdata = {
48 {
49 .virtual = (unsigned long)S5P_VA_SYSTIMER,
50 .pfn = __phys_to_pfn(S5PC100_PA_SYSTIMER),
51 .length = SZ_16K,
52 .type = MT_DEVICE,
53 }, {
54 .virtual = (unsigned long)VA_VIC2,
55 .pfn = __phys_to_pfn(S5PC100_PA_VIC2),
56 .length = SZ_16K,
57 .type = MT_DEVICE,
58 }, {
59 .virtual = (unsigned long)S5PC100_VA_OTHERS,
60 .pfn = __phys_to_pfn(S5PC100_PA_OTHERS),
61 .length = SZ_4K,
62 .type = MT_DEVICE,
63 }
49}; 64};
50 65
51static void s5pc100_idle(void) 66static void s5pc100_idle(void)
52{ 67{
53 unsigned long tmp; 68 if (!need_resched())
54 69 cpu_do_idle();
55 tmp = __raw_readl(S5PC100_PWR_CFG);
56 tmp &= ~S5PC100_PWRCFG_CFG_DEEP_IDLE;
57 tmp &= ~S5PC100_PWRCFG_CFG_WFI_MASK;
58 tmp |= S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE;
59 __raw_writel(tmp, S5PC100_PWR_CFG);
60 70
61 tmp = __raw_readl(S5PC100_OTHERS); 71 local_irq_enable();
62 tmp |= S5PC100_PMU_INT_DISABLE;
63 __raw_writel(tmp, S5PC100_OTHERS);
64
65 cpu_do_idle();
66} 72}
67 73
68/* s5pc100_map_io 74/* s5pc100_map_io
@@ -86,22 +92,23 @@ void __init s5pc100_map_io(void)
86 92
87void __init s5pc100_init_clocks(int xtal) 93void __init s5pc100_init_clocks(int xtal)
88{ 94{
89 printk(KERN_DEBUG "%s: initialising clocks\n", __func__); 95 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
96
90 s3c24xx_register_baseclocks(xtal); 97 s3c24xx_register_baseclocks(xtal);
91 s5pc1xx_register_clocks(); 98 s5p_register_clocks(xtal);
92 s5pc100_register_clocks(); 99 s5pc100_register_clocks();
93 s5pc100_setup_clocks(); 100 s5pc100_setup_clocks();
94} 101}
95 102
96void __init s5pc100_init_irq(void) 103void __init s5pc100_init_irq(void)
97{ 104{
98 u32 vic_valid[] = {~0, ~0, ~0}; 105 u32 vic[] = {~0, ~0, ~0};
99 106
100 /* VIC0, VIC1, and VIC2 are fully populated. */ 107 /* VIC0, VIC1, and VIC2 are fully populated. */
101 s5pc1xx_init_irq(vic_valid, ARRAY_SIZE(vic_valid)); 108 s5p_init_irq(vic, ARRAY_SIZE(vic));
102} 109}
103 110
104struct sysdev_class s5pc100_sysclass = { 111static struct sysdev_class s5pc100_sysclass = {
105 .name = "s5pc100-core", 112 .name = "s5pc100-core",
106}; 113};
107 114
@@ -118,9 +125,10 @@ core_initcall(s5pc100_core_init);
118 125
119int __init s5pc100_init(void) 126int __init s5pc100_init(void)
120{ 127{
121 printk(KERN_DEBUG "S5PC100: Initialising architecture\n"); 128 printk(KERN_INFO "S5PC100: Initializing architecture\n");
122 129
123 s5pc1xx_idle = s5pc100_idle; 130 /* set idle function */
131 pm_idle = s5pc100_idle;
124 132
125 return sysdev_register(&s5pc100_sysdev); 133 return sysdev_register(&s5pc100_sysdev);
126} 134}
diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c
index c8e8336a3a12..0fab7f2cd8bf 100644
--- a/arch/arm/mach-s5pc100/gpiolib.c
+++ b/arch/arm/mach-s5pc100/gpiolib.c
@@ -1,10 +1,10 @@
1/* 1/*
2 * arch/arm/plat-s5pc1xx/gpiolib.c 2 * arch/arm/plat-s5pc100/gpiolib.c
3 * 3 *
4 * Copyright 2009 Samsung Electronics Co 4 * Copyright 2009 Samsung Electronics Co
5 * Kyungmin Park <kyungmin.park@samsung.com> 5 * Kyungmin Park <kyungmin.park@samsung.com>
6 * 6 *
7 * S5PC1XX - GPIOlib support 7 * S5PC100 - GPIOlib support
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
@@ -61,13 +61,12 @@
61 * L3 8 4Bit None 61 * L3 8 4Bit None
62 */ 62 */
63 63
64#if 0 64static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
65static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
66{ 65{
67 return S3C_IRQ_GPIO(chip->base + offset); 66 return S3C_IRQ_GPIO(chip->base + offset);
68} 67}
69 68
70static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset) 69static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
71{ 70{
72 int base; 71 int base;
73 72
@@ -85,7 +84,7 @@ static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
85 return IRQ_EINT(24 + offset); 84 return IRQ_EINT(24 + offset);
86 return -EINVAL; 85 return -EINVAL;
87} 86}
88#endif 87
89static struct s3c_gpio_cfg gpio_cfg = { 88static struct s3c_gpio_cfg gpio_cfg = {
90 .set_config = s3c_gpio_setcfg_s3c64xx_4bit, 89 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
91 .set_pull = s3c_gpio_setpull_updown, 90 .set_pull = s3c_gpio_setpull_updown,
@@ -382,31 +381,30 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
382}; 381};
383 382
384/* FIXME move from irq-gpio.c */ 383/* FIXME move from irq-gpio.c */
385extern struct irq_chip s5pc1xx_gpioint; 384extern struct irq_chip s5pc100_gpioint;
386extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc); 385extern void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
387 386
388static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip) 387static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
389{ 388{
390#if 0
391 /* Interrupt */ 389 /* Interrupt */
392 if (chip->config == &gpio_cfg) { 390 if (chip->config == &gpio_cfg) {
393 int i, irq; 391 int i, irq;
394 392
395 chip->chip.to_irq = s5pc1xx_gpiolib_to_irq; 393 chip->chip.to_irq = s5pc100_gpiolib_to_irq;
396 394
397 for (i = 0; i < chip->chip.ngpio; i++) { 395 for (i = 0; i < chip->chip.ngpio; i++) {
398 irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i; 396 irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
399 set_irq_chip(irq, &s5pc1xx_gpioint); 397 set_irq_chip(irq, &s5pc100_gpioint);
400 set_irq_data(irq, &chip->chip); 398 set_irq_data(irq, &chip->chip);
401 set_irq_handler(irq, handle_level_irq); 399 set_irq_handler(irq, handle_level_irq);
402 set_irq_flags(irq, IRQF_VALID); 400 set_irq_flags(irq, IRQF_VALID);
403 } 401 }
404 } else if (chip->config == &gpio_cfg_eint) 402 } else if (chip->config == &gpio_cfg_eint) {
405 chip->chip.to_irq = s5pc1xx_gpiolib_to_eint; 403 chip->chip.to_irq = s5pc100_gpiolib_to_eint;
406#endif 404 }
407} 405}
408 406
409static __init int s5pc1xx_gpiolib_init(void) 407static __init int s5pc100_gpiolib_init(void)
410{ 408{
411 struct s3c_gpio_chip *chip; 409 struct s3c_gpio_chip *chip;
412 int nr_chips; 410 int nr_chips;
@@ -419,10 +417,10 @@ static __init int s5pc1xx_gpiolib_init(void)
419 417
420 samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, 418 samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips,
421 ARRAY_SIZE(s5pc100_gpio_chips)); 419 ARRAY_SIZE(s5pc100_gpio_chips));
422#if 0 420
423 /* Interrupt */ 421 /* Interrupt */
424 set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler); 422 set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler);
425#endif 423
426 return 0; 424 return 0;
427} 425}
428core_initcall(s5pc1xx_gpiolib_init); 426core_initcall(s5pc100_gpiolib_init);
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
index e181f5789482..70e02e91ee3c 100644
--- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
@@ -22,12 +22,14 @@
22 * aligned and add in the offset when we load the value here. 22 * aligned and add in the offset when we load the value here.
23 */ 23 */
24 24
25 .macro addruart, rx, tmp 25 .macro addruart, rx, rtmp
26 mrc p15, 0, \rx, c1, c0 26 mrc p15, 0, \rx, c1, c0
27 tst \rx, #1 27 tst \rx, #1
28 ldreq \rx, = S3C_PA_UART 28 ldreq \rx, = S3C_PA_UART
29 ldrne \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff) 29 ldrne \rx, = S3C_VA_UART
30#if CONFIG_DEBUG_S3C_UART != 0
30 add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) 31 add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
32#endif
31 .endm 33 .endm
32 34
33/* include the reset of the code which will do the work, we're only 35/* include the reset of the code which will do the work, we're only
diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
index 67131939e626..ba76af052c81 100644
--- a/arch/arm/mach-s5pc100/include/mach/entry-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
@@ -20,7 +20,7 @@
20 .endm 20 .endm
21 21
22 .macro get_irqnr_preamble, base, tmp 22 .macro get_irqnr_preamble, base, tmp
23 ldr \base, =S3C_VA_VIC0 23 ldr \base, =VA_VIC0
24 .endm 24 .endm
25 25
26 .macro arch_ret_to_user, tmp1, tmp2 26 .macro arch_ret_to_user, tmp1, tmp2
@@ -29,18 +29,18 @@
29 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 29 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
30 30
31 @ check the vic0 31 @ check the vic0
32 mov \irqnr, # S3C_IRQ_OFFSET + 31 32 mov \irqnr, # S5P_IRQ_OFFSET + 31
33 ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] 33 ldr \irqstat, [ \base, # VIC_IRQ_STATUS ]
34 teq \irqstat, #0 34 teq \irqstat, #0
35 35
36 @ otherwise try vic1 36 @ otherwise try vic1
37 addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0) 37 addeq \tmp, \base, #(VA_VIC1 - VA_VIC0)
38 addeq \irqnr, \irqnr, #32 38 addeq \irqnr, \irqnr, #32
39 ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] 39 ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
40 teqeq \irqstat, #0 40 teqeq \irqstat, #0
41 41
42 @ otherwise try vic2 42 @ otherwise try vic2
43 addeq \tmp, \base, #(S3C_VA_VIC2 - S3C_VA_VIC0) 43 addeq \tmp, \base, #(VA_VIC2 - VA_VIC0)
44 addeq \irqnr, \irqnr, #32 44 addeq \irqnr, \irqnr, #32
45 ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] 45 ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
46 teqeq \irqstat, #0 46 teqeq \irqstat, #0
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
index 29a8a12d9b4f..71ae1f52df1d 100644
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -146,6 +146,13 @@ enum s5p_gpio_number {
146/* define the number of gpios we need to the one after the MP04() range */ 146/* define the number of gpios we need to the one after the MP04() range */
147#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1) 147#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1)
148 148
149#define EINT_MODE S3C_GPIO_SFN(0x2)
150
151#define EINT_GPIO_0(x) S5PC100_GPH0(x)
152#define EINT_GPIO_1(x) S5PC100_GPH1(x)
153#define EINT_GPIO_2(x) S5PC100_GPH2(x)
154#define EINT_GPIO_3(x) S5PC100_GPH3(x)
155
149#include <asm-generic/gpio.h> 156#include <asm-generic/gpio.h>
150 157
151#endif /* __ASM_ARCH_GPIO_H */ 158#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index b53fa48a52c6..28aa551dc3a8 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -11,9 +11,104 @@
11 11
12#include <plat/irqs.h> 12#include <plat/irqs.h>
13 13
14/* LCD */ 14/* VIC0: system, DMA, timer */
15#define IRQ_EINT16_31 S5P_IRQ_VIC0(16)
16#define IRQ_BATF S5P_IRQ_VIC0(17)
17#define IRQ_MDMA S5P_IRQ_VIC0(18)
18#define IRQ_PDMA0 S5P_IRQ_VIC0(19)
19#define IRQ_PDMA1 S5P_IRQ_VIC0(20)
20#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21)
21#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22)
22#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23)
23#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24)
24#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25)
25#define IRQ_SYSTIMER S5P_IRQ_VIC0(26)
26#define IRQ_WDT S5P_IRQ_VIC0(27)
27#define IRQ_RTC_ALARM S5P_IRQ_VIC0(28)
28#define IRQ_RTC_TIC S5P_IRQ_VIC0(29)
29#define IRQ_GPIOINT S5P_IRQ_VIC0(30)
30
31/* VIC1: ARM, power, memory, connectivity */
32#define IRQ_CORTEX0 S5P_IRQ_VIC1(0)
33#define IRQ_CORTEX1 S5P_IRQ_VIC1(1)
34#define IRQ_CORTEX2 S5P_IRQ_VIC1(2)
35#define IRQ_CORTEX3 S5P_IRQ_VIC1(3)
36#define IRQ_CORTEX4 S5P_IRQ_VIC1(4)
37#define IRQ_IEMAPC S5P_IRQ_VIC1(5)
38#define IRQ_IEMIEC S5P_IRQ_VIC1(6)
39#define IRQ_ONENAND S5P_IRQ_VIC1(7)
40#define IRQ_NFC S5P_IRQ_VIC1(8)
41#define IRQ_CFC S5P_IRQ_VIC1(9)
42#define IRQ_UART0 S5P_IRQ_VIC1(10)
43#define IRQ_UART1 S5P_IRQ_VIC1(11)
44#define IRQ_UART2 S5P_IRQ_VIC1(12)
45#define IRQ_UART3 S5P_IRQ_VIC1(13)
46#define IRQ_IIC S5P_IRQ_VIC1(14)
47#define IRQ_SPI0 S5P_IRQ_VIC1(15)
48#define IRQ_SPI1 S5P_IRQ_VIC1(16)
49#define IRQ_SPI2 S5P_IRQ_VIC1(17)
50#define IRQ_IRDA S5P_IRQ_VIC1(18)
51#define IRQ_CAN0 S5P_IRQ_VIC1(19)
52#define IRQ_CAN1 S5P_IRQ_VIC1(20)
53#define IRQ_HSIRX S5P_IRQ_VIC1(21)
54#define IRQ_HSITX S5P_IRQ_VIC1(22)
55#define IRQ_UHOST S5P_IRQ_VIC1(23)
56#define IRQ_OTG S5P_IRQ_VIC1(24)
57#define IRQ_MSM S5P_IRQ_VIC1(25)
58#define IRQ_HSMMC0 S5P_IRQ_VIC1(26)
59#define IRQ_HSMMC1 S5P_IRQ_VIC1(27)
60#define IRQ_HSMMC2 S5P_IRQ_VIC1(28)
61#define IRQ_MIPICSI S5P_IRQ_VIC1(29)
62#define IRQ_MIPIDSI S5P_IRQ_VIC1(30)
63
64/* VIC2: multimedia, audio, security */
65#define IRQ_LCD0 S5P_IRQ_VIC2(0)
66#define IRQ_LCD1 S5P_IRQ_VIC2(1)
67#define IRQ_LCD2 S5P_IRQ_VIC2(2)
68#define IRQ_LCD3 S5P_IRQ_VIC2(3)
69#define IRQ_ROTATOR S5P_IRQ_VIC2(4)
70#define IRQ_FIMC0 S5P_IRQ_VIC2(5)
71#define IRQ_FIMC1 S5P_IRQ_VIC2(6)
72#define IRQ_FIMC2 S5P_IRQ_VIC2(7)
73#define IRQ_JPEG S5P_IRQ_VIC2(8)
74#define IRQ_2D S5P_IRQ_VIC2(9)
75#define IRQ_3D S5P_IRQ_VIC2(10)
76#define IRQ_MIXER S5P_IRQ_VIC2(11)
77#define IRQ_HDMI S5P_IRQ_VIC2(12)
78#define IRQ_IIC1 S5P_IRQ_VIC2(13)
79#define IRQ_MFC S5P_IRQ_VIC2(14)
80#define IRQ_TVENC S5P_IRQ_VIC2(15)
81#define IRQ_I2S0 S5P_IRQ_VIC2(16)
82#define IRQ_I2S1 S5P_IRQ_VIC2(17)
83#define IRQ_I2S2 S5P_IRQ_VIC2(18)
84#define IRQ_AC97 S5P_IRQ_VIC2(19)
85#define IRQ_PCM0 S5P_IRQ_VIC2(20)
86#define IRQ_PCM1 S5P_IRQ_VIC2(21)
87#define IRQ_SPDIF S5P_IRQ_VIC2(22)
88#define IRQ_ADC S5P_IRQ_VIC2(23)
89#define IRQ_PENDN S5P_IRQ_VIC2(24)
90#define IRQ_TC IRQ_PENDN
91#define IRQ_KEYPAD S5P_IRQ_VIC2(25)
92#define IRQ_CG S5P_IRQ_VIC2(26)
93#define IRQ_SEC S5P_IRQ_VIC2(27)
94#define IRQ_SECRX S5P_IRQ_VIC2(28)
95#define IRQ_SECTX S5P_IRQ_VIC2(29)
96#define IRQ_SDMIRQ S5P_IRQ_VIC2(30)
97#define IRQ_SDMFIQ S5P_IRQ_VIC2(31)
98#define IRQ_VIC_END S5P_IRQ_VIC2(31)
99
100#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
101#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
102
103#define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1)
104#define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x))
105
106/* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs */
107#define NR_IRQS (S3C_IRQ_GPIO(320) + 1)
108
109/* Compatibility */
15#define IRQ_LCD_FIFO IRQ_LCD0 110#define IRQ_LCD_FIFO IRQ_LCD0
16#define IRQ_LCD_VSYNC IRQ_LCD1 111#define IRQ_LCD_VSYNC IRQ_LCD1
17#define IRQ_LCD_SYSTEM IRQ_LCD2 112#define IRQ_LCD_SYSTEM IRQ_LCD2
18 113
19#endif /* __ASM_ARCH_IRQ_H */ 114#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 4681ebe8bef6..6428f4898202 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -3,9 +3,7 @@
3 * Copyright 2009 Samsung Electronics Co. 3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com> 4 * Byungho Min <bhmin@samsung.com>
5 * 5 *
6 * Based on mach-s3c6400/include/mach/map.h 6 * S5PC100 - Memory map definitions
7 *
8 * S5PC1XX - Memory map definitions
9 * 7 *
10 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -16,135 +14,59 @@
16#define __ASM_ARCH_MAP_H __FILE__ 14#define __ASM_ARCH_MAP_H __FILE__
17 15
18#include <plat/map-base.h> 16#include <plat/map-base.h>
17#include <plat/map-s5p.h>
19 18
20/*
21 * map-base.h has already defined virtual memory address
22 * S3C_VA_IRQ S3C_ADDR(0x00000000) irq controller(s)
23 * S3C_VA_SYS S3C_ADDR(0x00100000) system control
24 * S3C_VA_MEM S3C_ADDR(0x00200000) system control (not used)
25 * S3C_VA_TIMER S3C_ADDR(0x00300000) timer block
26 * S3C_VA_WATCHDOG S3C_ADDR(0x00400000) watchdog
27 * S3C_VA_UART S3C_ADDR(0x01000000) UART
28 *
29 * S5PC100 specific virtual memory address can be defined here
30 * S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) GPIO
31 *
32 */
33
34/* Chip ID */
35#define S5PC100_PA_CHIPID (0xE0000000) 19#define S5PC100_PA_CHIPID (0xE0000000)
36#define S5PC1XX_PA_CHIPID S5PC100_PA_CHIPID 20#define S5P_PA_CHIPID S5PC100_PA_CHIPID
37#define S5PC1XX_VA_CHIPID S3C_VA_SYS 21
38 22#define S5PC100_PA_SYSCON (0xE0100000)
39/* System */ 23#define S5P_PA_SYSCON S5PC100_PA_SYSCON
40#define S5PC100_PA_CLK (0xE0100000) 24
41#define S5PC100_PA_CLK_OTHER (0xE0200000) 25#define S5PC100_PA_OTHERS (0xE0200000)
42#define S5PC100_PA_PWR (0xE0108000) 26#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
43#define S5PC1XX_PA_CLK S5PC100_PA_CLK 27
44#define S5PC1XX_PA_PWR S5PC100_PA_PWR
45#define S5PC1XX_PA_CLK_OTHER S5PC100_PA_CLK_OTHER
46#define S5PC1XX_VA_CLK (S3C_VA_SYS + 0x10000)
47#define S5PC1XX_VA_PWR (S3C_VA_SYS + 0x20000)
48#define S5PC1XX_VA_CLK_OTHER (S3C_VA_SYS + 0x30000)
49
50/* GPIO */
51#define S5PC100_PA_GPIO (0xE0300000) 28#define S5PC100_PA_GPIO (0xE0300000)
52#define S5PC1XX_PA_GPIO S5PC100_PA_GPIO 29#define S5P_PA_GPIO S5PC100_PA_GPIO
53#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000)
54
55/* Interrupt */
56#define S5PC100_PA_VIC (0xE4000000)
57#define S5PC100_VA_VIC S3C_VA_IRQ
58#define S5PC100_PA_VIC_OFFSET 0x100000
59#define S5PC100_VA_VIC_OFFSET 0x10000
60#define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
61#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
62
63/* DMA */
64#define S5PC100_PA_MDMA (0xE8100000)
65#define S5PC100_PA_PDMA0 (0xE9000000)
66#define S5PC100_PA_PDMA1 (0xE9200000)
67
68/* Timer */
69#define S5PC100_PA_TIMER (0xEA000000)
70#define S5PC1XX_PA_TIMER S5PC100_PA_TIMER
71#define S5PC1XX_VA_TIMER S3C_VA_TIMER
72 30
73/* RTC */ 31#define S5PC100_PA_VIC0 (0xE4000000)
74#define S5PC100_PA_RTC (0xEA300000) 32#define S5P_PA_VIC0 S5PC100_PA_VIC0
75 33
76/* UART */ 34#define S5PC100_PA_VIC1 (0xE4100000)
77#define S5PC100_PA_UART (0xEC000000) 35#define S5P_PA_VIC1 S5PC100_PA_VIC1
78#define S5PC1XX_PA_UART S5PC100_PA_UART
79#define S5PC1XX_VA_UART S3C_VA_UART
80 36
81/* I2C */ 37#define S5PC100_PA_VIC2 (0xE4200000)
82#define S5PC100_PA_I2C (0xEC100000) 38#define S5P_PA_VIC2 S5PC100_PA_VIC2
83#define S5PC100_PA_I2C1 (0xEC200000)
84 39
85/* USB HS OTG */ 40#define S5PC100_PA_TIMER (0xEA000000)
86#define S5PC100_PA_USB_HSOTG (0xED200000) 41#define S5P_PA_TIMER S5PC100_PA_TIMER
87#define S5PC100_PA_USB_HSPHY (0xED300000)
88 42
89/* SD/MMC */ 43#define S5PC100_PA_SYSTIMER (0xEA100000)
90#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
91#define S5PC100_PA_HSMMC0 S5PC100_PA_HSMMC(0)
92#define S5PC100_PA_HSMMC1 S5PC100_PA_HSMMC(1)
93#define S5PC100_PA_HSMMC2 S5PC100_PA_HSMMC(2)
94 44
95/* LCD */ 45#define S5PC100_PA_UART (0xEC000000)
96#define S5PC100_PA_FB (0xEE000000)
97 46
98/* Multimedia */ 47#define S5P_PA_UART0 (S5PC100_PA_UART + 0x0)
99#define S5PC100_PA_G2D (0xEE800000) 48#define S5P_PA_UART1 (S5PC100_PA_UART + 0x400)
100#define S5PC100_PA_JPEG (0xEE500000) 49#define S5P_PA_UART2 (S5PC100_PA_UART + 0x800)
101#define S5PC100_PA_ROTATOR (0xEE100000) 50#define S5P_PA_UART3 (S5PC100_PA_UART + 0xC00)
102#define S5PC100_PA_G3D (0xEF000000) 51#define S5P_SZ_UART SZ_256
103 52
104/* I2S */ 53#define S5PC100_PA_IIC0 (0xEC100000)
105#define S5PC100_PA_I2S0 (0xF2000000) 54#define S5PC100_PA_IIC1 (0xEC200000)
106#define S5PC100_PA_I2S1 (0xF2100000)
107#define S5PC100_PA_I2S2 (0xF2200000)
108 55
109/* KEYPAD */ 56#define S5PC100_PA_FB (0xEE000000)
110#define S5PC100_PA_KEYPAD (0xF3100000)
111 57
112/* ADC & TouchScreen */ 58#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
113#define S5PC100_PA_TSADC (0xF3000000)
114 59
115/* ETC */
116#define S5PC100_PA_SDRAM (0x20000000) 60#define S5PC100_PA_SDRAM (0x20000000)
117#define S5PC1XX_PA_SDRAM S5PC100_PA_SDRAM 61#define S5P_PA_SDRAM S5PC100_PA_SDRAM
118 62
119/* compatibility defines. */ 63/* compatibiltiy defines. */
120#define S3C_PA_RTC S5PC100_PA_RTC
121#define S3C_PA_UART S5PC100_PA_UART 64#define S3C_PA_UART S5PC100_PA_UART
122#define S3C_PA_UART0 (S5PC100_PA_UART + 0x0) 65#define S3C_PA_IIC S5PC100_PA_IIC0
123#define S3C_PA_UART1 (S5PC100_PA_UART + 0x400) 66#define S3C_PA_IIC1 S5PC100_PA_IIC1
124#define S3C_PA_UART2 (S5PC100_PA_UART + 0x800)
125#define S3C_PA_UART3 (S5PC100_PA_UART + 0xC00)
126#define S3C_VA_UART0 (S3C_VA_UART + 0x0)
127#define S3C_VA_UART1 (S3C_VA_UART + 0x400)
128#define S3C_VA_UART2 (S3C_VA_UART + 0x800)
129#define S3C_VA_UART3 (S3C_VA_UART + 0xC00)
130#define S3C_UART_OFFSET 0x400
131#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
132#define S3C_PA_FB S5PC100_PA_FB 67#define S3C_PA_FB S5PC100_PA_FB
133#define S3C_PA_G2D S5PC100_PA_G2D 68#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0)
134#define S3C_PA_G3D S5PC100_PA_G3D 69#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1)
135#define S3C_PA_JPEG S5PC100_PA_JPEG 70#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2)
136#define S3C_PA_ROTATOR S5PC100_PA_ROTATOR 71
137#define S3C_VA_VIC0 (S3C_VA_IRQ + 0x0) 72#endif /* __ASM_ARCH_MAP_H */
138#define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000)
139#define S3C_VA_VIC2 (S3C_VA_IRQ + 0x20000)
140#define S3C_PA_IIC S5PC100_PA_I2C
141#define S3C_PA_IIC1 S5PC100_PA_I2C1
142#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
143#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
144#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC0
145#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC1
146#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC2
147#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
148#define S3C_PA_TSADC S5PC100_PA_TSADC
149
150#endif /* __ASM_ARCH_C100_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-clock.h b/arch/arm/mach-s5pc100/include/mach/regs-clock.h
index f2283bdc941e..5d27d286d504 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-clock.h
@@ -17,6 +17,8 @@
17 17
18#define S5P_CLKREG(x) (S3C_VA_SYS + (x)) 18#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
19 19
20#define S5PC100_REG_OTHERS(x) (S5PC100_VA_OTHERS + (x))
21
20#define S5P_APLL_LOCK S5P_CLKREG(0x00) 22#define S5P_APLL_LOCK S5P_CLKREG(0x00)
21#define S5P_MPLL_LOCK S5P_CLKREG(0x04) 23#define S5P_MPLL_LOCK S5P_CLKREG(0x04)
22#define S5P_EPLL_LOCK S5P_CLKREG(0x08) 24#define S5P_EPLL_LOCK S5P_CLKREG(0x08)
@@ -68,4 +70,8 @@
68#define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16) 70#define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16)
69#define S5P_CLKDIV1_PCLKD1_SHIFT (16) 71#define S5P_CLKDIV1_PCLKD1_SHIFT (16)
70 72
73#define S5PC100_SWRESET S5PC100_REG_OTHERS(0x000)
74
75#define S5PC100_SWRESET_RESETVAL 0xc100
76
71#endif /* __ASM_ARCH_REGS_CLOCK_H */ 77#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
index 68666913354c..dd6295e1251d 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
@@ -1,4 +1,4 @@
1/* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h 1/* linux/arch/arm/plat-s5pc100/include/plat/regs-gpio.h
2 * 2 *
3 * Copyright 2009 Samsung Electronics Co. 3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com> 4 * Byungho Min <bhmin@samsung.com>
@@ -12,7 +12,7 @@
12#include <mach/map.h> 12#include <mach/map.h>
13 13
14/* S5PC100 */ 14/* S5PC100 */
15#define S5PC100_GPIO_BASE S5PC1XX_VA_GPIO 15#define S5PC100_GPIO_BASE S5P_VA_GPIO
16#define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000) 16#define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000)
17#define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020) 17#define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020)
18#define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040) 18#define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040)
@@ -47,24 +47,29 @@
47#define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360) 47#define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360)
48#define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380) 48#define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380)
49#define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0) 49#define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0)
50#define S5PC100_EINT_BASE (S5PC100_GPIO_BASE + 0x0E00)
51 50
52#define S5PC100_UHOST (S5PC100_GPIO_BASE + 0x0B68) 51#define S5PC100EINT30CON (S5P_VA_GPIO + 0xE00)
53#define S5PC100_PDNEN (S5PC100_GPIO_BASE + 0x0F80) 52#define S5P_EINT_CON(x) (S5PC100EINT30CON + ((x) * 0x4))
54 53
55/* PDNEN */ 54#define S5PC100EINT30FLTCON0 (S5P_VA_GPIO + 0xE80)
56#define S5PC100_PDNEN_CFG_PDNEN (1 << 1) 55#define S5P_EINT_FLTCON(x) (S5PC100EINT30FLTCON0 + ((x) * 0x4))
57#define S5PC100_PDNEN_CFG_AUTO (0 << 1)
58#define S5PC100_PDNEN_POWERDOWN (1 << 0)
59#define S5PC100_PDNEN_NORMAL (0 << 0)
60 56
61/* Common part */ 57#define S5PC100EINT30MASK (S5P_VA_GPIO + 0xF00)
62/* External interrupt base is same at both s5pc100 and s5pc110 */ 58#define S5P_EINT_MASK(x) (S5PC100EINT30MASK + ((x) * 0x4))
63#define S5PC1XX_EINT_BASE (S5PC100_EINT_BASE)
64 59
65#define S5PC100_GPx_INPUT(__gpio) (0x0 << ((__gpio) * 4)) 60#define S5PC100EINT30PEND (S5P_VA_GPIO + 0xF40)
66#define S5PC100_GPx_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) 61#define S5P_EINT_PEND(x) (S5PC100EINT30PEND + ((x) * 0x4))
67#define S5PC100_GPx_CONMASK(__gpio) (0xf << ((__gpio) * 4)) 62
63#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
64
65#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
66
67/* values for S5P_EXTINT0 */
68#define S5P_EXTINT_LOWLEV (0x00)
69#define S5P_EXTINT_HILEV (0x01)
70#define S5P_EXTINT_FALLEDGE (0x02)
71#define S5P_EXTINT_RISEEDGE (0x03)
72#define S5P_EXTINT_BOTHEDGE (0x04)
68 73
69#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */ 74#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */
70 75
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-irq.h b/arch/arm/mach-s5pc100/include/mach/regs-irq.h
index 751ac15438c8..4d9036d0f288 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-irq.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-irq.h
@@ -3,7 +3,7 @@
3 * Copyright 2009 Samsung Electronics Co. 3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com> 4 * Byungho Min <bhmin@samsung.com>
5 * 5 *
6 * S5PC1XX - IRQ register definitions 6 * S5PC100 - IRQ register definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -16,9 +16,4 @@
16#include <mach/map.h> 16#include <mach/map.h>
17#include <asm/hardware/vic.h> 17#include <asm/hardware/vic.h>
18 18
19/* interrupt controller */
20#define S5PC1XX_VIC0REG(x) ((x) + S5PC1XX_VA_VIC(0))
21#define S5PC1XX_VIC1REG(x) ((x) + S5PC1XX_VA_VIC(1))
22#define S5PC1XX_VIC2REG(x) ((x) + S5PC1XX_VA_VIC(2))
23
24#endif /* __ASM_ARCH_REGS_IRQ_H */ 19#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h
index f0d31a2a598c..681f626a9ae1 100644
--- a/arch/arm/mach-s5pc100/include/mach/system.h
+++ b/arch/arm/mach-s5pc100/include/mach/system.h
@@ -3,7 +3,7 @@
3 * Copyright 2009 Samsung Electronics Co. 3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com> 4 * Byungho Min <bhmin@samsung.com>
5 * 5 *
6 * S5PC1XX - system implementation 6 * S5PC100 - system implementation
7 * 7 *
8 * Based on mach-s3c6400/include/mach/system.h 8 * Based on mach-s3c6400/include/mach/system.h
9 */ 9 */
@@ -13,14 +13,11 @@
13 13
14#include <linux/io.h> 14#include <linux/io.h>
15#include <mach/map.h> 15#include <mach/map.h>
16#include <plat/regs-clock.h> 16#include <mach/regs-clock.h>
17
18void (*s5pc1xx_idle)(void);
19 17
20static void arch_idle(void) 18static void arch_idle(void)
21{ 19{
22 if (s5pc1xx_idle) 20 /* nothing here yet */
23 s5pc1xx_idle();
24} 21}
25 22
26static void arch_reset(char mode, const char *cmd) 23static void arch_reset(char mode, const char *cmd)
diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h
index f338c9eec717..20f68730ed18 100644
--- a/arch/arm/mach-s5pc100/include/mach/tick.h
+++ b/arch/arm/mach-s5pc100/include/mach/tick.h
@@ -20,8 +20,8 @@
20 */ 20 */
21static inline u32 s3c24xx_ostimer_pending(void) 21static inline u32 s3c24xx_ostimer_pending(void)
22{ 22{
23 u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS); 23 u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
24 return pend & 1 << (IRQ_TIMER4_VIC - S5PC1XX_IRQ_VIC0(0)); 24 return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
25} 25}
26 26
27#define TICK_MAX (0xffffffff) 27#define TICK_MAX (0xffffffff)
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-init.c b/arch/arm/mach-s5pc100/init.c
index c58710884ceb..19d7b523c137 100644
--- a/arch/arm/plat-s5pc1xx/s5pc100-init.c
+++ b/arch/arm/mach-s5pc100/init.c
@@ -1,9 +1,8 @@
1/* linux/arch/arm/plat-s5pc1xx/s5pc100-init.c 1/* linux/arch/arm/plat-s5pc100/s5pc100-init.c
2 * 2 *
3 * Copyright 2009 Samsung Electronics Co. 3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com> 4 * Byungho Min <bhmin@samsung.com>
5 * 5 *
6 * S5PC100 - CPU initialisation (common with other S5PC1XX chips)
7 * 6 *
8 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -19,9 +18,7 @@
19#include <plat/s5pc100.h> 18#include <plat/s5pc100.h>
20 19
21/* uart registration process */ 20/* uart registration process */
22
23void __init s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) 21void __init s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
24{ 22{
25 /* The driver name is s3c6400-uart to reuse s3c6400_serial_drv */ 23 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
26 s3c24xx_init_uartdevs("s3c6400-uart", s5pc1xx_uart_resources, cfg, no);
27} 24}
diff --git a/arch/arm/plat-s5pc1xx/irq-gpio.c b/arch/arm/mach-s5pc100/irq-gpio.c
index fecca7a679b0..2bf86c18bc73 100644
--- a/arch/arm/plat-s5pc1xx/irq-gpio.c
+++ b/arch/arm/mach-s5pc100/irq-gpio.c
@@ -1,9 +1,9 @@
1/* 1/*
2 * arch/arm/plat-s5pc1xx/irq-gpio.c 2 * arch/arm/mach-s5pc100/irq-gpio.c
3 * 3 *
4 * Copyright (C) 2009 Samsung Electronics 4 * Copyright (C) 2009 Samsung Electronics
5 * 5 *
6 * S5PC1XX - Interrupt handling for IRQ_GPIO${group}(x) 6 * S5PC100 - Interrupt handling for IRQ_GPIO${group}(x)
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -19,7 +19,7 @@
19#include <mach/map.h> 19#include <mach/map.h>
20#include <plat/gpio-cfg.h> 20#include <plat/gpio-cfg.h>
21 21
22#define S5PC1XX_GPIOREG(x) (S5PC1XX_VA_GPIO + (x)) 22#define S5P_GPIOREG(x) (S5P_VA_GPIO + (x))
23 23
24#define CON_OFFSET 0x700 24#define CON_OFFSET 0x700
25#define MASK_OFFSET 0x900 25#define MASK_OFFSET 0x900
@@ -49,7 +49,7 @@ static int group_to_pend_offset(int group)
49 return group << 2; 49 return group << 2;
50} 50}
51 51
52static int s5pc1xx_get_start(unsigned int group) 52static int s5pc100_get_start(unsigned int group)
53{ 53{
54 switch (group) { 54 switch (group) {
55 case 0: return S5PC100_GPIO_A0_START; 55 case 0: return S5PC100_GPIO_A0_START;
@@ -80,7 +80,7 @@ static int s5pc1xx_get_start(unsigned int group)
80 return -EINVAL; 80 return -EINVAL;
81} 81}
82 82
83static int s5pc1xx_get_group(unsigned int irq) 83static int s5pc100_get_group(unsigned int irq)
84{ 84{
85 irq -= S3C_IRQ_GPIO(0); 85 irq -= S3C_IRQ_GPIO(0);
86 86
@@ -134,67 +134,67 @@ static int s5pc1xx_get_group(unsigned int irq)
134 return -EINVAL; 134 return -EINVAL;
135} 135}
136 136
137static int s5pc1xx_get_offset(unsigned int irq) 137static int s5pc100_get_offset(unsigned int irq)
138{ 138{
139 struct gpio_chip *chip = get_irq_data(irq); 139 struct gpio_chip *chip = get_irq_data(irq);
140 return irq - S3C_IRQ_GPIO(chip->base); 140 return irq - S3C_IRQ_GPIO(chip->base);
141} 141}
142 142
143static void s5pc1xx_gpioint_ack(unsigned int irq) 143static void s5pc100_gpioint_ack(unsigned int irq)
144{ 144{
145 int group, offset, pend_offset; 145 int group, offset, pend_offset;
146 unsigned int value; 146 unsigned int value;
147 147
148 group = s5pc1xx_get_group(irq); 148 group = s5pc100_get_group(irq);
149 offset = s5pc1xx_get_offset(irq); 149 offset = s5pc100_get_offset(irq);
150 pend_offset = group_to_pend_offset(group); 150 pend_offset = group_to_pend_offset(group);
151 151
152 value = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset); 152 value = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
153 value |= 1 << offset; 153 value |= 1 << offset;
154 __raw_writel(value, S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset); 154 __raw_writel(value, S5P_GPIOREG(PEND_OFFSET) + pend_offset);
155} 155}
156 156
157static void s5pc1xx_gpioint_mask(unsigned int irq) 157static void s5pc100_gpioint_mask(unsigned int irq)
158{ 158{
159 int group, offset, mask_offset; 159 int group, offset, mask_offset;
160 unsigned int value; 160 unsigned int value;
161 161
162 group = s5pc1xx_get_group(irq); 162 group = s5pc100_get_group(irq);
163 offset = s5pc1xx_get_offset(irq); 163 offset = s5pc100_get_offset(irq);
164 mask_offset = group_to_mask_offset(group); 164 mask_offset = group_to_mask_offset(group);
165 165
166 value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); 166 value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
167 value |= 1 << offset; 167 value |= 1 << offset;
168 __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); 168 __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
169} 169}
170 170
171static void s5pc1xx_gpioint_unmask(unsigned int irq) 171static void s5pc100_gpioint_unmask(unsigned int irq)
172{ 172{
173 int group, offset, mask_offset; 173 int group, offset, mask_offset;
174 unsigned int value; 174 unsigned int value;
175 175
176 group = s5pc1xx_get_group(irq); 176 group = s5pc100_get_group(irq);
177 offset = s5pc1xx_get_offset(irq); 177 offset = s5pc100_get_offset(irq);
178 mask_offset = group_to_mask_offset(group); 178 mask_offset = group_to_mask_offset(group);
179 179
180 value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); 180 value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
181 value &= ~(1 << offset); 181 value &= ~(1 << offset);
182 __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); 182 __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
183} 183}
184 184
185static void s5pc1xx_gpioint_mask_ack(unsigned int irq) 185static void s5pc100_gpioint_mask_ack(unsigned int irq)
186{ 186{
187 s5pc1xx_gpioint_mask(irq); 187 s5pc100_gpioint_mask(irq);
188 s5pc1xx_gpioint_ack(irq); 188 s5pc100_gpioint_ack(irq);
189} 189}
190 190
191static int s5pc1xx_gpioint_set_type(unsigned int irq, unsigned int type) 191static int s5pc100_gpioint_set_type(unsigned int irq, unsigned int type)
192{ 192{
193 int group, offset, con_offset; 193 int group, offset, con_offset;
194 unsigned int value; 194 unsigned int value;
195 195
196 group = s5pc1xx_get_group(irq); 196 group = s5pc100_get_group(irq);
197 offset = s5pc1xx_get_offset(irq); 197 offset = s5pc100_get_offset(irq);
198 con_offset = group_to_con_offset(group); 198 con_offset = group_to_con_offset(group);
199 199
200 switch (type) { 200 switch (type) {
@@ -221,24 +221,24 @@ static int s5pc1xx_gpioint_set_type(unsigned int irq, unsigned int type)
221 } 221 }
222 222
223 223
224 value = __raw_readl(S5PC1XX_GPIOREG(CON_OFFSET) + con_offset); 224 value = __raw_readl(S5P_GPIOREG(CON_OFFSET) + con_offset);
225 value &= ~(0xf << (offset * 0x4)); 225 value &= ~(0xf << (offset * 0x4));
226 value |= (type << (offset * 0x4)); 226 value |= (type << (offset * 0x4));
227 __raw_writel(value, S5PC1XX_GPIOREG(CON_OFFSET) + con_offset); 227 __raw_writel(value, S5P_GPIOREG(CON_OFFSET) + con_offset);
228 228
229 return 0; 229 return 0;
230} 230}
231 231
232struct irq_chip s5pc1xx_gpioint = { 232struct irq_chip s5pc100_gpioint = {
233 .name = "GPIO", 233 .name = "GPIO",
234 .ack = s5pc1xx_gpioint_ack, 234 .ack = s5pc100_gpioint_ack,
235 .mask = s5pc1xx_gpioint_mask, 235 .mask = s5pc100_gpioint_mask,
236 .mask_ack = s5pc1xx_gpioint_mask_ack, 236 .mask_ack = s5pc100_gpioint_mask_ack,
237 .unmask = s5pc1xx_gpioint_unmask, 237 .unmask = s5pc100_gpioint_unmask,
238 .set_type = s5pc1xx_gpioint_set_type, 238 .set_type = s5pc100_gpioint_set_type,
239}; 239};
240 240
241void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc) 241void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
242{ 242{
243 int group, offset, pend_offset, mask_offset; 243 int group, offset, pend_offset, mask_offset;
244 int real_irq, group_end; 244 int real_irq, group_end;
@@ -248,17 +248,17 @@ void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
248 248
249 for (group = 0; group < group_end; group++) { 249 for (group = 0; group < group_end; group++) {
250 pend_offset = group_to_pend_offset(group); 250 pend_offset = group_to_pend_offset(group);
251 pend = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset); 251 pend = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
252 if (!pend) 252 if (!pend)
253 continue; 253 continue;
254 254
255 mask_offset = group_to_mask_offset(group); 255 mask_offset = group_to_mask_offset(group);
256 mask = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); 256 mask = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
257 pend &= ~mask; 257 pend &= ~mask;
258 258
259 for (offset = 0; offset < 8; offset++) { 259 for (offset = 0; offset < 8; offset++) {
260 if (pend & (1 << offset)) { 260 if (pend & (1 << offset)) {
261 real_irq = s5pc1xx_get_start(group) + offset; 261 real_irq = s5pc100_get_start(group) + offset;
262 generic_handle_irq(S3C_IRQ_GPIO(real_irq)); 262 generic_handle_irq(S3C_IRQ_GPIO(real_irq));
263 } 263 }
264 } 264 }
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index bfe67db34f04..a95d8f7d36d1 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -43,38 +43,48 @@
43#include <plat/fb.h> 43#include <plat/fb.h>
44#include <plat/iic.h> 44#include <plat/iic.h>
45 45
46#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK) 46/* Following are default values for UCON, ULCON and UFCON UART registers */
47#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) 47#define S5PC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
48#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) 48 S3C2410_UCON_RXILEVEL | \
49 S3C2410_UCON_TXIRQMODE | \
50 S3C2410_UCON_RXIRQMODE | \
51 S3C2410_UCON_RXFIFO_TOI | \
52 S3C2443_UCON_RXERR_IRQEN)
53
54#define S5PC100_ULCON_DEFAULT S3C2410_LCON_CS8
55
56#define S5PC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
57 S3C2440_UFCON_RXTRIG8 | \
58 S3C2440_UFCON_TXTRIG16)
49 59
50static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = { 60static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
51 [0] = { 61 [0] = {
52 .hwport = 0, 62 .hwport = 0,
53 .flags = 0, 63 .flags = 0,
54 .ucon = 0x3c5, 64 .ucon = S5PC100_UCON_DEFAULT,
55 .ulcon = 0x03, 65 .ulcon = S5PC100_ULCON_DEFAULT,
56 .ufcon = 0x51, 66 .ufcon = S5PC100_UFCON_DEFAULT,
57 }, 67 },
58 [1] = { 68 [1] = {
59 .hwport = 1, 69 .hwport = 1,
60 .flags = 0, 70 .flags = 0,
61 .ucon = 0x3c5, 71 .ucon = S5PC100_UCON_DEFAULT,
62 .ulcon = 0x03, 72 .ulcon = S5PC100_ULCON_DEFAULT,
63 .ufcon = 0x51, 73 .ufcon = S5PC100_UFCON_DEFAULT,
64 }, 74 },
65 [2] = { 75 [2] = {
66 .hwport = 2, 76 .hwport = 2,
67 .flags = 0, 77 .flags = 0,
68 .ucon = 0x3c5, 78 .ucon = S5PC100_UCON_DEFAULT,
69 .ulcon = 0x03, 79 .ulcon = S5PC100_ULCON_DEFAULT,
70 .ufcon = 0x51, 80 .ufcon = S5PC100_UFCON_DEFAULT,
71 }, 81 },
72 [3] = { 82 [3] = {
73 .hwport = 3, 83 .hwport = 3,
74 .flags = 0, 84 .flags = 0,
75 .ucon = 0x3c5, 85 .ucon = S5PC100_UCON_DEFAULT,
76 .ulcon = 0x03, 86 .ulcon = S5PC100_ULCON_DEFAULT,
77 .ufcon = 0x51, 87 .ufcon = S5PC100_UFCON_DEFAULT,
78 }, 88 },
79}; 89};
80 90
@@ -118,8 +128,7 @@ static struct platform_device smdkc100_lcd_powerdev = {
118static struct s3c_fb_pd_win smdkc100_fb_win0 = { 128static struct s3c_fb_pd_win smdkc100_fb_win0 = {
119 /* this is to ensure we use win0 */ 129 /* this is to ensure we use win0 */
120 .win_mode = { 130 .win_mode = {
121 .refresh = 70, 131 .pixclock = 1000000000000ULL / ((8+13+3+800)*(7+5+1+480)*80),
122 .pixclock = (8+13+3+800)*(7+5+1+480),
123 .left_margin = 8, 132 .left_margin = 8,
124 .right_margin = 13, 133 .right_margin = 13,
125 .upper_margin = 7, 134 .upper_margin = 7,
@@ -140,8 +149,6 @@ static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = {
140 .setup_gpio = s5pc100_fb_gpio_setup_24bpp, 149 .setup_gpio = s5pc100_fb_gpio_setup_24bpp,
141}; 150};
142 151
143static struct map_desc smdkc100_iodesc[] = {};
144
145static struct platform_device *smdkc100_devices[] __initdata = { 152static struct platform_device *smdkc100_devices[] __initdata = {
146 &s3c_device_i2c0, 153 &s3c_device_i2c0,
147 &s3c_device_i2c1, 154 &s3c_device_i2c1,
@@ -154,7 +161,7 @@ static struct platform_device *smdkc100_devices[] __initdata = {
154 161
155static void __init smdkc100_map_io(void) 162static void __init smdkc100_map_io(void)
156{ 163{
157 s5pc1xx_init_io(smdkc100_iodesc, ARRAY_SIZE(smdkc100_iodesc)); 164 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
158 s3c24xx_init_clocks(12000000); 165 s3c24xx_init_clocks(12000000);
159 s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs)); 166 s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs));
160} 167}
@@ -178,10 +185,9 @@ static void __init smdkc100_machine_init(void)
178 185
179MACHINE_START(SMDKC100, "SMDKC100") 186MACHINE_START(SMDKC100, "SMDKC100")
180 /* Maintainer: Byungho Min <bhmin@samsung.com> */ 187 /* Maintainer: Byungho Min <bhmin@samsung.com> */
181 .phys_io = S5PC100_PA_UART & 0xfff00000, 188 .phys_io = S3C_PA_UART & 0xfff00000,
182 .io_pg_offst = (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc, 189 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
183 .boot_params = S5PC100_PA_SDRAM + 0x100, 190 .boot_params = S5P_PA_SDRAM + 0x100,
184
185 .init_irq = s5pc100_init_irq, 191 .init_irq = s5pc100_init_irq,
186 .map_io = smdkc100_map_io, 192 .map_io = smdkc100_map_io,
187 .init_machine = smdkc100_machine_init, 193 .init_machine = smdkc100_machine_init,
diff --git a/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
index 185c8941e644..7769c760c9ef 100644
--- a/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
@@ -1,8 +1,8 @@
1/* linux/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c 1/* linux/arch/arm/plat-s5pc100/setup-sdhci-gpio.c
2 * 2 *
3 * Copyright 2009 Samsung Eletronics 3 * Copyright 2009 Samsung Eletronics
4 * 4 *
5 * S5PC1XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) 5 * S5PC100 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index c2361132d867..5cb2dd1da632 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -7,7 +7,7 @@
7 7
8config PLAT_S5P 8config PLAT_S5P
9 bool 9 bool
10 depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PV210) 10 depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210)
11 default y 11 default y
12 select ARM_VIC 12 select ARM_VIC
13 select NO_IOPORT 13 select NO_IOPORT
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index f92e5de3a755..75cb8c37ca2c 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -19,12 +19,14 @@
19#include <plat/cpu.h> 19#include <plat/cpu.h>
20#include <plat/s5p6440.h> 20#include <plat/s5p6440.h>
21#include <plat/s5p6442.h> 21#include <plat/s5p6442.h>
22#include <plat/s5pc100.h>
22#include <plat/s5pv210.h> 23#include <plat/s5pv210.h>
23 24
24/* table of supported CPUs */ 25/* table of supported CPUs */
25 26
26static const char name_s5p6440[] = "S5P6440"; 27static const char name_s5p6440[] = "S5P6440";
27static const char name_s5p6442[] = "S5P6442"; 28static const char name_s5p6442[] = "S5P6442";
29static const char name_s5pc100[] = "S5PC100";
28static const char name_s5pv210[] = "S5PV210/S5PC110"; 30static const char name_s5pv210[] = "S5PV210/S5PC110";
29 31
30static struct cpu_table cpu_ids[] __initdata = { 32static struct cpu_table cpu_ids[] __initdata = {
@@ -45,6 +47,14 @@ static struct cpu_table cpu_ids[] __initdata = {
45 .init = s5p6442_init, 47 .init = s5p6442_init,
46 .name = name_s5p6442, 48 .name = name_s5p6442,
47 }, { 49 }, {
50 .idcode = 0x43100000,
51 .idmask = 0xfffff000,
52 .map_io = s5pc100_map_io,
53 .init_clocks = s5pc100_init_clocks,
54 .init_uarts = s5pc100_init_uarts,
55 .init = s5pc100_init,
56 .name = name_s5pc100,
57 }, {
48 .idcode = 0x43110000, 58 .idcode = 0x43110000,
49 .idmask = 0xfffff000, 59 .idmask = 0xfffff000,
50 .map_io = s5pv210_map_io, 60 .map_io = s5pv210_map_io,
diff --git a/arch/arm/plat-s5p/include/plat/s5pc100.h b/arch/arm/plat-s5p/include/plat/s5pc100.h
new file mode 100644
index 000000000000..5f6099dd7cad
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/s5pc100.h
@@ -0,0 +1,33 @@
1/* arch/arm/plat-s5p/include/plat/s5pc100.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Header file for s5pc100 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for S5PC100 related SoCs */
14
15extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
16extern void s5pc100_register_clocks(void);
17extern void s5pc100_setup_clocks(void);
18
19#ifdef CONFIG_CPU_S5PC100
20
21extern int s5pc100_init(void);
22extern void s5pc100_init_irq(void);
23extern void s5pc100_map_io(void);
24extern void s5pc100_init_clocks(int xtal);
25
26#define s5pc100_init_uarts s5pc100_common_init_uarts
27
28#else
29#define s5pc100_init_clocks NULL
30#define s5pc100_init_uarts NULL
31#define s5pc100_map_io NULL
32#define s5pc100_init NULL
33#endif
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
deleted file mode 100644
index c7bd2bbda239..000000000000
--- a/arch/arm/plat-s5pc1xx/Kconfig
+++ /dev/null
@@ -1,47 +0,0 @@
1# Copyright 2009 Samsung Electronics Co.
2# Byungho Min <bhmin@samsung.com>
3#
4# Licensed under GPLv2
5
6config PLAT_S5PC1XX
7 bool
8 depends on ARCH_S5PC1XX
9 default y
10 select PLAT_S3C
11 select ARM_VIC
12 select NO_IOPORT
13 select ARCH_REQUIRE_GPIOLIB
14 select SAMSUNG_CLKSRC
15 select SAMSUNG_IRQ_UART
16 select SAMSUNG_IRQ_VIC_TIMER
17 select S3C_GPIO_TRACK
18 select S3C_GPIO_PULL_UPDOWN
19 select S5P_GPIO_DRVSTR
20 select S3C_GPIO_CFG_S3C24XX
21 select S3C_GPIO_CFG_S3C64XX
22 select SAMSUNG_GPIOLIB_4BIT
23 help
24 Base platform code for any Samsung S5PC1XX device
25
26if PLAT_S5PC1XX
27
28# Configuration options shared by all S3C64XX implementations
29
30config CPU_S5PC100_INIT
31 bool
32 help
33 Common initialisation code for the S5PC1XX
34
35config CPU_S5PC100_CLOCK
36 bool
37 help
38 Common clock support code for the S5PC1XX
39
40# platform specific device setup
41
42config S5PC1XX_SETUP_SDHCI_GPIO
43 bool
44 help
45 Common setup code for SDHCI gpio.
46
47endif
diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile
deleted file mode 100644
index 9ce6409a9e02..000000000000
--- a/arch/arm/plat-s5pc1xx/Makefile
+++ /dev/null
@@ -1,26 +0,0 @@
1# arch/arm/plat-s5pc1xx/Makefile
2#
3# Copyright 2009 Samsung Electronics Co.
4#
5# Licensed under GPLv2
6
7obj-y :=
8obj-m :=
9obj-n := dummy.o
10obj- :=
11
12# Core files
13
14obj-y += dev-uart.o
15obj-y += cpu.o
16obj-y += irq.o
17obj-y += clock.o
18
19# CPU support
20
21obj-$(CONFIG_CPU_S5PC100_INIT) += s5pc100-init.o
22obj-$(CONFIG_CPU_S5PC100_CLOCK) += s5pc100-clock.o
23
24# Device setup
25
26obj-$(CONFIG_S5PC1XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c
deleted file mode 100644
index 387f23190c3c..000000000000
--- a/arch/arm/plat-s5pc1xx/clock.c
+++ /dev/null
@@ -1,709 +0,0 @@
1/* linux/arch/arm/plat-s5pc1xx/clock.c
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 *
5 * S5PC1XX Base clock support
6 *
7 * Based on plat-s3c64xx/clock.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/ioport.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20
21#include <mach/hardware.h>
22#include <mach/map.h>
23
24#include <plat/regs-clock.h>
25#include <plat/devs.h>
26#include <plat/clock.h>
27
28struct clk clk_27m = {
29 .name = "clk_27m",
30 .id = -1,
31 .rate = 27000000,
32};
33
34static int clk_48m_ctrl(struct clk *clk, int enable)
35{
36 unsigned long flags;
37 u32 val;
38
39 /* can't rely on clock lock, this register has other usages */
40 local_irq_save(flags);
41
42 val = __raw_readl(S5PC100_CLKSRC1);
43 if (enable)
44 val |= S5PC100_CLKSRC1_CLK48M_MASK;
45 else
46 val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
47
48 __raw_writel(val, S5PC100_CLKSRC1);
49 local_irq_restore(flags);
50
51 return 0;
52}
53
54struct clk clk_48m = {
55 .name = "clk_48m",
56 .id = -1,
57 .rate = 48000000,
58 .enable = clk_48m_ctrl,
59};
60
61struct clk clk_54m = {
62 .name = "clk_54m",
63 .id = -1,
64 .rate = 54000000,
65};
66
67struct clk clk_hd0 = {
68 .name = "hclkd0",
69 .id = -1,
70 .rate = 0,
71 .parent = NULL,
72 .ctrlbit = 0,
73 .ops = &clk_ops_def_setrate,
74};
75
76struct clk clk_pd0 = {
77 .name = "pclkd0",
78 .id = -1,
79 .rate = 0,
80 .parent = NULL,
81 .ctrlbit = 0,
82 .ops = &clk_ops_def_setrate,
83};
84
85static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)
86{
87 unsigned int ctrlbit = clk->ctrlbit;
88 u32 con;
89
90 con = __raw_readl(reg);
91 if (enable)
92 con |= ctrlbit;
93 else
94 con &= ~ctrlbit;
95 __raw_writel(con, reg);
96
97 return 0;
98}
99
100static int s5pc100_clk_d00_ctrl(struct clk *clk, int enable)
101{
102 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
103}
104
105static int s5pc100_clk_d01_ctrl(struct clk *clk, int enable)
106{
107 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
108}
109
110static int s5pc100_clk_d02_ctrl(struct clk *clk, int enable)
111{
112 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
113}
114
115static int s5pc100_clk_d10_ctrl(struct clk *clk, int enable)
116{
117 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
118}
119
120static int s5pc100_clk_d11_ctrl(struct clk *clk, int enable)
121{
122 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
123}
124
125static int s5pc100_clk_d12_ctrl(struct clk *clk, int enable)
126{
127 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
128}
129
130static int s5pc100_clk_d13_ctrl(struct clk *clk, int enable)
131{
132 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
133}
134
135static int s5pc100_clk_d14_ctrl(struct clk *clk, int enable)
136{
137 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
138}
139
140static int s5pc100_clk_d15_ctrl(struct clk *clk, int enable)
141{
142 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
143}
144
145static int s5pc100_clk_d20_ctrl(struct clk *clk, int enable)
146{
147 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
148}
149
150int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
151{
152 return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
153}
154
155int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
156{
157 return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
158}
159
160static struct clk s5pc100_init_clocks_disable[] = {
161 {
162 .name = "dsi",
163 .id = -1,
164 .parent = &clk_p,
165 .enable = s5pc100_clk_d11_ctrl,
166 .ctrlbit = S5PC100_CLKGATE_D11_DSI,
167 }, {
168 .name = "csi",
169 .id = -1,
170 .parent = &clk_h,
171 .enable = s5pc100_clk_d11_ctrl,
172 .ctrlbit = S5PC100_CLKGATE_D11_CSI,
173 }, {
174 .name = "ccan",
175 .id = 0,
176 .parent = &clk_p,
177 .enable = s5pc100_clk_d14_ctrl,
178 .ctrlbit = S5PC100_CLKGATE_D14_CCAN0,
179 }, {
180 .name = "ccan",
181 .id = 1,
182 .parent = &clk_p,
183 .enable = s5pc100_clk_d14_ctrl,
184 .ctrlbit = S5PC100_CLKGATE_D14_CCAN1,
185 }, {
186 .name = "keypad",
187 .id = -1,
188 .parent = &clk_p,
189 .enable = s5pc100_clk_d15_ctrl,
190 .ctrlbit = S5PC100_CLKGATE_D15_KEYIF,
191 }, {
192 .name = "hclkd2",
193 .id = -1,
194 .parent = NULL,
195 .enable = s5pc100_clk_d20_ctrl,
196 .ctrlbit = S5PC100_CLKGATE_D20_HCLKD2,
197 }, {
198 .name = "iis-d2",
199 .id = -1,
200 .parent = NULL,
201 .enable = s5pc100_clk_d20_ctrl,
202 .ctrlbit = S5PC100_CLKGATE_D20_I2SD2,
203 },
204};
205
206static struct clk s5pc100_init_clocks[] = {
207 /* System1 (D0_0) devices */
208 {
209 .name = "intc",
210 .id = -1,
211 .parent = &clk_hd0,
212 .enable = s5pc100_clk_d00_ctrl,
213 .ctrlbit = S5PC100_CLKGATE_D00_INTC,
214 }, {
215 .name = "tzic",
216 .id = -1,
217 .parent = &clk_hd0,
218 .enable = s5pc100_clk_d00_ctrl,
219 .ctrlbit = S5PC100_CLKGATE_D00_TZIC,
220 }, {
221 .name = "cf-ata",
222 .id = -1,
223 .parent = &clk_hd0,
224 .enable = s5pc100_clk_d00_ctrl,
225 .ctrlbit = S5PC100_CLKGATE_D00_CFCON,
226 }, {
227 .name = "mdma",
228 .id = -1,
229 .parent = &clk_hd0,
230 .enable = s5pc100_clk_d00_ctrl,
231 .ctrlbit = S5PC100_CLKGATE_D00_MDMA,
232 }, {
233 .name = "g2d",
234 .id = -1,
235 .parent = &clk_hd0,
236 .enable = s5pc100_clk_d00_ctrl,
237 .ctrlbit = S5PC100_CLKGATE_D00_G2D,
238 }, {
239 .name = "secss",
240 .id = -1,
241 .parent = &clk_hd0,
242 .enable = s5pc100_clk_d00_ctrl,
243 .ctrlbit = S5PC100_CLKGATE_D00_SECSS,
244 }, {
245 .name = "cssys",
246 .id = -1,
247 .parent = &clk_hd0,
248 .enable = s5pc100_clk_d00_ctrl,
249 .ctrlbit = S5PC100_CLKGATE_D00_CSSYS,
250 },
251
252 /* Memory (D0_1) devices */
253 {
254 .name = "dmc",
255 .id = -1,
256 .parent = &clk_hd0,
257 .enable = s5pc100_clk_d01_ctrl,
258 .ctrlbit = S5PC100_CLKGATE_D01_DMC,
259 }, {
260 .name = "sromc",
261 .id = -1,
262 .parent = &clk_hd0,
263 .enable = s5pc100_clk_d01_ctrl,
264 .ctrlbit = S5PC100_CLKGATE_D01_SROMC,
265 }, {
266 .name = "onenand",
267 .id = -1,
268 .parent = &clk_hd0,
269 .enable = s5pc100_clk_d01_ctrl,
270 .ctrlbit = S5PC100_CLKGATE_D01_ONENAND,
271 }, {
272 .name = "nand",
273 .id = -1,
274 .parent = &clk_hd0,
275 .enable = s5pc100_clk_d01_ctrl,
276 .ctrlbit = S5PC100_CLKGATE_D01_NFCON,
277 }, {
278 .name = "intmem",
279 .id = -1,
280 .parent = &clk_hd0,
281 .enable = s5pc100_clk_d01_ctrl,
282 .ctrlbit = S5PC100_CLKGATE_D01_INTMEM,
283 }, {
284 .name = "ebi",
285 .id = -1,
286 .parent = &clk_hd0,
287 .enable = s5pc100_clk_d01_ctrl,
288 .ctrlbit = S5PC100_CLKGATE_D01_EBI,
289 },
290
291 /* System2 (D0_2) devices */
292 {
293 .name = "seckey",
294 .id = -1,
295 .parent = &clk_pd0,
296 .enable = s5pc100_clk_d02_ctrl,
297 .ctrlbit = S5PC100_CLKGATE_D02_SECKEY,
298 }, {
299 .name = "sdm",
300 .id = -1,
301 .parent = &clk_hd0,
302 .enable = s5pc100_clk_d02_ctrl,
303 .ctrlbit = S5PC100_CLKGATE_D02_SDM,
304 },
305
306 /* File (D1_0) devices */
307 {
308 .name = "pdma",
309 .id = 0,
310 .parent = &clk_h,
311 .enable = s5pc100_clk_d10_ctrl,
312 .ctrlbit = S5PC100_CLKGATE_D10_PDMA0,
313 }, {
314 .name = "pdma",
315 .id = 1,
316 .parent = &clk_h,
317 .enable = s5pc100_clk_d10_ctrl,
318 .ctrlbit = S5PC100_CLKGATE_D10_PDMA1,
319 }, {
320 .name = "usb-host",
321 .id = -1,
322 .parent = &clk_h,
323 .enable = s5pc100_clk_d10_ctrl,
324 .ctrlbit = S5PC100_CLKGATE_D10_USBHOST,
325 }, {
326 .name = "otg",
327 .id = -1,
328 .parent = &clk_h,
329 .enable = s5pc100_clk_d10_ctrl,
330 .ctrlbit = S5PC100_CLKGATE_D10_USBOTG,
331 }, {
332 .name = "modem",
333 .id = -1,
334 .parent = &clk_h,
335 .enable = s5pc100_clk_d10_ctrl,
336 .ctrlbit = S5PC100_CLKGATE_D10_MODEMIF,
337 }, {
338 .name = "hsmmc",
339 .id = 0,
340 .parent = &clk_48m,
341 .enable = s5pc100_clk_d10_ctrl,
342 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC0,
343 }, {
344 .name = "hsmmc",
345 .id = 1,
346 .parent = &clk_48m,
347 .enable = s5pc100_clk_d10_ctrl,
348 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC1,
349 }, {
350 .name = "hsmmc",
351 .id = 2,
352 .parent = &clk_48m,
353 .enable = s5pc100_clk_d10_ctrl,
354 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC2,
355 },
356
357 /* Multimedia1 (D1_1) devices */
358 {
359 .name = "lcd",
360 .id = -1,
361 .parent = &clk_p,
362 .enable = s5pc100_clk_d11_ctrl,
363 .ctrlbit = S5PC100_CLKGATE_D11_LCD,
364 }, {
365 .name = "rotator",
366 .id = -1,
367 .parent = &clk_p,
368 .enable = s5pc100_clk_d11_ctrl,
369 .ctrlbit = S5PC100_CLKGATE_D11_ROTATOR,
370 }, {
371 .name = "fimc",
372 .id = -1,
373 .parent = &clk_p,
374 .enable = s5pc100_clk_d11_ctrl,
375 .ctrlbit = S5PC100_CLKGATE_D11_FIMC0,
376 }, {
377 .name = "fimc",
378 .id = -1,
379 .parent = &clk_p,
380 .enable = s5pc100_clk_d11_ctrl,
381 .ctrlbit = S5PC100_CLKGATE_D11_FIMC1,
382 }, {
383 .name = "fimc",
384 .id = -1,
385 .parent = &clk_p,
386 .enable = s5pc100_clk_d11_ctrl,
387 .ctrlbit = S5PC100_CLKGATE_D11_FIMC2,
388 }, {
389 .name = "jpeg",
390 .id = -1,
391 .parent = &clk_p,
392 .enable = s5pc100_clk_d11_ctrl,
393 .ctrlbit = S5PC100_CLKGATE_D11_JPEG,
394 }, {
395 .name = "g3d",
396 .id = -1,
397 .parent = &clk_p,
398 .enable = s5pc100_clk_d11_ctrl,
399 .ctrlbit = S5PC100_CLKGATE_D11_G3D,
400 },
401
402 /* Multimedia2 (D1_2) devices */
403 {
404 .name = "tv",
405 .id = -1,
406 .parent = &clk_p,
407 .enable = s5pc100_clk_d12_ctrl,
408 .ctrlbit = S5PC100_CLKGATE_D12_TV,
409 }, {
410 .name = "vp",
411 .id = -1,
412 .parent = &clk_p,
413 .enable = s5pc100_clk_d12_ctrl,
414 .ctrlbit = S5PC100_CLKGATE_D12_VP,
415 }, {
416 .name = "mixer",
417 .id = -1,
418 .parent = &clk_p,
419 .enable = s5pc100_clk_d12_ctrl,
420 .ctrlbit = S5PC100_CLKGATE_D12_MIXER,
421 }, {
422 .name = "hdmi",
423 .id = -1,
424 .parent = &clk_p,
425 .enable = s5pc100_clk_d12_ctrl,
426 .ctrlbit = S5PC100_CLKGATE_D12_HDMI,
427 }, {
428 .name = "mfc",
429 .id = -1,
430 .parent = &clk_p,
431 .enable = s5pc100_clk_d12_ctrl,
432 .ctrlbit = S5PC100_CLKGATE_D12_MFC,
433 },
434
435 /* System (D1_3) devices */
436 {
437 .name = "chipid",
438 .id = -1,
439 .parent = &clk_p,
440 .enable = s5pc100_clk_d13_ctrl,
441 .ctrlbit = S5PC100_CLKGATE_D13_CHIPID,
442 }, {
443 .name = "gpio",
444 .id = -1,
445 .parent = &clk_p,
446 .enable = s5pc100_clk_d13_ctrl,
447 .ctrlbit = S5PC100_CLKGATE_D13_GPIO,
448 }, {
449 .name = "apc",
450 .id = -1,
451 .parent = &clk_p,
452 .enable = s5pc100_clk_d13_ctrl,
453 .ctrlbit = S5PC100_CLKGATE_D13_APC,
454 }, {
455 .name = "iec",
456 .id = -1,
457 .parent = &clk_p,
458 .enable = s5pc100_clk_d13_ctrl,
459 .ctrlbit = S5PC100_CLKGATE_D13_IEC,
460 }, {
461 .name = "timers",
462 .id = -1,
463 .parent = &clk_p,
464 .enable = s5pc100_clk_d13_ctrl,
465 .ctrlbit = S5PC100_CLKGATE_D13_PWM,
466 }, {
467 .name = "systimer",
468 .id = -1,
469 .parent = &clk_p,
470 .enable = s5pc100_clk_d13_ctrl,
471 .ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER,
472 }, {
473 .name = "watchdog",
474 .id = -1,
475 .parent = &clk_p,
476 .enable = s5pc100_clk_d13_ctrl,
477 .ctrlbit = S5PC100_CLKGATE_D13_WDT,
478 }, {
479 .name = "rtc",
480 .id = -1,
481 .parent = &clk_p,
482 .enable = s5pc100_clk_d13_ctrl,
483 .ctrlbit = S5PC100_CLKGATE_D13_RTC,
484 },
485
486 /* Connectivity (D1_4) devices */
487 {
488 .name = "uart",
489 .id = 0,
490 .parent = &clk_p,
491 .enable = s5pc100_clk_d14_ctrl,
492 .ctrlbit = S5PC100_CLKGATE_D14_UART0,
493 }, {
494 .name = "uart",
495 .id = 1,
496 .parent = &clk_p,
497 .enable = s5pc100_clk_d14_ctrl,
498 .ctrlbit = S5PC100_CLKGATE_D14_UART1,
499 }, {
500 .name = "uart",
501 .id = 2,
502 .parent = &clk_p,
503 .enable = s5pc100_clk_d14_ctrl,
504 .ctrlbit = S5PC100_CLKGATE_D14_UART2,
505 }, {
506 .name = "uart",
507 .id = 3,
508 .parent = &clk_p,
509 .enable = s5pc100_clk_d14_ctrl,
510 .ctrlbit = S5PC100_CLKGATE_D14_UART3,
511 }, {
512 .name = "i2c",
513 .id = -1,
514 .parent = &clk_p,
515 .enable = s5pc100_clk_d14_ctrl,
516 .ctrlbit = S5PC100_CLKGATE_D14_IIC,
517 }, {
518 .name = "hdmi-i2c",
519 .id = -1,
520 .parent = &clk_p,
521 .enable = s5pc100_clk_d14_ctrl,
522 .ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC,
523 }, {
524 .name = "spi",
525 .id = 0,
526 .parent = &clk_p,
527 .enable = s5pc100_clk_d14_ctrl,
528 .ctrlbit = S5PC100_CLKGATE_D14_SPI0,
529 }, {
530 .name = "spi",
531 .id = 1,
532 .parent = &clk_p,
533 .enable = s5pc100_clk_d14_ctrl,
534 .ctrlbit = S5PC100_CLKGATE_D14_SPI1,
535 }, {
536 .name = "spi",
537 .id = 2,
538 .parent = &clk_p,
539 .enable = s5pc100_clk_d14_ctrl,
540 .ctrlbit = S5PC100_CLKGATE_D14_SPI2,
541 }, {
542 .name = "irda",
543 .id = -1,
544 .parent = &clk_p,
545 .enable = s5pc100_clk_d14_ctrl,
546 .ctrlbit = S5PC100_CLKGATE_D14_IRDA,
547 }, {
548 .name = "hsitx",
549 .id = -1,
550 .parent = &clk_p,
551 .enable = s5pc100_clk_d14_ctrl,
552 .ctrlbit = S5PC100_CLKGATE_D14_HSITX,
553 }, {
554 .name = "hsirx",
555 .id = -1,
556 .parent = &clk_p,
557 .enable = s5pc100_clk_d14_ctrl,
558 .ctrlbit = S5PC100_CLKGATE_D14_HSIRX,
559 },
560
561 /* Audio (D1_5) devices */
562 {
563 .name = "iis",
564 .id = 0,
565 .parent = &clk_p,
566 .enable = s5pc100_clk_d15_ctrl,
567 .ctrlbit = S5PC100_CLKGATE_D15_IIS0,
568 }, {
569 .name = "iis",
570 .id = 1,
571 .parent = &clk_p,
572 .enable = s5pc100_clk_d15_ctrl,
573 .ctrlbit = S5PC100_CLKGATE_D15_IIS1,
574 }, {
575 .name = "iis",
576 .id = 2,
577 .parent = &clk_p,
578 .enable = s5pc100_clk_d15_ctrl,
579 .ctrlbit = S5PC100_CLKGATE_D15_IIS2,
580 }, {
581 .name = "ac97",
582 .id = -1,
583 .parent = &clk_p,
584 .enable = s5pc100_clk_d15_ctrl,
585 .ctrlbit = S5PC100_CLKGATE_D15_AC97,
586 }, {
587 .name = "pcm",
588 .id = 0,
589 .parent = &clk_p,
590 .enable = s5pc100_clk_d15_ctrl,
591 .ctrlbit = S5PC100_CLKGATE_D15_PCM0,
592 }, {
593 .name = "pcm",
594 .id = 1,
595 .parent = &clk_p,
596 .enable = s5pc100_clk_d15_ctrl,
597 .ctrlbit = S5PC100_CLKGATE_D15_PCM1,
598 }, {
599 .name = "spdif",
600 .id = -1,
601 .parent = &clk_p,
602 .enable = s5pc100_clk_d15_ctrl,
603 .ctrlbit = S5PC100_CLKGATE_D15_SPDIF,
604 }, {
605 .name = "adc",
606 .id = -1,
607 .parent = &clk_p,
608 .enable = s5pc100_clk_d15_ctrl,
609 .ctrlbit = S5PC100_CLKGATE_D15_TSADC,
610 }, {
611 .name = "cg",
612 .id = -1,
613 .parent = &clk_p,
614 .enable = s5pc100_clk_d15_ctrl,
615 .ctrlbit = S5PC100_CLKGATE_D15_CG,
616 },
617
618 /* Audio (D2_0) devices: all disabled */
619
620 /* Special Clocks 0 */
621 {
622 .name = "sclk_hpm",
623 .id = -1,
624 .parent = NULL,
625 .enable = s5pc100_sclk0_ctrl,
626 .ctrlbit = S5PC100_CLKGATE_SCLK0_HPM,
627 }, {
628 .name = "sclk_onenand",
629 .id = -1,
630 .parent = NULL,
631 .enable = s5pc100_sclk0_ctrl,
632 .ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND,
633 }, {
634 .name = "spi_48",
635 .id = 0,
636 .parent = &clk_48m,
637 .enable = s5pc100_sclk0_ctrl,
638 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48,
639 }, {
640 .name = "spi_48",
641 .id = 1,
642 .parent = &clk_48m,
643 .enable = s5pc100_sclk0_ctrl,
644 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48,
645 }, {
646 .name = "spi_48",
647 .id = 2,
648 .parent = &clk_48m,
649 .enable = s5pc100_sclk0_ctrl,
650 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48,
651 }, {
652 .name = "mmc_48",
653 .id = 0,
654 .parent = &clk_48m,
655 .enable = s5pc100_sclk0_ctrl,
656 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48,
657 }, {
658 .name = "mmc_48",
659 .id = 1,
660 .parent = &clk_48m,
661 .enable = s5pc100_sclk0_ctrl,
662 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48,
663 }, {
664 .name = "mmc_48",
665 .id = 2,
666 .parent = &clk_48m,
667 .enable = s5pc100_sclk0_ctrl,
668 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48,
669 },
670 /* Special Clocks 1 */
671};
672
673static struct clk *clks[] __initdata = {
674 &clk_ext,
675 &clk_epll,
676 &clk_pd0,
677 &clk_hd0,
678 &clk_27m,
679 &clk_48m,
680 &clk_54m,
681};
682
683void __init s5pc1xx_register_clocks(void)
684{
685 struct clk *clkp;
686 int ret;
687 int ptr;
688 int size;
689
690 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
691
692 s3c_register_clocks(s5pc100_init_clocks,
693 ARRAY_SIZE(s5pc100_init_clocks));
694
695 clkp = s5pc100_init_clocks_disable;
696 size = ARRAY_SIZE(s5pc100_init_clocks_disable);
697
698 for (ptr = 0; ptr < size; ptr++, clkp++) {
699 ret = s3c24xx_register_clock(clkp);
700 if (ret < 0) {
701 printk(KERN_ERR "Failed to register clock %s (%d)\n",
702 clkp->name, ret);
703 }
704
705 (clkp->enable)(clkp, 0);
706 }
707
708 s3c_pwmclk_init();
709}
diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c
deleted file mode 100644
index 02baeaa2a121..000000000000
--- a/arch/arm/plat-s5pc1xx/cpu.c
+++ /dev/null
@@ -1,122 +0,0 @@
1/* linux/arch/arm/plat-s5pc1xx/cpu.c
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC1XX CPU Support
7 *
8 * Based on plat-s3c64xx/cpu.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/serial_core.h>
20#include <linux/platform_device.h>
21#include <linux/io.h>
22
23#include <mach/hardware.h>
24#include <mach/map.h>
25
26#include <asm/mach/map.h>
27
28#include <plat/regs-serial.h>
29
30#include <plat/cpu.h>
31#include <plat/devs.h>
32#include <plat/clock.h>
33
34#include <plat/s5pc100.h>
35
36/* table of supported CPUs */
37
38static const char name_s5pc100[] = "S5PC100";
39
40static struct cpu_table cpu_ids[] __initdata = {
41 {
42 .idcode = 0x43100000,
43 .idmask = 0xfffff000,
44 .map_io = s5pc100_map_io,
45 .init_clocks = s5pc100_init_clocks,
46 .init_uarts = s5pc100_init_uarts,
47 .init = s5pc100_init,
48 .name = name_s5pc100,
49 },
50};
51/* minimal IO mapping */
52
53/* see notes on uart map in arch/arm/mach-s5pc100/include/mach/debug-macro.S */
54#define UART_OFFS (S3C_PA_UART & 0xffff)
55
56static struct map_desc s5pc1xx_iodesc[] __initdata = {
57 {
58 .virtual = (unsigned long)S5PC1XX_VA_CLK_OTHER,
59 .pfn = __phys_to_pfn(S5PC1XX_PA_CLK_OTHER),
60 .length = SZ_4K,
61 .type = MT_DEVICE,
62 }, {
63 .virtual = (unsigned long)S5PC1XX_VA_GPIO,
64 .pfn = __phys_to_pfn(S5PC100_PA_GPIO),
65 .length = SZ_4K,
66 .type = MT_DEVICE,
67 }, {
68 .virtual = (unsigned long)S5PC1XX_VA_CHIPID,
69 .pfn = __phys_to_pfn(S5PC1XX_PA_CHIPID),
70 .length = SZ_16,
71 .type = MT_DEVICE,
72 }, {
73 .virtual = (unsigned long)S5PC1XX_VA_CLK,
74 .pfn = __phys_to_pfn(S5PC1XX_PA_CLK),
75 .length = SZ_4K,
76 .type = MT_DEVICE,
77 }, {
78 .virtual = (unsigned long)S5PC1XX_VA_PWR,
79 .pfn = __phys_to_pfn(S5PC1XX_PA_PWR),
80 .length = SZ_4K,
81 .type = MT_DEVICE,
82 }, {
83 .virtual = (unsigned long)(S5PC1XX_VA_UART),
84 .pfn = __phys_to_pfn(S5PC1XX_PA_UART),
85 .length = SZ_4K,
86 .type = MT_DEVICE,
87 }, {
88 .virtual = (unsigned long)S5PC1XX_VA_VIC(0),
89 .pfn = __phys_to_pfn(S5PC1XX_PA_VIC(0)),
90 .length = SZ_4K,
91 .type = MT_DEVICE,
92 }, {
93 .virtual = (unsigned long)S5PC1XX_VA_VIC(1),
94 .pfn = __phys_to_pfn(S5PC1XX_PA_VIC(1)),
95 .length = SZ_4K,
96 .type = MT_DEVICE,
97 }, {
98 .virtual = (unsigned long)S5PC1XX_VA_VIC(2),
99 .pfn = __phys_to_pfn(S5PC1XX_PA_VIC(2)),
100 .length = SZ_4K,
101 .type = MT_DEVICE,
102 }, {
103 .virtual = (unsigned long)S5PC1XX_VA_TIMER,
104 .pfn = __phys_to_pfn(S5PC1XX_PA_TIMER),
105 .length = SZ_256,
106 .type = MT_DEVICE,
107 },
108};
109
110/* read cpu identification code */
111
112void __init s5pc1xx_init_io(struct map_desc *mach_desc, int size)
113{
114 unsigned long idcode;
115
116 /* initialise the io descriptors we need for initialisation */
117 iotable_init(s5pc1xx_iodesc, ARRAY_SIZE(s5pc1xx_iodesc));
118 iotable_init(mach_desc, size);
119
120 idcode = __raw_readl(S5PC1XX_VA_CHIPID);
121 s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
122}
diff --git a/arch/arm/plat-s5pc1xx/dev-uart.c b/arch/arm/plat-s5pc1xx/dev-uart.c
deleted file mode 100644
index 586c95c60bfe..000000000000
--- a/arch/arm/plat-s5pc1xx/dev-uart.c
+++ /dev/null
@@ -1,145 +0,0 @@
1/* linux/arch/arm/plat-s5pc1xx/dev-uart.c
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * Based on plat-s3c64xx/dev-uart.c
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/platform_device.h>
19
20#include <asm/mach/arch.h>
21#include <asm/mach/irq.h>
22#include <mach/hardware.h>
23#include <mach/map.h>
24
25#include <plat/devs.h>
26
27/* Serial port registrations */
28
29/* 64xx uarts are closer together */
30
31static struct resource s5pc1xx_uart0_resource[] = {
32 [0] = {
33 .start = S3C_PA_UART0,
34 .end = S3C_PA_UART0 + 0x100,
35 .flags = IORESOURCE_MEM,
36 },
37 [1] = {
38 .start = IRQ_S3CUART_RX0,
39 .end = IRQ_S3CUART_RX0,
40 .flags = IORESOURCE_IRQ,
41 },
42 [2] = {
43 .start = IRQ_S3CUART_TX0,
44 .end = IRQ_S3CUART_TX0,
45 .flags = IORESOURCE_IRQ,
46
47 },
48 [3] = {
49 .start = IRQ_S3CUART_ERR0,
50 .end = IRQ_S3CUART_ERR0,
51 .flags = IORESOURCE_IRQ,
52 }
53};
54
55static struct resource s5pc1xx_uart1_resource[] = {
56 [0] = {
57 .start = S3C_PA_UART1,
58 .end = S3C_PA_UART1 + 0x100,
59 .flags = IORESOURCE_MEM,
60 },
61 [1] = {
62 .start = IRQ_S3CUART_RX1,
63 .end = IRQ_S3CUART_RX1,
64 .flags = IORESOURCE_IRQ,
65 },
66 [2] = {
67 .start = IRQ_S3CUART_TX1,
68 .end = IRQ_S3CUART_TX1,
69 .flags = IORESOURCE_IRQ,
70
71 },
72 [3] = {
73 .start = IRQ_S3CUART_ERR1,
74 .end = IRQ_S3CUART_ERR1,
75 .flags = IORESOURCE_IRQ,
76 },
77};
78
79static struct resource s5pc1xx_uart2_resource[] = {
80 [0] = {
81 .start = S3C_PA_UART2,
82 .end = S3C_PA_UART2 + 0x100,
83 .flags = IORESOURCE_MEM,
84 },
85 [1] = {
86 .start = IRQ_S3CUART_RX2,
87 .end = IRQ_S3CUART_RX2,
88 .flags = IORESOURCE_IRQ,
89 },
90 [2] = {
91 .start = IRQ_S3CUART_TX2,
92 .end = IRQ_S3CUART_TX2,
93 .flags = IORESOURCE_IRQ,
94
95 },
96 [3] = {
97 .start = IRQ_S3CUART_ERR2,
98 .end = IRQ_S3CUART_ERR2,
99 .flags = IORESOURCE_IRQ,
100 },
101};
102
103static struct resource s5pc1xx_uart3_resource[] = {
104 [0] = {
105 .start = S3C_PA_UART3,
106 .end = S3C_PA_UART3 + 0x100,
107 .flags = IORESOURCE_MEM,
108 },
109 [1] = {
110 .start = IRQ_S3CUART_RX3,
111 .end = IRQ_S3CUART_RX3,
112 .flags = IORESOURCE_IRQ,
113 },
114 [2] = {
115 .start = IRQ_S3CUART_TX3,
116 .end = IRQ_S3CUART_TX3,
117 .flags = IORESOURCE_IRQ,
118
119 },
120 [3] = {
121 .start = IRQ_S3CUART_ERR3,
122 .end = IRQ_S3CUART_ERR3,
123 .flags = IORESOURCE_IRQ,
124 },
125};
126
127
128struct s3c24xx_uart_resources s5pc1xx_uart_resources[] __initdata = {
129 [0] = {
130 .resources = s5pc1xx_uart0_resource,
131 .nr_resources = ARRAY_SIZE(s5pc1xx_uart0_resource),
132 },
133 [1] = {
134 .resources = s5pc1xx_uart1_resource,
135 .nr_resources = ARRAY_SIZE(s5pc1xx_uart1_resource),
136 },
137 [2] = {
138 .resources = s5pc1xx_uart2_resource,
139 .nr_resources = ARRAY_SIZE(s5pc1xx_uart2_resource),
140 },
141 [3] = {
142 .resources = s5pc1xx_uart3_resource,
143 .nr_resources = ARRAY_SIZE(s5pc1xx_uart3_resource),
144 },
145};
diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h
deleted file mode 100644
index 33ad267e8477..000000000000
--- a/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-eint.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 *
5 * External Interrupt (GPH0 ~ GPH3) control register definitions
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#define S5PC1XX_WKUP_INT_CON0_7 (S5PC1XX_EINT_BASE + 0x0)
13#define S5PC1XX_WKUP_INT_CON8_15 (S5PC1XX_EINT_BASE + 0x4)
14#define S5PC1XX_WKUP_INT_CON16_23 (S5PC1XX_EINT_BASE + 0x8)
15#define S5PC1XX_WKUP_INT_CON24_31 (S5PC1XX_EINT_BASE + 0xC)
16#define S5PC1XX_WKUP_INT_CON(x) (S5PC1XX_WKUP_INT_CON0_7 + (x * 0x4))
17
18#define S5PC1XX_WKUP_INT_FLTCON0_3 (S5PC1XX_EINT_BASE + 0x80)
19#define S5PC1XX_WKUP_INT_FLTCON4_7 (S5PC1XX_EINT_BASE + 0x84)
20#define S5PC1XX_WKUP_INT_FLTCON8_11 (S5PC1XX_EINT_BASE + 0x88)
21#define S5PC1XX_WKUP_INT_FLTCON12_15 (S5PC1XX_EINT_BASE + 0x8C)
22#define S5PC1XX_WKUP_INT_FLTCON16_19 (S5PC1XX_EINT_BASE + 0x90)
23#define S5PC1XX_WKUP_INT_FLTCON20_23 (S5PC1XX_EINT_BASE + 0x94)
24#define S5PC1XX_WKUP_INT_FLTCON24_27 (S5PC1XX_EINT_BASE + 0x98)
25#define S5PC1XX_WKUP_INT_FLTCON28_31 (S5PC1XX_EINT_BASE + 0x9C)
26#define S5PC1XX_WKUP_INT_FLTCON(x) (S5PC1XX_WKUP_INT_FLTCON0_3 + (x * 0x4))
27
28#define S5PC1XX_WKUP_INT_MASK0_7 (S5PC1XX_EINT_BASE + 0x100)
29#define S5PC1XX_WKUP_INT_MASK8_15 (S5PC1XX_EINT_BASE + 0x104)
30#define S5PC1XX_WKUP_INT_MASK16_23 (S5PC1XX_EINT_BASE + 0x108)
31#define S5PC1XX_WKUP_INT_MASK24_31 (S5PC1XX_EINT_BASE + 0x10C)
32#define S5PC1XX_WKUP_INT_MASK(x) (S5PC1XX_WKUP_INT_MASK0_7 + (x * 0x4))
33
34#define S5PC1XX_WKUP_INT_PEND0_7 (S5PC1XX_EINT_BASE + 0x140)
35#define S5PC1XX_WKUP_INT_PEND8_15 (S5PC1XX_EINT_BASE + 0x144)
36#define S5PC1XX_WKUP_INT_PEND16_23 (S5PC1XX_EINT_BASE + 0x148)
37#define S5PC1XX_WKUP_INT_PEND24_31 (S5PC1XX_EINT_BASE + 0x14C)
38#define S5PC1XX_WKUP_INT_PEND(x) (S5PC1XX_WKUP_INT_PEND0_7 + (x * 0x4))
39
40#define S5PC1XX_WKUP_INT_LOWLEV (0x00)
41#define S5PC1XX_WKUP_INT_HILEV (0x01)
42#define S5PC1XX_WKUP_INT_FALLEDGE (0x02)
43#define S5PC1XX_WKUP_INT_RISEEDGE (0x03)
44#define S5PC1XX_WKUP_INT_BOTHEDGE (0x04)
diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h
deleted file mode 100644
index 409c804315e8..000000000000
--- a/arch/arm/plat-s5pc1xx/include/plat/irqs.h
+++ /dev/null
@@ -1,198 +0,0 @@
1/* linux/arch/arm/plat-s5pc1xx/include/plat/irqs.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC1XX - Common IRQ support
7 *
8 * Based on plat-s3c64xx/include/plat/irqs.h
9 */
10
11#ifndef __ASM_PLAT_S5PC1XX_IRQS_H
12#define __ASM_PLAT_S5PC1XX_IRQS_H __FILE__
13
14/* we keep the first set of CPU IRQs out of the range of
15 * the ISA space, so that the PC104 has them to itself
16 * and we don't end up having to do horrible things to the
17 * standard ISA drivers....
18 *
19 * note, since we're using the VICs, our start must be a
20 * mulitple of 32 to allow the common code to work
21 */
22
23#define S3C_IRQ_OFFSET (32)
24
25#define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET)
26
27#define S3C_VIC0_BASE S3C_IRQ(0)
28#define S3C_VIC1_BASE S3C_IRQ(32)
29#define S3C_VIC2_BASE S3C_IRQ(64)
30
31/* UART interrupts, each UART has 4 intterupts per channel so
32 * use the space between the ISA and S3C main interrupts. Note, these
33 * are not in the same order as the S3C24XX series! */
34
35#define IRQ_S3CUART_BASE0 (16)
36#define IRQ_S3CUART_BASE1 (20)
37#define IRQ_S3CUART_BASE2 (24)
38#define IRQ_S3CUART_BASE3 (28)
39
40#define UART_IRQ_RXD (0)
41#define UART_IRQ_ERR (1)
42#define UART_IRQ_TXD (2)
43#define UART_IRQ_MODEM (3)
44
45#define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
46#define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
47#define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
48
49#define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
50#define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
51#define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
52
53#define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
54#define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
55#define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
56
57#define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
58#define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
59#define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
60
61/* VIC based IRQs */
62
63#define S5PC1XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x))
64#define S5PC1XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x))
65#define S5PC1XX_IRQ_VIC2(x) (S3C_VIC2_BASE + (x))
66
67/*
68 * VIC0: system, DMA, timer
69 */
70#define IRQ_EINT0 S5PC1XX_IRQ_VIC0(0)
71#define IRQ_EINT1 S5PC1XX_IRQ_VIC0(1)
72#define IRQ_EINT2 S5PC1XX_IRQ_VIC0(2)
73#define IRQ_EINT3 S5PC1XX_IRQ_VIC0(3)
74#define IRQ_EINT4 S5PC1XX_IRQ_VIC0(4)
75#define IRQ_EINT5 S5PC1XX_IRQ_VIC0(5)
76#define IRQ_EINT6 S5PC1XX_IRQ_VIC0(6)
77#define IRQ_EINT7 S5PC1XX_IRQ_VIC0(7)
78#define IRQ_EINT8 S5PC1XX_IRQ_VIC0(8)
79#define IRQ_EINT9 S5PC1XX_IRQ_VIC0(9)
80#define IRQ_EINT10 S5PC1XX_IRQ_VIC0(10)
81#define IRQ_EINT11 S5PC1XX_IRQ_VIC0(11)
82#define IRQ_EINT12 S5PC1XX_IRQ_VIC0(12)
83#define IRQ_EINT13 S5PC1XX_IRQ_VIC0(13)
84#define IRQ_EINT14 S5PC1XX_IRQ_VIC0(14)
85#define IRQ_EINT15 S5PC1XX_IRQ_VIC0(15)
86#define IRQ_EINT16_31 S5PC1XX_IRQ_VIC0(16)
87#define IRQ_BATF S5PC1XX_IRQ_VIC0(17)
88#define IRQ_MDMA S5PC1XX_IRQ_VIC0(18)
89#define IRQ_PDMA0 S5PC1XX_IRQ_VIC0(19)
90#define IRQ_PDMA1 S5PC1XX_IRQ_VIC0(20)
91#define IRQ_TIMER0_VIC S5PC1XX_IRQ_VIC0(21)
92#define IRQ_TIMER1_VIC S5PC1XX_IRQ_VIC0(22)
93#define IRQ_TIMER2_VIC S5PC1XX_IRQ_VIC0(23)
94#define IRQ_TIMER3_VIC S5PC1XX_IRQ_VIC0(24)
95#define IRQ_TIMER4_VIC S5PC1XX_IRQ_VIC0(25)
96#define IRQ_SYSTIMER S5PC1XX_IRQ_VIC0(26)
97#define IRQ_WDT S5PC1XX_IRQ_VIC0(27)
98#define IRQ_RTC_ALARM S5PC1XX_IRQ_VIC0(28)
99#define IRQ_RTC_TIC S5PC1XX_IRQ_VIC0(29)
100#define IRQ_GPIOINT S5PC1XX_IRQ_VIC0(30)
101
102/*
103 * VIC1: ARM, power, memory, connectivity
104 */
105#define IRQ_CORTEX0 S5PC1XX_IRQ_VIC1(0)
106#define IRQ_CORTEX1 S5PC1XX_IRQ_VIC1(1)
107#define IRQ_CORTEX2 S5PC1XX_IRQ_VIC1(2)
108#define IRQ_CORTEX3 S5PC1XX_IRQ_VIC1(3)
109#define IRQ_CORTEX4 S5PC1XX_IRQ_VIC1(4)
110#define IRQ_IEMAPC S5PC1XX_IRQ_VIC1(5)
111#define IRQ_IEMIEC S5PC1XX_IRQ_VIC1(6)
112#define IRQ_ONENAND S5PC1XX_IRQ_VIC1(7)
113#define IRQ_NFC S5PC1XX_IRQ_VIC1(8)
114#define IRQ_CFC S5PC1XX_IRQ_VIC1(9)
115#define IRQ_UART0 S5PC1XX_IRQ_VIC1(10)
116#define IRQ_UART1 S5PC1XX_IRQ_VIC1(11)
117#define IRQ_UART2 S5PC1XX_IRQ_VIC1(12)
118#define IRQ_UART3 S5PC1XX_IRQ_VIC1(13)
119#define IRQ_IIC S5PC1XX_IRQ_VIC1(14)
120#define IRQ_SPI0 S5PC1XX_IRQ_VIC1(15)
121#define IRQ_SPI1 S5PC1XX_IRQ_VIC1(16)
122#define IRQ_SPI2 S5PC1XX_IRQ_VIC1(17)
123#define IRQ_IRDA S5PC1XX_IRQ_VIC1(18)
124#define IRQ_CAN0 S5PC1XX_IRQ_VIC1(19)
125#define IRQ_CAN1 S5PC1XX_IRQ_VIC1(20)
126#define IRQ_HSIRX S5PC1XX_IRQ_VIC1(21)
127#define IRQ_HSITX S5PC1XX_IRQ_VIC1(22)
128#define IRQ_UHOST S5PC1XX_IRQ_VIC1(23)
129#define IRQ_OTG S5PC1XX_IRQ_VIC1(24)
130#define IRQ_MSM S5PC1XX_IRQ_VIC1(25)
131#define IRQ_HSMMC0 S5PC1XX_IRQ_VIC1(26)
132#define IRQ_HSMMC1 S5PC1XX_IRQ_VIC1(27)
133#define IRQ_HSMMC2 S5PC1XX_IRQ_VIC1(28)
134#define IRQ_MIPICSI S5PC1XX_IRQ_VIC1(29)
135#define IRQ_MIPIDSI S5PC1XX_IRQ_VIC1(30)
136
137/*
138 * VIC2: multimedia, audio, security
139 */
140#define IRQ_LCD0 S5PC1XX_IRQ_VIC2(0)
141#define IRQ_LCD1 S5PC1XX_IRQ_VIC2(1)
142#define IRQ_LCD2 S5PC1XX_IRQ_VIC2(2)
143#define IRQ_LCD3 S5PC1XX_IRQ_VIC2(3)
144#define IRQ_ROTATOR S5PC1XX_IRQ_VIC2(4)
145#define IRQ_FIMC0 S5PC1XX_IRQ_VIC2(5)
146#define IRQ_FIMC1 S5PC1XX_IRQ_VIC2(6)
147#define IRQ_FIMC2 S5PC1XX_IRQ_VIC2(7)
148#define IRQ_JPEG S5PC1XX_IRQ_VIC2(8)
149#define IRQ_2D S5PC1XX_IRQ_VIC2(9)
150#define IRQ_3D S5PC1XX_IRQ_VIC2(10)
151#define IRQ_MIXER S5PC1XX_IRQ_VIC2(11)
152#define IRQ_HDMI S5PC1XX_IRQ_VIC2(12)
153#define IRQ_IIC1 S5PC1XX_IRQ_VIC2(13)
154#define IRQ_MFC S5PC1XX_IRQ_VIC2(14)
155#define IRQ_TVENC S5PC1XX_IRQ_VIC2(15)
156#define IRQ_I2S0 S5PC1XX_IRQ_VIC2(16)
157#define IRQ_I2S1 S5PC1XX_IRQ_VIC2(17)
158#define IRQ_I2S2 S5PC1XX_IRQ_VIC2(18)
159#define IRQ_AC97 S5PC1XX_IRQ_VIC2(19)
160#define IRQ_PCM0 S5PC1XX_IRQ_VIC2(20)
161#define IRQ_PCM1 S5PC1XX_IRQ_VIC2(21)
162#define IRQ_SPDIF S5PC1XX_IRQ_VIC2(22)
163#define IRQ_ADC S5PC1XX_IRQ_VIC2(23)
164#define IRQ_PENDN S5PC1XX_IRQ_VIC2(24)
165#define IRQ_TC IRQ_PENDN
166#define IRQ_KEYPAD S5PC1XX_IRQ_VIC2(25)
167#define IRQ_CG S5PC1XX_IRQ_VIC2(26)
168#define IRQ_SEC S5PC1XX_IRQ_VIC2(27)
169#define IRQ_SECRX S5PC1XX_IRQ_VIC2(28)
170#define IRQ_SECTX S5PC1XX_IRQ_VIC2(29)
171#define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30)
172#define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31)
173
174#define IRQ_TIMER(x) (IRQ_SDMFIQ + 1 + (x))
175#define IRQ_TIMER0 IRQ_TIMER(0)
176#define IRQ_TIMER1 IRQ_TIMER(1)
177#define IRQ_TIMER2 IRQ_TIMER(2)
178#define IRQ_TIMER3 IRQ_TIMER(3)
179#define IRQ_TIMER4 IRQ_TIMER(4)
180
181/* External interrupt */
182#define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 6)
183
184#define S3C_EINT(x) (S3C_IRQ_EINT_BASE + (x - 16))
185#define IRQ_EINT(x) (x < 16 ? IRQ_EINT0 + x : S3C_EINT(x))
186#define IRQ_EINT_BIT(x) (x < IRQ_EINT16_31 ? x - IRQ_EINT0 : x - S3C_EINT(0))
187
188/* GPIO interrupt */
189#define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1)
190#define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x))
191
192/*
193 * Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs
194 */
195#define NR_IRQS (S3C_IRQ_GPIO(320) + 1)
196
197#endif /* __ASM_PLAT_S5PC1XX_IRQS_H */
198
diff --git a/arch/arm/plat-s5pc1xx/include/plat/pll.h b/arch/arm/plat-s5pc1xx/include/plat/pll.h
deleted file mode 100644
index 21afef1573e7..000000000000
--- a/arch/arm/plat-s5pc1xx/include/plat/pll.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/* arch/arm/plat-s5pc1xx/include/plat/pll.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC1XX PLL code
7 *
8 * Based on plat-s3c64xx/include/plat/pll.h
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#define S5P_PLL_MDIV_MASK ((1 << (25-16+1)) - 1)
16#define S5P_PLL_PDIV_MASK ((1 << (13-8+1)) - 1)
17#define S5P_PLL_SDIV_MASK ((1 << (2-0+1)) - 1)
18#define S5P_PLL_MDIV_SHIFT (16)
19#define S5P_PLL_PDIV_SHIFT (8)
20#define S5P_PLL_SDIV_SHIFT (0)
21
22#include <asm/div64.h>
23
24static inline unsigned long s5pc1xx_get_pll(unsigned long baseclk,
25 u32 pllcon)
26{
27 u32 mdiv, pdiv, sdiv;
28 u64 fvco = baseclk;
29
30 mdiv = (pllcon >> S5P_PLL_MDIV_SHIFT) & S5P_PLL_MDIV_MASK;
31 pdiv = (pllcon >> S5P_PLL_PDIV_SHIFT) & S5P_PLL_PDIV_MASK;
32 sdiv = (pllcon >> S5P_PLL_SDIV_SHIFT) & S5P_PLL_SDIV_MASK;
33
34 fvco *= mdiv;
35 do_div(fvco, (pdiv << sdiv));
36
37 return (unsigned long)fvco;
38}
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
deleted file mode 100644
index 24dec4e52538..000000000000
--- a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
+++ /dev/null
@@ -1,252 +0,0 @@
1/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC1XX clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __PLAT_REGS_CLOCK_H
14#define __PLAT_REGS_CLOCK_H __FILE__
15
16#define S5PC100_CLKREG(x) (S5PC1XX_VA_CLK + (x))
17#define S5PC100_CLKREG_OTHER(x) (S5PC1XX_VA_CLK_OTHER + (x))
18
19/* s5pc100 register for clock */
20#define S5PC100_APLL_LOCK S5PC100_CLKREG(0x00)
21#define S5PC100_MPLL_LOCK S5PC100_CLKREG(0x04)
22#define S5PC100_EPLL_LOCK S5PC100_CLKREG(0x08)
23#define S5PC100_HPLL_LOCK S5PC100_CLKREG(0x0C)
24
25#define S5PC100_APLL_CON S5PC100_CLKREG(0x100)
26#define S5PC100_MPLL_CON S5PC100_CLKREG(0x104)
27#define S5PC100_EPLL_CON S5PC100_CLKREG(0x108)
28#define S5PC100_HPLL_CON S5PC100_CLKREG(0x10C)
29
30#define S5PC100_CLKSRC0 S5PC100_CLKREG(0x200)
31#define S5PC100_CLKSRC1 S5PC100_CLKREG(0x204)
32#define S5PC100_CLKSRC2 S5PC100_CLKREG(0x208)
33#define S5PC100_CLKSRC3 S5PC100_CLKREG(0x20C)
34
35#define S5PC100_CLKDIV0 S5PC100_CLKREG(0x300)
36#define S5PC100_CLKDIV1 S5PC100_CLKREG(0x304)
37#define S5PC100_CLKDIV2 S5PC100_CLKREG(0x308)
38#define S5PC100_CLKDIV3 S5PC100_CLKREG(0x30C)
39#define S5PC100_CLKDIV4 S5PC100_CLKREG(0x310)
40
41#define S5PC100_CLK_OUT S5PC100_CLKREG(0x400)
42
43#define S5PC100_CLKGATE_D00 S5PC100_CLKREG(0x500)
44#define S5PC100_CLKGATE_D01 S5PC100_CLKREG(0x504)
45#define S5PC100_CLKGATE_D02 S5PC100_CLKREG(0x508)
46
47#define S5PC100_CLKGATE_D10 S5PC100_CLKREG(0x520)
48#define S5PC100_CLKGATE_D11 S5PC100_CLKREG(0x524)
49#define S5PC100_CLKGATE_D12 S5PC100_CLKREG(0x528)
50#define S5PC100_CLKGATE_D13 S5PC100_CLKREG(0x52C)
51#define S5PC100_CLKGATE_D14 S5PC100_CLKREG(0x530)
52#define S5PC100_CLKGATE_D15 S5PC100_CLKREG(0x534)
53
54#define S5PC100_CLKGATE_D20 S5PC100_CLKREG(0x540)
55
56#define S5PC100_SCLKGATE0 S5PC100_CLKREG(0x560)
57#define S5PC100_SCLKGATE1 S5PC100_CLKREG(0x564)
58
59/* EPLL_CON */
60#define S5PC100_EPLL_EN (1<<31)
61#define S5PC100_EPLL_MASK 0xffffffff
62#define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s)))
63
64/* CLKSRC0..CLKSRC3 -> mostly removed due to clksrc updates */
65#define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24)
66#define S5PC100_CLKSRC1_CLK48M_SHIFT (24)
67
68/* CLKDIV0 */
69#define S5PC100_CLKDIV0_APLL_MASK (0x1<<0)
70#define S5PC100_CLKDIV0_APLL_SHIFT (0)
71#define S5PC100_CLKDIV0_ARM_MASK (0x7<<4)
72#define S5PC100_CLKDIV0_ARM_SHIFT (4)
73#define S5PC100_CLKDIV0_D0_MASK (0x7<<8)
74#define S5PC100_CLKDIV0_D0_SHIFT (8)
75#define S5PC100_CLKDIV0_PCLKD0_MASK (0x7<<12)
76#define S5PC100_CLKDIV0_PCLKD0_SHIFT (12)
77#define S5PC100_CLKDIV0_SECSS_MASK (0x7<<16)
78#define S5PC100_CLKDIV0_SECSS_SHIFT (16)
79
80/* CLKDIV1 (OneNAND clock only used in one place, removed) */
81#define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0)
82#define S5PC100_CLKDIV1_APLL2_SHIFT (0)
83#define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4)
84#define S5PC100_CLKDIV1_MPLL_SHIFT (4)
85#define S5PC100_CLKDIV1_MPLL2_MASK (0x1<<8)
86#define S5PC100_CLKDIV1_MPLL2_SHIFT (8)
87#define S5PC100_CLKDIV1_D1_MASK (0x7<<12)
88#define S5PC100_CLKDIV1_D1_SHIFT (12)
89#define S5PC100_CLKDIV1_PCLKD1_MASK (0x7<<16)
90#define S5PC100_CLKDIV1_PCLKD1_SHIFT (16)
91#define S5PC100_CLKDIV1_CAM_MASK (0x1F<<24)
92#define S5PC100_CLKDIV1_CAM_SHIFT (24)
93
94/* CLKDIV2 => removed in clksrc update */
95/* CLKDIV3 => removed in clksrc update, or not needed */
96/* CLKDIV4 => removed in clksrc update, or not needed */
97
98/* HCLKD0/PCLKD0 Clock Gate 0 Registers */
99#define S5PC100_CLKGATE_D00_INTC (1<<0)
100#define S5PC100_CLKGATE_D00_TZIC (1<<1)
101#define S5PC100_CLKGATE_D00_CFCON (1<<2)
102#define S5PC100_CLKGATE_D00_MDMA (1<<3)
103#define S5PC100_CLKGATE_D00_G2D (1<<4)
104#define S5PC100_CLKGATE_D00_SECSS (1<<5)
105#define S5PC100_CLKGATE_D00_CSSYS (1<<6)
106
107/* HCLKD0/PCLKD0 Clock Gate 1 Registers */
108#define S5PC100_CLKGATE_D01_DMC (1<<0)
109#define S5PC100_CLKGATE_D01_SROMC (1<<1)
110#define S5PC100_CLKGATE_D01_ONENAND (1<<2)
111#define S5PC100_CLKGATE_D01_NFCON (1<<3)
112#define S5PC100_CLKGATE_D01_INTMEM (1<<4)
113#define S5PC100_CLKGATE_D01_EBI (1<<5)
114
115/* PCLKD0 Clock Gate 2 Registers */
116#define S5PC100_CLKGATE_D02_SECKEY (1<<1)
117#define S5PC100_CLKGATE_D02_SDM (1<<2)
118
119/* HCLKD1/PCLKD1 Clock Gate 0 Registers */
120#define S5PC100_CLKGATE_D10_PDMA0 (1<<0)
121#define S5PC100_CLKGATE_D10_PDMA1 (1<<1)
122#define S5PC100_CLKGATE_D10_USBHOST (1<<2)
123#define S5PC100_CLKGATE_D10_USBOTG (1<<3)
124#define S5PC100_CLKGATE_D10_MODEMIF (1<<4)
125#define S5PC100_CLKGATE_D10_HSMMC0 (1<<5)
126#define S5PC100_CLKGATE_D10_HSMMC1 (1<<6)
127#define S5PC100_CLKGATE_D10_HSMMC2 (1<<7)
128
129/* HCLKD1/PCLKD1 Clock Gate 1 Registers */
130#define S5PC100_CLKGATE_D11_LCD (1<<0)
131#define S5PC100_CLKGATE_D11_ROTATOR (1<<1)
132#define S5PC100_CLKGATE_D11_FIMC0 (1<<2)
133#define S5PC100_CLKGATE_D11_FIMC1 (1<<3)
134#define S5PC100_CLKGATE_D11_FIMC2 (1<<4)
135#define S5PC100_CLKGATE_D11_JPEG (1<<5)
136#define S5PC100_CLKGATE_D11_DSI (1<<6)
137#define S5PC100_CLKGATE_D11_CSI (1<<7)
138#define S5PC100_CLKGATE_D11_G3D (1<<8)
139
140/* HCLKD1/PCLKD1 Clock Gate 2 Registers */
141#define S5PC100_CLKGATE_D12_TV (1<<0)
142#define S5PC100_CLKGATE_D12_VP (1<<1)
143#define S5PC100_CLKGATE_D12_MIXER (1<<2)
144#define S5PC100_CLKGATE_D12_HDMI (1<<3)
145#define S5PC100_CLKGATE_D12_MFC (1<<4)
146
147/* HCLKD1/PCLKD1 Clock Gate 3 Registers */
148#define S5PC100_CLKGATE_D13_CHIPID (1<<0)
149#define S5PC100_CLKGATE_D13_GPIO (1<<1)
150#define S5PC100_CLKGATE_D13_APC (1<<2)
151#define S5PC100_CLKGATE_D13_IEC (1<<3)
152#define S5PC100_CLKGATE_D13_PWM (1<<6)
153#define S5PC100_CLKGATE_D13_SYSTIMER (1<<7)
154#define S5PC100_CLKGATE_D13_WDT (1<<8)
155#define S5PC100_CLKGATE_D13_RTC (1<<9)
156
157/* HCLKD1/PCLKD1 Clock Gate 4 Registers */
158#define S5PC100_CLKGATE_D14_UART0 (1<<0)
159#define S5PC100_CLKGATE_D14_UART1 (1<<1)
160#define S5PC100_CLKGATE_D14_UART2 (1<<2)
161#define S5PC100_CLKGATE_D14_UART3 (1<<3)
162#define S5PC100_CLKGATE_D14_IIC (1<<4)
163#define S5PC100_CLKGATE_D14_HDMI_IIC (1<<5)
164#define S5PC100_CLKGATE_D14_SPI0 (1<<6)
165#define S5PC100_CLKGATE_D14_SPI1 (1<<7)
166#define S5PC100_CLKGATE_D14_SPI2 (1<<8)
167#define S5PC100_CLKGATE_D14_IRDA (1<<9)
168#define S5PC100_CLKGATE_D14_CCAN0 (1<<10)
169#define S5PC100_CLKGATE_D14_CCAN1 (1<<11)
170#define S5PC100_CLKGATE_D14_HSITX (1<<12)
171#define S5PC100_CLKGATE_D14_HSIRX (1<<13)
172
173/* HCLKD1/PCLKD1 Clock Gate 5 Registers */
174#define S5PC100_CLKGATE_D15_IIS0 (1<<0)
175#define S5PC100_CLKGATE_D15_IIS1 (1<<1)
176#define S5PC100_CLKGATE_D15_IIS2 (1<<2)
177#define S5PC100_CLKGATE_D15_AC97 (1<<3)
178#define S5PC100_CLKGATE_D15_PCM0 (1<<4)
179#define S5PC100_CLKGATE_D15_PCM1 (1<<5)
180#define S5PC100_CLKGATE_D15_SPDIF (1<<6)
181#define S5PC100_CLKGATE_D15_TSADC (1<<7)
182#define S5PC100_CLKGATE_D15_KEYIF (1<<8)
183#define S5PC100_CLKGATE_D15_CG (1<<9)
184
185/* HCLKD2 Clock Gate 0 Registers */
186#define S5PC100_CLKGATE_D20_HCLKD2 (1<<0)
187#define S5PC100_CLKGATE_D20_I2SD2 (1<<1)
188
189/* Special Clock Gate 0 Registers */
190#define S5PC100_CLKGATE_SCLK0_HPM (1<<0)
191#define S5PC100_CLKGATE_SCLK0_PWI (1<<1)
192#define S5PC100_CLKGATE_SCLK0_ONENAND (1<<2)
193#define S5PC100_CLKGATE_SCLK0_UART (1<<3)
194#define S5PC100_CLKGATE_SCLK0_SPI0 (1<<4)
195#define S5PC100_CLKGATE_SCLK0_SPI1 (1<<5)
196#define S5PC100_CLKGATE_SCLK0_SPI2 (1<<6)
197#define S5PC100_CLKGATE_SCLK0_SPI0_48 (1<<7)
198#define S5PC100_CLKGATE_SCLK0_SPI1_48 (1<<8)
199#define S5PC100_CLKGATE_SCLK0_SPI2_48 (1<<9)
200#define S5PC100_CLKGATE_SCLK0_IRDA (1<<10)
201#define S5PC100_CLKGATE_SCLK0_USBHOST (1<<11)
202#define S5PC100_CLKGATE_SCLK0_MMC0 (1<<12)
203#define S5PC100_CLKGATE_SCLK0_MMC1 (1<<13)
204#define S5PC100_CLKGATE_SCLK0_MMC2 (1<<14)
205#define S5PC100_CLKGATE_SCLK0_MMC0_48 (1<<15)
206#define S5PC100_CLKGATE_SCLK0_MMC1_48 (1<<16)
207#define S5PC100_CLKGATE_SCLK0_MMC2_48 (1<<17)
208
209/* Special Clock Gate 1 Registers */
210#define S5PC100_CLKGATE_SCLK1_LCD (1<<0)
211#define S5PC100_CLKGATE_SCLK1_FIMC0 (1<<1)
212#define S5PC100_CLKGATE_SCLK1_FIMC1 (1<<2)
213#define S5PC100_CLKGATE_SCLK1_FIMC2 (1<<3)
214#define S5PC100_CLKGATE_SCLK1_TV54 (1<<4)
215#define S5PC100_CLKGATE_SCLK1_VDAC54 (1<<5)
216#define S5PC100_CLKGATE_SCLK1_MIXER (1<<6)
217#define S5PC100_CLKGATE_SCLK1_HDMI (1<<7)
218#define S5PC100_CLKGATE_SCLK1_AUDIO0 (1<<8)
219#define S5PC100_CLKGATE_SCLK1_AUDIO1 (1<<9)
220#define S5PC100_CLKGATE_SCLK1_AUDIO2 (1<<10)
221#define S5PC100_CLKGATE_SCLK1_SPDIF (1<<11)
222#define S5PC100_CLKGATE_SCLK1_CAM (1<<12)
223
224#define S5PC100_SWRESET S5PC100_CLKREG_OTHER(0x000)
225#define S5PC100_OND_SWRESET S5PC100_CLKREG_OTHER(0x008)
226#define S5PC100_GEN_CTRL S5PC100_CLKREG_OTHER(0x100)
227#define S5PC100_GEN_STATUS S5PC100_CLKREG_OTHER(0x104)
228#define S5PC100_MEM_SYS_CFG S5PC100_CLKREG_OTHER(0x200)
229#define S5PC100_CAM_MUX_SEL S5PC100_CLKREG_OTHER(0x300)
230#define S5PC100_MIXER_OUT_SEL S5PC100_CLKREG_OTHER(0x304)
231#define S5PC100_LPMP_MODE_SEL S5PC100_CLKREG_OTHER(0x308)
232#define S5PC100_MIPI_PHY_CON0 S5PC100_CLKREG_OTHER(0x400)
233#define S5PC100_MIPI_PHY_CON1 S5PC100_CLKREG_OTHER(0x414)
234#define S5PC100_HDMI_PHY_CON0 S5PC100_CLKREG_OTHER(0x420)
235
236#define S5PC100_SWRESET_RESETVAL 0xc100
237#define S5PC100_OTHER_SYS_INT 24
238#define S5PC100_OTHER_STA_TYPE 23
239#define STA_TYPE_EXPON 0
240#define STA_TYPE_SFR 1
241
242#define S5PC100_SLEEP_CFG_OSC_EN 0
243
244/* OTHERS Resgister */
245#define S5PC100_OTHERS_USB_SIG_MASK (1 << 16)
246#define S5PC100_OTHERS_MIPI_DPHY_EN (1 << 28)
247
248/* MIPI D-PHY Control Register 0 */
249#define S5PC100_MIPI_PHY_CON0_M_RESETN (1 << 1)
250#define S5PC100_MIPI_PHY_CON0_S_RESETN (1 << 0)
251
252#endif /* _PLAT_REGS_CLOCK_H */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-power.h b/arch/arm/plat-s5pc1xx/include/plat/regs-power.h
deleted file mode 100644
index 02ffa491b53a..000000000000
--- a/arch/arm/plat-s5pc1xx/include/plat/regs-power.h
+++ /dev/null
@@ -1,84 +0,0 @@
1/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Jongse Won <jongse.won@samsung.com>
5 *
6 * S5PC1XX clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARM_REGS_PWR
14#define __ASM_ARM_REGS_PWR __FILE__
15
16#define S5PC1XX_PWRREG(x) (S5PC1XX_VA_PWR + (x))
17
18/* s5pc100 (0xE0108000) register for power management */
19#define S5PC100_PWR_CFG S5PC1XX_PWRREG(0x0)
20#define S5PC100_EINT_WAKEUP_MASK S5PC1XX_PWRREG(0x4)
21#define S5PC100_NORMAL_CFG S5PC1XX_PWRREG(0x10)
22#define S5PC100_STOP_CFG S5PC1XX_PWRREG(0x14)
23#define S5PC100_SLEEP_CFG S5PC1XX_PWRREG(0x18)
24#define S5PC100_STOP_MEM_CFG S5PC1XX_PWRREG(0x1C)
25#define S5PC100_OSC_FREQ S5PC1XX_PWRREG(0x100)
26#define S5PC100_OSC_STABLE S5PC1XX_PWRREG(0x104)
27#define S5PC100_PWR_STABLE S5PC1XX_PWRREG(0x108)
28#define S5PC100_MTC_STABLE S5PC1XX_PWRREG(0x110)
29#define S5PC100_CLAMP_STABLE S5PC1XX_PWRREG(0x114)
30#define S5PC100_OTHERS S5PC1XX_PWRREG(0x200)
31#define S5PC100_RST_STAT S5PC1XX_PWRREG(0x300)
32#define S5PC100_WAKEUP_STAT S5PC1XX_PWRREG(0x304)
33#define S5PC100_BLK_PWR_STAT S5PC1XX_PWRREG(0x308)
34#define S5PC100_INFORM0 S5PC1XX_PWRREG(0x400)
35#define S5PC100_INFORM1 S5PC1XX_PWRREG(0x404)
36#define S5PC100_INFORM2 S5PC1XX_PWRREG(0x408)
37#define S5PC100_INFORM3 S5PC1XX_PWRREG(0x40C)
38#define S5PC100_INFORM4 S5PC1XX_PWRREG(0x410)
39#define S5PC100_INFORM5 S5PC1XX_PWRREG(0x414)
40#define S5PC100_INFORM6 S5PC1XX_PWRREG(0x418)
41#define S5PC100_INFORM7 S5PC1XX_PWRREG(0x41C)
42#define S5PC100_DCGIDX_MAP0 S5PC1XX_PWRREG(0x500)
43#define S5PC100_DCGIDX_MAP1 S5PC1XX_PWRREG(0x504)
44#define S5PC100_DCGIDX_MAP2 S5PC1XX_PWRREG(0x508)
45#define S5PC100_DCGPERF_MAP0 S5PC1XX_PWRREG(0x50C)
46#define S5PC100_DCGPERF_MAP1 S5PC1XX_PWRREG(0x510)
47#define S5PC100_DVCIDX_MAP S5PC1XX_PWRREG(0x514)
48#define S5PC100_FREQ_CPU S5PC1XX_PWRREG(0x518)
49#define S5PC100_FREQ_DPM S5PC1XX_PWRREG(0x51C)
50#define S5PC100_DVSEMCLK_EN S5PC1XX_PWRREG(0x520)
51#define S5PC100_APLL_CON_L8 S5PC1XX_PWRREG(0x600)
52#define S5PC100_APLL_CON_L7 S5PC1XX_PWRREG(0x604)
53#define S5PC100_APLL_CON_L6 S5PC1XX_PWRREG(0x608)
54#define S5PC100_APLL_CON_L5 S5PC1XX_PWRREG(0x60C)
55#define S5PC100_APLL_CON_L4 S5PC1XX_PWRREG(0x610)
56#define S5PC100_APLL_CON_L3 S5PC1XX_PWRREG(0x614)
57#define S5PC100_APLL_CON_L2 S5PC1XX_PWRREG(0x618)
58#define S5PC100_APLL_CON_L1 S5PC1XX_PWRREG(0x61C)
59#define S5PC100_IEM_CONTROL S5PC1XX_PWRREG(0x620)
60#define S5PC100_CLKDIV_IEM_L8 S5PC1XX_PWRREG(0x700)
61#define S5PC100_CLKDIV_IEM_L7 S5PC1XX_PWRREG(0x704)
62#define S5PC100_CLKDIV_IEM_L6 S5PC1XX_PWRREG(0x708)
63#define S5PC100_CLKDIV_IEM_L5 S5PC1XX_PWRREG(0x70C)
64#define S5PC100_CLKDIV_IEM_L4 S5PC1XX_PWRREG(0x710)
65#define S5PC100_CLKDIV_IEM_L3 S5PC1XX_PWRREG(0x714)
66#define S5PC100_CLKDIV_IEM_L2 S5PC1XX_PWRREG(0x718)
67#define S5PC100_CLKDIV_IEM_L1 S5PC1XX_PWRREG(0x71C)
68#define S5PC100_IEM_HPMCLK_DIV S5PC1XX_PWRREG(0x724)
69
70/* PWR_CFG */
71#define S5PC100_PWRCFG_CFG_DEEP_IDLE (1 << 31)
72#define S5PC100_PWRCFG_CFG_WFI_MASK (3 << 5)
73#define S5PC100_PWRCFG_CFG_WFI_IDLE (0 << 5)
74#define S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE (1 << 5)
75#define S5PC100_PWRCFG_CFG_WFI_STOP (2 << 5)
76#define S5PC100_PWRCFG_CFG_WFI_SLEEP (3 << 5)
77
78/* SLEEP_CFG */
79#define S5PC100_SLEEP_OSC_EN_SLEEP (1 << 0)
80
81/* OTHERS */
82#define S5PC100_PMU_INT_DISABLE (1 << 24)
83
84#endif /* __ASM_ARM_REGS_PWR */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
deleted file mode 100644
index 2531f34a56f3..000000000000
--- a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/* arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * Header file for s5pc100 cpu support
7 *
8 * Based on plat-s3c64xx/include/plat/s3c6400.h
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* Common init code for S5PC100 related SoCs */
16extern int s5pc100_init(void);
17extern void s5pc100_map_io(void);
18extern void s5pc100_init_clocks(int xtal);
19extern int s5pc100_register_baseclocks(unsigned long xtal);
20extern void s5pc100_init_irq(void);
21extern void s5pc100_init_io(struct map_desc *mach_desc, int size);
22extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
23extern void s5pc100_register_clocks(void);
24extern void s5pc100_setup_clocks(void);
25extern struct sysdev_class s5pc100_sysclass;
26
27#define s5pc100_init_uarts s5pc100_common_init_uarts
28
29/* Some day, belows will be moved to plat-s5pc/include/plat/cpu.h */
30extern void s5pc1xx_init_irq(u32 *vic_valid, int num);
31extern void s5pc1xx_init_io(struct map_desc *mach_desc, int size);
32
33/* Some day, belows will be moved to plat-s5pc/include/plat/clock.h */
34extern struct clk clk_hpll;
35extern struct clk clk_hd0;
36extern struct clk clk_pd0;
37extern struct clk clk_54m;
38extern void s5pc1xx_register_clocks(void);
39extern int s5pc100_sclk0_ctrl(struct clk *clk, int enable);
40extern int s5pc100_sclk1_ctrl(struct clk *clk, int enable);
41
42/* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */
43extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[];
44extern struct platform_device s3c_device_g2d;
45extern struct platform_device s3c_device_g3d;
46extern struct platform_device s3c_device_vpp;
47extern struct platform_device s3c_device_tvenc;
48extern struct platform_device s3c_device_tvscaler;
49extern struct platform_device s3c_device_rotator;
50extern struct platform_device s3c_device_jpeg;
51extern struct platform_device s3c_device_onenand;
52extern struct platform_device s3c_device_usb_otghcd;
53extern struct platform_device s3c_device_keypad;
54extern struct platform_device s3c_device_ts;
55extern struct platform_device s3c_device_g3d;
56extern struct platform_device s3c_device_smc911x;
57extern struct platform_device s3c_device_fimc0;
58extern struct platform_device s3c_device_fimc1;
59extern struct platform_device s3c_device_mfc;
60extern struct platform_device s3c_device_ac97;
61extern struct platform_device s3c_device_fimc0;
62extern struct platform_device s3c_device_fimc1;
63extern struct platform_device s3c_device_fimc2;
64
diff --git a/arch/arm/plat-s5pc1xx/irq-eint.c b/arch/arm/plat-s5pc1xx/irq-eint.c
deleted file mode 100644
index 373122f57d56..000000000000
--- a/arch/arm/plat-s5pc1xx/irq-eint.c
+++ /dev/null
@@ -1,281 +0,0 @@
1/*
2 * linux/arch/arm/plat-s5pc1xx/irq-eint.c
3 *
4 * Copyright 2009 Samsung Electronics Co.
5 * Byungho Min <bhmin@samsung.com>
6 * Kyungin Park <kyungmin.park@samsung.com>
7 *
8 * Based on plat-s3c64xx/irq-eint.c
9 *
10 * S5PC1XX - Interrupt handling for IRQ_EINT(x)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/kernel.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/io.h>
21#include <linux/sysdev.h>
22#include <linux/pm.h>
23#include <linux/gpio.h>
24
25#include <asm/hardware/vic.h>
26
27#include <mach/map.h>
28
29#include <plat/gpio-cfg.h>
30#include <plat/gpio-ext.h>
31#include <plat/pm.h>
32#include <plat/regs-gpio.h>
33#include <plat/regs-irqtype.h>
34
35/*
36 * bank is a group of external interrupt
37 * bank0 means EINT0 ... EINT7
38 * bank1 means EINT8 ... EINT15
39 * bank2 means EINT16 ... EINT23
40 * bank3 means EINT24 ... EINT31
41 */
42
43static inline int s3c_get_eint(unsigned int irq)
44{
45 int real;
46
47 if (irq < IRQ_EINT16_31)
48 real = (irq - IRQ_EINT0);
49 else
50 real = (irq - S3C_IRQ_EINT_BASE) + IRQ_EINT16_31 - IRQ_EINT0;
51
52 return real;
53}
54
55static inline int s3c_get_bank(unsigned int irq)
56{
57 return s3c_get_eint(irq) >> 3;
58}
59
60static inline int s3c_eint_to_bit(unsigned int irq)
61{
62 int real, bit;
63
64 real = s3c_get_eint(irq);
65 bit = 1 << (real & (8 - 1));
66
67 return bit;
68}
69
70static inline void s3c_irq_eint_mask(unsigned int irq)
71{
72 u32 mask;
73 u32 bank = s3c_get_bank(irq);
74
75 mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank));
76 mask |= s3c_eint_to_bit(irq);
77 __raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank));
78}
79
80static void s3c_irq_eint_unmask(unsigned int irq)
81{
82 u32 mask;
83 u32 bank = s3c_get_bank(irq);
84
85 mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank));
86 mask &= ~(s3c_eint_to_bit(irq));
87 __raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank));
88}
89
90static inline void s3c_irq_eint_ack(unsigned int irq)
91{
92 u32 bank = s3c_get_bank(irq);
93
94 __raw_writel(s3c_eint_to_bit(irq), S5PC1XX_WKUP_INT_PEND(bank));
95}
96
97static void s3c_irq_eint_maskack(unsigned int irq)
98{
99 /* compiler should in-line these */
100 s3c_irq_eint_mask(irq);
101 s3c_irq_eint_ack(irq);
102}
103
104static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
105{
106 u32 bank = s3c_get_bank(irq);
107 int real = s3c_get_eint(irq);
108 int gpio, shift, sfn;
109 u32 ctrl, con = 0;
110
111 switch (type) {
112 case IRQ_TYPE_NONE:
113 printk(KERN_WARNING "No edge setting!\n");
114 break;
115
116 case IRQ_TYPE_EDGE_RISING:
117 con = S5PC1XX_WKUP_INT_RISEEDGE;
118 break;
119
120 case IRQ_TYPE_EDGE_FALLING:
121 con = S5PC1XX_WKUP_INT_FALLEDGE;
122 break;
123
124 case IRQ_TYPE_EDGE_BOTH:
125 con = S5PC1XX_WKUP_INT_BOTHEDGE;
126 break;
127
128 case IRQ_TYPE_LEVEL_LOW:
129 con = S5PC1XX_WKUP_INT_LOWLEV;
130 break;
131
132 case IRQ_TYPE_LEVEL_HIGH:
133 con = S5PC1XX_WKUP_INT_HILEV;
134 break;
135
136 default:
137 printk(KERN_ERR "No such irq type %d", type);
138 return -EINVAL;
139 }
140
141 gpio = real & (8 - 1);
142 shift = gpio << 2;
143
144 ctrl = __raw_readl(S5PC1XX_WKUP_INT_CON(bank));
145 ctrl &= ~(0x7 << shift);
146 ctrl |= con << shift;
147 __raw_writel(ctrl, S5PC1XX_WKUP_INT_CON(bank));
148
149 switch (real) {
150 case 0 ... 7:
151 gpio = S5PC100_GPH0(gpio);
152 break;
153 case 8 ... 15:
154 gpio = S5PC100_GPH1(gpio);
155 break;
156 case 16 ... 23:
157 gpio = S5PC100_GPH2(gpio);
158 break;
159 case 24 ... 31:
160 gpio = S5PC100_GPH3(gpio);
161 break;
162 default:
163 return -EINVAL;
164 }
165
166 sfn = S3C_GPIO_SFN(0x2);
167 s3c_gpio_cfgpin(gpio, sfn);
168
169 return 0;
170}
171
172static struct irq_chip s3c_irq_eint = {
173 .name = "EINT",
174 .mask = s3c_irq_eint_mask,
175 .unmask = s3c_irq_eint_unmask,
176 .mask_ack = s3c_irq_eint_maskack,
177 .ack = s3c_irq_eint_ack,
178 .set_type = s3c_irq_eint_set_type,
179 .set_wake = s3c_irqext_wake,
180};
181
182/* s3c_irq_demux_eint
183 *
184 * This function demuxes the IRQ from external interrupts,
185 * from IRQ_EINT(16) to IRQ_EINT(31). It is designed to be inlined into
186 * the specific handlers s3c_irq_demux_eintX_Y.
187 */
188static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
189{
190 u32 status = __raw_readl(S5PC1XX_WKUP_INT_PEND((start >> 3)));
191 u32 mask = __raw_readl(S5PC1XX_WKUP_INT_MASK((start >> 3)));
192 unsigned int irq;
193
194 status &= ~mask;
195 status &= (1 << (end - start + 1)) - 1;
196
197 for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
198 if (status & 1)
199 generic_handle_irq(irq);
200
201 status >>= 1;
202 }
203}
204
205static void s3c_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
206{
207 s3c_irq_demux_eint(16, 23);
208 s3c_irq_demux_eint(24, 31);
209}
210
211/*
212 * Handle EINT0 ... EINT15 at VIC directly
213 */
214static void s3c_irq_vic_eint_mask(unsigned int irq)
215{
216 void __iomem *base = get_irq_chip_data(irq);
217 unsigned int real;
218
219 s3c_irq_eint_mask(irq);
220 real = s3c_get_eint(irq);
221 writel(1 << real, base + VIC_INT_ENABLE_CLEAR);
222}
223
224static void s3c_irq_vic_eint_unmask(unsigned int irq)
225{
226 void __iomem *base = get_irq_chip_data(irq);
227 unsigned int real;
228
229 s3c_irq_eint_unmask(irq);
230 real = s3c_get_eint(irq);
231 writel(1 << real, base + VIC_INT_ENABLE);
232}
233
234static inline void s3c_irq_vic_eint_ack(unsigned int irq)
235{
236 u32 bit;
237 u32 bank = s3c_get_bank(irq);
238
239 bit = s3c_eint_to_bit(irq);
240 __raw_writel(bit, S5PC1XX_WKUP_INT_PEND(bank));
241}
242
243static void s3c_irq_vic_eint_maskack(unsigned int irq)
244{
245 /* compiler should in-line these */
246 s3c_irq_vic_eint_mask(irq);
247 s3c_irq_vic_eint_ack(irq);
248}
249
250static struct irq_chip s3c_irq_vic_eint = {
251 .name = "EINT",
252 .mask = s3c_irq_vic_eint_mask,
253 .unmask = s3c_irq_vic_eint_unmask,
254 .mask_ack = s3c_irq_vic_eint_maskack,
255 .ack = s3c_irq_vic_eint_ack,
256 .set_type = s3c_irq_eint_set_type,
257 .set_wake = s3c_irqext_wake,
258};
259
260static int __init s5pc1xx_init_irq_eint(void)
261{
262 int irq;
263
264 for (irq = IRQ_EINT0; irq <= IRQ_EINT15; irq++) {
265 set_irq_chip(irq, &s3c_irq_vic_eint);
266 set_irq_handler(irq, handle_level_irq);
267 set_irq_flags(irq, IRQF_VALID);
268 }
269
270 for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
271 set_irq_chip(irq, &s3c_irq_eint);
272 set_irq_handler(irq, handle_level_irq);
273 set_irq_flags(irq, IRQF_VALID);
274 }
275
276 set_irq_chained_handler(IRQ_EINT16_31, s3c_irq_demux_eint16_31);
277
278 return 0;
279}
280
281arch_initcall(s5pc1xx_init_irq_eint);
diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c
deleted file mode 100644
index bfc524827819..000000000000
--- a/arch/arm/plat-s5pc1xx/irq.c
+++ /dev/null
@@ -1,75 +0,0 @@
1/* arch/arm/plat-s5pc1xx/irq.c
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC1XX - Interrupt handling
7 *
8 * Based on plat-s3c64xx/irq.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/io.h>
19
20#include <asm/hardware/vic.h>
21
22#include <mach/map.h>
23#include <plat/irq-vic-timer.h>
24#include <plat/irq-uart.h>
25#include <plat/cpu.h>
26
27/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
28 * are consecutive when looking up the interrupt in the demux routines.
29 */
30static struct s3c_uart_irq uart_irqs[] = {
31 [0] = {
32 .regs = (void *)S3C_VA_UART0,
33 .base_irq = IRQ_S3CUART_BASE0,
34 .parent_irq = IRQ_UART0,
35 },
36 [1] = {
37 .regs = (void *)S3C_VA_UART1,
38 .base_irq = IRQ_S3CUART_BASE1,
39 .parent_irq = IRQ_UART1,
40 },
41 [2] = {
42 .regs = (void *)S3C_VA_UART2,
43 .base_irq = IRQ_S3CUART_BASE2,
44 .parent_irq = IRQ_UART2,
45 },
46 [3] = {
47 .regs = (void *)S3C_VA_UART3,
48 .base_irq = IRQ_S3CUART_BASE3,
49 .parent_irq = IRQ_UART3,
50 },
51};
52
53void __init s5pc1xx_init_irq(u32 *vic_valid, int num)
54{
55 int i;
56
57 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
58
59 /* initialise the pair of VICs */
60 for (i = 0; i < num; i++)
61 vic_init((void *)S5PC1XX_VA_VIC(i), S3C_IRQ(i * S3C_IRQ_OFFSET),
62 vic_valid[i], 0);
63
64 /* add the timer sub-irqs */
65
66 s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
67 s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
68 s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
69 s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
70 s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
71
72 s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
73}
74
75
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
deleted file mode 100644
index 2bf6c57a96a2..000000000000
--- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c
+++ /dev/null
@@ -1,876 +0,0 @@
1/* linux/arch/arm/plat-s5pc1xx/s5pc100-clock.c
2 *
3 * Copyright 2009 Samsung Electronics, Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC100 based common clock support
7 *
8 * Based on plat-s3c64xx/s3c6400-clock.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/errno.h>
20#include <linux/err.h>
21#include <linux/clk.h>
22#include <linux/sysdev.h>
23#include <linux/io.h>
24
25#include <mach/hardware.h>
26#include <mach/map.h>
27
28#include <plat/cpu-freq.h>
29
30#include <plat/regs-clock.h>
31#include <plat/clock.h>
32#include <plat/clock-clksrc.h>
33#include <plat/cpu.h>
34#include <plat/pll.h>
35#include <plat/devs.h>
36#include <plat/s5pc100.h>
37
38/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
39 * ext_xtal_mux for want of an actual name from the manual.
40*/
41
42static struct clk clk_ext_xtal_mux = {
43 .name = "ext_xtal",
44 .id = -1,
45};
46
47#define clk_fin_apll clk_ext_xtal_mux
48#define clk_fin_mpll clk_ext_xtal_mux
49#define clk_fin_epll clk_ext_xtal_mux
50#define clk_fin_hpll clk_ext_xtal_mux
51
52#define clk_fout_mpll clk_mpll
53#define clk_vclk_54m clk_54m
54
55/* APLL */
56static struct clk clk_fout_apll = {
57 .name = "fout_apll",
58 .id = -1,
59 .rate = 27000000,
60};
61
62static struct clk *clk_src_apll_list[] = {
63 [0] = &clk_fin_apll,
64 [1] = &clk_fout_apll,
65};
66
67static struct clksrc_sources clk_src_apll = {
68 .sources = clk_src_apll_list,
69 .nr_sources = ARRAY_SIZE(clk_src_apll_list),
70};
71
72static struct clksrc_clk clk_mout_apll = {
73 .clk = {
74 .name = "mout_apll",
75 .id = -1,
76 },
77 .sources = &clk_src_apll,
78 .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 0, .size = 1, },
79};
80
81static unsigned long s5pc100_clk_dout_apll_get_rate(struct clk *clk)
82{
83 unsigned long rate = clk_get_rate(clk->parent);
84 unsigned int ratio;
85
86 ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_APLL_MASK;
87 ratio >>= S5PC100_CLKDIV0_APLL_SHIFT;
88
89 return rate / (ratio + 1);
90}
91
92static struct clk clk_dout_apll = {
93 .name = "dout_apll",
94 .id = -1,
95 .parent = &clk_mout_apll.clk,
96 .ops = &(struct clk_ops) {
97 .get_rate = s5pc100_clk_dout_apll_get_rate,
98 },
99};
100
101static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk)
102{
103 unsigned long rate = clk_get_rate(clk->parent);
104 unsigned int ratio;
105
106 ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_ARM_MASK;
107 ratio >>= S5PC100_CLKDIV0_ARM_SHIFT;
108
109 return rate / (ratio + 1);
110}
111
112static unsigned long s5pc100_clk_arm_round_rate(struct clk *clk,
113 unsigned long rate)
114{
115 unsigned long parent = clk_get_rate(clk->parent);
116 u32 div;
117
118 if (parent < rate)
119 return rate;
120
121 div = (parent / rate) - 1;
122 if (div > S5PC100_CLKDIV0_ARM_MASK)
123 div = S5PC100_CLKDIV0_ARM_MASK;
124
125 return parent / (div + 1);
126}
127
128static int s5pc100_clk_arm_set_rate(struct clk *clk, unsigned long rate)
129{
130 unsigned long parent = clk_get_rate(clk->parent);
131 u32 div;
132 u32 val;
133
134 if (rate < parent / (S5PC100_CLKDIV0_ARM_MASK + 1))
135 return -EINVAL;
136
137 rate = clk_round_rate(clk, rate);
138 div = clk_get_rate(clk->parent) / rate;
139
140 val = __raw_readl(S5PC100_CLKDIV0);
141 val &= S5PC100_CLKDIV0_ARM_MASK;
142 val |= (div - 1);
143 __raw_writel(val, S5PC100_CLKDIV0);
144
145 return 0;
146}
147
148static struct clk clk_arm = {
149 .name = "armclk",
150 .id = -1,
151 .parent = &clk_dout_apll,
152 .ops = &(struct clk_ops) {
153 .get_rate = s5pc100_clk_arm_get_rate,
154 .set_rate = s5pc100_clk_arm_set_rate,
155 .round_rate = s5pc100_clk_arm_round_rate,
156 },
157};
158
159static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk)
160{
161 unsigned long rate = clk_get_rate(clk->parent);
162 unsigned int ratio;
163
164 ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_D0_MASK;
165 ratio >>= S5PC100_CLKDIV0_D0_SHIFT;
166
167 return rate / (ratio + 1);
168}
169
170static struct clk clk_dout_d0_bus = {
171 .name = "dout_d0_bus",
172 .id = -1,
173 .parent = &clk_arm,
174 .ops = &(struct clk_ops) {
175 .get_rate = s5pc100_clk_dout_d0_bus_get_rate,
176 },
177};
178
179static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk)
180{
181 unsigned long rate = clk_get_rate(clk->parent);
182 unsigned int ratio;
183
184 ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_PCLKD0_MASK;
185 ratio >>= S5PC100_CLKDIV0_PCLKD0_SHIFT;
186
187 return rate / (ratio + 1);
188}
189
190static struct clk clk_dout_pclkd0 = {
191 .name = "dout_pclkd0",
192 .id = -1,
193 .parent = &clk_dout_d0_bus,
194 .ops = &(struct clk_ops) {
195 .get_rate = s5pc100_clk_dout_pclkd0_get_rate,
196 },
197};
198
199static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk)
200{
201 unsigned long rate = clk_get_rate(clk->parent);
202 unsigned int ratio;
203
204 ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_APLL2_MASK;
205 ratio >>= S5PC100_CLKDIV1_APLL2_SHIFT;
206
207 return rate / (ratio + 1);
208}
209
210static struct clk clk_dout_apll2 = {
211 .name = "dout_apll2",
212 .id = -1,
213 .parent = &clk_mout_apll.clk,
214 .ops = &(struct clk_ops) {
215 .get_rate = s5pc100_clk_dout_apll2_get_rate,
216 },
217};
218
219/* MPLL */
220static struct clk *clk_src_mpll_list[] = {
221 [0] = &clk_fin_mpll,
222 [1] = &clk_fout_mpll,
223};
224
225static struct clksrc_sources clk_src_mpll = {
226 .sources = clk_src_mpll_list,
227 .nr_sources = ARRAY_SIZE(clk_src_mpll_list),
228};
229
230static struct clksrc_clk clk_mout_mpll = {
231 .clk = {
232 .name = "mout_mpll",
233 .id = -1,
234 },
235 .sources = &clk_src_mpll,
236 .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 4, .size = 1, },
237};
238
239static struct clk *clkset_am_list[] = {
240 [0] = &clk_mout_mpll.clk,
241 [1] = &clk_dout_apll2,
242};
243
244static struct clksrc_sources clk_src_am = {
245 .sources = clkset_am_list,
246 .nr_sources = ARRAY_SIZE(clkset_am_list),
247};
248
249static struct clksrc_clk clk_mout_am = {
250 .clk = {
251 .name = "mout_am",
252 .id = -1,
253 },
254 .sources = &clk_src_am,
255 .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 16, .size = 1, },
256};
257
258static unsigned long s5pc100_clk_dout_d1_bus_get_rate(struct clk *clk)
259{
260 unsigned long rate = clk_get_rate(clk->parent);
261 unsigned int ratio;
262
263 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
264
265 ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_D1_MASK;
266 ratio >>= S5PC100_CLKDIV1_D1_SHIFT;
267
268 return rate / (ratio + 1);
269}
270
271static struct clk clk_dout_d1_bus = {
272 .name = "dout_d1_bus",
273 .id = -1,
274 .parent = &clk_mout_am.clk,
275 .ops = &(struct clk_ops) {
276 .get_rate = s5pc100_clk_dout_d1_bus_get_rate,
277 },
278};
279
280static struct clk *clkset_onenand_list[] = {
281 [0] = &clk_dout_d0_bus,
282 [1] = &clk_dout_d1_bus,
283};
284
285static struct clksrc_sources clk_src_onenand = {
286 .sources = clkset_onenand_list,
287 .nr_sources = ARRAY_SIZE(clkset_onenand_list),
288};
289
290static struct clksrc_clk clk_mout_onenand = {
291 .clk = {
292 .name = "mout_onenand",
293 .id = -1,
294 },
295 .sources = &clk_src_onenand,
296 .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 24, .size = 1, },
297};
298
299static unsigned long s5pc100_clk_dout_pclkd1_get_rate(struct clk *clk)
300{
301 unsigned long rate = clk_get_rate(clk->parent);
302 unsigned int ratio;
303
304 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
305
306 ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_PCLKD1_MASK;
307 ratio >>= S5PC100_CLKDIV1_PCLKD1_SHIFT;
308
309 return rate / (ratio + 1);
310}
311
312static struct clk clk_dout_pclkd1 = {
313 .name = "dout_pclkd1",
314 .id = -1,
315 .parent = &clk_dout_d1_bus,
316 .ops = &(struct clk_ops) {
317 .get_rate = s5pc100_clk_dout_pclkd1_get_rate,
318 },
319};
320
321static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk)
322{
323 unsigned long rate = clk_get_rate(clk->parent);
324 unsigned int ratio;
325
326 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
327
328 ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL2_MASK;
329 ratio >>= S5PC100_CLKDIV1_MPLL2_SHIFT;
330
331 return rate / (ratio + 1);
332}
333
334static struct clk clk_dout_mpll2 = {
335 .name = "dout_mpll2",
336 .id = -1,
337 .parent = &clk_mout_am.clk,
338 .ops = &(struct clk_ops) {
339 .get_rate = s5pc100_clk_dout_mpll2_get_rate,
340 },
341};
342
343static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk)
344{
345 unsigned long rate = clk_get_rate(clk->parent);
346 unsigned int ratio;
347
348 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
349
350 ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_CAM_MASK;
351 ratio >>= S5PC100_CLKDIV1_CAM_SHIFT;
352
353 return rate / (ratio + 1);
354}
355
356static struct clk clk_dout_cam = {
357 .name = "dout_cam",
358 .id = -1,
359 .parent = &clk_dout_mpll2,
360 .ops = &(struct clk_ops) {
361 .get_rate = s5pc100_clk_dout_cam_get_rate,
362 },
363};
364
365static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk)
366{
367 unsigned long rate = clk_get_rate(clk->parent);
368 unsigned int ratio;
369
370 printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
371
372 ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL_MASK;
373 ratio >>= S5PC100_CLKDIV1_MPLL_SHIFT;
374
375 return rate / (ratio + 1);
376}
377
378static struct clk clk_dout_mpll = {
379 .name = "dout_mpll",
380 .id = -1,
381 .parent = &clk_mout_am.clk,
382 .ops = &(struct clk_ops) {
383 .get_rate = s5pc100_clk_dout_mpll_get_rate,
384 },
385};
386
387/* EPLL */
388static struct clk clk_fout_epll = {
389 .name = "fout_epll",
390 .id = -1,
391};
392
393static struct clk *clk_src_epll_list[] = {
394 [0] = &clk_fin_epll,
395 [1] = &clk_fout_epll,
396};
397
398static struct clksrc_sources clk_src_epll = {
399 .sources = clk_src_epll_list,
400 .nr_sources = ARRAY_SIZE(clk_src_epll_list),
401};
402
403static struct clksrc_clk clk_mout_epll = {
404 .clk = {
405 .name = "mout_epll",
406 .id = -1,
407 },
408 .sources = &clk_src_epll,
409 .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 8, .size = 1, },
410};
411
412/* HPLL */
413static struct clk clk_fout_hpll = {
414 .name = "fout_hpll",
415 .id = -1,
416};
417
418static struct clk *clk_src_hpll_list[] = {
419 [0] = &clk_27m,
420 [1] = &clk_fout_hpll,
421};
422
423static struct clksrc_sources clk_src_hpll = {
424 .sources = clk_src_hpll_list,
425 .nr_sources = ARRAY_SIZE(clk_src_hpll_list),
426};
427
428static struct clksrc_clk clk_mout_hpll = {
429 .clk = {
430 .name = "mout_hpll",
431 .id = -1,
432 },
433 .sources = &clk_src_hpll,
434 .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 12, .size = 1, },
435};
436
437/* Peripherals */
438/*
439 * The peripheral clocks are all controlled via clocksource followed
440 * by an optional divider and gate stage. We currently roll this into
441 * one clock which hides the intermediate clock from the mux.
442 *
443 * Note, the JPEG clock can only be an even divider...
444 *
445 * The scaler and LCD clocks depend on the S5PC100 version, and also
446 * have a common parent divisor so are not included here.
447 */
448
449static struct clk clk_iis_cd0 = {
450 .name = "iis_cdclk0",
451 .id = -1,
452};
453
454static struct clk clk_iis_cd1 = {
455 .name = "iis_cdclk1",
456 .id = -1,
457};
458
459static struct clk clk_iis_cd2 = {
460 .name = "iis_cdclk2",
461 .id = -1,
462};
463
464static struct clk clk_pcm_cd0 = {
465 .name = "pcm_cdclk0",
466 .id = -1,
467};
468
469static struct clk clk_pcm_cd1 = {
470 .name = "pcm_cdclk1",
471 .id = -1,
472};
473
474static struct clk *clkset_audio0_list[] = {
475 &clk_mout_epll.clk,
476 &clk_dout_mpll,
477 &clk_fin_epll,
478 &clk_iis_cd0,
479 &clk_pcm_cd0,
480 &clk_mout_hpll.clk,
481};
482
483static struct clksrc_sources clkset_audio0 = {
484 .sources = clkset_audio0_list,
485 .nr_sources = ARRAY_SIZE(clkset_audio0_list),
486};
487
488static struct clk *clkset_spi_list[] = {
489 &clk_mout_epll.clk,
490 &clk_dout_mpll2,
491 &clk_fin_epll,
492 &clk_mout_hpll.clk,
493};
494
495static struct clksrc_sources clkset_spi = {
496 .sources = clkset_spi_list,
497 .nr_sources = ARRAY_SIZE(clkset_spi_list),
498};
499
500static struct clk *clkset_uart_list[] = {
501 &clk_mout_epll.clk,
502 &clk_dout_mpll,
503};
504
505static struct clksrc_sources clkset_uart = {
506 .sources = clkset_uart_list,
507 .nr_sources = ARRAY_SIZE(clkset_uart_list),
508};
509
510static struct clk *clkset_audio1_list[] = {
511 &clk_mout_epll.clk,
512 &clk_dout_mpll,
513 &clk_fin_epll,
514 &clk_iis_cd1,
515 &clk_pcm_cd1,
516 &clk_mout_hpll.clk,
517};
518
519static struct clksrc_sources clkset_audio1 = {
520 .sources = clkset_audio1_list,
521 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
522};
523
524static struct clk *clkset_audio2_list[] = {
525 &clk_mout_epll.clk,
526 &clk_dout_mpll,
527 &clk_fin_epll,
528 &clk_iis_cd2,
529 &clk_mout_hpll.clk,
530};
531
532static struct clksrc_sources clkset_audio2 = {
533 .sources = clkset_audio2_list,
534 .nr_sources = ARRAY_SIZE(clkset_audio2_list),
535};
536
537static struct clksrc_clk clksrc_audio[] = {
538 {
539 .clk = {
540 .name = "audio-bus",
541 .id = 0,
542 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0,
543 .enable = s5pc100_sclk1_ctrl,
544 },
545 .sources = &clkset_audio0,
546 .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 12, .size = 4, },
547 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 12, .size = 3, },
548 }, {
549 .clk = {
550 .name = "audio-bus",
551 .id = 1,
552 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1,
553 .enable = s5pc100_sclk1_ctrl,
554 },
555 .sources = &clkset_audio1,
556 .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 16, .size = 4, },
557 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 16, .size = 3, },
558 }, {
559 .clk = {
560 .name = "audio-bus",
561 .id = 2,
562 .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2,
563 .enable = s5pc100_sclk1_ctrl,
564 },
565 .sources = &clkset_audio2,
566 .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 20, .size = 4, },
567 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 20, .size = 3, },
568 },
569};
570
571static struct clk *clkset_spdif_list[] = {
572 &clksrc_audio[0].clk,
573 &clksrc_audio[1].clk,
574 &clksrc_audio[2].clk,
575};
576
577static struct clksrc_sources clkset_spdif = {
578 .sources = clkset_spdif_list,
579 .nr_sources = ARRAY_SIZE(clkset_spdif_list),
580};
581
582static struct clk *clkset_lcd_fimc_list[] = {
583 &clk_mout_epll.clk,
584 &clk_dout_mpll,
585 &clk_mout_hpll.clk,
586 &clk_vclk_54m,
587};
588
589static struct clksrc_sources clkset_lcd_fimc = {
590 .sources = clkset_lcd_fimc_list,
591 .nr_sources = ARRAY_SIZE(clkset_lcd_fimc_list),
592};
593
594static struct clk *clkset_mmc_list[] = {
595 &clk_mout_epll.clk,
596 &clk_dout_mpll,
597 &clk_fin_epll,
598 &clk_mout_hpll.clk ,
599};
600
601static struct clksrc_sources clkset_mmc = {
602 .sources = clkset_mmc_list,
603 .nr_sources = ARRAY_SIZE(clkset_mmc_list),
604};
605
606static struct clk *clkset_usbhost_list[] = {
607 &clk_mout_epll.clk,
608 &clk_dout_mpll,
609 &clk_mout_hpll.clk,
610 &clk_48m,
611};
612
613static struct clksrc_sources clkset_usbhost = {
614 .sources = clkset_usbhost_list,
615 .nr_sources = ARRAY_SIZE(clkset_usbhost_list),
616};
617
618static struct clksrc_clk clksrc_clks[] = {
619 {
620 .clk = {
621 .name = "spi_bus",
622 .id = 0,
623 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0,
624 .enable = s5pc100_sclk0_ctrl,
625
626 },
627 .sources = &clkset_spi,
628 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 4, .size = 4, },
629 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 4, .size = 2, },
630 }, {
631 .clk = {
632 .name = "spi_bus",
633 .id = 1,
634 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1,
635 .enable = s5pc100_sclk0_ctrl,
636 },
637 .sources = &clkset_spi,
638 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 8, .size = 4, },
639 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 8, .size = 2, },
640 }, {
641 .clk = {
642 .name = "spi_bus",
643 .id = 2,
644 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2,
645 .enable = s5pc100_sclk0_ctrl,
646 },
647 .sources = &clkset_spi,
648 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 12, .size = 4, },
649 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 12, .size = 2, },
650 }, {
651 .clk = {
652 .name = "uclk1",
653 .id = -1,
654 .ctrlbit = S5PC100_CLKGATE_SCLK0_UART,
655 .enable = s5pc100_sclk0_ctrl,
656 },
657 .sources = &clkset_uart,
658 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 0, .size = 3, },
659 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 0, .size = 1, },
660 }, {
661 .clk = {
662 .name = "spdif",
663 .id = -1,
664 },
665 .sources = &clkset_spdif,
666 .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 24, .size = 2, },
667 }, {
668 .clk = {
669 .name = "lcd",
670 .id = -1,
671 .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD,
672 .enable = s5pc100_sclk1_ctrl,
673 },
674 .sources = &clkset_lcd_fimc,
675 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 12, .size = 4, },
676 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 12, .size = 2, },
677 }, {
678 .clk = {
679 .name = "fimc",
680 .id = 0,
681 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0,
682 .enable = s5pc100_sclk1_ctrl,
683 },
684 .sources = &clkset_lcd_fimc,
685 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 16, .size = 4, },
686 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 16, .size = 2, },
687 }, {
688 .clk = {
689 .name = "fimc",
690 .id = 1,
691 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1,
692 .enable = s5pc100_sclk1_ctrl,
693 },
694 .sources = &clkset_lcd_fimc,
695 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 20, .size = 4, },
696 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 20, .size = 2, },
697 }, {
698 .clk = {
699 .name = "fimc",
700 .id = 2,
701 .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2,
702 .enable = s5pc100_sclk1_ctrl,
703 },
704 .sources = &clkset_lcd_fimc,
705 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 24, .size = 4, },
706 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 24, .size = 2, },
707 }, {
708 .clk = {
709 .name = "mmc_bus",
710 .id = 0,
711 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0,
712 .enable = s5pc100_sclk0_ctrl,
713 },
714 .sources = &clkset_mmc,
715 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 0, .size = 4, },
716 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 0, .size = 2, },
717 }, {
718 .clk = {
719 .name = "mmc_bus",
720 .id = 1,
721 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1,
722 .enable = s5pc100_sclk0_ctrl,
723 },
724 .sources = &clkset_mmc,
725 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 4, .size = 4, },
726 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 4, .size = 2, },
727 }, {
728 .clk = {
729 .name = "mmc_bus",
730 .id = 2,
731 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2,
732 .enable = s5pc100_sclk0_ctrl,
733 },
734 .sources = &clkset_mmc,
735 .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 8, .size = 4, },
736 .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 8, .size = 2, },
737 }, {
738 .clk = {
739 .name = "usbhost",
740 .id = -1,
741 .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST,
742 .enable = s5pc100_sclk0_ctrl,
743 },
744 .sources = &clkset_usbhost,
745 .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 20, .size = 4, },
746 .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 20, .size = 2, },
747 }
748};
749
750/* Clock initialisation code */
751
752static struct clksrc_clk *init_parents[] = {
753 &clk_mout_apll,
754 &clk_mout_mpll,
755 &clk_mout_am,
756 &clk_mout_onenand,
757 &clk_mout_epll,
758 &clk_mout_hpll,
759};
760
761#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
762
763void __init_or_cpufreq s5pc100_setup_clocks(void)
764{
765 struct clk *xtal_clk;
766 unsigned long xtal;
767 unsigned long armclk;
768 unsigned long hclkd0;
769 unsigned long hclk;
770 unsigned long pclkd0;
771 unsigned long pclk;
772 unsigned long apll, mpll, epll, hpll;
773 unsigned int ptr;
774 u32 clkdiv0, clkdiv1;
775
776 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
777
778 clkdiv0 = __raw_readl(S5PC100_CLKDIV0);
779 clkdiv1 = __raw_readl(S5PC100_CLKDIV1);
780
781 printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", __func__, clkdiv0, clkdiv1);
782
783 xtal_clk = clk_get(NULL, "xtal");
784 BUG_ON(IS_ERR(xtal_clk));
785
786 xtal = clk_get_rate(xtal_clk);
787 clk_put(xtal_clk);
788
789 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
790
791 apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_APLL_CON));
792 mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_MPLL_CON));
793 epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON));
794 hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON));
795
796 printk(KERN_INFO "S5PC100: Apll=%ld.%03ld Mhz, Mpll=%ld.%03ld Mhz"
797 ", Epll=%ld.%03ld Mhz, Hpll=%ld.%03ld Mhz\n",
798 print_mhz(apll), print_mhz(mpll),
799 print_mhz(epll), print_mhz(hpll));
800
801 armclk = apll / GET_DIV(clkdiv0, S5PC100_CLKDIV0_APLL);
802 armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM);
803 hclkd0 = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_D0);
804 pclkd0 = hclkd0 / GET_DIV(clkdiv0, S5PC100_CLKDIV0_PCLKD0);
805 hclk = mpll / GET_DIV(clkdiv1, S5PC100_CLKDIV1_D1);
806 pclk = hclk / GET_DIV(clkdiv1, S5PC100_CLKDIV1_PCLKD1);
807
808 printk(KERN_INFO "S5PC100: ARMCLK=%ld.%03ld MHz, HCLKD0=%ld.%03ld MHz,"
809 " PCLKD0=%ld.%03ld MHz\n, HCLK=%ld.%03ld MHz,"
810 " PCLK=%ld.%03ld MHz\n",
811 print_mhz(armclk), print_mhz(hclkd0),
812 print_mhz(pclkd0), print_mhz(hclk), print_mhz(pclk));
813
814 clk_fout_apll.rate = apll;
815 clk_fout_mpll.rate = mpll;
816 clk_fout_epll.rate = epll;
817 clk_fout_hpll.rate = hpll;
818
819 clk_h.rate = hclk;
820 clk_p.rate = pclk;
821 clk_f.rate = armclk;
822
823 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
824 s3c_set_clksrc(init_parents[ptr], true);
825
826 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_audio); ptr++)
827 s3c_set_clksrc(clksrc_audio + ptr, true);
828
829 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
830 s3c_set_clksrc(clksrc_clks + ptr, true);
831}
832
833static struct clk *clks[] __initdata = {
834 &clk_ext_xtal_mux,
835 &clk_dout_apll,
836 &clk_dout_d0_bus,
837 &clk_dout_pclkd0,
838 &clk_dout_apll2,
839 &clk_mout_apll.clk,
840 &clk_mout_mpll.clk,
841 &clk_mout_epll.clk,
842 &clk_mout_hpll.clk,
843 &clk_mout_am.clk,
844 &clk_dout_d1_bus,
845 &clk_mout_onenand.clk,
846 &clk_dout_pclkd1,
847 &clk_dout_mpll2,
848 &clk_dout_cam,
849 &clk_dout_mpll,
850 &clk_fout_epll,
851 &clk_iis_cd0,
852 &clk_iis_cd1,
853 &clk_iis_cd2,
854 &clk_pcm_cd0,
855 &clk_pcm_cd1,
856 &clk_arm,
857};
858
859void __init s5pc100_register_clocks(void)
860{
861 struct clk *clkp;
862 int ret;
863 int ptr;
864
865 for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
866 clkp = clks[ptr];
867 ret = s3c24xx_register_clock(clkp);
868 if (ret < 0) {
869 printk(KERN_ERR "Failed to register clock %s (%d)\n",
870 clkp->name, ret);
871 }
872 }
873
874 s3c_register_clksrc(clksrc_audio, ARRAY_SIZE(clksrc_audio));
875 s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
876}
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 229919e9744c..1077ebebfb03 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -6,7 +6,7 @@
6 6
7config PLAT_SAMSUNG 7config PLAT_SAMSUNG
8 bool 8 bool
9 depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX || ARCH_S5PC1XX 9 depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX
10 select NO_IOPORT 10 select NO_IOPORT
11 default y 11 default y
12 help 12 help
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 01:08:42 -0500