diff options
author | Arnd Bergmann <arnd@arndb.de> | 2013-04-09 17:08:19 -0400 |
---|---|---|
committer | Arnd Bergmann <arnd@arndb.de> | 2013-04-09 17:08:19 -0400 |
commit | a93216c9212cb9ec36bb71776b706e7ed2d9d67c (patch) | |
tree | 08f0647c0da73604678ae60a09bd81469730d3bd /arch/arm | |
parent | 518fbd02a5482dbcc5ddbaec4124b53a5df75de8 (diff) | |
parent | 329afd264592f8d0e40fa063c089b35fba0014cc (diff) |
Merge tag 'devel-samsung-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
From Kukjin Kim <kgene.kim@samsung.com>:
including various development for samsung for v3.10
* tag 'devel-samsung-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: replace cpumask by the corresponding macro
ARM: EXYNOS: handle properly the return values
ARM: EXYNOS: factor out the idle states
ARM: SAMSUNG: check processor type before cache restoration in resume
ARM: S3C64XX: Slow down mic detection rate for wm5102
ARM: S3C64XX: Clear DMA flags on channel request
ARM: EXYNOS: Clear ENABLE_WAKEUP_SW bit when entering suspend
ARM: EXYNOS: Remove hardcode wakeup unmask for EINT_0
ARM: EXYNOS: Add support for rtc wakeup
ARM: SAMSUNG: Export MIPI CSIS/DSIM PHY control functions
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-exynos/common.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-exynos/cpuidle.c | 58 | ||||
-rw-r--r-- | arch/arm/mach-exynos/include/mach/pm-core.h | 9 | ||||
-rw-r--r-- | arch/arm/mach-s3c64xx/dma.c | 1 | ||||
-rw-r--r-- | arch/arm/mach-s3c64xx/mach-crag6410-module.c | 1 | ||||
-rw-r--r-- | arch/arm/plat-samsung/s5p-sleep.S | 9 | ||||
-rw-r--r-- | arch/arm/plat-samsung/setup-mipiphy.c | 3 |
7 files changed, 44 insertions, 39 deletions
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index d63d399c7bae..789d4e66c950 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c | |||
@@ -463,6 +463,8 @@ void __init exynos4_init_irq(void) | |||
463 | * uses GIC instead of VIC. | 463 | * uses GIC instead of VIC. |
464 | */ | 464 | */ |
465 | s5p_init_irq(NULL, 0); | 465 | s5p_init_irq(NULL, 0); |
466 | |||
467 | gic_arch_extn.irq_set_wake = s3c_irq_wake; | ||
466 | } | 468 | } |
467 | 469 | ||
468 | void __init exynos5_init_irq(void) | 470 | void __init exynos5_init_irq(void) |
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index fcfe0251aa3e..e2689d1133b9 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c | |||
@@ -41,24 +41,25 @@ static int exynos4_enter_lowpower(struct cpuidle_device *dev, | |||
41 | struct cpuidle_driver *drv, | 41 | struct cpuidle_driver *drv, |
42 | int index); | 42 | int index); |
43 | 43 | ||
44 | static struct cpuidle_state exynos4_cpuidle_set[] __initdata = { | ||
45 | [0] = ARM_CPUIDLE_WFI_STATE, | ||
46 | [1] = { | ||
47 | .enter = exynos4_enter_lowpower, | ||
48 | .exit_latency = 300, | ||
49 | .target_residency = 100000, | ||
50 | .flags = CPUIDLE_FLAG_TIME_VALID, | ||
51 | .name = "C1", | ||
52 | .desc = "ARM power down", | ||
53 | }, | ||
54 | }; | ||
55 | |||
56 | static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device); | 44 | static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device); |
57 | 45 | ||
58 | static struct cpuidle_driver exynos4_idle_driver = { | 46 | static struct cpuidle_driver exynos4_idle_driver = { |
59 | .name = "exynos4_idle", | 47 | .name = "exynos4_idle", |
60 | .owner = THIS_MODULE, | 48 | .owner = THIS_MODULE, |
61 | .en_core_tk_irqen = 1, | 49 | .en_core_tk_irqen = 1, |
50 | .states = { | ||
51 | [0] = ARM_CPUIDLE_WFI_STATE, | ||
52 | [1] = { | ||
53 | .enter = exynos4_enter_lowpower, | ||
54 | .exit_latency = 300, | ||
55 | .target_residency = 100000, | ||
56 | .flags = CPUIDLE_FLAG_TIME_VALID, | ||
57 | .name = "C1", | ||
58 | .desc = "ARM power down", | ||
59 | }, | ||
60 | }, | ||
61 | .state_count = 2, | ||
62 | .safe_state_index = 0, | ||
62 | }; | 63 | }; |
63 | 64 | ||
64 | /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ | 65 | /* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */ |
@@ -193,37 +194,30 @@ static void __init exynos5_core_down_clk(void) | |||
193 | 194 | ||
194 | static int __init exynos4_init_cpuidle(void) | 195 | static int __init exynos4_init_cpuidle(void) |
195 | { | 196 | { |
196 | int i, max_cpuidle_state, cpu_id; | 197 | int cpu_id, ret; |
197 | struct cpuidle_device *device; | 198 | struct cpuidle_device *device; |
198 | struct cpuidle_driver *drv = &exynos4_idle_driver; | ||
199 | 199 | ||
200 | if (soc_is_exynos5250()) | 200 | if (soc_is_exynos5250()) |
201 | exynos5_core_down_clk(); | 201 | exynos5_core_down_clk(); |
202 | 202 | ||
203 | /* Setup cpuidle driver */ | 203 | ret = cpuidle_register_driver(&exynos4_idle_driver); |
204 | drv->state_count = (sizeof(exynos4_cpuidle_set) / | 204 | if (ret) { |
205 | sizeof(struct cpuidle_state)); | 205 | printk(KERN_ERR "CPUidle failed to register driver\n"); |
206 | max_cpuidle_state = drv->state_count; | 206 | return ret; |
207 | for (i = 0; i < max_cpuidle_state; i++) { | ||
208 | memcpy(&drv->states[i], &exynos4_cpuidle_set[i], | ||
209 | sizeof(struct cpuidle_state)); | ||
210 | } | 207 | } |
211 | drv->safe_state_index = 0; | ||
212 | cpuidle_register_driver(&exynos4_idle_driver); | ||
213 | 208 | ||
214 | for_each_cpu(cpu_id, cpu_online_mask) { | 209 | for_each_online_cpu(cpu_id) { |
215 | device = &per_cpu(exynos4_cpuidle_device, cpu_id); | 210 | device = &per_cpu(exynos4_cpuidle_device, cpu_id); |
216 | device->cpu = cpu_id; | 211 | device->cpu = cpu_id; |
217 | 212 | ||
218 | if (cpu_id == 0) | 213 | /* Support IDLE only */ |
219 | device->state_count = (sizeof(exynos4_cpuidle_set) / | 214 | if (cpu_id != 0) |
220 | sizeof(struct cpuidle_state)); | 215 | device->state_count = 1; |
221 | else | ||
222 | device->state_count = 1; /* Support IDLE only */ | ||
223 | 216 | ||
224 | if (cpuidle_register_device(device)) { | 217 | ret = cpuidle_register_device(device); |
225 | printk(KERN_ERR "CPUidle register device failed\n,"); | 218 | if (ret) { |
226 | return -EIO; | 219 | printk(KERN_ERR "CPUidle register device failed\n"); |
220 | return ret; | ||
227 | } | 221 | } |
228 | } | 222 | } |
229 | 223 | ||
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h index a67ecfaf1216..7dbbfec13ea5 100644 --- a/arch/arm/mach-exynos/include/mach/pm-core.h +++ b/arch/arm/mach-exynos/include/mach/pm-core.h | |||
@@ -27,13 +27,8 @@ static inline void s3c_pm_debug_init_uart(void) | |||
27 | 27 | ||
28 | static inline void s3c_pm_arch_prepare_irqs(void) | 28 | static inline void s3c_pm_arch_prepare_irqs(void) |
29 | { | 29 | { |
30 | unsigned int tmp; | 30 | __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK); |
31 | tmp = __raw_readl(S5P_WAKEUP_MASK); | 31 | __raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK); |
32 | tmp &= ~(1 << 31); | ||
33 | __raw_writel(tmp, S5P_WAKEUP_MASK); | ||
34 | |||
35 | __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK); | ||
36 | __raw_writel(s3c_irqwake_eintmask & 0xFFFFFFFE, S5P_EINT_WAKEUP_MASK); | ||
37 | } | 32 | } |
38 | 33 | ||
39 | static inline void s3c_pm_arch_stop_clocks(void) | 34 | static inline void s3c_pm_arch_stop_clocks(void) |
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c index 6af1aa1ef213..759846c28d12 100644 --- a/arch/arm/mach-s3c64xx/dma.c +++ b/arch/arm/mach-s3c64xx/dma.c | |||
@@ -509,6 +509,7 @@ int s3c2410_dma_request(enum dma_ch channel, | |||
509 | chan->client = client; | 509 | chan->client = client; |
510 | chan->in_use = 1; | 510 | chan->in_use = 1; |
511 | chan->peripheral = channel; | 511 | chan->peripheral = channel; |
512 | chan->flags = 0; | ||
512 | 513 | ||
513 | local_irq_restore(flags); | 514 | local_irq_restore(flags); |
514 | 515 | ||
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c index bf3d1c09b085..a946b759fabd 100644 --- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c +++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c | |||
@@ -210,6 +210,7 @@ static struct arizona_pdata wm5102_reva_pdata = { | |||
210 | .gpio_base = CODEC_GPIO_BASE, | 210 | .gpio_base = CODEC_GPIO_BASE, |
211 | .irq_active_high = true, | 211 | .irq_active_high = true, |
212 | .micd_pol_gpio = CODEC_GPIO_BASE + 4, | 212 | .micd_pol_gpio = CODEC_GPIO_BASE + 4, |
213 | .micd_rate = 6, | ||
213 | .gpio_defaults = { | 214 | .gpio_defaults = { |
214 | [2] = 0x10000, /* AIF3TXLRCLK */ | 215 | [2] = 0x10000, /* AIF3TXLRCLK */ |
215 | [3] = 0x4, /* OPCLK */ | 216 | [3] = 0x4, /* OPCLK */ |
diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S index bdf6dadf8790..a030e7301da8 100644 --- a/arch/arm/plat-samsung/s5p-sleep.S +++ b/arch/arm/plat-samsung/s5p-sleep.S | |||
@@ -25,6 +25,9 @@ | |||
25 | #include <asm/asm-offsets.h> | 25 | #include <asm/asm-offsets.h> |
26 | #include <asm/hardware/cache-l2x0.h> | 26 | #include <asm/hardware/cache-l2x0.h> |
27 | 27 | ||
28 | #define CPU_MASK 0xff0ffff0 | ||
29 | #define CPU_CORTEX_A9 0x410fc090 | ||
30 | |||
28 | /* | 31 | /* |
29 | * The following code is located into the .data section. This is to | 32 | * The following code is located into the .data section. This is to |
30 | * allow l2x0_regs_phys to be accessed with a relative load while we | 33 | * allow l2x0_regs_phys to be accessed with a relative load while we |
@@ -51,6 +54,12 @@ | |||
51 | 54 | ||
52 | ENTRY(s3c_cpu_resume) | 55 | ENTRY(s3c_cpu_resume) |
53 | #ifdef CONFIG_CACHE_L2X0 | 56 | #ifdef CONFIG_CACHE_L2X0 |
57 | mrc p15, 0, r0, c0, c0, 0 | ||
58 | ldr r1, =CPU_MASK | ||
59 | and r0, r0, r1 | ||
60 | ldr r1, =CPU_CORTEX_A9 | ||
61 | cmp r0, r1 | ||
62 | bne resume_l2on | ||
54 | adr r0, l2x0_regs_phys | 63 | adr r0, l2x0_regs_phys |
55 | ldr r0, [r0] | 64 | ldr r0, [r0] |
56 | ldr r1, [r0, #L2X0_R_PHY_BASE] | 65 | ldr r1, [r0, #L2X0_R_PHY_BASE] |
diff --git a/arch/arm/plat-samsung/setup-mipiphy.c b/arch/arm/plat-samsung/setup-mipiphy.c index 147459327601..66df315990a7 100644 --- a/arch/arm/plat-samsung/setup-mipiphy.c +++ b/arch/arm/plat-samsung/setup-mipiphy.c | |||
@@ -8,6 +8,7 @@ | |||
8 | * published by the Free Software Foundation. | 8 | * published by the Free Software Foundation. |
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <linux/export.h> | ||
11 | #include <linux/kernel.h> | 12 | #include <linux/kernel.h> |
12 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
13 | #include <linux/io.h> | 14 | #include <linux/io.h> |
@@ -50,8 +51,10 @@ int s5p_csis_phy_enable(int id, bool on) | |||
50 | { | 51 | { |
51 | return __s5p_mipi_phy_control(id, on, S5P_MIPI_DPHY_SRESETN); | 52 | return __s5p_mipi_phy_control(id, on, S5P_MIPI_DPHY_SRESETN); |
52 | } | 53 | } |
54 | EXPORT_SYMBOL(s5p_csis_phy_enable); | ||
53 | 55 | ||
54 | int s5p_dsim_phy_enable(struct platform_device *pdev, bool on) | 56 | int s5p_dsim_phy_enable(struct platform_device *pdev, bool on) |
55 | { | 57 | { |
56 | return __s5p_mipi_phy_control(pdev->id, on, S5P_MIPI_DPHY_MRESETN); | 58 | return __s5p_mipi_phy_control(pdev->id, on, S5P_MIPI_DPHY_MRESETN); |
57 | } | 59 | } |
60 | EXPORT_SYMBOL(s5p_dsim_phy_enable); | ||