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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2009-08-03 11:41:55 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-08-03 11:41:55 -0400
commit61f4a10cb4e9447a85245c63b3e7f46e09299fed (patch)
tree6fdf82a99d38a035b0876b6dbce5b53a36084700 /arch/arm
parent412bb0a6224f96661c042a109c4978649c00ed52 (diff)
parent78a1a6d3411de1a8b0dc1cb92754b5f12f251912 (diff)
Merge branch 'omap4_upstream' of git://dev.omapzoom.org/pub/scm/santosh/kernel-omap4-base into devel-stable
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c2
-rw-r--r--arch/arm/mach-omap2/mcbsp.c41
-rw-r--r--arch/arm/mach-omap2/serial.c10
-rw-r--r--arch/arm/plat-omap/gpio.c249
-rw-r--r--arch/arm/plat-omap/include/mach/dma.h88
-rw-r--r--arch/arm/plat-omap/include/mach/mcbsp.h8
-rw-r--r--arch/arm/plat-omap/mcbsp.c2
7 files changed, 346 insertions, 54 deletions
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 57e477bd89c6..7e1e721f0324 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -39,7 +39,7 @@ static struct platform_device *sdp4430_devices[] __initdata = {
39}; 39};
40 40
41static struct omap_uart_config sdp4430_uart_config __initdata = { 41static struct omap_uart_config sdp4430_uart_config __initdata = {
42 .enabled_uarts = (1 << 0) | (1 << 1) | (1 << 2), 42 .enabled_uarts = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3),
43}; 43};
44 44
45static struct omap_lcd_config sdp4430_lcd_config __initdata = { 45static struct omap_lcd_config sdp4430_lcd_config __initdata = {
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index a5c0f0435cd6..d49dfb5e931f 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -169,6 +169,42 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
169#define OMAP34XX_MCBSP_PDATA_SZ 0 169#define OMAP34XX_MCBSP_PDATA_SZ 0
170#endif 170#endif
171 171
172static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
173 {
174 .phys_base = OMAP44XX_MCBSP1_BASE,
175 .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX,
176 .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX,
177 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
178 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
179 .ops = &omap2_mcbsp_ops,
180 },
181 {
182 .phys_base = OMAP44XX_MCBSP2_BASE,
183 .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX,
184 .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX,
185 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
186 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
187 .ops = &omap2_mcbsp_ops,
188 },
189 {
190 .phys_base = OMAP44XX_MCBSP3_BASE,
191 .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX,
192 .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX,
193 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
194 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
195 .ops = &omap2_mcbsp_ops,
196 },
197 {
198 .phys_base = OMAP44XX_MCBSP4_BASE,
199 .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX,
200 .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX,
201 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
202 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
203 .ops = &omap2_mcbsp_ops,
204 },
205};
206#define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata)
207
172static int __init omap2_mcbsp_init(void) 208static int __init omap2_mcbsp_init(void)
173{ 209{
174 if (cpu_is_omap2420()) 210 if (cpu_is_omap2420())
@@ -177,6 +213,8 @@ static int __init omap2_mcbsp_init(void)
177 omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ; 213 omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
178 if (cpu_is_omap34xx()) 214 if (cpu_is_omap34xx())
179 omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ; 215 omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
216 if (cpu_is_omap44xx())
217 omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
180 218
181 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), 219 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
182 GFP_KERNEL); 220 GFP_KERNEL);
@@ -192,6 +230,9 @@ static int __init omap2_mcbsp_init(void)
192 if (cpu_is_omap34xx()) 230 if (cpu_is_omap34xx())
193 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata, 231 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
194 OMAP34XX_MCBSP_PDATA_SZ); 232 OMAP34XX_MCBSP_PDATA_SZ);
233 if (cpu_is_omap44xx())
234 omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata,
235 OMAP44XX_MCBSP_PDATA_SZ);
195 236
196 return omap_mcbsp_init(); 237 return omap_mcbsp_init();
197} 238}
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index b094c15bfe47..c0bea75f13f8 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -97,6 +97,16 @@ static struct plat_serial8250_port serial_platform_data[] = {
97 .regshift = 2, 97 .regshift = 2,
98 .uartclk = OMAP24XX_BASE_BAUD * 16, 98 .uartclk = OMAP24XX_BASE_BAUD * 16,
99 }, { 99 }, {
100#ifdef CONFIG_ARCH_OMAP4
101 .membase = IO_ADDRESS(OMAP_UART4_BASE),
102 .mapbase = OMAP_UART4_BASE,
103 .irq = 70,
104 .flags = UPF_BOOT_AUTOCONF,
105 .iotype = UPIO_MEM,
106 .regshift = 2,
107 .uartclk = OMAP24XX_BASE_BAUD * 16,
108 }, {
109#endif
100 .flags = 0 110 .flags = 0
101 } 111 }
102}; 112};
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 26b387c12423..f0b71680ec52 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -138,6 +138,32 @@
138#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090 138#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
139#define OMAP24XX_GPIO_SETDATAOUT 0x0094 139#define OMAP24XX_GPIO_SETDATAOUT 0x0094
140 140
141#define OMAP4_GPIO_REVISION 0x0000
142#define OMAP4_GPIO_SYSCONFIG 0x0010
143#define OMAP4_GPIO_EOI 0x0020
144#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
145#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
146#define OMAP4_GPIO_IRQSTATUS0 0x002c
147#define OMAP4_GPIO_IRQSTATUS1 0x0030
148#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
149#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
150#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
151#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
152#define OMAP4_GPIO_IRQWAKEN0 0x0044
153#define OMAP4_GPIO_IRQWAKEN1 0x0048
154#define OMAP4_GPIO_SYSSTATUS 0x0104
155#define OMAP4_GPIO_CTRL 0x0130
156#define OMAP4_GPIO_OE 0x0134
157#define OMAP4_GPIO_DATAIN 0x0138
158#define OMAP4_GPIO_DATAOUT 0x013c
159#define OMAP4_GPIO_LEVELDETECT0 0x0140
160#define OMAP4_GPIO_LEVELDETECT1 0x0144
161#define OMAP4_GPIO_RISINGDETECT 0x0148
162#define OMAP4_GPIO_FALLINGDETECT 0x014c
163#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
164#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
165#define OMAP4_GPIO_CLEARDATAOUT 0x0190
166#define OMAP4_GPIO_SETDATAOUT 0x0194
141/* 167/*
142 * omap34xx specific GPIO registers 168 * omap34xx specific GPIO registers
143 */ 169 */
@@ -386,12 +412,16 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
386 reg += OMAP850_GPIO_DIR_CONTROL; 412 reg += OMAP850_GPIO_DIR_CONTROL;
387 break; 413 break;
388#endif 414#endif
389#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 415#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
390 defined(CONFIG_ARCH_OMAP4)
391 case METHOD_GPIO_24XX: 416 case METHOD_GPIO_24XX:
392 reg += OMAP24XX_GPIO_OE; 417 reg += OMAP24XX_GPIO_OE;
393 break; 418 break;
394#endif 419#endif
420#if defined(CONFIG_ARCH_OMAP4)
421 case METHOD_GPIO_24XX:
422 reg += OMAP4_GPIO_OE;
423 break;
424#endif
395 default: 425 default:
396 WARN_ON(1); 426 WARN_ON(1);
397 return; 427 return;
@@ -459,8 +489,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
459 l &= ~(1 << gpio); 489 l &= ~(1 << gpio);
460 break; 490 break;
461#endif 491#endif
462#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 492#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
463 defined(CONFIG_ARCH_OMAP4)
464 case METHOD_GPIO_24XX: 493 case METHOD_GPIO_24XX:
465 if (enable) 494 if (enable)
466 reg += OMAP24XX_GPIO_SETDATAOUT; 495 reg += OMAP24XX_GPIO_SETDATAOUT;
@@ -469,6 +498,15 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
469 l = 1 << gpio; 498 l = 1 << gpio;
470 break; 499 break;
471#endif 500#endif
501#ifdef CONFIG_ARCH_OMAP4
502 case METHOD_GPIO_24XX:
503 if (enable)
504 reg += OMAP4_GPIO_SETDATAOUT;
505 else
506 reg += OMAP4_GPIO_CLEARDATAOUT;
507 l = 1 << gpio;
508 break;
509#endif
472 default: 510 default:
473 WARN_ON(1); 511 WARN_ON(1);
474 return; 512 return;
@@ -511,12 +549,16 @@ static int __omap_get_gpio_datain(int gpio)
511 reg += OMAP850_GPIO_DATA_INPUT; 549 reg += OMAP850_GPIO_DATA_INPUT;
512 break; 550 break;
513#endif 551#endif
514#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 552#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
515 defined(CONFIG_ARCH_OMAP4)
516 case METHOD_GPIO_24XX: 553 case METHOD_GPIO_24XX:
517 reg += OMAP24XX_GPIO_DATAIN; 554 reg += OMAP24XX_GPIO_DATAIN;
518 break; 555 break;
519#endif 556#endif
557#ifdef CONFIG_ARCH_OMAP4
558 case METHOD_GPIO_24XX:
559 reg += OMAP4_GPIO_DATAIN;
560 break;
561#endif
520 default: 562 default:
521 return -EINVAL; 563 return -EINVAL;
522 } 564 }
@@ -544,7 +586,11 @@ void omap_set_gpio_debounce(int gpio, int enable)
544 586
545 bank = get_gpio_bank(gpio); 587 bank = get_gpio_bank(gpio);
546 reg = bank->base; 588 reg = bank->base;
589#ifdef CONFIG_ARCH_OMAP4
590 reg += OMAP4_GPIO_DEBOUNCENABLE;
591#else
547 reg += OMAP24XX_GPIO_DEBOUNCE_EN; 592 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
593#endif
548 594
549 spin_lock_irqsave(&bank->lock, flags); 595 spin_lock_irqsave(&bank->lock, flags);
550 val = __raw_readl(reg); 596 val = __raw_readl(reg);
@@ -581,7 +627,11 @@ void omap_set_gpio_debounce_time(int gpio, int enc_time)
581 reg = bank->base; 627 reg = bank->base;
582 628
583 enc_time &= 0xff; 629 enc_time &= 0xff;
630#ifdef CONFIG_ARCH_OMAP4
631 reg += OMAP4_GPIO_DEBOUNCINGTIME;
632#else
584 reg += OMAP24XX_GPIO_DEBOUNCE_VAL; 633 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
634#endif
585 __raw_writel(enc_time, reg); 635 __raw_writel(enc_time, reg);
586} 636}
587EXPORT_SYMBOL(omap_set_gpio_debounce_time); 637EXPORT_SYMBOL(omap_set_gpio_debounce_time);
@@ -593,23 +643,46 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
593{ 643{
594 void __iomem *base = bank->base; 644 void __iomem *base = bank->base;
595 u32 gpio_bit = 1 << gpio; 645 u32 gpio_bit = 1 << gpio;
646 u32 val;
596 647
597 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, 648 if (cpu_is_omap44xx()) {
598 trigger & IRQ_TYPE_LEVEL_LOW); 649 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
599 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, 650 trigger & IRQ_TYPE_LEVEL_LOW);
600 trigger & IRQ_TYPE_LEVEL_HIGH); 651 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
601 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit, 652 trigger & IRQ_TYPE_LEVEL_HIGH);
602 trigger & IRQ_TYPE_EDGE_RISING); 653 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
603 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, 654 trigger & IRQ_TYPE_EDGE_RISING);
604 trigger & IRQ_TYPE_EDGE_FALLING); 655 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
605 656 trigger & IRQ_TYPE_EDGE_FALLING);
657 } else {
658 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
659 trigger & IRQ_TYPE_LEVEL_LOW);
660 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
661 trigger & IRQ_TYPE_LEVEL_HIGH);
662 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
663 trigger & IRQ_TYPE_EDGE_RISING);
664 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
665 trigger & IRQ_TYPE_EDGE_FALLING);
666 }
606 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { 667 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
607 if (trigger != 0) 668 if (cpu_is_omap44xx()) {
608 __raw_writel(1 << gpio, bank->base 669 if (trigger != 0)
670 __raw_writel(1 << gpio, bank->base+
671 OMAP4_GPIO_IRQWAKEN0);
672 else {
673 val = __raw_readl(bank->base +
674 OMAP4_GPIO_IRQWAKEN0);
675 __raw_writel(val & (~(1 << gpio)), bank->base +
676 OMAP4_GPIO_IRQWAKEN0);
677 }
678 } else {
679 if (trigger != 0)
680 __raw_writel(1 << gpio, bank->base
609 + OMAP24XX_GPIO_SETWKUENA); 681 + OMAP24XX_GPIO_SETWKUENA);
610 else 682 else
611 __raw_writel(1 << gpio, bank->base 683 __raw_writel(1 << gpio, bank->base
612 + OMAP24XX_GPIO_CLEARWKUENA); 684 + OMAP24XX_GPIO_CLEARWKUENA);
685 }
613 } else { 686 } else {
614 if (trigger != 0) 687 if (trigger != 0)
615 bank->enabled_non_wakeup_gpios |= gpio_bit; 688 bank->enabled_non_wakeup_gpios |= gpio_bit;
@@ -617,9 +690,15 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
617 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 690 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
618 } 691 }
619 692
620 bank->level_mask = 693 if (cpu_is_omap44xx()) {
621 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | 694 bank->level_mask =
622 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); 695 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
696 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
697 } else {
698 bank->level_mask =
699 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
700 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
701 }
623} 702}
624#endif 703#endif
625 704
@@ -783,12 +862,16 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
783 reg += OMAP850_GPIO_INT_STATUS; 862 reg += OMAP850_GPIO_INT_STATUS;
784 break; 863 break;
785#endif 864#endif
786#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 865#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
787 defined(CONFIG_ARCH_OMAP4)
788 case METHOD_GPIO_24XX: 866 case METHOD_GPIO_24XX:
789 reg += OMAP24XX_GPIO_IRQSTATUS1; 867 reg += OMAP24XX_GPIO_IRQSTATUS1;
790 break; 868 break;
791#endif 869#endif
870#if defined(CONFIG_ARCH_OMAP4)
871 case METHOD_GPIO_24XX:
872 reg += OMAP4_GPIO_IRQSTATUS0;
873 break;
874#endif
792 default: 875 default:
793 WARN_ON(1); 876 WARN_ON(1);
794 return; 877 return;
@@ -798,12 +881,16 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
798 /* Workaround for clearing DSP GPIO interrupts to allow retention */ 881 /* Workaround for clearing DSP GPIO interrupts to allow retention */
799#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 882#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
800 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2; 883 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
801 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 884#endif
885#if defined(CONFIG_ARCH_OMAP4)
886 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
887#endif
888 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
802 __raw_writel(gpio_mask, reg); 889 __raw_writel(gpio_mask, reg);
803 890
804 /* Flush posted write for the irq status to avoid spurious interrupts */ 891 /* Flush posted write for the irq status to avoid spurious interrupts */
805 __raw_readl(reg); 892 __raw_readl(reg);
806#endif 893 }
807} 894}
808 895
809static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) 896static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
@@ -853,13 +940,18 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
853 inv = 1; 940 inv = 1;
854 break; 941 break;
855#endif 942#endif
856#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 943#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
857 defined(CONFIG_ARCH_OMAP4)
858 case METHOD_GPIO_24XX: 944 case METHOD_GPIO_24XX:
859 reg += OMAP24XX_GPIO_IRQENABLE1; 945 reg += OMAP24XX_GPIO_IRQENABLE1;
860 mask = 0xffffffff; 946 mask = 0xffffffff;
861 break; 947 break;
862#endif 948#endif
949#if defined(CONFIG_ARCH_OMAP4)
950 case METHOD_GPIO_24XX:
951 reg += OMAP4_GPIO_IRQSTATUSSET0;
952 mask = 0xffffffff;
953 break;
954#endif
863 default: 955 default:
864 WARN_ON(1); 956 WARN_ON(1);
865 return 0; 957 return 0;
@@ -927,8 +1019,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
927 l |= gpio_mask; 1019 l |= gpio_mask;
928 break; 1020 break;
929#endif 1021#endif
930#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1022#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
931 defined(CONFIG_ARCH_OMAP4)
932 case METHOD_GPIO_24XX: 1023 case METHOD_GPIO_24XX:
933 if (enable) 1024 if (enable)
934 reg += OMAP24XX_GPIO_SETIRQENABLE1; 1025 reg += OMAP24XX_GPIO_SETIRQENABLE1;
@@ -937,6 +1028,15 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
937 l = gpio_mask; 1028 l = gpio_mask;
938 break; 1029 break;
939#endif 1030#endif
1031#ifdef CONFIG_ARCH_OMAP4
1032 case METHOD_GPIO_24XX:
1033 if (enable)
1034 reg += OMAP4_GPIO_IRQSTATUSSET0;
1035 else
1036 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1037 l = gpio_mask;
1038 break;
1039#endif
940 default: 1040 default:
941 WARN_ON(1); 1041 WARN_ON(1);
942 return; 1042 return;
@@ -1112,11 +1212,14 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1112 if (bank->method == METHOD_GPIO_850) 1212 if (bank->method == METHOD_GPIO_850)
1113 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS; 1213 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
1114#endif 1214#endif
1115#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1215#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1116 defined(CONFIG_ARCH_OMAP4)
1117 if (bank->method == METHOD_GPIO_24XX) 1216 if (bank->method == METHOD_GPIO_24XX)
1118 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; 1217 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1119#endif 1218#endif
1219#if defined(CONFIG_ARCH_OMAP4)
1220 if (bank->method == METHOD_GPIO_24XX)
1221 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1222#endif
1120 while(1) { 1223 while(1) {
1121 u32 isr_saved, level_mask = 0; 1224 u32 isr_saved, level_mask = 0;
1122 u32 enabled; 1225 u32 enabled;
@@ -1547,7 +1650,7 @@ static int __init _omap_gpio_init(void)
1547 1650
1548 gpio_bank_count = OMAP34XX_NR_GPIOS; 1651 gpio_bank_count = OMAP34XX_NR_GPIOS;
1549 gpio_bank = gpio_bank_44xx; 1652 gpio_bank = gpio_bank_44xx;
1550 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION); 1653 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1551 printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n", 1654 printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
1552 (rev >> 4) & 0x0f, rev & 0x0f); 1655 (rev >> 4) & 0x0f, rev & 0x0f);
1553 } 1656 }
@@ -1581,7 +1684,16 @@ static int __init _omap_gpio_init(void)
1581 static const u32 non_wakeup_gpios[] = { 1684 static const u32 non_wakeup_gpios[] = {
1582 0xe203ffc0, 0x08700040 1685 0xe203ffc0, 0x08700040
1583 }; 1686 };
1584 1687 if (cpu_is_omap44xx()) {
1688 __raw_writel(0xffffffff, bank->base +
1689 OMAP4_GPIO_IRQSTATUSCLR0);
1690 __raw_writew(0x0015, bank->base +
1691 OMAP4_GPIO_SYSCONFIG);
1692 __raw_writel(0x00000000, bank->base +
1693 OMAP4_GPIO_DEBOUNCENABLE);
1694 /* Initialize interface clock ungated, module enabled */
1695 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1696 } else {
1585 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1); 1697 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1586 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1); 1698 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1587 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG); 1699 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
@@ -1589,12 +1701,12 @@ static int __init _omap_gpio_init(void)
1589 1701
1590 /* Initialize interface clock ungated, module enabled */ 1702 /* Initialize interface clock ungated, module enabled */
1591 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); 1703 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1704 }
1592 if (i < ARRAY_SIZE(non_wakeup_gpios)) 1705 if (i < ARRAY_SIZE(non_wakeup_gpios))
1593 bank->non_wakeup_gpios = non_wakeup_gpios[i]; 1706 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1594 gpio_count = 32; 1707 gpio_count = 32;
1595 } 1708 }
1596#endif 1709#endif
1597
1598 /* REVISIT eventually switch from OMAP-specific gpio structs 1710 /* REVISIT eventually switch from OMAP-specific gpio structs
1599 * over to the generic ones 1711 * over to the generic ones
1600 */ 1712 */
@@ -1680,14 +1792,20 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1680 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1792 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1681 break; 1793 break;
1682#endif 1794#endif
1683#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1795#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1684 defined(CONFIG_ARCH_OMAP4)
1685 case METHOD_GPIO_24XX: 1796 case METHOD_GPIO_24XX:
1686 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; 1797 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1687 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1798 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1688 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; 1799 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1689 break; 1800 break;
1690#endif 1801#endif
1802#ifdef CONFIG_ARCH_OMAP4
1803 case METHOD_GPIO_24XX:
1804 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1805 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1806 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1807 break;
1808#endif
1691 default: 1809 default:
1692 continue; 1810 continue;
1693 } 1811 }
@@ -1722,13 +1840,18 @@ static int omap_gpio_resume(struct sys_device *dev)
1722 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1840 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1723 break; 1841 break;
1724#endif 1842#endif
1725#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1843#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1726 defined(CONFIG_ARCH_OMAP4)
1727 case METHOD_GPIO_24XX: 1844 case METHOD_GPIO_24XX:
1728 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1845 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1729 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; 1846 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1730 break; 1847 break;
1731#endif 1848#endif
1849#ifdef CONFIG_ARCH_OMAP4
1850 case METHOD_GPIO_24XX:
1851 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1852 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1853 break;
1854#endif
1732 default: 1855 default:
1733 continue; 1856 continue;
1734 } 1857 }
@@ -1772,21 +1895,29 @@ void omap2_gpio_prepare_for_retention(void)
1772 1895
1773 if (!(bank->enabled_non_wakeup_gpios)) 1896 if (!(bank->enabled_non_wakeup_gpios))
1774 continue; 1897 continue;
1775#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1898#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1776 defined(CONFIG_ARCH_OMAP4)
1777 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); 1899 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1778 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1900 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1779 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); 1901 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1780#endif 1902#endif
1903#ifdef CONFIG_ARCH_OMAP4
1904 bank->saved_datain = __raw_readl(bank->base +
1905 OMAP4_GPIO_DATAIN);
1906 l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
1907 l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
1908#endif
1781 bank->saved_fallingdetect = l1; 1909 bank->saved_fallingdetect = l1;
1782 bank->saved_risingdetect = l2; 1910 bank->saved_risingdetect = l2;
1783 l1 &= ~bank->enabled_non_wakeup_gpios; 1911 l1 &= ~bank->enabled_non_wakeup_gpios;
1784 l2 &= ~bank->enabled_non_wakeup_gpios; 1912 l2 &= ~bank->enabled_non_wakeup_gpios;
1785#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1913#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1786 defined(CONFIG_ARCH_OMAP4)
1787 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1914 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1788 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT); 1915 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1789#endif 1916#endif
1917#ifdef CONFIG_ARCH_OMAP4
1918 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1919 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1920#endif
1790 c++; 1921 c++;
1791 } 1922 }
1792 if (!c) { 1923 if (!c) {
@@ -1808,27 +1939,29 @@ void omap2_gpio_resume_after_retention(void)
1808 1939
1809 if (!(bank->enabled_non_wakeup_gpios)) 1940 if (!(bank->enabled_non_wakeup_gpios))
1810 continue; 1941 continue;
1811#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1942#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1812 defined(CONFIG_ARCH_OMAP4)
1813 __raw_writel(bank->saved_fallingdetect, 1943 __raw_writel(bank->saved_fallingdetect,
1814 bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1944 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1815 __raw_writel(bank->saved_risingdetect, 1945 __raw_writel(bank->saved_risingdetect,
1816 bank->base + OMAP24XX_GPIO_RISINGDETECT); 1946 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1947 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1948#endif
1949#ifdef CONFIG_ARCH_OMAP4
1950 __raw_writel(bank->saved_fallingdetect,
1951 bank->base + OMAP4_GPIO_FALLINGDETECT);
1952 __raw_writel(bank->saved_risingdetect,
1953 bank->base + OMAP4_GPIO_RISINGDETECT);
1954 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1817#endif 1955#endif
1818 /* Check if any of the non-wakeup interrupt GPIOs have changed 1956 /* Check if any of the non-wakeup interrupt GPIOs have changed
1819 * state. If so, generate an IRQ by software. This is 1957 * state. If so, generate an IRQ by software. This is
1820 * horribly racy, but it's the best we can do to work around 1958 * horribly racy, but it's the best we can do to work around
1821 * this silicon bug. */ 1959 * this silicon bug. */
1822#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1823 defined(CONFIG_ARCH_OMAP4)
1824 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1825#endif
1826 l ^= bank->saved_datain; 1960 l ^= bank->saved_datain;
1827 l &= bank->non_wakeup_gpios; 1961 l &= bank->non_wakeup_gpios;
1828 if (l) { 1962 if (l) {
1829 u32 old0, old1; 1963 u32 old0, old1;
1830#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ 1964#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1831 defined(CONFIG_ARCH_OMAP4)
1832 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); 1965 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1833 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); 1966 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1834 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0); 1967 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
@@ -1836,6 +1969,20 @@ void omap2_gpio_resume_after_retention(void)
1836 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0); 1969 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1837 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1); 1970 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1838#endif 1971#endif
1972#ifdef CONFIG_ARCH_OMAP4
1973 old0 = __raw_readl(bank->base +
1974 OMAP4_GPIO_LEVELDETECT0);
1975 old1 = __raw_readl(bank->base +
1976 OMAP4_GPIO_LEVELDETECT1);
1977 __raw_writel(old0 | l, bank->base +
1978 OMAP4_GPIO_LEVELDETECT0);
1979 __raw_writel(old1 | l, bank->base +
1980 OMAP4_GPIO_LEVELDETECT1);
1981 __raw_writel(old0, bank->base +
1982 OMAP4_GPIO_LEVELDETECT0);
1983 __raw_writel(old1, bank->base +
1984 OMAP4_GPIO_LEVELDETECT1);
1985#endif
1839 } 1986 }
1840 } 1987 }
1841 1988
diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h
index 7b939cc01962..72f680b7180d 100644
--- a/arch/arm/plat-omap/include/mach/dma.h
+++ b/arch/arm/plat-omap/include/mach/dma.h
@@ -122,6 +122,11 @@
122#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0) 122#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
123#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4) 123#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
124 124
125/* Additional registers available on OMAP4 */
126#define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0)
127#define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4)
128#define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8)
129
125/* Dummy defines to keep multi-omap compiles happy */ 130/* Dummy defines to keep multi-omap compiles happy */
126#define OMAP1_DMA_REVISION 0 131#define OMAP1_DMA_REVISION 0
127#define OMAP1_DMA_IRQSTATUS_L0 0 132#define OMAP1_DMA_IRQSTATUS_L0 0
@@ -311,6 +316,89 @@
311#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ 316#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
312#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ 317#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
313 318
319/* DMA request lines for 44xx */
320#define OMAP44XX_DMA_DSS_DISPC_REQ 6 /* S_DMA_5 */
321#define OMAP44XX_DMA_SYS_REQ2 7 /* S_DMA_6 */
322#define OMAP44XX_DMA_ISS_REQ1 9 /* S_DMA_8 */
323#define OMAP44XX_DMA_ISS_REQ2 10 /* S_DMA_9 */
324#define OMAP44XX_DMA_ISS_REQ3 12 /* S_DMA_11 */
325#define OMAP44XX_DMA_ISS_REQ4 13 /* S_DMA_12 */
326#define OMAP44XX_DMA_DSS_RFBI_REQ 14 /* S_DMA_13 */
327#define OMAP44XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
328#define OMAP44XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
329#define OMAP44XX_DMA_MCBSP2_TX 17 /* S_DMA_16 */
330#define OMAP44XX_DMA_MCBSP2_RX 18 /* S_DMA_17 */
331#define OMAP44XX_DMA_MCBSP3_TX 19 /* S_DMA_18 */
332#define OMAP44XX_DMA_MCBSP3_RX 20 /* S_DMA_19 */
333#define OMAP44XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
334#define OMAP44XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
335#define OMAP44XX_DMA_I2C3_TX 25 /* S_DMA_24 */
336#define OMAP44XX_DMA_I2C3_RX 26 /* S_DMA_25 */
337#define OMAP44XX_DMA_I2C1_TX 27 /* S_DMA_26 */
338#define OMAP44XX_DMA_I2C1_RX 28 /* S_DMA_27 */
339#define OMAP44XX_DMA_I2C2_TX 29 /* S_DMA_28 */
340#define OMAP44XX_DMA_I2C2_RX 30 /* S_DMA_29 */
341#define OMAP44XX_DMA_MCBSP4_TX 31 /* S_DMA_30 */
342#define OMAP44XX_DMA_MCBSP4_RX 32 /* S_DMA_31 */
343#define OMAP44XX_DMA_MCBSP1_TX 33 /* S_DMA_32 */
344#define OMAP44XX_DMA_MCBSP1_RX 34 /* S_DMA_33 */
345#define OMAP44XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
346#define OMAP44XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
347#define OMAP44XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
348#define OMAP44XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
349#define OMAP44XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
350#define OMAP44XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
351#define OMAP44XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
352#define OMAP44XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
353#define OMAP44XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
354#define OMAP44XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
355#define OMAP44XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
356#define OMAP44XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
357#define OMAP44XX_DMA_MMC2_TX 47 /* S_DMA_46 */
358#define OMAP44XX_DMA_MMC2_RX 48 /* S_DMA_47 */
359#define OMAP44XX_DMA_UART1_TX 49 /* S_DMA_48 */
360#define OMAP44XX_DMA_UART1_RX 50 /* S_DMA_49 */
361#define OMAP44XX_DMA_UART2_TX 51 /* S_DMA_50 */
362#define OMAP44XX_DMA_UART2_RX 52 /* S_DMA_51 */
363#define OMAP44XX_DMA_UART3_TX 53 /* S_DMA_52 */
364#define OMAP44XX_DMA_UART3_RX 54 /* S_DMA_53 */
365#define OMAP44XX_DMA_UART4_TX 55 /* S_DMA_54 */
366#define OMAP44XX_DMA_UART4_RX 56 /* S_DMA_55 */
367#define OMAP44XX_DMA_MMC4_TX 57 /* S_DMA_56 */
368#define OMAP44XX_DMA_MMC4_RX 58 /* S_DMA_57 */
369#define OMAP44XX_DMA_MMC5_TX 59 /* S_DMA_58 */
370#define OMAP44XX_DMA_MMC5_RX 60 /* S_DMA_59 */
371#define OMAP44XX_DMA_MMC1_TX 61 /* S_DMA_60 */
372#define OMAP44XX_DMA_MMC1_RX 62 /* S_DMA_61 */
373#define OMAP44XX_DMA_SYS_REQ3 64 /* S_DMA_63 */
374#define OMAP44XX_DMA_MCPDM_UP 65 /* S_DMA_64 */
375#define OMAP44XX_DMA_MCPDM_DL 66 /* S_DMA_65 */
376#define OMAP44XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
377#define OMAP44XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
378#define OMAP44XX_DMA_DSS_DSI1_REQ0 72 /* S_DMA_71 */
379#define OMAP44XX_DMA_DSS_DSI1_REQ1 73 /* S_DMA_72 */
380#define OMAP44XX_DMA_DSS_DSI1_REQ2 74 /* S_DMA_73 */
381#define OMAP44XX_DMA_DSS_DSI1_REQ3 75 /* S_DMA_74 */
382#define OMAP44XX_DMA_DSS_HDMI_REQ 76 /* S_DMA_75 */
383#define OMAP44XX_DMA_MMC3_TX 77 /* S_DMA_76 */
384#define OMAP44XX_DMA_MMC3_RX 78 /* S_DMA_77 */
385#define OMAP44XX_DMA_USIM_TX 79 /* S_DMA_78 */
386#define OMAP44XX_DMA_USIM_RX 80 /* S_DMA_79 */
387#define OMAP44XX_DMA_DSS_DSI2_REQ0 81 /* S_DMA_80 */
388#define OMAP44XX_DMA_DSS_DSI2_REQ1 82 /* S_DMA_81 */
389#define OMAP44XX_DMA_DSS_DSI2_REQ2 83 /* S_DMA_82 */
390#define OMAP44XX_DMA_DSS_DSI2_REQ3 84 /* S_DMA_83 */
391#define OMAP44XX_DMA_ABE_REQ0 101 /* S_DMA_100 */
392#define OMAP44XX_DMA_ABE_REQ1 102 /* S_DMA_101 */
393#define OMAP44XX_DMA_ABE_REQ2 103 /* S_DMA_102 */
394#define OMAP44XX_DMA_ABE_REQ3 104 /* S_DMA_103 */
395#define OMAP44XX_DMA_ABE_REQ4 105 /* S_DMA_104 */
396#define OMAP44XX_DMA_ABE_REQ5 106 /* S_DMA_105 */
397#define OMAP44XX_DMA_ABE_REQ6 107 /* S_DMA_106 */
398#define OMAP44XX_DMA_ABE_REQ7 108 /* S_DMA_107 */
399#define OMAP44XX_DMA_I2C4_TX 124 /* S_DMA_123 */
400#define OMAP44XX_DMA_I2C4_RX 125 /* S_DMA_124 */
401
314/*----------------------------------------------------------------------------*/ 402/*----------------------------------------------------------------------------*/
315 403
316/* Hardware registers for LCD DMA */ 404/* Hardware registers for LCD DMA */
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
index bb154ea76769..ec6f81e06d39 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
@@ -53,6 +53,11 @@
53#define OMAP34XX_MCBSP4_BASE 0x49026000 53#define OMAP34XX_MCBSP4_BASE 0x49026000
54#define OMAP34XX_MCBSP5_BASE 0x48096000 54#define OMAP34XX_MCBSP5_BASE 0x48096000
55 55
56#define OMAP44XX_MCBSP1_BASE 0x49022000
57#define OMAP44XX_MCBSP2_BASE 0x49024000
58#define OMAP44XX_MCBSP3_BASE 0x49026000
59#define OMAP44XX_MCBSP4_BASE 0x48074000
60
56#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) 61#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
57 62
58#define OMAP_MCBSP_REG_DRR2 0x00 63#define OMAP_MCBSP_REG_DRR2 0x00
@@ -98,7 +103,8 @@
98#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX 103#define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX
99#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX 104#define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX
100 105
101#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) 106#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
107 defined(CONFIG_ARCH_OMAP4)
102 108
103#define OMAP_MCBSP_REG_DRR2 0x00 109#define OMAP_MCBSP_REG_DRR2 0x00
104#define OMAP_MCBSP_REG_DRR1 0x04 110#define OMAP_MCBSP_REG_DRR1 0x04
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index efa0e0111f38..e42fa7cfc795 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -191,7 +191,7 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
191 OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2); 191 OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
192 OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1); 192 OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
193 OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0); 193 OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
194 if (cpu_is_omap2430() || cpu_is_omap34xx()) { 194 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
195 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr); 195 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
196 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr); 196 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
197 } 197 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 22:11:12 -0500