diff options
author | Will Deacon <will.deacon@arm.com> | 2011-11-14 11:24:58 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2011-11-21 08:12:18 -0500 |
commit | 11ed0ba1754841316d4095478944300acf19acc3 (patch) | |
tree | 2b7b1002398ca3bd035ec69fbec92ac6648fadf6 /arch/arm | |
parent | 6fe4c6d466e95d31164f14b1ac4aefb51f0f4f82 (diff) |
ARM: 7161/1: errata: no automatic store buffer drain
This patch implements a workaround for PL310 erratum 769419. On
revisions of the PL310 prior to r3p2, the Store Buffer does not
automatically drain. This can cause normal, non-cacheable writes to be
retained when the memory system is idle, leading to suboptimal I/O
performance for drivers using coherent DMA.
This patch adds an optional wmb() call to the cpu_idle loop. On systems
with an outer cache, this causes an explicit flush of the store buffer.
Cc: stable@vger.kernel.org
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/Kconfig | 12 | ||||
-rw-r--r-- | arch/arm/kernel/process.c | 3 |
2 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 44789eff983f..83aa746e71d6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -1352,6 +1352,18 @@ config ARM_ERRATA_764369 | |||
1352 | relevant cache maintenance functions and sets a specific bit | 1352 | relevant cache maintenance functions and sets a specific bit |
1353 | in the diagnostic control register of the SCU. | 1353 | in the diagnostic control register of the SCU. |
1354 | 1354 | ||
1355 | config PL310_ERRATA_769419 | ||
1356 | bool "PL310 errata: no automatic Store Buffer drain" | ||
1357 | depends on CACHE_L2X0 | ||
1358 | help | ||
1359 | On revisions of the PL310 prior to r3p2, the Store Buffer does | ||
1360 | not automatically drain. This can cause normal, non-cacheable | ||
1361 | writes to be retained when the memory system is idle, leading | ||
1362 | to suboptimal I/O performance for drivers using coherent DMA. | ||
1363 | This option adds a write barrier to the cpu_idle loop so that, | ||
1364 | on systems with an outer cache, the store buffer is drained | ||
1365 | explicitly. | ||
1366 | |||
1355 | endmenu | 1367 | endmenu |
1356 | 1368 | ||
1357 | source "arch/arm/common/Kconfig" | 1369 | source "arch/arm/common/Kconfig" |
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index 75316f0dd02a..3d0c6fb74ae4 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c | |||
@@ -192,6 +192,9 @@ void cpu_idle(void) | |||
192 | #endif | 192 | #endif |
193 | 193 | ||
194 | local_irq_disable(); | 194 | local_irq_disable(); |
195 | #ifdef CONFIG_PL310_ERRATA_769419 | ||
196 | wmb(); | ||
197 | #endif | ||
195 | if (hlt_counter) { | 198 | if (hlt_counter) { |
196 | local_irq_enable(); | 199 | local_irq_enable(); |
197 | cpu_relax(); | 200 | cpu_relax(); |