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authorWolfram Sang <w.sang@pengutronix.de>2011-04-29 09:06:42 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-05-02 14:08:55 -0400
commitf295dc6874bf271253f70cb75a483d4a23911117 (patch)
treed3f37cbd0c0552cd83bee1d7cf77dc3d19df4ae0 /arch/arm
parent7635965891761a732a610aa7ad9371de742ef52b (diff)
ARM: mach-stmp378x: remove mach
This mach has not seen any updates since the initial inclusion besides generic cleanup. Furthermore: - The i.MX23 covered in mach-mxs is just a renamed version of the STMP378x. - mach-stmp378x has a lot of reinvented interfaces, leaking all sorts of mach-related includes into the drivers. One example is the dmaengine which does not use the linux dmaengine-API but some privately exported symbols. So drivers cannot be reused. mach-mxs does it better. - There is only one board defined (which I couldn't find any trace of despite being a development board). It has been converted to mach-mxs in a previous patch. Since the only user of this mach was converted, it means that mach-stmp378x can go. Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/configs/stmp378x_defconfig128
-rw-r--r--arch/arm/mach-stmp378x/Makefile2
-rw-r--r--arch/arm/mach-stmp378x/Makefile.boot3
-rw-r--r--arch/arm/mach-stmp378x/include/mach/entry-macro.S35
-rw-r--r--arch/arm/mach-stmp378x/include/mach/irqs.h95
-rw-r--r--arch/arm/mach-stmp378x/include/mach/pins.h151
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-apbh.h101
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-apbx.h119
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-audioin.h63
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-audioout.h104
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-bch.h56
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h88
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-dcp.h87
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-digctl.h38
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-dram.h27
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-dri.h45
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-ecc8.h39
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-emi.h25
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-gpmi.h78
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-i2c.h55
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-icoll.h45
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-ir.h23
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-lcdif.h195
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-lradc.h99
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-ocotp.h40
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h90
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-power.h63
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-pwm.h53
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-pxp.h140
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-rtc.h59
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-saif.h21
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-spdif.h49
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-ssp.h102
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-sydma.h23
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-timrot.h68
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-tvenc.h67
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-uartapp.h87
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h268
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h40
-rw-r--r--arch/arm/mach-stmp378x/include/mach/regs-usbphy.h37
-rw-r--r--arch/arm/mach-stmp378x/stmp378x.c299
-rw-r--r--arch/arm/mach-stmp378x/stmp378x.h25
-rw-r--r--arch/arm/mach-stmp378x/stmp378x_devb.c332
-rw-r--r--arch/arm/plat-stmp3xxx/Kconfig20
45 files changed, 0 insertions, 3585 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 23ecbdad6607..ca473b1669a3 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -185,7 +185,6 @@ machine-$(CONFIG_ARCH_EXYNOS4) := exynos4
185machine-$(CONFIG_ARCH_SA1100) := sa1100 185machine-$(CONFIG_ARCH_SA1100) := sa1100
186machine-$(CONFIG_ARCH_SHARK) := shark 186machine-$(CONFIG_ARCH_SHARK) := shark
187machine-$(CONFIG_ARCH_SHMOBILE) := shmobile 187machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
188machine-$(CONFIG_ARCH_STMP378X) := stmp378x
189machine-$(CONFIG_ARCH_TCC8K) := tcc8k 188machine-$(CONFIG_ARCH_TCC8K) := tcc8k
190machine-$(CONFIG_ARCH_TEGRA) := tegra 189machine-$(CONFIG_ARCH_TEGRA) := tegra
191machine-$(CONFIG_ARCH_U300) := u300 190machine-$(CONFIG_ARCH_U300) := u300
diff --git a/arch/arm/configs/stmp378x_defconfig b/arch/arm/configs/stmp378x_defconfig
deleted file mode 100644
index 1079c2b6eb3a..000000000000
--- a/arch/arm/configs/stmp378x_defconfig
+++ /dev/null
@@ -1,128 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_LOCALVERSION="-default"
3CONFIG_SYSVIPC=y
4CONFIG_POSIX_MQUEUE=y
5CONFIG_BSD_PROCESS_ACCT=y
6CONFIG_SYSFS_DEPRECATED_V2=y
7CONFIG_BLK_DEV_INITRD=y
8CONFIG_EXPERT=y
9CONFIG_SLAB=y
10CONFIG_MODULES=y
11CONFIG_MODULE_UNLOAD=y
12CONFIG_MODULE_FORCE_UNLOAD=y
13CONFIG_MODVERSIONS=y
14CONFIG_MODULE_SRCVERSION_ALL=y
15# CONFIG_BLK_DEV_BSG is not set
16CONFIG_ARCH_STMP3XXX=y
17CONFIG_ARCH_STMP378X=y
18CONFIG_NO_HZ=y
19CONFIG_HIGH_RES_TIMERS=y
20CONFIG_PREEMPT=y
21CONFIG_AEABI=y
22CONFIG_HIGHMEM=y
23CONFIG_ZBOOT_ROM_TEXT=0x0
24CONFIG_ZBOOT_ROM_BSS=0x0
25CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M"
26CONFIG_NET=y
27CONFIG_PACKET=y
28CONFIG_UNIX=y
29CONFIG_INET=y
30CONFIG_IP_MULTICAST=y
31CONFIG_IP_ADVANCED_ROUTER=y
32CONFIG_IP_MULTIPLE_TABLES=y
33CONFIG_IP_ROUTE_MULTIPATH=y
34CONFIG_IP_ROUTE_VERBOSE=y
35CONFIG_IP_PNP=y
36CONFIG_IP_PNP_DHCP=y
37CONFIG_IP_PNP_BOOTP=y
38CONFIG_IP_MROUTE=y
39CONFIG_IP_PIMSM_V1=y
40CONFIG_IP_PIMSM_V2=y
41CONFIG_SYN_COOKIES=y
42# CONFIG_INET_LRO is not set
43# CONFIG_IPV6 is not set
44CONFIG_NET_SCHED=y
45# CONFIG_WIRELESS is not set
46CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
47# CONFIG_STANDALONE is not set
48CONFIG_MTD=y
49CONFIG_MTD_CHAR=y
50CONFIG_MTD_NAND=y
51CONFIG_MTD_UBI=y
52CONFIG_MTD_UBI_GLUEBI=y
53CONFIG_BLK_DEV_LOOP=y
54CONFIG_BLK_DEV_CRYPTOLOOP=y
55CONFIG_BLK_DEV_RAM=y
56CONFIG_BLK_DEV_RAM_COUNT=4
57CONFIG_BLK_DEV_RAM_SIZE=6144
58# CONFIG_MISC_DEVICES is not set
59CONFIG_SCSI=y
60CONFIG_BLK_DEV_SD=y
61CONFIG_CHR_DEV_SG=y
62# CONFIG_SCSI_LOWLEVEL is not set
63CONFIG_INPUT_POLLDEV=y
64CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
65CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
66CONFIG_INPUT_EVDEV=y
67# CONFIG_KEYBOARD_ATKBD is not set
68# CONFIG_INPUT_MOUSE is not set
69CONFIG_INPUT_TOUCHSCREEN=y
70CONFIG_INPUT_MISC=y
71# CONFIG_SERIO_SERPORT is not set
72CONFIG_VT_HW_CONSOLE_BINDING=y
73# CONFIG_LEGACY_PTYS is not set
74CONFIG_HW_RANDOM=y
75CONFIG_DEBUG_GPIO=y
76CONFIG_GPIO_SYSFS=y
77# CONFIG_HWMON is not set
78CONFIG_FB=y
79CONFIG_BACKLIGHT_LCD_SUPPORT=y
80CONFIG_LCD_CLASS_DEVICE=y
81CONFIG_BACKLIGHT_CLASS_DEVICE=y
82# CONFIG_VGA_CONSOLE is not set
83CONFIG_FRAMEBUFFER_CONSOLE=y
84CONFIG_LOGO=y
85# CONFIG_HID_SUPPORT is not set
86# CONFIG_USB_SUPPORT is not set
87# CONFIG_DNOTIFY is not set
88CONFIG_TMPFS=y
89CONFIG_CONFIGFS_FS=m
90# CONFIG_MISC_FILESYSTEMS is not set
91# CONFIG_NETWORK_FILESYSTEMS is not set
92# CONFIG_ENABLE_MUST_CHECK is not set
93CONFIG_STRIP_ASM_SYMS=y
94CONFIG_DEBUG_KERNEL=y
95CONFIG_DEBUG_SHIRQ=y
96# CONFIG_SCHED_DEBUG is not set
97CONFIG_DEBUG_OBJECTS=y
98CONFIG_DEBUG_OBJECTS_SELFTEST=y
99CONFIG_DEBUG_OBJECTS_FREE=y
100CONFIG_DEBUG_OBJECTS_TIMERS=y
101CONFIG_DEBUG_SLAB=y
102CONFIG_DEBUG_SLAB_LEAK=y
103CONFIG_DEBUG_RT_MUTEXES=y
104CONFIG_PROVE_LOCKING=y
105CONFIG_DEBUG_SPINLOCK_SLEEP=y
106CONFIG_DEBUG_KOBJECT=y
107# CONFIG_DEBUG_BUGVERBOSE is not set
108CONFIG_DEBUG_INFO=y
109# CONFIG_RCU_CPU_STALL_DETECTOR is not set
110CONFIG_SYSCTL_SYSCALL_CHECK=y
111CONFIG_BOOT_TRACER=y
112CONFIG_STACK_TRACER=y
113CONFIG_BLK_DEV_IO_TRACE=y
114CONFIG_KEYS=y
115CONFIG_KEYS_DEBUG_PROC_KEYS=y
116CONFIG_SECURITY=y
117CONFIG_CRYPTO_TEST=m
118CONFIG_CRYPTO_ECB=y
119CONFIG_CRYPTO_HMAC=y
120CONFIG_CRYPTO_MD5=y
121CONFIG_CRYPTO_SHA1=m
122CONFIG_CRYPTO_AES=m
123CONFIG_CRYPTO_DES=y
124CONFIG_CRYPTO_DEFLATE=y
125CONFIG_CRYPTO_LZO=y
126# CONFIG_CRYPTO_ANSI_CPRNG is not set
127CONFIG_CRC_CCITT=m
128CONFIG_CRC16=y
diff --git a/arch/arm/mach-stmp378x/Makefile b/arch/arm/mach-stmp378x/Makefile
deleted file mode 100644
index d156f76b379f..000000000000
--- a/arch/arm/mach-stmp378x/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
1obj-$(CONFIG_ARCH_STMP378X) += stmp378x.o
2obj-$(CONFIG_MACH_STMP378X) += stmp378x_devb.o
diff --git a/arch/arm/mach-stmp378x/Makefile.boot b/arch/arm/mach-stmp378x/Makefile.boot
deleted file mode 100644
index 1568ad404d59..000000000000
--- a/arch/arm/mach-stmp378x/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1 zreladdr-y := 0x40008000
2params_phys-y := 0x40000100
3initrd_phys-y := 0x40800000
diff --git a/arch/arm/mach-stmp378x/include/mach/entry-macro.S b/arch/arm/mach-stmp378x/include/mach/entry-macro.S
deleted file mode 100644
index 731a92286da2..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/entry-macro.S
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Low-level IRQ helper macros for Freescale STMP378X
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18
19 .macro disable_fiq
20 .endm
21
22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
23
24 mov \base, #0xf0000000 @ vm address of IRQ controller
25 ldr \irqnr, [\base, #0x70] @ HW_ICOLL_STAT
26 cmp \irqnr, #0x7f
27 moveqs \irqnr, #0 @ Zero flag set for no IRQ
28
29 .endm
30
31 .macro get_irqnr_preamble, base, tmp
32 .endm
33
34 .macro arch_ret_to_user, tmp1, tmp2
35 .endm
diff --git a/arch/arm/mach-stmp378x/include/mach/irqs.h b/arch/arm/mach-stmp378x/include/mach/irqs.h
deleted file mode 100644
index cc59673becdd..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/irqs.h
+++ /dev/null
@@ -1,95 +0,0 @@
1/*
2 * Freescale STMP378X interrupts
3 *
4 * Copyright (C) 2005 Sigmatel Inc
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18
19#define IRQ_DEBUG_UART 0
20#define IRQ_COMMS_RX 1
21#define IRQ_COMMS_TX 1
22#define IRQ_SSP2_ERROR 2
23#define IRQ_VDD5V 3
24#define IRQ_HEADPHONE_SHORT 4
25#define IRQ_DAC_DMA 5
26#define IRQ_DAC_ERROR 6
27#define IRQ_ADC_DMA 7
28#define IRQ_ADC_ERROR 8
29#define IRQ_SPDIF_DMA 9
30#define IRQ_SAIF2_DMA 9
31#define IRQ_SPDIF_ERROR 10
32#define IRQ_SAIF1_IRQ 10
33#define IRQ_SAIF2_IRQ 10
34#define IRQ_USB_CTRL 11
35#define IRQ_USB_WAKEUP 12
36#define IRQ_GPMI_DMA 13
37#define IRQ_SSP1_DMA 14
38#define IRQ_SSP_ERROR 15
39#define IRQ_GPIO0 16
40#define IRQ_GPIO1 17
41#define IRQ_GPIO2 18
42#define IRQ_SAIF1_DMA 19
43#define IRQ_SSP2_DMA 20
44#define IRQ_ECC8_IRQ 21
45#define IRQ_RTC_ALARM 22
46#define IRQ_UARTAPP_TX_DMA 23
47#define IRQ_UARTAPP_INTERNAL 24
48#define IRQ_UARTAPP_RX_DMA 25
49#define IRQ_I2C_DMA 26
50#define IRQ_I2C_ERROR 27
51#define IRQ_TIMER0 28
52#define IRQ_TIMER1 29
53#define IRQ_TIMER2 30
54#define IRQ_TIMER3 31
55#define IRQ_BATT_BRNOUT 32
56#define IRQ_VDDD_BRNOUT 33
57#define IRQ_VDDIO_BRNOUT 34
58#define IRQ_VDD18_BRNOUT 35
59#define IRQ_TOUCH_DETECT 36
60#define IRQ_LRADC_CH0 37
61#define IRQ_LRADC_CH1 38
62#define IRQ_LRADC_CH2 39
63#define IRQ_LRADC_CH3 40
64#define IRQ_LRADC_CH4 41
65#define IRQ_LRADC_CH5 42
66#define IRQ_LRADC_CH6 43
67#define IRQ_LRADC_CH7 44
68#define IRQ_LCDIF_DMA 45
69#define IRQ_LCDIF_ERROR 46
70#define IRQ_DIGCTL_DEBUG_TRAP 47
71#define IRQ_RTC_1MSEC 48
72#define IRQ_DRI_DMA 49
73#define IRQ_DRI_ATTENTION 50
74#define IRQ_GPMI_ATTENTION 51
75#define IRQ_IR 52
76#define IRQ_DCP_VMI 53
77#define IRQ_DCP 54
78#define IRQ_BCH 56
79#define IRQ_PXP 57
80#define IRQ_UARTAPP2_TX_DMA 58
81#define IRQ_UARTAPP2_INTERNAL 59
82#define IRQ_UARTAPP2_RX_DMA 60
83#define IRQ_VDAC_DETECT 61
84#define IRQ_VDD5V_DROOP 64
85#define IRQ_DCDC4P2_BO 65
86
87
88#define NR_REAL_IRQS 128
89#define NR_IRQS (NR_REAL_IRQS + 32 * 3)
90
91/* All interrupts are FIQ capable */
92#define FIQ_START IRQ_DEBUG_UART
93
94/* Hard disk IRQ is a GPMI attention IRQ */
95#define IRQ_HARDDISK IRQ_GPMI_ATTENTION
diff --git a/arch/arm/mach-stmp378x/include/mach/pins.h b/arch/arm/mach-stmp378x/include/mach/pins.h
deleted file mode 100644
index 93f952d35969..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/pins.h
+++ /dev/null
@@ -1,151 +0,0 @@
1/*
2 * Freescale STMP378X SoC pin multiplexing
3 *
4 * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __ASM_ARCH_PINS_H
19#define __ASM_ARCH_PINS_H
20
21/*
22 * Define all STMP378x pins, a pin name corresponds to a STMP378x hardware
23 * interface this pin belongs to.
24 */
25
26/* Bank 0 */
27#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0)
28#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1)
29#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2)
30#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3)
31#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4)
32#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5)
33#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6)
34#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7)
35#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8)
36#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9)
37#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10)
38#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11)
39#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12)
40#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13)
41#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14)
42#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15)
43#define PINID_GPMI_CLE STMP3XXX_PINID(0, 16)
44#define PINID_GPMI_ALE STMP3XXX_PINID(0, 17)
45#define PINID_GMPI_CE2N STMP3XXX_PINID(0, 18)
46#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19)
47#define PINID_GPMI_RDY1 STMP3XXX_PINID(0, 20)
48#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 21)
49#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 22)
50#define PINID_GPMI_WPN STMP3XXX_PINID(0, 23)
51#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24)
52#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25)
53#define PINID_AUART1_CTS STMP3XXX_PINID(0, 26)
54#define PINID_AUART1_RTS STMP3XXX_PINID(0, 27)
55#define PINID_AUART1_RX STMP3XXX_PINID(0, 28)
56#define PINID_AUART1_TX STMP3XXX_PINID(0, 29)
57#define PINID_I2C_SCL STMP3XXX_PINID(0, 30)
58#define PINID_I2C_SDA STMP3XXX_PINID(0, 31)
59
60/* Bank 1 */
61#define PINID_LCD_D00 STMP3XXX_PINID(1, 0)
62#define PINID_LCD_D01 STMP3XXX_PINID(1, 1)
63#define PINID_LCD_D02 STMP3XXX_PINID(1, 2)
64#define PINID_LCD_D03 STMP3XXX_PINID(1, 3)
65#define PINID_LCD_D04 STMP3XXX_PINID(1, 4)
66#define PINID_LCD_D05 STMP3XXX_PINID(1, 5)
67#define PINID_LCD_D06 STMP3XXX_PINID(1, 6)
68#define PINID_LCD_D07 STMP3XXX_PINID(1, 7)
69#define PINID_LCD_D08 STMP3XXX_PINID(1, 8)
70#define PINID_LCD_D09 STMP3XXX_PINID(1, 9)
71#define PINID_LCD_D10 STMP3XXX_PINID(1, 10)
72#define PINID_LCD_D11 STMP3XXX_PINID(1, 11)
73#define PINID_LCD_D12 STMP3XXX_PINID(1, 12)
74#define PINID_LCD_D13 STMP3XXX_PINID(1, 13)
75#define PINID_LCD_D14 STMP3XXX_PINID(1, 14)
76#define PINID_LCD_D15 STMP3XXX_PINID(1, 15)
77#define PINID_LCD_D16 STMP3XXX_PINID(1, 16)
78#define PINID_LCD_D17 STMP3XXX_PINID(1, 17)
79#define PINID_LCD_RESET STMP3XXX_PINID(1, 18)
80#define PINID_LCD_RS STMP3XXX_PINID(1, 19)
81#define PINID_LCD_WR STMP3XXX_PINID(1, 20)
82#define PINID_LCD_CS STMP3XXX_PINID(1, 21)
83#define PINID_LCD_DOTCK STMP3XXX_PINID(1, 22)
84#define PINID_LCD_ENABLE STMP3XXX_PINID(1, 23)
85#define PINID_LCD_HSYNC STMP3XXX_PINID(1, 24)
86#define PINID_LCD_VSYNC STMP3XXX_PINID(1, 25)
87#define PINID_PWM0 STMP3XXX_PINID(1, 26)
88#define PINID_PWM1 STMP3XXX_PINID(1, 27)
89#define PINID_PWM2 STMP3XXX_PINID(1, 28)
90#define PINID_PWM3 STMP3XXX_PINID(1, 29)
91#define PINID_PWM4 STMP3XXX_PINID(1, 30)
92
93/* Bank 2 */
94#define PINID_SSP1_CMD STMP3XXX_PINID(2, 0)
95#define PINID_SSP1_DETECT STMP3XXX_PINID(2, 1)
96#define PINID_SSP1_DATA0 STMP3XXX_PINID(2, 2)
97#define PINID_SSP1_DATA1 STMP3XXX_PINID(2, 3)
98#define PINID_SSP1_DATA2 STMP3XXX_PINID(2, 4)
99#define PINID_SSP1_DATA3 STMP3XXX_PINID(2, 5)
100#define PINID_SSP1_SCK STMP3XXX_PINID(2, 6)
101#define PINID_ROTARYA STMP3XXX_PINID(2, 7)
102#define PINID_ROTARYB STMP3XXX_PINID(2, 8)
103#define PINID_EMI_A00 STMP3XXX_PINID(2, 9)
104#define PINID_EMI_A01 STMP3XXX_PINID(2, 10)
105#define PINID_EMI_A02 STMP3XXX_PINID(2, 11)
106#define PINID_EMI_A03 STMP3XXX_PINID(2, 12)
107#define PINID_EMI_A04 STMP3XXX_PINID(2, 13)
108#define PINID_EMI_A05 STMP3XXX_PINID(2, 14)
109#define PINID_EMI_A06 STMP3XXX_PINID(2, 15)
110#define PINID_EMI_A07 STMP3XXX_PINID(2, 16)
111#define PINID_EMI_A08 STMP3XXX_PINID(2, 17)
112#define PINID_EMI_A09 STMP3XXX_PINID(2, 18)
113#define PINID_EMI_A10 STMP3XXX_PINID(2, 19)
114#define PINID_EMI_A11 STMP3XXX_PINID(2, 20)
115#define PINID_EMI_A12 STMP3XXX_PINID(2, 21)
116#define PINID_EMI_BA0 STMP3XXX_PINID(2, 22)
117#define PINID_EMI_BA1 STMP3XXX_PINID(2, 23)
118#define PINID_EMI_CASN STMP3XXX_PINID(2, 24)
119#define PINID_EMI_CE0N STMP3XXX_PINID(2, 25)
120#define PINID_EMI_CE1N STMP3XXX_PINID(2, 26)
121#define PINID_GPMI_CE1N STMP3XXX_PINID(2, 27)
122#define PINID_GPMI_CE0N STMP3XXX_PINID(2, 28)
123#define PINID_EMI_CKE STMP3XXX_PINID(2, 29)
124#define PINID_EMI_RASN STMP3XXX_PINID(2, 30)
125#define PINID_EMI_WEN STMP3XXX_PINID(2, 31)
126
127/* Bank 3 */
128#define PINID_EMI_D00 STMP3XXX_PINID(3, 0)
129#define PINID_EMI_D01 STMP3XXX_PINID(3, 1)
130#define PINID_EMI_D02 STMP3XXX_PINID(3, 2)
131#define PINID_EMI_D03 STMP3XXX_PINID(3, 3)
132#define PINID_EMI_D04 STMP3XXX_PINID(3, 4)
133#define PINID_EMI_D05 STMP3XXX_PINID(3, 5)
134#define PINID_EMI_D06 STMP3XXX_PINID(3, 6)
135#define PINID_EMI_D07 STMP3XXX_PINID(3, 7)
136#define PINID_EMI_D08 STMP3XXX_PINID(3, 8)
137#define PINID_EMI_D09 STMP3XXX_PINID(3, 9)
138#define PINID_EMI_D10 STMP3XXX_PINID(3, 10)
139#define PINID_EMI_D11 STMP3XXX_PINID(3, 11)
140#define PINID_EMI_D12 STMP3XXX_PINID(3, 12)
141#define PINID_EMI_D13 STMP3XXX_PINID(3, 13)
142#define PINID_EMI_D14 STMP3XXX_PINID(3, 14)
143#define PINID_EMI_D15 STMP3XXX_PINID(3, 15)
144#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 16)
145#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 17)
146#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 18)
147#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 19)
148#define PINID_EMI_CLK STMP3XXX_PINID(3, 20)
149#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21)
150
151#endif /* __ASM_ARCH_PINS_H */
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h
deleted file mode 100644
index dbcf85b6ac2a..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h
+++ /dev/null
@@ -1,101 +0,0 @@
1/*
2 * stmp378x: APBH register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_APBH
22#define _MACH_REGS_APBH
23
24#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000)
25#define REGS_APBH_PHYS 0x80004000
26#define REGS_APBH_SIZE 0x2000
27
28#define HW_APBH_CTRL0 0x0
29#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
30#define BP_APBH_CTRL0_RESET_CHANNEL 16
31#define BM_APBH_CTRL0_CLKGATE 0x40000000
32#define BM_APBH_CTRL0_SFTRST 0x80000000
33
34#define HW_APBH_CTRL1 0x10
35#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
36#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
37
38#define HW_APBH_CTRL2 0x20
39
40#define HW_APBH_DEVSEL 0x30
41
42#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70)
43#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70)
44#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70)
45#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70)
46#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70)
47#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70)
48#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70)
49#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70)
50#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70)
51#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70)
52#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70)
53#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70)
54#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70)
55#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70)
56#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70)
57#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70)
58
59#define HW_APBH_CHn_NXTCMDAR 0x50
60
61#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0
62#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 1
63#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 2
64#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 3
65#define BM_APBH_CHn_CMD_COMMAND 0x00000003
66#define BP_APBH_CHn_CMD_COMMAND 0
67#define BM_APBH_CHn_CMD_CHAIN 0x00000004
68#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
69#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
70#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
71#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
72#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
73#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
74#define BP_APBH_CHn_CMD_CMDWORDS 12
75#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
76#define BP_APBH_CHn_CMD_XFER_COUNT 16
77
78#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70)
79#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70)
80#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70)
81#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70)
82#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70)
83#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70)
84#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70)
85#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70)
86#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70)
87#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70)
88#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70)
89#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70)
90#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70)
91#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70)
92#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70)
93#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70)
94
95#define HW_APBH_CHn_SEMA 0x80
96#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
97#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
98#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
99#define BP_APBH_CHn_SEMA_PHORE 16
100
101#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h
deleted file mode 100644
index 3b934a4d27f0..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h
+++ /dev/null
@@ -1,119 +0,0 @@
1/*
2 * stmp378x: APBX register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_APBX
22#define _MACH_REGS_APBX
23
24#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000)
25#define REGS_APBX_PHYS 0x80024000
26#define REGS_APBX_SIZE 0x2000
27
28#define HW_APBX_CTRL0 0x0
29#define BM_APBX_CTRL0_CLKGATE 0x40000000
30#define BM_APBX_CTRL0_SFTRST 0x80000000
31
32#define HW_APBX_CTRL1 0x10
33
34#define HW_APBX_CTRL2 0x20
35
36#define HW_APBX_CHANNEL_CTRL 0x30
37#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000
38#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16
39
40#define HW_APBX_DEVSEL 0x40
41
42#define HW_APBX_CH0_NXTCMDAR (0x110 + 0 * 0x70)
43#define HW_APBX_CH1_NXTCMDAR (0x110 + 1 * 0x70)
44#define HW_APBX_CH2_NXTCMDAR (0x110 + 2 * 0x70)
45#define HW_APBX_CH3_NXTCMDAR (0x110 + 3 * 0x70)
46#define HW_APBX_CH4_NXTCMDAR (0x110 + 4 * 0x70)
47#define HW_APBX_CH5_NXTCMDAR (0x110 + 5 * 0x70)
48#define HW_APBX_CH6_NXTCMDAR (0x110 + 6 * 0x70)
49#define HW_APBX_CH7_NXTCMDAR (0x110 + 7 * 0x70)
50#define HW_APBX_CH8_NXTCMDAR (0x110 + 8 * 0x70)
51#define HW_APBX_CH9_NXTCMDAR (0x110 + 9 * 0x70)
52#define HW_APBX_CH10_NXTCMDAR (0x110 + 10 * 0x70)
53#define HW_APBX_CH11_NXTCMDAR (0x110 + 11 * 0x70)
54#define HW_APBX_CH12_NXTCMDAR (0x110 + 12 * 0x70)
55#define HW_APBX_CH13_NXTCMDAR (0x110 + 13 * 0x70)
56#define HW_APBX_CH14_NXTCMDAR (0x110 + 14 * 0x70)
57#define HW_APBX_CH15_NXTCMDAR (0x110 + 15 * 0x70)
58
59#define HW_APBX_CHn_NXTCMDAR 0x110
60#define BM_APBX_CHn_CMD_COMMAND 0x00000003
61#define BP_APBX_CHn_CMD_COMMAND 0
62#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0
63#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 1
64#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 2
65#define BV_APBX_CHn_CMD_COMMAND__DMA_SENSE 3
66#define BM_APBX_CHn_CMD_CHAIN 0x00000004
67#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
68#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
69#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
70#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100
71#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
72#define BP_APBX_CHn_CMD_CMDWORDS 12
73#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
74#define BP_APBX_CHn_CMD_XFER_COUNT 16
75
76#define HW_APBX_CH0_BAR (0x130 + 0 * 0x70)
77#define HW_APBX_CH1_BAR (0x130 + 1 * 0x70)
78#define HW_APBX_CH2_BAR (0x130 + 2 * 0x70)
79#define HW_APBX_CH3_BAR (0x130 + 3 * 0x70)
80#define HW_APBX_CH4_BAR (0x130 + 4 * 0x70)
81#define HW_APBX_CH5_BAR (0x130 + 5 * 0x70)
82#define HW_APBX_CH6_BAR (0x130 + 6 * 0x70)
83#define HW_APBX_CH7_BAR (0x130 + 7 * 0x70)
84#define HW_APBX_CH8_BAR (0x130 + 8 * 0x70)
85#define HW_APBX_CH9_BAR (0x130 + 9 * 0x70)
86#define HW_APBX_CH10_BAR (0x130 + 10 * 0x70)
87#define HW_APBX_CH11_BAR (0x130 + 11 * 0x70)
88#define HW_APBX_CH12_BAR (0x130 + 12 * 0x70)
89#define HW_APBX_CH13_BAR (0x130 + 13 * 0x70)
90#define HW_APBX_CH14_BAR (0x130 + 14 * 0x70)
91#define HW_APBX_CH15_BAR (0x130 + 15 * 0x70)
92
93#define HW_APBX_CHn_BAR 0x130
94
95#define HW_APBX_CH0_SEMA (0x140 + 0 * 0x70)
96#define HW_APBX_CH1_SEMA (0x140 + 1 * 0x70)
97#define HW_APBX_CH2_SEMA (0x140 + 2 * 0x70)
98#define HW_APBX_CH3_SEMA (0x140 + 3 * 0x70)
99#define HW_APBX_CH4_SEMA (0x140 + 4 * 0x70)
100#define HW_APBX_CH5_SEMA (0x140 + 5 * 0x70)
101#define HW_APBX_CH6_SEMA (0x140 + 6 * 0x70)
102#define HW_APBX_CH7_SEMA (0x140 + 7 * 0x70)
103#define HW_APBX_CH8_SEMA (0x140 + 8 * 0x70)
104#define HW_APBX_CH9_SEMA (0x140 + 9 * 0x70)
105#define HW_APBX_CH10_SEMA (0x140 + 10 * 0x70)
106#define HW_APBX_CH11_SEMA (0x140 + 11 * 0x70)
107#define HW_APBX_CH12_SEMA (0x140 + 12 * 0x70)
108#define HW_APBX_CH13_SEMA (0x140 + 13 * 0x70)
109#define HW_APBX_CH14_SEMA (0x140 + 14 * 0x70)
110#define HW_APBX_CH15_SEMA (0x140 + 15 * 0x70)
111
112#define HW_APBX_CHn_SEMA 0x140
113#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
114#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
115#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
116#define BP_APBX_CHn_SEMA_PHORE 16
117
118#endif
119
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h b/arch/arm/mach-stmp378x/include/mach/regs-audioin.h
deleted file mode 100644
index 641ac6126f83..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * stmp378x: AUDIOIN register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000)
22#define REGS_AUDIOIN_PHYS 0x8004C000
23#define REGS_AUDIOIN_SIZE 0x2000
24
25#define HW_AUDIOIN_CTRL 0x0
26#define BM_AUDIOIN_CTRL_RUN 0x00000001
27#define BP_AUDIOIN_CTRL_RUN 0
28#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
29#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
30#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
31#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020
32#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
33#define BM_AUDIOIN_CTRL_SFTRST 0x80000000
34
35#define HW_AUDIOIN_STAT 0x10
36
37#define HW_AUDIOIN_ADCSRR 0x20
38
39#define HW_AUDIOIN_ADCVOLUME 0x30
40#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF
41#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0
42#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000
43#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16
44
45#define HW_AUDIOIN_ADCDEBUG 0x40
46
47#define HW_AUDIOIN_ADCVOL 0x50
48#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F
49#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0
50#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030
51#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4
52#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00
53#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8
54#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000
55#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12
56#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000
57
58#define HW_AUDIOIN_MICLINE 0x60
59
60#define HW_AUDIOIN_ANACLKCTRL 0x70
61#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000
62
63#define HW_AUDIOIN_DATA 0x80
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h b/arch/arm/mach-stmp378x/include/mach/regs-audioout.h
deleted file mode 100644
index f533e23694a0..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h
+++ /dev/null
@@ -1,104 +0,0 @@
1/*
2 * stmp378x: AUDIOOUT register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000)
22#define REGS_AUDIOOUT_PHYS 0x80048000
23#define REGS_AUDIOOUT_SIZE 0x2000
24
25#define HW_AUDIOOUT_CTRL 0x0
26#define BM_AUDIOOUT_CTRL_RUN 0x00000001
27#define BP_AUDIOOUT_CTRL_RUN 0
28#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
29#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
30#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
31#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040
32#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000
33#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
34
35#define HW_AUDIOOUT_STAT 0x10
36
37#define HW_AUDIOOUT_DACSRR 0x20
38#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF
39#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0
40#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000
41#define BP_AUDIOOUT_DACSRR_SRC_INT 16
42#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000
43#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24
44#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000
45#define BP_AUDIOOUT_DACSRR_BASEMULT 28
46
47#define HW_AUDIOOUT_DACVOLUME 0x30
48#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100
49#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
50#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000
51
52#define HW_AUDIOOUT_DACDEBUG 0x40
53
54#define HW_AUDIOOUT_HPVOL 0x50
55#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000
56#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000
57
58#define HW_AUDIOOUT_PWRDN 0x70
59#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001
60#define BP_AUDIOOUT_PWRDN_HEADPHONE 0
61#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010
62#define BM_AUDIOOUT_PWRDN_ADC 0x00000100
63#define BM_AUDIOOUT_PWRDN_DAC 0x00001000
64#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000
65#define BM_AUDIOOUT_PWRDN_SPEAKER 0x01000000
66
67#define HW_AUDIOOUT_REFCTRL 0x80
68#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0
69#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4
70#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00
71#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8
72#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000
73#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000
74#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000
75#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16
76#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000
77#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000
78#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20
79#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000
80#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000
81
82#define HW_AUDIOOUT_ANACTRL 0x90
83#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010
84#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
85
86#define HW_AUDIOOUT_TEST 0xA0
87#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000
88#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22
89
90#define HW_AUDIOOUT_BISTCTRL 0xB0
91
92#define HW_AUDIOOUT_BISTSTAT0 0xC0
93
94#define HW_AUDIOOUT_BISTSTAT1 0xD0
95
96#define HW_AUDIOOUT_ANACLKCTRL 0xE0
97#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000
98
99#define HW_AUDIOOUT_DATA 0xF0
100
101#define HW_AUDIOOUT_SPEAKERCTRL 0x100
102#define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x01000000
103
104#define HW_AUDIOOUT_VERSION 0x200
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-bch.h b/arch/arm/mach-stmp378x/include/mach/regs-bch.h
deleted file mode 100644
index 532d24650717..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-bch.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * stmp378x: BCH register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_BCH_BASE (STMP3XXX_REGS_BASE + 0xA000)
22#define REGS_BCH_PHYS 0x8000A000
23#define REGS_BCH_SIZE 0x2000
24
25#define HW_BCH_CTRL 0x0
26#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001
27#define BP_BCH_CTRL_COMPLETE_IRQ 0
28#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100
29
30#define HW_BCH_STATUS0 0x10
31#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004
32#define BM_BCH_STATUS0_CORRECTED 0x00000008
33#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00
34#define BP_BCH_STATUS0_STATUS_BLK0 8
35#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000
36#define BP_BCH_STATUS0_COMPLETED_CE 16
37
38#define HW_BCH_LAYOUTSELECT 0x70
39
40#define HW_BCH_FLASH0LAYOUT0 0x80
41#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF
42#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0
43#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000
44#define BP_BCH_FLASH0LAYOUT0_ECC0 12
45#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000
46#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16
47#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000
48#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24
49#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF
50#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0
51#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000
52#define BP_BCH_FLASH0LAYOUT1_ECCN 12
53#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000
54#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16
55
56#define HW_BCH_BLOCKNAME 0x150
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h
deleted file mode 100644
index 7c546afd57a3..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h
+++ /dev/null
@@ -1,88 +0,0 @@
1/*
2 * stmp378x: CLKCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_CLKCTRL
22#define _MACH_REGS_CLKCTRL
23
24#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000)
25#define REGS_CLKCTRL_PHYS 0x80040000
26#define REGS_CLKCTRL_SIZE 0x2000
27
28#define HW_CLKCTRL_PLLCTRL0 0x0
29#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
30
31#define HW_CLKCTRL_CPU 0x20
32#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
33#define BP_CLKCTRL_CPU_DIV_CPU 0
34
35#define HW_CLKCTRL_HBUS 0x30
36#define BM_CLKCTRL_HBUS_DIV 0x0000001F
37#define BP_CLKCTRL_HBUS_DIV 0
38#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
39
40#define HW_CLKCTRL_XBUS 0x40
41
42#define HW_CLKCTRL_XTAL 0x50
43#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
44
45#define HW_CLKCTRL_PIX 0x60
46#define BM_CLKCTRL_PIX_DIV 0x00000FFF
47#define BP_CLKCTRL_PIX_DIV 0
48#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
49
50#define HW_CLKCTRL_SSP 0x70
51
52#define HW_CLKCTRL_GPMI 0x80
53
54#define HW_CLKCTRL_SPDIF 0x90
55
56#define HW_CLKCTRL_EMI 0xA0
57#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
58#define BP_CLKCTRL_EMI_DIV_EMI 0
59#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
60#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
61#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
62#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
63
64#define HW_CLKCTRL_IR 0xB0
65
66#define HW_CLKCTRL_SAIF 0xC0
67
68#define HW_CLKCTRL_TV 0xD0
69
70#define HW_CLKCTRL_ETM 0xE0
71
72#define HW_CLKCTRL_FRAC 0xF0
73#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
74#define BP_CLKCTRL_FRAC_EMIFRAC 8
75#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
76#define BP_CLKCTRL_FRAC_PIXFRAC 16
77#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
78
79#define HW_CLKCTRL_FRAC1 0x100
80
81#define HW_CLKCTRL_CLKSEQ 0x110
82#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
83
84#define HW_CLKCTRL_RESET 0x120
85#define BM_CLKCTRL_RESET_DIG 0x00000001
86#define BP_CLKCTRL_RESET_DIG 0
87
88#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h b/arch/arm/mach-stmp378x/include/mach/regs-dcp.h
deleted file mode 100644
index fdedd00c0e28..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * stmp378x: DCP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DCP_BASE (STMP3XXX_REGS_BASE + 0x28000)
22#define REGS_DCP_PHYS 0x80028000
23#define REGS_DCP_SIZE 0x2000
24
25#define HW_DCP_CTRL 0x0
26#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0x000000FF
27#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0
28#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x00400000
29#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x00800000
30#define BM_DCP_CTRL_CLKGATE 0x40000000
31#define BM_DCP_CTRL_SFTRST 0x80000000
32
33#define HW_DCP_STAT 0x10
34#define BM_DCP_STAT_IRQ 0x0000000F
35#define BP_DCP_STAT_IRQ 0
36
37#define HW_DCP_CHANNELCTRL 0x20
38#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0x000000FF
39#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0
40
41#define HW_DCP_CONTEXT 0x50
42#define BM_DCP_PACKET1_INTERRUPT 0x00000001
43#define BP_DCP_PACKET1_INTERRUPT 0
44#define BM_DCP_PACKET1_DECR_SEMAPHORE 0x00000002
45#define BM_DCP_PACKET1_CHAIN 0x00000004
46#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x00000008
47#define BM_DCP_PACKET1_ENABLE_CIPHER 0x00000020
48#define BM_DCP_PACKET1_ENABLE_HASH 0x00000040
49#define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x00000100
50#define BM_DCP_PACKET1_CIPHER_INIT 0x00000200
51#define BM_DCP_PACKET1_OTP_KEY 0x00000400
52#define BM_DCP_PACKET1_PAYLOAD_KEY 0x00000800
53#define BM_DCP_PACKET1_HASH_INIT 0x00001000
54#define BM_DCP_PACKET1_HASH_TERM 0x00002000
55#define BM_DCP_PACKET2_CIPHER_SELECT 0x0000000F
56#define BP_DCP_PACKET2_CIPHER_SELECT 0
57#define BM_DCP_PACKET2_CIPHER_MODE 0x000000F0
58#define BP_DCP_PACKET2_CIPHER_MODE 4
59#define BM_DCP_PACKET2_KEY_SELECT 0x0000FF00
60#define BP_DCP_PACKET2_KEY_SELECT 8
61#define BM_DCP_PACKET2_HASH_SELECT 0x000F0000
62#define BP_DCP_PACKET2_HASH_SELECT 16
63#define BM_DCP_PACKET2_CIPHER_CFG 0xFF000000
64#define BP_DCP_PACKET2_CIPHER_CFG 24
65
66#define HW_DCP_CH0CMDPTR (0x100 + 0 * 0x40)
67#define HW_DCP_CH1CMDPTR (0x100 + 1 * 0x40)
68#define HW_DCP_CH2CMDPTR (0x100 + 2 * 0x40)
69#define HW_DCP_CH3CMDPTR (0x100 + 3 * 0x40)
70
71#define HW_DCP_CHnCMDPTR 0x100
72
73#define HW_DCP_CH0SEMA (0x110 + 0 * 0x40)
74#define HW_DCP_CH1SEMA (0x110 + 1 * 0x40)
75#define HW_DCP_CH2SEMA (0x110 + 2 * 0x40)
76#define HW_DCP_CH3SEMA (0x110 + 3 * 0x40)
77
78#define HW_DCP_CHnSEMA 0x110
79#define BM_DCP_CHnSEMA_INCREMENT 0x000000FF
80#define BP_DCP_CHnSEMA_INCREMENT 0
81
82#define HW_DCP_CH0STAT (0x120 + 0 * 0x40)
83#define HW_DCP_CH1STAT (0x120 + 1 * 0x40)
84#define HW_DCP_CH2STAT (0x120 + 2 * 0x40)
85#define HW_DCP_CH3STAT (0x120 + 3 * 0x40)
86
87#define HW_DCP_CHnSTAT 0x120
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h b/arch/arm/mach-stmp378x/include/mach/regs-digctl.h
deleted file mode 100644
index 5293005523b3..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * stmp378x: DIGCTL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000)
22#define REGS_DIGCTL_PHYS 0x8001C000
23#define REGS_DIGCTL_SIZE 0x2000
24
25#define HW_DIGCTL_CTRL 0x0
26#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004
27
28#define HW_DIGCTL_ARMCACHE 0x2B0
29#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x00000003
30#define BP_DIGCTL_ARMCACHE_ITAG_SS 0
31#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x00000030
32#define BP_DIGCTL_ARMCACHE_DTAG_SS 4
33#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x00000300
34#define BP_DIGCTL_ARMCACHE_CACHE_SS 8
35#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x00003000
36#define BP_DIGCTL_ARMCACHE_DRTY_SS 12
37#define BM_DIGCTL_ARMCACHE_VALID_SS 0x00030000
38#define BP_DIGCTL_ARMCACHE_VALID_SS 16
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dram.h b/arch/arm/mach-stmp378x/include/mach/regs-dram.h
deleted file mode 100644
index 02851431677c..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-dram.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * stmp378x: DRAM register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DRAM_BASE (STMP3XXX_REGS_BASE + 0xE0000)
22#define REGS_DRAM_PHYS 0x800E0000
23#define REGS_DRAM_SIZE 0x2000
24
25#define HW_DRAM_CTL06 0x18
26
27#define HW_DRAM_CTL08 0x20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dri.h b/arch/arm/mach-stmp378x/include/mach/regs-dri.h
deleted file mode 100644
index da25f7e397e5..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-dri.h
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * stmp378x: DRI register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_DRI_BASE (STMP3XXX_REGS_BASE + 0x74000)
22#define REGS_DRI_PHYS 0x80074000
23#define REGS_DRI_SIZE 0x2000
24
25#define HW_DRI_CTRL 0x0
26#define BM_DRI_CTRL_RUN 0x00000001
27#define BP_DRI_CTRL_RUN 0
28#define BM_DRI_CTRL_ATTENTION_IRQ 0x00000002
29#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x00000004
30#define BM_DRI_CTRL_OVERFLOW_IRQ 0x00000008
31#define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x00000200
32#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x00000400
33#define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x00000800
34#define BM_DRI_CTRL_REACQUIRE_PHASE 0x00008000
35#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x02000000
36#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x04000000
37#define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000
38#define BM_DRI_CTRL_CLKGATE 0x40000000
39#define BM_DRI_CTRL_SFTRST 0x80000000
40
41#define HW_DRI_TIMING 0x10
42#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0x000000FF
43#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0
44#define BM_DRI_TIMING_PILOT_REP_RATE 0x000F0000
45#define BP_DRI_TIMING_PILOT_REP_RATE 16
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h b/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h
deleted file mode 100644
index cc353bec331b..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * stmp378x: ECC8 register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000)
22#define REGS_ECC8_PHYS 0x80008000
23#define REGS_ECC8_SIZE 0x2000
24
25#define HW_ECC8_CTRL 0x0
26#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001
27#define BP_ECC8_CTRL_COMPLETE_IRQ 0
28#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100
29#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000
30
31#define HW_ECC8_STATUS0 0x10
32#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004
33#define BM_ECC8_STATUS0_CORRECTED 0x00000008
34#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00
35#define BP_ECC8_STATUS0_STATUS_AUX 8
36#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000
37#define BP_ECC8_STATUS0_COMPLETED_CE 16
38
39#define HW_ECC8_STATUS1 0x20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-emi.h b/arch/arm/mach-stmp378x/include/mach/regs-emi.h
deleted file mode 100644
index 98773fc33d7b..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-emi.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * stmp378x: EMI register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_EMI_BASE (STMP3XXX_REGS_BASE + 0x20000)
22#define REGS_EMI_PHYS 0x80020000
23#define REGS_EMI_SIZE 0x2000
24
25#define HW_EMI_STAT 0x10
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h b/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h
deleted file mode 100644
index 2cc8bbe91687..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h
+++ /dev/null
@@ -1,78 +0,0 @@
1/*
2 * stmp378x: GPMI register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000)
22#define REGS_GPMI_PHYS 0x8000C000
23#define REGS_GPMI_SIZE 0x2000
24
25#define HW_GPMI_CTRL0 0x0
26#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_GPMI_CTRL0_XFER_COUNT 0
28#define BM_GPMI_CTRL0_CS 0x00300000
29#define BP_GPMI_CTRL0_CS 20
30#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
31#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
32#define BM_GPMI_CTRL0_ADDRESS 0x000E0000
33#define BP_GPMI_CTRL0_ADDRESS 17
34#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
35#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
36#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
37#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000
38#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
39#define BP_GPMI_CTRL0_COMMAND_MODE 24
40#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
41#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
42#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
43#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
44#define BM_GPMI_CTRL0_RUN 0x20000000
45#define BM_GPMI_CTRL0_CLKGATE 0x40000000
46#define BM_GPMI_CTRL0_SFTRST 0x80000000
47#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF
48#define BP_GPMI_ECCCTRL_BUFFER_MASK 0
49#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
50#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
51#define BP_GPMI_ECCCTRL_ECC_CMD 13
52#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0
53#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 1
54#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 2
55#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 3
56
57#define HW_GPMI_CTRL1 0x60
58#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
59#define BP_GPMI_CTRL1_GPMI_MODE 0
60#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
61#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
62#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
63#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
64#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
65#define BP_GPMI_CTRL1_RDN_DELAY 12
66#define BM_GPMI_CTRL1_BCH_MODE 0x00040000
67
68#define HW_GPMI_TIMING0 0x70
69#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
70#define BP_GPMI_TIMING0_DATA_SETUP 0
71#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
72#define BP_GPMI_TIMING0_DATA_HOLD 8
73#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000
74#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
75
76#define HW_GPMI_TIMING1 0x80
77#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
78#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h b/arch/arm/mach-stmp378x/include/mach/regs-i2c.h
deleted file mode 100644
index 13a234c99433..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * stmp378x: I2C register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000)
22#define REGS_I2C_PHYS 0x80058000
23#define REGS_I2C_SIZE 0x2000
24
25#define HW_I2C_CTRL0 0x0
26#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
27#define BP_I2C_CTRL0_XFER_COUNT 0
28#define BM_I2C_CTRL0_DIRECTION 0x00010000
29#define BM_I2C_CTRL0_MASTER_MODE 0x00020000
30#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000
31#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000
32#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000
33#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
34#define BM_I2C_CTRL0_CLKGATE 0x40000000
35#define BM_I2C_CTRL0_SFTRST 0x80000000
36
37#define HW_I2C_TIMING0 0x10
38
39#define HW_I2C_TIMING1 0x20
40
41#define HW_I2C_TIMING2 0x30
42
43#define HW_I2C_CTRL1 0x40
44#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001
45#define BP_I2C_CTRL1_SLAVE_IRQ 0
46#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002
47#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004
48#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008
49#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010
50#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020
51#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040
52#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080
53#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
54
55#define HW_I2C_VERSION 0x90
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h b/arch/arm/mach-stmp378x/include/mach/regs-icoll.h
deleted file mode 100644
index f996e80f40e7..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * stmp378x: ICOLL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_ICOLL
22#define _MACH_REGS_ICOLL
23
24#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0)
25#define REGS_ICOLL_PHYS 0x80000000
26#define REGS_ICOLL_SIZE 0x2000
27
28#define HW_ICOLL_VECTOR 0x0
29
30#define HW_ICOLL_LEVELACK 0x10
31#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F
32#define BP_ICOLL_LEVELACK_IRQLEVELACK 0
33
34#define HW_ICOLL_CTRL 0x20
35#define BM_ICOLL_CTRL_CLKGATE 0x40000000
36#define BM_ICOLL_CTRL_SFTRST 0x80000000
37
38#define HW_ICOLL_STAT 0x70
39
40#define HW_ICOLL_INTERRUPTn 0x120
41
42#define HW_ICOLL_INTERRUPTn 0x120
43#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004
44
45#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ir.h b/arch/arm/mach-stmp378x/include/mach/regs-ir.h
deleted file mode 100644
index a5b4ef10fab8..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-ir.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * stmp378x: IR register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_IR_BASE (STMP3XXX_REGS_BASE + 0x78000)
22#define REGS_IR_PHYS 0x80078000
23#define REGS_IR_SIZE 0x2000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h b/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h
deleted file mode 100644
index 9cdbef4badc3..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h
+++ /dev/null
@@ -1,195 +0,0 @@
1/*
2 * stmp378x: LCDIF register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000)
22#define REGS_LCDIF_PHYS 0x80030000
23#define REGS_LCDIF_SIZE 0x2000
24
25#define HW_LCDIF_CTRL 0x0
26#define BM_LCDIF_CTRL_RUN 0x00000001
27#define BP_LCDIF_CTRL_RUN 0
28#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020
29#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080
30#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300
31#define BP_LCDIF_CTRL_WORD_LENGTH 8
32#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00
33#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10
34#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000
35#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14
36#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000
37#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000
38#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000
39#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000
40#define BM_LCDIF_CTRL_DVI_MODE 0x00100000
41#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000
42#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21
43#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000
44#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000
45#define BM_LCDIF_CTRL_CLKGATE 0x40000000
46#define BM_LCDIF_CTRL_SFTRST 0x80000000
47
48#define HW_LCDIF_CTRL1 0x10
49#define BM_LCDIF_CTRL1_RESET 0x00000001
50#define BP_LCDIF_CTRL1_RESET 0
51#define BM_LCDIF_CTRL1_MODE86 0x00000002
52#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004
53#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100
54#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200
55#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400
56#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800
57#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000
58#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000
59#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16
60#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000
61#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000
62
63#define HW_LCDIF_TRANSFER_COUNT 0x20
64#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF
65#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0
66#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000
67#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16
68
69#define HW_LCDIF_CUR_BUF 0x30
70
71#define HW_LCDIF_NEXT_BUF 0x40
72
73#define HW_LCDIF_TIMING 0x60
74
75#define HW_LCDIF_VDCTRL0 0x70
76#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF
77#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0
78#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
79#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000
80#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000
81#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000
82#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000
83#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000
84#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
85#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000
86
87#define HW_LCDIF_VDCTRL1 0x80
88#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF
89#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0
90
91#define HW_LCDIF_VDCTRL2 0x90
92#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF
93#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0
94#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF000000
95#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 24
96
97#define HW_LCDIF_VDCTRL3 0xA0
98#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF
99#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0
100#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000
101#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16
102
103#define HW_LCDIF_VDCTRL4 0xB0
104#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF
105#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0
106#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000
107
108#define HW_LCDIF_DVICTRL0 0xC0
109#define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x000003FF
110#define BP_LCDIF_DVICTRL0_V_LINES_CNT 0
111#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x000FFC00
112#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10
113#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7FF00000
114#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20
115
116#define HW_LCDIF_DVICTRL1 0xD0
117#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF
118#define BP_LCDIF_DVICTRL1_F2_START_LINE 0
119#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00
120#define BP_LCDIF_DVICTRL1_F1_END_LINE 10
121#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000
122#define BP_LCDIF_DVICTRL1_F1_START_LINE 20
123
124#define HW_LCDIF_DVICTRL2 0xE0
125#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF
126#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0
127#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00
128#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10
129#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000
130#define BP_LCDIF_DVICTRL2_F2_END_LINE 20
131
132#define HW_LCDIF_DVICTRL3 0xF0
133#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000003FF
134#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0
135#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x03FF0000
136#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16
137
138#define HW_LCDIF_DVICTRL4 0x100
139#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF
140#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0
141#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00
142#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8
143#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000
144#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16
145#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000
146#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24
147
148#define HW_LCDIF_CSC_COEFF0 0x110
149#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003
150#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0
151#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000
152#define BP_LCDIF_CSC_COEFF0_C0 16
153
154#define HW_LCDIF_CSC_COEFF1 0x120
155#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF
156#define BP_LCDIF_CSC_COEFF1_C1 0
157#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000
158#define BP_LCDIF_CSC_COEFF1_C2 16
159
160#define HW_LCDIF_CSC_COEFF2 0x130
161#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF
162#define BP_LCDIF_CSC_COEFF2_C3 0
163#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000
164#define BP_LCDIF_CSC_COEFF2_C4 16
165
166#define HW_LCDIF_CSC_COEFF3 0x140
167#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF
168#define BP_LCDIF_CSC_COEFF3_C5 0
169#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000
170#define BP_LCDIF_CSC_COEFF3_C6 16
171
172#define HW_LCDIF_CSC_COEFF4 0x150
173#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF
174#define BP_LCDIF_CSC_COEFF4_C7 0
175#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000
176#define BP_LCDIF_CSC_COEFF4_C8 16
177
178#define HW_LCDIF_CSC_OFFSET 0x160
179#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF
180#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0
181#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000
182#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16
183
184#define HW_LCDIF_CSC_LIMIT 0x170
185#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF
186#define BP_LCDIF_CSC_LIMIT_Y_MAX 0
187#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00
188#define BP_LCDIF_CSC_LIMIT_Y_MIN 8
189#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000
190#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16
191#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000
192#define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24
193
194#define HW_LCDIF_STAT 0x1D0
195#define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h b/arch/arm/mach-stmp378x/include/mach/regs-lradc.h
deleted file mode 100644
index cb8cb06f8277..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h
+++ /dev/null
@@ -1,99 +0,0 @@
1/*
2 * stmp378x: LRADC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000)
22#define REGS_LRADC_PHYS 0x80050000
23#define REGS_LRADC_SIZE 0x2000
24
25#define HW_LRADC_CTRL0 0x0
26#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF
27#define BP_LRADC_CTRL0_SCHEDULE 0
28#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000
29#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000
30#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000
31#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000
32#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000
33#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000
34#define BM_LRADC_CTRL0_CLKGATE 0x40000000
35#define BM_LRADC_CTRL0_SFTRST 0x80000000
36
37#define HW_LRADC_CTRL1 0x10
38#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001
39#define BP_LRADC_CTRL1_LRADC0_IRQ 0
40#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020
41#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040
42#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100
43#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000
44#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000
45#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000
46
47#define HW_LRADC_CTRL2 0x20
48#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000
49#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16
50#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000
51#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000
52#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000
53#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24
54
55#define HW_LRADC_CTRL3 0x30
56#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300
57#define BP_LRADC_CTRL3_CYCLE_TIME 8
58
59#define HW_LRADC_STATUS 0x40
60#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001
61#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0
62
63#define HW_LRADC_CH0 (0x50 + 0 * 0x10)
64#define HW_LRADC_CH1 (0x50 + 1 * 0x10)
65#define HW_LRADC_CH2 (0x50 + 2 * 0x10)
66#define HW_LRADC_CH3 (0x50 + 3 * 0x10)
67#define HW_LRADC_CH4 (0x50 + 4 * 0x10)
68#define HW_LRADC_CH5 (0x50 + 5 * 0x10)
69#define HW_LRADC_CH6 (0x50 + 6 * 0x10)
70#define HW_LRADC_CH7 (0x50 + 7 * 0x10)
71
72#define HW_LRADC_CHn 0x50
73#define BM_LRADC_CHn_VALUE 0x0003FFFF
74#define BP_LRADC_CHn_VALUE 0
75#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000
76#define BP_LRADC_CHn_NUM_SAMPLES 24
77#define BM_LRADC_CHn_ACCUMULATE 0x20000000
78
79#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10)
80#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10)
81#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10)
82#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10)
83
84#define HW_LRADC_DELAYn 0xD0
85#define BM_LRADC_DELAYn_DELAY 0x000007FF
86#define BP_LRADC_DELAYn_DELAY 0
87#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800
88#define BP_LRADC_DELAYn_LOOP_COUNT 11
89#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000
90#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16
91#define BM_LRADC_DELAYn_KICK 0x00100000
92#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000
93#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24
94
95#define HW_LRADC_CTRL4 0x140
96#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000
97#define BP_LRADC_CTRL4_LRADC6SELECT 24
98#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000
99#define BP_LRADC_CTRL4_LRADC7SELECT 28
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h b/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h
deleted file mode 100644
index f0af64d9937e..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * stmp378x: OCOTP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_OCOTP_BASE (STMP3XXX_REGS_BASE + 0x2C000)
22#define REGS_OCOTP_PHYS 0x8002C000
23#define REGS_OCOTP_SIZE 0x2000
24
25#define HW_OCOTP_CTRL 0x0
26#define BM_OCOTP_CTRL_BUSY 0x00000100
27#define BM_OCOTP_CTRL_ERROR 0x00000200
28#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000
29#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000
30#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000
31#define BP_OCOTP_CTRL_WR_UNLOCK 16
32
33#define HW_OCOTP_DATA 0x10
34
35#define HW_OCOTP_CUST0 (0x20 + 0 * 0x10)
36#define HW_OCOTP_CUST1 (0x20 + 1 * 0x10)
37#define HW_OCOTP_CUST2 (0x20 + 2 * 0x10)
38#define HW_OCOTP_CUST3 (0x20 + 3 * 0x10)
39
40#define HW_OCOTP_CUSTn 0x20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h
deleted file mode 100644
index 50d90ea1b136..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h
+++ /dev/null
@@ -1,90 +0,0 @@
1/*
2 * stmp378x: PINCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_PINCTRL
22#define _MACH_REGS_PINCTRL
23
24#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000)
25#define REGS_PINCTRL_PHYS 0x80018000
26#define REGS_PINCTRL_SIZE 0x2000
27
28#define HW_PINCTRL_MUXSEL0 0x100
29#define HW_PINCTRL_MUXSEL1 0x110
30#define HW_PINCTRL_MUXSEL2 0x120
31#define HW_PINCTRL_MUXSEL3 0x130
32#define HW_PINCTRL_MUXSEL4 0x140
33#define HW_PINCTRL_MUXSEL5 0x150
34#define HW_PINCTRL_MUXSEL6 0x160
35#define HW_PINCTRL_MUXSEL7 0x170
36
37#define HW_PINCTRL_DRIVE0 0x200
38#define HW_PINCTRL_DRIVE1 0x210
39#define HW_PINCTRL_DRIVE2 0x220
40#define HW_PINCTRL_DRIVE3 0x230
41#define HW_PINCTRL_DRIVE4 0x240
42#define HW_PINCTRL_DRIVE5 0x250
43#define HW_PINCTRL_DRIVE6 0x260
44#define HW_PINCTRL_DRIVE7 0x270
45#define HW_PINCTRL_DRIVE8 0x280
46#define HW_PINCTRL_DRIVE9 0x290
47#define HW_PINCTRL_DRIVE10 0x2A0
48#define HW_PINCTRL_DRIVE11 0x2B0
49#define HW_PINCTRL_DRIVE12 0x2C0
50#define HW_PINCTRL_DRIVE13 0x2D0
51#define HW_PINCTRL_DRIVE14 0x2E0
52
53#define HW_PINCTRL_PULL0 0x400
54#define HW_PINCTRL_PULL1 0x410
55#define HW_PINCTRL_PULL2 0x420
56#define HW_PINCTRL_PULL3 0x430
57
58#define HW_PINCTRL_DOUT0 0x500
59#define HW_PINCTRL_DOUT1 0x510
60#define HW_PINCTRL_DOUT2 0x520
61
62#define HW_PINCTRL_DIN0 0x600
63#define HW_PINCTRL_DIN1 0x610
64#define HW_PINCTRL_DIN2 0x620
65
66#define HW_PINCTRL_DOE0 0x700
67#define HW_PINCTRL_DOE1 0x710
68#define HW_PINCTRL_DOE2 0x720
69
70#define HW_PINCTRL_PIN2IRQ0 0x800
71#define HW_PINCTRL_PIN2IRQ1 0x810
72#define HW_PINCTRL_PIN2IRQ2 0x820
73
74#define HW_PINCTRL_IRQEN0 0x900
75#define HW_PINCTRL_IRQEN1 0x910
76#define HW_PINCTRL_IRQEN2 0x920
77
78#define HW_PINCTRL_IRQLEVEL0 0xA00
79#define HW_PINCTRL_IRQLEVEL1 0xA10
80#define HW_PINCTRL_IRQLEVEL2 0xA20
81
82#define HW_PINCTRL_IRQPOL0 0xB00
83#define HW_PINCTRL_IRQPOL1 0xB10
84#define HW_PINCTRL_IRQPOL2 0xB20
85
86#define HW_PINCTRL_IRQSTAT0 0xC00
87#define HW_PINCTRL_IRQSTAT1 0xC10
88#define HW_PINCTRL_IRQSTAT2 0xC20
89
90#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-power.h b/arch/arm/mach-stmp378x/include/mach/regs-power.h
deleted file mode 100644
index e454c830f076..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-power.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * stmp378x: POWER register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_POWER
22#define _MACH_REGS_POWER
23
24#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000)
25#define REGS_POWER_PHYS 0x80044000
26#define REGS_POWER_SIZE 0x2000
27
28#define HW_POWER_CTRL 0x0
29#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001
30#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0
31#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000
32#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000
33#define BM_POWER_CTRL_CLKGATE 0x40000000
34
35#define HW_POWER_5VCTRL 0x10
36#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040
37
38#define HW_POWER_MINPWR 0x20
39
40#define HW_POWER_CHARGE 0x30
41
42#define HW_POWER_VDDDCTRL 0x40
43
44#define HW_POWER_VDDACTRL 0x50
45
46#define HW_POWER_VDDIOCTRL 0x60
47#define BM_POWER_VDDIOCTRL_TRG 0x0000001F
48#define BP_POWER_VDDIOCTRL_TRG 0
49
50#define HW_POWER_STS 0xC0
51#define BM_POWER_STS_VBUSVALID 0x00000002
52#define BM_POWER_STS_BVALID 0x00000004
53#define BM_POWER_STS_AVALID 0x00000008
54#define BM_POWER_STS_DC_OK 0x00000200
55
56#define HW_POWER_RESET 0x100
57
58#define HW_POWER_DEBUG 0x110
59#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002
60#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004
61#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
62
63#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h b/arch/arm/mach-stmp378x/include/mach/regs-pwm.h
deleted file mode 100644
index 0d0f9e56ec77..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * stmp378x: PWM register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000)
22#define REGS_PWM_PHYS 0x80064000
23#define REGS_PWM_SIZE 0x2000
24
25#define HW_PWM_CTRL 0x0
26#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
27#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020
28
29#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20)
30#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20)
31#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20)
32#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20)
33
34#define HW_PWM_ACTIVEn 0x10
35#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF
36#define BP_PWM_ACTIVEn_ACTIVE 0
37#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
38#define BP_PWM_ACTIVEn_INACTIVE 16
39
40#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20)
41#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20)
42#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20)
43#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20)
44
45#define HW_PWM_PERIODn 0x20
46#define BM_PWM_PERIODn_PERIOD 0x0000FFFF
47#define BP_PWM_PERIODn_PERIOD 0
48#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000
49#define BP_PWM_PERIODn_ACTIVE_STATE 16
50#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000
51#define BP_PWM_PERIODn_INACTIVE_STATE 18
52#define BM_PWM_PERIODn_CDIV 0x00700000
53#define BP_PWM_PERIODn_CDIV 20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h b/arch/arm/mach-stmp378x/include/mach/regs-pxp.h
deleted file mode 100644
index 54d297896de8..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h
+++ /dev/null
@@ -1,140 +0,0 @@
1/*
2 * stmp378x: PXP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_PXP_BASE (STMP3XXX_REGS_BASE + 0x2A000)
22#define REGS_PXP_PHYS 0x8002A000
23#define REGS_PXP_SIZE 0x2000
24
25#define HW_PXP_CTRL 0x0
26#define BM_PXP_CTRL_ENABLE 0x00000001
27#define BP_PXP_CTRL_ENABLE 0
28#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002
29#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT 0x000000F0
30#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT 4
31#define BM_PXP_CTRL_ROTATE 0x00000300
32#define BP_PXP_CTRL_ROTATE 8
33#define BM_PXP_CTRL_HFLIP 0x00000400
34#define BM_PXP_CTRL_VFLIP 0x00000800
35#define BM_PXP_CTRL_S0_FORMAT 0x0000F000
36#define BP_PXP_CTRL_S0_FORMAT 12
37#define BM_PXP_CTRL_SCALE 0x00040000
38#define BM_PXP_CTRL_CROP 0x00080000
39
40#define HW_PXP_STAT 0x10
41#define BM_PXP_STAT_IRQ 0x00000001
42#define BP_PXP_STAT_IRQ 0
43
44#define HW_PXP_RGBBUF 0x20
45
46#define HW_PXP_RGBSIZE 0x40
47#define BM_PXP_RGBSIZE_HEIGHT 0x00000FFF
48#define BP_PXP_RGBSIZE_HEIGHT 0
49#define BM_PXP_RGBSIZE_WIDTH 0x00FFF000
50#define BP_PXP_RGBSIZE_WIDTH 12
51
52#define HW_PXP_S0BUF 0x50
53
54#define HW_PXP_S0UBUF 0x60
55
56#define HW_PXP_S0VBUF 0x70
57
58#define HW_PXP_S0PARAM 0x80
59#define BM_PXP_S0PARAM_HEIGHT 0x000000FF
60#define BP_PXP_S0PARAM_HEIGHT 0
61#define BM_PXP_S0PARAM_WIDTH 0x0000FF00
62#define BP_PXP_S0PARAM_WIDTH 8
63#define BM_PXP_S0PARAM_YBASE 0x00FF0000
64#define BP_PXP_S0PARAM_YBASE 16
65#define BM_PXP_S0PARAM_XBASE 0xFF000000
66#define BP_PXP_S0PARAM_XBASE 24
67
68#define HW_PXP_S0BACKGROUND 0x90
69
70#define HW_PXP_S0CROP 0xA0
71#define BM_PXP_S0CROP_HEIGHT 0x000000FF
72#define BP_PXP_S0CROP_HEIGHT 0
73#define BM_PXP_S0CROP_WIDTH 0x0000FF00
74#define BP_PXP_S0CROP_WIDTH 8
75#define BM_PXP_S0CROP_YBASE 0x00FF0000
76#define BP_PXP_S0CROP_YBASE 16
77#define BM_PXP_S0CROP_XBASE 0xFF000000
78#define BP_PXP_S0CROP_XBASE 24
79
80#define HW_PXP_S0SCALE 0xB0
81#define BM_PXP_S0SCALE_XSCALE 0x00003FFF
82#define BP_PXP_S0SCALE_XSCALE 0
83#define BM_PXP_S0SCALE_YSCALE 0x3FFF0000
84#define BP_PXP_S0SCALE_YSCALE 16
85
86#define HW_PXP_CSCCOEFF0 0xD0
87
88#define HW_PXP_CSCCOEFF1 0xE0
89
90#define HW_PXP_CSCCOEFF2 0xF0
91
92#define HW_PXP_S0COLORKEYLOW 0x180
93
94#define HW_PXP_S0COLORKEYHIGH 0x190
95
96#define HW_PXP_OL0 (0x200 + 0 * 0x40)
97#define HW_PXP_OL1 (0x200 + 1 * 0x40)
98#define HW_PXP_OL2 (0x200 + 2 * 0x40)
99#define HW_PXP_OL3 (0x200 + 3 * 0x40)
100#define HW_PXP_OL4 (0x200 + 4 * 0x40)
101#define HW_PXP_OL5 (0x200 + 5 * 0x40)
102#define HW_PXP_OL6 (0x200 + 6 * 0x40)
103#define HW_PXP_OL7 (0x200 + 7 * 0x40)
104
105#define HW_PXP_OLn 0x200
106
107#define HW_PXP_OL0SIZE (0x210 + 0 * 0x40)
108#define HW_PXP_OL1SIZE (0x210 + 1 * 0x40)
109#define HW_PXP_OL2SIZE (0x210 + 2 * 0x40)
110#define HW_PXP_OL3SIZE (0x210 + 3 * 0x40)
111#define HW_PXP_OL4SIZE (0x210 + 4 * 0x40)
112#define HW_PXP_OL5SIZE (0x210 + 5 * 0x40)
113#define HW_PXP_OL6SIZE (0x210 + 6 * 0x40)
114#define HW_PXP_OL7SIZE (0x210 + 7 * 0x40)
115
116#define HW_PXP_OLnSIZE 0x210
117#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF
118#define BP_PXP_OLnSIZE_HEIGHT 0
119#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00
120#define BP_PXP_OLnSIZE_WIDTH 8
121
122#define HW_PXP_OL0PARAM (0x220 + 0 * 0x40)
123#define HW_PXP_OL1PARAM (0x220 + 1 * 0x40)
124#define HW_PXP_OL2PARAM (0x220 + 2 * 0x40)
125#define HW_PXP_OL3PARAM (0x220 + 3 * 0x40)
126#define HW_PXP_OL4PARAM (0x220 + 4 * 0x40)
127#define HW_PXP_OL5PARAM (0x220 + 5 * 0x40)
128#define HW_PXP_OL6PARAM (0x220 + 6 * 0x40)
129#define HW_PXP_OL7PARAM (0x220 + 7 * 0x40)
130
131#define HW_PXP_OLnPARAM 0x220
132#define BM_PXP_OLnPARAM_ENABLE 0x00000001
133#define BP_PXP_OLnPARAM_ENABLE 0
134#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006
135#define BP_PXP_OLnPARAM_ALPHA_CNTL 1
136#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008
137#define BM_PXP_OLnPARAM_FORMAT 0x000000F0
138#define BP_PXP_OLnPARAM_FORMAT 4
139#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00
140#define BP_PXP_OLnPARAM_ALPHA 8
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h b/arch/arm/mach-stmp378x/include/mach/regs-rtc.h
deleted file mode 100644
index b8dbd6742d98..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * stmp378x: RTC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000)
22#define REGS_RTC_PHYS 0x8005C000
23#define REGS_RTC_SIZE 0x2000
24
25#define HW_RTC_CTRL 0x0
26#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001
27#define BP_RTC_CTRL_ALARM_IRQ_EN 0
28#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
29#define BM_RTC_CTRL_ALARM_IRQ 0x00000004
30#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008
31#define BM_RTC_CTRL_WATCHDOGEN 0x00000010
32
33#define HW_RTC_STAT 0x10
34#define BM_RTC_STAT_NEW_REGS 0x0000FF00
35#define BP_RTC_STAT_NEW_REGS 8
36#define BM_RTC_STAT_STALE_REGS 0x00FF0000
37#define BP_RTC_STAT_STALE_REGS 16
38#define BM_RTC_STAT_RTC_PRESENT 0x80000000
39
40#define HW_RTC_SECONDS 0x30
41
42#define HW_RTC_ALARM 0x40
43
44#define HW_RTC_WATCHDOG 0x50
45
46#define HW_RTC_PERSISTENT0 0x60
47#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002
48#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004
49#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010
50#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020
51#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080
52#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
53#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
54
55#define HW_RTC_PERSISTENT1 0x70
56#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF
57#define BP_RTC_PERSISTENT1_GENERAL 0
58
59#define HW_RTC_VERSION 0xD0
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-saif.h b/arch/arm/mach-stmp378x/include/mach/regs-saif.h
deleted file mode 100644
index 6df41762c2a3..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-saif.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * stmp378x: SAIF register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SAIF_SIZE 0x2000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h b/arch/arm/mach-stmp378x/include/mach/regs-spdif.h
deleted file mode 100644
index 801539848c28..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h
+++ /dev/null
@@ -1,49 +0,0 @@
1/*
2 * stmp378x: SPDIF register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SPDIF_BASE (STMP3XXX_REGS_BASE + 0x54000)
22#define REGS_SPDIF_PHYS 0x80054000
23#define REGS_SPDIF_SIZE 0x2000
24
25#define HW_SPDIF_CTRL 0x0
26#define BM_SPDIF_CTRL_RUN 0x00000001
27#define BP_SPDIF_CTRL_RUN 0
28#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
29#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
30#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
31#define BM_SPDIF_CTRL_WORD_LENGTH 0x00000010
32#define BM_SPDIF_CTRL_CLKGATE 0x40000000
33#define BM_SPDIF_CTRL_SFTRST 0x80000000
34
35#define HW_SPDIF_STAT 0x10
36
37#define HW_SPDIF_FRAMECTRL 0x20
38
39#define HW_SPDIF_SRR 0x30
40#define BM_SPDIF_SRR_RATE 0x000FFFFF
41#define BP_SPDIF_SRR_RATE 0
42#define BM_SPDIF_SRR_BASEMULT 0x70000000
43#define BP_SPDIF_SRR_BASEMULT 28
44
45#define HW_SPDIF_DEBUG 0x40
46
47#define HW_SPDIF_DATA 0x50
48
49#define HW_SPDIF_VERSION 0x60
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h b/arch/arm/mach-stmp378x/include/mach/regs-ssp.h
deleted file mode 100644
index 28aacf0f58ed..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h
+++ /dev/null
@@ -1,102 +0,0 @@
1/*
2 * stmp378x: SSP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SSP1_BASE (STMP3XXX_REGS_BASE + 0x10000)
22#define REGS_SSP1_PHYS 0x80010000
23#define REGS_SSP2_BASE (STMP3XXX_REGS_BASE + 0x34000)
24#define REGS_SSP2_PHYS 0x80034000
25#define REGS_SSP_SIZE 0x2000
26
27#define HW_SSP_CTRL0 0x0
28#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
29#define BP_SSP_CTRL0_XFER_COUNT 0
30#define BM_SSP_CTRL0_ENABLE 0x00010000
31#define BM_SSP_CTRL0_GET_RESP 0x00020000
32#define BM_SSP_CTRL0_LONG_RESP 0x00080000
33#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000
34#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000
35#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000
36#define BP_SSP_CTRL0_BUS_WIDTH 22
37#define BM_SSP_CTRL0_DATA_XFER 0x01000000
38#define BM_SSP_CTRL0_READ 0x02000000
39#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
40#define BM_SSP_CTRL0_LOCK_CS 0x08000000
41#define BM_SSP_CTRL0_RUN 0x20000000
42#define BM_SSP_CTRL0_CLKGATE 0x40000000
43#define BM_SSP_CTRL0_SFTRST 0x80000000
44
45#define HW_SSP_CMD0 0x10
46#define BM_SSP_CMD0_CMD 0x000000FF
47#define BP_SSP_CMD0_CMD 0
48#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
49#define BP_SSP_CMD0_BLOCK_COUNT 8
50#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000
51#define BP_SSP_CMD0_BLOCK_SIZE 16
52#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
53#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF
54#define BP_SSP_CMD1_CMD_ARG 0
55
56#define HW_SSP_TIMING 0x50
57#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF
58#define BP_SSP_TIMING_CLOCK_RATE 0
59#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00
60#define BP_SSP_TIMING_CLOCK_DIVIDE 8
61#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000
62#define BP_SSP_TIMING_TIMEOUT 16
63
64#define HW_SSP_CTRL1 0x60
65#define BM_SSP_CTRL1_SSP_MODE 0x0000000F
66#define BP_SSP_CTRL1_SSP_MODE 0
67#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0
68#define BP_SSP_CTRL1_WORD_LENGTH 4
69#define BM_SSP_CTRL1_POLARITY 0x00000200
70#define BM_SSP_CTRL1_PHASE 0x00000400
71#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
72#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000
73#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000
74#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000
75#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000
76#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000
77#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000
78#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000
79#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000
80#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000
81#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000
82#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
83#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
84#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
85
86#define HW_SSP_DATA 0x70
87
88#define HW_SSP_SDRESP0 0x80
89
90#define HW_SSP_SDRESP1 0x90
91
92#define HW_SSP_SDRESP2 0xA0
93
94#define HW_SSP_SDRESP3 0xB0
95
96#define HW_SSP_STATUS 0xC0
97#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020
98#define BM_SSP_STATUS_TIMEOUT 0x00001000
99#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000
100#define BM_SSP_STATUS_RESP_ERR 0x00008000
101#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000
102#define BM_SSP_STATUS_CARD_DETECT 0x10000000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h b/arch/arm/mach-stmp378x/include/mach/regs-sydma.h
deleted file mode 100644
index 08343a8b5566..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * stmp378x: SYDMA register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_SYDMA_BASE (STMP3XXX_REGS_BASE + 0x26000)
22#define REGS_SYDMA_PHYS 0x80026000
23#define REGS_SYDMA_SIZE 0x2000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h b/arch/arm/mach-stmp378x/include/mach/regs-timrot.h
deleted file mode 100644
index b5527957c67f..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * stmp378x: TIMROT register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef _MACH_REGS_TIMROT
22#define _MACH_REGS_TIMROT
23
24#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000)
25#define REGS_TIMROT_PHYS 0x80068000
26#define REGS_TIMROT_SIZE 0x2000
27
28#define HW_TIMROT_ROTCTRL 0x0
29#define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007
30#define BP_TIMROT_ROTCTRL_SELECT_A 0
31#define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070
32#define BP_TIMROT_ROTCTRL_SELECT_B 4
33#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100
34#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200
35#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00
36#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10
37#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000
38#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000
39#define BP_TIMROT_ROTCTRL_DIVIDER 16
40#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000
41#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
42#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
43
44#define HW_TIMROT_ROTCOUNT 0x10
45#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF
46#define BP_TIMROT_ROTCOUNT_UPDOWN 0
47
48#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20)
49#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20)
50#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20)
51
52#define HW_TIMROT_TIMCTRLn 0x20
53#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
54#define BP_TIMROT_TIMCTRLn_SELECT 0
55#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
56#define BP_TIMROT_TIMCTRLn_PRESCALE 4
57#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
58#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
59#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
60#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
61
62#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20)
63#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20)
64#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20)
65
66#define HW_TIMROT_TIMCOUNTn 0x30
67
68#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h b/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h
deleted file mode 100644
index 7f895cb34350..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * stmp378x: TVENC register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_TVENC_BASE (STMP3XXX_REGS_BASE + 0x38000)
22#define REGS_TVENC_PHYS 0x80038000
23#define REGS_TVENC_SIZE 0x2000
24
25#define HW_TVENC_CTRL 0x0
26#define BM_TVENC_CTRL_CLKGATE 0x40000000
27#define BM_TVENC_CTRL_SFTRST 0x80000000
28
29#define HW_TVENC_CONFIG 0x10
30#define BM_TVENC_CONFIG_ENCD_MODE 0x00000007
31#define BP_TVENC_CONFIG_ENCD_MODE 0
32#define BM_TVENC_CONFIG_SYNC_MODE 0x00000070
33#define BP_TVENC_CONFIG_SYNC_MODE 4
34#define BM_TVENC_CONFIG_FSYNC_PHS 0x00000200
35#define BM_TVENC_CONFIG_CGAIN 0x0000C000
36#define BP_TVENC_CONFIG_CGAIN 14
37#define BM_TVENC_CONFIG_YGAIN_SEL 0x00030000
38#define BP_TVENC_CONFIG_YGAIN_SEL 16
39#define BM_TVENC_CONFIG_PAL_SHAPE 0x00100000
40
41#define HW_TVENC_SYNCOFFSET 0x30
42
43#define HW_TVENC_COLORSUB0 0xC0
44
45#define HW_TVENC_COLORBURST 0x140
46#define BM_TVENC_COLORBURST_PBA 0x00FF0000
47#define BP_TVENC_COLORBURST_PBA 16
48#define BM_TVENC_COLORBURST_NBA 0xFF000000
49#define BP_TVENC_COLORBURST_NBA 24
50
51#define HW_TVENC_MACROVISION0 0x150
52
53#define HW_TVENC_MACROVISION1 0x160
54
55#define HW_TVENC_MACROVISION2 0x170
56
57#define HW_TVENC_MACROVISION3 0x180
58
59#define HW_TVENC_MACROVISION4 0x190
60
61#define HW_TVENC_DACCTRL 0x1A0
62#define BM_TVENC_DACCTRL_RVAL 0x00000070
63#define BP_TVENC_DACCTRL_RVAL 4
64#define BM_TVENC_DACCTRL_DUMP_TOVDD1 0x00000100
65#define BM_TVENC_DACCTRL_PWRUP1 0x00001000
66#define BM_TVENC_DACCTRL_GAINUP 0x00040000
67#define BM_TVENC_DACCTRL_GAINDN 0x00080000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h b/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h
deleted file mode 100644
index a251e68bb3a1..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * stmp378x: UARTAPP register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_UARTAPP1_BASE (STMP3XXX_REGS_BASE + 0x6C000)
22#define REGS_UARTAPP1_PHYS 0x8006C000
23#define REGS_UARTAPP2_BASE (STMP3XXX_REGS_BASE + 0x6E000)
24#define REGS_UARTAPP2_PHYS 0x8006E000
25#define REGS_UARTAPP_SIZE 0x2000
26
27#define HW_UARTAPP_CTRL0 0x0
28#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF
29#define BP_UARTAPP_CTRL0_XFER_COUNT 0
30#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000
31#define BP_UARTAPP_CTRL0_RXTIMEOUT 16
32#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000
33#define BM_UARTAPP_CTRL0_RUN 0x20000000
34#define BM_UARTAPP_CTRL0_SFTRST 0x80000000
35#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF
36#define BP_UARTAPP_CTRL1_XFER_COUNT 0
37#define BM_UARTAPP_CTRL1_RUN 0x10000000
38
39#define HW_UARTAPP_CTRL2 0x20
40#define BM_UARTAPP_CTRL2_UARTEN 0x00000001
41#define BP_UARTAPP_CTRL2_UARTEN 0
42#define BM_UARTAPP_CTRL2_TXE 0x00000100
43#define BM_UARTAPP_CTRL2_RXE 0x00000200
44#define BM_UARTAPP_CTRL2_RTS 0x00000800
45#define BM_UARTAPP_CTRL2_RTSEN 0x00004000
46#define BM_UARTAPP_CTRL2_CTSEN 0x00008000
47#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000
48#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000
49#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000
50
51#define HW_UARTAPP_LINECTRL 0x30
52#define BM_UARTAPP_LINECTRL_BRK 0x00000001
53#define BP_UARTAPP_LINECTRL_BRK 0
54#define BM_UARTAPP_LINECTRL_PEN 0x00000002
55#define BM_UARTAPP_LINECTRL_EPS 0x00000004
56#define BM_UARTAPP_LINECTRL_STP2 0x00000008
57#define BM_UARTAPP_LINECTRL_FEN 0x00000010
58#define BM_UARTAPP_LINECTRL_WLEN 0x00000060
59#define BP_UARTAPP_LINECTRL_WLEN 5
60#define BM_UARTAPP_LINECTRL_SPS 0x00000080
61#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00
62#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8
63#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000
64#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16
65
66#define HW_UARTAPP_INTR 0x50
67#define BM_UARTAPP_INTR_CTSMIS 0x00000002
68#define BM_UARTAPP_INTR_RTIS 0x00000040
69#define BM_UARTAPP_INTR_CTSMIEN 0x00020000
70#define BM_UARTAPP_INTR_RXIEN 0x00100000
71#define BM_UARTAPP_INTR_RTIEN 0x00400000
72
73#define HW_UARTAPP_DATA 0x60
74
75#define HW_UARTAPP_STAT 0x70
76#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF
77#define BP_UARTAPP_STAT_RXCOUNT 0
78#define BM_UARTAPP_STAT_FERR 0x00010000
79#define BM_UARTAPP_STAT_PERR 0x00020000
80#define BM_UARTAPP_STAT_BERR 0x00040000
81#define BM_UARTAPP_STAT_OERR 0x00080000
82#define BM_UARTAPP_STAT_RXFE 0x01000000
83#define BM_UARTAPP_STAT_TXFF 0x02000000
84#define BM_UARTAPP_STAT_TXFE 0x08000000
85#define BM_UARTAPP_STAT_CTS 0x10000000
86
87#define HW_UARTAPP_VERSION 0x90
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h
deleted file mode 100644
index b810deb552a9..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h
+++ /dev/null
@@ -1,268 +0,0 @@
1/*
2 * stmp378x: UARTDBG register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000)
22#define REGS_UARTDBG_PHYS 0x80070000
23#define REGS_UARTDBG_SIZE 0x2000
24
25#define HW_UARTDBGDR 0x00000000
26#define BP_UARTDBGDR_UNAVAILABLE 16
27#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
28#define BF_UARTDBGDR_UNAVAILABLE(v) \
29 (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
30#define BP_UARTDBGDR_RESERVED 12
31#define BM_UARTDBGDR_RESERVED 0x0000F000
32#define BF_UARTDBGDR_RESERVED(v) \
33 (((v) << 12) & BM_UARTDBGDR_RESERVED)
34#define BM_UARTDBGDR_OE 0x00000800
35#define BM_UARTDBGDR_BE 0x00000400
36#define BM_UARTDBGDR_PE 0x00000200
37#define BM_UARTDBGDR_FE 0x00000100
38#define BP_UARTDBGDR_DATA 0
39#define BM_UARTDBGDR_DATA 0x000000FF
40#define BF_UARTDBGDR_DATA(v) \
41 (((v) << 0) & BM_UARTDBGDR_DATA)
42#define HW_UARTDBGRSR_ECR 0x00000004
43#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
44#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
45#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
46 (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
47#define BP_UARTDBGRSR_ECR_EC 4
48#define BM_UARTDBGRSR_ECR_EC 0x000000F0
49#define BF_UARTDBGRSR_ECR_EC(v) \
50 (((v) << 4) & BM_UARTDBGRSR_ECR_EC)
51#define BM_UARTDBGRSR_ECR_OE 0x00000008
52#define BM_UARTDBGRSR_ECR_BE 0x00000004
53#define BM_UARTDBGRSR_ECR_PE 0x00000002
54#define BM_UARTDBGRSR_ECR_FE 0x00000001
55#define HW_UARTDBGFR 0x00000018
56#define BP_UARTDBGFR_UNAVAILABLE 16
57#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
58#define BF_UARTDBGFR_UNAVAILABLE(v) \
59 (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
60#define BP_UARTDBGFR_RESERVED 9
61#define BM_UARTDBGFR_RESERVED 0x0000FE00
62#define BF_UARTDBGFR_RESERVED(v) \
63 (((v) << 9) & BM_UARTDBGFR_RESERVED)
64#define BM_UARTDBGFR_RI 0x00000100
65#define BM_UARTDBGFR_TXFE 0x00000080
66#define BM_UARTDBGFR_RXFF 0x00000040
67#define BM_UARTDBGFR_TXFF 0x00000020
68#define BM_UARTDBGFR_RXFE 0x00000010
69#define BM_UARTDBGFR_BUSY 0x00000008
70#define BM_UARTDBGFR_DCD 0x00000004
71#define BM_UARTDBGFR_DSR 0x00000002
72#define BM_UARTDBGFR_CTS 0x00000001
73#define HW_UARTDBGILPR 0x00000020
74#define BP_UARTDBGILPR_UNAVAILABLE 8
75#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
76#define BF_UARTDBGILPR_UNAVAILABLE(v) \
77 (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
78#define BP_UARTDBGILPR_ILPDVSR 0
79#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
80#define BF_UARTDBGILPR_ILPDVSR(v) \
81 (((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
82#define HW_UARTDBGIBRD 0x00000024
83#define BP_UARTDBGIBRD_UNAVAILABLE 16
84#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
85#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
86 (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
87#define BP_UARTDBGIBRD_BAUD_DIVINT 0
88#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
89#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
90 (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
91#define HW_UARTDBGFBRD 0x00000028
92#define BP_UARTDBGFBRD_UNAVAILABLE 8
93#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
94#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
95 (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
96#define BP_UARTDBGFBRD_RESERVED 6
97#define BM_UARTDBGFBRD_RESERVED 0x000000C0
98#define BF_UARTDBGFBRD_RESERVED(v) \
99 (((v) << 6) & BM_UARTDBGFBRD_RESERVED)
100#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
101#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
102#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
103 (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
104#define HW_UARTDBGLCR_H 0x0000002c
105#define BP_UARTDBGLCR_H_UNAVAILABLE 16
106#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
107#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
108 (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
109#define BP_UARTDBGLCR_H_RESERVED 8
110#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
111#define BF_UARTDBGLCR_H_RESERVED(v) \
112 (((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
113#define BM_UARTDBGLCR_H_SPS 0x00000080
114#define BP_UARTDBGLCR_H_WLEN 5
115#define BM_UARTDBGLCR_H_WLEN 0x00000060
116#define BF_UARTDBGLCR_H_WLEN(v) \
117 (((v) << 5) & BM_UARTDBGLCR_H_WLEN)
118#define BM_UARTDBGLCR_H_FEN 0x00000010
119#define BM_UARTDBGLCR_H_STP2 0x00000008
120#define BM_UARTDBGLCR_H_EPS 0x00000004
121#define BM_UARTDBGLCR_H_PEN 0x00000002
122#define BM_UARTDBGLCR_H_BRK 0x00000001
123#define HW_UARTDBGCR 0x00000030
124#define BP_UARTDBGCR_UNAVAILABLE 16
125#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
126#define BF_UARTDBGCR_UNAVAILABLE(v) \
127 (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
128#define BM_UARTDBGCR_CTSEN 0x00008000
129#define BM_UARTDBGCR_RTSEN 0x00004000
130#define BM_UARTDBGCR_OUT2 0x00002000
131#define BM_UARTDBGCR_OUT1 0x00001000
132#define BM_UARTDBGCR_RTS 0x00000800
133#define BM_UARTDBGCR_DTR 0x00000400
134#define BM_UARTDBGCR_RXE 0x00000200
135#define BM_UARTDBGCR_TXE 0x00000100
136#define BM_UARTDBGCR_LBE 0x00000080
137#define BP_UARTDBGCR_RESERVED 3
138#define BM_UARTDBGCR_RESERVED 0x00000078
139#define BF_UARTDBGCR_RESERVED(v) \
140 (((v) << 3) & BM_UARTDBGCR_RESERVED)
141#define BM_UARTDBGCR_SIRLP 0x00000004
142#define BM_UARTDBGCR_SIREN 0x00000002
143#define BM_UARTDBGCR_UARTEN 0x00000001
144#define HW_UARTDBGIFLS 0x00000034
145#define BP_UARTDBGIFLS_UNAVAILABLE 16
146#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
147#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
148 (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
149#define BP_UARTDBGIFLS_RESERVED 6
150#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
151#define BF_UARTDBGIFLS_RESERVED(v) \
152 (((v) << 6) & BM_UARTDBGIFLS_RESERVED)
153#define BP_UARTDBGIFLS_RXIFLSEL 3
154#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
155#define BF_UARTDBGIFLS_RXIFLSEL(v) \
156 (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
157#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0
158#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
159#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
160#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
161#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
162#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
163#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
164#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
165#define BP_UARTDBGIFLS_TXIFLSEL 0
166#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
167#define BF_UARTDBGIFLS_TXIFLSEL(v) \
168 (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
169#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0
170#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
171#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
172#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
173#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
174#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
175#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
176#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
177#define HW_UARTDBGIMSC 0x00000038
178#define BP_UARTDBGIMSC_UNAVAILABLE 16
179#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
180#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
181 (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
182#define BP_UARTDBGIMSC_RESERVED 11
183#define BM_UARTDBGIMSC_RESERVED 0x0000F800
184#define BF_UARTDBGIMSC_RESERVED(v) \
185 (((v) << 11) & BM_UARTDBGIMSC_RESERVED)
186#define BM_UARTDBGIMSC_OEIM 0x00000400
187#define BM_UARTDBGIMSC_BEIM 0x00000200
188#define BM_UARTDBGIMSC_PEIM 0x00000100
189#define BM_UARTDBGIMSC_FEIM 0x00000080
190#define BM_UARTDBGIMSC_RTIM 0x00000040
191#define BM_UARTDBGIMSC_TXIM 0x00000020
192#define BM_UARTDBGIMSC_RXIM 0x00000010
193#define BM_UARTDBGIMSC_DSRMIM 0x00000008
194#define BM_UARTDBGIMSC_DCDMIM 0x00000004
195#define BM_UARTDBGIMSC_CTSMIM 0x00000002
196#define BM_UARTDBGIMSC_RIMIM 0x00000001
197#define HW_UARTDBGRIS 0x0000003c
198#define BP_UARTDBGRIS_UNAVAILABLE 16
199#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
200#define BF_UARTDBGRIS_UNAVAILABLE(v) \
201 (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
202#define BP_UARTDBGRIS_RESERVED 11
203#define BM_UARTDBGRIS_RESERVED 0x0000F800
204#define BF_UARTDBGRIS_RESERVED(v) \
205 (((v) << 11) & BM_UARTDBGRIS_RESERVED)
206#define BM_UARTDBGRIS_OERIS 0x00000400
207#define BM_UARTDBGRIS_BERIS 0x00000200
208#define BM_UARTDBGRIS_PERIS 0x00000100
209#define BM_UARTDBGRIS_FERIS 0x00000080
210#define BM_UARTDBGRIS_RTRIS 0x00000040
211#define BM_UARTDBGRIS_TXRIS 0x00000020
212#define BM_UARTDBGRIS_RXRIS 0x00000010
213#define BM_UARTDBGRIS_DSRRMIS 0x00000008
214#define BM_UARTDBGRIS_DCDRMIS 0x00000004
215#define BM_UARTDBGRIS_CTSRMIS 0x00000002
216#define BM_UARTDBGRIS_RIRMIS 0x00000001
217#define HW_UARTDBGMIS 0x00000040
218#define BP_UARTDBGMIS_UNAVAILABLE 16
219#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
220#define BF_UARTDBGMIS_UNAVAILABLE(v) \
221 (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
222#define BP_UARTDBGMIS_RESERVED 11
223#define BM_UARTDBGMIS_RESERVED 0x0000F800
224#define BF_UARTDBGMIS_RESERVED(v) \
225 (((v) << 11) & BM_UARTDBGMIS_RESERVED)
226#define BM_UARTDBGMIS_OEMIS 0x00000400
227#define BM_UARTDBGMIS_BEMIS 0x00000200
228#define BM_UARTDBGMIS_PEMIS 0x00000100
229#define BM_UARTDBGMIS_FEMIS 0x00000080
230#define BM_UARTDBGMIS_RTMIS 0x00000040
231#define BM_UARTDBGMIS_TXMIS 0x00000020
232#define BM_UARTDBGMIS_RXMIS 0x00000010
233#define BM_UARTDBGMIS_DSRMMIS 0x00000008
234#define BM_UARTDBGMIS_DCDMMIS 0x00000004
235#define BM_UARTDBGMIS_CTSMMIS 0x00000002
236#define BM_UARTDBGMIS_RIMMIS 0x00000001
237#define HW_UARTDBGICR 0x00000044
238#define BP_UARTDBGICR_UNAVAILABLE 16
239#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
240#define BF_UARTDBGICR_UNAVAILABLE(v) \
241 (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
242#define BP_UARTDBGICR_RESERVED 11
243#define BM_UARTDBGICR_RESERVED 0x0000F800
244#define BF_UARTDBGICR_RESERVED(v) \
245 (((v) << 11) & BM_UARTDBGICR_RESERVED)
246#define BM_UARTDBGICR_OEIC 0x00000400
247#define BM_UARTDBGICR_BEIC 0x00000200
248#define BM_UARTDBGICR_PEIC 0x00000100
249#define BM_UARTDBGICR_FEIC 0x00000080
250#define BM_UARTDBGICR_RTIC 0x00000040
251#define BM_UARTDBGICR_TXIC 0x00000020
252#define BM_UARTDBGICR_RXIC 0x00000010
253#define BM_UARTDBGICR_DSRMIC 0x00000008
254#define BM_UARTDBGICR_DCDMIC 0x00000004
255#define BM_UARTDBGICR_CTSMIC 0x00000002
256#define BM_UARTDBGICR_RIMIC 0x00000001
257#define HW_UARTDBGDMACR 0x00000048
258#define BP_UARTDBGDMACR_UNAVAILABLE 16
259#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
260#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
261 (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
262#define BP_UARTDBGDMACR_RESERVED 3
263#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
264#define BF_UARTDBGDMACR_RESERVED(v) \
265 (((v) << 3) & BM_UARTDBGDMACR_RESERVED)
266#define BM_UARTDBGDMACR_DMAONERR 0x00000004
267#define BM_UARTDBGDMACR_TXDMAE 0x00000002
268#define BM_UARTDBGDMACR_RXDMAE 0x00000001
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h
deleted file mode 100644
index 25112c1aa608..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * stmp378x: USBCTRL register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000)
22#define REGS_USBCTRL_PHYS 0x80080000
23#define REGS_USBCTRL_SIZE 0x2000
24
25#define HW_USBCTRL_USBCMD 0x140
26#define BM_USBCTRL_USBCMD_RS 0x00000001
27#define BP_USBCTRL_USBCMD_RS 0
28#define BM_USBCTRL_USBCMD_RST 0x00000002
29
30#define HW_USBCTRL_USBINTR 0x148
31#define BM_USBCTRL_USBINTR_UE 0x00000001
32#define BP_USBCTRL_USBINTR_UE 0
33
34#define HW_USBCTRL_PORTSC1 0x184
35#define BM_USBCTRL_PORTSC1_PHCD 0x00800000
36
37#define HW_USBCTRL_OTGSC 0x1A4
38#define BM_USBCTRL_OTGSC_ID 0x00000100
39#define BM_USBCTRL_OTGSC_IDIS 0x00010000
40#define BM_USBCTRL_OTGSC_IDIE 0x01000000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h b/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h
deleted file mode 100644
index 11f3b732dc92..000000000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * stmp378x: USBPHY register definitions
3 *
4 * Copyright (c) 2008 Freescale Semiconductor
5 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000)
22#define REGS_USBPHY_PHYS 0x8007C000
23#define REGS_USBPHY_SIZE 0x2000
24
25#define HW_USBPHY_PWD 0x0
26
27#define HW_USBPHY_CTRL 0x30
28#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002
29#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010
30#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080
31#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800
32#define BM_USBPHY_CTRL_CLKGATE 0x40000000
33#define BM_USBPHY_CTRL_SFTRST 0x80000000
34
35#define HW_USBPHY_STATUS 0x40
36#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040
37#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100
diff --git a/arch/arm/mach-stmp378x/stmp378x.c b/arch/arm/mach-stmp378x/stmp378x.c
deleted file mode 100644
index c2f9fe04c112..000000000000
--- a/arch/arm/mach-stmp378x/stmp378x.c
+++ /dev/null
@@ -1,299 +0,0 @@
1/*
2 * Freescale STMP378X platform support
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/platform_device.h>
21#include <linux/irq.h>
22#include <linux/dma-mapping.h>
23
24#include <asm/dma.h>
25#include <asm/setup.h>
26#include <asm/mach-types.h>
27
28#include <asm/mach/arch.h>
29#include <asm/mach/irq.h>
30#include <asm/mach/map.h>
31#include <asm/mach/time.h>
32
33#include <mach/pins.h>
34#include <mach/pinmux.h>
35#include <mach/dma.h>
36#include <mach/hardware.h>
37#include <mach/system.h>
38#include <mach/platform.h>
39#include <mach/stmp3xxx.h>
40#include <mach/regs-icoll.h>
41#include <mach/regs-apbh.h>
42#include <mach/regs-apbx.h>
43#include <mach/regs-pxp.h>
44#include <mach/regs-i2c.h>
45
46#include "stmp378x.h"
47/*
48 * IRQ handling
49 */
50static void stmp378x_ack_irq(struct irq_data *d)
51{
52 /* Tell ICOLL to release IRQ line */
53 __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
54
55 /* ACK current interrupt */
56 __raw_writel(0x01 /* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 */,
57 REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
58
59 /* Barrier */
60 (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
61}
62
63static void stmp378x_mask_irq(struct irq_data *d)
64{
65 /* IRQ disable */
66 stmp3xxx_clearl(BM_ICOLL_INTERRUPTn_ENABLE,
67 REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10);
68}
69
70static void stmp378x_unmask_irq(struct irq_data *d)
71{
72 /* IRQ enable */
73 stmp3xxx_setl(BM_ICOLL_INTERRUPTn_ENABLE,
74 REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10);
75}
76
77static struct irq_chip stmp378x_chip = {
78 .irq_ack = stmp378x_ack_irq,
79 .irq_mask = stmp378x_mask_irq,
80 .irq_unmask = stmp378x_unmask_irq,
81};
82
83void __init stmp378x_init_irq(void)
84{
85 stmp3xxx_init_irq(&stmp378x_chip);
86}
87
88/*
89 * DMA interrupt handling
90 */
91void stmp3xxx_arch_dma_enable_interrupt(int channel)
92{
93 void __iomem *c1, *c2;
94
95 switch (STMP3XXX_DMA_BUS(channel)) {
96 case STMP3XXX_BUS_APBH:
97 c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
98 c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
99 break;
100
101 case STMP3XXX_BUS_APBX:
102 c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
103 c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
104 break;
105
106 default:
107 return;
108 }
109 stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c1);
110 stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c2);
111}
112EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
113
114void stmp3xxx_arch_dma_clear_interrupt(int channel)
115{
116 void __iomem *c1, *c2;
117
118 switch (STMP3XXX_DMA_BUS(channel)) {
119 case STMP3XXX_BUS_APBH:
120 c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
121 c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
122 break;
123
124 case STMP3XXX_BUS_APBX:
125 c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
126 c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
127 break;
128
129 default:
130 return;
131 }
132 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c1);
133 stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c2);
134}
135EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
136
137int stmp3xxx_arch_dma_is_interrupt(int channel)
138{
139 int r = 0;
140
141 switch (STMP3XXX_DMA_BUS(channel)) {
142 case STMP3XXX_BUS_APBH:
143 r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
144 (1 << STMP3XXX_DMA_CHANNEL(channel));
145 break;
146
147 case STMP3XXX_BUS_APBX:
148 r = __raw_readl(REGS_APBX_BASE + HW_APBX_CTRL1) &
149 (1 << STMP3XXX_DMA_CHANNEL(channel));
150 break;
151 }
152 return r;
153}
154EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
155
156void stmp3xxx_arch_dma_reset_channel(int channel)
157{
158 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
159 void __iomem *c0;
160 u32 mask;
161
162 switch (STMP3XXX_DMA_BUS(channel)) {
163 case STMP3XXX_BUS_APBH:
164 c0 = REGS_APBH_BASE + HW_APBH_CTRL0;
165 mask = chbit << BP_APBH_CTRL0_RESET_CHANNEL;
166 break;
167 case STMP3XXX_BUS_APBX:
168 c0 = REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL;
169 mask = chbit << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL;
170 break;
171 default:
172 return;
173 }
174
175 /* Reset channel and wait for it to complete */
176 stmp3xxx_setl(mask, c0);
177 while (__raw_readl(c0) & mask)
178 cpu_relax();
179}
180EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
181
182void stmp3xxx_arch_dma_freeze(int channel)
183{
184 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
185 u32 mask = 1 << chbit;
186
187 switch (STMP3XXX_DMA_BUS(channel)) {
188 case STMP3XXX_BUS_APBH:
189 stmp3xxx_setl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
190 break;
191 case STMP3XXX_BUS_APBX:
192 stmp3xxx_setl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
193 break;
194 }
195}
196EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
197
198void stmp3xxx_arch_dma_unfreeze(int channel)
199{
200 unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
201 u32 mask = 1 << chbit;
202
203 switch (STMP3XXX_DMA_BUS(channel)) {
204 case STMP3XXX_BUS_APBH:
205 stmp3xxx_clearl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
206 break;
207 case STMP3XXX_BUS_APBX:
208 stmp3xxx_clearl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
209 break;
210 }
211}
212EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
213
214/*
215 * The registers are all very closely mapped, so we might as well map them all
216 * with a single mapping
217 *
218 * Logical Physical
219 * f0000000 80000000 On-chip registers
220 * f1000000 00000000 32k on-chip SRAM
221 */
222
223static struct map_desc stmp378x_io_desc[] __initdata = {
224 {
225 .virtual = (u32)STMP3XXX_REGS_BASE,
226 .pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE),
227 .length = STMP3XXX_REGS_SIZE,
228 .type = MT_DEVICE,
229 },
230 {
231 .virtual = (u32)STMP3XXX_OCRAM_BASE,
232 .pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE),
233 .length = STMP3XXX_OCRAM_SIZE,
234 .type = MT_DEVICE,
235 },
236};
237
238
239static u64 common_dmamask = DMA_BIT_MASK(32);
240
241/*
242 * devices that are present only on stmp378x, not on all 3xxx boards:
243 * PxP
244 * I2C
245 */
246static struct resource pxp_resource[] = {
247 {
248 .flags = IORESOURCE_MEM,
249 .start = REGS_PXP_PHYS,
250 .end = REGS_PXP_PHYS + REGS_PXP_SIZE,
251 }, {
252 .flags = IORESOURCE_IRQ,
253 .start = IRQ_PXP,
254 .end = IRQ_PXP,
255 },
256};
257
258struct platform_device stmp378x_pxp = {
259 .name = "stmp3xxx-pxp",
260 .id = -1,
261 .dev = {
262 .dma_mask = &common_dmamask,
263 .coherent_dma_mask = DMA_BIT_MASK(32),
264 },
265 .num_resources = ARRAY_SIZE(pxp_resource),
266 .resource = pxp_resource,
267};
268
269static struct resource i2c_resources[] = {
270 {
271 .flags = IORESOURCE_IRQ,
272 .start = IRQ_I2C_ERROR,
273 .end = IRQ_I2C_ERROR,
274 }, {
275 .flags = IORESOURCE_MEM,
276 .start = REGS_I2C_PHYS,
277 .end = REGS_I2C_PHYS + REGS_I2C_SIZE,
278 }, {
279 .flags = IORESOURCE_DMA,
280 .start = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX),
281 .end = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX),
282 },
283};
284
285struct platform_device stmp378x_i2c = {
286 .name = "i2c_stmp3xxx",
287 .id = 0,
288 .dev = {
289 .dma_mask = &common_dmamask,
290 .coherent_dma_mask = DMA_BIT_MASK(32),
291 },
292 .resource = i2c_resources,
293 .num_resources = ARRAY_SIZE(i2c_resources),
294};
295
296void __init stmp378x_map_io(void)
297{
298 iotable_init(stmp378x_io_desc, ARRAY_SIZE(stmp378x_io_desc));
299}
diff --git a/arch/arm/mach-stmp378x/stmp378x.h b/arch/arm/mach-stmp378x/stmp378x.h
deleted file mode 100644
index 0dc15b3c891f..000000000000
--- a/arch/arm/mach-stmp378x/stmp378x.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * Freescale STMP37XX/STMP378X internal functions and data declarations
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#ifndef __MACH_STMP378X_H
19#define __MACH_STMP378X_H
20
21void stmp378x_map_io(void);
22void stmp378x_init_irq(void);
23
24extern struct platform_device stmp378x_pxp, stmp378x_i2c;
25#endif /* __MACH_STMP378X_COMMON_H */
diff --git a/arch/arm/mach-stmp378x/stmp378x_devb.c b/arch/arm/mach-stmp378x/stmp378x_devb.c
deleted file mode 100644
index 06158848afd9..000000000000
--- a/arch/arm/mach-stmp378x/stmp378x_devb.c
+++ /dev/null
@@ -1,332 +0,0 @@
1/*
2 * Freescale STMP378X development board support
3 *
4 * Embedded Alley Solutions, Inc <source@embeddedalley.com>
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
8 */
9
10/*
11 * The code contained herein is licensed under the GNU General Public
12 * License. You may obtain a copy of the GNU General Public License
13 * Version 2 or later at the following locations:
14 *
15 * http://www.opensource.org/licenses/gpl-license.html
16 * http://www.gnu.org/copyleft/gpl.html
17 */
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/platform_device.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/err.h>
25#include <linux/spi/spi.h>
26
27#include <asm/setup.h>
28#include <asm/mach-types.h>
29#include <asm/mach/arch.h>
30
31#include <mach/pins.h>
32#include <mach/pinmux.h>
33#include <mach/platform.h>
34#include <mach/stmp3xxx.h>
35#include <mach/mmc.h>
36#include <mach/gpmi.h>
37
38#include "stmp378x.h"
39
40static struct platform_device *devices[] = {
41 &stmp3xxx_dbguart,
42 &stmp3xxx_appuart,
43 &stmp3xxx_watchdog,
44 &stmp3xxx_touchscreen,
45 &stmp3xxx_rtc,
46 &stmp3xxx_keyboard,
47 &stmp3xxx_framebuffer,
48 &stmp3xxx_backlight,
49 &stmp3xxx_rotdec,
50 &stmp3xxx_persistent,
51 &stmp3xxx_dcp_bootstream,
52 &stmp3xxx_dcp,
53 &stmp3xxx_battery,
54 &stmp378x_pxp,
55 &stmp378x_i2c,
56};
57
58static struct pin_desc i2c_pins_desc[] = {
59 { PINID_I2C_SCL, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
60 { PINID_I2C_SDA, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
61};
62
63static struct pin_group i2c_pins = {
64 .pins = i2c_pins_desc,
65 .nr_pins = ARRAY_SIZE(i2c_pins_desc),
66};
67
68static struct pin_desc dbguart_pins_0[] = {
69 { PINID_PWM0, PIN_FUN3, },
70 { PINID_PWM1, PIN_FUN3, },
71};
72
73static struct pin_group dbguart_pins[] = {
74 [0] = {
75 .pins = dbguart_pins_0,
76 .nr_pins = ARRAY_SIZE(dbguart_pins_0),
77 },
78};
79
80static int dbguart_pins_control(int id, int request)
81{
82 int r = 0;
83
84 if (request)
85 r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart");
86 else
87 stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart");
88 return r;
89}
90
91static struct pin_desc appuart_pins_0[] = {
92 { PINID_AUART1_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
93 { PINID_AUART1_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
94 { PINID_AUART1_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
95 { PINID_AUART1_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
96};
97
98static struct pin_desc appuart_pins_1[] = {
99#if 0 /* enable these when second appuart will be connected */
100 { PINID_AUART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
101 { PINID_AUART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
102 { PINID_AUART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
103 { PINID_AUART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
104#endif
105};
106
107static struct pin_desc mmc_pins_desc[] = {
108 { PINID_SSP1_DATA0, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
109 { PINID_SSP1_DATA1, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
110 { PINID_SSP1_DATA2, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
111 { PINID_SSP1_DATA3, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
112 { PINID_SSP1_CMD, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
113 { PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 },
114 { PINID_SSP1_DETECT, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 },
115};
116
117static struct pin_group mmc_pins = {
118 .pins = mmc_pins_desc,
119 .nr_pins = ARRAY_SIZE(mmc_pins_desc),
120};
121
122static int stmp3xxxmmc_get_wp(void)
123{
124 return gpio_get_value(PINID_PWM4);
125}
126
127static int stmp3xxxmmc_hw_init_ssp1(void)
128{
129 int ret;
130
131 ret = stmp3xxx_request_pin_group(&mmc_pins, "mmc");
132 if (ret)
133 goto out;
134
135 /* Configure write protect GPIO pin */
136 ret = gpio_request(PINID_PWM4, "mmc wp");
137 if (ret)
138 goto out_wp;
139
140 gpio_direction_input(PINID_PWM4);
141
142 /* Configure POWER pin as gpio to drive power to MMC slot */
143 ret = gpio_request(PINID_PWM3, "mmc power");
144 if (ret)
145 goto out_power;
146
147 gpio_direction_output(PINID_PWM3, 0);
148 mdelay(100);
149
150 return 0;
151
152out_power:
153 gpio_free(PINID_PWM4);
154out_wp:
155 stmp3xxx_release_pin_group(&mmc_pins, "mmc");
156out:
157 return ret;
158}
159
160static void stmp3xxxmmc_hw_release_ssp1(void)
161{
162 gpio_free(PINID_PWM3);
163 gpio_free(PINID_PWM4);
164 stmp3xxx_release_pin_group(&mmc_pins, "mmc");
165}
166
167static void stmp3xxxmmc_cmd_pullup_ssp1(int enable)
168{
169 stmp3xxx_pin_pullup(PINID_SSP1_CMD, enable, "mmc");
170}
171
172static unsigned long
173stmp3xxxmmc_setclock_ssp1(void __iomem *base, unsigned long hz)
174{
175 struct clk *ssp, *parent;
176 char *p;
177 long r;
178
179 ssp = clk_get(NULL, "ssp");
180
181 /* using SSP1, no timeout, clock rate 1 */
182 writel(BF(2, SSP_TIMING_CLOCK_DIVIDE) |
183 BF(0xFFFF, SSP_TIMING_TIMEOUT),
184 base + HW_SSP_TIMING);
185
186 p = (hz > 1000000) ? "io" : "osc_24M";
187 parent = clk_get(NULL, p);
188 clk_set_parent(ssp, parent);
189 r = clk_set_rate(ssp, 2 * hz / 1000);
190 clk_put(parent);
191 clk_put(ssp);
192
193 return hz;
194}
195
196static struct stmp3xxxmmc_platform_data mmc_data = {
197 .hw_init = stmp3xxxmmc_hw_init_ssp1,
198 .hw_release = stmp3xxxmmc_hw_release_ssp1,
199 .get_wp = stmp3xxxmmc_get_wp,
200 .cmd_pullup = stmp3xxxmmc_cmd_pullup_ssp1,
201 .setclock = stmp3xxxmmc_setclock_ssp1,
202};
203
204
205static struct pin_group appuart_pins[] = {
206 [0] = {
207 .pins = appuart_pins_0,
208 .nr_pins = ARRAY_SIZE(appuart_pins_0),
209 },
210 [1] = {
211 .pins = appuart_pins_1,
212 .nr_pins = ARRAY_SIZE(appuart_pins_1),
213 },
214};
215
216static struct pin_desc ssp1_pins_desc[] = {
217 { PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0, },
218 { PINID_SSP1_CMD, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
219 { PINID_SSP1_DATA0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
220 { PINID_SSP1_DATA3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
221};
222
223static struct pin_desc ssp2_pins_desc[] = {
224 { PINID_GPMI_WRN, PIN_FUN3, PIN_8MA, PIN_3_3V, 0, },
225 { PINID_GPMI_RDY1, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
226 { PINID_GPMI_D00, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
227 { PINID_GPMI_D03, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
228};
229
230static struct pin_group ssp1_pins = {
231 .pins = ssp1_pins_desc,
232 .nr_pins = ARRAY_SIZE(ssp1_pins_desc),
233};
234
235static struct pin_group ssp2_pins = {
236 .pins = ssp1_pins_desc,
237 .nr_pins = ARRAY_SIZE(ssp2_pins_desc),
238};
239
240static struct pin_desc gpmi_pins_desc[] = {
241 { PINID_GPMI_CE0N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
242 { PINID_GPMI_CE1N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
243 { PINID_GMPI_CE2N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
244 { PINID_GPMI_CLE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
245 { PINID_GPMI_ALE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
246 { PINID_GPMI_WPN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
247 { PINID_GPMI_RDY1, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
248 { PINID_GPMI_D00, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
249 { PINID_GPMI_D01, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
250 { PINID_GPMI_D02, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
251 { PINID_GPMI_D03, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
252 { PINID_GPMI_D04, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
253 { PINID_GPMI_D05, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
254 { PINID_GPMI_D06, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
255 { PINID_GPMI_D07, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
256 { PINID_GPMI_RDY0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
257 { PINID_GPMI_RDY2, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
258 { PINID_GPMI_RDY3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
259 { PINID_GPMI_WRN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
260 { PINID_GPMI_RDN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
261};
262
263static struct pin_group gpmi_pins = {
264 .pins = gpmi_pins_desc,
265 .nr_pins = ARRAY_SIZE(gpmi_pins_desc),
266};
267
268static struct mtd_partition gpmi_partitions[] = {
269 [0] = {
270 .name = "boot",
271 .size = 10 * SZ_1M,
272 .offset = 0,
273 },
274 [1] = {
275 .name = "data",
276 .size = MTDPART_SIZ_FULL,
277 .offset = MTDPART_OFS_APPEND,
278 },
279};
280
281static struct gpmi_platform_data gpmi_data = {
282 .pins = &gpmi_pins,
283 .nr_parts = ARRAY_SIZE(gpmi_partitions),
284 .parts = gpmi_partitions,
285 .part_types = { "cmdline", NULL },
286};
287
288static struct spi_board_info spi_board_info[] __initdata = {
289#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
290 {
291 .modalias = "enc28j60",
292 .max_speed_hz = 6 * 1000 * 1000,
293 .bus_num = 1,
294 .chip_select = 0,
295 .platform_data = NULL,
296 },
297#endif
298};
299
300static void __init stmp378x_devb_init(void)
301{
302 stmp3xxx_pinmux_init(NR_REAL_IRQS);
303
304 /* init stmp3xxx platform */
305 stmp3xxx_init();
306
307 stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control;
308 stmp3xxx_appuart.dev.platform_data = appuart_pins;
309 stmp3xxx_mmc.dev.platform_data = &mmc_data;
310 stmp3xxx_gpmi.dev.platform_data = &gpmi_data;
311 stmp3xxx_spi1.dev.platform_data = &ssp1_pins;
312 stmp3xxx_spi2.dev.platform_data = &ssp2_pins;
313 stmp378x_i2c.dev.platform_data = &i2c_pins;
314
315 /* register spi devices */
316 spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
317
318 /* add board's devices */
319 platform_add_devices(devices, ARRAY_SIZE(devices));
320
321 /* add devices selected by command line ssp1= and ssp2= options */
322 stmp3xxx_ssp1_device_register();
323 stmp3xxx_ssp2_device_register();
324}
325
326MACHINE_START(STMP378X, "STMP378X")
327 .boot_params = 0x40000100,
328 .map_io = stmp378x_map_io,
329 .init_irq = stmp378x_init_irq,
330 .timer = &stmp3xxx_timer,
331 .init_machine = stmp378x_devb_init,
332MACHINE_END
diff --git a/arch/arm/plat-stmp3xxx/Kconfig b/arch/arm/plat-stmp3xxx/Kconfig
index dcdbe327fed3..e6e312b6bdb5 100644
--- a/arch/arm/plat-stmp3xxx/Kconfig
+++ b/arch/arm/plat-stmp3xxx/Kconfig
@@ -2,26 +2,6 @@ if ARCH_STMP3XXX
2 2
3menu "Freescale STMP3xxx implementations" 3menu "Freescale STMP3xxx implementations"
4 4
5choice
6 prompt "Select STMP3xxx chip family"
7
8config ARCH_STMP378X
9 bool "Freescale STMP378x"
10 select CPU_ARM926T
11 ---help---
12 STMP378x refers to 3780 through 3789 chips
13
14endchoice
15
16choice
17 prompt "Select STMP3xxx board type"
18
19config MACH_STMP378X
20 depends on ARCH_STMP378X
21 bool "Freescale STMP378x development board"
22
23endchoice
24
25endmenu 5endmenu
26 6
27endif 7endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 04:23:08 -0500