aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm
diff options
context:
space:
mode:
authorPaul Walmsley <paul@pwsan.com>2008-08-19 04:08:44 -0400
committerTony Lindgren <tony@atomide.com>2008-08-19 04:08:44 -0400
commit801954d3debb87af9fa7f9187cb1100175d76ac7 (patch)
tree3f554033edbbeb6f2c6a29d24b4c08e0c5e647d2 /arch/arm
parent8420bb13630032097be911a039cb64b5f62c01da (diff)
ARM: OMAP2: Clockdomain: Encode OMAP2/3 clockdomains
Add clockdomain definitions for OMAP24xx and OMAP34xx chips. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-omap2/clockdomains.h298
-rw-r--r--arch/arm/mach-omap2/cm-regbits-24xx.h24
-rw-r--r--arch/arm/mach-omap2/cm-regbits-34xx.h42
-rw-r--r--arch/arm/mach-omap2/io.c4
4 files changed, 349 insertions, 19 deletions
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h
new file mode 100644
index 000000000000..a27632037138
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains.h
@@ -0,0 +1,298 @@
1/*
2 * OMAP2/3 clockdomains
3 *
4 * Copyright (C) 2008 Texas Instruments, Inc.
5 * Copyright (C) 2008 Nokia Corporation
6 *
7 * Written by Paul Walmsley
8 */
9
10#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
11#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
12
13#include <mach/clockdomain.h>
14
15/*
16 * OMAP2/3-common clockdomains
17 */
18
19/* This is an implicit clockdomain - it is never defined as such in TRM */
20static struct clockdomain wkup_clkdm = {
21 .name = "wkup_clkdm",
22 .pwrdm_name = "wkup_pwrdm",
23 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
24};
25
26/*
27 * 2420-only clockdomains
28 */
29
30#if defined(CONFIG_ARCH_OMAP2420)
31
32static struct clockdomain mpu_2420_clkdm = {
33 .name = "mpu_clkdm",
34 .pwrdm_name = "mpu_pwrdm",
35 .flags = CLKDM_CAN_HWSUP,
36 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
37 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
38};
39
40static struct clockdomain iva1_2420_clkdm = {
41 .name = "iva1_clkdm",
42 .pwrdm_name = "dsp_pwrdm",
43 .flags = CLKDM_CAN_HWSUP_SWSUP,
44 .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
45 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
46};
47
48#endif /* CONFIG_ARCH_OMAP2420 */
49
50
51/*
52 * 2430-only clockdomains
53 */
54
55#if defined(CONFIG_ARCH_OMAP2430)
56
57static struct clockdomain mpu_2430_clkdm = {
58 .name = "mpu_clkdm",
59 .pwrdm_name = "mpu_pwrdm",
60 .flags = CLKDM_CAN_HWSUP_SWSUP,
61 .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
62 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
63};
64
65static struct clockdomain mdm_clkdm = {
66 .name = "mdm_clkdm",
67 .pwrdm_name = "mdm_pwrdm",
68 .flags = CLKDM_CAN_HWSUP_SWSUP,
69 .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
70 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
71};
72
73#endif /* CONFIG_ARCH_OMAP2430 */
74
75
76/*
77 * 24XX-only clockdomains
78 */
79
80#if defined(CONFIG_ARCH_OMAP24XX)
81
82static struct clockdomain dsp_clkdm = {
83 .name = "dsp_clkdm",
84 .pwrdm_name = "dsp_pwrdm",
85 .flags = CLKDM_CAN_HWSUP_SWSUP,
86 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
87 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
88};
89
90static struct clockdomain gfx_24xx_clkdm = {
91 .name = "gfx_clkdm",
92 .pwrdm_name = "gfx_pwrdm",
93 .flags = CLKDM_CAN_HWSUP_SWSUP,
94 .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
95 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
96};
97
98static struct clockdomain core_l3_24xx_clkdm = {
99 .name = "core_l3_clkdm",
100 .pwrdm_name = "core_pwrdm",
101 .flags = CLKDM_CAN_HWSUP,
102 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
103 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
104};
105
106static struct clockdomain core_l4_24xx_clkdm = {
107 .name = "core_l4_clkdm",
108 .pwrdm_name = "core_pwrdm",
109 .flags = CLKDM_CAN_HWSUP,
110 .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
111 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
112};
113
114static struct clockdomain dss_24xx_clkdm = {
115 .name = "dss_clkdm",
116 .pwrdm_name = "core_pwrdm",
117 .flags = CLKDM_CAN_HWSUP,
118 .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
119 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
120};
121
122#endif /* CONFIG_ARCH_OMAP24XX */
123
124
125/*
126 * 34xx clockdomains
127 */
128
129#if defined(CONFIG_ARCH_OMAP34XX)
130
131static struct clockdomain mpu_34xx_clkdm = {
132 .name = "mpu_clkdm",
133 .pwrdm_name = "mpu_pwrdm",
134 .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
135 .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
136 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
137};
138
139static struct clockdomain neon_clkdm = {
140 .name = "neon_clkdm",
141 .pwrdm_name = "neon_pwrdm",
142 .flags = CLKDM_CAN_HWSUP_SWSUP,
143 .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
144 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
145};
146
147static struct clockdomain iva2_clkdm = {
148 .name = "iva2_clkdm",
149 .pwrdm_name = "iva2_pwrdm",
150 .flags = CLKDM_CAN_HWSUP_SWSUP,
151 .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
152 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
153};
154
155static struct clockdomain gfx_3430es1_clkdm = {
156 .name = "gfx_clkdm",
157 .pwrdm_name = "gfx_pwrdm",
158 .flags = CLKDM_CAN_HWSUP_SWSUP,
159 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
160 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
161};
162
163static struct clockdomain sgx_clkdm = {
164 .name = "sgx_clkdm",
165 .pwrdm_name = "sgx_pwrdm",
166 .flags = CLKDM_CAN_HWSUP_SWSUP,
167 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
168 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
169};
170
171static struct clockdomain d2d_clkdm = {
172 .name = "d2d_clkdm",
173 .pwrdm_name = "core_pwrdm",
174 .flags = CLKDM_CAN_HWSUP,
175 .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
176 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
177};
178
179static struct clockdomain core_l3_34xx_clkdm = {
180 .name = "core_l3_clkdm",
181 .pwrdm_name = "core_pwrdm",
182 .flags = CLKDM_CAN_HWSUP,
183 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
184 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
185};
186
187static struct clockdomain core_l4_34xx_clkdm = {
188 .name = "core_l4_clkdm",
189 .pwrdm_name = "core_pwrdm",
190 .flags = CLKDM_CAN_HWSUP,
191 .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
192 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
193};
194
195static struct clockdomain dss_34xx_clkdm = {
196 .name = "dss_clkdm",
197 .pwrdm_name = "dss_pwrdm",
198 .flags = CLKDM_CAN_HWSUP_SWSUP,
199 .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
200 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
201};
202
203static struct clockdomain cam_clkdm = {
204 .name = "cam_clkdm",
205 .pwrdm_name = "cam_pwrdm",
206 .flags = CLKDM_CAN_HWSUP_SWSUP,
207 .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
208 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
209};
210
211static struct clockdomain usbhost_clkdm = {
212 .name = "usbhost_clkdm",
213 .pwrdm_name = "usbhost_pwrdm",
214 .flags = CLKDM_CAN_HWSUP_SWSUP,
215 .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
216 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2),
217};
218
219static struct clockdomain per_clkdm = {
220 .name = "per_clkdm",
221 .pwrdm_name = "per_pwrdm",
222 .flags = CLKDM_CAN_HWSUP_SWSUP,
223 .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
224 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
225};
226
227static struct clockdomain emu_clkdm = {
228 .name = "emu_clkdm",
229 .pwrdm_name = "emu_pwrdm",
230 .flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP,
231 .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
232 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
233};
234
235#endif /* CONFIG_ARCH_OMAP34XX */
236
237/*
238 * Clockdomain-powerdomain hwsup dependencies (34XX only)
239 */
240
241static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = {
242 {
243 .pwrdm_name = "mpu_pwrdm",
244 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
245 },
246 {
247 .pwrdm_name = "iva2_pwrdm",
248 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
249 },
250 { NULL }
251};
252
253/*
254 *
255 */
256
257static struct clockdomain *clockdomains_omap[] = {
258
259 &wkup_clkdm,
260
261#ifdef CONFIG_ARCH_OMAP2420
262 &mpu_2420_clkdm,
263 &iva1_2420_clkdm,
264#endif
265
266#ifdef CONFIG_ARCH_OMAP2430
267 &mpu_2430_clkdm,
268 &mdm_clkdm,
269#endif
270
271#ifdef CONFIG_ARCH_OMAP24XX
272 &dsp_clkdm,
273 &gfx_24xx_clkdm,
274 &core_l3_24xx_clkdm,
275 &core_l4_24xx_clkdm,
276 &dss_24xx_clkdm,
277#endif
278
279#ifdef CONFIG_ARCH_OMAP34XX
280 &mpu_34xx_clkdm,
281 &neon_clkdm,
282 &iva2_clkdm,
283 &gfx_3430es1_clkdm,
284 &sgx_clkdm,
285 &d2d_clkdm,
286 &core_l3_34xx_clkdm,
287 &core_l4_34xx_clkdm,
288 &dss_34xx_clkdm,
289 &cam_clkdm,
290 &usbhost_clkdm,
291 &per_clkdm,
292 &emu_clkdm,
293#endif
294
295 NULL,
296};
297
298#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 20ac38100678..1098ecfab861 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -63,7 +63,8 @@
63#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0) 63#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
64 64
65/* CM_CLKSTCTRL_MPU */ 65/* CM_CLKSTCTRL_MPU */
66#define OMAP24XX_AUTOSTATE_MPU (1 << 0) 66#define OMAP24XX_AUTOSTATE_MPU_SHIFT 0
67#define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0)
67 68
68/* CM_FCLKEN1_CORE specific bits*/ 69/* CM_FCLKEN1_CORE specific bits*/
69#define OMAP24XX_EN_TV_SHIFT 2 70#define OMAP24XX_EN_TV_SHIFT 2
@@ -238,9 +239,12 @@
238#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2) 239#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2)
239 240
240/* CM_CLKSTCTRL_CORE */ 241/* CM_CLKSTCTRL_CORE */
241#define OMAP24XX_AUTOSTATE_DSS (1 << 2) 242#define OMAP24XX_AUTOSTATE_DSS_SHIFT 2
242#define OMAP24XX_AUTOSTATE_L4 (1 << 1) 243#define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2)
243#define OMAP24XX_AUTOSTATE_L3 (1 << 0) 244#define OMAP24XX_AUTOSTATE_L4_SHIFT 1
245#define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1)
246#define OMAP24XX_AUTOSTATE_L3_SHIFT 0
247#define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0)
244 248
245/* CM_FCLKEN_GFX */ 249/* CM_FCLKEN_GFX */
246#define OMAP24XX_EN_3D_SHIFT 2 250#define OMAP24XX_EN_3D_SHIFT 2
@@ -255,7 +259,8 @@
255/* CM_CLKSEL_GFX specific bits */ 259/* CM_CLKSEL_GFX specific bits */
256 260
257/* CM_CLKSTCTRL_GFX */ 261/* CM_CLKSTCTRL_GFX */
258#define OMAP24XX_AUTOSTATE_GFX (1 << 0) 262#define OMAP24XX_AUTOSTATE_GFX_SHIFT 0
263#define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0)
259 264
260/* CM_FCLKEN_WKUP specific bits */ 265/* CM_FCLKEN_WKUP specific bits */
261 266
@@ -367,8 +372,10 @@
367#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0) 372#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0)
368 373
369/* CM_CLKSTCTRL_DSP */ 374/* CM_CLKSTCTRL_DSP */
370#define OMAP2420_AUTOSTATE_IVA (1 << 8) 375#define OMAP2420_AUTOSTATE_IVA_SHIFT 8
371#define OMAP24XX_AUTOSTATE_DSP (1 << 0) 376#define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8)
377#define OMAP24XX_AUTOSTATE_DSP_SHIFT 0
378#define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0)
372 379
373/* CM_FCLKEN_MDM */ 380/* CM_FCLKEN_MDM */
374/* 2430 only */ 381/* 2430 only */
@@ -396,6 +403,7 @@
396 403
397/* CM_CLKSTCTRL_MDM */ 404/* CM_CLKSTCTRL_MDM */
398/* 2430 only */ 405/* 2430 only */
399#define OMAP2430_AUTOSTATE_MDM (1 << 0) 406#define OMAP2430_AUTOSTATE_MDM_SHIFT 0
407#define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0)
400 408
401#endif 409#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index ee4c0ca1a708..219f5c8d9659 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -96,7 +96,8 @@
96#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) 96#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
97 97
98/* CM_CLKSTST_IVA2 */ 98/* CM_CLKSTST_IVA2 */
99#define OMAP3430_CLKACTIVITY_IVA2 (1 << 0) 99#define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0
100#define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)
100 101
101/* CM_REVISION specific bits */ 102/* CM_REVISION specific bits */
102 103
@@ -140,7 +141,8 @@
140#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) 141#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
141 142
142/* CM_CLKSTST_MPU */ 143/* CM_CLKSTST_MPU */
143#define OMAP3430_CLKACTIVITY_MPU (1 << 0) 144#define OMAP3430_CLKACTIVITY_MPU_SHIFT 0
145#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0)
144 146
145/* CM_FCLKEN1_CORE specific bits */ 147/* CM_FCLKEN1_CORE specific bits */
146 148
@@ -300,9 +302,12 @@
300#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) 302#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
301 303
302/* CM_CLKSTST_CORE */ 304/* CM_CLKSTST_CORE */
303#define OMAP3430ES1_CLKACTIVITY_D2D (1 << 2) 305#define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2
304#define OMAP3430_CLKACTIVITY_L4 (1 << 1) 306#define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2)
305#define OMAP3430_CLKACTIVITY_L3 (1 << 0) 307#define OMAP3430_CLKACTIVITY_L4_SHIFT 1
308#define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1)
309#define OMAP3430_CLKACTIVITY_L3_SHIFT 0
310#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0)
306 311
307/* CM_FCLKEN_GFX */ 312/* CM_FCLKEN_GFX */
308#define OMAP3430ES1_EN_3D (1 << 2) 313#define OMAP3430ES1_EN_3D (1 << 2)
@@ -323,7 +328,8 @@
323#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) 328#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
324 329
325/* CM_CLKSTST_GFX */ 330/* CM_CLKSTST_GFX */
326#define OMAP3430ES1_CLKACTIVITY_GFX (1 << 0) 331#define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0
332#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0)
327 333
328/* CM_FCLKEN_SGX */ 334/* CM_FCLKEN_SGX */
329#define OMAP3430ES2_EN_SGX_SHIFT 1 335#define OMAP3430ES2_EN_SGX_SHIFT 1
@@ -333,6 +339,14 @@
333#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 339#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
334#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) 340#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
335 341
342/* CM_CLKSTCTRL_SGX */
343#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0
344#define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0)
345
346/* CM_CLKSTST_SGX */
347#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0
348#define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0)
349
336/* CM_FCLKEN_WKUP specific bits */ 350/* CM_FCLKEN_WKUP specific bits */
337#define OMAP3430ES2_EN_USIMOCP_SHIFT 9 351#define OMAP3430ES2_EN_USIMOCP_SHIFT 9
338 352
@@ -498,7 +512,8 @@
498#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) 512#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
499 513
500/* CM_CLKSTST_DSS */ 514/* CM_CLKSTST_DSS */
501#define OMAP3430_CLKACTIVITY_DSS (1 << 0) 515#define OMAP3430_CLKACTIVITY_DSS_SHIFT 0
516#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)
502 517
503/* CM_FCLKEN_CAM specific bits */ 518/* CM_FCLKEN_CAM specific bits */
504 519
@@ -522,7 +537,8 @@
522#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) 537#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
523 538
524/* CM_CLKSTST_CAM */ 539/* CM_CLKSTST_CAM */
525#define OMAP3430_CLKACTIVITY_CAM (1 << 0) 540#define OMAP3430_CLKACTIVITY_CAM_SHIFT 0
541#define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0)
526 542
527/* CM_FCLKEN_PER specific bits */ 543/* CM_FCLKEN_PER specific bits */
528 544
@@ -598,7 +614,8 @@
598#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) 614#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
599 615
600/* CM_CLKSTST_PER */ 616/* CM_CLKSTST_PER */
601#define OMAP3430_CLKACTIVITY_PER (1 << 0) 617#define OMAP3430_CLKACTIVITY_PER_SHIFT 0
618#define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0)
602 619
603/* CM_CLKSEL1_EMU */ 620/* CM_CLKSEL1_EMU */
604#define OMAP3430_DIV_DPLL4_SHIFT 24 621#define OMAP3430_DIV_DPLL4_SHIFT 24
@@ -623,7 +640,8 @@
623#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) 640#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
624 641
625/* CM_CLKSTST_EMU */ 642/* CM_CLKSTST_EMU */
626#define OMAP3430_CLKACTIVITY_EMU (1 << 0) 643#define OMAP3430_CLKACTIVITY_EMU_SHIFT 0
644#define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0)
627 645
628/* CM_CLKSEL2_EMU specific bits */ 646/* CM_CLKSEL2_EMU specific bits */
629#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 647#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
@@ -673,6 +691,8 @@
673#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 691#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
674#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) 692#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
675 693
676 694/* CM_CLKSTST_USBHOST */
695#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0
696#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0)
677 697
678#endif 698#endif
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 5f73cf0bb7ef..371e5409fef0 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -28,6 +28,9 @@
28 28
29#include "powerdomains.h" 29#include "powerdomains.h"
30 30
31#include <mach/clockdomain.h>
32#include "clockdomains.h"
33
31extern void omap_sram_init(void); 34extern void omap_sram_init(void);
32extern int omap2_clk_init(void); 35extern int omap2_clk_init(void);
33extern void omap2_check_revision(void); 36extern void omap2_check_revision(void);
@@ -106,6 +109,7 @@ void __init omap2_init_common_hw(void)
106{ 109{
107 omap2_mux_init(); 110 omap2_mux_init();
108 pwrdm_init(powerdomains_omap); 111 pwrdm_init(powerdomains_omap);
112 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
109 omap2_clk_init(); 113 omap2_clk_init();
110/* 114/*
111 * Need to Fix this for 2430 115 * Need to Fix this for 2430