aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm
diff options
context:
space:
mode:
authorPaul Walmsley <paul@pwsan.com>2008-10-09 10:51:28 -0400
committerTony Lindgren <tony@atomide.com>2008-10-09 10:51:28 -0400
commit2e7509e5b3acc4b8653faa1966e5ac234d36ac82 (patch)
tree734ad4fa94498e21ca0095319823b9f8a8ee6b8b /arch/arm
parent646e3ed1a349fbccce651fed2d3987f0e7b0f0f4 (diff)
ARM: OMAP2: Fix sparse, checkpatch warnings in OMAP2/3 IRQ code
Fix sparse warnings in mach-omap2/irq.c. Fix by defining intc_bank_write_reg() and intc_bank_read_reg(), and convert INTC module register access to use them rather than __raw_{read,write}l. Also clear up some checkpatch warnings involving includes from asm/ rather than linux/. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-omap2/irq.c69
1 files changed, 40 insertions, 29 deletions
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index a5c748a4a56d..c39e26dc5ee3 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -13,17 +13,23 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/interrupt.h> 15#include <linux/interrupt.h>
16#include <linux/io.h>
16#include <mach/hardware.h> 17#include <mach/hardware.h>
17#include <asm/mach/irq.h> 18#include <asm/mach/irq.h>
18#include <asm/irq.h>
19#include <asm/io.h>
20 19
21#define INTC_REVISION 0x0000 20
22#define INTC_SYSCONFIG 0x0010 21/* selected INTC register offsets */
23#define INTC_SYSSTATUS 0x0014 22
24#define INTC_CONTROL 0x0048 23#define INTC_REVISION 0x0000
25#define INTC_MIR_CLEAR0 0x0088 24#define INTC_SYSCONFIG 0x0010
26#define INTC_MIR_SET0 0x008c 25#define INTC_SYSSTATUS 0x0014
26#define INTC_CONTROL 0x0048
27#define INTC_MIR_CLEAR0 0x0088
28#define INTC_MIR_SET0 0x008c
29#define INTC_PENDING_IRQ0 0x0098
30
31/* Number of IRQ state bits in each MIR register */
32#define IRQ_BITS_PER_REG 32
27 33
28/* 34/*
29 * OMAP2 has a number of different interrupt controllers, each interrupt 35 * OMAP2 has a number of different interrupt controllers, each interrupt
@@ -42,36 +48,40 @@ static struct omap_irq_bank {
42 }, 48 },
43}; 49};
44 50
51/* INTC bank register get/set */
52
53static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
54{
55 __raw_writel(val, bank->base_reg + reg);
56}
57
58static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
59{
60 return __raw_readl(bank->base_reg + reg);
61}
62
45/* XXX: FIQ and additional INTC support (only MPU at the moment) */ 63/* XXX: FIQ and additional INTC support (only MPU at the moment) */
46static void omap_ack_irq(unsigned int irq) 64static void omap_ack_irq(unsigned int irq)
47{ 65{
48 __raw_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL); 66 intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
49} 67}
50 68
51static void omap_mask_irq(unsigned int irq) 69static void omap_mask_irq(unsigned int irq)
52{ 70{
53 int offset = (irq >> 5) << 5; 71 int offset = irq & (~(IRQ_BITS_PER_REG - 1));
54 72
55 if (irq >= 64) { 73 irq &= (IRQ_BITS_PER_REG - 1);
56 irq %= 64;
57 } else if (irq >= 32) {
58 irq %= 32;
59 }
60 74
61 __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset); 75 intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
62} 76}
63 77
64static void omap_unmask_irq(unsigned int irq) 78static void omap_unmask_irq(unsigned int irq)
65{ 79{
66 int offset = (irq >> 5) << 5; 80 int offset = irq & (~(IRQ_BITS_PER_REG - 1));
67 81
68 if (irq >= 64) { 82 irq &= (IRQ_BITS_PER_REG - 1);
69 irq %= 64;
70 } else if (irq >= 32) {
71 irq %= 32;
72 }
73 83
74 __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset); 84 intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
75} 85}
76 86
77static void omap_mask_ack_irq(unsigned int irq) 87static void omap_mask_ack_irq(unsigned int irq)
@@ -91,20 +101,20 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
91{ 101{
92 unsigned long tmp; 102 unsigned long tmp;
93 103
94 tmp = __raw_readl(bank->base_reg + INTC_REVISION) & 0xff; 104 tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
95 printk(KERN_INFO "IRQ: Found an INTC at 0x%p " 105 printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
96 "(revision %ld.%ld) with %d interrupts\n", 106 "(revision %ld.%ld) with %d interrupts\n",
97 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); 107 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
98 108
99 tmp = __raw_readl(bank->base_reg + INTC_SYSCONFIG); 109 tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
100 tmp |= 1 << 1; /* soft reset */ 110 tmp |= 1 << 1; /* soft reset */
101 __raw_writel(tmp, bank->base_reg + INTC_SYSCONFIG); 111 intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
102 112
103 while (!(__raw_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1)) 113 while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
104 /* Wait for reset to complete */; 114 /* Wait for reset to complete */;
105 115
106 /* Enable autoidle */ 116 /* Enable autoidle */
107 __raw_writel(1 << 0, bank->base_reg + INTC_SYSCONFIG); 117 intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
108} 118}
109 119
110void __init omap_init_irq(void) 120void __init omap_init_irq(void)
@@ -117,7 +127,8 @@ void __init omap_init_irq(void)
117 struct omap_irq_bank *bank = irq_banks + i; 127 struct omap_irq_bank *bank = irq_banks + i;
118 128
119 if (cpu_is_omap24xx()) 129 if (cpu_is_omap24xx())
120 bank->base_reg = IO_ADDRESS(OMAP24XX_IC_BASE); 130 bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE);
131
121 omap_irq_bank_init_one(bank); 132 omap_irq_bank_init_one(bank);
122 133
123 nr_irqs += bank->nr_irqs; 134 nr_irqs += bank->nr_irqs;