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authorHiroshi DOYU <Hiroshi.DOYU@nokia.com>2006-12-07 18:43:59 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-05-09 05:37:10 -0400
commit340a614ac6766df18cba87ff7e66182193c2bd6d (patch)
treed1ad622625ba6933904567501a7387fc636c0a68 /arch/arm
parentc40fae9525e6c29c87a4f4361ff0a8d67a36e448 (diff)
ARM: OMAP: Add mailbox support for IVA
This patch adds a generic mailbox interface for for DSP and IVA (Image Video Accelerator). This patch itself doesn't contain any IVA driver. Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-omap1/mailbox.c206
-rw-r--r--arch/arm/mach-omap2/mailbox.c318
-rw-r--r--arch/arm/plat-omap/mailbox.c509
-rw-r--r--arch/arm/plat-omap/mailbox.h100
4 files changed, 1133 insertions, 0 deletions
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
new file mode 100644
index 000000000000..d3abf5609902
--- /dev/null
+++ b/arch/arm/mach-omap1/mailbox.c
@@ -0,0 +1,206 @@
1/*
2 * Mailbox reservation modules for DSP
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12#include <linux/kernel.h>
13#include <linux/resource.h>
14#include <linux/interrupt.h>
15#include <linux/platform_device.h>
16#include <asm/arch/mailbox.h>
17#include <asm/arch/irqs.h>
18#include <asm/io.h>
19
20#define MAILBOX_ARM2DSP1 0x00
21#define MAILBOX_ARM2DSP1b 0x04
22#define MAILBOX_DSP2ARM1 0x08
23#define MAILBOX_DSP2ARM1b 0x0c
24#define MAILBOX_DSP2ARM2 0x10
25#define MAILBOX_DSP2ARM2b 0x14
26#define MAILBOX_ARM2DSP1_Flag 0x18
27#define MAILBOX_DSP2ARM1_Flag 0x1c
28#define MAILBOX_DSP2ARM2_Flag 0x20
29
30unsigned long mbox_base;
31
32struct omap_mbox1_fifo {
33 unsigned long cmd;
34 unsigned long data;
35 unsigned long flag;
36};
37
38struct omap_mbox1_priv {
39 struct omap_mbox1_fifo tx_fifo;
40 struct omap_mbox1_fifo rx_fifo;
41};
42
43static inline int mbox_read_reg(unsigned int reg)
44{
45 return __raw_readw(mbox_base + reg);
46}
47
48static inline void mbox_write_reg(unsigned int val, unsigned int reg)
49{
50 __raw_writew(val, mbox_base + reg);
51}
52
53/* msg */
54static inline mbox_msg_t omap1_mbox_fifo_read(struct omap_mbox *mbox)
55{
56 struct omap_mbox1_fifo *fifo =
57 &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo;
58 mbox_msg_t msg;
59
60 msg = mbox_read_reg(fifo->data);
61 msg |= ((mbox_msg_t) mbox_read_reg(fifo->cmd)) << 16;
62
63 return msg;
64}
65
66static inline void
67omap1_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
68{
69 struct omap_mbox1_fifo *fifo =
70 &((struct omap_mbox1_priv *)mbox->priv)->tx_fifo;
71
72 mbox_write_reg(msg & 0xffff, fifo->data);
73 mbox_write_reg(msg >> 16, fifo->cmd);
74}
75
76static inline int omap1_mbox_fifo_empty(struct omap_mbox *mbox)
77{
78 return 0;
79}
80
81static inline int omap1_mbox_fifo_full(struct omap_mbox *mbox)
82{
83 struct omap_mbox1_fifo *fifo =
84 &((struct omap_mbox1_priv *)mbox->priv)->rx_fifo;
85
86 return (mbox_read_reg(fifo->flag));
87}
88
89/* irq */
90static inline void
91omap1_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
92{
93 if (irq == IRQ_RX)
94 enable_irq(mbox->irq);
95}
96
97static inline void
98omap1_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
99{
100 if (irq == IRQ_RX)
101 disable_irq(mbox->irq);
102}
103
104static inline int
105omap1_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_type_t irq)
106{
107 if (irq == IRQ_TX)
108 return 0;
109 return 1;
110}
111
112static struct omap_mbox_ops omap1_mbox_ops = {
113 .type = OMAP_MBOX_TYPE1,
114 .fifo_read = omap1_mbox_fifo_read,
115 .fifo_write = omap1_mbox_fifo_write,
116 .fifo_empty = omap1_mbox_fifo_empty,
117 .fifo_full = omap1_mbox_fifo_full,
118 .enable_irq = omap1_mbox_enable_irq,
119 .disable_irq = omap1_mbox_disable_irq,
120 .is_irq = omap1_mbox_is_irq,
121};
122
123/* FIXME: the following struct should be created automatically by the user id */
124
125/* DSP */
126static struct omap_mbox1_priv omap1_mbox_dsp_priv = {
127 .tx_fifo = {
128 .cmd = MAILBOX_ARM2DSP1b,
129 .data = MAILBOX_ARM2DSP1,
130 .flag = MAILBOX_ARM2DSP1_Flag,
131 },
132 .rx_fifo = {
133 .cmd = MAILBOX_DSP2ARM1b,
134 .data = MAILBOX_DSP2ARM1,
135 .flag = MAILBOX_DSP2ARM1_Flag,
136 },
137};
138
139struct omap_mbox mbox_dsp_info = {
140 .name = "dsp",
141 .ops = &omap1_mbox_ops,
142 .priv = &omap1_mbox_dsp_priv,
143};
144EXPORT_SYMBOL(mbox_dsp_info);
145
146static int __init omap1_mbox_probe(struct platform_device *pdev)
147{
148 struct resource *res;
149 int ret = 0;
150
151 if (pdev->num_resources != 2) {
152 dev_err(&pdev->dev, "invalid number of resources: %d\n",
153 pdev->num_resources);
154 return -ENODEV;
155 }
156
157 /* MBOX base */
158 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
159 if (unlikely(!res)) {
160 dev_err(&pdev->dev, "invalid mem resource\n");
161 return -ENODEV;
162 }
163 mbox_base = res->start;
164
165 /* DSP IRQ */
166 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
167 if (unlikely(!res)) {
168 dev_err(&pdev->dev, "invalid irq resource\n");
169 return -ENODEV;
170 }
171 mbox_dsp_info.irq = res->start;
172
173 ret = omap_mbox_register(&mbox_dsp_info);
174
175 return ret;
176}
177
178static int omap1_mbox_remove(struct platform_device *pdev)
179{
180 omap_mbox_unregister(&mbox_dsp_info);
181
182 return 0;
183}
184
185static struct platform_driver omap1_mbox_driver = {
186 .probe = omap1_mbox_probe,
187 .remove = omap1_mbox_remove,
188 .driver = {
189 .name = "mailbox",
190 },
191};
192
193static int __init omap1_mbox_init(void)
194{
195 return platform_driver_register(&omap1_mbox_driver);
196}
197
198static void __exit omap1_mbox_exit(void)
199{
200 platform_driver_unregister(&omap1_mbox_driver);
201}
202
203module_init(omap1_mbox_init);
204module_exit(omap1_mbox_exit);
205
206MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
new file mode 100644
index 000000000000..b03cd06e055b
--- /dev/null
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -0,0 +1,318 @@
1/*
2 * Mailbox reservation modules for OMAP2
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
6 * and Paul Mundt <paul.mundt@nokia.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/clk.h>
15#include <linux/err.h>
16#include <linux/platform_device.h>
17#include <asm/arch/mailbox.h>
18#include <asm/arch/irqs.h>
19#include <asm/io.h>
20
21#define MAILBOX_REVISION 0x00
22#define MAILBOX_SYSCONFIG 0x10
23#define MAILBOX_SYSSTATUS 0x14
24#define MAILBOX_MESSAGE_0 0x40
25#define MAILBOX_MESSAGE_1 0x44
26#define MAILBOX_MESSAGE_2 0x48
27#define MAILBOX_MESSAGE_3 0x4c
28#define MAILBOX_MESSAGE_4 0x50
29#define MAILBOX_MESSAGE_5 0x54
30#define MAILBOX_FIFOSTATUS_0 0x80
31#define MAILBOX_FIFOSTATUS_1 0x84
32#define MAILBOX_FIFOSTATUS_2 0x88
33#define MAILBOX_FIFOSTATUS_3 0x8c
34#define MAILBOX_FIFOSTATUS_4 0x90
35#define MAILBOX_FIFOSTATUS_5 0x94
36#define MAILBOX_MSGSTATUS_0 0xc0
37#define MAILBOX_MSGSTATUS_1 0xc4
38#define MAILBOX_MSGSTATUS_2 0xc8
39#define MAILBOX_MSGSTATUS_3 0xcc
40#define MAILBOX_MSGSTATUS_4 0xd0
41#define MAILBOX_MSGSTATUS_5 0xd4
42#define MAILBOX_IRQSTATUS_0 0x100
43#define MAILBOX_IRQENABLE_0 0x104
44#define MAILBOX_IRQSTATUS_1 0x108
45#define MAILBOX_IRQENABLE_1 0x10c
46#define MAILBOX_IRQSTATUS_2 0x110
47#define MAILBOX_IRQENABLE_2 0x114
48#define MAILBOX_IRQSTATUS_3 0x118
49#define MAILBOX_IRQENABLE_3 0x11c
50
51static unsigned long mbox_base;
52
53#define MAILBOX_IRQ_NOTFULL(n) (1 << (2 * (n) + 1))
54#define MAILBOX_IRQ_NEWMSG(n) (1 << (2 * (n)))
55
56struct omap_mbox2_fifo {
57 unsigned long msg;
58 unsigned long fifo_stat;
59 unsigned long msg_stat;
60};
61
62struct omap_mbox2_priv {
63 struct omap_mbox2_fifo tx_fifo;
64 struct omap_mbox2_fifo rx_fifo;
65 unsigned long irqenable;
66 unsigned long irqstatus;
67 u32 newmsg_bit;
68 u32 notfull_bit;
69};
70
71static struct clk *mbox_ick_handle;
72
73static inline unsigned int mbox_read_reg(unsigned int reg)
74{
75 return __raw_readl(mbox_base + reg);
76}
77
78static inline void mbox_write_reg(unsigned int val, unsigned int reg)
79{
80 __raw_writel(val, mbox_base + reg);
81}
82
83/* Mailbox H/W preparations */
84static inline int omap2_mbox_startup(struct omap_mbox *mbox)
85{
86 unsigned int l;
87
88 mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
89 if (IS_ERR(mbox_ick_handle)) {
90 printk("Could not get mailboxes_ick\n");
91 return -ENODEV;
92 }
93 clk_enable(mbox_ick_handle);
94
95 /* set smart-idle & autoidle */
96 l = mbox_read_reg(MAILBOX_SYSCONFIG);
97 l |= 0x00000011;
98 mbox_write_reg(l, MAILBOX_SYSCONFIG);
99
100 return 0;
101}
102
103static inline void omap2_mbox_shutdown(struct omap_mbox *mbox)
104{
105 clk_disable(mbox_ick_handle);
106 clk_put(mbox_ick_handle);
107}
108
109/* Mailbox FIFO handle functions */
110static inline mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
111{
112 struct omap_mbox2_fifo *fifo =
113 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
114 return (mbox_msg_t) mbox_read_reg(fifo->msg);
115}
116
117static inline void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
118{
119 struct omap_mbox2_fifo *fifo =
120 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
121 mbox_write_reg(msg, fifo->msg);
122}
123
124static inline int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
125{
126 struct omap_mbox2_fifo *fifo =
127 &((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
128 return (mbox_read_reg(fifo->msg_stat) == 0);
129}
130
131static inline int omap2_mbox_fifo_full(struct omap_mbox *mbox)
132{
133 struct omap_mbox2_fifo *fifo =
134 &((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
135 return (mbox_read_reg(fifo->fifo_stat));
136}
137
138/* Mailbox IRQ handle functions */
139static inline void omap2_mbox_enable_irq(struct omap_mbox *mbox,
140 omap_mbox_type_t irq)
141{
142 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
143 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
144
145 l = mbox_read_reg(p->irqenable);
146 l |= bit;
147 mbox_write_reg(l, p->irqenable);
148}
149
150static inline void omap2_mbox_disable_irq(struct omap_mbox *mbox,
151 omap_mbox_type_t irq)
152{
153 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
154 u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
155
156 l = mbox_read_reg(p->irqenable);
157 l &= ~bit;
158 mbox_write_reg(l, p->irqenable);
159}
160
161static inline void omap2_mbox_ack_irq(struct omap_mbox *mbox,
162 omap_mbox_type_t irq)
163{
164 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
165 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
166
167 mbox_write_reg(bit, p->irqstatus);
168}
169
170static inline int omap2_mbox_is_irq(struct omap_mbox *mbox,
171 omap_mbox_type_t irq)
172{
173 struct omap_mbox2_priv *p = (struct omap_mbox2_priv *)mbox->priv;
174 u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
175 u32 enable = mbox_read_reg(p->irqenable);
176 u32 status = mbox_read_reg(p->irqstatus);
177
178 return (enable & status & bit);
179}
180
181static struct omap_mbox_ops omap2_mbox_ops = {
182 .type = OMAP_MBOX_TYPE2,
183 .startup = omap2_mbox_startup,
184 .shutdown = omap2_mbox_shutdown,
185 .fifo_read = omap2_mbox_fifo_read,
186 .fifo_write = omap2_mbox_fifo_write,
187 .fifo_empty = omap2_mbox_fifo_empty,
188 .fifo_full = omap2_mbox_fifo_full,
189 .enable_irq = omap2_mbox_enable_irq,
190 .disable_irq = omap2_mbox_disable_irq,
191 .ack_irq = omap2_mbox_ack_irq,
192 .is_irq = omap2_mbox_is_irq,
193};
194
195/*
196 * MAILBOX 0: ARM -> DSP,
197 * MAILBOX 1: ARM <- DSP.
198 * MAILBOX 2: ARM -> IVA,
199 * MAILBOX 3: ARM <- IVA.
200 */
201
202/* FIXME: the following structs should be filled automatically by the user id */
203
204/* DSP */
205static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
206 .tx_fifo = {
207 .msg = MAILBOX_MESSAGE_0,
208 .fifo_stat = MAILBOX_FIFOSTATUS_0,
209 },
210 .rx_fifo = {
211 .msg = MAILBOX_MESSAGE_1,
212 .msg_stat = MAILBOX_MSGSTATUS_1,
213 },
214 .irqenable = MAILBOX_IRQENABLE_0,
215 .irqstatus = MAILBOX_IRQSTATUS_0,
216 .notfull_bit = MAILBOX_IRQ_NOTFULL(0),
217 .newmsg_bit = MAILBOX_IRQ_NEWMSG(1),
218};
219
220struct omap_mbox mbox_dsp_info = {
221 .name = "dsp",
222 .ops = &omap2_mbox_ops,
223 .priv = &omap2_mbox_dsp_priv,
224};
225EXPORT_SYMBOL(mbox_dsp_info);
226
227/* IVA */
228static struct omap_mbox2_priv omap2_mbox_iva_priv = {
229 .tx_fifo = {
230 .msg = MAILBOX_MESSAGE_2,
231 .fifo_stat = MAILBOX_FIFOSTATUS_2,
232 },
233 .rx_fifo = {
234 .msg = MAILBOX_MESSAGE_3,
235 .msg_stat = MAILBOX_MSGSTATUS_3,
236 },
237 .irqenable = MAILBOX_IRQENABLE_3,
238 .irqstatus = MAILBOX_IRQSTATUS_3,
239 .notfull_bit = MAILBOX_IRQ_NOTFULL(2),
240 .newmsg_bit = MAILBOX_IRQ_NEWMSG(3),
241};
242
243static struct omap_mbox mbox_iva_info = {
244 .name = "iva",
245 .ops = &omap2_mbox_ops,
246 .priv = &omap2_mbox_iva_priv,
247};
248
249static int __init omap2_mbox_probe(struct platform_device *pdev)
250{
251 struct resource *res;
252 int ret = 0;
253
254 if (pdev->num_resources != 3) {
255 dev_err(&pdev->dev, "invalid number of resources: %d\n",
256 pdev->num_resources);
257 return -ENODEV;
258 }
259
260 /* MBOX base */
261 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
262 if (unlikely(!res)) {
263 dev_err(&pdev->dev, "invalid mem resource\n");
264 return -ENODEV;
265 }
266 mbox_base = res->start;
267
268 /* DSP IRQ */
269 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
270 if (unlikely(!res)) {
271 dev_err(&pdev->dev, "invalid irq resource\n");
272 return -ENODEV;
273 }
274 mbox_dsp_info.irq = res->start;
275
276 ret = omap_mbox_register(&mbox_dsp_info);
277
278 /* IVA IRQ */
279 res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
280 if (unlikely(!res)) {
281 dev_err(&pdev->dev, "invalid irq resource\n");
282 return -ENODEV;
283 }
284 mbox_iva_info.irq = res->start;
285
286 ret = omap_mbox_register(&mbox_iva_info);
287
288 return ret;
289}
290
291static int omap2_mbox_remove(struct platform_device *pdev)
292{
293 omap_mbox_unregister(&mbox_dsp_info);
294 return 0;
295}
296
297static struct platform_driver omap2_mbox_driver = {
298 .probe = omap2_mbox_probe,
299 .remove = omap2_mbox_remove,
300 .driver = {
301 .name = "mailbox",
302 },
303};
304
305static int __init omap2_mbox_init(void)
306{
307 return platform_driver_register(&omap2_mbox_driver);
308}
309
310static void __exit omap2_mbox_exit(void)
311{
312 platform_driver_unregister(&omap2_mbox_driver);
313}
314
315module_init(omap2_mbox_init);
316module_exit(omap2_mbox_exit);
317
318MODULE_LICENSE("GPL");
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
new file mode 100644
index 000000000000..de7e6ef48bd0
--- /dev/null
+++ b/arch/arm/plat-omap/mailbox.c
@@ -0,0 +1,509 @@
1/*
2 * OMAP mailbox driver
3 *
4 * Copyright (C) 2006 Nokia Corporation. All rights reserved.
5 *
6 * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com>
7 * Restructured by Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/sched.h>
28#include <linux/interrupt.h>
29#include <linux/device.h>
30#include <linux/blkdev.h>
31#include <linux/err.h>
32#include <linux/delay.h>
33#include <asm/io.h>
34#include <asm/arch/mailbox.h>
35#include "mailbox.h"
36
37static struct omap_mbox *mboxes;
38static DEFINE_RWLOCK(mboxes_lock);
39
40/* Mailbox Sequence Bit function */
41void omap_mbox_init_seq(struct omap_mbox *mbox)
42{
43 mbox_seq_init(mbox);
44}
45EXPORT_SYMBOL(omap_mbox_init_seq);
46
47/*
48 * message sender
49 */
50static int __mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg, void *arg)
51{
52 int ret = 0, i = 1000;
53
54 while (mbox_fifo_full(mbox)) {
55 if (mbox->ops->type == OMAP_MBOX_TYPE2)
56 return -1;
57 if (--i == 0)
58 return -1;
59 udelay(1);
60 }
61
62 if (arg && mbox->txq->callback) {
63 ret = mbox->txq->callback(arg);
64 if (ret)
65 goto out;
66 }
67
68 mbox_seq_toggle(mbox, &msg);
69 mbox_fifo_write(mbox, msg);
70 out:
71 return ret;
72}
73
74int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg, void* arg)
75{
76 struct request *rq;
77 struct request_queue *q = mbox->txq->queue;
78 int ret = 0;
79
80 rq = blk_get_request(q, WRITE, GFP_ATOMIC);
81 if (unlikely(!rq)) {
82 ret = -ENOMEM;
83 goto fail;
84 }
85
86 rq->data = (void *)msg;
87 blk_insert_request(q, rq, 0, arg);
88
89 schedule_work(&mbox->txq->work);
90 fail:
91 return ret;
92}
93EXPORT_SYMBOL(omap_mbox_msg_send);
94
95static void mbox_tx_work(struct work_struct *work)
96{
97 int ret;
98 struct request *rq;
99 struct omap_mbox_queue *mq = container_of(work,
100 struct omap_mbox_queue, work);
101 struct omap_mbox *mbox = mq->queue->queuedata;
102 struct request_queue *q = mbox->txq->queue;
103
104 while (1) {
105 spin_lock(q->queue_lock);
106 rq = elv_next_request(q);
107 spin_unlock(q->queue_lock);
108
109 if (!rq)
110 break;
111
112 ret = __mbox_msg_send(mbox, (mbox_msg_t) rq->data, rq->special);
113 if (ret) {
114 enable_mbox_irq(mbox, IRQ_TX);
115 return;
116 }
117
118 spin_lock(q->queue_lock);
119 blkdev_dequeue_request(rq);
120 end_that_request_last(rq, 0);
121 spin_unlock(q->queue_lock);
122 }
123}
124
125/*
126 * Message receiver(workqueue)
127 */
128static void mbox_rx_work(struct work_struct *work)
129{
130 struct omap_mbox_queue *mq =
131 container_of(work, struct omap_mbox_queue, work);
132 struct omap_mbox *mbox = mq->queue->queuedata;
133 struct request_queue *q = mbox->rxq->queue;
134 struct request *rq;
135 mbox_msg_t msg;
136 unsigned long flags;
137
138 if (mbox->rxq->callback == NULL) {
139 sysfs_notify(&mbox->dev.kobj, NULL, "mbox");
140 return;
141 }
142
143 while (1) {
144 spin_lock_irqsave(q->queue_lock, flags);
145 rq = elv_next_request(q);
146 spin_unlock_irqrestore(q->queue_lock, flags);
147 if (!rq)
148 break;
149
150 msg = (mbox_msg_t) rq->data;
151
152 spin_lock_irqsave(q->queue_lock, flags);
153 blkdev_dequeue_request(rq);
154 end_that_request_last(rq, 0);
155 spin_unlock_irqrestore(q->queue_lock, flags);
156
157 mbox->rxq->callback((void *)msg);
158 }
159}
160
161/*
162 * Mailbox interrupt handler
163 */
164static void mbox_txq_fn(request_queue_t * q)
165{
166}
167
168static void mbox_rxq_fn(request_queue_t * q)
169{
170}
171
172static void __mbox_tx_interrupt(struct omap_mbox *mbox)
173{
174 disable_mbox_irq(mbox, IRQ_TX);
175 ack_mbox_irq(mbox, IRQ_TX);
176 schedule_work(&mbox->txq->work);
177}
178
179static void __mbox_rx_interrupt(struct omap_mbox *mbox)
180{
181 struct request *rq;
182 mbox_msg_t msg;
183 request_queue_t *q = mbox->rxq->queue;
184
185 disable_mbox_irq(mbox, IRQ_RX);
186
187 while (!mbox_fifo_empty(mbox)) {
188 rq = blk_get_request(q, WRITE, GFP_ATOMIC);
189 if (unlikely(!rq))
190 goto nomem;
191
192 msg = mbox_fifo_read(mbox);
193 rq->data = (void *)msg;
194
195 if (unlikely(mbox_seq_test(mbox, msg))) {
196 pr_info("mbox: Illegal seq bit!(%08x)\n", msg);
197 if (mbox->err_notify)
198 mbox->err_notify();
199 }
200
201 blk_insert_request(q, rq, 0, NULL);
202 if (mbox->ops->type == OMAP_MBOX_TYPE1)
203 break;
204 }
205
206 /* no more messages in the fifo. clear IRQ source. */
207 ack_mbox_irq(mbox, IRQ_RX);
208 enable_mbox_irq(mbox, IRQ_RX);
209 nomem:
210 schedule_work(&mbox->rxq->work);
211}
212
213static irqreturn_t mbox_interrupt(int irq, void *p)
214{
215 struct omap_mbox *mbox = (struct omap_mbox *)p;
216
217 if (is_mbox_irq(mbox, IRQ_TX))
218 __mbox_tx_interrupt(mbox);
219
220 if (is_mbox_irq(mbox, IRQ_RX))
221 __mbox_rx_interrupt(mbox);
222
223 return IRQ_HANDLED;
224}
225
226/*
227 * sysfs files
228 */
229static ssize_t
230omap_mbox_write(struct device *dev, struct device_attribute *attr,
231 const char * buf, size_t count)
232{
233 int ret;
234 mbox_msg_t *p = (mbox_msg_t *)buf;
235 struct omap_mbox *mbox = dev_get_drvdata(dev);
236
237 for (; count >= sizeof(mbox_msg_t); count -= sizeof(mbox_msg_t)) {
238 ret = omap_mbox_msg_send(mbox, be32_to_cpu(*p), NULL);
239 if (ret)
240 return -EAGAIN;
241 p++;
242 }
243
244 return (size_t)((char *)p - buf);
245}
246
247static ssize_t
248omap_mbox_read(struct device *dev, struct device_attribute *attr, char *buf)
249{
250 unsigned long flags;
251 struct request *rq;
252 mbox_msg_t *p = (mbox_msg_t *) buf;
253 struct omap_mbox *mbox = dev_get_drvdata(dev);
254 struct request_queue *q = mbox->rxq->queue;
255
256 while (1) {
257 spin_lock_irqsave(q->queue_lock, flags);
258 rq = elv_next_request(q);
259 spin_unlock_irqrestore(q->queue_lock, flags);
260
261 if (!rq)
262 break;
263
264 *p = (mbox_msg_t) rq->data;
265
266 spin_lock_irqsave(q->queue_lock, flags);
267 blkdev_dequeue_request(rq);
268 end_that_request_last(rq, 0);
269 spin_unlock_irqrestore(q->queue_lock, flags);
270
271 if (unlikely(mbox_seq_test(mbox, *p))) {
272 pr_info("mbox: Illegal seq bit!(%08x) ignored\n", *p);
273 continue;
274 }
275 p++;
276 }
277
278 pr_debug("%02x %02x %02x %02x\n", buf[0], buf[1], buf[2], buf[3]);
279
280 return (size_t) ((char *)p - buf);
281}
282
283static DEVICE_ATTR(mbox, S_IRUGO | S_IWUSR, omap_mbox_read, omap_mbox_write);
284
285static ssize_t mbox_show(struct class *class, char *buf)
286{
287 return sprintf(buf, "mbox");
288}
289
290static CLASS_ATTR(mbox, S_IRUGO, mbox_show, NULL);
291
292static struct class omap_mbox_class = {
293 .name = "omap_mbox",
294};
295
296static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
297 request_fn_proc * proc,
298 void (*work) (struct work_struct *))
299{
300 request_queue_t *q;
301 struct omap_mbox_queue *mq;
302
303 mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL);
304 if (!mq)
305 return NULL;
306
307 spin_lock_init(&mq->lock);
308
309 q = blk_init_queue(proc, &mq->lock);
310 if (!q)
311 goto error;
312 q->queuedata = mbox;
313 mq->queue = q;
314
315 INIT_WORK(&mq->work, work);
316
317 return mq;
318error:
319 kfree(mq);
320 return NULL;
321}
322
323static void mbox_queue_free(struct omap_mbox_queue *q)
324{
325 blk_cleanup_queue(q->queue);
326 kfree(q);
327}
328
329static int omap_mbox_init(struct omap_mbox *mbox)
330{
331 int ret;
332 struct omap_mbox_queue *mq;
333
334 if (likely(mbox->ops->startup)) {
335 ret = mbox->ops->startup(mbox);
336 if (unlikely(ret))
337 return ret;
338 }
339
340 mbox->dev.class = &omap_mbox_class;
341 strlcpy(mbox->dev.bus_id, mbox->name, KOBJ_NAME_LEN);
342 dev_set_drvdata(&mbox->dev, mbox);
343
344 ret = device_register(&mbox->dev);
345 if (unlikely(ret))
346 goto fail_device_reg;
347
348 ret = device_create_file(&mbox->dev, &dev_attr_mbox);
349 if (unlikely(ret)) {
350 printk(KERN_ERR
351 "device_create_file failed: %d\n", ret);
352 goto fail_create_mbox;
353 }
354
355 ret = request_irq(mbox->irq, mbox_interrupt, IRQF_DISABLED,
356 mbox->name, mbox);
357 if (unlikely(ret)) {
358 printk(KERN_ERR
359 "failed to register mailbox interrupt:%d\n", ret);
360 goto fail_request_irq;
361 }
362 enable_mbox_irq(mbox, IRQ_RX);
363
364 mq = mbox_queue_alloc(mbox, mbox_txq_fn, mbox_tx_work);
365 if (!mq) {
366 ret = -ENOMEM;
367 goto fail_alloc_txq;
368 }
369 mbox->txq = mq;
370
371 mq = mbox_queue_alloc(mbox, mbox_rxq_fn, mbox_rx_work);
372 if (!mq) {
373 ret = -ENOMEM;
374 goto fail_alloc_rxq;
375 }
376 mbox->rxq = mq;
377
378 return 0;
379
380 fail_alloc_rxq:
381 mbox_queue_free(mbox->txq);
382 fail_alloc_txq:
383 free_irq(mbox->irq, mbox);
384 fail_request_irq:
385 device_remove_file(&mbox->dev, &dev_attr_mbox);
386 fail_create_mbox:
387 device_unregister(&mbox->dev);
388 fail_device_reg:
389 if (unlikely(mbox->ops->shutdown))
390 mbox->ops->shutdown(mbox);
391
392 return ret;
393}
394
395static void omap_mbox_fini(struct omap_mbox *mbox)
396{
397 mbox_queue_free(mbox->txq);
398 mbox_queue_free(mbox->rxq);
399
400 free_irq(mbox->irq, mbox);
401 device_remove_file(&mbox->dev, &dev_attr_mbox);
402 class_unregister(&omap_mbox_class);
403
404 if (unlikely(mbox->ops->shutdown))
405 mbox->ops->shutdown(mbox);
406}
407
408static struct omap_mbox **find_mboxes(const char *name)
409{
410 struct omap_mbox **p;
411
412 for (p = &mboxes; *p; p = &(*p)->next) {
413 if (strcmp((*p)->name, name) == 0)
414 break;
415 }
416
417 return p;
418}
419
420struct omap_mbox *omap_mbox_get(const char *name)
421{
422 struct omap_mbox *mbox;
423 int ret;
424
425 read_lock(&mboxes_lock);
426 mbox = *(find_mboxes(name));
427 if (mbox == NULL) {
428 read_unlock(&mboxes_lock);
429 return ERR_PTR(-ENOENT);
430 }
431
432 read_unlock(&mboxes_lock);
433
434 ret = omap_mbox_init(mbox);
435 if (ret)
436 return ERR_PTR(-ENODEV);
437
438 return mbox;
439}
440EXPORT_SYMBOL(omap_mbox_get);
441
442void omap_mbox_put(struct omap_mbox *mbox)
443{
444 omap_mbox_fini(mbox);
445}
446EXPORT_SYMBOL(omap_mbox_put);
447
448int omap_mbox_register(struct omap_mbox *mbox)
449{
450 int ret = 0;
451 struct omap_mbox **tmp;
452
453 if (!mbox)
454 return -EINVAL;
455 if (mbox->next)
456 return -EBUSY;
457
458 write_lock(&mboxes_lock);
459 tmp = find_mboxes(mbox->name);
460 if (*tmp)
461 ret = -EBUSY;
462 else
463 *tmp = mbox;
464 write_unlock(&mboxes_lock);
465
466 return ret;
467}
468EXPORT_SYMBOL(omap_mbox_register);
469
470int omap_mbox_unregister(struct omap_mbox *mbox)
471{
472 struct omap_mbox **tmp;
473
474 write_lock(&mboxes_lock);
475 tmp = &mboxes;
476 while (*tmp) {
477 if (mbox == *tmp) {
478 *tmp = mbox->next;
479 mbox->next = NULL;
480 write_unlock(&mboxes_lock);
481 return 0;
482 }
483 tmp = &(*tmp)->next;
484 }
485 write_unlock(&mboxes_lock);
486
487 return -EINVAL;
488}
489EXPORT_SYMBOL(omap_mbox_unregister);
490
491static int __init omap_mbox_class_init(void)
492{
493 int ret = class_register(&omap_mbox_class);
494 if (!ret)
495 ret = class_create_file(&omap_mbox_class, &class_attr_mbox);
496
497 return ret;
498}
499
500static void __exit omap_mbox_class_exit(void)
501{
502 class_remove_file(&omap_mbox_class, &class_attr_mbox);
503 class_unregister(&omap_mbox_class);
504}
505
506subsys_initcall(omap_mbox_class_init);
507module_exit(omap_mbox_class_exit);
508
509MODULE_LICENSE("GPL");
diff --git a/arch/arm/plat-omap/mailbox.h b/arch/arm/plat-omap/mailbox.h
new file mode 100644
index 000000000000..67c6740b8ad5
--- /dev/null
+++ b/arch/arm/plat-omap/mailbox.h
@@ -0,0 +1,100 @@
1/*
2 * Mailbox internal functions
3 *
4 * Copyright (C) 2006 Nokia Corporation
5 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12#ifndef __ARCH_ARM_PLAT_MAILBOX_H
13#define __ARCH_ARM_PLAT_MAILBOX_H
14
15/*
16 * Mailbox sequence bit API
17 */
18#if defined(CONFIG_ARCH_OMAP1)
19# define MBOX_USE_SEQ_BIT
20#elif defined(CONFIG_ARCH_OMAP2)
21# define MBOX_USE_SEQ_BIT
22#endif
23
24#ifdef MBOX_USE_SEQ_BIT
25/* seq_rcv should be initialized with any value other than
26 * 0 and 1 << 31, to allow either value for the first
27 * message. */
28static inline void mbox_seq_init(struct omap_mbox *mbox)
29{
30 /* any value other than 0 and 1 << 31 */
31 mbox->seq_rcv = 0xffffffff;
32}
33
34static inline void mbox_seq_toggle(struct omap_mbox *mbox, mbox_msg_t * msg)
35{
36 /* add seq_snd to msg */
37 *msg = (*msg & 0x7fffffff) | mbox->seq_snd;
38 /* flip seq_snd */
39 mbox->seq_snd ^= 1 << 31;
40}
41
42static inline int mbox_seq_test(struct omap_mbox *mbox, mbox_msg_t msg)
43{
44 mbox_msg_t seq = msg & (1 << 31);
45 if (seq == mbox->seq_rcv)
46 return -1;
47 mbox->seq_rcv = seq;
48 return 0;
49}
50#else
51static inline void mbox_seq_init(struct omap_mbox *mbox)
52{
53}
54static inline void mbox_seq_toggle(struct omap_mbox *mbox, mbox_msg_t * msg)
55{
56}
57static inline int mbox_seq_test(struct omap_mbox *mbox, mbox_msg_t msg)
58{
59 return 0;
60}
61#endif
62
63/* Mailbox FIFO handle functions */
64static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
65{
66 return mbox->ops->fifo_read(mbox);
67}
68static inline void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
69{
70 mbox->ops->fifo_write(mbox, msg);
71}
72static inline int mbox_fifo_empty(struct omap_mbox *mbox)
73{
74 return mbox->ops->fifo_empty(mbox);
75}
76static inline int mbox_fifo_full(struct omap_mbox *mbox)
77{
78 return mbox->ops->fifo_full(mbox);
79}
80
81/* Mailbox IRQ handle functions */
82static inline void enable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
83{
84 mbox->ops->enable_irq(mbox, irq);
85}
86static inline void disable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
87{
88 mbox->ops->disable_irq(mbox, irq);
89}
90static inline void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
91{
92 if (mbox->ops->ack_irq)
93 mbox->ops->ack_irq(mbox, irq);
94}
95static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
96{
97 return mbox->ops->is_irq(mbox, irq);
98}
99
100#endif /* __ARCH_ARM_PLAT_MAILBOX_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 02:05:38 -0500