aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm
diff options
context:
space:
mode:
authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-07-10 11:41:50 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-07-10 11:41:50 -0400
commitf0006314d37639714da9658cf4ff3f1f9f420764 (patch)
treeb8a18e014a40f2f8fd5148aab09c869dfaabd7a9 /arch/arm
parenta177ba3b7a08beef3f0fe74efa0f90701891945a (diff)
parent1bd55a436f1f90de0e7f476e514e01bd67497b88 (diff)
Merge branch 'imx' into devel
Conflicts: arch/arm/mm/Kconfig
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig4
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/configs/imx27ads_defconfig826
-rw-r--r--arch/arm/configs/mx31ads_defconfig839
-rw-r--r--arch/arm/configs/mx31litekit_defconfig1100
-rw-r--r--arch/arm/configs/pcm037_defconfig748
-rw-r--r--arch/arm/configs/pcm038_defconfig1008
-rw-r--r--arch/arm/mach-imx/Makefile2
-rw-r--r--arch/arm/mach-imx/clock.c205
-rw-r--r--arch/arm/mach-imx/cpufreq.c20
-rw-r--r--arch/arm/mach-imx/generic.c76
-rw-r--r--arch/arm/mach-imx/mx1ads.c10
-rw-r--r--arch/arm/mach-imx/time.c23
-rw-r--r--arch/arm/mach-mx2/Kconfig39
-rw-r--r--arch/arm/mach-mx2/Makefile14
-rw-r--r--arch/arm/mach-mx2/Makefile.boot3
-rw-r--r--arch/arm/mach-mx2/clock_imx27.c1626
-rw-r--r--arch/arm/mach-mx2/cpu_imx27.c63
-rw-r--r--arch/arm/mach-mx2/crm_regs.h273
-rw-r--r--arch/arm/mach-mx2/devices.c231
-rw-r--r--arch/arm/mach-mx2/generic.c74
-rw-r--r--arch/arm/mach-mx2/mx27ads.c304
-rw-r--r--arch/arm/mach-mx2/pcm038.c204
-rw-r--r--arch/arm/mach-mx2/pcm970-baseboard.c32
-rw-r--r--arch/arm/mach-mx2/serial.c177
-rw-r--r--arch/arm/mach-mx2/system.c63
-rw-r--r--arch/arm/mach-mx3/Kconfig13
-rw-r--r--arch/arm/mach-mx3/Makefile4
-rw-r--r--arch/arm/mach-mx3/clock.c1147
-rw-r--r--arch/arm/mach-mx3/crm_regs.h401
-rw-r--r--arch/arm/mach-mx3/devices.c180
-rw-r--r--arch/arm/mach-mx3/iomux.c111
-rw-r--r--arch/arm/mach-mx3/mx31ads.c14
-rw-r--r--arch/arm/mach-mx3/mx31lite.c107
-rw-r--r--arch/arm/mach-mx3/pcm037.c130
-rw-r--r--arch/arm/mach-mx3/time.c148
-rw-r--r--arch/arm/mm/Kconfig17
-rw-r--r--arch/arm/plat-mxc/Kconfig8
-rw-r--r--arch/arm/plat-mxc/Makefile4
-rw-r--r--arch/arm/plat-mxc/clock.c331
-rw-r--r--arch/arm/plat-mxc/gpio.c253
-rw-r--r--arch/arm/plat-mxc/iomux-mx1-mx2.c156
-rw-r--r--arch/arm/plat-mxc/irq.c70
-rw-r--r--arch/arm/plat-mxc/time.c228
44 files changed, 11031 insertions, 256 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b92925c70172..3d9397ec746d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -401,7 +401,11 @@ config ARCH_MV78XX0
401 401
402config ARCH_MXC 402config ARCH_MXC
403 bool "Freescale MXC/iMX-based" 403 bool "Freescale MXC/iMX-based"
404 select GENERIC_TIME
405 select GENERIC_CLOCKEVENTS
404 select ARCH_MTD_XIP 406 select ARCH_MTD_XIP
407 select GENERIC_GPIO
408 select HAVE_GPIO_LIB
405 help 409 help
406 Support for Freescale MXC/iMX-based family of processors 410 Support for Freescale MXC/iMX-based family of processors
407 411
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 91fac81833e8..b20995a82e04 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -136,6 +136,7 @@ endif
136 machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood 136 machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood
137 machine-$(CONFIG_ARCH_KS8695) := ks8695 137 machine-$(CONFIG_ARCH_KS8695) := ks8695
138 incdir-$(CONFIG_ARCH_MXC) := mxc 138 incdir-$(CONFIG_ARCH_MXC) := mxc
139 machine-$(CONFIG_ARCH_MX2) := mx2
139 machine-$(CONFIG_ARCH_MX3) := mx3 140 machine-$(CONFIG_ARCH_MX3) := mx3
140 machine-$(CONFIG_ARCH_ORION5X) := orion5x 141 machine-$(CONFIG_ARCH_ORION5X) := orion5x
141 machine-$(CONFIG_ARCH_MSM7X00A) := msm 142 machine-$(CONFIG_ARCH_MSM7X00A) := msm
diff --git a/arch/arm/configs/imx27ads_defconfig b/arch/arm/configs/imx27ads_defconfig
new file mode 100644
index 000000000000..bcd95b8dd2df
--- /dev/null
+++ b/arch/arm/configs/imx27ads_defconfig
@@ -0,0 +1,826 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc6
4# Fri Jun 20 16:29:34 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ARCH_SUPPORTS_AOUT=y
25CONFIG_ZONE_DMA=y
26CONFIG_ARCH_MTD_XIP=y
27CONFIG_VECTORS_BASE=0xffff0000
28CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
29
30#
31# General setup
32#
33CONFIG_EXPERIMENTAL=y
34CONFIG_BROKEN_ON_SMP=y
35CONFIG_LOCK_KERNEL=y
36CONFIG_INIT_ENV_ARG_LIMIT=32
37CONFIG_LOCALVERSION=""
38CONFIG_LOCALVERSION_AUTO=y
39# CONFIG_SWAP is not set
40CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y
42CONFIG_POSIX_MQUEUE=y
43# CONFIG_BSD_PROCESS_ACCT is not set
44# CONFIG_TASKSTATS is not set
45# CONFIG_AUDIT is not set
46# CONFIG_IKCONFIG is not set
47CONFIG_LOG_BUF_SHIFT=14
48# CONFIG_CGROUPS is not set
49# CONFIG_GROUP_SCHED is not set
50CONFIG_SYSFS_DEPRECATED=y
51CONFIG_SYSFS_DEPRECATED_V2=y
52# CONFIG_RELAY is not set
53# CONFIG_NAMESPACES is not set
54# CONFIG_BLK_DEV_INITRD is not set
55# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
56CONFIG_SYSCTL=y
57CONFIG_EMBEDDED=y
58CONFIG_UID16=y
59CONFIG_SYSCTL_SYSCALL=y
60CONFIG_SYSCTL_SYSCALL_CHECK=y
61CONFIG_KALLSYMS=y
62CONFIG_KALLSYMS_EXTRA_PASS=y
63CONFIG_HOTPLUG=y
64CONFIG_PRINTK=y
65CONFIG_BUG=y
66CONFIG_ELF_CORE=y
67CONFIG_COMPAT_BRK=y
68CONFIG_BASE_FULL=y
69CONFIG_FUTEX=y
70CONFIG_ANON_INODES=y
71CONFIG_EPOLL=y
72CONFIG_SIGNALFD=y
73CONFIG_TIMERFD=y
74CONFIG_EVENTFD=y
75CONFIG_SHMEM=y
76CONFIG_VM_EVENT_COUNTERS=y
77CONFIG_SLAB=y
78# CONFIG_SLUB is not set
79# CONFIG_SLOB is not set
80# CONFIG_PROFILING is not set
81# CONFIG_MARKERS is not set
82CONFIG_HAVE_OPROFILE=y
83# CONFIG_KPROBES is not set
84CONFIG_HAVE_KPROBES=y
85CONFIG_HAVE_KRETPROBES=y
86# CONFIG_HAVE_DMA_ATTRS is not set
87CONFIG_PROC_PAGE_MONITOR=y
88CONFIG_SLABINFO=y
89CONFIG_RT_MUTEXES=y
90# CONFIG_TINY_SHMEM is not set
91CONFIG_BASE_SMALL=0
92CONFIG_MODULES=y
93# CONFIG_MODULE_FORCE_LOAD is not set
94CONFIG_MODULE_UNLOAD=y
95# CONFIG_MODULE_FORCE_UNLOAD is not set
96# CONFIG_MODVERSIONS is not set
97# CONFIG_MODULE_SRCVERSION_ALL is not set
98# CONFIG_KMOD is not set
99CONFIG_BLOCK=y
100# CONFIG_LBD is not set
101# CONFIG_BLK_DEV_IO_TRACE is not set
102# CONFIG_LSF is not set
103# CONFIG_BLK_DEV_BSG is not set
104
105#
106# IO Schedulers
107#
108CONFIG_IOSCHED_NOOP=y
109# CONFIG_IOSCHED_AS is not set
110# CONFIG_IOSCHED_DEADLINE is not set
111# CONFIG_IOSCHED_CFQ is not set
112# CONFIG_DEFAULT_AS is not set
113# CONFIG_DEFAULT_DEADLINE is not set
114# CONFIG_DEFAULT_CFQ is not set
115CONFIG_DEFAULT_NOOP=y
116CONFIG_DEFAULT_IOSCHED="noop"
117CONFIG_CLASSIC_RCU=y
118
119#
120# System Type
121#
122# CONFIG_ARCH_AAEC2000 is not set
123# CONFIG_ARCH_INTEGRATOR is not set
124# CONFIG_ARCH_REALVIEW is not set
125# CONFIG_ARCH_VERSATILE is not set
126# CONFIG_ARCH_AT91 is not set
127# CONFIG_ARCH_CLPS7500 is not set
128# CONFIG_ARCH_CLPS711X is not set
129# CONFIG_ARCH_CO285 is not set
130# CONFIG_ARCH_EBSA110 is not set
131# CONFIG_ARCH_EP93XX is not set
132# CONFIG_ARCH_FOOTBRIDGE is not set
133# CONFIG_ARCH_NETX is not set
134# CONFIG_ARCH_H720X is not set
135# CONFIG_ARCH_IMX is not set
136# CONFIG_ARCH_IOP13XX is not set
137# CONFIG_ARCH_IOP32X is not set
138# CONFIG_ARCH_IOP33X is not set
139# CONFIG_ARCH_IXP23XX is not set
140# CONFIG_ARCH_IXP2000 is not set
141# CONFIG_ARCH_IXP4XX is not set
142# CONFIG_ARCH_L7200 is not set
143# CONFIG_ARCH_KS8695 is not set
144# CONFIG_ARCH_NS9XXX is not set
145CONFIG_ARCH_MXC=y
146# CONFIG_ARCH_ORION5X is not set
147# CONFIG_ARCH_PNX4008 is not set
148# CONFIG_ARCH_PXA is not set
149# CONFIG_ARCH_RPC is not set
150# CONFIG_ARCH_SA1100 is not set
151# CONFIG_ARCH_S3C2410 is not set
152# CONFIG_ARCH_SHARK is not set
153# CONFIG_ARCH_LH7A40X is not set
154# CONFIG_ARCH_DAVINCI is not set
155# CONFIG_ARCH_OMAP is not set
156# CONFIG_ARCH_MSM7X00A is not set
157
158#
159# Boot options
160#
161
162#
163# Power management
164#
165
166#
167# Freescale MXC Implementations
168#
169CONFIG_ARCH_MX2=y
170# CONFIG_ARCH_MX3 is not set
171
172#
173# MX2 family CPU support
174#
175CONFIG_MACH_MX27=y
176
177#
178# MX2 Platforms
179#
180CONFIG_MACH_MX27ADS=y
181# CONFIG_MACH_PCM038 is not set
182
183#
184# Processor Type
185#
186CONFIG_CPU_32=y
187CONFIG_CPU_ARM926T=y
188CONFIG_CPU_32v5=y
189CONFIG_CPU_ABRT_EV5TJ=y
190CONFIG_CPU_PABRT_NOIFAR=y
191CONFIG_CPU_CACHE_VIVT=y
192CONFIG_CPU_COPY_V4WB=y
193CONFIG_CPU_TLB_V4WBI=y
194CONFIG_CPU_CP15=y
195CONFIG_CPU_CP15_MMU=y
196
197#
198# Processor Features
199#
200CONFIG_ARM_THUMB=y
201# CONFIG_CPU_ICACHE_DISABLE is not set
202# CONFIG_CPU_DCACHE_DISABLE is not set
203# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
204# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
205# CONFIG_OUTER_CACHE is not set
206
207#
208# Bus support
209#
210# CONFIG_PCI_SYSCALL is not set
211# CONFIG_ARCH_SUPPORTS_MSI is not set
212# CONFIG_PCCARD is not set
213
214#
215# Kernel Features
216#
217CONFIG_TICK_ONESHOT=y
218CONFIG_NO_HZ=y
219CONFIG_HIGH_RES_TIMERS=y
220CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
221CONFIG_PREEMPT=y
222CONFIG_HZ=100
223CONFIG_AEABI=y
224# CONFIG_OABI_COMPAT is not set
225# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
226CONFIG_SELECT_MEMORY_MODEL=y
227CONFIG_FLATMEM_MANUAL=y
228# CONFIG_DISCONTIGMEM_MANUAL is not set
229# CONFIG_SPARSEMEM_MANUAL is not set
230CONFIG_FLATMEM=y
231CONFIG_FLAT_NODE_MEM_MAP=y
232# CONFIG_SPARSEMEM_STATIC is not set
233# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
234CONFIG_PAGEFLAGS_EXTENDED=y
235CONFIG_SPLIT_PTLOCK_CPUS=4096
236# CONFIG_RESOURCES_64BIT is not set
237CONFIG_ZONE_DMA_FLAG=1
238CONFIG_BOUNCE=y
239CONFIG_VIRT_TO_BUS=y
240CONFIG_ALIGNMENT_TRAP=y
241
242#
243# Boot options
244#
245CONFIG_ZBOOT_ROM_TEXT=0x0
246CONFIG_ZBOOT_ROM_BSS=0x0
247CONFIG_CMDLINE=""
248# CONFIG_XIP_KERNEL is not set
249# CONFIG_KEXEC is not set
250
251#
252# Floating point emulation
253#
254
255#
256# At least one emulation must be selected
257#
258# CONFIG_VFP is not set
259
260#
261# Userspace binary formats
262#
263CONFIG_BINFMT_ELF=y
264# CONFIG_BINFMT_AOUT is not set
265# CONFIG_BINFMT_MISC is not set
266
267#
268# Power management options
269#
270# CONFIG_PM is not set
271CONFIG_ARCH_SUSPEND_POSSIBLE=y
272
273#
274# Networking
275#
276CONFIG_NET=y
277
278#
279# Networking options
280#
281CONFIG_PACKET=y
282CONFIG_PACKET_MMAP=y
283CONFIG_UNIX=y
284# CONFIG_NET_KEY is not set
285CONFIG_INET=y
286CONFIG_IP_MULTICAST=y
287# CONFIG_IP_ADVANCED_ROUTER is not set
288CONFIG_IP_FIB_HASH=y
289CONFIG_IP_PNP=y
290# CONFIG_IP_PNP_DHCP is not set
291# CONFIG_IP_PNP_BOOTP is not set
292# CONFIG_IP_PNP_RARP is not set
293# CONFIG_NET_IPIP is not set
294# CONFIG_NET_IPGRE is not set
295# CONFIG_IP_MROUTE is not set
296# CONFIG_ARPD is not set
297# CONFIG_SYN_COOKIES is not set
298# CONFIG_INET_AH is not set
299# CONFIG_INET_ESP is not set
300# CONFIG_INET_IPCOMP is not set
301# CONFIG_INET_XFRM_TUNNEL is not set
302# CONFIG_INET_TUNNEL is not set
303# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
304# CONFIG_INET_XFRM_MODE_TUNNEL is not set
305# CONFIG_INET_XFRM_MODE_BEET is not set
306# CONFIG_INET_LRO is not set
307# CONFIG_INET_DIAG is not set
308# CONFIG_TCP_CONG_ADVANCED is not set
309CONFIG_TCP_CONG_CUBIC=y
310CONFIG_DEFAULT_TCP_CONG="cubic"
311# CONFIG_TCP_MD5SIG is not set
312# CONFIG_IPV6 is not set
313# CONFIG_NETWORK_SECMARK is not set
314# CONFIG_NETFILTER is not set
315# CONFIG_IP_DCCP is not set
316# CONFIG_IP_SCTP is not set
317# CONFIG_TIPC is not set
318# CONFIG_ATM is not set
319# CONFIG_BRIDGE is not set
320# CONFIG_VLAN_8021Q is not set
321# CONFIG_DECNET is not set
322# CONFIG_LLC2 is not set
323# CONFIG_IPX is not set
324# CONFIG_ATALK is not set
325# CONFIG_X25 is not set
326# CONFIG_LAPB is not set
327# CONFIG_ECONET is not set
328# CONFIG_WAN_ROUTER is not set
329# CONFIG_NET_SCHED is not set
330
331#
332# Network testing
333#
334# CONFIG_NET_PKTGEN is not set
335# CONFIG_HAMRADIO is not set
336# CONFIG_CAN is not set
337# CONFIG_IRDA is not set
338# CONFIG_BT is not set
339# CONFIG_AF_RXRPC is not set
340
341#
342# Wireless
343#
344# CONFIG_CFG80211 is not set
345# CONFIG_WIRELESS_EXT is not set
346# CONFIG_MAC80211 is not set
347# CONFIG_IEEE80211 is not set
348# CONFIG_RFKILL is not set
349# CONFIG_NET_9P is not set
350
351#
352# Device Drivers
353#
354
355#
356# Generic Driver Options
357#
358CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
359CONFIG_STANDALONE=y
360CONFIG_PREVENT_FIRMWARE_BUILD=y
361# CONFIG_FW_LOADER is not set
362# CONFIG_SYS_HYPERVISOR is not set
363# CONFIG_CONNECTOR is not set
364CONFIG_MTD=y
365# CONFIG_MTD_DEBUG is not set
366# CONFIG_MTD_CONCAT is not set
367CONFIG_MTD_PARTITIONS=y
368# CONFIG_MTD_REDBOOT_PARTS is not set
369CONFIG_MTD_CMDLINE_PARTS=y
370# CONFIG_MTD_AFS_PARTS is not set
371# CONFIG_MTD_AR7_PARTS is not set
372
373#
374# User Modules And Translation Layers
375#
376CONFIG_MTD_CHAR=y
377CONFIG_MTD_BLKDEVS=y
378CONFIG_MTD_BLOCK=y
379# CONFIG_FTL is not set
380# CONFIG_NFTL is not set
381# CONFIG_INFTL is not set
382# CONFIG_RFD_FTL is not set
383# CONFIG_SSFDC is not set
384# CONFIG_MTD_OOPS is not set
385
386#
387# RAM/ROM/Flash chip drivers
388#
389CONFIG_MTD_CFI=y
390# CONFIG_MTD_JEDECPROBE is not set
391CONFIG_MTD_GEN_PROBE=y
392CONFIG_MTD_CFI_ADV_OPTIONS=y
393CONFIG_MTD_CFI_NOSWAP=y
394# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
395# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
396CONFIG_MTD_CFI_GEOMETRY=y
397# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
398CONFIG_MTD_MAP_BANK_WIDTH_2=y
399# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
400# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
401# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
402# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
403CONFIG_MTD_CFI_I1=y
404# CONFIG_MTD_CFI_I2 is not set
405# CONFIG_MTD_CFI_I4 is not set
406# CONFIG_MTD_CFI_I8 is not set
407# CONFIG_MTD_OTP is not set
408CONFIG_MTD_CFI_INTELEXT=y
409# CONFIG_MTD_CFI_AMDSTD is not set
410# CONFIG_MTD_CFI_STAA is not set
411CONFIG_MTD_CFI_UTIL=y
412# CONFIG_MTD_RAM is not set
413# CONFIG_MTD_ROM is not set
414# CONFIG_MTD_ABSENT is not set
415# CONFIG_MTD_XIP is not set
416
417#
418# Mapping drivers for chip access
419#
420# CONFIG_MTD_COMPLEX_MAPPINGS is not set
421CONFIG_MTD_PHYSMAP=y
422CONFIG_MTD_PHYSMAP_START=0x00000000
423CONFIG_MTD_PHYSMAP_LEN=0x0
424CONFIG_MTD_PHYSMAP_BANKWIDTH=2
425# CONFIG_MTD_ARM_INTEGRATOR is not set
426# CONFIG_MTD_PLATRAM is not set
427
428#
429# Self-contained MTD device drivers
430#
431# CONFIG_MTD_SLRAM is not set
432# CONFIG_MTD_PHRAM is not set
433# CONFIG_MTD_MTDRAM is not set
434# CONFIG_MTD_BLOCK2MTD is not set
435
436#
437# Disk-On-Chip Device Drivers
438#
439# CONFIG_MTD_DOC2000 is not set
440# CONFIG_MTD_DOC2001 is not set
441# CONFIG_MTD_DOC2001PLUS is not set
442# CONFIG_MTD_NAND is not set
443# CONFIG_MTD_ONENAND is not set
444
445#
446# UBI - Unsorted block images
447#
448# CONFIG_MTD_UBI is not set
449# CONFIG_PARPORT is not set
450CONFIG_BLK_DEV=y
451# CONFIG_BLK_DEV_COW_COMMON is not set
452# CONFIG_BLK_DEV_LOOP is not set
453# CONFIG_BLK_DEV_NBD is not set
454# CONFIG_BLK_DEV_RAM is not set
455# CONFIG_CDROM_PKTCDVD is not set
456# CONFIG_ATA_OVER_ETH is not set
457# CONFIG_MISC_DEVICES is not set
458CONFIG_HAVE_IDE=y
459# CONFIG_IDE is not set
460
461#
462# SCSI device support
463#
464# CONFIG_RAID_ATTRS is not set
465# CONFIG_SCSI is not set
466# CONFIG_SCSI_DMA is not set
467# CONFIG_SCSI_NETLINK is not set
468# CONFIG_ATA is not set
469# CONFIG_MD is not set
470CONFIG_NETDEVICES=y
471# CONFIG_NETDEVICES_MULTIQUEUE is not set
472# CONFIG_DUMMY is not set
473# CONFIG_BONDING is not set
474# CONFIG_MACVLAN is not set
475# CONFIG_EQUALIZER is not set
476# CONFIG_TUN is not set
477# CONFIG_VETH is not set
478# CONFIG_PHYLIB is not set
479CONFIG_NET_ETHERNET=y
480# CONFIG_MII is not set
481# CONFIG_AX88796 is not set
482# CONFIG_SMC91X is not set
483# CONFIG_DM9000 is not set
484# CONFIG_IBM_NEW_EMAC_ZMII is not set
485# CONFIG_IBM_NEW_EMAC_RGMII is not set
486# CONFIG_IBM_NEW_EMAC_TAH is not set
487# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
488# CONFIG_B44 is not set
489# CONFIG_FEC_OLD is not set
490# CONFIG_NETDEV_1000 is not set
491# CONFIG_NETDEV_10000 is not set
492
493#
494# Wireless LAN
495#
496# CONFIG_WLAN_PRE80211 is not set
497# CONFIG_WLAN_80211 is not set
498# CONFIG_IWLWIFI_LEDS is not set
499# CONFIG_WAN is not set
500# CONFIG_PPP is not set
501# CONFIG_SLIP is not set
502# CONFIG_NETCONSOLE is not set
503# CONFIG_NETPOLL is not set
504# CONFIG_NET_POLL_CONTROLLER is not set
505# CONFIG_ISDN is not set
506
507#
508# Input device support
509#
510CONFIG_INPUT=y
511# CONFIG_INPUT_FF_MEMLESS is not set
512# CONFIG_INPUT_POLLDEV is not set
513
514#
515# Userland interfaces
516#
517# CONFIG_INPUT_MOUSEDEV is not set
518# CONFIG_INPUT_JOYDEV is not set
519CONFIG_INPUT_EVDEV=y
520# CONFIG_INPUT_EVBUG is not set
521
522#
523# Input Device Drivers
524#
525# CONFIG_INPUT_KEYBOARD is not set
526# CONFIG_INPUT_MOUSE is not set
527# CONFIG_INPUT_JOYSTICK is not set
528# CONFIG_INPUT_TABLET is not set
529CONFIG_INPUT_TOUCHSCREEN=y
530# CONFIG_TOUCHSCREEN_FUJITSU is not set
531# CONFIG_TOUCHSCREEN_GUNZE is not set
532# CONFIG_TOUCHSCREEN_ELO is not set
533# CONFIG_TOUCHSCREEN_MTOUCH is not set
534# CONFIG_TOUCHSCREEN_MK712 is not set
535# CONFIG_TOUCHSCREEN_PENMOUNT is not set
536# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
537# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
538# CONFIG_TOUCHSCREEN_UCB1400 is not set
539# CONFIG_INPUT_MISC is not set
540
541#
542# Hardware I/O ports
543#
544# CONFIG_SERIO is not set
545# CONFIG_GAMEPORT is not set
546
547#
548# Character devices
549#
550# CONFIG_VT is not set
551CONFIG_DEVKMEM=y
552# CONFIG_SERIAL_NONSTANDARD is not set
553
554#
555# Serial drivers
556#
557# CONFIG_SERIAL_8250 is not set
558
559#
560# Non-8250 serial port support
561#
562# CONFIG_SERIAL_IMX is not set
563CONFIG_UNIX98_PTYS=y
564# CONFIG_LEGACY_PTYS is not set
565# CONFIG_IPMI_HANDLER is not set
566# CONFIG_HW_RANDOM is not set
567# CONFIG_NVRAM is not set
568# CONFIG_R3964 is not set
569# CONFIG_RAW_DRIVER is not set
570# CONFIG_TCG_TPM is not set
571# CONFIG_I2C is not set
572# CONFIG_SPI is not set
573CONFIG_HAVE_GPIO_LIB=y
574
575#
576# GPIO Support
577#
578
579#
580# I2C GPIO expanders:
581#
582
583#
584# SPI GPIO expanders:
585#
586# CONFIG_W1 is not set
587# CONFIG_POWER_SUPPLY is not set
588# CONFIG_HWMON is not set
589# CONFIG_WATCHDOG is not set
590
591#
592# Sonics Silicon Backplane
593#
594CONFIG_SSB_POSSIBLE=y
595# CONFIG_SSB is not set
596
597#
598# Multifunction device drivers
599#
600# CONFIG_MFD_SM501 is not set
601# CONFIG_MFD_ASIC3 is not set
602# CONFIG_HTC_EGPIO is not set
603# CONFIG_HTC_PASIC3 is not set
604
605#
606# Multimedia devices
607#
608
609#
610# Multimedia core support
611#
612# CONFIG_VIDEO_DEV is not set
613# CONFIG_DVB_CORE is not set
614# CONFIG_VIDEO_MEDIA is not set
615
616#
617# Multimedia drivers
618#
619# CONFIG_DAB is not set
620
621#
622# Graphics support
623#
624# CONFIG_VGASTATE is not set
625# CONFIG_VIDEO_OUTPUT_CONTROL is not set
626# CONFIG_FB is not set
627# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
628
629#
630# Display device support
631#
632# CONFIG_DISPLAY_SUPPORT is not set
633
634#
635# Sound
636#
637# CONFIG_SOUND is not set
638# CONFIG_HID_SUPPORT is not set
639# CONFIG_USB_SUPPORT is not set
640# CONFIG_MMC is not set
641# CONFIG_NEW_LEDS is not set
642CONFIG_RTC_LIB=y
643# CONFIG_RTC_CLASS is not set
644# CONFIG_UIO is not set
645
646#
647# File systems
648#
649# CONFIG_EXT2_FS is not set
650# CONFIG_EXT3_FS is not set
651# CONFIG_EXT4DEV_FS is not set
652# CONFIG_REISERFS_FS is not set
653# CONFIG_JFS_FS is not set
654# CONFIG_FS_POSIX_ACL is not set
655# CONFIG_XFS_FS is not set
656# CONFIG_OCFS2_FS is not set
657# CONFIG_DNOTIFY is not set
658# CONFIG_INOTIFY is not set
659# CONFIG_QUOTA is not set
660# CONFIG_AUTOFS_FS is not set
661# CONFIG_AUTOFS4_FS is not set
662# CONFIG_FUSE_FS is not set
663
664#
665# CD-ROM/DVD Filesystems
666#
667# CONFIG_ISO9660_FS is not set
668# CONFIG_UDF_FS is not set
669
670#
671# DOS/FAT/NT Filesystems
672#
673# CONFIG_MSDOS_FS is not set
674# CONFIG_VFAT_FS is not set
675# CONFIG_NTFS_FS is not set
676
677#
678# Pseudo filesystems
679#
680CONFIG_PROC_FS=y
681CONFIG_PROC_SYSCTL=y
682CONFIG_SYSFS=y
683CONFIG_TMPFS=y
684# CONFIG_TMPFS_POSIX_ACL is not set
685# CONFIG_HUGETLB_PAGE is not set
686# CONFIG_CONFIGFS_FS is not set
687
688#
689# Miscellaneous filesystems
690#
691# CONFIG_ADFS_FS is not set
692# CONFIG_AFFS_FS is not set
693# CONFIG_HFS_FS is not set
694# CONFIG_HFSPLUS_FS is not set
695# CONFIG_BEFS_FS is not set
696# CONFIG_BFS_FS is not set
697# CONFIG_EFS_FS is not set
698CONFIG_JFFS2_FS=y
699CONFIG_JFFS2_FS_DEBUG=0
700CONFIG_JFFS2_FS_WRITEBUFFER=y
701# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
702# CONFIG_JFFS2_SUMMARY is not set
703# CONFIG_JFFS2_FS_XATTR is not set
704# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
705CONFIG_JFFS2_ZLIB=y
706# CONFIG_JFFS2_LZO is not set
707CONFIG_JFFS2_RTIME=y
708# CONFIG_JFFS2_RUBIN is not set
709# CONFIG_CRAMFS is not set
710# CONFIG_VXFS_FS is not set
711# CONFIG_MINIX_FS is not set
712# CONFIG_HPFS_FS is not set
713# CONFIG_QNX4FS_FS is not set
714# CONFIG_ROMFS_FS is not set
715# CONFIG_SYSV_FS is not set
716# CONFIG_UFS_FS is not set
717CONFIG_NETWORK_FILESYSTEMS=y
718CONFIG_NFS_FS=y
719CONFIG_NFS_V3=y
720# CONFIG_NFS_V3_ACL is not set
721# CONFIG_NFS_V4 is not set
722# CONFIG_NFSD is not set
723CONFIG_ROOT_NFS=y
724CONFIG_LOCKD=y
725CONFIG_LOCKD_V4=y
726CONFIG_NFS_COMMON=y
727CONFIG_SUNRPC=y
728# CONFIG_SUNRPC_BIND34 is not set
729# CONFIG_RPCSEC_GSS_KRB5 is not set
730# CONFIG_RPCSEC_GSS_SPKM3 is not set
731# CONFIG_SMB_FS is not set
732# CONFIG_CIFS is not set
733# CONFIG_NCP_FS is not set
734# CONFIG_CODA_FS is not set
735# CONFIG_AFS_FS is not set
736
737#
738# Partition Types
739#
740# CONFIG_PARTITION_ADVANCED is not set
741CONFIG_MSDOS_PARTITION=y
742CONFIG_NLS=y
743CONFIG_NLS_DEFAULT="iso8859-1"
744CONFIG_NLS_CODEPAGE_437=m
745# CONFIG_NLS_CODEPAGE_737 is not set
746# CONFIG_NLS_CODEPAGE_775 is not set
747CONFIG_NLS_CODEPAGE_850=m
748# CONFIG_NLS_CODEPAGE_852 is not set
749# CONFIG_NLS_CODEPAGE_855 is not set
750# CONFIG_NLS_CODEPAGE_857 is not set
751# CONFIG_NLS_CODEPAGE_860 is not set
752# CONFIG_NLS_CODEPAGE_861 is not set
753# CONFIG_NLS_CODEPAGE_862 is not set
754# CONFIG_NLS_CODEPAGE_863 is not set
755# CONFIG_NLS_CODEPAGE_864 is not set
756# CONFIG_NLS_CODEPAGE_865 is not set
757# CONFIG_NLS_CODEPAGE_866 is not set
758# CONFIG_NLS_CODEPAGE_869 is not set
759# CONFIG_NLS_CODEPAGE_936 is not set
760# CONFIG_NLS_CODEPAGE_950 is not set
761# CONFIG_NLS_CODEPAGE_932 is not set
762# CONFIG_NLS_CODEPAGE_949 is not set
763# CONFIG_NLS_CODEPAGE_874 is not set
764# CONFIG_NLS_ISO8859_8 is not set
765# CONFIG_NLS_CODEPAGE_1250 is not set
766# CONFIG_NLS_CODEPAGE_1251 is not set
767# CONFIG_NLS_ASCII is not set
768CONFIG_NLS_ISO8859_1=y
769# CONFIG_NLS_ISO8859_2 is not set
770# CONFIG_NLS_ISO8859_3 is not set
771# CONFIG_NLS_ISO8859_4 is not set
772# CONFIG_NLS_ISO8859_5 is not set
773# CONFIG_NLS_ISO8859_6 is not set
774# CONFIG_NLS_ISO8859_7 is not set
775# CONFIG_NLS_ISO8859_9 is not set
776# CONFIG_NLS_ISO8859_13 is not set
777# CONFIG_NLS_ISO8859_14 is not set
778CONFIG_NLS_ISO8859_15=m
779# CONFIG_NLS_KOI8_R is not set
780# CONFIG_NLS_KOI8_U is not set
781# CONFIG_NLS_UTF8 is not set
782# CONFIG_DLM is not set
783
784#
785# Kernel hacking
786#
787# CONFIG_PRINTK_TIME is not set
788CONFIG_ENABLE_WARN_DEPRECATED=y
789CONFIG_ENABLE_MUST_CHECK=y
790CONFIG_FRAME_WARN=1024
791# CONFIG_MAGIC_SYSRQ is not set
792# CONFIG_UNUSED_SYMBOLS is not set
793# CONFIG_DEBUG_FS is not set
794# CONFIG_HEADERS_CHECK is not set
795# CONFIG_DEBUG_KERNEL is not set
796# CONFIG_DEBUG_BUGVERBOSE is not set
797CONFIG_FRAME_POINTER=y
798# CONFIG_SAMPLES is not set
799# CONFIG_DEBUG_USER is not set
800
801#
802# Security options
803#
804# CONFIG_KEYS is not set
805# CONFIG_SECURITY is not set
806# CONFIG_SECURITY_FILE_CAPABILITIES is not set
807# CONFIG_CRYPTO is not set
808
809#
810# Library routines
811#
812CONFIG_BITREVERSE=y
813# CONFIG_GENERIC_FIND_FIRST_BIT is not set
814# CONFIG_GENERIC_FIND_NEXT_BIT is not set
815# CONFIG_CRC_CCITT is not set
816# CONFIG_CRC16 is not set
817# CONFIG_CRC_ITU_T is not set
818CONFIG_CRC32=y
819# CONFIG_CRC7 is not set
820# CONFIG_LIBCRC32C is not set
821CONFIG_ZLIB_INFLATE=y
822CONFIG_ZLIB_DEFLATE=y
823CONFIG_PLIST=y
824CONFIG_HAS_IOMEM=y
825CONFIG_HAS_IOPORT=y
826CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/mx31ads_defconfig b/arch/arm/configs/mx31ads_defconfig
new file mode 100644
index 000000000000..e05271753e15
--- /dev/null
+++ b/arch/arm/configs/mx31ads_defconfig
@@ -0,0 +1,839 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc6
4# Fri Jun 20 16:21:11 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ARCH_SUPPORTS_AOUT=y
25CONFIG_ZONE_DMA=y
26CONFIG_ARCH_MTD_XIP=y
27CONFIG_VECTORS_BASE=0xffff0000
28CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
29
30#
31# General setup
32#
33CONFIG_EXPERIMENTAL=y
34CONFIG_BROKEN_ON_SMP=y
35CONFIG_LOCK_KERNEL=y
36CONFIG_INIT_ENV_ARG_LIMIT=32
37CONFIG_LOCALVERSION=""
38CONFIG_LOCALVERSION_AUTO=y
39CONFIG_SWAP=y
40CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set
43# CONFIG_BSD_PROCESS_ACCT is not set
44# CONFIG_TASKSTATS is not set
45# CONFIG_AUDIT is not set
46CONFIG_IKCONFIG=y
47CONFIG_IKCONFIG_PROC=y
48CONFIG_LOG_BUF_SHIFT=14
49# CONFIG_CGROUPS is not set
50CONFIG_GROUP_SCHED=y
51CONFIG_FAIR_GROUP_SCHED=y
52# CONFIG_RT_GROUP_SCHED is not set
53CONFIG_USER_SCHED=y
54# CONFIG_CGROUP_SCHED is not set
55CONFIG_SYSFS_DEPRECATED=y
56CONFIG_SYSFS_DEPRECATED_V2=y
57# CONFIG_RELAY is not set
58# CONFIG_NAMESPACES is not set
59# CONFIG_BLK_DEV_INITRD is not set
60CONFIG_CC_OPTIMIZE_FOR_SIZE=y
61CONFIG_SYSCTL=y
62CONFIG_EMBEDDED=y
63CONFIG_UID16=y
64CONFIG_SYSCTL_SYSCALL=y
65CONFIG_SYSCTL_SYSCALL_CHECK=y
66CONFIG_KALLSYMS=y
67# CONFIG_KALLSYMS_EXTRA_PASS is not set
68CONFIG_HOTPLUG=y
69CONFIG_PRINTK=y
70CONFIG_BUG=y
71CONFIG_ELF_CORE=y
72CONFIG_COMPAT_BRK=y
73CONFIG_BASE_FULL=y
74CONFIG_FUTEX=y
75CONFIG_ANON_INODES=y
76CONFIG_EPOLL=y
77CONFIG_SIGNALFD=y
78CONFIG_TIMERFD=y
79CONFIG_EVENTFD=y
80CONFIG_SHMEM=y
81CONFIG_VM_EVENT_COUNTERS=y
82CONFIG_SLAB=y
83# CONFIG_SLUB is not set
84# CONFIG_SLOB is not set
85# CONFIG_PROFILING is not set
86# CONFIG_MARKERS is not set
87CONFIG_HAVE_OPROFILE=y
88# CONFIG_KPROBES is not set
89CONFIG_HAVE_KPROBES=y
90CONFIG_HAVE_KRETPROBES=y
91# CONFIG_HAVE_DMA_ATTRS is not set
92CONFIG_PROC_PAGE_MONITOR=y
93CONFIG_SLABINFO=y
94CONFIG_RT_MUTEXES=y
95# CONFIG_TINY_SHMEM is not set
96CONFIG_BASE_SMALL=0
97CONFIG_MODULES=y
98# CONFIG_MODULE_FORCE_LOAD is not set
99CONFIG_MODULE_UNLOAD=y
100CONFIG_MODULE_FORCE_UNLOAD=y
101CONFIG_MODVERSIONS=y
102# CONFIG_MODULE_SRCVERSION_ALL is not set
103CONFIG_KMOD=y
104CONFIG_BLOCK=y
105# CONFIG_LBD is not set
106# CONFIG_BLK_DEV_IO_TRACE is not set
107# CONFIG_LSF is not set
108# CONFIG_BLK_DEV_BSG is not set
109
110#
111# IO Schedulers
112#
113CONFIG_IOSCHED_NOOP=y
114CONFIG_IOSCHED_AS=y
115CONFIG_IOSCHED_DEADLINE=y
116CONFIG_IOSCHED_CFQ=y
117# CONFIG_DEFAULT_AS is not set
118# CONFIG_DEFAULT_DEADLINE is not set
119CONFIG_DEFAULT_CFQ=y
120# CONFIG_DEFAULT_NOOP is not set
121CONFIG_DEFAULT_IOSCHED="cfq"
122CONFIG_CLASSIC_RCU=y
123
124#
125# System Type
126#
127# CONFIG_ARCH_AAEC2000 is not set
128# CONFIG_ARCH_INTEGRATOR is not set
129# CONFIG_ARCH_REALVIEW is not set
130# CONFIG_ARCH_VERSATILE is not set
131# CONFIG_ARCH_AT91 is not set
132# CONFIG_ARCH_CLPS7500 is not set
133# CONFIG_ARCH_CLPS711X is not set
134# CONFIG_ARCH_CO285 is not set
135# CONFIG_ARCH_EBSA110 is not set
136# CONFIG_ARCH_EP93XX is not set
137# CONFIG_ARCH_FOOTBRIDGE is not set
138# CONFIG_ARCH_NETX is not set
139# CONFIG_ARCH_H720X is not set
140# CONFIG_ARCH_IMX is not set
141# CONFIG_ARCH_IOP13XX is not set
142# CONFIG_ARCH_IOP32X is not set
143# CONFIG_ARCH_IOP33X is not set
144# CONFIG_ARCH_IXP23XX is not set
145# CONFIG_ARCH_IXP2000 is not set
146# CONFIG_ARCH_IXP4XX is not set
147# CONFIG_ARCH_L7200 is not set
148# CONFIG_ARCH_KS8695 is not set
149# CONFIG_ARCH_NS9XXX is not set
150CONFIG_ARCH_MXC=y
151# CONFIG_ARCH_ORION5X is not set
152# CONFIG_ARCH_PNX4008 is not set
153# CONFIG_ARCH_PXA is not set
154# CONFIG_ARCH_RPC is not set
155# CONFIG_ARCH_SA1100 is not set
156# CONFIG_ARCH_S3C2410 is not set
157# CONFIG_ARCH_SHARK is not set
158# CONFIG_ARCH_LH7A40X is not set
159# CONFIG_ARCH_DAVINCI is not set
160# CONFIG_ARCH_OMAP is not set
161# CONFIG_ARCH_MSM7X00A is not set
162
163#
164# Boot options
165#
166
167#
168# Power management
169#
170
171#
172# Freescale MXC Implementations
173#
174# CONFIG_ARCH_MX2 is not set
175CONFIG_ARCH_MX3=y
176
177#
178# MX3 Options
179#
180CONFIG_MACH_MX31ADS=y
181# CONFIG_MACH_PCM037 is not set
182
183#
184# Processor Type
185#
186CONFIG_CPU_32=y
187CONFIG_CPU_V6=y
188# CONFIG_CPU_32v6K is not set
189CONFIG_CPU_32v6=y
190CONFIG_CPU_ABRT_EV6=y
191CONFIG_CPU_PABRT_NOIFAR=y
192CONFIG_CPU_CACHE_V6=y
193CONFIG_CPU_CACHE_VIPT=y
194CONFIG_CPU_COPY_V6=y
195CONFIG_CPU_TLB_V6=y
196CONFIG_CPU_HAS_ASID=y
197CONFIG_CPU_CP15=y
198CONFIG_CPU_CP15_MMU=y
199
200#
201# Processor Features
202#
203CONFIG_ARM_THUMB=y
204# CONFIG_CPU_ICACHE_DISABLE is not set
205# CONFIG_CPU_DCACHE_DISABLE is not set
206# CONFIG_CPU_BPREDICT_DISABLE is not set
207# CONFIG_OUTER_CACHE is not set
208
209#
210# Bus support
211#
212# CONFIG_PCI_SYSCALL is not set
213# CONFIG_ARCH_SUPPORTS_MSI is not set
214# CONFIG_PCCARD is not set
215
216#
217# Kernel Features
218#
219CONFIG_TICK_ONESHOT=y
220CONFIG_NO_HZ=y
221CONFIG_HIGH_RES_TIMERS=y
222CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
223CONFIG_PREEMPT=y
224CONFIG_HZ=100
225CONFIG_AEABI=y
226# CONFIG_OABI_COMPAT is not set
227# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
228CONFIG_SELECT_MEMORY_MODEL=y
229CONFIG_FLATMEM_MANUAL=y
230# CONFIG_DISCONTIGMEM_MANUAL is not set
231# CONFIG_SPARSEMEM_MANUAL is not set
232CONFIG_FLATMEM=y
233CONFIG_FLAT_NODE_MEM_MAP=y
234# CONFIG_SPARSEMEM_STATIC is not set
235# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
236CONFIG_PAGEFLAGS_EXTENDED=y
237CONFIG_SPLIT_PTLOCK_CPUS=4
238# CONFIG_RESOURCES_64BIT is not set
239CONFIG_ZONE_DMA_FLAG=1
240CONFIG_BOUNCE=y
241CONFIG_VIRT_TO_BUS=y
242CONFIG_ALIGNMENT_TRAP=y
243
244#
245# Boot options
246#
247CONFIG_ZBOOT_ROM_TEXT=0x0
248CONFIG_ZBOOT_ROM_BSS=0x0
249CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off"
250# CONFIG_XIP_KERNEL is not set
251# CONFIG_KEXEC is not set
252
253#
254# Floating point emulation
255#
256
257#
258# At least one emulation must be selected
259#
260CONFIG_VFP=y
261
262#
263# Userspace binary formats
264#
265CONFIG_BINFMT_ELF=y
266# CONFIG_BINFMT_AOUT is not set
267# CONFIG_BINFMT_MISC is not set
268
269#
270# Power management options
271#
272# CONFIG_PM is not set
273CONFIG_ARCH_SUSPEND_POSSIBLE=y
274
275#
276# Networking
277#
278CONFIG_NET=y
279
280#
281# Networking options
282#
283CONFIG_PACKET=y
284# CONFIG_PACKET_MMAP is not set
285CONFIG_UNIX=y
286CONFIG_XFRM=y
287# CONFIG_XFRM_USER is not set
288# CONFIG_XFRM_SUB_POLICY is not set
289# CONFIG_XFRM_MIGRATE is not set
290# CONFIG_XFRM_STATISTICS is not set
291# CONFIG_NET_KEY is not set
292CONFIG_INET=y
293# CONFIG_IP_MULTICAST is not set
294# CONFIG_IP_ADVANCED_ROUTER is not set
295CONFIG_IP_FIB_HASH=y
296CONFIG_IP_PNP=y
297CONFIG_IP_PNP_DHCP=y
298# CONFIG_IP_PNP_BOOTP is not set
299# CONFIG_IP_PNP_RARP is not set
300# CONFIG_NET_IPIP is not set
301# CONFIG_NET_IPGRE is not set
302# CONFIG_ARPD is not set
303# CONFIG_SYN_COOKIES is not set
304# CONFIG_INET_AH is not set
305# CONFIG_INET_ESP is not set
306# CONFIG_INET_IPCOMP is not set
307# CONFIG_INET_XFRM_TUNNEL is not set
308# CONFIG_INET_TUNNEL is not set
309CONFIG_INET_XFRM_MODE_TRANSPORT=y
310CONFIG_INET_XFRM_MODE_TUNNEL=y
311CONFIG_INET_XFRM_MODE_BEET=y
312# CONFIG_INET_LRO is not set
313CONFIG_INET_DIAG=y
314CONFIG_INET_TCP_DIAG=y
315# CONFIG_TCP_CONG_ADVANCED is not set
316CONFIG_TCP_CONG_CUBIC=y
317CONFIG_DEFAULT_TCP_CONG="cubic"
318# CONFIG_TCP_MD5SIG is not set
319# CONFIG_IPV6 is not set
320# CONFIG_NETWORK_SECMARK is not set
321# CONFIG_NETFILTER is not set
322# CONFIG_IP_DCCP is not set
323# CONFIG_IP_SCTP is not set
324# CONFIG_TIPC is not set
325# CONFIG_ATM is not set
326# CONFIG_BRIDGE is not set
327# CONFIG_VLAN_8021Q is not set
328# CONFIG_DECNET is not set
329# CONFIG_LLC2 is not set
330# CONFIG_IPX is not set
331# CONFIG_ATALK is not set
332# CONFIG_X25 is not set
333# CONFIG_LAPB is not set
334# CONFIG_ECONET is not set
335# CONFIG_WAN_ROUTER is not set
336# CONFIG_NET_SCHED is not set
337
338#
339# Network testing
340#
341# CONFIG_NET_PKTGEN is not set
342# CONFIG_HAMRADIO is not set
343# CONFIG_CAN is not set
344# CONFIG_IRDA is not set
345# CONFIG_BT is not set
346# CONFIG_AF_RXRPC is not set
347
348#
349# Wireless
350#
351# CONFIG_CFG80211 is not set
352# CONFIG_WIRELESS_EXT is not set
353# CONFIG_MAC80211 is not set
354# CONFIG_IEEE80211 is not set
355# CONFIG_RFKILL is not set
356# CONFIG_NET_9P is not set
357
358#
359# Device Drivers
360#
361
362#
363# Generic Driver Options
364#
365CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
366CONFIG_STANDALONE=y
367CONFIG_PREVENT_FIRMWARE_BUILD=y
368CONFIG_FW_LOADER=m
369# CONFIG_SYS_HYPERVISOR is not set
370# CONFIG_CONNECTOR is not set
371CONFIG_MTD=y
372# CONFIG_MTD_DEBUG is not set
373# CONFIG_MTD_CONCAT is not set
374CONFIG_MTD_PARTITIONS=y
375CONFIG_MTD_REDBOOT_PARTS=y
376CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
377# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
378# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
379CONFIG_MTD_CMDLINE_PARTS=y
380# CONFIG_MTD_AFS_PARTS is not set
381# CONFIG_MTD_AR7_PARTS is not set
382
383#
384# User Modules And Translation Layers
385#
386CONFIG_MTD_CHAR=y
387CONFIG_MTD_BLKDEVS=y
388CONFIG_MTD_BLOCK=y
389# CONFIG_FTL is not set
390# CONFIG_NFTL is not set
391# CONFIG_INFTL is not set
392# CONFIG_RFD_FTL is not set
393# CONFIG_SSFDC is not set
394# CONFIG_MTD_OOPS is not set
395
396#
397# RAM/ROM/Flash chip drivers
398#
399CONFIG_MTD_CFI=y
400# CONFIG_MTD_JEDECPROBE is not set
401CONFIG_MTD_GEN_PROBE=y
402CONFIG_MTD_CFI_ADV_OPTIONS=y
403CONFIG_MTD_CFI_NOSWAP=y
404# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
405# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
406CONFIG_MTD_CFI_GEOMETRY=y
407# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
408CONFIG_MTD_MAP_BANK_WIDTH_2=y
409# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
410# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
411# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
412# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
413CONFIG_MTD_CFI_I1=y
414# CONFIG_MTD_CFI_I2 is not set
415# CONFIG_MTD_CFI_I4 is not set
416# CONFIG_MTD_CFI_I8 is not set
417# CONFIG_MTD_OTP is not set
418# CONFIG_MTD_CFI_INTELEXT is not set
419CONFIG_MTD_CFI_AMDSTD=y
420# CONFIG_MTD_CFI_STAA is not set
421CONFIG_MTD_CFI_UTIL=y
422CONFIG_MTD_RAM=y
423# CONFIG_MTD_ROM is not set
424# CONFIG_MTD_ABSENT is not set
425# CONFIG_MTD_XIP is not set
426
427#
428# Mapping drivers for chip access
429#
430# CONFIG_MTD_COMPLEX_MAPPINGS is not set
431# CONFIG_MTD_PHYSMAP is not set
432# CONFIG_MTD_ARM_INTEGRATOR is not set
433# CONFIG_MTD_PLATRAM is not set
434
435#
436# Self-contained MTD device drivers
437#
438# CONFIG_MTD_SLRAM is not set
439# CONFIG_MTD_PHRAM is not set
440# CONFIG_MTD_MTDRAM is not set
441# CONFIG_MTD_BLOCK2MTD is not set
442
443#
444# Disk-On-Chip Device Drivers
445#
446# CONFIG_MTD_DOC2000 is not set
447# CONFIG_MTD_DOC2001 is not set
448# CONFIG_MTD_DOC2001PLUS is not set
449CONFIG_MTD_NAND=y
450# CONFIG_MTD_NAND_VERIFY_WRITE is not set
451# CONFIG_MTD_NAND_ECC_SMC is not set
452# CONFIG_MTD_NAND_MUSEUM_IDS is not set
453CONFIG_MTD_NAND_IDS=y
454# CONFIG_MTD_NAND_DISKONCHIP is not set
455# CONFIG_MTD_NAND_NANDSIM is not set
456# CONFIG_MTD_NAND_PLATFORM is not set
457# CONFIG_MTD_ONENAND is not set
458
459#
460# UBI - Unsorted block images
461#
462# CONFIG_MTD_UBI is not set
463# CONFIG_PARPORT is not set
464# CONFIG_BLK_DEV is not set
465# CONFIG_MISC_DEVICES is not set
466CONFIG_HAVE_IDE=y
467# CONFIG_IDE is not set
468
469#
470# SCSI device support
471#
472# CONFIG_RAID_ATTRS is not set
473# CONFIG_SCSI is not set
474# CONFIG_SCSI_DMA is not set
475# CONFIG_SCSI_NETLINK is not set
476# CONFIG_ATA is not set
477# CONFIG_MD is not set
478CONFIG_NETDEVICES=y
479# CONFIG_NETDEVICES_MULTIQUEUE is not set
480# CONFIG_DUMMY is not set
481# CONFIG_BONDING is not set
482# CONFIG_MACVLAN is not set
483# CONFIG_EQUALIZER is not set
484# CONFIG_TUN is not set
485# CONFIG_VETH is not set
486# CONFIG_PHYLIB is not set
487CONFIG_NET_ETHERNET=y
488CONFIG_MII=y
489# CONFIG_AX88796 is not set
490# CONFIG_SMC91X is not set
491# CONFIG_DM9000 is not set
492# CONFIG_IBM_NEW_EMAC_ZMII is not set
493# CONFIG_IBM_NEW_EMAC_RGMII is not set
494# CONFIG_IBM_NEW_EMAC_TAH is not set
495# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
496# CONFIG_B44 is not set
497# CONFIG_NETDEV_1000 is not set
498# CONFIG_NETDEV_10000 is not set
499
500#
501# Wireless LAN
502#
503# CONFIG_WLAN_PRE80211 is not set
504# CONFIG_WLAN_80211 is not set
505# CONFIG_IWLWIFI_LEDS is not set
506# CONFIG_WAN is not set
507# CONFIG_PPP is not set
508# CONFIG_SLIP is not set
509# CONFIG_NETCONSOLE is not set
510# CONFIG_NETPOLL is not set
511# CONFIG_NET_POLL_CONTROLLER is not set
512# CONFIG_ISDN is not set
513
514#
515# Input device support
516#
517# CONFIG_INPUT is not set
518
519#
520# Hardware I/O ports
521#
522# CONFIG_SERIO is not set
523# CONFIG_GAMEPORT is not set
524
525#
526# Character devices
527#
528# CONFIG_VT is not set
529CONFIG_DEVKMEM=y
530# CONFIG_SERIAL_NONSTANDARD is not set
531
532#
533# Serial drivers
534#
535# CONFIG_SERIAL_8250 is not set
536
537#
538# Non-8250 serial port support
539#
540CONFIG_SERIAL_IMX=y
541CONFIG_SERIAL_IMX_CONSOLE=y
542CONFIG_SERIAL_CORE=y
543CONFIG_SERIAL_CORE_CONSOLE=y
544CONFIG_UNIX98_PTYS=y
545# CONFIG_LEGACY_PTYS is not set
546# CONFIG_IPMI_HANDLER is not set
547# CONFIG_HW_RANDOM is not set
548# CONFIG_NVRAM is not set
549# CONFIG_R3964 is not set
550# CONFIG_RAW_DRIVER is not set
551# CONFIG_TCG_TPM is not set
552# CONFIG_I2C is not set
553# CONFIG_SPI is not set
554CONFIG_HAVE_GPIO_LIB=y
555
556#
557# GPIO Support
558#
559
560#
561# I2C GPIO expanders:
562#
563
564#
565# SPI GPIO expanders:
566#
567# CONFIG_W1 is not set
568# CONFIG_POWER_SUPPLY is not set
569# CONFIG_HWMON is not set
570# CONFIG_WATCHDOG is not set
571
572#
573# Sonics Silicon Backplane
574#
575CONFIG_SSB_POSSIBLE=y
576# CONFIG_SSB is not set
577
578#
579# Multifunction device drivers
580#
581# CONFIG_MFD_SM501 is not set
582# CONFIG_MFD_ASIC3 is not set
583# CONFIG_HTC_EGPIO is not set
584# CONFIG_HTC_PASIC3 is not set
585
586#
587# Multimedia devices
588#
589
590#
591# Multimedia core support
592#
593# CONFIG_VIDEO_DEV is not set
594# CONFIG_DVB_CORE is not set
595# CONFIG_VIDEO_MEDIA is not set
596
597#
598# Multimedia drivers
599#
600# CONFIG_DAB is not set
601
602#
603# Graphics support
604#
605# CONFIG_VGASTATE is not set
606# CONFIG_VIDEO_OUTPUT_CONTROL is not set
607# CONFIG_FB is not set
608# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
609
610#
611# Display device support
612#
613# CONFIG_DISPLAY_SUPPORT is not set
614
615#
616# Sound
617#
618# CONFIG_SOUND is not set
619# CONFIG_USB_SUPPORT is not set
620# CONFIG_MMC is not set
621# CONFIG_NEW_LEDS is not set
622CONFIG_RTC_LIB=y
623# CONFIG_RTC_CLASS is not set
624# CONFIG_UIO is not set
625
626#
627# File systems
628#
629# CONFIG_EXT2_FS is not set
630# CONFIG_EXT3_FS is not set
631# CONFIG_EXT4DEV_FS is not set
632# CONFIG_REISERFS_FS is not set
633# CONFIG_JFS_FS is not set
634# CONFIG_FS_POSIX_ACL is not set
635# CONFIG_XFS_FS is not set
636# CONFIG_OCFS2_FS is not set
637# CONFIG_DNOTIFY is not set
638CONFIG_INOTIFY=y
639CONFIG_INOTIFY_USER=y
640# CONFIG_QUOTA is not set
641# CONFIG_AUTOFS_FS is not set
642# CONFIG_AUTOFS4_FS is not set
643# CONFIG_FUSE_FS is not set
644
645#
646# CD-ROM/DVD Filesystems
647#
648# CONFIG_ISO9660_FS is not set
649# CONFIG_UDF_FS is not set
650
651#
652# DOS/FAT/NT Filesystems
653#
654# CONFIG_MSDOS_FS is not set
655# CONFIG_VFAT_FS is not set
656# CONFIG_NTFS_FS is not set
657
658#
659# Pseudo filesystems
660#
661CONFIG_PROC_FS=y
662CONFIG_PROC_SYSCTL=y
663CONFIG_SYSFS=y
664CONFIG_TMPFS=y
665# CONFIG_TMPFS_POSIX_ACL is not set
666# CONFIG_HUGETLB_PAGE is not set
667# CONFIG_CONFIGFS_FS is not set
668
669#
670# Miscellaneous filesystems
671#
672# CONFIG_ADFS_FS is not set
673# CONFIG_AFFS_FS is not set
674# CONFIG_HFS_FS is not set
675# CONFIG_HFSPLUS_FS is not set
676# CONFIG_BEFS_FS is not set
677# CONFIG_BFS_FS is not set
678# CONFIG_EFS_FS is not set
679CONFIG_JFFS2_FS=y
680CONFIG_JFFS2_FS_DEBUG=0
681CONFIG_JFFS2_FS_WRITEBUFFER=y
682# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
683# CONFIG_JFFS2_SUMMARY is not set
684# CONFIG_JFFS2_FS_XATTR is not set
685# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
686CONFIG_JFFS2_ZLIB=y
687# CONFIG_JFFS2_LZO is not set
688CONFIG_JFFS2_RTIME=y
689# CONFIG_JFFS2_RUBIN is not set
690CONFIG_CRAMFS=y
691# CONFIG_VXFS_FS is not set
692# CONFIG_MINIX_FS is not set
693# CONFIG_HPFS_FS is not set
694# CONFIG_QNX4FS_FS is not set
695# CONFIG_ROMFS_FS is not set
696# CONFIG_SYSV_FS is not set
697# CONFIG_UFS_FS is not set
698CONFIG_NETWORK_FILESYSTEMS=y
699CONFIG_NFS_FS=y
700# CONFIG_NFS_V3 is not set
701# CONFIG_NFS_V4 is not set
702# CONFIG_NFSD is not set
703CONFIG_ROOT_NFS=y
704CONFIG_LOCKD=y
705CONFIG_NFS_COMMON=y
706CONFIG_SUNRPC=y
707# CONFIG_SUNRPC_BIND34 is not set
708# CONFIG_RPCSEC_GSS_KRB5 is not set
709# CONFIG_RPCSEC_GSS_SPKM3 is not set
710# CONFIG_SMB_FS is not set
711# CONFIG_CIFS is not set
712# CONFIG_NCP_FS is not set
713# CONFIG_CODA_FS is not set
714# CONFIG_AFS_FS is not set
715
716#
717# Partition Types
718#
719# CONFIG_PARTITION_ADVANCED is not set
720CONFIG_MSDOS_PARTITION=y
721# CONFIG_NLS is not set
722# CONFIG_DLM is not set
723
724#
725# Kernel hacking
726#
727CONFIG_PRINTK_TIME=y
728CONFIG_ENABLE_WARN_DEPRECATED=y
729CONFIG_ENABLE_MUST_CHECK=y
730CONFIG_FRAME_WARN=1024
731# CONFIG_MAGIC_SYSRQ is not set
732# CONFIG_UNUSED_SYMBOLS is not set
733# CONFIG_DEBUG_FS is not set
734# CONFIG_HEADERS_CHECK is not set
735# CONFIG_DEBUG_KERNEL is not set
736# CONFIG_DEBUG_BUGVERBOSE is not set
737CONFIG_FRAME_POINTER=y
738# CONFIG_SAMPLES is not set
739# CONFIG_DEBUG_USER is not set
740
741#
742# Security options
743#
744# CONFIG_KEYS is not set
745# CONFIG_SECURITY is not set
746# CONFIG_SECURITY_FILE_CAPABILITIES is not set
747CONFIG_CRYPTO=y
748
749#
750# Crypto core or helper
751#
752# CONFIG_CRYPTO_MANAGER is not set
753# CONFIG_CRYPTO_GF128MUL is not set
754# CONFIG_CRYPTO_NULL is not set
755# CONFIG_CRYPTO_CRYPTD is not set
756# CONFIG_CRYPTO_AUTHENC is not set
757# CONFIG_CRYPTO_TEST is not set
758
759#
760# Authenticated Encryption with Associated Data
761#
762# CONFIG_CRYPTO_CCM is not set
763# CONFIG_CRYPTO_GCM is not set
764# CONFIG_CRYPTO_SEQIV is not set
765
766#
767# Block modes
768#
769# CONFIG_CRYPTO_CBC is not set
770# CONFIG_CRYPTO_CTR is not set
771# CONFIG_CRYPTO_CTS is not set
772# CONFIG_CRYPTO_ECB is not set
773# CONFIG_CRYPTO_LRW is not set
774# CONFIG_CRYPTO_PCBC is not set
775# CONFIG_CRYPTO_XTS is not set
776
777#
778# Hash modes
779#
780# CONFIG_CRYPTO_HMAC is not set
781# CONFIG_CRYPTO_XCBC is not set
782
783#
784# Digest
785#
786# CONFIG_CRYPTO_CRC32C is not set
787# CONFIG_CRYPTO_MD4 is not set
788# CONFIG_CRYPTO_MD5 is not set
789# CONFIG_CRYPTO_MICHAEL_MIC is not set
790# CONFIG_CRYPTO_SHA1 is not set
791# CONFIG_CRYPTO_SHA256 is not set
792# CONFIG_CRYPTO_SHA512 is not set
793# CONFIG_CRYPTO_TGR192 is not set
794# CONFIG_CRYPTO_WP512 is not set
795
796#
797# Ciphers
798#
799# CONFIG_CRYPTO_AES is not set
800# CONFIG_CRYPTO_ANUBIS is not set
801# CONFIG_CRYPTO_ARC4 is not set
802# CONFIG_CRYPTO_BLOWFISH is not set
803# CONFIG_CRYPTO_CAMELLIA is not set
804# CONFIG_CRYPTO_CAST5 is not set
805# CONFIG_CRYPTO_CAST6 is not set
806# CONFIG_CRYPTO_DES is not set
807# CONFIG_CRYPTO_FCRYPT is not set
808# CONFIG_CRYPTO_KHAZAD is not set
809# CONFIG_CRYPTO_SALSA20 is not set
810# CONFIG_CRYPTO_SEED is not set
811# CONFIG_CRYPTO_SERPENT is not set
812# CONFIG_CRYPTO_TEA is not set
813# CONFIG_CRYPTO_TWOFISH is not set
814
815#
816# Compression
817#
818# CONFIG_CRYPTO_DEFLATE is not set
819# CONFIG_CRYPTO_LZO is not set
820# CONFIG_CRYPTO_HW is not set
821
822#
823# Library routines
824#
825CONFIG_BITREVERSE=y
826# CONFIG_GENERIC_FIND_FIRST_BIT is not set
827# CONFIG_GENERIC_FIND_NEXT_BIT is not set
828# CONFIG_CRC_CCITT is not set
829# CONFIG_CRC16 is not set
830# CONFIG_CRC_ITU_T is not set
831CONFIG_CRC32=y
832# CONFIG_CRC7 is not set
833# CONFIG_LIBCRC32C is not set
834CONFIG_ZLIB_INFLATE=y
835CONFIG_ZLIB_DEFLATE=y
836CONFIG_PLIST=y
837CONFIG_HAS_IOMEM=y
838CONFIG_HAS_IOPORT=y
839CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/mx31litekit_defconfig b/arch/arm/configs/mx31litekit_defconfig
new file mode 100644
index 000000000000..4f41c4135685
--- /dev/null
+++ b/arch/arm/configs/mx31litekit_defconfig
@@ -0,0 +1,1100 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5
4# Fri Jun 13 14:23:39 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8# CONFIG_GENERIC_GPIO is not set
9# CONFIG_GENERIC_TIME is not set
10# CONFIG_GENERIC_CLOCKEVENTS is not set
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ARCH_SUPPORTS_AOUT=y
25CONFIG_ZONE_DMA=y
26CONFIG_ARCH_MTD_XIP=y
27CONFIG_VECTORS_BASE=0xffff0000
28CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
29
30#
31# General setup
32#
33CONFIG_EXPERIMENTAL=y
34CONFIG_BROKEN_ON_SMP=y
35CONFIG_LOCK_KERNEL=y
36CONFIG_INIT_ENV_ARG_LIMIT=32
37CONFIG_LOCALVERSION=""
38CONFIG_LOCALVERSION_AUTO=y
39CONFIG_SWAP=y
40CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set
43# CONFIG_BSD_PROCESS_ACCT is not set
44# CONFIG_TASKSTATS is not set
45# CONFIG_AUDIT is not set
46CONFIG_IKCONFIG=y
47CONFIG_IKCONFIG_PROC=y
48CONFIG_LOG_BUF_SHIFT=14
49# CONFIG_CGROUPS is not set
50# CONFIG_GROUP_SCHED is not set
51CONFIG_SYSFS_DEPRECATED=y
52CONFIG_SYSFS_DEPRECATED_V2=y
53# CONFIG_RELAY is not set
54# CONFIG_NAMESPACES is not set
55# CONFIG_BLK_DEV_INITRD is not set
56CONFIG_CC_OPTIMIZE_FOR_SIZE=y
57CONFIG_SYSCTL=y
58CONFIG_EMBEDDED=y
59CONFIG_UID16=y
60CONFIG_SYSCTL_SYSCALL=y
61CONFIG_SYSCTL_SYSCALL_CHECK=y
62CONFIG_KALLSYMS=y
63# CONFIG_KALLSYMS_ALL is not set
64# CONFIG_KALLSYMS_EXTRA_PASS is not set
65CONFIG_HOTPLUG=y
66CONFIG_PRINTK=y
67CONFIG_BUG=y
68CONFIG_ELF_CORE=y
69CONFIG_COMPAT_BRK=y
70CONFIG_BASE_FULL=y
71CONFIG_FUTEX=y
72CONFIG_ANON_INODES=y
73CONFIG_EPOLL=y
74CONFIG_SIGNALFD=y
75CONFIG_TIMERFD=y
76CONFIG_EVENTFD=y
77CONFIG_SHMEM=y
78CONFIG_VM_EVENT_COUNTERS=y
79CONFIG_SLAB=y
80# CONFIG_SLUB is not set
81# CONFIG_SLOB is not set
82# CONFIG_PROFILING is not set
83# CONFIG_MARKERS is not set
84CONFIG_HAVE_OPROFILE=y
85# CONFIG_KPROBES is not set
86CONFIG_HAVE_KPROBES=y
87CONFIG_HAVE_KRETPROBES=y
88# CONFIG_HAVE_DMA_ATTRS is not set
89CONFIG_PROC_PAGE_MONITOR=y
90CONFIG_SLABINFO=y
91CONFIG_RT_MUTEXES=y
92# CONFIG_TINY_SHMEM is not set
93CONFIG_BASE_SMALL=0
94CONFIG_MODULES=y
95# CONFIG_MODULE_FORCE_LOAD is not set
96CONFIG_MODULE_UNLOAD=y
97CONFIG_MODULE_FORCE_UNLOAD=y
98CONFIG_MODVERSIONS=y
99# CONFIG_MODULE_SRCVERSION_ALL is not set
100CONFIG_KMOD=y
101CONFIG_BLOCK=y
102# CONFIG_LBD is not set
103# CONFIG_BLK_DEV_IO_TRACE is not set
104# CONFIG_LSF is not set
105# CONFIG_BLK_DEV_BSG is not set
106
107#
108# IO Schedulers
109#
110CONFIG_IOSCHED_NOOP=y
111CONFIG_IOSCHED_AS=y
112CONFIG_IOSCHED_DEADLINE=y
113CONFIG_IOSCHED_CFQ=y
114# CONFIG_DEFAULT_AS is not set
115# CONFIG_DEFAULT_DEADLINE is not set
116CONFIG_DEFAULT_CFQ=y
117# CONFIG_DEFAULT_NOOP is not set
118CONFIG_DEFAULT_IOSCHED="cfq"
119CONFIG_CLASSIC_RCU=y
120
121#
122# System Type
123#
124# CONFIG_ARCH_AAEC2000 is not set
125# CONFIG_ARCH_INTEGRATOR is not set
126# CONFIG_ARCH_REALVIEW is not set
127# CONFIG_ARCH_VERSATILE is not set
128# CONFIG_ARCH_AT91 is not set
129# CONFIG_ARCH_CLPS7500 is not set
130# CONFIG_ARCH_CLPS711X is not set
131# CONFIG_ARCH_CO285 is not set
132# CONFIG_ARCH_EBSA110 is not set
133# CONFIG_ARCH_EP93XX is not set
134# CONFIG_ARCH_FOOTBRIDGE is not set
135# CONFIG_ARCH_NETX is not set
136# CONFIG_ARCH_H720X is not set
137# CONFIG_ARCH_IMX is not set
138# CONFIG_ARCH_IOP13XX is not set
139# CONFIG_ARCH_IOP32X is not set
140# CONFIG_ARCH_IOP33X is not set
141# CONFIG_ARCH_IXP23XX is not set
142# CONFIG_ARCH_IXP2000 is not set
143# CONFIG_ARCH_IXP4XX is not set
144# CONFIG_ARCH_L7200 is not set
145# CONFIG_ARCH_KS8695 is not set
146# CONFIG_ARCH_NS9XXX is not set
147CONFIG_ARCH_MXC=y
148# CONFIG_ARCH_ORION5X is not set
149# CONFIG_ARCH_PNX4008 is not set
150# CONFIG_ARCH_PXA is not set
151# CONFIG_ARCH_RPC is not set
152# CONFIG_ARCH_SA1100 is not set
153# CONFIG_ARCH_S3C2410 is not set
154# CONFIG_ARCH_SHARK is not set
155# CONFIG_ARCH_LH7A40X is not set
156# CONFIG_ARCH_DAVINCI is not set
157# CONFIG_ARCH_OMAP is not set
158# CONFIG_ARCH_MSM7X00A is not set
159
160#
161# Boot options
162#
163
164#
165# Power management
166#
167
168#
169# Freescale MXC Implementations
170#
171CONFIG_ARCH_MX3=y
172
173#
174# MX3 Options
175#
176# CONFIG_MACH_MX31ADS is not set
177CONFIG_MACH_MX31LITE=y
178
179#
180# Processor Type
181#
182CONFIG_CPU_32=y
183CONFIG_CPU_V6=y
184# CONFIG_CPU_32v6K is not set
185CONFIG_CPU_32v6=y
186CONFIG_CPU_ABRT_EV6=y
187CONFIG_CPU_PABRT_NOIFAR=y
188CONFIG_CPU_CACHE_V6=y
189CONFIG_CPU_CACHE_VIPT=y
190CONFIG_CPU_COPY_V6=y
191CONFIG_CPU_TLB_V6=y
192CONFIG_CPU_HAS_ASID=y
193CONFIG_CPU_CP15=y
194CONFIG_CPU_CP15_MMU=y
195
196#
197# Processor Features
198#
199CONFIG_ARM_THUMB=y
200# CONFIG_CPU_ICACHE_DISABLE is not set
201# CONFIG_CPU_DCACHE_DISABLE is not set
202# CONFIG_CPU_BPREDICT_DISABLE is not set
203# CONFIG_OUTER_CACHE is not set
204
205#
206# Bus support
207#
208# CONFIG_PCI_SYSCALL is not set
209# CONFIG_ARCH_SUPPORTS_MSI is not set
210CONFIG_PCCARD=m
211# CONFIG_PCMCIA_DEBUG is not set
212# CONFIG_PCMCIA is not set
213
214#
215# PC-card bridges
216#
217
218#
219# Kernel Features
220#
221# CONFIG_TICK_ONESHOT is not set
222CONFIG_PREEMPT=y
223# CONFIG_NO_IDLE_HZ is not set
224CONFIG_HZ=100
225CONFIG_AEABI=y
226# CONFIG_OABI_COMPAT is not set
227# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
228CONFIG_SELECT_MEMORY_MODEL=y
229CONFIG_FLATMEM_MANUAL=y
230# CONFIG_DISCONTIGMEM_MANUAL is not set
231# CONFIG_SPARSEMEM_MANUAL is not set
232CONFIG_FLATMEM=y
233CONFIG_FLAT_NODE_MEM_MAP=y
234# CONFIG_SPARSEMEM_STATIC is not set
235# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
236CONFIG_PAGEFLAGS_EXTENDED=y
237CONFIG_SPLIT_PTLOCK_CPUS=4
238# CONFIG_RESOURCES_64BIT is not set
239CONFIG_ZONE_DMA_FLAG=1
240CONFIG_BOUNCE=y
241CONFIG_VIRT_TO_BUS=y
242CONFIG_ALIGNMENT_TRAP=y
243
244#
245# Boot options
246#
247CONFIG_ZBOOT_ROM_TEXT=0x0
248CONFIG_ZBOOT_ROM_BSS=0x0
249CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off"
250# CONFIG_XIP_KERNEL is not set
251# CONFIG_KEXEC is not set
252
253#
254# Floating point emulation
255#
256
257#
258# At least one emulation must be selected
259#
260CONFIG_VFP=y
261
262#
263# Userspace binary formats
264#
265CONFIG_BINFMT_ELF=y
266CONFIG_BINFMT_AOUT=y
267# CONFIG_BINFMT_MISC is not set
268
269#
270# Power management options
271#
272CONFIG_PM=y
273# CONFIG_PM_DEBUG is not set
274# CONFIG_SUSPEND is not set
275# CONFIG_APM_EMULATION is not set
276CONFIG_ARCH_SUSPEND_POSSIBLE=y
277
278#
279# Networking
280#
281CONFIG_NET=y
282
283#
284# Networking options
285#
286CONFIG_PACKET=y
287# CONFIG_PACKET_MMAP is not set
288CONFIG_UNIX=y
289CONFIG_XFRM=y
290# CONFIG_XFRM_USER is not set
291# CONFIG_XFRM_SUB_POLICY is not set
292# CONFIG_XFRM_MIGRATE is not set
293# CONFIG_XFRM_STATISTICS is not set
294# CONFIG_NET_KEY is not set
295CONFIG_INET=y
296# CONFIG_IP_MULTICAST is not set
297# CONFIG_IP_ADVANCED_ROUTER is not set
298CONFIG_IP_FIB_HASH=y
299CONFIG_IP_PNP=y
300CONFIG_IP_PNP_DHCP=y
301# CONFIG_IP_PNP_BOOTP is not set
302# CONFIG_IP_PNP_RARP is not set
303# CONFIG_NET_IPIP is not set
304# CONFIG_NET_IPGRE is not set
305# CONFIG_ARPD is not set
306# CONFIG_SYN_COOKIES is not set
307# CONFIG_INET_AH is not set
308# CONFIG_INET_ESP is not set
309# CONFIG_INET_IPCOMP is not set
310# CONFIG_INET_XFRM_TUNNEL is not set
311# CONFIG_INET_TUNNEL is not set
312CONFIG_INET_XFRM_MODE_TRANSPORT=y
313CONFIG_INET_XFRM_MODE_TUNNEL=y
314CONFIG_INET_XFRM_MODE_BEET=y
315# CONFIG_INET_LRO is not set
316CONFIG_INET_DIAG=y
317CONFIG_INET_TCP_DIAG=y
318# CONFIG_TCP_CONG_ADVANCED is not set
319CONFIG_TCP_CONG_CUBIC=y
320CONFIG_DEFAULT_TCP_CONG="cubic"
321# CONFIG_TCP_MD5SIG is not set
322# CONFIG_IPV6 is not set
323# CONFIG_NETWORK_SECMARK is not set
324# CONFIG_NETFILTER is not set
325# CONFIG_IP_DCCP is not set
326# CONFIG_IP_SCTP is not set
327# CONFIG_TIPC is not set
328# CONFIG_ATM is not set
329# CONFIG_BRIDGE is not set
330# CONFIG_VLAN_8021Q is not set
331# CONFIG_DECNET is not set
332# CONFIG_LLC2 is not set
333# CONFIG_IPX is not set
334# CONFIG_ATALK is not set
335# CONFIG_X25 is not set
336# CONFIG_LAPB is not set
337# CONFIG_ECONET is not set
338# CONFIG_WAN_ROUTER is not set
339# CONFIG_NET_SCHED is not set
340
341#
342# Network testing
343#
344# CONFIG_NET_PKTGEN is not set
345# CONFIG_HAMRADIO is not set
346# CONFIG_CAN is not set
347# CONFIG_IRDA is not set
348# CONFIG_BT is not set
349# CONFIG_AF_RXRPC is not set
350
351#
352# Wireless
353#
354# CONFIG_CFG80211 is not set
355# CONFIG_WIRELESS_EXT is not set
356# CONFIG_MAC80211 is not set
357# CONFIG_IEEE80211 is not set
358# CONFIG_RFKILL is not set
359# CONFIG_NET_9P is not set
360
361#
362# Device Drivers
363#
364
365#
366# Generic Driver Options
367#
368CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
369CONFIG_STANDALONE=y
370CONFIG_PREVENT_FIRMWARE_BUILD=y
371CONFIG_FW_LOADER=m
372# CONFIG_DEBUG_DRIVER is not set
373# CONFIG_DEBUG_DEVRES is not set
374# CONFIG_SYS_HYPERVISOR is not set
375# CONFIG_CONNECTOR is not set
376CONFIG_MTD=y
377# CONFIG_MTD_DEBUG is not set
378# CONFIG_MTD_CONCAT is not set
379CONFIG_MTD_PARTITIONS=y
380CONFIG_MTD_REDBOOT_PARTS=y
381CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
382# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
383# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
384CONFIG_MTD_CMDLINE_PARTS=y
385# CONFIG_MTD_AFS_PARTS is not set
386# CONFIG_MTD_AR7_PARTS is not set
387
388#
389# User Modules And Translation Layers
390#
391CONFIG_MTD_CHAR=y
392CONFIG_MTD_BLKDEVS=y
393CONFIG_MTD_BLOCK=y
394# CONFIG_FTL is not set
395# CONFIG_NFTL is not set
396# CONFIG_INFTL is not set
397# CONFIG_RFD_FTL is not set
398# CONFIG_SSFDC is not set
399# CONFIG_MTD_OOPS is not set
400
401#
402# RAM/ROM/Flash chip drivers
403#
404CONFIG_MTD_CFI=y
405# CONFIG_MTD_JEDECPROBE is not set
406CONFIG_MTD_GEN_PROBE=y
407CONFIG_MTD_CFI_ADV_OPTIONS=y
408CONFIG_MTD_CFI_NOSWAP=y
409# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
410# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
411CONFIG_MTD_CFI_GEOMETRY=y
412# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
413CONFIG_MTD_MAP_BANK_WIDTH_2=y
414# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
415# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
416# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
417# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
418CONFIG_MTD_CFI_I1=y
419# CONFIG_MTD_CFI_I2 is not set
420# CONFIG_MTD_CFI_I4 is not set
421# CONFIG_MTD_CFI_I8 is not set
422# CONFIG_MTD_OTP is not set
423# CONFIG_MTD_CFI_INTELEXT is not set
424CONFIG_MTD_CFI_AMDSTD=y
425# CONFIG_MTD_CFI_STAA is not set
426CONFIG_MTD_CFI_UTIL=y
427CONFIG_MTD_RAM=y
428# CONFIG_MTD_ROM is not set
429# CONFIG_MTD_ABSENT is not set
430# CONFIG_MTD_XIP is not set
431
432#
433# Mapping drivers for chip access
434#
435# CONFIG_MTD_COMPLEX_MAPPINGS is not set
436# CONFIG_MTD_PHYSMAP is not set
437# CONFIG_MTD_ARM_INTEGRATOR is not set
438# CONFIG_MTD_PLATRAM is not set
439
440#
441# Self-contained MTD device drivers
442#
443# CONFIG_MTD_SLRAM is not set
444# CONFIG_MTD_PHRAM is not set
445# CONFIG_MTD_MTDRAM is not set
446# CONFIG_MTD_BLOCK2MTD is not set
447
448#
449# Disk-On-Chip Device Drivers
450#
451# CONFIG_MTD_DOC2000 is not set
452# CONFIG_MTD_DOC2001 is not set
453# CONFIG_MTD_DOC2001PLUS is not set
454CONFIG_MTD_NAND=y
455# CONFIG_MTD_NAND_VERIFY_WRITE is not set
456# CONFIG_MTD_NAND_ECC_SMC is not set
457# CONFIG_MTD_NAND_MUSEUM_IDS is not set
458CONFIG_MTD_NAND_IDS=y
459# CONFIG_MTD_NAND_DISKONCHIP is not set
460# CONFIG_MTD_NAND_NANDSIM is not set
461# CONFIG_MTD_NAND_PLATFORM is not set
462# CONFIG_MTD_ALAUDA is not set
463# CONFIG_MTD_ONENAND is not set
464
465#
466# UBI - Unsorted block images
467#
468# CONFIG_MTD_UBI is not set
469# CONFIG_PARPORT is not set
470# CONFIG_BLK_DEV is not set
471# CONFIG_MISC_DEVICES is not set
472CONFIG_HAVE_IDE=y
473# CONFIG_IDE is not set
474
475#
476# SCSI device support
477#
478# CONFIG_RAID_ATTRS is not set
479CONFIG_SCSI=y
480CONFIG_SCSI_DMA=y
481# CONFIG_SCSI_TGT is not set
482# CONFIG_SCSI_NETLINK is not set
483CONFIG_SCSI_PROC_FS=y
484
485#
486# SCSI support type (disk, tape, CD-ROM)
487#
488CONFIG_BLK_DEV_SD=y
489# CONFIG_CHR_DEV_ST is not set
490# CONFIG_CHR_DEV_OSST is not set
491# CONFIG_BLK_DEV_SR is not set
492# CONFIG_CHR_DEV_SG is not set
493# CONFIG_CHR_DEV_SCH is not set
494
495#
496# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
497#
498CONFIG_SCSI_MULTI_LUN=y
499# CONFIG_SCSI_CONSTANTS is not set
500# CONFIG_SCSI_LOGGING is not set
501# CONFIG_SCSI_SCAN_ASYNC is not set
502CONFIG_SCSI_WAIT_SCAN=m
503
504#
505# SCSI Transports
506#
507# CONFIG_SCSI_SPI_ATTRS is not set
508# CONFIG_SCSI_FC_ATTRS is not set
509# CONFIG_SCSI_ISCSI_ATTRS is not set
510# CONFIG_SCSI_SAS_LIBSAS is not set
511# CONFIG_SCSI_SRP_ATTRS is not set
512CONFIG_SCSI_LOWLEVEL=y
513# CONFIG_ISCSI_TCP is not set
514# CONFIG_SCSI_DEBUG is not set
515# CONFIG_ATA is not set
516# CONFIG_MD is not set
517CONFIG_NETDEVICES=y
518# CONFIG_NETDEVICES_MULTIQUEUE is not set
519# CONFIG_DUMMY is not set
520# CONFIG_BONDING is not set
521# CONFIG_MACVLAN is not set
522# CONFIG_EQUALIZER is not set
523# CONFIG_TUN is not set
524# CONFIG_VETH is not set
525# CONFIG_PHYLIB is not set
526CONFIG_NET_ETHERNET=y
527CONFIG_MII=y
528# CONFIG_AX88796 is not set
529# CONFIG_SMC91X is not set
530# CONFIG_DM9000 is not set
531# CONFIG_IBM_NEW_EMAC_ZMII is not set
532# CONFIG_IBM_NEW_EMAC_RGMII is not set
533# CONFIG_IBM_NEW_EMAC_TAH is not set
534# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
535# CONFIG_B44 is not set
536# CONFIG_NETDEV_1000 is not set
537# CONFIG_NETDEV_10000 is not set
538
539#
540# Wireless LAN
541#
542# CONFIG_WLAN_PRE80211 is not set
543# CONFIG_WLAN_80211 is not set
544# CONFIG_IWLWIFI_LEDS is not set
545
546#
547# USB Network Adapters
548#
549# CONFIG_USB_CATC is not set
550# CONFIG_USB_KAWETH is not set
551# CONFIG_USB_PEGASUS is not set
552# CONFIG_USB_RTL8150 is not set
553# CONFIG_USB_USBNET is not set
554# CONFIG_WAN is not set
555# CONFIG_PPP is not set
556# CONFIG_SLIP is not set
557# CONFIG_NETCONSOLE is not set
558# CONFIG_NETPOLL is not set
559# CONFIG_NET_POLL_CONTROLLER is not set
560# CONFIG_ISDN is not set
561
562#
563# Input device support
564#
565CONFIG_INPUT=y
566# CONFIG_INPUT_FF_MEMLESS is not set
567# CONFIG_INPUT_POLLDEV is not set
568
569#
570# Userland interfaces
571#
572# CONFIG_INPUT_MOUSEDEV is not set
573# CONFIG_INPUT_JOYDEV is not set
574CONFIG_INPUT_EVDEV=y
575# CONFIG_INPUT_EVBUG is not set
576
577#
578# Input Device Drivers
579#
580CONFIG_INPUT_KEYBOARD=y
581# CONFIG_KEYBOARD_ATKBD is not set
582# CONFIG_KEYBOARD_SUNKBD is not set
583# CONFIG_KEYBOARD_LKKBD is not set
584# CONFIG_KEYBOARD_XTKBD is not set
585# CONFIG_KEYBOARD_NEWTON is not set
586# CONFIG_KEYBOARD_STOWAWAY is not set
587# CONFIG_INPUT_MOUSE is not set
588# CONFIG_INPUT_JOYSTICK is not set
589# CONFIG_INPUT_TABLET is not set
590CONFIG_INPUT_TOUCHSCREEN=y
591# CONFIG_TOUCHSCREEN_FUJITSU is not set
592# CONFIG_TOUCHSCREEN_GUNZE is not set
593# CONFIG_TOUCHSCREEN_ELO is not set
594# CONFIG_TOUCHSCREEN_MTOUCH is not set
595# CONFIG_TOUCHSCREEN_MK712 is not set
596# CONFIG_TOUCHSCREEN_PENMOUNT is not set
597# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
598# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
599# CONFIG_TOUCHSCREEN_UCB1400 is not set
600# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
601# CONFIG_INPUT_MISC is not set
602
603#
604# Hardware I/O ports
605#
606# CONFIG_SERIO is not set
607# CONFIG_GAMEPORT is not set
608
609#
610# Character devices
611#
612CONFIG_VT=y
613CONFIG_VT_CONSOLE=y
614CONFIG_HW_CONSOLE=y
615# CONFIG_VT_HW_CONSOLE_BINDING is not set
616CONFIG_DEVKMEM=y
617# CONFIG_SERIAL_NONSTANDARD is not set
618
619#
620# Serial drivers
621#
622# CONFIG_SERIAL_8250 is not set
623
624#
625# Non-8250 serial port support
626#
627CONFIG_UNIX98_PTYS=y
628CONFIG_LEGACY_PTYS=y
629CONFIG_LEGACY_PTY_COUNT=256
630# CONFIG_IPMI_HANDLER is not set
631CONFIG_HW_RANDOM=y
632# CONFIG_NVRAM is not set
633# CONFIG_R3964 is not set
634# CONFIG_RAW_DRIVER is not set
635# CONFIG_TCG_TPM is not set
636# CONFIG_I2C is not set
637# CONFIG_SPI is not set
638# CONFIG_W1 is not set
639# CONFIG_POWER_SUPPLY is not set
640# CONFIG_HWMON is not set
641CONFIG_WATCHDOG=y
642CONFIG_WATCHDOG_NOWAYOUT=y
643
644#
645# Watchdog Device Drivers
646#
647# CONFIG_SOFT_WATCHDOG is not set
648
649#
650# USB-based Watchdog Cards
651#
652# CONFIG_USBPCWATCHDOG is not set
653
654#
655# Sonics Silicon Backplane
656#
657CONFIG_SSB_POSSIBLE=y
658# CONFIG_SSB is not set
659
660#
661# Multifunction device drivers
662#
663# CONFIG_MFD_SM501 is not set
664# CONFIG_MFD_ASIC3 is not set
665# CONFIG_HTC_PASIC3 is not set
666
667#
668# Multimedia devices
669#
670
671#
672# Multimedia core support
673#
674CONFIG_VIDEO_DEV=y
675CONFIG_VIDEO_V4L2_COMMON=y
676CONFIG_VIDEO_ALLOW_V4L1=y
677CONFIG_VIDEO_V4L1_COMPAT=y
678# CONFIG_DVB_CORE is not set
679CONFIG_VIDEO_MEDIA=y
680
681#
682# Multimedia drivers
683#
684# CONFIG_MEDIA_ATTACH is not set
685CONFIG_VIDEO_V4L2=y
686CONFIG_VIDEO_V4L1=y
687CONFIG_VIDEO_CAPTURE_DRIVERS=y
688# CONFIG_VIDEO_ADV_DEBUG is not set
689CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
690# CONFIG_VIDEO_VIVI is not set
691# CONFIG_VIDEO_CPIA is not set
692# CONFIG_VIDEO_CPIA2 is not set
693CONFIG_V4L_USB_DRIVERS=y
694# CONFIG_USB_VICAM is not set
695# CONFIG_USB_IBMCAM is not set
696# CONFIG_USB_KONICAWC is not set
697# CONFIG_USB_QUICKCAM_MESSENGER is not set
698# CONFIG_USB_ET61X251 is not set
699# CONFIG_USB_OV511 is not set
700# CONFIG_USB_SE401 is not set
701# CONFIG_USB_SN9C102 is not set
702# CONFIG_USB_STV680 is not set
703# CONFIG_USB_ZC0301 is not set
704# CONFIG_USB_PWC is not set
705# CONFIG_USB_ZR364XX is not set
706# CONFIG_USB_STKWEBCAM is not set
707# CONFIG_SOC_CAMERA is not set
708CONFIG_RADIO_ADAPTERS=y
709# CONFIG_USB_DSBR is not set
710# CONFIG_USB_SI470X is not set
711CONFIG_DAB=y
712# CONFIG_USB_DABUSB is not set
713
714#
715# Graphics support
716#
717# CONFIG_VGASTATE is not set
718# CONFIG_VIDEO_OUTPUT_CONTROL is not set
719CONFIG_FB=y
720# CONFIG_FIRMWARE_EDID is not set
721# CONFIG_FB_DDC is not set
722# CONFIG_FB_CFB_FILLRECT is not set
723# CONFIG_FB_CFB_COPYAREA is not set
724# CONFIG_FB_CFB_IMAGEBLIT is not set
725# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
726# CONFIG_FB_SYS_FILLRECT is not set
727# CONFIG_FB_SYS_COPYAREA is not set
728# CONFIG_FB_SYS_IMAGEBLIT is not set
729# CONFIG_FB_FOREIGN_ENDIAN is not set
730# CONFIG_FB_SYS_FOPS is not set
731# CONFIG_FB_SVGALIB is not set
732# CONFIG_FB_MACMODES is not set
733# CONFIG_FB_BACKLIGHT is not set
734# CONFIG_FB_MODE_HELPERS is not set
735# CONFIG_FB_TILEBLITTING is not set
736
737#
738# Frame buffer hardware drivers
739#
740# CONFIG_FB_S1D13XXX is not set
741# CONFIG_FB_VIRTUAL is not set
742# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
743
744#
745# Display device support
746#
747# CONFIG_DISPLAY_SUPPORT is not set
748
749#
750# Console display driver support
751#
752# CONFIG_VGA_CONSOLE is not set
753CONFIG_DUMMY_CONSOLE=y
754CONFIG_FRAMEBUFFER_CONSOLE=y
755# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
756# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
757# CONFIG_FONTS is not set
758CONFIG_FONT_8x8=y
759CONFIG_FONT_8x16=y
760CONFIG_LOGO=y
761# CONFIG_LOGO_LINUX_MONO is not set
762# CONFIG_LOGO_LINUX_VGA16 is not set
763CONFIG_LOGO_LINUX_CLUT224=y
764
765#
766# Sound
767#
768# CONFIG_SOUND is not set
769# CONFIG_HID_SUPPORT is not set
770CONFIG_USB_SUPPORT=y
771CONFIG_USB_ARCH_HAS_HCD=y
772# CONFIG_USB_ARCH_HAS_OHCI is not set
773# CONFIG_USB_ARCH_HAS_EHCI is not set
774CONFIG_USB=y
775# CONFIG_USB_DEBUG is not set
776# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
777
778#
779# Miscellaneous USB options
780#
781# CONFIG_USB_DEVICEFS is not set
782CONFIG_USB_DEVICE_CLASS=y
783# CONFIG_USB_DYNAMIC_MINORS is not set
784# CONFIG_USB_SUSPEND is not set
785# CONFIG_USB_OTG is not set
786# CONFIG_USB_OTG_WHITELIST is not set
787# CONFIG_USB_OTG_BLACKLIST_HUB is not set
788
789#
790# USB Host Controller Drivers
791#
792# CONFIG_USB_C67X00_HCD is not set
793# CONFIG_USB_ISP116X_HCD is not set
794# CONFIG_USB_ISP1760_HCD is not set
795# CONFIG_USB_SL811_HCD is not set
796# CONFIG_USB_R8A66597_HCD is not set
797
798#
799# USB Device Class drivers
800#
801# CONFIG_USB_ACM is not set
802# CONFIG_USB_PRINTER is not set
803# CONFIG_USB_WDM is not set
804
805#
806# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
807#
808
809#
810# may also be needed; see USB_STORAGE Help for more information
811#
812# CONFIG_USB_STORAGE is not set
813# CONFIG_USB_LIBUSUAL is not set
814
815#
816# USB Imaging devices
817#
818# CONFIG_USB_MDC800 is not set
819# CONFIG_USB_MICROTEK is not set
820CONFIG_USB_MON=y
821
822#
823# USB port drivers
824#
825# CONFIG_USB_SERIAL is not set
826
827#
828# USB Miscellaneous drivers
829#
830# CONFIG_USB_EMI62 is not set
831# CONFIG_USB_EMI26 is not set
832# CONFIG_USB_ADUTUX is not set
833# CONFIG_USB_AUERSWALD is not set
834# CONFIG_USB_RIO500 is not set
835# CONFIG_USB_LEGOTOWER is not set
836# CONFIG_USB_LCD is not set
837# CONFIG_USB_BERRY_CHARGE is not set
838# CONFIG_USB_LED is not set
839# CONFIG_USB_CYPRESS_CY7C63 is not set
840# CONFIG_USB_CYTHERM is not set
841# CONFIG_USB_PHIDGET is not set
842# CONFIG_USB_IDMOUSE is not set
843# CONFIG_USB_FTDI_ELAN is not set
844# CONFIG_USB_APPLEDISPLAY is not set
845# CONFIG_USB_LD is not set
846# CONFIG_USB_TRANCEVIBRATOR is not set
847# CONFIG_USB_IOWARRIOR is not set
848# CONFIG_USB_ISIGHTFW is not set
849# CONFIG_USB_GADGET is not set
850# CONFIG_MMC is not set
851# CONFIG_NEW_LEDS is not set
852CONFIG_RTC_LIB=y
853# CONFIG_RTC_CLASS is not set
854# CONFIG_UIO is not set
855
856#
857# File systems
858#
859# CONFIG_EXT2_FS is not set
860# CONFIG_EXT3_FS is not set
861# CONFIG_EXT4DEV_FS is not set
862# CONFIG_REISERFS_FS is not set
863# CONFIG_JFS_FS is not set
864# CONFIG_FS_POSIX_ACL is not set
865# CONFIG_XFS_FS is not set
866# CONFIG_OCFS2_FS is not set
867# CONFIG_DNOTIFY is not set
868CONFIG_INOTIFY=y
869CONFIG_INOTIFY_USER=y
870# CONFIG_QUOTA is not set
871# CONFIG_AUTOFS_FS is not set
872# CONFIG_AUTOFS4_FS is not set
873# CONFIG_FUSE_FS is not set
874
875#
876# CD-ROM/DVD Filesystems
877#
878# CONFIG_ISO9660_FS is not set
879# CONFIG_UDF_FS is not set
880
881#
882# DOS/FAT/NT Filesystems
883#
884# CONFIG_MSDOS_FS is not set
885# CONFIG_VFAT_FS is not set
886# CONFIG_NTFS_FS is not set
887
888#
889# Pseudo filesystems
890#
891CONFIG_PROC_FS=y
892CONFIG_PROC_SYSCTL=y
893CONFIG_SYSFS=y
894CONFIG_TMPFS=y
895# CONFIG_TMPFS_POSIX_ACL is not set
896# CONFIG_HUGETLB_PAGE is not set
897# CONFIG_CONFIGFS_FS is not set
898
899#
900# Miscellaneous filesystems
901#
902# CONFIG_ADFS_FS is not set
903# CONFIG_AFFS_FS is not set
904# CONFIG_HFS_FS is not set
905# CONFIG_HFSPLUS_FS is not set
906# CONFIG_BEFS_FS is not set
907# CONFIG_BFS_FS is not set
908# CONFIG_EFS_FS is not set
909CONFIG_JFFS2_FS=y
910CONFIG_JFFS2_FS_DEBUG=0
911CONFIG_JFFS2_FS_WRITEBUFFER=y
912# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
913# CONFIG_JFFS2_SUMMARY is not set
914# CONFIG_JFFS2_FS_XATTR is not set
915# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
916CONFIG_JFFS2_ZLIB=y
917# CONFIG_JFFS2_LZO is not set
918CONFIG_JFFS2_RTIME=y
919# CONFIG_JFFS2_RUBIN is not set
920CONFIG_CRAMFS=y
921# CONFIG_VXFS_FS is not set
922# CONFIG_MINIX_FS is not set
923# CONFIG_HPFS_FS is not set
924# CONFIG_QNX4FS_FS is not set
925# CONFIG_ROMFS_FS is not set
926# CONFIG_SYSV_FS is not set
927# CONFIG_UFS_FS is not set
928CONFIG_NETWORK_FILESYSTEMS=y
929CONFIG_NFS_FS=y
930# CONFIG_NFS_V3 is not set
931# CONFIG_NFS_V4 is not set
932# CONFIG_NFSD is not set
933CONFIG_ROOT_NFS=y
934CONFIG_LOCKD=y
935CONFIG_NFS_COMMON=y
936CONFIG_SUNRPC=y
937# CONFIG_SUNRPC_BIND34 is not set
938# CONFIG_RPCSEC_GSS_KRB5 is not set
939# CONFIG_RPCSEC_GSS_SPKM3 is not set
940# CONFIG_SMB_FS is not set
941# CONFIG_CIFS is not set
942# CONFIG_NCP_FS is not set
943# CONFIG_CODA_FS is not set
944# CONFIG_AFS_FS is not set
945
946#
947# Partition Types
948#
949# CONFIG_PARTITION_ADVANCED is not set
950CONFIG_MSDOS_PARTITION=y
951# CONFIG_NLS is not set
952# CONFIG_DLM is not set
953
954#
955# Kernel hacking
956#
957CONFIG_PRINTK_TIME=y
958CONFIG_ENABLE_WARN_DEPRECATED=y
959CONFIG_ENABLE_MUST_CHECK=y
960CONFIG_FRAME_WARN=1024
961# CONFIG_MAGIC_SYSRQ is not set
962# CONFIG_UNUSED_SYMBOLS is not set
963# CONFIG_DEBUG_FS is not set
964# CONFIG_HEADERS_CHECK is not set
965CONFIG_DEBUG_KERNEL=y
966# CONFIG_DEBUG_SHIRQ is not set
967CONFIG_DETECT_SOFTLOCKUP=y
968CONFIG_SCHED_DEBUG=y
969# CONFIG_SCHEDSTATS is not set
970# CONFIG_TIMER_STATS is not set
971# CONFIG_DEBUG_OBJECTS is not set
972# CONFIG_DEBUG_SLAB is not set
973CONFIG_DEBUG_PREEMPT=y
974# CONFIG_DEBUG_RT_MUTEXES is not set
975# CONFIG_RT_MUTEX_TESTER is not set
976# CONFIG_DEBUG_SPINLOCK is not set
977# CONFIG_DEBUG_MUTEXES is not set
978# CONFIG_DEBUG_LOCK_ALLOC is not set
979# CONFIG_PROVE_LOCKING is not set
980# CONFIG_LOCK_STAT is not set
981# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
982# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
983# CONFIG_DEBUG_KOBJECT is not set
984CONFIG_DEBUG_BUGVERBOSE=y
985# CONFIG_DEBUG_INFO is not set
986# CONFIG_DEBUG_VM is not set
987# CONFIG_DEBUG_WRITECOUNT is not set
988# CONFIG_DEBUG_LIST is not set
989# CONFIG_DEBUG_SG is not set
990CONFIG_FRAME_POINTER=y
991# CONFIG_BOOT_PRINTK_DELAY is not set
992# CONFIG_RCU_TORTURE_TEST is not set
993# CONFIG_BACKTRACE_SELF_TEST is not set
994# CONFIG_FAULT_INJECTION is not set
995# CONFIG_SAMPLES is not set
996# CONFIG_DEBUG_USER is not set
997CONFIG_DEBUG_ERRORS=y
998# CONFIG_DEBUG_STACK_USAGE is not set
999CONFIG_DEBUG_LL=y
1000# CONFIG_DEBUG_ICEDCC is not set
1001
1002#
1003# Security options
1004#
1005# CONFIG_KEYS is not set
1006# CONFIG_SECURITY is not set
1007# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1008CONFIG_CRYPTO=y
1009
1010#
1011# Crypto core or helper
1012#
1013# CONFIG_CRYPTO_MANAGER is not set
1014# CONFIG_CRYPTO_GF128MUL is not set
1015# CONFIG_CRYPTO_NULL is not set
1016# CONFIG_CRYPTO_CRYPTD is not set
1017# CONFIG_CRYPTO_AUTHENC is not set
1018# CONFIG_CRYPTO_TEST is not set
1019
1020#
1021# Authenticated Encryption with Associated Data
1022#
1023# CONFIG_CRYPTO_CCM is not set
1024# CONFIG_CRYPTO_GCM is not set
1025# CONFIG_CRYPTO_SEQIV is not set
1026
1027#
1028# Block modes
1029#
1030# CONFIG_CRYPTO_CBC is not set
1031# CONFIG_CRYPTO_CTR is not set
1032# CONFIG_CRYPTO_CTS is not set
1033# CONFIG_CRYPTO_ECB is not set
1034# CONFIG_CRYPTO_LRW is not set
1035# CONFIG_CRYPTO_PCBC is not set
1036# CONFIG_CRYPTO_XTS is not set
1037
1038#
1039# Hash modes
1040#
1041# CONFIG_CRYPTO_HMAC is not set
1042# CONFIG_CRYPTO_XCBC is not set
1043
1044#
1045# Digest
1046#
1047# CONFIG_CRYPTO_CRC32C is not set
1048# CONFIG_CRYPTO_MD4 is not set
1049# CONFIG_CRYPTO_MD5 is not set
1050# CONFIG_CRYPTO_MICHAEL_MIC is not set
1051# CONFIG_CRYPTO_SHA1 is not set
1052# CONFIG_CRYPTO_SHA256 is not set
1053# CONFIG_CRYPTO_SHA512 is not set
1054# CONFIG_CRYPTO_TGR192 is not set
1055# CONFIG_CRYPTO_WP512 is not set
1056
1057#
1058# Ciphers
1059#
1060# CONFIG_CRYPTO_AES is not set
1061# CONFIG_CRYPTO_ANUBIS is not set
1062# CONFIG_CRYPTO_ARC4 is not set
1063# CONFIG_CRYPTO_BLOWFISH is not set
1064# CONFIG_CRYPTO_CAMELLIA is not set
1065# CONFIG_CRYPTO_CAST5 is not set
1066# CONFIG_CRYPTO_CAST6 is not set
1067# CONFIG_CRYPTO_DES is not set
1068# CONFIG_CRYPTO_FCRYPT is not set
1069# CONFIG_CRYPTO_KHAZAD is not set
1070# CONFIG_CRYPTO_SALSA20 is not set
1071# CONFIG_CRYPTO_SEED is not set
1072# CONFIG_CRYPTO_SERPENT is not set
1073# CONFIG_CRYPTO_TEA is not set
1074# CONFIG_CRYPTO_TWOFISH is not set
1075
1076#
1077# Compression
1078#
1079# CONFIG_CRYPTO_DEFLATE is not set
1080# CONFIG_CRYPTO_LZO is not set
1081CONFIG_CRYPTO_HW=y
1082
1083#
1084# Library routines
1085#
1086CONFIG_BITREVERSE=y
1087# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1088# CONFIG_GENERIC_FIND_NEXT_BIT is not set
1089CONFIG_CRC_CCITT=m
1090# CONFIG_CRC16 is not set
1091# CONFIG_CRC_ITU_T is not set
1092CONFIG_CRC32=y
1093# CONFIG_CRC7 is not set
1094# CONFIG_LIBCRC32C is not set
1095CONFIG_ZLIB_INFLATE=y
1096CONFIG_ZLIB_DEFLATE=y
1097CONFIG_PLIST=y
1098CONFIG_HAS_IOMEM=y
1099CONFIG_HAS_IOPORT=y
1100CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/pcm037_defconfig b/arch/arm/configs/pcm037_defconfig
new file mode 100644
index 000000000000..627474586470
--- /dev/null
+++ b/arch/arm/configs/pcm037_defconfig
@@ -0,0 +1,748 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc6
4# Wed Jun 25 11:52:42 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ARCH_SUPPORTS_AOUT=y
25CONFIG_ZONE_DMA=y
26CONFIG_ARCH_MTD_XIP=y
27CONFIG_VECTORS_BASE=0xffff0000
28CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
29
30#
31# General setup
32#
33CONFIG_EXPERIMENTAL=y
34CONFIG_BROKEN_ON_SMP=y
35CONFIG_LOCK_KERNEL=y
36CONFIG_INIT_ENV_ARG_LIMIT=32
37CONFIG_LOCALVERSION=""
38CONFIG_LOCALVERSION_AUTO=y
39CONFIG_SWAP=y
40CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set
43# CONFIG_BSD_PROCESS_ACCT is not set
44# CONFIG_TASKSTATS is not set
45# CONFIG_AUDIT is not set
46CONFIG_IKCONFIG=y
47CONFIG_IKCONFIG_PROC=y
48CONFIG_LOG_BUF_SHIFT=14
49# CONFIG_CGROUPS is not set
50CONFIG_GROUP_SCHED=y
51CONFIG_FAIR_GROUP_SCHED=y
52# CONFIG_RT_GROUP_SCHED is not set
53CONFIG_USER_SCHED=y
54# CONFIG_CGROUP_SCHED is not set
55CONFIG_SYSFS_DEPRECATED=y
56CONFIG_SYSFS_DEPRECATED_V2=y
57# CONFIG_RELAY is not set
58# CONFIG_NAMESPACES is not set
59# CONFIG_BLK_DEV_INITRD is not set
60CONFIG_CC_OPTIMIZE_FOR_SIZE=y
61CONFIG_SYSCTL=y
62CONFIG_EMBEDDED=y
63CONFIG_UID16=y
64CONFIG_SYSCTL_SYSCALL=y
65CONFIG_SYSCTL_SYSCALL_CHECK=y
66CONFIG_KALLSYMS=y
67# CONFIG_KALLSYMS_EXTRA_PASS is not set
68CONFIG_HOTPLUG=y
69CONFIG_PRINTK=y
70CONFIG_BUG=y
71CONFIG_ELF_CORE=y
72CONFIG_COMPAT_BRK=y
73CONFIG_BASE_FULL=y
74CONFIG_FUTEX=y
75CONFIG_ANON_INODES=y
76CONFIG_EPOLL=y
77CONFIG_SIGNALFD=y
78CONFIG_TIMERFD=y
79CONFIG_EVENTFD=y
80CONFIG_SHMEM=y
81CONFIG_VM_EVENT_COUNTERS=y
82CONFIG_SLAB=y
83# CONFIG_SLUB is not set
84# CONFIG_SLOB is not set
85# CONFIG_PROFILING is not set
86# CONFIG_MARKERS is not set
87CONFIG_HAVE_OPROFILE=y
88# CONFIG_KPROBES is not set
89CONFIG_HAVE_KPROBES=y
90CONFIG_HAVE_KRETPROBES=y
91# CONFIG_HAVE_DMA_ATTRS is not set
92CONFIG_PROC_PAGE_MONITOR=y
93CONFIG_SLABINFO=y
94CONFIG_RT_MUTEXES=y
95# CONFIG_TINY_SHMEM is not set
96CONFIG_BASE_SMALL=0
97CONFIG_MODULES=y
98# CONFIG_MODULE_FORCE_LOAD is not set
99CONFIG_MODULE_UNLOAD=y
100CONFIG_MODULE_FORCE_UNLOAD=y
101CONFIG_MODVERSIONS=y
102# CONFIG_MODULE_SRCVERSION_ALL is not set
103CONFIG_KMOD=y
104CONFIG_BLOCK=y
105# CONFIG_LBD is not set
106# CONFIG_BLK_DEV_IO_TRACE is not set
107# CONFIG_LSF is not set
108# CONFIG_BLK_DEV_BSG is not set
109
110#
111# IO Schedulers
112#
113CONFIG_IOSCHED_NOOP=y
114CONFIG_IOSCHED_AS=y
115CONFIG_IOSCHED_DEADLINE=y
116CONFIG_IOSCHED_CFQ=y
117# CONFIG_DEFAULT_AS is not set
118# CONFIG_DEFAULT_DEADLINE is not set
119CONFIG_DEFAULT_CFQ=y
120# CONFIG_DEFAULT_NOOP is not set
121CONFIG_DEFAULT_IOSCHED="cfq"
122CONFIG_CLASSIC_RCU=y
123
124#
125# System Type
126#
127# CONFIG_ARCH_AAEC2000 is not set
128# CONFIG_ARCH_INTEGRATOR is not set
129# CONFIG_ARCH_REALVIEW is not set
130# CONFIG_ARCH_VERSATILE is not set
131# CONFIG_ARCH_AT91 is not set
132# CONFIG_ARCH_CLPS7500 is not set
133# CONFIG_ARCH_CLPS711X is not set
134# CONFIG_ARCH_CO285 is not set
135# CONFIG_ARCH_EBSA110 is not set
136# CONFIG_ARCH_EP93XX is not set
137# CONFIG_ARCH_FOOTBRIDGE is not set
138# CONFIG_ARCH_NETX is not set
139# CONFIG_ARCH_H720X is not set
140# CONFIG_ARCH_IMX is not set
141# CONFIG_ARCH_IOP13XX is not set
142# CONFIG_ARCH_IOP32X is not set
143# CONFIG_ARCH_IOP33X is not set
144# CONFIG_ARCH_IXP23XX is not set
145# CONFIG_ARCH_IXP2000 is not set
146# CONFIG_ARCH_IXP4XX is not set
147# CONFIG_ARCH_L7200 is not set
148# CONFIG_ARCH_KS8695 is not set
149# CONFIG_ARCH_NS9XXX is not set
150CONFIG_ARCH_MXC=y
151# CONFIG_ARCH_ORION5X is not set
152# CONFIG_ARCH_PNX4008 is not set
153# CONFIG_ARCH_PXA is not set
154# CONFIG_ARCH_RPC is not set
155# CONFIG_ARCH_SA1100 is not set
156# CONFIG_ARCH_S3C2410 is not set
157# CONFIG_ARCH_SHARK is not set
158# CONFIG_ARCH_LH7A40X is not set
159# CONFIG_ARCH_DAVINCI is not set
160# CONFIG_ARCH_OMAP is not set
161# CONFIG_ARCH_MSM7X00A is not set
162
163#
164# Boot options
165#
166
167#
168# Power management
169#
170
171#
172# Freescale MXC Implementations
173#
174CONFIG_ARCH_MX3=y
175
176#
177# MX3 Options
178#
179# CONFIG_MACH_MX31ADS is not set
180CONFIG_MACH_PCM037=y
181
182#
183# Processor Type
184#
185CONFIG_CPU_32=y
186CONFIG_CPU_V6=y
187# CONFIG_CPU_32v6K is not set
188CONFIG_CPU_32v6=y
189CONFIG_CPU_ABRT_EV6=y
190CONFIG_CPU_PABRT_NOIFAR=y
191CONFIG_CPU_CACHE_V6=y
192CONFIG_CPU_CACHE_VIPT=y
193CONFIG_CPU_COPY_V6=y
194CONFIG_CPU_TLB_V6=y
195CONFIG_CPU_HAS_ASID=y
196CONFIG_CPU_CP15=y
197CONFIG_CPU_CP15_MMU=y
198
199#
200# Processor Features
201#
202CONFIG_ARM_THUMB=y
203# CONFIG_CPU_ICACHE_DISABLE is not set
204# CONFIG_CPU_DCACHE_DISABLE is not set
205# CONFIG_CPU_BPREDICT_DISABLE is not set
206# CONFIG_OUTER_CACHE is not set
207
208#
209# Bus support
210#
211# CONFIG_PCI_SYSCALL is not set
212# CONFIG_ARCH_SUPPORTS_MSI is not set
213# CONFIG_PCCARD is not set
214
215#
216# Kernel Features
217#
218CONFIG_TICK_ONESHOT=y
219CONFIG_NO_HZ=y
220CONFIG_HIGH_RES_TIMERS=y
221CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
222CONFIG_PREEMPT=y
223CONFIG_HZ=100
224CONFIG_AEABI=y
225# CONFIG_OABI_COMPAT is not set
226# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
227CONFIG_SELECT_MEMORY_MODEL=y
228CONFIG_FLATMEM_MANUAL=y
229# CONFIG_DISCONTIGMEM_MANUAL is not set
230# CONFIG_SPARSEMEM_MANUAL is not set
231CONFIG_FLATMEM=y
232CONFIG_FLAT_NODE_MEM_MAP=y
233# CONFIG_SPARSEMEM_STATIC is not set
234# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
235CONFIG_PAGEFLAGS_EXTENDED=y
236CONFIG_SPLIT_PTLOCK_CPUS=4
237# CONFIG_RESOURCES_64BIT is not set
238CONFIG_ZONE_DMA_FLAG=1
239CONFIG_BOUNCE=y
240CONFIG_VIRT_TO_BUS=y
241CONFIG_ALIGNMENT_TRAP=y
242
243#
244# Boot options
245#
246CONFIG_ZBOOT_ROM_TEXT=0x0
247CONFIG_ZBOOT_ROM_BSS=0x0
248CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off"
249# CONFIG_XIP_KERNEL is not set
250# CONFIG_KEXEC is not set
251
252#
253# Floating point emulation
254#
255
256#
257# At least one emulation must be selected
258#
259CONFIG_VFP=y
260
261#
262# Userspace binary formats
263#
264CONFIG_BINFMT_ELF=y
265# CONFIG_BINFMT_AOUT is not set
266# CONFIG_BINFMT_MISC is not set
267
268#
269# Power management options
270#
271# CONFIG_PM is not set
272CONFIG_ARCH_SUSPEND_POSSIBLE=y
273
274#
275# Networking
276#
277CONFIG_NET=y
278
279#
280# Networking options
281#
282CONFIG_PACKET=y
283# CONFIG_PACKET_MMAP is not set
284CONFIG_UNIX=y
285# CONFIG_NET_KEY is not set
286CONFIG_INET=y
287# CONFIG_IP_MULTICAST is not set
288# CONFIG_IP_ADVANCED_ROUTER is not set
289CONFIG_IP_FIB_HASH=y
290CONFIG_IP_PNP=y
291CONFIG_IP_PNP_DHCP=y
292# CONFIG_IP_PNP_BOOTP is not set
293# CONFIG_IP_PNP_RARP is not set
294# CONFIG_NET_IPIP is not set
295# CONFIG_NET_IPGRE is not set
296# CONFIG_ARPD is not set
297# CONFIG_SYN_COOKIES is not set
298# CONFIG_INET_AH is not set
299# CONFIG_INET_ESP is not set
300# CONFIG_INET_IPCOMP is not set
301# CONFIG_INET_XFRM_TUNNEL is not set
302# CONFIG_INET_TUNNEL is not set
303# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
304# CONFIG_INET_XFRM_MODE_TUNNEL is not set
305# CONFIG_INET_XFRM_MODE_BEET is not set
306# CONFIG_INET_LRO is not set
307# CONFIG_INET_DIAG is not set
308# CONFIG_TCP_CONG_ADVANCED is not set
309CONFIG_TCP_CONG_CUBIC=y
310CONFIG_DEFAULT_TCP_CONG="cubic"
311# CONFIG_TCP_MD5SIG is not set
312# CONFIG_IPV6 is not set
313# CONFIG_NETWORK_SECMARK is not set
314# CONFIG_NETFILTER is not set
315# CONFIG_IP_DCCP is not set
316# CONFIG_IP_SCTP is not set
317# CONFIG_TIPC is not set
318# CONFIG_ATM is not set
319# CONFIG_BRIDGE is not set
320# CONFIG_VLAN_8021Q is not set
321# CONFIG_DECNET is not set
322# CONFIG_LLC2 is not set
323# CONFIG_IPX is not set
324# CONFIG_ATALK is not set
325# CONFIG_X25 is not set
326# CONFIG_LAPB is not set
327# CONFIG_ECONET is not set
328# CONFIG_WAN_ROUTER is not set
329# CONFIG_NET_SCHED is not set
330
331#
332# Network testing
333#
334# CONFIG_NET_PKTGEN is not set
335# CONFIG_HAMRADIO is not set
336# CONFIG_CAN is not set
337# CONFIG_IRDA is not set
338# CONFIG_BT is not set
339# CONFIG_AF_RXRPC is not set
340
341#
342# Wireless
343#
344# CONFIG_CFG80211 is not set
345# CONFIG_WIRELESS_EXT is not set
346# CONFIG_MAC80211 is not set
347# CONFIG_IEEE80211 is not set
348# CONFIG_RFKILL is not set
349# CONFIG_NET_9P is not set
350
351#
352# Device Drivers
353#
354
355#
356# Generic Driver Options
357#
358CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
359CONFIG_STANDALONE=y
360CONFIG_PREVENT_FIRMWARE_BUILD=y
361CONFIG_FW_LOADER=m
362# CONFIG_SYS_HYPERVISOR is not set
363# CONFIG_CONNECTOR is not set
364CONFIG_MTD=y
365# CONFIG_MTD_DEBUG is not set
366# CONFIG_MTD_CONCAT is not set
367CONFIG_MTD_PARTITIONS=y
368# CONFIG_MTD_REDBOOT_PARTS is not set
369CONFIG_MTD_CMDLINE_PARTS=y
370# CONFIG_MTD_AFS_PARTS is not set
371# CONFIG_MTD_AR7_PARTS is not set
372
373#
374# User Modules And Translation Layers
375#
376CONFIG_MTD_CHAR=y
377CONFIG_MTD_BLKDEVS=y
378CONFIG_MTD_BLOCK=y
379# CONFIG_FTL is not set
380# CONFIG_NFTL is not set
381# CONFIG_INFTL is not set
382# CONFIG_RFD_FTL is not set
383# CONFIG_SSFDC is not set
384# CONFIG_MTD_OOPS is not set
385
386#
387# RAM/ROM/Flash chip drivers
388#
389CONFIG_MTD_CFI=y
390# CONFIG_MTD_JEDECPROBE is not set
391CONFIG_MTD_GEN_PROBE=y
392# CONFIG_MTD_CFI_ADV_OPTIONS is not set
393# CONFIG_MTD_CFI_NOSWAP is not set
394# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
395# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
396CONFIG_MTD_MAP_BANK_WIDTH_1=y
397CONFIG_MTD_MAP_BANK_WIDTH_2=y
398CONFIG_MTD_MAP_BANK_WIDTH_4=y
399# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
400# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
401# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
402CONFIG_MTD_CFI_I1=y
403CONFIG_MTD_CFI_I2=y
404# CONFIG_MTD_CFI_I4 is not set
405# CONFIG_MTD_CFI_I8 is not set
406# CONFIG_MTD_CFI_INTELEXT is not set
407# CONFIG_MTD_CFI_AMDSTD is not set
408# CONFIG_MTD_CFI_STAA is not set
409# CONFIG_MTD_RAM is not set
410# CONFIG_MTD_ROM is not set
411# CONFIG_MTD_ABSENT is not set
412
413#
414# Mapping drivers for chip access
415#
416# CONFIG_MTD_COMPLEX_MAPPINGS is not set
417CONFIG_MTD_PHYSMAP=y
418CONFIG_MTD_PHYSMAP_START=0x0
419CONFIG_MTD_PHYSMAP_LEN=0
420CONFIG_MTD_PHYSMAP_BANKWIDTH=2
421# CONFIG_MTD_ARM_INTEGRATOR is not set
422# CONFIG_MTD_PLATRAM is not set
423
424#
425# Self-contained MTD device drivers
426#
427# CONFIG_MTD_SLRAM is not set
428# CONFIG_MTD_PHRAM is not set
429# CONFIG_MTD_MTDRAM is not set
430# CONFIG_MTD_BLOCK2MTD is not set
431
432#
433# Disk-On-Chip Device Drivers
434#
435# CONFIG_MTD_DOC2000 is not set
436# CONFIG_MTD_DOC2001 is not set
437# CONFIG_MTD_DOC2001PLUS is not set
438# CONFIG_MTD_NAND is not set
439# CONFIG_MTD_ONENAND is not set
440
441#
442# UBI - Unsorted block images
443#
444# CONFIG_MTD_UBI is not set
445# CONFIG_PARPORT is not set
446# CONFIG_BLK_DEV is not set
447# CONFIG_MISC_DEVICES is not set
448CONFIG_HAVE_IDE=y
449# CONFIG_IDE is not set
450
451#
452# SCSI device support
453#
454# CONFIG_RAID_ATTRS is not set
455# CONFIG_SCSI is not set
456# CONFIG_SCSI_DMA is not set
457# CONFIG_SCSI_NETLINK is not set
458# CONFIG_ATA is not set
459# CONFIG_MD is not set
460CONFIG_NETDEVICES=y
461# CONFIG_NETDEVICES_MULTIQUEUE is not set
462# CONFIG_DUMMY is not set
463# CONFIG_BONDING is not set
464# CONFIG_MACVLAN is not set
465# CONFIG_EQUALIZER is not set
466# CONFIG_TUN is not set
467# CONFIG_VETH is not set
468# CONFIG_PHYLIB is not set
469CONFIG_NET_ETHERNET=y
470CONFIG_MII=y
471# CONFIG_AX88796 is not set
472CONFIG_SMC91X=y
473# CONFIG_DM9000 is not set
474# CONFIG_IBM_NEW_EMAC_ZMII is not set
475# CONFIG_IBM_NEW_EMAC_RGMII is not set
476# CONFIG_IBM_NEW_EMAC_TAH is not set
477# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
478# CONFIG_B44 is not set
479# CONFIG_NETDEV_1000 is not set
480# CONFIG_NETDEV_10000 is not set
481
482#
483# Wireless LAN
484#
485# CONFIG_WLAN_PRE80211 is not set
486# CONFIG_WLAN_80211 is not set
487# CONFIG_IWLWIFI_LEDS is not set
488# CONFIG_WAN is not set
489# CONFIG_PPP is not set
490# CONFIG_SLIP is not set
491# CONFIG_NETCONSOLE is not set
492# CONFIG_NETPOLL is not set
493# CONFIG_NET_POLL_CONTROLLER is not set
494# CONFIG_ISDN is not set
495
496#
497# Input device support
498#
499# CONFIG_INPUT is not set
500
501#
502# Hardware I/O ports
503#
504# CONFIG_SERIO is not set
505# CONFIG_GAMEPORT is not set
506
507#
508# Character devices
509#
510# CONFIG_VT is not set
511CONFIG_DEVKMEM=y
512# CONFIG_SERIAL_NONSTANDARD is not set
513
514#
515# Serial drivers
516#
517# CONFIG_SERIAL_8250 is not set
518
519#
520# Non-8250 serial port support
521#
522CONFIG_SERIAL_IMX=y
523CONFIG_SERIAL_IMX_CONSOLE=y
524CONFIG_SERIAL_CORE=y
525CONFIG_SERIAL_CORE_CONSOLE=y
526CONFIG_UNIX98_PTYS=y
527# CONFIG_LEGACY_PTYS is not set
528# CONFIG_IPMI_HANDLER is not set
529# CONFIG_HW_RANDOM is not set
530# CONFIG_NVRAM is not set
531# CONFIG_R3964 is not set
532# CONFIG_RAW_DRIVER is not set
533# CONFIG_TCG_TPM is not set
534# CONFIG_I2C is not set
535# CONFIG_SPI is not set
536CONFIG_HAVE_GPIO_LIB=y
537
538#
539# GPIO Support
540#
541
542#
543# I2C GPIO expanders:
544#
545
546#
547# SPI GPIO expanders:
548#
549# CONFIG_W1 is not set
550# CONFIG_POWER_SUPPLY is not set
551# CONFIG_HWMON is not set
552# CONFIG_WATCHDOG is not set
553
554#
555# Sonics Silicon Backplane
556#
557CONFIG_SSB_POSSIBLE=y
558# CONFIG_SSB is not set
559
560#
561# Multifunction device drivers
562#
563# CONFIG_MFD_SM501 is not set
564# CONFIG_MFD_ASIC3 is not set
565# CONFIG_HTC_EGPIO is not set
566# CONFIG_HTC_PASIC3 is not set
567
568#
569# Multimedia devices
570#
571
572#
573# Multimedia core support
574#
575# CONFIG_VIDEO_DEV is not set
576# CONFIG_DVB_CORE is not set
577# CONFIG_VIDEO_MEDIA is not set
578
579#
580# Multimedia drivers
581#
582# CONFIG_DAB is not set
583
584#
585# Graphics support
586#
587# CONFIG_VGASTATE is not set
588# CONFIG_VIDEO_OUTPUT_CONTROL is not set
589# CONFIG_FB is not set
590# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
591
592#
593# Display device support
594#
595# CONFIG_DISPLAY_SUPPORT is not set
596
597#
598# Sound
599#
600# CONFIG_SOUND is not set
601# CONFIG_USB_SUPPORT is not set
602# CONFIG_MMC is not set
603# CONFIG_NEW_LEDS is not set
604CONFIG_RTC_LIB=y
605# CONFIG_RTC_CLASS is not set
606# CONFIG_UIO is not set
607
608#
609# File systems
610#
611# CONFIG_EXT2_FS is not set
612# CONFIG_EXT3_FS is not set
613# CONFIG_EXT4DEV_FS is not set
614# CONFIG_REISERFS_FS is not set
615# CONFIG_JFS_FS is not set
616# CONFIG_FS_POSIX_ACL is not set
617# CONFIG_XFS_FS is not set
618# CONFIG_OCFS2_FS is not set
619# CONFIG_DNOTIFY is not set
620CONFIG_INOTIFY=y
621CONFIG_INOTIFY_USER=y
622# CONFIG_QUOTA is not set
623# CONFIG_AUTOFS_FS is not set
624# CONFIG_AUTOFS4_FS is not set
625# CONFIG_FUSE_FS is not set
626
627#
628# CD-ROM/DVD Filesystems
629#
630# CONFIG_ISO9660_FS is not set
631# CONFIG_UDF_FS is not set
632
633#
634# DOS/FAT/NT Filesystems
635#
636# CONFIG_MSDOS_FS is not set
637# CONFIG_VFAT_FS is not set
638# CONFIG_NTFS_FS is not set
639
640#
641# Pseudo filesystems
642#
643CONFIG_PROC_FS=y
644CONFIG_PROC_SYSCTL=y
645CONFIG_SYSFS=y
646CONFIG_TMPFS=y
647# CONFIG_TMPFS_POSIX_ACL is not set
648# CONFIG_HUGETLB_PAGE is not set
649# CONFIG_CONFIGFS_FS is not set
650
651#
652# Miscellaneous filesystems
653#
654# CONFIG_ADFS_FS is not set
655# CONFIG_AFFS_FS is not set
656# CONFIG_HFS_FS is not set
657# CONFIG_HFSPLUS_FS is not set
658# CONFIG_BEFS_FS is not set
659# CONFIG_BFS_FS is not set
660# CONFIG_EFS_FS is not set
661CONFIG_JFFS2_FS=y
662CONFIG_JFFS2_FS_DEBUG=0
663CONFIG_JFFS2_FS_WRITEBUFFER=y
664# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
665# CONFIG_JFFS2_SUMMARY is not set
666# CONFIG_JFFS2_FS_XATTR is not set
667# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
668CONFIG_JFFS2_ZLIB=y
669# CONFIG_JFFS2_LZO is not set
670CONFIG_JFFS2_RTIME=y
671# CONFIG_JFFS2_RUBIN is not set
672# CONFIG_CRAMFS is not set
673# CONFIG_VXFS_FS is not set
674# CONFIG_MINIX_FS is not set
675# CONFIG_HPFS_FS is not set
676# CONFIG_QNX4FS_FS is not set
677# CONFIG_ROMFS_FS is not set
678# CONFIG_SYSV_FS is not set
679# CONFIG_UFS_FS is not set
680CONFIG_NETWORK_FILESYSTEMS=y
681CONFIG_NFS_FS=y
682# CONFIG_NFS_V3 is not set
683# CONFIG_NFS_V4 is not set
684# CONFIG_NFSD is not set
685CONFIG_ROOT_NFS=y
686CONFIG_LOCKD=y
687CONFIG_NFS_COMMON=y
688CONFIG_SUNRPC=y
689# CONFIG_SUNRPC_BIND34 is not set
690# CONFIG_RPCSEC_GSS_KRB5 is not set
691# CONFIG_RPCSEC_GSS_SPKM3 is not set
692# CONFIG_SMB_FS is not set
693# CONFIG_CIFS is not set
694# CONFIG_NCP_FS is not set
695# CONFIG_CODA_FS is not set
696# CONFIG_AFS_FS is not set
697
698#
699# Partition Types
700#
701# CONFIG_PARTITION_ADVANCED is not set
702CONFIG_MSDOS_PARTITION=y
703# CONFIG_NLS is not set
704# CONFIG_DLM is not set
705
706#
707# Kernel hacking
708#
709# CONFIG_PRINTK_TIME is not set
710# CONFIG_ENABLE_WARN_DEPRECATED is not set
711# CONFIG_ENABLE_MUST_CHECK is not set
712CONFIG_FRAME_WARN=1024
713# CONFIG_MAGIC_SYSRQ is not set
714# CONFIG_UNUSED_SYMBOLS is not set
715# CONFIG_DEBUG_FS is not set
716# CONFIG_HEADERS_CHECK is not set
717# CONFIG_DEBUG_KERNEL is not set
718# CONFIG_DEBUG_BUGVERBOSE is not set
719CONFIG_FRAME_POINTER=y
720# CONFIG_SAMPLES is not set
721# CONFIG_DEBUG_USER is not set
722
723#
724# Security options
725#
726# CONFIG_KEYS is not set
727# CONFIG_SECURITY is not set
728# CONFIG_SECURITY_FILE_CAPABILITIES is not set
729# CONFIG_CRYPTO is not set
730
731#
732# Library routines
733#
734CONFIG_BITREVERSE=y
735# CONFIG_GENERIC_FIND_FIRST_BIT is not set
736# CONFIG_GENERIC_FIND_NEXT_BIT is not set
737# CONFIG_CRC_CCITT is not set
738# CONFIG_CRC16 is not set
739# CONFIG_CRC_ITU_T is not set
740CONFIG_CRC32=y
741# CONFIG_CRC7 is not set
742# CONFIG_LIBCRC32C is not set
743CONFIG_ZLIB_INFLATE=y
744CONFIG_ZLIB_DEFLATE=y
745CONFIG_PLIST=y
746CONFIG_HAS_IOMEM=y
747CONFIG_HAS_IOPORT=y
748CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/pcm038_defconfig b/arch/arm/configs/pcm038_defconfig
new file mode 100644
index 000000000000..6b798c215ca8
--- /dev/null
+++ b/arch/arm/configs/pcm038_defconfig
@@ -0,0 +1,1008 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc6
4# Fri Jun 20 16:38:36 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ARCH_SUPPORTS_AOUT=y
25CONFIG_ZONE_DMA=y
26CONFIG_ARCH_MTD_XIP=y
27CONFIG_VECTORS_BASE=0xffff0000
28CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
29
30#
31# General setup
32#
33CONFIG_EXPERIMENTAL=y
34CONFIG_BROKEN_ON_SMP=y
35CONFIG_LOCK_KERNEL=y
36CONFIG_INIT_ENV_ARG_LIMIT=32
37CONFIG_LOCALVERSION=""
38CONFIG_LOCALVERSION_AUTO=y
39# CONFIG_SWAP is not set
40CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y
42CONFIG_POSIX_MQUEUE=y
43# CONFIG_BSD_PROCESS_ACCT is not set
44# CONFIG_TASKSTATS is not set
45# CONFIG_AUDIT is not set
46# CONFIG_IKCONFIG is not set
47CONFIG_LOG_BUF_SHIFT=14
48# CONFIG_CGROUPS is not set
49CONFIG_GROUP_SCHED=y
50CONFIG_FAIR_GROUP_SCHED=y
51CONFIG_RT_GROUP_SCHED=y
52CONFIG_USER_SCHED=y
53# CONFIG_CGROUP_SCHED is not set
54# CONFIG_SYSFS_DEPRECATED_V2 is not set
55# CONFIG_RELAY is not set
56# CONFIG_NAMESPACES is not set
57# CONFIG_BLK_DEV_INITRD is not set
58# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
59CONFIG_SYSCTL=y
60CONFIG_EMBEDDED=y
61CONFIG_UID16=y
62CONFIG_SYSCTL_SYSCALL=y
63CONFIG_SYSCTL_SYSCALL_CHECK=y
64CONFIG_KALLSYMS=y
65CONFIG_KALLSYMS_EXTRA_PASS=y
66CONFIG_HOTPLUG=y
67CONFIG_PRINTK=y
68CONFIG_BUG=y
69CONFIG_ELF_CORE=y
70# CONFIG_COMPAT_BRK is not set
71CONFIG_BASE_FULL=y
72CONFIG_FUTEX=y
73CONFIG_ANON_INODES=y
74CONFIG_EPOLL=y
75CONFIG_SIGNALFD=y
76CONFIG_TIMERFD=y
77CONFIG_EVENTFD=y
78CONFIG_SHMEM=y
79CONFIG_VM_EVENT_COUNTERS=y
80CONFIG_SLAB=y
81# CONFIG_SLUB is not set
82# CONFIG_SLOB is not set
83CONFIG_PROFILING=y
84CONFIG_MARKERS=y
85CONFIG_OPROFILE=y
86CONFIG_HAVE_OPROFILE=y
87CONFIG_KPROBES=y
88CONFIG_KRETPROBES=y
89CONFIG_HAVE_KPROBES=y
90CONFIG_HAVE_KRETPROBES=y
91# CONFIG_HAVE_DMA_ATTRS is not set
92# CONFIG_PROC_PAGE_MONITOR is not set
93CONFIG_SLABINFO=y
94CONFIG_RT_MUTEXES=y
95# CONFIG_TINY_SHMEM is not set
96CONFIG_BASE_SMALL=0
97CONFIG_MODULES=y
98# CONFIG_MODULE_FORCE_LOAD is not set
99CONFIG_MODULE_UNLOAD=y
100# CONFIG_MODULE_FORCE_UNLOAD is not set
101# CONFIG_MODVERSIONS is not set
102# CONFIG_MODULE_SRCVERSION_ALL is not set
103# CONFIG_KMOD is not set
104CONFIG_BLOCK=y
105# CONFIG_LBD is not set
106# CONFIG_BLK_DEV_IO_TRACE is not set
107# CONFIG_LSF is not set
108# CONFIG_BLK_DEV_BSG is not set
109
110#
111# IO Schedulers
112#
113CONFIG_IOSCHED_NOOP=y
114# CONFIG_IOSCHED_AS is not set
115# CONFIG_IOSCHED_DEADLINE is not set
116# CONFIG_IOSCHED_CFQ is not set
117# CONFIG_DEFAULT_AS is not set
118# CONFIG_DEFAULT_DEADLINE is not set
119# CONFIG_DEFAULT_CFQ is not set
120CONFIG_DEFAULT_NOOP=y
121CONFIG_DEFAULT_IOSCHED="noop"
122CONFIG_CLASSIC_RCU=y
123
124#
125# System Type
126#
127# CONFIG_ARCH_AAEC2000 is not set
128# CONFIG_ARCH_INTEGRATOR is not set
129# CONFIG_ARCH_REALVIEW is not set
130# CONFIG_ARCH_VERSATILE is not set
131# CONFIG_ARCH_AT91 is not set
132# CONFIG_ARCH_CLPS7500 is not set
133# CONFIG_ARCH_CLPS711X is not set
134# CONFIG_ARCH_CO285 is not set
135# CONFIG_ARCH_EBSA110 is not set
136# CONFIG_ARCH_EP93XX is not set
137# CONFIG_ARCH_FOOTBRIDGE is not set
138# CONFIG_ARCH_NETX is not set
139# CONFIG_ARCH_H720X is not set
140# CONFIG_ARCH_IMX is not set
141# CONFIG_ARCH_IOP13XX is not set
142# CONFIG_ARCH_IOP32X is not set
143# CONFIG_ARCH_IOP33X is not set
144# CONFIG_ARCH_IXP23XX is not set
145# CONFIG_ARCH_IXP2000 is not set
146# CONFIG_ARCH_IXP4XX is not set
147# CONFIG_ARCH_L7200 is not set
148# CONFIG_ARCH_KS8695 is not set
149# CONFIG_ARCH_NS9XXX is not set
150CONFIG_ARCH_MXC=y
151# CONFIG_ARCH_ORION5X is not set
152# CONFIG_ARCH_PNX4008 is not set
153# CONFIG_ARCH_PXA is not set
154# CONFIG_ARCH_RPC is not set
155# CONFIG_ARCH_SA1100 is not set
156# CONFIG_ARCH_S3C2410 is not set
157# CONFIG_ARCH_SHARK is not set
158# CONFIG_ARCH_LH7A40X is not set
159# CONFIG_ARCH_DAVINCI is not set
160# CONFIG_ARCH_OMAP is not set
161# CONFIG_ARCH_MSM7X00A is not set
162
163#
164# Boot options
165#
166
167#
168# Power management
169#
170
171#
172# Freescale MXC Implementations
173#
174CONFIG_ARCH_MX2=y
175# CONFIG_ARCH_MX3 is not set
176
177#
178# MX2 family CPU support
179#
180CONFIG_MACH_MX27=y
181
182#
183# MX2 Platforms
184#
185# CONFIG_MACH_MX27ADS is not set
186CONFIG_MACH_PCM038=y
187CONFIG_MACH_PCM970_BASEBOARD=y
188
189#
190# Processor Type
191#
192CONFIG_CPU_32=y
193CONFIG_CPU_ARM926T=y
194CONFIG_CPU_32v5=y
195CONFIG_CPU_ABRT_EV5TJ=y
196CONFIG_CPU_PABRT_NOIFAR=y
197CONFIG_CPU_CACHE_VIVT=y
198CONFIG_CPU_COPY_V4WB=y
199CONFIG_CPU_TLB_V4WBI=y
200CONFIG_CPU_CP15=y
201CONFIG_CPU_CP15_MMU=y
202
203#
204# Processor Features
205#
206CONFIG_ARM_THUMB=y
207# CONFIG_CPU_ICACHE_DISABLE is not set
208# CONFIG_CPU_DCACHE_DISABLE is not set
209# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
210# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
211# CONFIG_OUTER_CACHE is not set
212
213#
214# Bus support
215#
216# CONFIG_PCI_SYSCALL is not set
217# CONFIG_ARCH_SUPPORTS_MSI is not set
218# CONFIG_PCCARD is not set
219
220#
221# Kernel Features
222#
223CONFIG_TICK_ONESHOT=y
224CONFIG_NO_HZ=y
225CONFIG_HIGH_RES_TIMERS=y
226CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
227CONFIG_PREEMPT=y
228CONFIG_HZ=100
229CONFIG_AEABI=y
230# CONFIG_OABI_COMPAT is not set
231# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
232CONFIG_SELECT_MEMORY_MODEL=y
233CONFIG_FLATMEM_MANUAL=y
234# CONFIG_DISCONTIGMEM_MANUAL is not set
235# CONFIG_SPARSEMEM_MANUAL is not set
236CONFIG_FLATMEM=y
237CONFIG_FLAT_NODE_MEM_MAP=y
238# CONFIG_SPARSEMEM_STATIC is not set
239# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
240CONFIG_PAGEFLAGS_EXTENDED=y
241CONFIG_SPLIT_PTLOCK_CPUS=4096
242# CONFIG_RESOURCES_64BIT is not set
243CONFIG_ZONE_DMA_FLAG=1
244CONFIG_BOUNCE=y
245CONFIG_VIRT_TO_BUS=y
246CONFIG_ALIGNMENT_TRAP=y
247
248#
249# Boot options
250#
251CONFIG_ZBOOT_ROM_TEXT=0x0
252CONFIG_ZBOOT_ROM_BSS=0x0
253CONFIG_CMDLINE=""
254# CONFIG_XIP_KERNEL is not set
255# CONFIG_KEXEC is not set
256
257#
258# Floating point emulation
259#
260
261#
262# At least one emulation must be selected
263#
264# CONFIG_VFP is not set
265
266#
267# Userspace binary formats
268#
269CONFIG_BINFMT_ELF=y
270# CONFIG_BINFMT_AOUT is not set
271# CONFIG_BINFMT_MISC is not set
272
273#
274# Power management options
275#
276# CONFIG_PM is not set
277CONFIG_ARCH_SUSPEND_POSSIBLE=y
278
279#
280# Networking
281#
282CONFIG_NET=y
283
284#
285# Networking options
286#
287CONFIG_PACKET=y
288CONFIG_PACKET_MMAP=y
289CONFIG_UNIX=y
290# CONFIG_NET_KEY is not set
291CONFIG_INET=y
292CONFIG_IP_MULTICAST=y
293# CONFIG_IP_ADVANCED_ROUTER is not set
294CONFIG_IP_FIB_HASH=y
295CONFIG_IP_PNP=y
296# CONFIG_IP_PNP_DHCP is not set
297# CONFIG_IP_PNP_BOOTP is not set
298# CONFIG_IP_PNP_RARP is not set
299# CONFIG_NET_IPIP is not set
300# CONFIG_NET_IPGRE is not set
301# CONFIG_IP_MROUTE is not set
302# CONFIG_ARPD is not set
303# CONFIG_SYN_COOKIES is not set
304# CONFIG_INET_AH is not set
305# CONFIG_INET_ESP is not set
306# CONFIG_INET_IPCOMP is not set
307# CONFIG_INET_XFRM_TUNNEL is not set
308# CONFIG_INET_TUNNEL is not set
309# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
310# CONFIG_INET_XFRM_MODE_TUNNEL is not set
311# CONFIG_INET_XFRM_MODE_BEET is not set
312# CONFIG_INET_LRO is not set
313# CONFIG_INET_DIAG is not set
314# CONFIG_TCP_CONG_ADVANCED is not set
315CONFIG_TCP_CONG_CUBIC=y
316CONFIG_DEFAULT_TCP_CONG="cubic"
317# CONFIG_TCP_MD5SIG is not set
318# CONFIG_IPV6 is not set
319# CONFIG_NETWORK_SECMARK is not set
320# CONFIG_NETFILTER is not set
321# CONFIG_IP_DCCP is not set
322# CONFIG_IP_SCTP is not set
323# CONFIG_TIPC is not set
324# CONFIG_ATM is not set
325# CONFIG_BRIDGE is not set
326# CONFIG_VLAN_8021Q is not set
327# CONFIG_DECNET is not set
328# CONFIG_LLC2 is not set
329# CONFIG_IPX is not set
330# CONFIG_ATALK is not set
331# CONFIG_X25 is not set
332# CONFIG_LAPB is not set
333# CONFIG_ECONET is not set
334# CONFIG_WAN_ROUTER is not set
335# CONFIG_NET_SCHED is not set
336
337#
338# Network testing
339#
340# CONFIG_NET_PKTGEN is not set
341# CONFIG_NET_TCPPROBE is not set
342# CONFIG_HAMRADIO is not set
343# CONFIG_CAN is not set
344# CONFIG_IRDA is not set
345# CONFIG_BT is not set
346# CONFIG_AF_RXRPC is not set
347
348#
349# Wireless
350#
351# CONFIG_CFG80211 is not set
352# CONFIG_WIRELESS_EXT is not set
353# CONFIG_MAC80211 is not set
354# CONFIG_IEEE80211 is not set
355# CONFIG_RFKILL is not set
356# CONFIG_NET_9P is not set
357
358#
359# Device Drivers
360#
361
362#
363# Generic Driver Options
364#
365CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
366CONFIG_STANDALONE=y
367CONFIG_PREVENT_FIRMWARE_BUILD=y
368CONFIG_FW_LOADER=y
369# CONFIG_SYS_HYPERVISOR is not set
370# CONFIG_CONNECTOR is not set
371CONFIG_MTD=y
372# CONFIG_MTD_DEBUG is not set
373# CONFIG_MTD_CONCAT is not set
374CONFIG_MTD_PARTITIONS=y
375# CONFIG_MTD_REDBOOT_PARTS is not set
376CONFIG_MTD_CMDLINE_PARTS=y
377# CONFIG_MTD_AFS_PARTS is not set
378# CONFIG_MTD_AR7_PARTS is not set
379
380#
381# User Modules And Translation Layers
382#
383CONFIG_MTD_CHAR=y
384CONFIG_MTD_BLKDEVS=y
385CONFIG_MTD_BLOCK=y
386# CONFIG_FTL is not set
387# CONFIG_NFTL is not set
388# CONFIG_INFTL is not set
389# CONFIG_RFD_FTL is not set
390# CONFIG_SSFDC is not set
391# CONFIG_MTD_OOPS is not set
392
393#
394# RAM/ROM/Flash chip drivers
395#
396CONFIG_MTD_CFI=y
397# CONFIG_MTD_JEDECPROBE is not set
398CONFIG_MTD_GEN_PROBE=y
399CONFIG_MTD_CFI_ADV_OPTIONS=y
400CONFIG_MTD_CFI_NOSWAP=y
401# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
402# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
403CONFIG_MTD_CFI_GEOMETRY=y
404# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
405CONFIG_MTD_MAP_BANK_WIDTH_2=y
406# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
407# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
408# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
409# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
410CONFIG_MTD_CFI_I1=y
411# CONFIG_MTD_CFI_I2 is not set
412# CONFIG_MTD_CFI_I4 is not set
413# CONFIG_MTD_CFI_I8 is not set
414# CONFIG_MTD_OTP is not set
415CONFIG_MTD_CFI_INTELEXT=y
416# CONFIG_MTD_CFI_AMDSTD is not set
417# CONFIG_MTD_CFI_STAA is not set
418CONFIG_MTD_CFI_UTIL=y
419# CONFIG_MTD_RAM is not set
420# CONFIG_MTD_ROM is not set
421# CONFIG_MTD_ABSENT is not set
422# CONFIG_MTD_XIP is not set
423
424#
425# Mapping drivers for chip access
426#
427# CONFIG_MTD_COMPLEX_MAPPINGS is not set
428CONFIG_MTD_PHYSMAP=y
429CONFIG_MTD_PHYSMAP_START=0x00000000
430CONFIG_MTD_PHYSMAP_LEN=0x0
431CONFIG_MTD_PHYSMAP_BANKWIDTH=2
432# CONFIG_MTD_ARM_INTEGRATOR is not set
433# CONFIG_MTD_PLATRAM is not set
434
435#
436# Self-contained MTD device drivers
437#
438# CONFIG_MTD_DATAFLASH is not set
439# CONFIG_MTD_M25P80 is not set
440# CONFIG_MTD_SLRAM is not set
441# CONFIG_MTD_PHRAM is not set
442# CONFIG_MTD_MTDRAM is not set
443# CONFIG_MTD_BLOCK2MTD is not set
444
445#
446# Disk-On-Chip Device Drivers
447#
448# CONFIG_MTD_DOC2000 is not set
449# CONFIG_MTD_DOC2001 is not set
450# CONFIG_MTD_DOC2001PLUS is not set
451# CONFIG_MTD_NAND is not set
452# CONFIG_MTD_ONENAND is not set
453
454#
455# UBI - Unsorted block images
456#
457# CONFIG_MTD_UBI is not set
458# CONFIG_PARPORT is not set
459CONFIG_BLK_DEV=y
460# CONFIG_BLK_DEV_COW_COMMON is not set
461# CONFIG_BLK_DEV_LOOP is not set
462# CONFIG_BLK_DEV_NBD is not set
463# CONFIG_BLK_DEV_RAM is not set
464# CONFIG_CDROM_PKTCDVD is not set
465# CONFIG_ATA_OVER_ETH is not set
466# CONFIG_MISC_DEVICES is not set
467CONFIG_HAVE_IDE=y
468# CONFIG_IDE is not set
469
470#
471# SCSI device support
472#
473# CONFIG_RAID_ATTRS is not set
474# CONFIG_SCSI is not set
475# CONFIG_SCSI_DMA is not set
476# CONFIG_SCSI_NETLINK is not set
477# CONFIG_ATA is not set
478# CONFIG_MD is not set
479CONFIG_NETDEVICES=y
480# CONFIG_NETDEVICES_MULTIQUEUE is not set
481# CONFIG_DUMMY is not set
482# CONFIG_BONDING is not set
483# CONFIG_MACVLAN is not set
484# CONFIG_EQUALIZER is not set
485# CONFIG_TUN is not set
486# CONFIG_VETH is not set
487# CONFIG_PHYLIB is not set
488CONFIG_NET_ETHERNET=y
489# CONFIG_MII is not set
490# CONFIG_AX88796 is not set
491# CONFIG_SMC91X is not set
492# CONFIG_DM9000 is not set
493# CONFIG_ENC28J60 is not set
494# CONFIG_IBM_NEW_EMAC_ZMII is not set
495# CONFIG_IBM_NEW_EMAC_RGMII is not set
496# CONFIG_IBM_NEW_EMAC_TAH is not set
497# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
498# CONFIG_B44 is not set
499CONFIG_FEC_OLD=y
500# CONFIG_NETDEV_1000 is not set
501# CONFIG_NETDEV_10000 is not set
502
503#
504# Wireless LAN
505#
506# CONFIG_WLAN_PRE80211 is not set
507# CONFIG_WLAN_80211 is not set
508# CONFIG_IWLWIFI_LEDS is not set
509# CONFIG_WAN is not set
510# CONFIG_PPP is not set
511# CONFIG_SLIP is not set
512# CONFIG_NETCONSOLE is not set
513# CONFIG_NETPOLL is not set
514# CONFIG_NET_POLL_CONTROLLER is not set
515# CONFIG_ISDN is not set
516
517#
518# Input device support
519#
520CONFIG_INPUT=y
521# CONFIG_INPUT_FF_MEMLESS is not set
522# CONFIG_INPUT_POLLDEV is not set
523
524#
525# Userland interfaces
526#
527# CONFIG_INPUT_MOUSEDEV is not set
528# CONFIG_INPUT_JOYDEV is not set
529CONFIG_INPUT_EVDEV=y
530# CONFIG_INPUT_EVBUG is not set
531
532#
533# Input Device Drivers
534#
535# CONFIG_INPUT_KEYBOARD is not set
536# CONFIG_INPUT_MOUSE is not set
537# CONFIG_INPUT_JOYSTICK is not set
538# CONFIG_INPUT_TABLET is not set
539CONFIG_INPUT_TOUCHSCREEN=y
540# CONFIG_TOUCHSCREEN_ADS7846 is not set
541# CONFIG_TOUCHSCREEN_FUJITSU is not set
542# CONFIG_TOUCHSCREEN_GUNZE is not set
543# CONFIG_TOUCHSCREEN_ELO is not set
544# CONFIG_TOUCHSCREEN_MTOUCH is not set
545# CONFIG_TOUCHSCREEN_MK712 is not set
546# CONFIG_TOUCHSCREEN_PENMOUNT is not set
547# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
548# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
549# CONFIG_TOUCHSCREEN_UCB1400 is not set
550# CONFIG_INPUT_MISC is not set
551
552#
553# Hardware I/O ports
554#
555# CONFIG_SERIO is not set
556# CONFIG_GAMEPORT is not set
557
558#
559# Character devices
560#
561CONFIG_VT=y
562CONFIG_VT_CONSOLE=y
563CONFIG_HW_CONSOLE=y
564# CONFIG_VT_HW_CONSOLE_BINDING is not set
565CONFIG_DEVKMEM=y
566# CONFIG_SERIAL_NONSTANDARD is not set
567
568#
569# Serial drivers
570#
571# CONFIG_SERIAL_8250 is not set
572
573#
574# Non-8250 serial port support
575#
576CONFIG_SERIAL_IMX=y
577CONFIG_SERIAL_IMX_CONSOLE=y
578CONFIG_SERIAL_CORE=y
579CONFIG_SERIAL_CORE_CONSOLE=y
580CONFIG_UNIX98_PTYS=y
581# CONFIG_LEGACY_PTYS is not set
582# CONFIG_IPMI_HANDLER is not set
583# CONFIG_HW_RANDOM is not set
584# CONFIG_NVRAM is not set
585# CONFIG_R3964 is not set
586# CONFIG_RAW_DRIVER is not set
587# CONFIG_TCG_TPM is not set
588CONFIG_I2C=y
589CONFIG_I2C_BOARDINFO=y
590# CONFIG_I2C_CHARDEV is not set
591
592#
593# I2C Hardware Bus support
594#
595# CONFIG_I2C_GPIO is not set
596# CONFIG_I2C_OCORES is not set
597# CONFIG_I2C_PARPORT_LIGHT is not set
598# CONFIG_I2C_SIMTEC is not set
599# CONFIG_I2C_TAOS_EVM is not set
600# CONFIG_I2C_STUB is not set
601# CONFIG_I2C_PCA_PLATFORM is not set
602
603#
604# Miscellaneous I2C Chip support
605#
606# CONFIG_DS1682 is not set
607# CONFIG_SENSORS_EEPROM is not set
608# CONFIG_SENSORS_PCF8574 is not set
609# CONFIG_PCF8575 is not set
610# CONFIG_SENSORS_PCF8591 is not set
611# CONFIG_TPS65010 is not set
612# CONFIG_SENSORS_MAX6875 is not set
613# CONFIG_SENSORS_TSL2550 is not set
614# CONFIG_I2C_DEBUG_CORE is not set
615# CONFIG_I2C_DEBUG_ALGO is not set
616# CONFIG_I2C_DEBUG_BUS is not set
617# CONFIG_I2C_DEBUG_CHIP is not set
618CONFIG_SPI=y
619CONFIG_SPI_MASTER=y
620
621#
622# SPI Master Controller Drivers
623#
624CONFIG_SPI_BITBANG=y
625
626#
627# SPI Protocol Masters
628#
629# CONFIG_SPI_AT25 is not set
630# CONFIG_SPI_SPIDEV is not set
631# CONFIG_SPI_TLE62X0 is not set
632CONFIG_HAVE_GPIO_LIB=y
633
634#
635# GPIO Support
636#
637
638#
639# I2C GPIO expanders:
640#
641# CONFIG_GPIO_PCA953X is not set
642# CONFIG_GPIO_PCF857X is not set
643
644#
645# SPI GPIO expanders:
646#
647# CONFIG_GPIO_MCP23S08 is not set
648# CONFIG_W1 is not set
649# CONFIG_POWER_SUPPLY is not set
650# CONFIG_HWMON is not set
651# CONFIG_WATCHDOG is not set
652
653#
654# Sonics Silicon Backplane
655#
656CONFIG_SSB_POSSIBLE=y
657# CONFIG_SSB is not set
658
659#
660# Multifunction device drivers
661#
662# CONFIG_MFD_SM501 is not set
663# CONFIG_MFD_ASIC3 is not set
664# CONFIG_HTC_EGPIO is not set
665# CONFIG_HTC_PASIC3 is not set
666
667#
668# Multimedia devices
669#
670
671#
672# Multimedia core support
673#
674CONFIG_VIDEO_DEV=y
675CONFIG_VIDEO_V4L2_COMMON=y
676CONFIG_VIDEO_ALLOW_V4L1=y
677CONFIG_VIDEO_V4L1_COMPAT=y
678# CONFIG_DVB_CORE is not set
679CONFIG_VIDEO_MEDIA=y
680
681#
682# Multimedia drivers
683#
684# CONFIG_MEDIA_ATTACH is not set
685CONFIG_MEDIA_TUNER=y
686# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
687CONFIG_MEDIA_TUNER_SIMPLE=y
688CONFIG_MEDIA_TUNER_TDA8290=y
689CONFIG_MEDIA_TUNER_TDA9887=y
690CONFIG_MEDIA_TUNER_TEA5761=y
691CONFIG_MEDIA_TUNER_TEA5767=y
692CONFIG_MEDIA_TUNER_MT20XX=y
693CONFIG_MEDIA_TUNER_XC2028=y
694CONFIG_MEDIA_TUNER_XC5000=y
695CONFIG_VIDEO_V4L2=y
696CONFIG_VIDEO_V4L1=y
697CONFIG_VIDEO_CAPTURE_DRIVERS=y
698# CONFIG_VIDEO_ADV_DEBUG is not set
699CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
700# CONFIG_VIDEO_VIVI is not set
701# CONFIG_VIDEO_CPIA is not set
702# CONFIG_VIDEO_SAA5246A is not set
703# CONFIG_VIDEO_SAA5249 is not set
704# CONFIG_TUNER_3036 is not set
705# CONFIG_SOC_CAMERA is not set
706# CONFIG_RADIO_ADAPTERS is not set
707# CONFIG_DAB is not set
708
709#
710# Graphics support
711#
712# CONFIG_VGASTATE is not set
713# CONFIG_VIDEO_OUTPUT_CONTROL is not set
714CONFIG_FB=y
715# CONFIG_FIRMWARE_EDID is not set
716# CONFIG_FB_DDC is not set
717# CONFIG_FB_CFB_FILLRECT is not set
718# CONFIG_FB_CFB_COPYAREA is not set
719# CONFIG_FB_CFB_IMAGEBLIT is not set
720# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
721# CONFIG_FB_SYS_FILLRECT is not set
722# CONFIG_FB_SYS_COPYAREA is not set
723# CONFIG_FB_SYS_IMAGEBLIT is not set
724# CONFIG_FB_FOREIGN_ENDIAN is not set
725# CONFIG_FB_SYS_FOPS is not set
726# CONFIG_FB_SVGALIB is not set
727# CONFIG_FB_MACMODES is not set
728# CONFIG_FB_BACKLIGHT is not set
729# CONFIG_FB_MODE_HELPERS is not set
730# CONFIG_FB_TILEBLITTING is not set
731
732#
733# Frame buffer hardware drivers
734#
735# CONFIG_FB_S1D13XXX is not set
736# CONFIG_FB_VIRTUAL is not set
737# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
738
739#
740# Display device support
741#
742# CONFIG_DISPLAY_SUPPORT is not set
743
744#
745# Console display driver support
746#
747# CONFIG_VGA_CONSOLE is not set
748CONFIG_DUMMY_CONSOLE=y
749CONFIG_FRAMEBUFFER_CONSOLE=y
750# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
751# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
752CONFIG_FONTS=y
753CONFIG_FONT_8x8=y
754# CONFIG_FONT_8x16 is not set
755# CONFIG_FONT_6x11 is not set
756# CONFIG_FONT_7x14 is not set
757# CONFIG_FONT_PEARL_8x8 is not set
758# CONFIG_FONT_ACORN_8x8 is not set
759# CONFIG_FONT_MINI_4x6 is not set
760# CONFIG_FONT_SUN8x16 is not set
761# CONFIG_FONT_SUN12x22 is not set
762# CONFIG_FONT_10x18 is not set
763# CONFIG_LOGO is not set
764
765#
766# Sound
767#
768# CONFIG_SOUND is not set
769# CONFIG_HID_SUPPORT is not set
770# CONFIG_USB_SUPPORT is not set
771# CONFIG_MMC is not set
772# CONFIG_NEW_LEDS is not set
773CONFIG_RTC_LIB=y
774CONFIG_RTC_CLASS=y
775CONFIG_RTC_HCTOSYS=y
776CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
777# CONFIG_RTC_DEBUG is not set
778
779#
780# RTC interfaces
781#
782CONFIG_RTC_INTF_SYSFS=y
783CONFIG_RTC_INTF_PROC=y
784CONFIG_RTC_INTF_DEV=y
785# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
786# CONFIG_RTC_DRV_TEST is not set
787
788#
789# I2C RTC drivers
790#
791# CONFIG_RTC_DRV_DS1307 is not set
792# CONFIG_RTC_DRV_DS1374 is not set
793# CONFIG_RTC_DRV_DS1672 is not set
794# CONFIG_RTC_DRV_MAX6900 is not set
795# CONFIG_RTC_DRV_RS5C372 is not set
796# CONFIG_RTC_DRV_ISL1208 is not set
797# CONFIG_RTC_DRV_X1205 is not set
798CONFIG_RTC_DRV_PCF8563=y
799# CONFIG_RTC_DRV_PCF8583 is not set
800# CONFIG_RTC_DRV_M41T80 is not set
801# CONFIG_RTC_DRV_S35390A is not set
802# CONFIG_RTC_DRV_FM3130 is not set
803
804#
805# SPI RTC drivers
806#
807# CONFIG_RTC_DRV_MAX6902 is not set
808# CONFIG_RTC_DRV_R9701 is not set
809# CONFIG_RTC_DRV_RS5C348 is not set
810
811#
812# Platform RTC drivers
813#
814# CONFIG_RTC_DRV_CMOS is not set
815# CONFIG_RTC_DRV_DS1511 is not set
816# CONFIG_RTC_DRV_DS1553 is not set
817# CONFIG_RTC_DRV_DS1742 is not set
818# CONFIG_RTC_DRV_STK17TA8 is not set
819# CONFIG_RTC_DRV_M48T86 is not set
820# CONFIG_RTC_DRV_M48T59 is not set
821# CONFIG_RTC_DRV_V3020 is not set
822
823#
824# on-CPU RTC drivers
825#
826# CONFIG_UIO is not set
827
828#
829# File systems
830#
831# CONFIG_EXT2_FS is not set
832# CONFIG_EXT3_FS is not set
833# CONFIG_EXT4DEV_FS is not set
834# CONFIG_REISERFS_FS is not set
835# CONFIG_JFS_FS is not set
836# CONFIG_FS_POSIX_ACL is not set
837# CONFIG_XFS_FS is not set
838# CONFIG_OCFS2_FS is not set
839# CONFIG_DNOTIFY is not set
840# CONFIG_INOTIFY is not set
841# CONFIG_QUOTA is not set
842# CONFIG_AUTOFS_FS is not set
843# CONFIG_AUTOFS4_FS is not set
844# CONFIG_FUSE_FS is not set
845
846#
847# CD-ROM/DVD Filesystems
848#
849# CONFIG_ISO9660_FS is not set
850# CONFIG_UDF_FS is not set
851
852#
853# DOS/FAT/NT Filesystems
854#
855# CONFIG_MSDOS_FS is not set
856# CONFIG_VFAT_FS is not set
857# CONFIG_NTFS_FS is not set
858
859#
860# Pseudo filesystems
861#
862CONFIG_PROC_FS=y
863CONFIG_PROC_SYSCTL=y
864CONFIG_SYSFS=y
865CONFIG_TMPFS=y
866# CONFIG_TMPFS_POSIX_ACL is not set
867# CONFIG_HUGETLB_PAGE is not set
868# CONFIG_CONFIGFS_FS is not set
869
870#
871# Miscellaneous filesystems
872#
873# CONFIG_ADFS_FS is not set
874# CONFIG_AFFS_FS is not set
875# CONFIG_HFS_FS is not set
876# CONFIG_HFSPLUS_FS is not set
877# CONFIG_BEFS_FS is not set
878# CONFIG_BFS_FS is not set
879# CONFIG_EFS_FS is not set
880CONFIG_JFFS2_FS=y
881CONFIG_JFFS2_FS_DEBUG=0
882CONFIG_JFFS2_FS_WRITEBUFFER=y
883# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
884# CONFIG_JFFS2_SUMMARY is not set
885# CONFIG_JFFS2_FS_XATTR is not set
886# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
887CONFIG_JFFS2_ZLIB=y
888# CONFIG_JFFS2_LZO is not set
889CONFIG_JFFS2_RTIME=y
890# CONFIG_JFFS2_RUBIN is not set
891# CONFIG_CRAMFS is not set
892# CONFIG_VXFS_FS is not set
893# CONFIG_MINIX_FS is not set
894# CONFIG_HPFS_FS is not set
895# CONFIG_QNX4FS_FS is not set
896# CONFIG_ROMFS_FS is not set
897# CONFIG_SYSV_FS is not set
898# CONFIG_UFS_FS is not set
899CONFIG_NETWORK_FILESYSTEMS=y
900CONFIG_NFS_FS=y
901CONFIG_NFS_V3=y
902# CONFIG_NFS_V3_ACL is not set
903# CONFIG_NFS_V4 is not set
904# CONFIG_NFSD is not set
905CONFIG_ROOT_NFS=y
906CONFIG_LOCKD=y
907CONFIG_LOCKD_V4=y
908CONFIG_NFS_COMMON=y
909CONFIG_SUNRPC=y
910# CONFIG_SUNRPC_BIND34 is not set
911# CONFIG_RPCSEC_GSS_KRB5 is not set
912# CONFIG_RPCSEC_GSS_SPKM3 is not set
913# CONFIG_SMB_FS is not set
914# CONFIG_CIFS is not set
915# CONFIG_NCP_FS is not set
916# CONFIG_CODA_FS is not set
917# CONFIG_AFS_FS is not set
918
919#
920# Partition Types
921#
922# CONFIG_PARTITION_ADVANCED is not set
923CONFIG_MSDOS_PARTITION=y
924CONFIG_NLS=y
925CONFIG_NLS_DEFAULT="iso8859-1"
926CONFIG_NLS_CODEPAGE_437=m
927# CONFIG_NLS_CODEPAGE_737 is not set
928# CONFIG_NLS_CODEPAGE_775 is not set
929CONFIG_NLS_CODEPAGE_850=m
930# CONFIG_NLS_CODEPAGE_852 is not set
931# CONFIG_NLS_CODEPAGE_855 is not set
932# CONFIG_NLS_CODEPAGE_857 is not set
933# CONFIG_NLS_CODEPAGE_860 is not set
934# CONFIG_NLS_CODEPAGE_861 is not set
935# CONFIG_NLS_CODEPAGE_862 is not set
936# CONFIG_NLS_CODEPAGE_863 is not set
937# CONFIG_NLS_CODEPAGE_864 is not set
938# CONFIG_NLS_CODEPAGE_865 is not set
939# CONFIG_NLS_CODEPAGE_866 is not set
940# CONFIG_NLS_CODEPAGE_869 is not set
941# CONFIG_NLS_CODEPAGE_936 is not set
942# CONFIG_NLS_CODEPAGE_950 is not set
943# CONFIG_NLS_CODEPAGE_932 is not set
944# CONFIG_NLS_CODEPAGE_949 is not set
945# CONFIG_NLS_CODEPAGE_874 is not set
946# CONFIG_NLS_ISO8859_8 is not set
947# CONFIG_NLS_CODEPAGE_1250 is not set
948# CONFIG_NLS_CODEPAGE_1251 is not set
949# CONFIG_NLS_ASCII is not set
950CONFIG_NLS_ISO8859_1=y
951# CONFIG_NLS_ISO8859_2 is not set
952# CONFIG_NLS_ISO8859_3 is not set
953# CONFIG_NLS_ISO8859_4 is not set
954# CONFIG_NLS_ISO8859_5 is not set
955# CONFIG_NLS_ISO8859_6 is not set
956# CONFIG_NLS_ISO8859_7 is not set
957# CONFIG_NLS_ISO8859_9 is not set
958# CONFIG_NLS_ISO8859_13 is not set
959# CONFIG_NLS_ISO8859_14 is not set
960CONFIG_NLS_ISO8859_15=m
961# CONFIG_NLS_KOI8_R is not set
962# CONFIG_NLS_KOI8_U is not set
963# CONFIG_NLS_UTF8 is not set
964# CONFIG_DLM is not set
965
966#
967# Kernel hacking
968#
969# CONFIG_PRINTK_TIME is not set
970CONFIG_ENABLE_WARN_DEPRECATED=y
971CONFIG_ENABLE_MUST_CHECK=y
972CONFIG_FRAME_WARN=1024
973# CONFIG_MAGIC_SYSRQ is not set
974# CONFIG_UNUSED_SYMBOLS is not set
975# CONFIG_DEBUG_FS is not set
976# CONFIG_HEADERS_CHECK is not set
977# CONFIG_DEBUG_KERNEL is not set
978# CONFIG_DEBUG_BUGVERBOSE is not set
979CONFIG_FRAME_POINTER=y
980# CONFIG_SAMPLES is not set
981# CONFIG_DEBUG_USER is not set
982
983#
984# Security options
985#
986# CONFIG_KEYS is not set
987# CONFIG_SECURITY is not set
988# CONFIG_SECURITY_FILE_CAPABILITIES is not set
989# CONFIG_CRYPTO is not set
990
991#
992# Library routines
993#
994CONFIG_BITREVERSE=y
995# CONFIG_GENERIC_FIND_FIRST_BIT is not set
996# CONFIG_GENERIC_FIND_NEXT_BIT is not set
997# CONFIG_CRC_CCITT is not set
998# CONFIG_CRC16 is not set
999# CONFIG_CRC_ITU_T is not set
1000CONFIG_CRC32=y
1001# CONFIG_CRC7 is not set
1002# CONFIG_LIBCRC32C is not set
1003CONFIG_ZLIB_INFLATE=y
1004CONFIG_ZLIB_DEFLATE=y
1005CONFIG_PLIST=y
1006CONFIG_HAS_IOMEM=y
1007CONFIG_HAS_IOPORT=y
1008CONFIG_HAS_DMA=y
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 88d5e61a2e13..b047c7e795a9 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -4,7 +4,7 @@
4 4
5# Object file lists. 5# Object file lists.
6 6
7obj-y += irq.o time.o dma.o generic.o 7obj-y += irq.o time.o dma.o generic.o clock.o
8 8
9obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o 9obj-$(CONFIG_CPU_FREQ_IMX) += cpufreq.o
10 10
diff --git a/arch/arm/mach-imx/clock.c b/arch/arm/mach-imx/clock.c
new file mode 100644
index 000000000000..6a90fe5578df
--- /dev/null
+++ b/arch/arm/mach-imx/clock.c
@@ -0,0 +1,205 @@
1/*
2 * Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#include <linux/kernel.h>
20#include <linux/device.h>
21#include <linux/list.h>
22#include <linux/math64.h>
23#include <linux/err.h>
24
25#include <asm/io.h>
26#include <asm/arch/imx-regs.h>
27
28/*
29 * Very simple approach: We can't disable clocks, so we do
30 * not need refcounting
31 */
32
33struct clk {
34 struct list_head node;
35 const char *name;
36 unsigned long (*get_rate)(void);
37};
38
39/*
40 * get the system pll clock in Hz
41 *
42 * mfi + mfn / (mfd +1)
43 * f = 2 * f_ref * --------------------
44 * pd + 1
45 */
46static unsigned long imx_decode_pll(unsigned int pll, u32 f_ref)
47{
48 unsigned long long ll;
49 unsigned long quot;
50
51 u32 mfi = (pll >> 10) & 0xf;
52 u32 mfn = pll & 0x3ff;
53 u32 mfd = (pll >> 16) & 0x3ff;
54 u32 pd = (pll >> 26) & 0xf;
55
56 mfi = mfi <= 5 ? 5 : mfi;
57
58 ll = 2 * (unsigned long long)f_ref *
59 ((mfi << 16) + (mfn << 16) / (mfd + 1));
60 quot = (pd + 1) * (1 << 16);
61 ll += quot / 2;
62 do_div(ll, quot);
63 return (unsigned long)ll;
64}
65
66static unsigned long imx_get_system_clk(void)
67{
68 u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512);
69
70 return imx_decode_pll(SPCTL0, f_ref);
71}
72
73static unsigned long imx_get_mcu_clk(void)
74{
75 return imx_decode_pll(MPCTL0, CLK32 * 512);
76}
77
78/*
79 * get peripheral clock 1 ( UART[12], Timer[12], PWM )
80 */
81static unsigned long imx_get_perclk1(void)
82{
83 return imx_get_system_clk() / (((PCDR) & 0xf)+1);
84}
85
86/*
87 * get peripheral clock 2 ( LCD, SD, SPI[12] )
88 */
89static unsigned long imx_get_perclk2(void)
90{
91 return imx_get_system_clk() / (((PCDR>>4) & 0xf)+1);
92}
93
94/*
95 * get peripheral clock 3 ( SSI )
96 */
97static unsigned long imx_get_perclk3(void)
98{
99 return imx_get_system_clk() / (((PCDR>>16) & 0x7f)+1);
100}
101
102/*
103 * get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA )
104 */
105static unsigned long imx_get_hclk(void)
106{
107 return imx_get_system_clk() / (((CSCR>>10) & 0xf)+1);
108}
109
110static struct clk clk_system_clk = {
111 .name = "system_clk",
112 .get_rate = imx_get_system_clk,
113};
114
115static struct clk clk_hclk = {
116 .name = "hclk",
117 .get_rate = imx_get_hclk,
118};
119
120static struct clk clk_mcu_clk = {
121 .name = "mcu_clk",
122 .get_rate = imx_get_mcu_clk,
123};
124
125static struct clk clk_perclk1 = {
126 .name = "perclk1",
127 .get_rate = imx_get_perclk1,
128};
129
130static struct clk clk_uart_clk = {
131 .name = "uart_clk",
132 .get_rate = imx_get_perclk1,
133};
134
135static struct clk clk_perclk2 = {
136 .name = "perclk2",
137 .get_rate = imx_get_perclk2,
138};
139
140static struct clk clk_perclk3 = {
141 .name = "perclk3",
142 .get_rate = imx_get_perclk3,
143};
144
145static struct clk *clks[] = {
146 &clk_perclk1,
147 &clk_perclk2,
148 &clk_perclk3,
149 &clk_system_clk,
150 &clk_hclk,
151 &clk_mcu_clk,
152 &clk_uart_clk,
153};
154
155static LIST_HEAD(clocks);
156static DEFINE_MUTEX(clocks_mutex);
157
158struct clk *clk_get(struct device *dev, const char *id)
159{
160 struct clk *p, *clk = ERR_PTR(-ENOENT);
161
162 mutex_lock(&clocks_mutex);
163 list_for_each_entry(p, &clocks, node) {
164 if (!strcmp(p->name, id)) {
165 clk = p;
166 goto found;
167 }
168 }
169
170found:
171 mutex_unlock(&clocks_mutex);
172
173 return clk;
174}
175
176void clk_put(struct clk *clk)
177{
178}
179
180int clk_enable(struct clk *clk)
181{
182 return 0;
183}
184
185void clk_disable(struct clk *clk)
186{
187}
188
189unsigned long clk_get_rate(struct clk *clk)
190{
191 return clk->get_rate();
192}
193
194int imx_clocks_init(void)
195{
196 int i;
197
198 mutex_lock(&clocks_mutex);
199 for (i = 0; i < ARRAY_SIZE(clks); i++)
200 list_add(&clks[i]->node, &clocks);
201 mutex_unlock(&clocks_mutex);
202
203 return 0;
204}
205
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c
index e548ba74a4d2..be0809b33e08 100644
--- a/arch/arm/mach-imx/cpufreq.c
+++ b/arch/arm/mach-imx/cpufreq.c
@@ -32,6 +32,8 @@
32#include <linux/types.h> 32#include <linux/types.h>
33#include <linux/init.h> 33#include <linux/init.h>
34#include <linux/cpufreq.h> 34#include <linux/cpufreq.h>
35#include <linux/clk.h>
36#include <linux/err.h>
35#include <asm/system.h> 37#include <asm/system.h>
36 38
37#include <asm/hardware.h> 39#include <asm/hardware.h>
@@ -52,6 +54,8 @@
52static u32 mpctl0_at_boot; 54static u32 mpctl0_at_boot;
53static u32 bclk_div_at_boot; 55static u32 bclk_div_at_boot;
54 56
57static struct clk *system_clk, *mcu_clk;
58
55static void imx_set_async_mode(void) 59static void imx_set_async_mode(void)
56{ 60{
57 adjust_cr(CR_920T_CLOCK_MODE, CR_920T_ASYNC_MODE); 61 adjust_cr(CR_920T_CLOCK_MODE, CR_920T_ASYNC_MODE);
@@ -160,10 +164,10 @@ static unsigned int imx_get_speed(unsigned int cpu)
160 cr = get_cr(); 164 cr = get_cr();
161 165
162 if((cr & CR_920T_CLOCK_MODE) == CR_920T_FASTBUS_MODE) { 166 if((cr & CR_920T_CLOCK_MODE) == CR_920T_FASTBUS_MODE) {
163 freq = imx_get_system_clk(); 167 freq = clk_get_rate(system_clk);
164 freq = (freq + bclk_div/2) / bclk_div; 168 freq = (freq + bclk_div/2) / bclk_div;
165 } else { 169 } else {
166 freq = imx_get_mcu_clk(); 170 freq = clk_get_rate(mcu_clk);
167 if (cscr & CSCR_MPU_PRESC) 171 if (cscr & CSCR_MPU_PRESC)
168 freq /= 2; 172 freq /= 2;
169 } 173 }
@@ -201,7 +205,7 @@ static int imx_set_target(struct cpufreq_policy *policy,
201 pr_debug(KERN_DEBUG "imx: requested frequency %ld Hz, mpctl0 at boot 0x%08x\n", 205 pr_debug(KERN_DEBUG "imx: requested frequency %ld Hz, mpctl0 at boot 0x%08x\n",
202 freq, mpctl0_at_boot); 206 freq, mpctl0_at_boot);
203 207
204 sysclk = imx_get_system_clk(); 208 sysclk = clk_get_rate(system_clk);
205 209
206 if (freq > sysclk / bclk_div_at_boot + 1000000) { 210 if (freq > sysclk / bclk_div_at_boot + 1000000) {
207 freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, CLK32 * 512, freq, relation); 211 freq = imx_compute_mpctl(&mpctl0, mpctl0_at_boot, CLK32 * 512, freq, relation);
@@ -290,6 +294,16 @@ static int __init imx_cpufreq_init(void)
290 bclk_div_at_boot = __mfld2val(CSCR_BCLK_DIV, CSCR) + 1; 294 bclk_div_at_boot = __mfld2val(CSCR_BCLK_DIV, CSCR) + 1;
291 mpctl0_at_boot = 0; 295 mpctl0_at_boot = 0;
292 296
297 system_clk = clk_get(NULL, "system_clk");
298 if (IS_ERR(system_clk))
299 return PTR_ERR(system_clk);
300
301 mcu_clk = clk_get(NULL, "mcu_clk");
302 if (IS_ERR(mcu_clk)) {
303 clk_put(system_clk);
304 return PTR_ERR(mcu_clk);
305 }
306
293 if((CSCR & CSCR_MPEN) && 307 if((CSCR & CSCR_MPEN) &&
294 ((get_cr() & CR_920T_CLOCK_MODE) != CR_920T_FASTBUS_MODE)) 308 ((get_cr() & CR_920T_CLOCK_MODE) != CR_920T_FASTBUS_MODE))
295 mpctl0_at_boot = MPCTL0; 309 mpctl0_at_boot = MPCTL0;
diff --git a/arch/arm/mach-imx/generic.c b/arch/arm/mach-imx/generic.c
index 4cfc9d3af28a..98ddd8a6d05f 100644
--- a/arch/arm/mach-imx/generic.c
+++ b/arch/arm/mach-imx/generic.c
@@ -214,82 +214,6 @@ int imx_irq_to_gpio(unsigned irq)
214 214
215EXPORT_SYMBOL(imx_irq_to_gpio); 215EXPORT_SYMBOL(imx_irq_to_gpio);
216 216
217/*
218 * get the system pll clock in Hz
219 *
220 * mfi + mfn / (mfd +1)
221 * f = 2 * f_ref * --------------------
222 * pd + 1
223 */
224static unsigned int imx_decode_pll(unsigned int pll, u32 f_ref)
225{
226 unsigned long long ll;
227 unsigned long quot;
228
229 u32 mfi = (pll >> 10) & 0xf;
230 u32 mfn = pll & 0x3ff;
231 u32 mfd = (pll >> 16) & 0x3ff;
232 u32 pd = (pll >> 26) & 0xf;
233
234 mfi = mfi <= 5 ? 5 : mfi;
235
236 ll = 2 * (unsigned long long)f_ref * ( (mfi<<16) + (mfn<<16) / (mfd+1) );
237 quot = (pd+1) * (1<<16);
238 ll += quot / 2;
239 do_div(ll, quot);
240 return (unsigned int) ll;
241}
242
243unsigned int imx_get_system_clk(void)
244{
245 u32 f_ref = (CSCR & CSCR_SYSTEM_SEL) ? 16000000 : (CLK32 * 512);
246
247 return imx_decode_pll(SPCTL0, f_ref);
248}
249EXPORT_SYMBOL(imx_get_system_clk);
250
251unsigned int imx_get_mcu_clk(void)
252{
253 return imx_decode_pll(MPCTL0, CLK32 * 512);
254}
255EXPORT_SYMBOL(imx_get_mcu_clk);
256
257/*
258 * get peripheral clock 1 ( UART[12], Timer[12], PWM )
259 */
260unsigned int imx_get_perclk1(void)
261{
262 return imx_get_system_clk() / (((PCDR) & 0xf)+1);
263}
264EXPORT_SYMBOL(imx_get_perclk1);
265
266/*
267 * get peripheral clock 2 ( LCD, SD, SPI[12] )
268 */
269unsigned int imx_get_perclk2(void)
270{
271 return imx_get_system_clk() / (((PCDR>>4) & 0xf)+1);
272}
273EXPORT_SYMBOL(imx_get_perclk2);
274
275/*
276 * get peripheral clock 3 ( SSI )
277 */
278unsigned int imx_get_perclk3(void)
279{
280 return imx_get_system_clk() / (((PCDR>>16) & 0x7f)+1);
281}
282EXPORT_SYMBOL(imx_get_perclk3);
283
284/*
285 * get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA )
286 */
287unsigned int imx_get_hclk(void)
288{
289 return imx_get_system_clk() / (((CSCR>>10) & 0xf)+1);
290}
291EXPORT_SYMBOL(imx_get_hclk);
292
293static struct resource imx_mmc_resources[] = { 217static struct resource imx_mmc_resources[] = {
294 [0] = { 218 [0] = {
295 .start = 0x00214000, 219 .start = 0x00214000,
diff --git a/arch/arm/mach-imx/mx1ads.c b/arch/arm/mach-imx/mx1ads.c
index a9778c1587ab..9635d5812bcd 100644
--- a/arch/arm/mach-imx/mx1ads.c
+++ b/arch/arm/mach-imx/mx1ads.c
@@ -69,6 +69,11 @@ static struct resource imx_uart1_resources[] = {
69 .end = (UART1_MINT_TX), 69 .end = (UART1_MINT_TX),
70 .flags = IORESOURCE_IRQ, 70 .flags = IORESOURCE_IRQ,
71 }, 71 },
72 [3] = {
73 .start = UART1_MINT_RTS,
74 .end = UART1_MINT_RTS,
75 .flags = IORESOURCE_IRQ,
76 },
72}; 77};
73 78
74static struct platform_device imx_uart1_device = { 79static struct platform_device imx_uart1_device = {
@@ -97,6 +102,11 @@ static struct resource imx_uart2_resources[] = {
97 .end = (UART2_MINT_TX), 102 .end = (UART2_MINT_TX),
98 .flags = IORESOURCE_IRQ, 103 .flags = IORESOURCE_IRQ,
99 }, 104 },
105 [3] = {
106 .start = UART2_MINT_RTS,
107 .end = UART2_MINT_RTS,
108 .flags = IORESOURCE_IRQ,
109 },
100}; 110};
101 111
102static struct platform_device imx_uart2_device = { 112static struct platform_device imx_uart2_device = {
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index d86d124aea22..5a41e96e8586 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -17,6 +17,7 @@
17#include <linux/time.h> 17#include <linux/time.h>
18#include <linux/clocksource.h> 18#include <linux/clocksource.h>
19#include <linux/clockchips.h> 19#include <linux/clockchips.h>
20#include <linux/clk.h>
20 21
21#include <asm/hardware.h> 22#include <asm/hardware.h>
22#include <asm/io.h> 23#include <asm/io.h>
@@ -86,10 +87,10 @@ static struct clocksource clocksource_imx = {
86 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 87 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
87}; 88};
88 89
89static int __init imx_clocksource_init(void) 90static int __init imx_clocksource_init(unsigned long rate)
90{ 91{
91 clocksource_imx.mult = 92 clocksource_imx.mult =
92 clocksource_hz2mult(imx_get_perclk1(), clocksource_imx.shift); 93 clocksource_hz2mult(rate, clocksource_imx.shift);
93 clocksource_register(&clocksource_imx); 94 clocksource_register(&clocksource_imx);
94 95
95 return 0; 96 return 0;
@@ -174,9 +175,9 @@ static struct clock_event_device clockevent_imx = {
174 .rating = 200, 175 .rating = 200,
175}; 176};
176 177
177static int __init imx_clockevent_init(void) 178static int __init imx_clockevent_init(unsigned long rate)
178{ 179{
179 clockevent_imx.mult = div_sc(imx_get_perclk1(), NSEC_PER_SEC, 180 clockevent_imx.mult = div_sc(rate, NSEC_PER_SEC,
180 clockevent_imx.shift); 181 clockevent_imx.shift);
181 clockevent_imx.max_delta_ns = 182 clockevent_imx.max_delta_ns =
182 clockevent_delta2ns(0xfffffffe, &clockevent_imx); 183 clockevent_delta2ns(0xfffffffe, &clockevent_imx);
@@ -190,13 +191,23 @@ static int __init imx_clockevent_init(void)
190 return 0; 191 return 0;
191} 192}
192 193
194extern int imx_clocks_init(void);
193 195
194static void __init imx_timer_init(void) 196static void __init imx_timer_init(void)
195{ 197{
198 struct clk *clk;
199 unsigned long rate;
200
201 imx_clocks_init();
202
203 clk = clk_get(NULL, "perclk1");
204 clk_enable(clk);
205 rate = clk_get_rate(clk);
206
196 imx_timer_hardware_init(); 207 imx_timer_hardware_init();
197 imx_clocksource_init(); 208 imx_clocksource_init(rate);
198 209
199 imx_clockevent_init(); 210 imx_clockevent_init(rate);
200 211
201 /* 212 /*
202 * Make irqs happen for the system timer 213 * Make irqs happen for the system timer
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig
new file mode 100644
index 000000000000..1eaa97cb716d
--- /dev/null
+++ b/arch/arm/mach-mx2/Kconfig
@@ -0,0 +1,39 @@
1comment "MX2 family CPU support"
2 depends on ARCH_MX2
3
4config MACH_MX27
5 bool "i.MX27 support"
6 depends on ARCH_MX2
7 help
8 This enables support for Freescale's MX2 based i.MX27 processor.
9
10comment "MX2 Platforms"
11 depends on ARCH_MX2
12
13config MACH_MX27ADS
14 bool "MX27ADS platform"
15 depends on MACH_MX27
16 help
17 Include support for MX27ADS platform. This includes specific
18 configurations for the board and its peripherals.
19
20config MACH_PCM038
21 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
22 depends on MACH_MX27
23 help
24 Include support for phyCORE-i.MX27 (aka pcm038) platform. This
25 includes specific configurations for the module and its peripherals.
26
27choice
28 prompt "Baseboard"
29 depends on MACH_PCM038
30 default MACH_PCM970_BASEBOARD
31
32config MACH_PCM970_BASEBOARD
33 prompt "PHYTEC PCM970 development board"
34 bool
35 help
36 This adds board specific devices that can be found on Phytec's
37 PCM970 evaluation board.
38
39endchoice
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
new file mode 100644
index 000000000000..382d86080e86
--- /dev/null
+++ b/arch/arm/mach-mx2/Makefile
@@ -0,0 +1,14 @@
1#
2# Makefile for the linux kernel.
3#
4
5# Object file lists.
6
7obj-y := system.o generic.o devices.o serial.o
8
9obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
10obj-$(CONFIG_MACH_MX27) += clock_imx27.o
11
12obj-$(CONFIG_MACH_MX27ADS) += mx27ads.o
13obj-$(CONFIG_MACH_PCM038) += pcm038.o
14obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
diff --git a/arch/arm/mach-mx2/Makefile.boot b/arch/arm/mach-mx2/Makefile.boot
new file mode 100644
index 000000000000..696831dcd485
--- /dev/null
+++ b/arch/arm/mach-mx2/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0xA0008000
2params_phys-y := 0xA0000100
3initrd_phys-y := 0xA0800000
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
new file mode 100644
index 000000000000..0a29ef29c73a
--- /dev/null
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -0,0 +1,1626 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/spinlock.h>
24
25#include <asm/arch/clock.h>
26#include <asm/arch/common.h>
27#include <asm/div64.h>
28#include <asm/mach-types.h>
29
30#include "crm_regs.h"
31
32static struct clk ckil_clk;
33static struct clk mpll_clk;
34static struct clk mpll_main_clk[];
35static struct clk spll_clk;
36
37static int _clk_enable(struct clk *clk)
38{
39 unsigned long reg;
40
41 reg = __raw_readl(clk->enable_reg);
42 reg |= 1 << clk->enable_shift;
43 __raw_writel(reg, clk->enable_reg);
44
45 return 0;
46}
47
48static void _clk_disable(struct clk *clk)
49{
50 unsigned long reg;
51
52 reg = __raw_readl(clk->enable_reg);
53 reg &= ~(1 << clk->enable_shift);
54 __raw_writel(reg, clk->enable_reg);
55}
56
57static int _clk_spll_enable(struct clk *clk)
58{
59 unsigned long reg;
60
61 reg = __raw_readl(CCM_CSCR);
62 reg |= CCM_CSCR_SPEN;
63 __raw_writel(reg, CCM_CSCR);
64
65 while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0)
66 ;
67
68 return 0;
69}
70
71static void _clk_spll_disable(struct clk *clk)
72{
73 unsigned long reg;
74
75 reg = __raw_readl(CCM_CSCR);
76 reg &= ~CCM_CSCR_SPEN;
77 __raw_writel(reg, CCM_CSCR);
78}
79
80static void _clk_pccr01_enable(unsigned long mask0, unsigned long mask1)
81{
82 unsigned long reg;
83
84 reg = __raw_readl(CCM_PCCR0);
85 reg |= mask0;
86 __raw_writel(reg, CCM_PCCR0);
87
88 reg = __raw_readl(CCM_PCCR1);
89 reg |= mask1;
90 __raw_writel(reg, CCM_PCCR1);
91
92}
93
94static void _clk_pccr01_disable(unsigned long mask0, unsigned long mask1)
95{
96 unsigned long reg;
97
98 reg = __raw_readl(CCM_PCCR0);
99 reg &= ~mask0;
100 __raw_writel(reg, CCM_PCCR0);
101
102 reg = __raw_readl(CCM_PCCR1);
103 reg &= ~mask1;
104 __raw_writel(reg, CCM_PCCR1);
105}
106
107static void _clk_pccr10_enable(unsigned long mask1, unsigned long mask0)
108{
109 unsigned long reg;
110
111 reg = __raw_readl(CCM_PCCR1);
112 reg |= mask1;
113 __raw_writel(reg, CCM_PCCR1);
114
115 reg = __raw_readl(CCM_PCCR0);
116 reg |= mask0;
117 __raw_writel(reg, CCM_PCCR0);
118}
119
120static void _clk_pccr10_disable(unsigned long mask1, unsigned long mask0)
121{
122 unsigned long reg;
123
124 reg = __raw_readl(CCM_PCCR1);
125 reg &= ~mask1;
126 __raw_writel(reg, CCM_PCCR1);
127
128 reg = __raw_readl(CCM_PCCR0);
129 reg &= ~mask0;
130 __raw_writel(reg, CCM_PCCR0);
131}
132
133static int _clk_dma_enable(struct clk *clk)
134{
135 _clk_pccr01_enable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK);
136
137 return 0;
138}
139
140static void _clk_dma_disable(struct clk *clk)
141{
142 _clk_pccr01_disable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK);
143}
144
145static int _clk_rtic_enable(struct clk *clk)
146{
147 _clk_pccr01_enable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK);
148
149 return 0;
150}
151
152static void _clk_rtic_disable(struct clk *clk)
153{
154 _clk_pccr01_disable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK);
155}
156
157static int _clk_emma_enable(struct clk *clk)
158{
159 _clk_pccr01_enable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK);
160
161 return 0;
162}
163
164static void _clk_emma_disable(struct clk *clk)
165{
166 _clk_pccr01_disable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK);
167}
168
169static int _clk_slcdc_enable(struct clk *clk)
170{
171 _clk_pccr01_enable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK);
172
173 return 0;
174}
175
176static void _clk_slcdc_disable(struct clk *clk)
177{
178 _clk_pccr01_disable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK);
179}
180
181static int _clk_fec_enable(struct clk *clk)
182{
183 _clk_pccr01_enable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK);
184
185 return 0;
186}
187
188static void _clk_fec_disable(struct clk *clk)
189{
190 _clk_pccr01_disable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK);
191}
192
193static int _clk_vpu_enable(struct clk *clk)
194{
195 unsigned long reg;
196
197 reg = __raw_readl(CCM_PCCR1);
198 reg |= CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK;
199 __raw_writel(reg, CCM_PCCR1);
200
201 return 0;
202}
203
204static void _clk_vpu_disable(struct clk *clk)
205{
206 unsigned long reg;
207
208 reg = __raw_readl(CCM_PCCR1);
209 reg &= ~(CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK);
210 __raw_writel(reg, CCM_PCCR1);
211}
212
213static int _clk_sahara2_enable(struct clk *clk)
214{
215 _clk_pccr01_enable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK);
216
217 return 0;
218}
219
220static void _clk_sahara2_disable(struct clk *clk)
221{
222 _clk_pccr01_disable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK);
223}
224
225static int _clk_mstick1_enable(struct clk *clk)
226{
227 _clk_pccr10_enable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK);
228
229 return 0;
230}
231
232static void _clk_mstick1_disable(struct clk *clk)
233{
234 _clk_pccr10_disable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK);
235}
236
237#define CSCR() (__raw_readl(CCM_CSCR))
238#define PCDR0() (__raw_readl(CCM_PCDR0))
239#define PCDR1() (__raw_readl(CCM_PCDR1))
240
241static int _clk_cpu_set_parent(struct clk *clk, struct clk *parent)
242{
243 int cscr = CSCR();
244
245 if (clk->parent == parent)
246 return 0;
247
248 if (mx27_revision() >= CHIP_REV_2_0) {
249 if (parent == &mpll_main_clk[0]) {
250 cscr |= CCM_CSCR_ARM_SRC;
251 } else {
252 if (parent == &mpll_main_clk[1])
253 cscr &= ~CCM_CSCR_ARM_SRC;
254 else
255 return -EINVAL;
256 }
257 __raw_writel(cscr, CCM_CSCR);
258 } else
259 return -ENODEV;
260
261 clk->parent = parent;
262 return 0;
263}
264
265static unsigned long _clk_cpu_round_rate(struct clk *clk, unsigned long rate)
266{
267 int div;
268 unsigned long parent_rate;
269
270 parent_rate = clk_get_rate(clk->parent);
271
272 div = parent_rate / rate;
273 if (parent_rate % rate)
274 div++;
275
276 if (div > 4)
277 div = 4;
278
279 return parent_rate / div;
280}
281
282static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate)
283{
284 unsigned int div;
285 uint32_t reg;
286 unsigned long parent_rate;
287
288 parent_rate = clk_get_rate(clk->parent);
289
290 div = parent_rate / rate;
291
292 if (div > 4 || div < 1 || ((parent_rate / div) != rate))
293 return -EINVAL;
294
295 div--;
296
297 reg = __raw_readl(CCM_CSCR);
298 if (mx27_revision() >= CHIP_REV_2_0) {
299 reg &= ~CCM_CSCR_ARM_MASK;
300 reg |= div << CCM_CSCR_ARM_OFFSET;
301 reg &= ~0x06;
302 __raw_writel(reg | 0x80000000, CCM_CSCR);
303 } else {
304 printk(KERN_ERR "Cant set CPU frequency!\n");
305 }
306
307 return 0;
308}
309
310static unsigned long _clk_perclkx_round_rate(struct clk *clk,
311 unsigned long rate)
312{
313 u32 div;
314 unsigned long parent_rate;
315
316 parent_rate = clk_get_rate(clk->parent);
317
318 div = parent_rate / rate;
319 if (parent_rate % rate)
320 div++;
321
322 if (div > 64)
323 div = 64;
324
325 return parent_rate / div;
326}
327
328static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate)
329{
330 u32 reg;
331 u32 div;
332 unsigned long parent_rate;
333
334 parent_rate = clk_get_rate(clk->parent);
335
336 if (clk->id < 0 || clk->id > 3)
337 return -EINVAL;
338
339 div = parent_rate / rate;
340 if (div > 64 || div < 1 || ((parent_rate / div) != rate))
341 return -EINVAL;
342 div--;
343
344 reg =
345 __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK <<
346 (clk->id << 3));
347 reg |= div << (clk->id << 3);
348 __raw_writel(reg, CCM_PCDR1);
349
350 return 0;
351}
352
353static unsigned long _clk_usb_recalc(struct clk *clk)
354{
355 unsigned long usb_pdf;
356 unsigned long parent_rate;
357
358 parent_rate = clk_get_rate(clk->parent);
359
360 usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET;
361
362 return parent_rate / (usb_pdf + 1U);
363}
364
365static unsigned long _clk_ssi1_recalc(struct clk *clk)
366{
367 unsigned long ssi1_pdf;
368 unsigned long parent_rate;
369
370 parent_rate = clk_get_rate(clk->parent);
371
372 ssi1_pdf = (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK) >>
373 CCM_PCDR0_SSI1BAUDDIV_OFFSET;
374
375 if (mx27_revision() >= CHIP_REV_2_0)
376 ssi1_pdf += 4;
377 else
378 ssi1_pdf = (ssi1_pdf < 2) ? 124UL : ssi1_pdf;
379
380 return 2UL * parent_rate / ssi1_pdf;
381}
382
383static unsigned long _clk_ssi2_recalc(struct clk *clk)
384{
385 unsigned long ssi2_pdf;
386 unsigned long parent_rate;
387
388 parent_rate = clk_get_rate(clk->parent);
389
390 ssi2_pdf = (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >>
391 CCM_PCDR0_SSI2BAUDDIV_OFFSET;
392
393 if (mx27_revision() >= CHIP_REV_2_0)
394 ssi2_pdf += 4;
395 else
396 ssi2_pdf = (ssi2_pdf < 2) ? 124UL : ssi2_pdf;
397
398 return 2UL * parent_rate / ssi2_pdf;
399}
400
401static unsigned long _clk_nfc_recalc(struct clk *clk)
402{
403 unsigned long nfc_pdf;
404 unsigned long parent_rate;
405
406 parent_rate = clk_get_rate(clk->parent);
407
408 if (mx27_revision() >= CHIP_REV_2_0) {
409 nfc_pdf =
410 (PCDR0() & CCM_PCDR0_NFCDIV2_MASK) >>
411 CCM_PCDR0_NFCDIV2_OFFSET;
412 } else {
413 nfc_pdf =
414 (PCDR0() & CCM_PCDR0_NFCDIV_MASK) >>
415 CCM_PCDR0_NFCDIV_OFFSET;
416 }
417
418 return parent_rate / (nfc_pdf + 1);
419}
420
421static unsigned long _clk_vpu_recalc(struct clk *clk)
422{
423 unsigned long vpu_pdf;
424 unsigned long parent_rate;
425
426 parent_rate = clk_get_rate(clk->parent);
427
428 if (mx27_revision() >= CHIP_REV_2_0) {
429 vpu_pdf =
430 (PCDR0() & CCM_PCDR0_VPUDIV2_MASK) >>
431 CCM_PCDR0_VPUDIV2_OFFSET;
432 vpu_pdf += 4;
433 } else {
434 vpu_pdf =
435 (PCDR0() & CCM_PCDR0_VPUDIV_MASK) >>
436 CCM_PCDR0_VPUDIV_OFFSET;
437 vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf;
438 }
439 return 2UL * parent_rate / vpu_pdf;
440}
441
442static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
443{
444 return clk->parent->round_rate(clk->parent, rate);
445}
446
447static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
448{
449 return clk->parent->set_rate(clk->parent, rate);
450}
451
452/* in Hz */
453static unsigned long external_high_reference = 26000000;
454
455static unsigned long get_high_reference_clock_rate(struct clk *clk)
456{
457 return external_high_reference;
458}
459
460/*
461 * the high frequency external clock reference
462 * Default case is 26MHz. Could be changed at runtime
463 * with a call to change_external_high_reference()
464 */
465static struct clk ckih_clk = {
466 .name = "ckih",
467 .get_rate = get_high_reference_clock_rate,
468};
469
470/* in Hz */
471static unsigned long external_low_reference = 32768;
472
473static unsigned long get_low_reference_clock_rate(struct clk *clk)
474{
475 return external_low_reference;
476}
477
478/*
479 * the low frequency external clock reference
480 * Default case is 32.768kHz Could be changed at runtime
481 * with a call to change_external_low_reference()
482 */
483static struct clk ckil_clk = {
484 .name = "ckil",
485 .get_rate = get_low_reference_clock_rate,
486};
487
488static unsigned long get_mpll_clk(struct clk *clk)
489{
490 uint32_t reg;
491 unsigned long ref_clk;
492 unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
493 unsigned long long temp;
494
495 ref_clk = clk_get_rate(clk->parent);
496
497 reg = __raw_readl(CCM_MPCTL0);
498 pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET;
499 mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET;
500 mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET;
501 mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET;
502
503 mfi = (mfi <= 5) ? 5 : mfi;
504 temp = 2LL * ref_clk * mfn;
505 do_div(temp, mfd + 1);
506 temp = 2LL * ref_clk * mfi + temp;
507 do_div(temp, pdf + 1);
508
509 return (unsigned long)temp;
510}
511
512static struct clk mpll_clk = {
513 .name = "mpll",
514 .parent = &ckih_clk,
515 .get_rate = get_mpll_clk,
516};
517
518static unsigned long _clk_mpll_main_get_rate(struct clk *clk)
519{
520 unsigned long parent_rate;
521
522 parent_rate = clk_get_rate(clk->parent);
523
524 /* i.MX27 TO2:
525 * clk->id == 0: arm clock source path 1 which is from 2*MPLL/DIV_2
526 * clk->id == 1: arm clock source path 2 which is from 2*MPLL/DIV_3
527 */
528
529 if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1)
530 return 2UL * parent_rate / 3UL;
531
532 return parent_rate;
533}
534
535static struct clk mpll_main_clk[] = {
536 {
537 /* For i.MX27 TO2, it is the MPLL path 1 of ARM core
538 * It provide the clock source whose rate is same as MPLL
539 */
540 .name = "mpll_main",
541 .id = 0,
542 .parent = &mpll_clk,
543 .get_rate = _clk_mpll_main_get_rate
544 }, {
545 /* For i.MX27 TO2, it is the MPLL path 2 of ARM core
546 * It provide the clock source whose rate is same MPLL * 2/3
547 */
548 .name = "mpll_main",
549 .id = 1,
550 .parent = &mpll_clk,
551 .get_rate = _clk_mpll_main_get_rate
552 }
553};
554
555static unsigned long get_spll_clk(struct clk *clk)
556{
557 uint32_t reg;
558 unsigned long ref_clk;
559 unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
560 unsigned long long temp;
561
562 ref_clk = clk_get_rate(clk->parent);
563
564 reg = __raw_readl(CCM_SPCTL0);
565 /*TODO: This is TO2 Bug */
566 if (mx27_revision() >= CHIP_REV_2_0)
567 __raw_writel(reg, CCM_SPCTL0);
568
569 pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET;
570 mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET;
571 mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET;
572 mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET;
573
574 mfi = (mfi <= 5) ? 5 : mfi;
575 temp = 2LL * ref_clk * mfn;
576 do_div(temp, mfd + 1);
577 temp = 2LL * ref_clk * mfi + temp;
578 do_div(temp, pdf + 1);
579
580 return (unsigned long)temp;
581}
582
583static struct clk spll_clk = {
584 .name = "spll",
585 .parent = &ckih_clk,
586 .get_rate = get_spll_clk,
587 .enable = _clk_spll_enable,
588 .disable = _clk_spll_disable,
589};
590
591static unsigned long get_cpu_clk(struct clk *clk)
592{
593 u32 div;
594 unsigned long rate;
595
596 if (mx27_revision() >= CHIP_REV_2_0)
597 div = (CSCR() & CCM_CSCR_ARM_MASK) >> CCM_CSCR_ARM_OFFSET;
598 else
599 div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET;
600
601 rate = clk_get_rate(clk->parent);
602 return rate / (div + 1);
603}
604
605static struct clk cpu_clk = {
606 .name = "cpu_clk",
607 .parent = &mpll_main_clk[1],
608 .set_parent = _clk_cpu_set_parent,
609 .round_rate = _clk_cpu_round_rate,
610 .get_rate = get_cpu_clk,
611 .set_rate = _clk_cpu_set_rate,
612};
613
614static unsigned long get_ahb_clk(struct clk *clk)
615{
616 unsigned long rate;
617 unsigned long bclk_pdf;
618
619 if (mx27_revision() >= CHIP_REV_2_0)
620 bclk_pdf = (CSCR() & CCM_CSCR_AHB_MASK)
621 >> CCM_CSCR_AHB_OFFSET;
622 else
623 bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK)
624 >> CCM_CSCR_BCLK_OFFSET;
625
626 rate = clk_get_rate(clk->parent);
627 return rate / (bclk_pdf + 1);
628}
629
630static struct clk ahb_clk = {
631 .name = "ahb_clk",
632 .parent = &mpll_main_clk[1],
633 .get_rate = get_ahb_clk,
634};
635
636static unsigned long get_ipg_clk(struct clk *clk)
637{
638 unsigned long rate;
639 unsigned long ipg_pdf;
640
641 if (mx27_revision() >= CHIP_REV_2_0)
642 return clk_get_rate(clk->parent);
643 else
644 ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET;
645
646 rate = clk_get_rate(clk->parent);
647 return rate / (ipg_pdf + 1);
648}
649
650static struct clk ipg_clk = {
651 .name = "ipg_clk",
652 .parent = &ahb_clk,
653 .get_rate = get_ipg_clk,
654};
655
656static unsigned long _clk_perclkx_recalc(struct clk *clk)
657{
658 unsigned long perclk_pdf;
659 unsigned long parent_rate;
660
661 parent_rate = clk_get_rate(clk->parent);
662
663 if (clk->id < 0 || clk->id > 3)
664 return 0;
665
666 perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK;
667
668 return parent_rate / (perclk_pdf + 1);
669}
670
671static struct clk per_clk[] = {
672 {
673 .name = "per_clk",
674 .id = 0,
675 .parent = &mpll_main_clk[1],
676 .get_rate = _clk_perclkx_recalc,
677 .enable = _clk_enable,
678 .enable_reg = CCM_PCCR1,
679 .enable_shift = CCM_PCCR1_PERCLK1_OFFSET,
680 .disable = _clk_disable,
681 }, {
682 .name = "per_clk",
683 .id = 1,
684 .parent = &mpll_main_clk[1],
685 .get_rate = _clk_perclkx_recalc,
686 .enable = _clk_enable,
687 .enable_reg = CCM_PCCR1,
688 .enable_shift = CCM_PCCR1_PERCLK2_OFFSET,
689 .disable = _clk_disable,
690 }, {
691 .name = "per_clk",
692 .id = 2,
693 .parent = &mpll_main_clk[1],
694 .round_rate = _clk_perclkx_round_rate,
695 .set_rate = _clk_perclkx_set_rate,
696 .get_rate = _clk_perclkx_recalc,
697 .enable = _clk_enable,
698 .enable_reg = CCM_PCCR1,
699 .enable_shift = CCM_PCCR1_PERCLK3_OFFSET,
700 .disable = _clk_disable,
701 }, {
702 .name = "per_clk",
703 .id = 3,
704 .parent = &mpll_main_clk[1],
705 .round_rate = _clk_perclkx_round_rate,
706 .set_rate = _clk_perclkx_set_rate,
707 .get_rate = _clk_perclkx_recalc,
708 .enable = _clk_enable,
709 .enable_reg = CCM_PCCR1,
710 .enable_shift = CCM_PCCR1_PERCLK4_OFFSET,
711 .disable = _clk_disable,
712 },
713};
714
715struct clk uart1_clk[] = {
716 {
717 .name = "uart_clk",
718 .id = 0,
719 .parent = &per_clk[0],
720 .secondary = &uart1_clk[1],
721 }, {
722 .name = "uart_ipg_clk",
723 .id = 0,
724 .parent = &ipg_clk,
725 .enable = _clk_enable,
726 .enable_reg = CCM_PCCR1,
727 .enable_shift = CCM_PCCR1_UART1_OFFSET,
728 .disable = _clk_disable,
729 },
730};
731
732struct clk uart2_clk[] = {
733 {
734 .name = "uart_clk",
735 .id = 1,
736 .parent = &per_clk[0],
737 .secondary = &uart2_clk[1],
738 }, {
739 .name = "uart_ipg_clk",
740 .id = 1,
741 .parent = &ipg_clk,
742 .enable = _clk_enable,
743 .enable_reg = CCM_PCCR1,
744 .enable_shift = CCM_PCCR1_UART2_OFFSET,
745 .disable = _clk_disable,
746 },
747};
748
749struct clk uart3_clk[] = {
750 {
751 .name = "uart_clk",
752 .id = 2,
753 .parent = &per_clk[0],
754 .secondary = &uart3_clk[1],
755 }, {
756 .name = "uart_ipg_clk",
757 .id = 2,
758 .parent = &ipg_clk,
759 .enable = _clk_enable,
760 .enable_reg = CCM_PCCR1,
761 .enable_shift = CCM_PCCR1_UART3_OFFSET,
762 .disable = _clk_disable,
763 },
764};
765
766struct clk uart4_clk[] = {
767 {
768 .name = "uart_clk",
769 .id = 3,
770 .parent = &per_clk[0],
771 .secondary = &uart4_clk[1],
772 }, {
773 .name = "uart_ipg_clk",
774 .id = 3,
775 .parent = &ipg_clk,
776 .enable = _clk_enable,
777 .enable_reg = CCM_PCCR1,
778 .enable_shift = CCM_PCCR1_UART4_OFFSET,
779 .disable = _clk_disable,
780 },
781};
782
783struct clk uart5_clk[] = {
784 {
785 .name = "uart_clk",
786 .id = 4,
787 .parent = &per_clk[0],
788 .secondary = &uart5_clk[1],
789 }, {
790 .name = "uart_ipg_clk",
791 .id = 4,
792 .parent = &ipg_clk,
793 .enable = _clk_enable,
794 .enable_reg = CCM_PCCR1,
795 .enable_shift = CCM_PCCR1_UART5_OFFSET,
796 .disable = _clk_disable,
797 },
798};
799
800struct clk uart6_clk[] = {
801 {
802 .name = "uart_clk",
803 .id = 5,
804 .parent = &per_clk[0],
805 .secondary = &uart6_clk[1],
806 }, {
807 .name = "uart_ipg_clk",
808 .id = 5,
809 .parent = &ipg_clk,
810 .enable = _clk_enable,
811 .enable_reg = CCM_PCCR1,
812 .enable_shift = CCM_PCCR1_UART6_OFFSET,
813 .disable = _clk_disable,
814 },
815};
816
817static struct clk gpt1_clk[] = {
818 {
819 .name = "gpt_clk",
820 .id = 0,
821 .parent = &per_clk[0],
822 .secondary = &gpt1_clk[1],
823 }, {
824 .name = "gpt_ipg_clk",
825 .id = 0,
826 .parent = &ipg_clk,
827 .enable = _clk_enable,
828 .enable_reg = CCM_PCCR0,
829 .enable_shift = CCM_PCCR0_GPT1_OFFSET,
830 .disable = _clk_disable,
831 },
832};
833
834static struct clk gpt2_clk[] = {
835 {
836 .name = "gpt_clk",
837 .id = 1,
838 .parent = &per_clk[0],
839 .secondary = &gpt2_clk[1],
840 }, {
841 .name = "gpt_ipg_clk",
842 .id = 1,
843 .parent = &ipg_clk,
844 .enable = _clk_enable,
845 .enable_reg = CCM_PCCR0,
846 .enable_shift = CCM_PCCR0_GPT2_OFFSET,
847 .disable = _clk_disable,
848 },
849};
850
851static struct clk gpt3_clk[] = {
852 {
853 .name = "gpt_clk",
854 .id = 2,
855 .parent = &per_clk[0],
856 .secondary = &gpt3_clk[1],
857 }, {
858 .name = "gpt_ipg_clk",
859 .id = 2,
860 .parent = &ipg_clk,
861 .enable = _clk_enable,
862 .enable_reg = CCM_PCCR0,
863 .enable_shift = CCM_PCCR0_GPT3_OFFSET,
864 .disable = _clk_disable,
865 },
866};
867
868static struct clk gpt4_clk[] = {
869 {
870 .name = "gpt_clk",
871 .id = 3,
872 .parent = &per_clk[0],
873 .secondary = &gpt4_clk[1],
874 }, {
875 .name = "gpt_ipg_clk",
876 .id = 3,
877 .parent = &ipg_clk,
878 .enable = _clk_enable,
879 .enable_reg = CCM_PCCR0,
880 .enable_shift = CCM_PCCR0_GPT4_OFFSET,
881 .disable = _clk_disable,
882 },
883};
884
885static struct clk gpt5_clk[] = {
886 {
887 .name = "gpt_clk",
888 .id = 4,
889 .parent = &per_clk[0],
890 .secondary = &gpt5_clk[1],
891 }, {
892 .name = "gpt_ipg_clk",
893 .id = 4,
894 .parent = &ipg_clk,
895 .enable = _clk_enable,
896 .enable_reg = CCM_PCCR0,
897 .enable_shift = CCM_PCCR0_GPT5_OFFSET,
898 .disable = _clk_disable,
899 },
900};
901
902static struct clk gpt6_clk[] = {
903 {
904 .name = "gpt_clk",
905 .id = 5,
906 .parent = &per_clk[0],
907 .secondary = &gpt6_clk[1],
908 }, {
909 .name = "gpt_ipg_clk",
910 .id = 5,
911 .parent = &ipg_clk,
912 .enable = _clk_enable,
913 .enable_reg = CCM_PCCR0,
914 .enable_shift = CCM_PCCR0_GPT6_OFFSET,
915 .disable = _clk_disable,
916 },
917};
918
919static struct clk pwm_clk[] = {
920 {
921 .name = "pwm_clk",
922 .parent = &per_clk[0],
923 .secondary = &pwm_clk[1],
924 }, {
925 .name = "pwm_clk",
926 .parent = &ipg_clk,
927 .enable = _clk_enable,
928 .enable_reg = CCM_PCCR0,
929 .enable_shift = CCM_PCCR0_PWM_OFFSET,
930 .disable = _clk_disable,
931 },
932};
933
934static struct clk sdhc1_clk[] = {
935 {
936 .name = "sdhc_clk",
937 .id = 0,
938 .parent = &per_clk[1],
939 .secondary = &sdhc1_clk[1],
940 }, {
941 .name = "sdhc_ipg_clk",
942 .id = 0,
943 .parent = &ipg_clk,
944 .enable = _clk_enable,
945 .enable_reg = CCM_PCCR0,
946 .enable_shift = CCM_PCCR0_SDHC1_OFFSET,
947 .disable = _clk_disable,
948 },
949};
950
951static struct clk sdhc2_clk[] = {
952 {
953 .name = "sdhc_clk",
954 .id = 1,
955 .parent = &per_clk[1],
956 .secondary = &sdhc2_clk[1],
957 }, {
958 .name = "sdhc_ipg_clk",
959 .id = 1,
960 .parent = &ipg_clk,
961 .enable = _clk_enable,
962 .enable_reg = CCM_PCCR0,
963 .enable_shift = CCM_PCCR0_SDHC2_OFFSET,
964 .disable = _clk_disable,
965 },
966};
967
968static struct clk sdhc3_clk[] = {
969 {
970 .name = "sdhc_clk",
971 .id = 2,
972 .parent = &per_clk[1],
973 .secondary = &sdhc3_clk[1],
974 }, {
975 .name = "sdhc_ipg_clk",
976 .id = 2,
977 .parent = &ipg_clk,
978 .enable = _clk_enable,
979 .enable_reg = CCM_PCCR0,
980 .enable_shift = CCM_PCCR0_SDHC3_OFFSET,
981 .disable = _clk_disable,
982 },
983};
984
985static struct clk cspi1_clk[] = {
986 {
987 .name = "cspi_clk",
988 .id = 0,
989 .parent = &per_clk[1],
990 .secondary = &cspi1_clk[1],
991 }, {
992 .name = "cspi_ipg_clk",
993 .id = 0,
994 .parent = &ipg_clk,
995 .enable = _clk_enable,
996 .enable_reg = CCM_PCCR0,
997 .enable_shift = CCM_PCCR0_CSPI1_OFFSET,
998 .disable = _clk_disable,
999 },
1000};
1001
1002static struct clk cspi2_clk[] = {
1003 {
1004 .name = "cspi_clk",
1005 .id = 1,
1006 .parent = &per_clk[1],
1007 .secondary = &cspi2_clk[1],
1008 }, {
1009 .name = "cspi_ipg_clk",
1010 .id = 1,
1011 .parent = &ipg_clk,
1012 .enable = _clk_enable,
1013 .enable_reg = CCM_PCCR0,
1014 .enable_shift = CCM_PCCR0_CSPI2_OFFSET,
1015 .disable = _clk_disable,
1016 },
1017};
1018
1019static struct clk cspi3_clk[] = {
1020 {
1021 .name = "cspi_clk",
1022 .id = 2,
1023 .parent = &per_clk[1],
1024 .secondary = &cspi3_clk[1],
1025 }, {
1026 .name = "cspi_ipg_clk",
1027 .id = 2,
1028 .parent = &ipg_clk,
1029 .enable = _clk_enable,
1030 .enable_reg = CCM_PCCR0,
1031 .enable_shift = CCM_PCCR0_CSPI3_OFFSET,
1032 .disable = _clk_disable,
1033 },
1034};
1035
1036static struct clk lcdc_clk[] = {
1037 {
1038 .name = "lcdc_clk",
1039 .parent = &per_clk[2],
1040 .secondary = &lcdc_clk[1],
1041 .round_rate = _clk_parent_round_rate,
1042 .set_rate = _clk_parent_set_rate,
1043 }, {
1044 .name = "lcdc_ipg_clk",
1045 .parent = &ipg_clk,
1046 .secondary = &lcdc_clk[2],
1047 .enable = _clk_enable,
1048 .enable_reg = CCM_PCCR0,
1049 .enable_shift = CCM_PCCR0_LCDC_OFFSET,
1050 .disable = _clk_disable,
1051 }, {
1052 .name = "lcdc_ahb_clk",
1053 .parent = &ahb_clk,
1054 .enable = _clk_enable,
1055 .enable_reg = CCM_PCCR1,
1056 .enable_shift = CCM_PCCR1_HCLK_LCDC_OFFSET,
1057 .disable = _clk_disable,
1058 },
1059};
1060
1061static struct clk csi_clk[] = {
1062 {
1063 .name = "csi_perclk",
1064 .parent = &per_clk[3],
1065 .secondary = &csi_clk[1],
1066 .round_rate = _clk_parent_round_rate,
1067 .set_rate = _clk_parent_set_rate,
1068 }, {
1069 .name = "csi_ahb_clk",
1070 .parent = &ahb_clk,
1071 .enable = _clk_enable,
1072 .enable_reg = CCM_PCCR1,
1073 .enable_shift = CCM_PCCR1_HCLK_CSI_OFFSET,
1074 .disable = _clk_disable,
1075 },
1076};
1077
1078static struct clk usb_clk[] = {
1079 {
1080 .name = "usb_clk",
1081 .parent = &spll_clk,
1082 .get_rate = _clk_usb_recalc,
1083 .enable = _clk_enable,
1084 .enable_reg = CCM_PCCR1,
1085 .enable_shift = CCM_PCCR1_USBOTG_OFFSET,
1086 .disable = _clk_disable,
1087 }, {
1088 .name = "usb_ahb_clk",
1089 .parent = &ahb_clk,
1090 .enable = _clk_enable,
1091 .enable_reg = CCM_PCCR1,
1092 .enable_shift = CCM_PCCR1_HCLK_USBOTG_OFFSET,
1093 .disable = _clk_disable,
1094 }
1095};
1096
1097static struct clk ssi1_clk[] = {
1098 {
1099 .name = "ssi_clk",
1100 .id = 0,
1101 .parent = &mpll_main_clk[1],
1102 .secondary = &ssi1_clk[1],
1103 .get_rate = _clk_ssi1_recalc,
1104 .enable = _clk_enable,
1105 .enable_reg = CCM_PCCR1,
1106 .enable_shift = CCM_PCCR1_SSI1_BAUD_OFFSET,
1107 .disable = _clk_disable,
1108 }, {
1109 .name = "ssi_ipg_clk",
1110 .id = 0,
1111 .parent = &ipg_clk,
1112 .enable = _clk_enable,
1113 .enable_reg = CCM_PCCR0,
1114 .enable_shift = CCM_PCCR0_SSI1_IPG_OFFSET,
1115 .disable = _clk_disable,
1116 },
1117};
1118
1119static struct clk ssi2_clk[] = {
1120 {
1121 .name = "ssi_clk",
1122 .id = 1,
1123 .parent = &mpll_main_clk[1],
1124 .secondary = &ssi2_clk[1],
1125 .get_rate = _clk_ssi2_recalc,
1126 .enable = _clk_enable,
1127 .enable_reg = CCM_PCCR1,
1128 .enable_shift = CCM_PCCR1_SSI2_BAUD_OFFSET,
1129 .disable = _clk_disable,
1130 }, {
1131 .name = "ssi_ipg_clk",
1132 .id = 1,
1133 .parent = &ipg_clk,
1134 .enable = _clk_enable,
1135 .enable_reg = CCM_PCCR0,
1136 .enable_shift = CCM_PCCR0_SSI2_IPG_OFFSET,
1137 .disable = _clk_disable,
1138 },
1139};
1140
1141static struct clk nfc_clk = {
1142 .name = "nfc_clk",
1143 .parent = &cpu_clk,
1144 .get_rate = _clk_nfc_recalc,
1145 .enable = _clk_enable,
1146 .enable_reg = CCM_PCCR1,
1147 .enable_shift = CCM_PCCR1_NFC_BAUD_OFFSET,
1148 .disable = _clk_disable,
1149};
1150
1151static struct clk vpu_clk = {
1152 .name = "vpu_clk",
1153 .parent = &mpll_main_clk[1],
1154 .get_rate = _clk_vpu_recalc,
1155 .enable = _clk_vpu_enable,
1156 .disable = _clk_vpu_disable,
1157};
1158
1159static struct clk dma_clk = {
1160 .name = "dma_clk",
1161 .parent = &ahb_clk,
1162 .enable = _clk_dma_enable,
1163 .disable = _clk_dma_disable,
1164};
1165
1166static struct clk rtic_clk = {
1167 .name = "rtic_clk",
1168 .parent = &ahb_clk,
1169 .enable = _clk_rtic_enable,
1170 .disable = _clk_rtic_disable,
1171};
1172
1173static struct clk brom_clk = {
1174 .name = "brom_clk",
1175 .parent = &ahb_clk,
1176 .enable = _clk_enable,
1177 .enable_reg = CCM_PCCR1,
1178 .enable_shift = CCM_PCCR1_HCLK_BROM_OFFSET,
1179 .disable = _clk_disable,
1180};
1181
1182static struct clk emma_clk = {
1183 .name = "emma_clk",
1184 .parent = &ahb_clk,
1185 .enable = _clk_emma_enable,
1186 .disable = _clk_emma_disable,
1187};
1188
1189static struct clk slcdc_clk = {
1190 .name = "slcdc_clk",
1191 .parent = &ahb_clk,
1192 .enable = _clk_slcdc_enable,
1193 .disable = _clk_slcdc_disable,
1194};
1195
1196static struct clk fec_clk = {
1197 .name = "fec_clk",
1198 .parent = &ahb_clk,
1199 .enable = _clk_fec_enable,
1200 .disable = _clk_fec_disable,
1201};
1202
1203static struct clk emi_clk = {
1204 .name = "emi_clk",
1205 .parent = &ahb_clk,
1206 .enable = _clk_enable,
1207 .enable_reg = CCM_PCCR1,
1208 .enable_shift = CCM_PCCR1_HCLK_EMI_OFFSET,
1209 .disable = _clk_disable,
1210};
1211
1212static struct clk sahara2_clk = {
1213 .name = "sahara_clk",
1214 .parent = &ahb_clk,
1215 .enable = _clk_sahara2_enable,
1216 .disable = _clk_sahara2_disable,
1217};
1218
1219static struct clk ata_clk = {
1220 .name = "ata_clk",
1221 .parent = &ahb_clk,
1222 .enable = _clk_enable,
1223 .enable_reg = CCM_PCCR1,
1224 .enable_shift = CCM_PCCR1_HCLK_ATA_OFFSET,
1225 .disable = _clk_disable,
1226};
1227
1228static struct clk mstick1_clk = {
1229 .name = "mstick1_clk",
1230 .parent = &ipg_clk,
1231 .enable = _clk_mstick1_enable,
1232 .disable = _clk_mstick1_disable,
1233};
1234
1235static struct clk wdog_clk = {
1236 .name = "wdog_clk",
1237 .parent = &ipg_clk,
1238 .enable = _clk_enable,
1239 .enable_reg = CCM_PCCR1,
1240 .enable_shift = CCM_PCCR1_WDT_OFFSET,
1241 .disable = _clk_disable,
1242};
1243
1244static struct clk gpio_clk = {
1245 .name = "gpio_clk",
1246 .parent = &ipg_clk,
1247 .enable = _clk_enable,
1248 .enable_reg = CCM_PCCR1,
1249 .enable_shift = CCM_PCCR0_GPIO_OFFSET,
1250 .disable = _clk_disable,
1251};
1252
1253static struct clk i2c_clk[] = {
1254 {
1255 .name = "i2c_clk",
1256 .id = 0,
1257 .parent = &ipg_clk,
1258 .enable = _clk_enable,
1259 .enable_reg = CCM_PCCR0,
1260 .enable_shift = CCM_PCCR0_I2C1_OFFSET,
1261 .disable = _clk_disable,
1262 }, {
1263 .name = "i2c_clk",
1264 .id = 1,
1265 .parent = &ipg_clk,
1266 .enable = _clk_enable,
1267 .enable_reg = CCM_PCCR0,
1268 .enable_shift = CCM_PCCR0_I2C2_OFFSET,
1269 .disable = _clk_disable,
1270 },
1271};
1272
1273static struct clk iim_clk = {
1274 .name = "iim_clk",
1275 .parent = &ipg_clk,
1276 .enable = _clk_enable,
1277 .enable_reg = CCM_PCCR0,
1278 .enable_shift = CCM_PCCR0_IIM_OFFSET,
1279 .disable = _clk_disable,
1280};
1281
1282static struct clk kpp_clk = {
1283 .name = "kpp_clk",
1284 .parent = &ipg_clk,
1285 .enable = _clk_enable,
1286 .enable_reg = CCM_PCCR0,
1287 .enable_shift = CCM_PCCR0_KPP_OFFSET,
1288 .disable = _clk_disable,
1289};
1290
1291static struct clk owire_clk = {
1292 .name = "owire_clk",
1293 .parent = &ipg_clk,
1294 .enable = _clk_enable,
1295 .enable_reg = CCM_PCCR0,
1296 .enable_shift = CCM_PCCR0_OWIRE_OFFSET,
1297 .disable = _clk_disable,
1298};
1299
1300static struct clk rtc_clk = {
1301 .name = "rtc_clk",
1302 .parent = &ipg_clk,
1303 .enable = _clk_enable,
1304 .enable_reg = CCM_PCCR0,
1305 .enable_shift = CCM_PCCR0_RTC_OFFSET,
1306 .disable = _clk_disable,
1307};
1308
1309static struct clk scc_clk = {
1310 .name = "scc_clk",
1311 .parent = &ipg_clk,
1312 .enable = _clk_enable,
1313 .enable_reg = CCM_PCCR0,
1314 .enable_shift = CCM_PCCR0_SCC_OFFSET,
1315 .disable = _clk_disable,
1316};
1317
1318static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate)
1319{
1320 u32 div;
1321 unsigned long parent_rate;
1322
1323 parent_rate = clk_get_rate(clk->parent);
1324 div = parent_rate / rate;
1325 if (parent_rate % rate)
1326 div++;
1327
1328 if (div > 8)
1329 div = 8;
1330
1331 return parent_rate / div;
1332}
1333
1334static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
1335{
1336 u32 reg;
1337 u32 div;
1338 unsigned long parent_rate;
1339
1340 parent_rate = clk_get_rate(clk->parent);
1341
1342 div = parent_rate / rate;
1343
1344 if (div > 8 || div < 1 || ((parent_rate / div) != rate))
1345 return -EINVAL;
1346 div--;
1347
1348 reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKODIV_MASK;
1349 reg |= div << CCM_PCDR0_CLKODIV_OFFSET;
1350 __raw_writel(reg, CCM_PCDR0);
1351
1352 return 0;
1353}
1354
1355static unsigned long _clk_clko_recalc(struct clk *clk)
1356{
1357 u32 div;
1358 unsigned long parent_rate;
1359
1360 parent_rate = clk_get_rate(clk->parent);
1361
1362 div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_CLKODIV_MASK >>
1363 CCM_PCDR0_CLKODIV_OFFSET;
1364 div++;
1365
1366 return parent_rate / div;
1367}
1368
1369static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
1370{
1371 u32 reg;
1372
1373 reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK;
1374
1375 if (parent == &ckil_clk)
1376 reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET;
1377 else if (parent == &ckih_clk)
1378 reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET;
1379 else if (parent == mpll_clk.parent)
1380 reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET;
1381 else if (parent == spll_clk.parent)
1382 reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET;
1383 else if (parent == &mpll_clk)
1384 reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET;
1385 else if (parent == &spll_clk)
1386 reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET;
1387 else if (parent == &cpu_clk)
1388 reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET;
1389 else if (parent == &ahb_clk)
1390 reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET;
1391 else if (parent == &ipg_clk)
1392 reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET;
1393 else if (parent == &per_clk[0])
1394 reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET;
1395 else if (parent == &per_clk[1])
1396 reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET;
1397 else if (parent == &per_clk[2])
1398 reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET;
1399 else if (parent == &per_clk[3])
1400 reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET;
1401 else if (parent == &ssi1_clk[0])
1402 reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET;
1403 else if (parent == &ssi2_clk[0])
1404 reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET;
1405 else if (parent == &nfc_clk)
1406 reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET;
1407 else if (parent == &mstick1_clk)
1408 reg |= 0x11 << CCM_CCSR_CLKOSEL_OFFSET;
1409 else if (parent == &vpu_clk)
1410 reg |= 0x12 << CCM_CCSR_CLKOSEL_OFFSET;
1411 else if (parent == &usb_clk[0])
1412 reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET;
1413 else
1414 return -EINVAL;
1415
1416 __raw_writel(reg, CCM_CCSR);
1417
1418 return 0;
1419}
1420
1421static int _clk_clko_enable(struct clk *clk)
1422{
1423 u32 reg;
1424
1425 reg = __raw_readl(CCM_PCDR0) | CCM_PCDR0_CLKO_EN;
1426 __raw_writel(reg, CCM_PCDR0);
1427
1428 return 0;
1429}
1430
1431static void _clk_clko_disable(struct clk *clk)
1432{
1433 u32 reg;
1434
1435 reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKO_EN;
1436 __raw_writel(reg, CCM_PCDR0);
1437}
1438
1439static struct clk clko_clk = {
1440 .name = "clko_clk",
1441 .get_rate = _clk_clko_recalc,
1442 .set_rate = _clk_clko_set_rate,
1443 .round_rate = _clk_clko_round_rate,
1444 .set_parent = _clk_clko_set_parent,
1445 .enable = _clk_clko_enable,
1446 .disable = _clk_clko_disable,
1447};
1448
1449static struct clk *mxc_clks[] = {
1450 &ckih_clk,
1451 &ckil_clk,
1452 &mpll_clk,
1453 &mpll_main_clk[0],
1454 &mpll_main_clk[1],
1455 &spll_clk,
1456 &cpu_clk,
1457 &ahb_clk,
1458 &ipg_clk,
1459 &per_clk[0],
1460 &per_clk[1],
1461 &per_clk[2],
1462 &per_clk[3],
1463 &clko_clk,
1464 &uart1_clk[0],
1465 &uart1_clk[1],
1466 &uart2_clk[0],
1467 &uart2_clk[1],
1468 &uart3_clk[0],
1469 &uart3_clk[1],
1470 &uart4_clk[0],
1471 &uart4_clk[1],
1472 &uart5_clk[0],
1473 &uart5_clk[1],
1474 &uart6_clk[0],
1475 &uart6_clk[1],
1476 &gpt1_clk[0],
1477 &gpt1_clk[1],
1478 &gpt2_clk[0],
1479 &gpt2_clk[1],
1480 &gpt3_clk[0],
1481 &gpt3_clk[1],
1482 &gpt4_clk[0],
1483 &gpt4_clk[1],
1484 &gpt5_clk[0],
1485 &gpt5_clk[1],
1486 &gpt6_clk[0],
1487 &gpt6_clk[1],
1488 &pwm_clk[0],
1489 &pwm_clk[1],
1490 &sdhc1_clk[0],
1491 &sdhc1_clk[1],
1492 &sdhc2_clk[0],
1493 &sdhc2_clk[1],
1494 &sdhc3_clk[0],
1495 &sdhc3_clk[1],
1496 &cspi1_clk[0],
1497 &cspi1_clk[1],
1498 &cspi2_clk[0],
1499 &cspi2_clk[1],
1500 &cspi3_clk[0],
1501 &cspi3_clk[1],
1502 &lcdc_clk[0],
1503 &lcdc_clk[1],
1504 &lcdc_clk[2],
1505 &csi_clk[0],
1506 &csi_clk[1],
1507 &usb_clk[0],
1508 &usb_clk[1],
1509 &ssi1_clk[0],
1510 &ssi1_clk[1],
1511 &ssi2_clk[0],
1512 &ssi2_clk[1],
1513 &nfc_clk,
1514 &vpu_clk,
1515 &dma_clk,
1516 &rtic_clk,
1517 &brom_clk,
1518 &emma_clk,
1519 &slcdc_clk,
1520 &fec_clk,
1521 &emi_clk,
1522 &sahara2_clk,
1523 &ata_clk,
1524 &mstick1_clk,
1525 &wdog_clk,
1526 &gpio_clk,
1527 &i2c_clk[0],
1528 &i2c_clk[1],
1529 &iim_clk,
1530 &kpp_clk,
1531 &owire_clk,
1532 &rtc_clk,
1533 &scc_clk,
1534};
1535
1536void __init change_external_low_reference(unsigned long new_ref)
1537{
1538 external_low_reference = new_ref;
1539}
1540
1541unsigned long __init clk_early_get_timer_rate(void)
1542{
1543 return clk_get_rate(&per_clk[0]);
1544}
1545
1546static void __init probe_mxc_clocks(void)
1547{
1548 int i;
1549
1550 if (mx27_revision() >= CHIP_REV_2_0) {
1551 if (CSCR() & 0x8000)
1552 cpu_clk.parent = &mpll_main_clk[0];
1553
1554 if (!(CSCR() & 0x00800000))
1555 ssi2_clk[0].parent = &spll_clk;
1556
1557 if (!(CSCR() & 0x00400000))
1558 ssi1_clk[0].parent = &spll_clk;
1559
1560 if (!(CSCR() & 0x00200000))
1561 vpu_clk.parent = &spll_clk;
1562 } else {
1563 cpu_clk.parent = &mpll_clk;
1564 cpu_clk.set_parent = NULL;
1565 cpu_clk.round_rate = NULL;
1566 cpu_clk.set_rate = NULL;
1567 ahb_clk.parent = &mpll_clk;
1568
1569 for (i = 0; i < sizeof(per_clk) / sizeof(per_clk[0]); i++)
1570 per_clk[i].parent = &mpll_clk;
1571
1572 ssi1_clk[0].parent = &mpll_clk;
1573 ssi2_clk[0].parent = &mpll_clk;
1574
1575 vpu_clk.parent = &mpll_clk;
1576 }
1577}
1578
1579/*
1580 * must be called very early to get information about the
1581 * available clock rate when the timer framework starts
1582 */
1583int __init mxc_clocks_init(unsigned long fref)
1584{
1585 u32 cscr;
1586 struct clk **clkp;
1587
1588 external_high_reference = fref;
1589
1590 /* detect clock reference for both system PLL */
1591 cscr = CSCR();
1592 if (cscr & CCM_CSCR_MCU)
1593 mpll_clk.parent = &ckih_clk;
1594 else
1595 mpll_clk.parent = &ckil_clk;
1596
1597 if (cscr & CCM_CSCR_SP)
1598 spll_clk.parent = &ckih_clk;
1599 else
1600 spll_clk.parent = &ckil_clk;
1601
1602 probe_mxc_clocks();
1603
1604 per_clk[0].enable(&per_clk[0]);
1605 gpt1_clk[1].enable(&gpt1_clk[1]);
1606
1607 for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++)
1608 clk_register(*clkp);
1609
1610 /* Turn off all possible clocks */
1611 __raw_writel(CCM_PCCR0_GPT1_MASK, CCM_PCCR0);
1612 __raw_writel(CCM_PCCR1_PERCLK1_MASK | CCM_PCCR1_HCLK_EMI_MASK,
1613 CCM_PCCR1);
1614 spll_clk.disable(&spll_clk);
1615
1616 /* This will propagate to all children and init all the clock rates */
1617
1618 clk_enable(&emi_clk);
1619 clk_enable(&gpio_clk);
1620 clk_enable(&iim_clk);
1621 clk_enable(&gpt1_clk[0]);
1622#ifdef CONFIG_DEBUG_LL_CONSOLE
1623 clk_enable(&uart1_clk[0]);
1624#endif
1625 return 0;
1626}
diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-mx2/cpu_imx27.c
new file mode 100644
index 000000000000..d6b5c2e3377f
--- /dev/null
+++ b/arch/arm/mach-mx2/cpu_imx27.c
@@ -0,0 +1,63 @@
1/*
2 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20/*
21 * i.MX27 specific CPU detection code
22 */
23
24#include <linux/io.h>
25#include <linux/module.h>
26
27#include <asm/hardware.h>
28
29#include "crm_regs.h"
30
31static int cpu_silicon_rev = -1;
32static int cpu_partnumber;
33
34static void query_silicon_parameter(void)
35{
36 u32 val;
37 /*
38 * now we have access to the IO registers. As we need
39 * the silicon revision very early we read it here to
40 * avoid any further hooks
41 */
42 val = __raw_readl(IO_ADDRESS(SYSCTRL_BASE_ADDR) + SYS_CHIP_ID);
43
44 cpu_silicon_rev = (int)(val >> 28);
45 cpu_partnumber = (int)((val >> 12) & 0xFFFF);
46}
47
48/*
49 * Returns:
50 * the silicon revision of the cpu
51 * -EINVAL - not a mx27
52 */
53int mx27_revision(void)
54{
55 if (cpu_silicon_rev == -1)
56 query_silicon_parameter();
57
58 if (cpu_partnumber != 0x8821)
59 return -EINVAL;
60
61 return cpu_silicon_rev;
62}
63EXPORT_SYMBOL(mx27_revision);
diff --git a/arch/arm/mach-mx2/crm_regs.h b/arch/arm/mach-mx2/crm_regs.h
new file mode 100644
index 000000000000..a40a9b950ce9
--- /dev/null
+++ b/arch/arm/mach-mx2/crm_regs.h
@@ -0,0 +1,273 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ARCH_ARM_MACH_MX2_CRM_REGS_H__
21#define __ARCH_ARM_MACH_MX2_CRM_REGS_H__
22
23#include <asm/arch/hardware.h>
24
25/* Register offsets */
26#define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0)
27#define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4)
28#define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8)
29#define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC)
30#define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10)
31#define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14)
32#define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18)
33#define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c)
34#define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20)
35#define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24)
36#define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28)
37#define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c)
38#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30)
39#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34)
40
41#define CCM_CSCR_USB_OFFSET 28
42#define CCM_CSCR_USB_MASK (0x7 << 28)
43#define CCM_CSCR_SD_OFFSET 24
44#define CCM_CSCR_SD_MASK (0x3 << 24)
45#define CCM_CSCR_SSI2 (1 << 23)
46#define CCM_CSCR_SSI2_OFFSET 23
47#define CCM_CSCR_SSI1 (1 << 22)
48#define CCM_CSCR_SSI1_OFFSET 22
49#define CCM_CSCR_VPU (1 << 21)
50#define CCM_CSCR_VPU_OFFSET 21
51#define CCM_CSCR_MSHC (1 << 20)
52#define CCM_CSCR_SPLLRES (1 << 19)
53#define CCM_CSCR_MPLLRES (1 << 18)
54#define CCM_CSCR_SP (1 << 17)
55#define CCM_CSCR_MCU (1 << 16)
56/* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/
57#define CCM_CSCR_ARM_SRC (1 << 15)
58#define CCM_CSCR_ARM_OFFSET 12
59#define CCM_CSCR_ARM_MASK (0x3 << 12)
60/* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/
61#define CCM_CSCR_PRESC_OFFSET 13
62#define CCM_CSCR_PRESC_MASK (0x7 << 13)
63#define CCM_CSCR_BCLK_OFFSET 9
64#define CCM_CSCR_BCLK_MASK (0xf << 9)
65#define CCM_CSCR_IPDIV_OFFSET 8
66#define CCM_CSCR_IPDIV (1 << 8)
67/* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/
68#define CCM_CSCR_AHB_OFFSET 8
69#define CCM_CSCR_AHB_MASK (0x3 << 8)
70/* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/
71#define CCM_CSCR_OSC26MDIV (1 << 4)
72#define CCM_CSCR_OSC26M (1 << 3)
73#define CCM_CSCR_FPM (1 << 2)
74#define CCM_CSCR_SPEN (1 << 1)
75#define CCM_CSCR_MPEN 1
76
77#define CCM_MPCTL0_CPLM (1 << 31)
78#define CCM_MPCTL0_PD_OFFSET 26
79#define CCM_MPCTL0_PD_MASK (0xf << 26)
80#define CCM_MPCTL0_MFD_OFFSET 16
81#define CCM_MPCTL0_MFD_MASK (0x3ff << 16)
82#define CCM_MPCTL0_MFI_OFFSET 10
83#define CCM_MPCTL0_MFI_MASK (0xf << 10)
84#define CCM_MPCTL0_MFN_OFFSET 0
85#define CCM_MPCTL0_MFN_MASK 0x3ff
86
87#define CCM_MPCTL1_LF (1 << 15)
88#define CCM_MPCTL1_BRMO (1 << 6)
89
90#define CCM_SPCTL0_CPLM (1 << 31)
91#define CCM_SPCTL0_PD_OFFSET 26
92#define CCM_SPCTL0_PD_MASK (0xf << 26)
93#define CCM_SPCTL0_MFD_OFFSET 16
94#define CCM_SPCTL0_MFD_MASK (0x3ff << 16)
95#define CCM_SPCTL0_MFI_OFFSET 10
96#define CCM_SPCTL0_MFI_MASK (0xf << 10)
97#define CCM_SPCTL0_MFN_OFFSET 0
98#define CCM_SPCTL0_MFN_MASK 0x3ff
99
100#define CCM_SPCTL1_LF (1 << 15)
101#define CCM_SPCTL1_BRMO (1 << 6)
102
103#define CCM_OSC26MCTL_PEAK_OFFSET 16
104#define CCM_OSC26MCTL_PEAK_MASK (0x3 << 16)
105#define CCM_OSC26MCTL_AGC_OFFSET 8
106#define CCM_OSC26MCTL_AGC_MASK (0x3f << 8)
107#define CCM_OSC26MCTL_ANATEST_OFFSET 0
108#define CCM_OSC26MCTL_ANATEST_MASK 0x3f
109
110#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26
111#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26)
112#define CCM_PCDR0_CLKO_EN 25
113#define CCM_PCDR0_CLKODIV_OFFSET 22
114#define CCM_PCDR0_CLKODIV_MASK (0x7 << 22)
115#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16
116#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16)
117/*The difinition for i.MX27 TO2*/
118#define CCM_PCDR0_VPUDIV2_OFFSET 10
119#define CCM_PCDR0_VPUDIV2_MASK (0x3f << 10)
120#define CCM_PCDR0_NFCDIV2_OFFSET 6
121#define CCM_PCDR0_NFCDIV2_MASK (0xf << 6)
122#define CCM_PCDR0_MSHCDIV2_MASK 0x3f
123/*The difinition for i.MX27 TO2*/
124#define CCM_PCDR0_NFCDIV_OFFSET 12
125#define CCM_PCDR0_NFCDIV_MASK (0xf << 12)
126#define CCM_PCDR0_VPUDIV_OFFSET 8
127#define CCM_PCDR0_VPUDIV_MASK (0xf << 8)
128#define CCM_PCDR0_MSHCDIV_OFFSET 0
129#define CCM_PCDR0_MSHCDIV_MASK 0x1f
130
131#define CCM_PCDR1_PERDIV4_OFFSET 24
132#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24)
133#define CCM_PCDR1_PERDIV3_OFFSET 16
134#define CCM_PCDR1_PERDIV3_MASK (0x3f << 16)
135#define CCM_PCDR1_PERDIV2_OFFSET 8
136#define CCM_PCDR1_PERDIV2_MASK (0x3f << 8)
137#define CCM_PCDR1_PERDIV1_OFFSET 0
138#define CCM_PCDR1_PERDIV1_MASK 0x3f
139
140#define CCM_PCCR0_CSPI1_OFFSET 31
141#define CCM_PCCR0_CSPI1_MASK (1 << 31)
142#define CCM_PCCR0_CSPI2_OFFSET 30
143#define CCM_PCCR0_CSPI2_MASK (1 << 30)
144#define CCM_PCCR0_CSPI3_OFFSET 29
145#define CCM_PCCR0_CSPI3_MASK (1 << 29)
146#define CCM_PCCR0_DMA_OFFSET 28
147#define CCM_PCCR0_DMA_MASK (1 << 28)
148#define CCM_PCCR0_EMMA_OFFSET 27
149#define CCM_PCCR0_EMMA_MASK (1 << 27)
150#define CCM_PCCR0_FEC_OFFSET 26
151#define CCM_PCCR0_FEC_MASK (1 << 26)
152#define CCM_PCCR0_GPIO_OFFSET 25
153#define CCM_PCCR0_GPIO_MASK (1 << 25)
154#define CCM_PCCR0_GPT1_OFFSET 24
155#define CCM_PCCR0_GPT1_MASK (1 << 24)
156#define CCM_PCCR0_GPT2_OFFSET 23
157#define CCM_PCCR0_GPT2_MASK (1 << 23)
158#define CCM_PCCR0_GPT3_OFFSET 22
159#define CCM_PCCR0_GPT3_MASK (1 << 22)
160#define CCM_PCCR0_GPT4_OFFSET 21
161#define CCM_PCCR0_GPT4_MASK (1 << 21)
162#define CCM_PCCR0_GPT5_OFFSET 20
163#define CCM_PCCR0_GPT5_MASK (1 << 20)
164#define CCM_PCCR0_GPT6_OFFSET 19
165#define CCM_PCCR0_GPT6_MASK (1 << 19)
166#define CCM_PCCR0_I2C1_OFFSET 18
167#define CCM_PCCR0_I2C1_MASK (1 << 18)
168#define CCM_PCCR0_I2C2_OFFSET 17
169#define CCM_PCCR0_I2C2_MASK (1 << 17)
170#define CCM_PCCR0_IIM_OFFSET 16
171#define CCM_PCCR0_IIM_MASK (1 << 16)
172#define CCM_PCCR0_KPP_OFFSET 15
173#define CCM_PCCR0_KPP_MASK (1 << 15)
174#define CCM_PCCR0_LCDC_OFFSET 14
175#define CCM_PCCR0_LCDC_MASK (1 << 14)
176#define CCM_PCCR0_MSHC_OFFSET 13
177#define CCM_PCCR0_MSHC_MASK (1 << 13)
178#define CCM_PCCR0_OWIRE_OFFSET 12
179#define CCM_PCCR0_OWIRE_MASK (1 << 12)
180#define CCM_PCCR0_PWM_OFFSET 11
181#define CCM_PCCR0_PWM_MASK (1 << 11)
182#define CCM_PCCR0_RTC_OFFSET 9
183#define CCM_PCCR0_RTC_MASK (1 << 9)
184#define CCM_PCCR0_RTIC_OFFSET 8
185#define CCM_PCCR0_RTIC_MASK (1 << 8)
186#define CCM_PCCR0_SAHARA_OFFSET 7
187#define CCM_PCCR0_SAHARA_MASK (1 << 7)
188#define CCM_PCCR0_SCC_OFFSET 6
189#define CCM_PCCR0_SCC_MASK (1 << 6)
190#define CCM_PCCR0_SDHC1_OFFSET 5
191#define CCM_PCCR0_SDHC1_MASK (1 << 5)
192#define CCM_PCCR0_SDHC2_OFFSET 4
193#define CCM_PCCR0_SDHC2_MASK (1 << 4)
194#define CCM_PCCR0_SDHC3_OFFSET 3
195#define CCM_PCCR0_SDHC3_MASK (1 << 3)
196#define CCM_PCCR0_SLCDC_OFFSET 2
197#define CCM_PCCR0_SLCDC_MASK (1 << 2)
198#define CCM_PCCR0_SSI1_IPG_OFFSET 1
199#define CCM_PCCR0_SSI1_IPG_MASK (1 << 1)
200#define CCM_PCCR0_SSI2_IPG_OFFSET 0
201#define CCM_PCCR0_SSI2_IPG_MASK (1 << 0)
202
203#define CCM_PCCR1_UART1_OFFSET 31
204#define CCM_PCCR1_UART1_MASK (1 << 31)
205#define CCM_PCCR1_UART2_OFFSET 30
206#define CCM_PCCR1_UART2_MASK (1 << 30)
207#define CCM_PCCR1_UART3_OFFSET 29
208#define CCM_PCCR1_UART3_MASK (1 << 29)
209#define CCM_PCCR1_UART4_OFFSET 28
210#define CCM_PCCR1_UART4_MASK (1 << 28)
211#define CCM_PCCR1_UART5_OFFSET 27
212#define CCM_PCCR1_UART5_MASK (1 << 27)
213#define CCM_PCCR1_UART6_OFFSET 26
214#define CCM_PCCR1_UART6_MASK (1 << 26)
215#define CCM_PCCR1_USBOTG_OFFSET 25
216#define CCM_PCCR1_USBOTG_MASK (1 << 25)
217#define CCM_PCCR1_WDT_OFFSET 24
218#define CCM_PCCR1_WDT_MASK (1 << 24)
219#define CCM_PCCR1_HCLK_ATA_OFFSET 23
220#define CCM_PCCR1_HCLK_ATA_MASK (1 << 23)
221#define CCM_PCCR1_HCLK_BROM_OFFSET 22
222#define CCM_PCCR1_HCLK_BROM_MASK (1 << 22)
223#define CCM_PCCR1_HCLK_CSI_OFFSET 21
224#define CCM_PCCR1_HCLK_CSI_MASK (1 << 21)
225#define CCM_PCCR1_HCLK_DMA_OFFSET 20
226#define CCM_PCCR1_HCLK_DMA_MASK (1 << 20)
227#define CCM_PCCR1_HCLK_EMI_OFFSET 19
228#define CCM_PCCR1_HCLK_EMI_MASK (1 << 19)
229#define CCM_PCCR1_HCLK_EMMA_OFFSET 18
230#define CCM_PCCR1_HCLK_EMMA_MASK (1 << 18)
231#define CCM_PCCR1_HCLK_FEC_OFFSET 17
232#define CCM_PCCR1_HCLK_FEC_MASK (1 << 17)
233#define CCM_PCCR1_HCLK_VPU_OFFSET 16
234#define CCM_PCCR1_HCLK_VPU_MASK (1 << 16)
235#define CCM_PCCR1_HCLK_LCDC_OFFSET 15
236#define CCM_PCCR1_HCLK_LCDC_MASK (1 << 15)
237#define CCM_PCCR1_HCLK_RTIC_OFFSET 14
238#define CCM_PCCR1_HCLK_RTIC_MASK (1 << 14)
239#define CCM_PCCR1_HCLK_SAHARA_OFFSET 13
240#define CCM_PCCR1_HCLK_SAHARA_MASK (1 << 13)
241#define CCM_PCCR1_HCLK_SLCDC_OFFSET 12
242#define CCM_PCCR1_HCLK_SLCDC_MASK (1 << 12)
243#define CCM_PCCR1_HCLK_USBOTG_OFFSET 11
244#define CCM_PCCR1_HCLK_USBOTG_MASK (1 << 11)
245#define CCM_PCCR1_PERCLK1_OFFSET 10
246#define CCM_PCCR1_PERCLK1_MASK (1 << 10)
247#define CCM_PCCR1_PERCLK2_OFFSET 9
248#define CCM_PCCR1_PERCLK2_MASK (1 << 9)
249#define CCM_PCCR1_PERCLK3_OFFSET 8
250#define CCM_PCCR1_PERCLK3_MASK (1 << 8)
251#define CCM_PCCR1_PERCLK4_OFFSET 7
252#define CCM_PCCR1_PERCLK4_MASK (1 << 7)
253#define CCM_PCCR1_VPU_BAUD_OFFSET 6
254#define CCM_PCCR1_VPU_BAUD_MASK (1 << 6)
255#define CCM_PCCR1_SSI1_BAUD_OFFSET 5
256#define CCM_PCCR1_SSI1_BAUD_MASK (1 << 5)
257#define CCM_PCCR1_SSI2_BAUD_OFFSET 4
258#define CCM_PCCR1_SSI2_BAUD_MASK (1 << 4)
259#define CCM_PCCR1_NFC_BAUD_OFFSET 3
260#define CCM_PCCR1_NFC_BAUD_MASK (1 << 3)
261#define CCM_PCCR1_MSHC_BAUD_OFFSET 2
262#define CCM_PCCR1_MSHC_BAUD_MASK (1 << 2)
263
264#define CCM_CCSR_32KSR (1 << 15)
265#define CCM_CCSR_CLKMODE1 (1 << 9)
266#define CCM_CCSR_CLKMODE0 (1 << 8)
267#define CCM_CCSR_CLKOSEL_OFFSET 0
268#define CCM_CCSR_CLKOSEL_MASK 0x1f
269
270#define SYS_FMCR 0x14 /* Functional Muxing Control Reg */
271#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */
272
273#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
new file mode 100644
index 000000000000..a1f44c3c5315
--- /dev/null
+++ b/arch/arm/mach-mx2/devices.c
@@ -0,0 +1,231 @@
1/*
2 * Author: MontaVista Software, Inc.
3 * <source@mvista.com>
4 *
5 * Based on the OMAP devices.c
6 *
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
27 * MA 02110-1301, USA.
28 */
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/init.h>
32#include <linux/platform_device.h>
33#include <linux/gpio.h>
34
35#include <asm/hardware.h>
36
37/*
38 * Resource definition for the MXC IrDA
39 */
40static struct resource mxc_irda_resources[] = {
41 [0] = {
42 .start = UART3_BASE_ADDR,
43 .end = UART3_BASE_ADDR + SZ_4K - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = {
47 .start = MXC_INT_UART3,
48 .end = MXC_INT_UART3,
49 .flags = IORESOURCE_IRQ,
50 },
51};
52
53/* Platform Data for MXC IrDA */
54struct platform_device mxc_irda_device = {
55 .name = "mxc_irda",
56 .id = 0,
57 .num_resources = ARRAY_SIZE(mxc_irda_resources),
58 .resource = mxc_irda_resources,
59};
60
61/*
62 * General Purpose Timer
63 * - i.MX1: 2 timer (slighly different register handling)
64 * - i.MX21: 3 timer
65 * - i.MX27: 6 timer
66 */
67
68/* We use gpt0 as system timer, so do not add a device for this one */
69
70static struct resource timer1_resources[] = {
71 [0] = {
72 .start = GPT2_BASE_ADDR,
73 .end = GPT2_BASE_ADDR + 0x17,
74 .flags = IORESOURCE_MEM
75 },
76 [1] = {
77 .start = MXC_INT_GPT2,
78 .end = MXC_INT_GPT2,
79 .flags = IORESOURCE_IRQ,
80 }
81};
82
83struct platform_device mxc_gpt1 = {
84 .name = "imx_gpt",
85 .id = 1,
86 .num_resources = ARRAY_SIZE(timer1_resources),
87 .resource = timer1_resources
88};
89
90static struct resource timer2_resources[] = {
91 [0] = {
92 .start = GPT3_BASE_ADDR,
93 .end = GPT3_BASE_ADDR + 0x17,
94 .flags = IORESOURCE_MEM
95 },
96 [1] = {
97 .start = MXC_INT_GPT3,
98 .end = MXC_INT_GPT3,
99 .flags = IORESOURCE_IRQ,
100 }
101};
102
103struct platform_device mxc_gpt2 = {
104 .name = "imx_gpt",
105 .id = 2,
106 .num_resources = ARRAY_SIZE(timer2_resources),
107 .resource = timer2_resources
108};
109
110#ifdef CONFIG_MACH_MX27
111static struct resource timer3_resources[] = {
112 [0] = {
113 .start = GPT4_BASE_ADDR,
114 .end = GPT4_BASE_ADDR + 0x17,
115 .flags = IORESOURCE_MEM
116 },
117 [1] = {
118 .start = MXC_INT_GPT4,
119 .end = MXC_INT_GPT4,
120 .flags = IORESOURCE_IRQ,
121 }
122};
123
124struct platform_device mxc_gpt3 = {
125 .name = "imx_gpt",
126 .id = 3,
127 .num_resources = ARRAY_SIZE(timer3_resources),
128 .resource = timer3_resources
129};
130
131static struct resource timer4_resources[] = {
132 [0] = {
133 .start = GPT5_BASE_ADDR,
134 .end = GPT5_BASE_ADDR + 0x17,
135 .flags = IORESOURCE_MEM
136 },
137 [1] = {
138 .start = MXC_INT_GPT5,
139 .end = MXC_INT_GPT5,
140 .flags = IORESOURCE_IRQ,
141 }
142};
143
144struct platform_device mxc_gpt4 = {
145 .name = "imx_gpt",
146 .id = 4,
147 .num_resources = ARRAY_SIZE(timer4_resources),
148 .resource = timer4_resources
149};
150
151static struct resource timer5_resources[] = {
152 [0] = {
153 .start = GPT6_BASE_ADDR,
154 .end = GPT6_BASE_ADDR + 0x17,
155 .flags = IORESOURCE_MEM
156 },
157 [1] = {
158 .start = MXC_INT_GPT6,
159 .end = MXC_INT_GPT6,
160 .flags = IORESOURCE_IRQ,
161 }
162};
163
164struct platform_device mxc_gpt5 = {
165 .name = "imx_gpt",
166 .id = 5,
167 .num_resources = ARRAY_SIZE(timer5_resources),
168 .resource = timer5_resources
169};
170#endif
171
172/*
173 * Watchdog:
174 * - i.MX1
175 * - i.MX21
176 * - i.MX27
177 */
178static struct resource mxc_wdt_resources[] = {
179 {
180 .start = WDOG_BASE_ADDR,
181 .end = WDOG_BASE_ADDR + 0x30,
182 .flags = IORESOURCE_MEM,
183 },
184};
185
186struct platform_device mxc_wdt = {
187 .name = "mxc_wdt",
188 .id = 0,
189 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
190 .resource = mxc_wdt_resources,
191};
192
193/* GPIO port description */
194static struct mxc_gpio_port imx_gpio_ports[] = {
195 [0] = {
196 .chip.label = "gpio-0",
197 .irq = MXC_INT_GPIO,
198 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 0),
199 .virtual_irq_start = MXC_MAX_INT_LINES,
200 },
201 [1] = {
202 .chip.label = "gpio-1",
203 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 1),
204 .virtual_irq_start = MXC_MAX_INT_LINES + 32,
205 },
206 [2] = {
207 .chip.label = "gpio-2",
208 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 2),
209 .virtual_irq_start = MXC_MAX_INT_LINES + 64,
210 },
211 [3] = {
212 .chip.label = "gpio-3",
213 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 3),
214 .virtual_irq_start = MXC_MAX_INT_LINES + 96,
215 },
216 [4] = {
217 .chip.label = "gpio-4",
218 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 4),
219 .virtual_irq_start = MXC_MAX_INT_LINES + 128,
220 },
221 [5] = {
222 .chip.label = "gpio-5",
223 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 5),
224 .virtual_irq_start = MXC_MAX_INT_LINES + 160,
225 }
226};
227
228int __init mxc_register_gpios(void)
229{
230 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
231}
diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/generic.c
new file mode 100644
index 000000000000..07875cf00de9
--- /dev/null
+++ b/arch/arm/mach-mx2/generic.c
@@ -0,0 +1,74 @@
1/*
2 * generic.c
3 *
4 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#include <linux/mm.h>
22#include <linux/init.h>
23#include <asm/hardware.h>
24#include <asm/pgtable.h>
25#include <asm/mach/map.h>
26
27/* MX27 memory map definition */
28static struct map_desc mxc_io_desc[] __initdata = {
29 /*
30 * this fixed mapping covers:
31 * - AIPI1
32 * - AIPI2
33 * - AITC
34 * - ROM Patch
35 * - and some reserved space
36 */
37 {
38 .virtual = AIPI_BASE_ADDR_VIRT,
39 .pfn = __phys_to_pfn(AIPI_BASE_ADDR),
40 .length = AIPI_SIZE,
41 .type = MT_DEVICE
42 },
43 /*
44 * this fixed mapping covers:
45 * - CSI
46 * - ATA
47 */
48 {
49 .virtual = SAHB1_BASE_ADDR_VIRT,
50 .pfn = __phys_to_pfn(SAHB1_BASE_ADDR),
51 .length = SAHB1_SIZE,
52 .type = MT_DEVICE
53 },
54 /*
55 * this fixed mapping covers:
56 * - EMI
57 */
58 {
59 .virtual = X_MEMC_BASE_ADDR_VIRT,
60 .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR),
61 .length = X_MEMC_SIZE,
62 .type = MT_DEVICE
63 }
64};
65
66/*
67 * Initialize the memory map. It is called during the
68 * system startup to create static physical to virtual
69 * memory map for the IO modules.
70 */
71void __init mxc_map_io(void)
72{
73 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
74}
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c
new file mode 100644
index 000000000000..a9ff01fff137
--- /dev/null
+++ b/arch/arm/mach-mx2/mx27ads.c
@@ -0,0 +1,304 @@
1/*
2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/platform_device.h>
22#include <linux/mtd/mtd.h>
23#include <linux/mtd/map.h>
24#include <linux/mtd/partitions.h>
25#include <linux/mtd/physmap.h>
26#include <asm/arch/common.h>
27#include <asm/hardware.h>
28#include <asm/mach-types.h>
29#include <asm/mach/arch.h>
30#include <asm/mach/time.h>
31#include <asm/mach/map.h>
32#include <asm/arch/gpio.h>
33#include <asm/arch/imx-uart.h>
34#include <asm/arch/iomux-mx1-mx2.h>
35#include <asm/arch/board-mx27ads.h>
36
37/* ADS's NOR flash */
38static struct physmap_flash_data mx27ads_flash_data = {
39 .width = 2,
40};
41
42static struct resource mx27ads_flash_resource = {
43 .start = 0xc0000000,
44 .end = 0xc0000000 + 0x02000000 - 1,
45 .flags = IORESOURCE_MEM,
46
47};
48
49static struct platform_device mx27ads_nor_mtd_device = {
50 .name = "physmap-flash",
51 .id = 0,
52 .dev = {
53 .platform_data = &mx27ads_flash_data,
54 },
55 .num_resources = 1,
56 .resource = &mx27ads_flash_resource,
57};
58
59static int mxc_uart0_pins[] = {
60 PE12_PF_UART1_TXD,
61 PE13_PF_UART1_RXD,
62 PE14_PF_UART1_CTS,
63 PE15_PF_UART1_RTS
64};
65
66static int uart_mxc_port0_init(struct platform_device *pdev)
67{
68 return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
69 ARRAY_SIZE(mxc_uart0_pins),
70 MXC_GPIO_ALLOC_MODE_NORMAL, "UART0");
71}
72
73static int uart_mxc_port0_exit(struct platform_device *pdev)
74{
75 return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
76 ARRAY_SIZE(mxc_uart0_pins),
77 MXC_GPIO_ALLOC_MODE_RELEASE, "UART0");
78}
79
80static int mxc_uart1_pins[] = {
81 PE3_PF_UART2_CTS,
82 PE4_PF_UART2_RTS,
83 PE6_PF_UART2_TXD,
84 PE7_PF_UART2_RXD
85};
86
87static int uart_mxc_port1_init(struct platform_device *pdev)
88{
89 return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
90 ARRAY_SIZE(mxc_uart1_pins),
91 MXC_GPIO_ALLOC_MODE_NORMAL, "UART1");
92}
93
94static int uart_mxc_port1_exit(struct platform_device *pdev)
95{
96 return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
97 ARRAY_SIZE(mxc_uart1_pins),
98 MXC_GPIO_ALLOC_MODE_RELEASE, "UART1");
99}
100
101static int mxc_uart2_pins[] = {
102 PE8_PF_UART3_TXD,
103 PE9_PF_UART3_RXD,
104 PE10_PF_UART3_CTS,
105 PE11_PF_UART3_RTS
106};
107
108static int uart_mxc_port2_init(struct platform_device *pdev)
109{
110 return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
111 ARRAY_SIZE(mxc_uart2_pins),
112 MXC_GPIO_ALLOC_MODE_NORMAL, "UART2");
113}
114
115static int uart_mxc_port2_exit(struct platform_device *pdev)
116{
117 return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
118 ARRAY_SIZE(mxc_uart2_pins),
119 MXC_GPIO_ALLOC_MODE_RELEASE, "UART2");
120}
121
122static int mxc_uart3_pins[] = {
123 PB26_AF_UART4_RTS,
124 PB28_AF_UART4_TXD,
125 PB29_AF_UART4_CTS,
126 PB31_AF_UART4_RXD
127};
128
129static int uart_mxc_port3_init(struct platform_device *pdev)
130{
131 return mxc_gpio_setup_multiple_pins(mxc_uart3_pins,
132 ARRAY_SIZE(mxc_uart3_pins),
133 MXC_GPIO_ALLOC_MODE_NORMAL, "UART3");
134}
135
136static int uart_mxc_port3_exit(struct platform_device *pdev)
137{
138 return mxc_gpio_setup_multiple_pins(mxc_uart3_pins,
139 ARRAY_SIZE(mxc_uart3_pins),
140 MXC_GPIO_ALLOC_MODE_RELEASE, "UART3");
141}
142
143static int mxc_uart4_pins[] = {
144 PB18_AF_UART5_TXD,
145 PB19_AF_UART5_RXD,
146 PB20_AF_UART5_CTS,
147 PB21_AF_UART5_RTS
148};
149
150static int uart_mxc_port4_init(struct platform_device *pdev)
151{
152 return mxc_gpio_setup_multiple_pins(mxc_uart4_pins,
153 ARRAY_SIZE(mxc_uart4_pins),
154 MXC_GPIO_ALLOC_MODE_NORMAL, "UART4");
155}
156
157static int uart_mxc_port4_exit(struct platform_device *pdev)
158{
159 return mxc_gpio_setup_multiple_pins(mxc_uart4_pins,
160 ARRAY_SIZE(mxc_uart4_pins),
161 MXC_GPIO_ALLOC_MODE_RELEASE, "UART4");
162}
163
164static int mxc_uart5_pins[] = {
165 PB10_AF_UART6_TXD,
166 PB12_AF_UART6_CTS,
167 PB11_AF_UART6_RXD,
168 PB13_AF_UART6_RTS
169};
170
171static int uart_mxc_port5_init(struct platform_device *pdev)
172{
173 return mxc_gpio_setup_multiple_pins(mxc_uart5_pins,
174 ARRAY_SIZE(mxc_uart5_pins),
175 MXC_GPIO_ALLOC_MODE_NORMAL, "UART5");
176}
177
178static int uart_mxc_port5_exit(struct platform_device *pdev)
179{
180 return mxc_gpio_setup_multiple_pins(mxc_uart5_pins,
181 ARRAY_SIZE(mxc_uart5_pins),
182 MXC_GPIO_ALLOC_MODE_RELEASE, "UART5");
183}
184
185static struct platform_device *platform_devices[] __initdata = {
186 &mx27ads_nor_mtd_device,
187};
188
189static int mxc_fec_pins[] = {
190 PD0_AIN_FEC_TXD0,
191 PD1_AIN_FEC_TXD1,
192 PD2_AIN_FEC_TXD2,
193 PD3_AIN_FEC_TXD3,
194 PD4_AOUT_FEC_RX_ER,
195 PD5_AOUT_FEC_RXD1,
196 PD6_AOUT_FEC_RXD2,
197 PD7_AOUT_FEC_RXD3,
198 PD8_AF_FEC_MDIO,
199 PD9_AIN_FEC_MDC,
200 PD10_AOUT_FEC_CRS,
201 PD11_AOUT_FEC_TX_CLK,
202 PD12_AOUT_FEC_RXD0,
203 PD13_AOUT_FEC_RX_DV,
204 PD14_AOUT_FEC_CLR,
205 PD15_AOUT_FEC_COL,
206 PD16_AIN_FEC_TX_ER,
207 PF23_AIN_FEC_TX_EN
208};
209
210static void gpio_fec_active(void)
211{
212 mxc_gpio_setup_multiple_pins(mxc_fec_pins,
213 ARRAY_SIZE(mxc_fec_pins),
214 MXC_GPIO_ALLOC_MODE_NORMAL, "FEC");
215}
216
217static void gpio_fec_inactive(void)
218{
219 mxc_gpio_setup_multiple_pins(mxc_fec_pins,
220 ARRAY_SIZE(mxc_fec_pins),
221 MXC_GPIO_ALLOC_MODE_RELEASE, "FEC");
222}
223
224static struct imxuart_platform_data uart_pdata[] = {
225 {
226 .init = uart_mxc_port0_init,
227 .exit = uart_mxc_port0_exit,
228 .flags = IMXUART_HAVE_RTSCTS,
229 }, {
230 .init = uart_mxc_port1_init,
231 .exit = uart_mxc_port1_exit,
232 .flags = IMXUART_HAVE_RTSCTS,
233 }, {
234 .init = uart_mxc_port2_init,
235 .exit = uart_mxc_port2_exit,
236 .flags = IMXUART_HAVE_RTSCTS,
237 }, {
238 .init = uart_mxc_port3_init,
239 .exit = uart_mxc_port3_exit,
240 .flags = IMXUART_HAVE_RTSCTS,
241 }, {
242 .init = uart_mxc_port4_init,
243 .exit = uart_mxc_port4_exit,
244 .flags = IMXUART_HAVE_RTSCTS,
245 }, {
246 .init = uart_mxc_port5_init,
247 .exit = uart_mxc_port5_exit,
248 .flags = IMXUART_HAVE_RTSCTS,
249 },
250};
251
252static void __init mx27ads_board_init(void)
253{
254 int i;
255
256 gpio_fec_active();
257
258 for (i = 0; i < 6; i++)
259 imx_init_uart(i, &uart_pdata[i]);
260
261 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
262}
263
264static void __init mx27ads_timer_init(void)
265{
266 unsigned long fref = 26000000;
267
268 if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
269 fref = 27000000;
270
271 mxc_clocks_init(fref);
272 mxc_timer_init("gpt_clk.0");
273}
274
275struct sys_timer mx27ads_timer = {
276 .init = mx27ads_timer_init,
277};
278
279static struct map_desc mx27ads_io_desc[] __initdata = {
280 {
281 .virtual = PBC_BASE_ADDRESS,
282 .pfn = __phys_to_pfn(CS4_BASE_ADDR),
283 .length = SZ_1M,
284 .type = MT_DEVICE,
285 },
286};
287
288void __init mx27ads_map_io(void)
289{
290 mxc_map_io();
291 iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
292}
293
294MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
295 /* maintainer: Freescale Semiconductor, Inc. */
296 .phys_io = AIPI_BASE_ADDR,
297 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
298 .boot_params = PHYS_OFFSET + 0x100,
299 .map_io = mx27ads_map_io,
300 .init_irq = mxc_init_irq,
301 .init_machine = mx27ads_board_init,
302 .timer = &mx27ads_timer,
303MACHINE_END
304
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c
new file mode 100644
index 000000000000..a9a28f58e714
--- /dev/null
+++ b/arch/arm/mach-mx2/pcm038.c
@@ -0,0 +1,204 @@
1/*
2 * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/platform_device.h>
21#include <linux/mtd/physmap.h>
22#include <asm/mach/arch.h>
23#include <asm/mach-types.h>
24#include <asm/arch/common.h>
25#include <asm/hardware.h>
26#include <asm/arch/iomux-mx1-mx2.h>
27#include <asm/mach/time.h>
28#include <asm/arch/imx-uart.h>
29#include <asm/arch/board-pcm038.h>
30
31/*
32 * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
33 * 16 bit width
34 */
35static struct physmap_flash_data pcm038_flash_data = {
36 .width = 2,
37};
38
39static struct resource pcm038_flash_resource = {
40 .start = 0xc0000000,
41 .end = 0xc1ffffff,
42 .flags = IORESOURCE_MEM,
43};
44
45static struct platform_device pcm038_nor_mtd_device = {
46 .name = "physmap-flash",
47 .id = 0,
48 .dev = {
49 .platform_data = &pcm038_flash_data,
50 },
51 .num_resources = 1,
52 .resource = &pcm038_flash_resource,
53};
54
55static int mxc_uart0_pins[] = {
56 PE12_PF_UART1_TXD,
57 PE13_PF_UART1_RXD,
58 PE14_PF_UART1_CTS,
59 PE15_PF_UART1_RTS
60};
61
62static int uart_mxc_port0_init(struct platform_device *pdev)
63{
64 return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
65 ARRAY_SIZE(mxc_uart0_pins),
66 MXC_GPIO_ALLOC_MODE_NORMAL, "UART0");
67}
68
69static int uart_mxc_port0_exit(struct platform_device *pdev)
70{
71 return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
72 ARRAY_SIZE(mxc_uart0_pins),
73 MXC_GPIO_ALLOC_MODE_RELEASE, "UART0");
74}
75
76static int mxc_uart1_pins[] = {
77 PE3_PF_UART2_CTS,
78 PE4_PF_UART2_RTS,
79 PE6_PF_UART2_TXD,
80 PE7_PF_UART2_RXD
81};
82
83static int uart_mxc_port1_init(struct platform_device *pdev)
84{
85 return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
86 ARRAY_SIZE(mxc_uart1_pins),
87 MXC_GPIO_ALLOC_MODE_NORMAL, "UART1");
88}
89
90static int uart_mxc_port1_exit(struct platform_device *pdev)
91{
92 return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
93 ARRAY_SIZE(mxc_uart1_pins),
94 MXC_GPIO_ALLOC_MODE_RELEASE, "UART1");
95}
96
97static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS,
98 PE9_PF_UART3_RXD,
99 PE10_PF_UART3_CTS,
100 PE9_PF_UART3_RXD };
101
102static int uart_mxc_port2_init(struct platform_device *pdev)
103{
104 return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
105 ARRAY_SIZE(mxc_uart2_pins),
106 MXC_GPIO_ALLOC_MODE_NORMAL, "UART2");
107}
108
109static int uart_mxc_port2_exit(struct platform_device *pdev)
110{
111 return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
112 ARRAY_SIZE(mxc_uart2_pins),
113 MXC_GPIO_ALLOC_MODE_RELEASE, "UART2");
114}
115
116static struct imxuart_platform_data uart_pdata[] = {
117 {
118 .init = uart_mxc_port0_init,
119 .exit = uart_mxc_port0_exit,
120 .flags = IMXUART_HAVE_RTSCTS,
121 }, {
122 .init = uart_mxc_port1_init,
123 .exit = uart_mxc_port1_exit,
124 .flags = IMXUART_HAVE_RTSCTS,
125 }, {
126 .init = uart_mxc_port2_init,
127 .exit = uart_mxc_port2_exit,
128 .flags = IMXUART_HAVE_RTSCTS,
129 },
130};
131
132static int mxc_fec_pins[] = {
133 PD0_AIN_FEC_TXD0,
134 PD1_AIN_FEC_TXD1,
135 PD2_AIN_FEC_TXD2,
136 PD3_AIN_FEC_TXD3,
137 PD4_AOUT_FEC_RX_ER,
138 PD5_AOUT_FEC_RXD1,
139 PD6_AOUT_FEC_RXD2,
140 PD7_AOUT_FEC_RXD3,
141 PD8_AF_FEC_MDIO,
142 PD9_AIN_FEC_MDC,
143 PD10_AOUT_FEC_CRS,
144 PD11_AOUT_FEC_TX_CLK,
145 PD12_AOUT_FEC_RXD0,
146 PD13_AOUT_FEC_RX_DV,
147 PD14_AOUT_FEC_CLR,
148 PD15_AOUT_FEC_COL,
149 PD16_AIN_FEC_TX_ER,
150 PF23_AIN_FEC_TX_EN
151};
152
153static void gpio_fec_active(void)
154{
155 mxc_gpio_setup_multiple_pins(mxc_fec_pins,
156 ARRAY_SIZE(mxc_fec_pins),
157 MXC_GPIO_ALLOC_MODE_NORMAL, "FEC");
158}
159
160static void gpio_fec_inactive(void)
161{
162 mxc_gpio_setup_multiple_pins(mxc_fec_pins,
163 ARRAY_SIZE(mxc_fec_pins),
164 MXC_GPIO_ALLOC_MODE_RELEASE, "FEC");
165}
166
167static struct platform_device *platform_devices[] __initdata = {
168 &pcm038_nor_mtd_device,
169};
170
171static void __init pcm038_init(void)
172{
173 int i;
174 gpio_fec_active();
175
176 for (i = 0; i < 3; i++)
177 imx_init_uart(i, &uart_pdata[i]);
178
179 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
180
181#ifdef CONFIG_MACH_PCM970_BASEBOARD
182 pcm970_baseboard_init();
183#endif
184}
185
186static void __init pcm038_timer_init(void)
187{
188 mxc_clocks_init(26000000);
189 mxc_timer_init("gpt_clk.0");
190}
191
192struct sys_timer pcm038_timer = {
193 .init = pcm038_timer_init,
194};
195
196MACHINE_START(PCM038, "phyCORE-i.MX27")
197 .phys_io = AIPI_BASE_ADDR,
198 .io_pg_offst = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
199 .boot_params = PHYS_OFFSET + 0x100,
200 .map_io = mxc_map_io,
201 .init_irq = mxc_init_irq,
202 .init_machine = pcm038_init,
203 .timer = &pcm038_timer,
204MACHINE_END
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c
new file mode 100644
index 000000000000..028ac4d33684
--- /dev/null
+++ b/arch/arm/mach-mx2/pcm970-baseboard.c
@@ -0,0 +1,32 @@
1/*
2 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#include <linux/platform_device.h>
20#include <asm/hardware.h>
21#include <asm/mach-types.h>
22#include <asm/mach/arch.h>
23
24/*
25 * system init for baseboard usage. Will be called by pcm038 init.
26 *
27 * Add platform devices present on this baseboard and init
28 * them from CPU side as far as required to use them later on
29 */
30void __init pcm970_baseboard_init(void)
31{
32}
diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c
new file mode 100644
index 000000000000..570c02b8e5df
--- /dev/null
+++ b/arch/arm/mach-mx2/serial.c
@@ -0,0 +1,177 @@
1/*
2 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/serial.h>
23#include <asm/hardware.h>
24#include <asm/arch/imx-uart.h>
25
26static struct resource uart0[] = {
27 {
28 .start = UART1_BASE_ADDR,
29 .end = UART1_BASE_ADDR + 0x0B5,
30 .flags = IORESOURCE_MEM,
31 }, {
32 .start = MXC_INT_UART1,
33 .end = MXC_INT_UART1,
34 .flags = IORESOURCE_IRQ,
35 },
36};
37
38static struct platform_device mxc_uart_device0 = {
39 .name = "imx-uart",
40 .id = 0,
41 .resource = uart0,
42 .num_resources = ARRAY_SIZE(uart0),
43};
44
45static struct resource uart1[] = {
46 {
47 .start = UART2_BASE_ADDR,
48 .end = UART2_BASE_ADDR + 0x0B5,
49 .flags = IORESOURCE_MEM,
50 }, {
51 .start = MXC_INT_UART2,
52 .end = MXC_INT_UART2,
53 .flags = IORESOURCE_IRQ,
54 },
55};
56
57static struct platform_device mxc_uart_device1 = {
58 .name = "imx-uart",
59 .id = 1,
60 .resource = uart1,
61 .num_resources = ARRAY_SIZE(uart1),
62};
63
64static struct resource uart2[] = {
65 {
66 .start = UART3_BASE_ADDR,
67 .end = UART3_BASE_ADDR + 0x0B5,
68 .flags = IORESOURCE_MEM,
69 }, {
70 .start = MXC_INT_UART3,
71 .end = MXC_INT_UART3,
72 .flags = IORESOURCE_IRQ,
73 },
74};
75
76static struct platform_device mxc_uart_device2 = {
77 .name = "imx-uart",
78 .id = 2,
79 .resource = uart2,
80 .num_resources = ARRAY_SIZE(uart2),
81};
82
83static struct resource uart3[] = {
84 {
85 .start = UART4_BASE_ADDR,
86 .end = UART4_BASE_ADDR + 0x0B5,
87 .flags = IORESOURCE_MEM,
88 }, {
89 .start = MXC_INT_UART4,
90 .end = MXC_INT_UART4,
91 .flags = IORESOURCE_IRQ,
92 },
93};
94
95static struct platform_device mxc_uart_device3 = {
96 .name = "imx-uart",
97 .id = 3,
98 .resource = uart3,
99 .num_resources = ARRAY_SIZE(uart3),
100};
101
102static struct resource uart4[] = {
103 {
104 .start = UART5_BASE_ADDR,
105 .end = UART5_BASE_ADDR + 0x0B5,
106 .flags = IORESOURCE_MEM,
107 }, {
108 .start = MXC_INT_UART5,
109 .end = MXC_INT_UART5,
110 .flags = IORESOURCE_IRQ,
111 },
112};
113
114static struct platform_device mxc_uart_device4 = {
115 .name = "imx-uart",
116 .id = 4,
117 .resource = uart4,
118 .num_resources = ARRAY_SIZE(uart4),
119};
120
121static struct resource uart5[] = {
122 {
123 .start = UART6_BASE_ADDR,
124 .end = UART6_BASE_ADDR + 0x0B5,
125 .flags = IORESOURCE_MEM,
126 }, {
127 .start = MXC_INT_UART6,
128 .end = MXC_INT_UART6,
129 .flags = IORESOURCE_IRQ,
130 },
131};
132
133static struct platform_device mxc_uart_device5 = {
134 .name = "imx-uart",
135 .id = 5,
136 .resource = uart5,
137 .num_resources = ARRAY_SIZE(uart5),
138};
139
140/*
141 * Register only those UARTs that physically exists
142 */
143int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata)
144{
145 switch (uart_no) {
146 case 0:
147 mxc_uart_device0.dev.platform_data = pdata;
148 platform_device_register(&mxc_uart_device0);
149 break;
150 case 1:
151 mxc_uart_device1.dev.platform_data = pdata;
152 platform_device_register(&mxc_uart_device1);
153 break;
154#ifndef CONFIG_MXC_IRDA
155 case 2:
156 mxc_uart_device2.dev.platform_data = pdata;
157 platform_device_register(&mxc_uart_device2);
158 break;
159#endif
160 case 3:
161 mxc_uart_device3.dev.platform_data = pdata;
162 platform_device_register(&mxc_uart_device3);
163 break;
164 case 4:
165 mxc_uart_device4.dev.platform_data = pdata;
166 platform_device_register(&mxc_uart_device4);
167 break;
168 case 5:
169 mxc_uart_device5.dev.platform_data = pdata;
170 platform_device_register(&mxc_uart_device5);
171 break;
172 default:
173 return -ENODEV;
174 }
175
176 return 0;
177}
diff --git a/arch/arm/mach-mx2/system.c b/arch/arm/mach-mx2/system.c
new file mode 100644
index 000000000000..99304645299d
--- /dev/null
+++ b/arch/arm/mach-mx2/system.c
@@ -0,0 +1,63 @@
1/*
2 * Copyright (C) 1999 ARM Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/kernel.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25
26#include <asm/arch/hardware.h>
27#include <asm/proc-fns.h>
28#include <asm/system.h>
29
30/*
31 * Put the CPU into idle mode. It is called by default_idle()
32 * in process.c file.
33 */
34void arch_idle(void)
35{
36 /*
37 * This should do all the clock switching
38 * and wait for interrupt tricks.
39 */
40 cpu_do_idle();
41}
42
43#define WDOG_WCR_REG IO_ADDRESS(WDOG_BASE_ADDR)
44#define WDOG_WCR_SRS (1 << 4)
45
46/*
47 * Reset the system. It is called by machine_restart().
48 */
49void arch_reset(char mode)
50{
51 struct clk *clk;
52
53 clk = clk_get(NULL, "wdog_clk");
54 if (!clk) {
55 printk(KERN_ERR"Cannot activate the watchdog. Giving up\n");
56 return;
57 }
58
59 clk_enable(clk);
60
61 /* Assert SRS signal */
62 __raw_writew(__raw_readw(WDOG_WCR_REG) & ~WDOG_WCR_SRS, WDOG_WCR_REG);
63}
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 5fe8606cac08..db9431dee1b4 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -8,5 +8,18 @@ config MACH_MX31ADS
8 Include support for MX31ADS platform. This includes specific 8 Include support for MX31ADS platform. This includes specific
9 configurations for the board and its peripherals. 9 configurations for the board and its peripherals.
10 10
11config MACH_PCM037
12 bool "Support Phytec pcm037 platforms"
13 help
14 Include support for Phytec pcm037 platform. This includes
15 specific configurations for the board and its peripherals.
16
17config MACH_MX31LITE
18 bool "Support MX31 LITEKIT (LogicPD)"
19 default n
20 help
21 Include support for MX31 LITEKIT platform. This includes specific
22 configurations for the board and its peripherals.
23
11endmenu 24endmenu
12 25
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index cbec997f332a..8b21abb71fb0 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -4,5 +4,7 @@
4 4
5# Object file lists. 5# Object file lists.
6 6
7obj-y := mm.o time.o 7obj-y := mm.o clock.o devices.o iomux.o
8obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o 8obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o
9obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o
10obj-$(CONFIG_MACH_PCM037) += pcm037.o
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c
new file mode 100644
index 000000000000..2f3635943e70
--- /dev/null
+++ b/arch/arm/mach-mx3/clock.c
@@ -0,0 +1,1147 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/module.h>
21#include <linux/spinlock.h>
22#include <linux/delay.h>
23#include <linux/clk.h>
24#include <linux/err.h>
25#include <linux/io.h>
26#include <asm/arch/clock.h>
27#include <asm/div64.h>
28
29#include "crm_regs.h"
30
31#define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */
32
33static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
34{
35 u32 min_pre, temp_pre, old_err, err;
36
37 if (div >= 512) {
38 *pre = 8;
39 *post = 64;
40 } else if (div >= 64) {
41 min_pre = (div - 1) / 64 + 1;
42 old_err = 8;
43 for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
44 err = div % temp_pre;
45 if (err == 0) {
46 *pre = temp_pre;
47 break;
48 }
49 err = temp_pre - err;
50 if (err < old_err) {
51 old_err = err;
52 *pre = temp_pre;
53 }
54 }
55 *post = (div + *pre - 1) / *pre;
56 } else if (div <= 8) {
57 *pre = div;
58 *post = 1;
59 } else {
60 *pre = 1;
61 *post = div;
62 }
63}
64
65static struct clk mcu_pll_clk;
66static struct clk mcu_main_clk;
67static struct clk usb_pll_clk;
68static struct clk serial_pll_clk;
69static struct clk ipg_clk;
70static struct clk ckih_clk;
71static struct clk ahb_clk;
72
73static int _clk_enable(struct clk *clk)
74{
75 u32 reg;
76
77 reg = __raw_readl(clk->enable_reg);
78 reg |= 3 << clk->enable_shift;
79 __raw_writel(reg, clk->enable_reg);
80
81 return 0;
82}
83
84static void _clk_disable(struct clk *clk)
85{
86 u32 reg;
87
88 reg = __raw_readl(clk->enable_reg);
89 reg &= ~(3 << clk->enable_shift);
90 __raw_writel(reg, clk->enable_reg);
91}
92
93static void _clk_emi_disable(struct clk *clk)
94{
95 u32 reg;
96
97 reg = __raw_readl(clk->enable_reg);
98 reg &= ~(3 << clk->enable_shift);
99 reg |= (1 << clk->enable_shift);
100 __raw_writel(reg, clk->enable_reg);
101}
102
103static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
104{
105 u32 reg;
106 signed long pd = 1; /* Pre-divider */
107 signed long mfi; /* Multiplication Factor (Integer part) */
108 signed long mfn; /* Multiplication Factor (Integer part) */
109 signed long mfd; /* Multiplication Factor (Denominator Part) */
110 signed long tmp;
111 u32 ref_freq = clk_get_rate(clk->parent);
112
113 while (((ref_freq / pd) * 10) > rate)
114 pd++;
115
116 if ((ref_freq / pd) < PRE_DIV_MIN_FREQ)
117 return -EINVAL;
118
119 /* the ref_freq/2 in the following is to round up */
120 mfi = (((rate / 2) * pd) + (ref_freq / 2)) / ref_freq;
121 if (mfi < 5 || mfi > 15)
122 return -EINVAL;
123
124 /* pick a mfd value that will work
125 * then solve for mfn */
126 mfd = ref_freq / 50000;
127
128 /*
129 * pll_freq * pd * mfd
130 * mfn = -------------------- - (mfi * mfd)
131 * 2 * ref_freq
132 */
133 /* the tmp/2 is for rounding */
134 tmp = ref_freq / 10000;
135 mfn =
136 ((((((rate / 2) + (tmp / 2)) / tmp) * pd) * mfd) / 10000) -
137 (mfi * mfd);
138
139 mfn = mfn & 0x3ff;
140 pd--;
141 mfd--;
142
143 /* Change the Pll value */
144 reg = (mfi << MXC_CCM_PCTL_MFI_OFFSET) |
145 (mfn << MXC_CCM_PCTL_MFN_OFFSET) |
146 (mfd << MXC_CCM_PCTL_MFD_OFFSET) | (pd << MXC_CCM_PCTL_PD_OFFSET);
147
148 if (clk == &mcu_pll_clk)
149 __raw_writel(reg, MXC_CCM_MPCTL);
150 else if (clk == &usb_pll_clk)
151 __raw_writel(reg, MXC_CCM_UPCTL);
152 else if (clk == &serial_pll_clk)
153 __raw_writel(reg, MXC_CCM_SRPCTL);
154
155 return 0;
156}
157
158static unsigned long _clk_pll_get_rate(struct clk *clk)
159{
160 long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
161 unsigned long reg, ccmr;
162 s64 temp;
163 unsigned int prcs;
164
165 ccmr = __raw_readl(MXC_CCM_CCMR);
166 prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
167 if (prcs == 0x1)
168 ref_clk = CKIL_CLK_FREQ * 1024;
169 else
170 ref_clk = clk_get_rate(&ckih_clk);
171
172 if (clk == &mcu_pll_clk) {
173 if ((ccmr & MXC_CCM_CCMR_MPE) == 0)
174 return ref_clk;
175 if ((ccmr & MXC_CCM_CCMR_MDS) != 0)
176 return ref_clk;
177 reg = __raw_readl(MXC_CCM_MPCTL);
178 } else if (clk == &usb_pll_clk)
179 reg = __raw_readl(MXC_CCM_UPCTL);
180 else if (clk == &serial_pll_clk)
181 reg = __raw_readl(MXC_CCM_SRPCTL);
182 else {
183 BUG();
184 return 0;
185 }
186
187 pdf = (reg & MXC_CCM_PCTL_PD_MASK) >> MXC_CCM_PCTL_PD_OFFSET;
188 mfd = (reg & MXC_CCM_PCTL_MFD_MASK) >> MXC_CCM_PCTL_MFD_OFFSET;
189 mfi = (reg & MXC_CCM_PCTL_MFI_MASK) >> MXC_CCM_PCTL_MFI_OFFSET;
190 mfi = (mfi <= 5) ? 5 : mfi;
191 mfn = mfn_abs = reg & MXC_CCM_PCTL_MFN_MASK;
192
193 if (mfn >= 0x200) {
194 mfn |= 0xFFFFFE00;
195 mfn_abs = -mfn;
196 }
197
198 ref_clk *= 2;
199 ref_clk /= pdf + 1;
200
201 temp = (u64) ref_clk * mfn_abs;
202 do_div(temp, mfd + 1);
203 if (mfn < 0)
204 temp = -temp;
205 temp = (ref_clk * mfi) + temp;
206
207 return temp;
208}
209
210static int _clk_usb_pll_enable(struct clk *clk)
211{
212 u32 reg;
213
214 reg = __raw_readl(MXC_CCM_CCMR);
215 reg |= MXC_CCM_CCMR_UPE;
216 __raw_writel(reg, MXC_CCM_CCMR);
217
218 /* No lock bit on MX31, so using max time from spec */
219 udelay(80);
220
221 return 0;
222}
223
224static void _clk_usb_pll_disable(struct clk *clk)
225{
226 u32 reg;
227
228 reg = __raw_readl(MXC_CCM_CCMR);
229 reg &= ~MXC_CCM_CCMR_UPE;
230 __raw_writel(reg, MXC_CCM_CCMR);
231}
232
233static int _clk_serial_pll_enable(struct clk *clk)
234{
235 u32 reg;
236
237 reg = __raw_readl(MXC_CCM_CCMR);
238 reg |= MXC_CCM_CCMR_SPE;
239 __raw_writel(reg, MXC_CCM_CCMR);
240
241 /* No lock bit on MX31, so using max time from spec */
242 udelay(80);
243
244 return 0;
245}
246
247static void _clk_serial_pll_disable(struct clk *clk)
248{
249 u32 reg;
250
251 reg = __raw_readl(MXC_CCM_CCMR);
252 reg &= ~MXC_CCM_CCMR_SPE;
253 __raw_writel(reg, MXC_CCM_CCMR);
254}
255
256#define PDR0(mask, off) ((__raw_readl(MXC_CCM_PDR0) & mask) >> off)
257#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
258#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)
259
260static unsigned long _clk_mcu_main_get_rate(struct clk *clk)
261{
262 u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
263
264 if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL)
265 return clk_get_rate(&serial_pll_clk);
266 else
267 return clk_get_rate(&mcu_pll_clk);
268}
269
270static unsigned long _clk_hclk_get_rate(struct clk *clk)
271{
272 unsigned long max_pdf;
273
274 max_pdf = PDR0(MXC_CCM_PDR0_MAX_PODF_MASK,
275 MXC_CCM_PDR0_MAX_PODF_OFFSET);
276 return clk_get_rate(clk->parent) / (max_pdf + 1);
277}
278
279static unsigned long _clk_ipg_get_rate(struct clk *clk)
280{
281 unsigned long ipg_pdf;
282
283 ipg_pdf = PDR0(MXC_CCM_PDR0_IPG_PODF_MASK,
284 MXC_CCM_PDR0_IPG_PODF_OFFSET);
285 return clk_get_rate(clk->parent) / (ipg_pdf + 1);
286}
287
288static unsigned long _clk_nfc_get_rate(struct clk *clk)
289{
290 unsigned long nfc_pdf;
291
292 nfc_pdf = PDR0(MXC_CCM_PDR0_NFC_PODF_MASK,
293 MXC_CCM_PDR0_NFC_PODF_OFFSET);
294 return clk_get_rate(clk->parent) / (nfc_pdf + 1);
295}
296
297static unsigned long _clk_hsp_get_rate(struct clk *clk)
298{
299 unsigned long hsp_pdf;
300
301 hsp_pdf = PDR0(MXC_CCM_PDR0_HSP_PODF_MASK,
302 MXC_CCM_PDR0_HSP_PODF_OFFSET);
303 return clk_get_rate(clk->parent) / (hsp_pdf + 1);
304}
305
306static unsigned long _clk_usb_get_rate(struct clk *clk)
307{
308 unsigned long usb_pdf, usb_prepdf;
309
310 usb_pdf = PDR1(MXC_CCM_PDR1_USB_PODF_MASK,
311 MXC_CCM_PDR1_USB_PODF_OFFSET);
312 usb_prepdf = PDR1(MXC_CCM_PDR1_USB_PRDF_MASK,
313 MXC_CCM_PDR1_USB_PRDF_OFFSET);
314 return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
315}
316
317static unsigned long _clk_csi_get_rate(struct clk *clk)
318{
319 u32 reg, pre, post;
320
321 reg = __raw_readl(MXC_CCM_PDR0);
322 pre = (reg & MXC_CCM_PDR0_CSI_PRDF_MASK) >>
323 MXC_CCM_PDR0_CSI_PRDF_OFFSET;
324 pre++;
325 post = (reg & MXC_CCM_PDR0_CSI_PODF_MASK) >>
326 MXC_CCM_PDR0_CSI_PODF_OFFSET;
327 post++;
328 return clk_get_rate(clk->parent) / (pre * post);
329}
330
331static unsigned long _clk_csi_round_rate(struct clk *clk, unsigned long rate)
332{
333 u32 pre, post, parent = clk_get_rate(clk->parent);
334 u32 div = parent / rate;
335
336 if (parent % rate)
337 div++;
338
339 __calc_pre_post_dividers(div, &pre, &post);
340
341 return parent / (pre * post);
342}
343
344static int _clk_csi_set_rate(struct clk *clk, unsigned long rate)
345{
346 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
347
348 div = parent / rate;
349
350 if ((parent / div) != rate)
351 return -EINVAL;
352
353 __calc_pre_post_dividers(div, &pre, &post);
354
355 /* Set CSI clock divider */
356 reg = __raw_readl(MXC_CCM_PDR0) &
357 ~(MXC_CCM_PDR0_CSI_PODF_MASK | MXC_CCM_PDR0_CSI_PRDF_MASK);
358 reg |= (post - 1) << MXC_CCM_PDR0_CSI_PODF_OFFSET;
359 reg |= (pre - 1) << MXC_CCM_PDR0_CSI_PRDF_OFFSET;
360 __raw_writel(reg, MXC_CCM_PDR0);
361
362 return 0;
363}
364
365static unsigned long _clk_per_get_rate(struct clk *clk)
366{
367 unsigned long per_pdf;
368
369 per_pdf = PDR0(MXC_CCM_PDR0_PER_PODF_MASK,
370 MXC_CCM_PDR0_PER_PODF_OFFSET);
371 return clk_get_rate(clk->parent) / (per_pdf + 1);
372}
373
374static unsigned long _clk_ssi1_get_rate(struct clk *clk)
375{
376 unsigned long ssi1_pdf, ssi1_prepdf;
377
378 ssi1_pdf = PDR1(MXC_CCM_PDR1_SSI1_PODF_MASK,
379 MXC_CCM_PDR1_SSI1_PODF_OFFSET);
380 ssi1_prepdf = PDR1(MXC_CCM_PDR1_SSI1_PRE_PODF_MASK,
381 MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET);
382 return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
383}
384
385static unsigned long _clk_ssi2_get_rate(struct clk *clk)
386{
387 unsigned long ssi2_pdf, ssi2_prepdf;
388
389 ssi2_pdf = PDR1(MXC_CCM_PDR1_SSI2_PODF_MASK,
390 MXC_CCM_PDR1_SSI2_PODF_OFFSET);
391 ssi2_prepdf = PDR1(MXC_CCM_PDR1_SSI2_PRE_PODF_MASK,
392 MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET);
393 return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
394}
395
396static unsigned long _clk_firi_get_rate(struct clk *clk)
397{
398 unsigned long firi_pdf, firi_prepdf;
399
400 firi_pdf = PDR1(MXC_CCM_PDR1_FIRI_PODF_MASK,
401 MXC_CCM_PDR1_FIRI_PODF_OFFSET);
402 firi_prepdf = PDR1(MXC_CCM_PDR1_FIRI_PRE_PODF_MASK,
403 MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET);
404 return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
405}
406
407static unsigned long _clk_firi_round_rate(struct clk *clk, unsigned long rate)
408{
409 u32 pre, post;
410 u32 parent = clk_get_rate(clk->parent);
411 u32 div = parent / rate;
412
413 if (parent % rate)
414 div++;
415
416 __calc_pre_post_dividers(div, &pre, &post);
417
418 return parent / (pre * post);
419
420}
421
422static int _clk_firi_set_rate(struct clk *clk, unsigned long rate)
423{
424 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
425
426 div = parent / rate;
427
428 if ((parent / div) != rate)
429 return -EINVAL;
430
431 __calc_pre_post_dividers(div, &pre, &post);
432
433 /* Set FIRI clock divider */
434 reg = __raw_readl(MXC_CCM_PDR1) &
435 ~(MXC_CCM_PDR1_FIRI_PODF_MASK | MXC_CCM_PDR1_FIRI_PRE_PODF_MASK);
436 reg |= (pre - 1) << MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET;
437 reg |= (post - 1) << MXC_CCM_PDR1_FIRI_PODF_OFFSET;
438 __raw_writel(reg, MXC_CCM_PDR1);
439
440 return 0;
441}
442
443static unsigned long _clk_mbx_get_rate(struct clk *clk)
444{
445 return clk_get_rate(clk->parent) / 2;
446}
447
448static unsigned long _clk_mstick1_get_rate(struct clk *clk)
449{
450 unsigned long msti_pdf;
451
452 msti_pdf = PDR2(MXC_CCM_PDR2_MST1_PDF_MASK,
453 MXC_CCM_PDR2_MST1_PDF_OFFSET);
454 return clk_get_rate(clk->parent) / (msti_pdf + 1);
455}
456
457static unsigned long _clk_mstick2_get_rate(struct clk *clk)
458{
459 unsigned long msti_pdf;
460
461 msti_pdf = PDR2(MXC_CCM_PDR2_MST2_PDF_MASK,
462 MXC_CCM_PDR2_MST2_PDF_OFFSET);
463 return clk_get_rate(clk->parent) / (msti_pdf + 1);
464}
465
466static unsigned long ckih_rate;
467
468static unsigned long clk_ckih_get_rate(struct clk *clk)
469{
470 return ckih_rate;
471}
472
473static struct clk ckih_clk = {
474 .name = "ckih",
475 .get_rate = clk_ckih_get_rate,
476};
477
478static unsigned long clk_ckil_get_rate(struct clk *clk)
479{
480 return CKIL_CLK_FREQ;
481}
482
483static struct clk ckil_clk = {
484 .name = "ckil",
485 .get_rate = clk_ckil_get_rate,
486};
487
488static struct clk mcu_pll_clk = {
489 .name = "mcu_pll",
490 .parent = &ckih_clk,
491 .set_rate = _clk_pll_set_rate,
492 .get_rate = _clk_pll_get_rate,
493};
494
495static struct clk mcu_main_clk = {
496 .name = "mcu_main_clk",
497 .parent = &mcu_pll_clk,
498 .get_rate = _clk_mcu_main_get_rate,
499};
500
501static struct clk serial_pll_clk = {
502 .name = "serial_pll",
503 .parent = &ckih_clk,
504 .set_rate = _clk_pll_set_rate,
505 .get_rate = _clk_pll_get_rate,
506 .enable = _clk_serial_pll_enable,
507 .disable = _clk_serial_pll_disable,
508};
509
510static struct clk usb_pll_clk = {
511 .name = "usb_pll",
512 .parent = &ckih_clk,
513 .set_rate = _clk_pll_set_rate,
514 .get_rate = _clk_pll_get_rate,
515 .enable = _clk_usb_pll_enable,
516 .disable = _clk_usb_pll_disable,
517};
518
519static struct clk ahb_clk = {
520 .name = "ahb_clk",
521 .parent = &mcu_main_clk,
522 .get_rate = _clk_hclk_get_rate,
523};
524
525static struct clk per_clk = {
526 .name = "per_clk",
527 .parent = &usb_pll_clk,
528 .get_rate = _clk_per_get_rate,
529};
530
531static struct clk perclk_clk = {
532 .name = "perclk_clk",
533 .parent = &ipg_clk,
534};
535
536static struct clk cspi_clk[] = {
537 {
538 .name = "cspi_clk",
539 .id = 0,
540 .parent = &ipg_clk,
541 .enable = _clk_enable,
542 .enable_reg = MXC_CCM_CGR2,
543 .enable_shift = MXC_CCM_CGR2_CSPI1_OFFSET,
544 .disable = _clk_disable,},
545 {
546 .name = "cspi_clk",
547 .id = 1,
548 .parent = &ipg_clk,
549 .enable = _clk_enable,
550 .enable_reg = MXC_CCM_CGR2,
551 .enable_shift = MXC_CCM_CGR2_CSPI2_OFFSET,
552 .disable = _clk_disable,},
553 {
554 .name = "cspi_clk",
555 .id = 2,
556 .parent = &ipg_clk,
557 .enable = _clk_enable,
558 .enable_reg = MXC_CCM_CGR0,
559 .enable_shift = MXC_CCM_CGR0_CSPI3_OFFSET,
560 .disable = _clk_disable,},
561};
562
563static struct clk ipg_clk = {
564 .name = "ipg_clk",
565 .parent = &ahb_clk,
566 .get_rate = _clk_ipg_get_rate,
567};
568
569static struct clk emi_clk = {
570 .name = "emi_clk",
571 .parent = &ahb_clk,
572 .enable = _clk_enable,
573 .enable_reg = MXC_CCM_CGR2,
574 .enable_shift = MXC_CCM_CGR2_EMI_OFFSET,
575 .disable = _clk_emi_disable,
576};
577
578static struct clk gpt_clk = {
579 .name = "gpt_clk",
580 .parent = &perclk_clk,
581 .enable = _clk_enable,
582 .enable_reg = MXC_CCM_CGR0,
583 .enable_shift = MXC_CCM_CGR0_GPT_OFFSET,
584 .disable = _clk_disable,
585};
586
587static struct clk pwm_clk = {
588 .name = "pwm_clk",
589 .parent = &perclk_clk,
590 .enable = _clk_enable,
591 .enable_reg = MXC_CCM_CGR0,
592 .enable_shift = MXC_CCM_CGR1_PWM_OFFSET,
593 .disable = _clk_disable,
594};
595
596static struct clk epit_clk[] = {
597 {
598 .name = "epit_clk",
599 .id = 0,
600 .parent = &perclk_clk,
601 .enable = _clk_enable,
602 .enable_reg = MXC_CCM_CGR0,
603 .enable_shift = MXC_CCM_CGR0_EPIT1_OFFSET,
604 .disable = _clk_disable,},
605 {
606 .name = "epit_clk",
607 .id = 1,
608 .parent = &perclk_clk,
609 .enable = _clk_enable,
610 .enable_reg = MXC_CCM_CGR0,
611 .enable_shift = MXC_CCM_CGR0_EPIT2_OFFSET,
612 .disable = _clk_disable,},
613};
614
615static struct clk nfc_clk = {
616 .name = "nfc_clk",
617 .parent = &ahb_clk,
618 .get_rate = _clk_nfc_get_rate,
619};
620
621static struct clk scc_clk = {
622 .name = "scc_clk",
623 .parent = &ipg_clk,
624};
625
626static struct clk ipu_clk = {
627 .name = "ipu_clk",
628 .parent = &mcu_main_clk,
629 .get_rate = _clk_hsp_get_rate,
630 .enable = _clk_enable,
631 .enable_reg = MXC_CCM_CGR1,
632 .enable_shift = MXC_CCM_CGR1_IPU_OFFSET,
633 .disable = _clk_disable,
634};
635
636static struct clk kpp_clk = {
637 .name = "kpp_clk",
638 .parent = &ipg_clk,
639 .enable = _clk_enable,
640 .enable_reg = MXC_CCM_CGR1,
641 .enable_shift = MXC_CCM_CGR1_KPP_OFFSET,
642 .disable = _clk_disable,
643};
644
645static struct clk wdog_clk = {
646 .name = "wdog_clk",
647 .parent = &ipg_clk,
648 .enable = _clk_enable,
649 .enable_reg = MXC_CCM_CGR1,
650 .enable_shift = MXC_CCM_CGR1_WDOG_OFFSET,
651 .disable = _clk_disable,
652};
653static struct clk rtc_clk = {
654 .name = "rtc_clk",
655 .parent = &ipg_clk,
656 .enable = _clk_enable,
657 .enable_reg = MXC_CCM_CGR1,
658 .enable_shift = MXC_CCM_CGR1_RTC_OFFSET,
659 .disable = _clk_disable,
660};
661
662static struct clk usb_clk[] = {
663 {
664 .name = "usb_clk",
665 .parent = &usb_pll_clk,
666 .get_rate = _clk_usb_get_rate,},
667 {
668 .name = "usb_ahb_clk",
669 .parent = &ahb_clk,
670 .enable = _clk_enable,
671 .enable_reg = MXC_CCM_CGR1,
672 .enable_shift = MXC_CCM_CGR1_USBOTG_OFFSET,
673 .disable = _clk_disable,},
674};
675
676static struct clk csi_clk = {
677 .name = "csi_clk",
678 .parent = &serial_pll_clk,
679 .get_rate = _clk_csi_get_rate,
680 .round_rate = _clk_csi_round_rate,
681 .set_rate = _clk_csi_set_rate,
682 .enable = _clk_enable,
683 .enable_reg = MXC_CCM_CGR1,
684 .enable_shift = MXC_CCM_CGR1_CSI_OFFSET,
685 .disable = _clk_disable,
686};
687
688static struct clk uart_clk[] = {
689 {
690 .name = "uart_clk",
691 .id = 0,
692 .parent = &perclk_clk,
693 .enable = _clk_enable,
694 .enable_reg = MXC_CCM_CGR0,
695 .enable_shift = MXC_CCM_CGR0_UART1_OFFSET,
696 .disable = _clk_disable,},
697 {
698 .name = "uart_clk",
699 .id = 1,
700 .parent = &perclk_clk,
701 .enable = _clk_enable,
702 .enable_reg = MXC_CCM_CGR0,
703 .enable_shift = MXC_CCM_CGR0_UART2_OFFSET,
704 .disable = _clk_disable,},
705 {
706 .name = "uart_clk",
707 .id = 2,
708 .parent = &perclk_clk,
709 .enable = _clk_enable,
710 .enable_reg = MXC_CCM_CGR1,
711 .enable_shift = MXC_CCM_CGR1_UART3_OFFSET,
712 .disable = _clk_disable,},
713 {
714 .name = "uart_clk",
715 .id = 3,
716 .parent = &perclk_clk,
717 .enable = _clk_enable,
718 .enable_reg = MXC_CCM_CGR1,
719 .enable_shift = MXC_CCM_CGR1_UART4_OFFSET,
720 .disable = _clk_disable,},
721 {
722 .name = "uart_clk",
723 .id = 4,
724 .parent = &perclk_clk,
725 .enable = _clk_enable,
726 .enable_reg = MXC_CCM_CGR1,
727 .enable_shift = MXC_CCM_CGR1_UART5_OFFSET,
728 .disable = _clk_disable,},
729};
730
731static struct clk i2c_clk[] = {
732 {
733 .name = "i2c_clk",
734 .id = 0,
735 .parent = &perclk_clk,
736 .enable = _clk_enable,
737 .enable_reg = MXC_CCM_CGR0,
738 .enable_shift = MXC_CCM_CGR0_I2C1_OFFSET,
739 .disable = _clk_disable,},
740 {
741 .name = "i2c_clk",
742 .id = 1,
743 .parent = &perclk_clk,
744 .enable = _clk_enable,
745 .enable_reg = MXC_CCM_CGR0,
746 .enable_shift = MXC_CCM_CGR0_I2C2_OFFSET,
747 .disable = _clk_disable,},
748 {
749 .name = "i2c_clk",
750 .id = 2,
751 .parent = &perclk_clk,
752 .enable = _clk_enable,
753 .enable_reg = MXC_CCM_CGR0,
754 .enable_shift = MXC_CCM_CGR0_I2C3_OFFSET,
755 .disable = _clk_disable,},
756};
757
758static struct clk owire_clk = {
759 .name = "owire_clk",
760 .parent = &perclk_clk,
761 .enable_reg = MXC_CCM_CGR1,
762 .enable_shift = MXC_CCM_CGR1_OWIRE_OFFSET,
763 .enable = _clk_enable,
764 .disable = _clk_disable,
765};
766
767static struct clk sdhc_clk[] = {
768 {
769 .name = "sdhc_clk",
770 .id = 0,
771 .parent = &perclk_clk,
772 .enable = _clk_enable,
773 .enable_reg = MXC_CCM_CGR0,
774 .enable_shift = MXC_CCM_CGR0_SD_MMC1_OFFSET,
775 .disable = _clk_disable,},
776 {
777 .name = "sdhc_clk",
778 .id = 1,
779 .parent = &perclk_clk,
780 .enable = _clk_enable,
781 .enable_reg = MXC_CCM_CGR0,
782 .enable_shift = MXC_CCM_CGR0_SD_MMC2_OFFSET,
783 .disable = _clk_disable,},
784};
785
786static struct clk ssi_clk[] = {
787 {
788 .name = "ssi_clk",
789 .parent = &serial_pll_clk,
790 .get_rate = _clk_ssi1_get_rate,
791 .enable = _clk_enable,
792 .enable_reg = MXC_CCM_CGR0,
793 .enable_shift = MXC_CCM_CGR0_SSI1_OFFSET,
794 .disable = _clk_disable,},
795 {
796 .name = "ssi_clk",
797 .id = 1,
798 .parent = &serial_pll_clk,
799 .get_rate = _clk_ssi2_get_rate,
800 .enable = _clk_enable,
801 .enable_reg = MXC_CCM_CGR2,
802 .enable_shift = MXC_CCM_CGR2_SSI2_OFFSET,
803 .disable = _clk_disable,},
804};
805
806static struct clk firi_clk = {
807 .name = "firi_clk",
808 .parent = &usb_pll_clk,
809 .round_rate = _clk_firi_round_rate,
810 .set_rate = _clk_firi_set_rate,
811 .get_rate = _clk_firi_get_rate,
812 .enable = _clk_enable,
813 .enable_reg = MXC_CCM_CGR2,
814 .enable_shift = MXC_CCM_CGR2_FIRI_OFFSET,
815 .disable = _clk_disable,
816};
817
818static struct clk ata_clk = {
819 .name = "ata_clk",
820 .parent = &ipg_clk,
821 .enable = _clk_enable,
822 .enable_reg = MXC_CCM_CGR0,
823 .enable_shift = MXC_CCM_CGR0_ATA_OFFSET,
824 .disable = _clk_disable,
825};
826
827static struct clk mbx_clk = {
828 .name = "mbx_clk",
829 .parent = &ahb_clk,
830 .enable = _clk_enable,
831 .enable_reg = MXC_CCM_CGR2,
832 .enable_shift = MXC_CCM_CGR2_GACC_OFFSET,
833 .get_rate = _clk_mbx_get_rate,
834};
835
836static struct clk vpu_clk = {
837 .name = "vpu_clk",
838 .parent = &ahb_clk,
839 .enable = _clk_enable,
840 .enable_reg = MXC_CCM_CGR2,
841 .enable_shift = MXC_CCM_CGR2_GACC_OFFSET,
842 .get_rate = _clk_mbx_get_rate,
843};
844
845static struct clk rtic_clk = {
846 .name = "rtic_clk",
847 .parent = &ahb_clk,
848 .enable = _clk_enable,
849 .enable_reg = MXC_CCM_CGR2,
850 .enable_shift = MXC_CCM_CGR2_RTIC_OFFSET,
851 .disable = _clk_disable,
852};
853
854static struct clk rng_clk = {
855 .name = "rng_clk",
856 .parent = &ipg_clk,
857 .enable = _clk_enable,
858 .enable_reg = MXC_CCM_CGR0,
859 .enable_shift = MXC_CCM_CGR0_RNG_OFFSET,
860 .disable = _clk_disable,
861};
862
863static struct clk sdma_clk[] = {
864 {
865 .name = "sdma_ahb_clk",
866 .parent = &ahb_clk,
867 .enable = _clk_enable,
868 .enable_reg = MXC_CCM_CGR0,
869 .enable_shift = MXC_CCM_CGR0_SDMA_OFFSET,
870 .disable = _clk_disable,},
871 {
872 .name = "sdma_ipg_clk",
873 .parent = &ipg_clk,}
874};
875
876static struct clk mpeg4_clk = {
877 .name = "mpeg4_clk",
878 .parent = &ahb_clk,
879 .enable = _clk_enable,
880 .enable_reg = MXC_CCM_CGR1,
881 .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET,
882 .disable = _clk_disable,
883};
884
885static struct clk vl2cc_clk = {
886 .name = "vl2cc_clk",
887 .parent = &ahb_clk,
888 .enable = _clk_enable,
889 .enable_reg = MXC_CCM_CGR1,
890 .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET,
891 .disable = _clk_disable,
892};
893
894static struct clk mstick_clk[] = {
895 {
896 .name = "mstick_clk",
897 .id = 0,
898 .parent = &usb_pll_clk,
899 .get_rate = _clk_mstick1_get_rate,
900 .enable = _clk_enable,
901 .enable_reg = MXC_CCM_CGR1,
902 .enable_shift = MXC_CCM_CGR1_MEMSTICK1_OFFSET,
903 .disable = _clk_disable,},
904 {
905 .name = "mstick_clk",
906 .id = 1,
907 .parent = &usb_pll_clk,
908 .get_rate = _clk_mstick2_get_rate,
909 .enable = _clk_enable,
910 .enable_reg = MXC_CCM_CGR1,
911 .enable_shift = MXC_CCM_CGR1_MEMSTICK2_OFFSET,
912 .disable = _clk_disable,},
913};
914
915static struct clk iim_clk = {
916 .name = "iim_clk",
917 .parent = &ipg_clk,
918 .enable = _clk_enable,
919 .enable_reg = MXC_CCM_CGR0,
920 .enable_shift = MXC_CCM_CGR0_IIM_OFFSET,
921 .disable = _clk_disable,
922};
923
924static unsigned long _clk_cko1_round_rate(struct clk *clk, unsigned long rate)
925{
926 u32 div, parent = clk_get_rate(clk->parent);
927
928 div = parent / rate;
929 if (parent % rate)
930 div++;
931
932 if (div > 8)
933 div = 16;
934 else if (div > 4)
935 div = 8;
936 else if (div > 2)
937 div = 4;
938
939 return parent / div;
940}
941
942static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate)
943{
944 u32 reg, div, parent = clk_get_rate(clk->parent);
945
946 div = parent / rate;
947
948 if (div == 16)
949 div = 4;
950 else if (div == 8)
951 div = 3;
952 else if (div == 4)
953 div = 2;
954 else if (div == 2)
955 div = 1;
956 else if (div == 1)
957 div = 0;
958 else
959 return -EINVAL;
960
961 reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOUTDIV_MASK;
962 reg |= div << MXC_CCM_COSR_CLKOUTDIV_OFFSET;
963 __raw_writel(reg, MXC_CCM_COSR);
964
965 return 0;
966}
967
968static unsigned long _clk_cko1_get_rate(struct clk *clk)
969{
970 u32 div;
971
972 div = __raw_readl(MXC_CCM_COSR) & MXC_CCM_COSR_CLKOUTDIV_MASK >>
973 MXC_CCM_COSR_CLKOUTDIV_OFFSET;
974
975 return clk_get_rate(clk->parent) / (1 << div);
976}
977
978static int _clk_cko1_set_parent(struct clk *clk, struct clk *parent)
979{
980 u32 reg;
981
982 reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOSEL_MASK;
983
984 if (parent == &mcu_main_clk)
985 reg |= 0 << MXC_CCM_COSR_CLKOSEL_OFFSET;
986 else if (parent == &ipg_clk)
987 reg |= 1 << MXC_CCM_COSR_CLKOSEL_OFFSET;
988 else if (parent == &usb_pll_clk)
989 reg |= 2 << MXC_CCM_COSR_CLKOSEL_OFFSET;
990 else if (parent == mcu_main_clk.parent)
991 reg |= 3 << MXC_CCM_COSR_CLKOSEL_OFFSET;
992 else if (parent == &ahb_clk)
993 reg |= 5 << MXC_CCM_COSR_CLKOSEL_OFFSET;
994 else if (parent == &serial_pll_clk)
995 reg |= 7 << MXC_CCM_COSR_CLKOSEL_OFFSET;
996 else if (parent == &ckih_clk)
997 reg |= 8 << MXC_CCM_COSR_CLKOSEL_OFFSET;
998 else if (parent == &emi_clk)
999 reg |= 9 << MXC_CCM_COSR_CLKOSEL_OFFSET;
1000 else if (parent == &ipu_clk)
1001 reg |= 0xA << MXC_CCM_COSR_CLKOSEL_OFFSET;
1002 else if (parent == &nfc_clk)
1003 reg |= 0xB << MXC_CCM_COSR_CLKOSEL_OFFSET;
1004 else if (parent == &uart_clk[0])
1005 reg |= 0xC << MXC_CCM_COSR_CLKOSEL_OFFSET;
1006 else
1007 return -EINVAL;
1008
1009 __raw_writel(reg, MXC_CCM_COSR);
1010
1011 return 0;
1012}
1013
1014static int _clk_cko1_enable(struct clk *clk)
1015{
1016 u32 reg;
1017
1018 reg = __raw_readl(MXC_CCM_COSR) | MXC_CCM_COSR_CLKOEN;
1019 __raw_writel(reg, MXC_CCM_COSR);
1020
1021 return 0;
1022}
1023
1024static void _clk_cko1_disable(struct clk *clk)
1025{
1026 u32 reg;
1027
1028 reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOEN;
1029 __raw_writel(reg, MXC_CCM_COSR);
1030}
1031
1032static struct clk cko1_clk = {
1033 .name = "cko1_clk",
1034 .get_rate = _clk_cko1_get_rate,
1035 .set_rate = _clk_cko1_set_rate,
1036 .round_rate = _clk_cko1_round_rate,
1037 .set_parent = _clk_cko1_set_parent,
1038 .enable = _clk_cko1_enable,
1039 .disable = _clk_cko1_disable,
1040};
1041
1042static struct clk *mxc_clks[] = {
1043 &ckih_clk,
1044 &ckil_clk,
1045 &mcu_pll_clk,
1046 &usb_pll_clk,
1047 &serial_pll_clk,
1048 &mcu_main_clk,
1049 &ahb_clk,
1050 &per_clk,
1051 &perclk_clk,
1052 &cko1_clk,
1053 &emi_clk,
1054 &cspi_clk[0],
1055 &cspi_clk[1],
1056 &cspi_clk[2],
1057 &ipg_clk,
1058 &gpt_clk,
1059 &pwm_clk,
1060 &wdog_clk,
1061 &rtc_clk,
1062 &epit_clk[0],
1063 &epit_clk[1],
1064 &nfc_clk,
1065 &ipu_clk,
1066 &kpp_clk,
1067 &usb_clk[0],
1068 &usb_clk[1],
1069 &csi_clk,
1070 &uart_clk[0],
1071 &uart_clk[1],
1072 &uart_clk[2],
1073 &uart_clk[3],
1074 &uart_clk[4],
1075 &i2c_clk[0],
1076 &i2c_clk[1],
1077 &i2c_clk[2],
1078 &owire_clk,
1079 &sdhc_clk[0],
1080 &sdhc_clk[1],
1081 &ssi_clk[0],
1082 &ssi_clk[1],
1083 &firi_clk,
1084 &ata_clk,
1085 &rtic_clk,
1086 &rng_clk,
1087 &sdma_clk[0],
1088 &sdma_clk[1],
1089 &mstick_clk[0],
1090 &mstick_clk[1],
1091 &scc_clk,
1092 &iim_clk,
1093};
1094
1095int __init mxc_clocks_init(unsigned long fref)
1096{
1097 u32 reg;
1098 struct clk **clkp;
1099
1100 ckih_rate = fref;
1101
1102 for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++)
1103 clk_register(*clkp);
1104
1105 if (cpu_is_mx31()) {
1106 clk_register(&mpeg4_clk);
1107 clk_register(&mbx_clk);
1108 } else {
1109 clk_register(&vpu_clk);
1110 clk_register(&vl2cc_clk);
1111 }
1112
1113 /* Turn off all possible clocks */
1114 __raw_writel(MXC_CCM_CGR0_GPT_MASK, MXC_CCM_CGR0);
1115 __raw_writel(0, MXC_CCM_CGR1);
1116
1117 __raw_writel(MXC_CCM_CGR2_EMI_MASK |
1118 MXC_CCM_CGR2_IPMUX1_MASK |
1119 MXC_CCM_CGR2_IPMUX2_MASK |
1120 MXC_CCM_CGR2_MXCCLKENSEL_MASK | /* for MX32 */
1121 MXC_CCM_CGR2_CHIKCAMPEN_MASK | /* for MX32 */
1122 MXC_CCM_CGR2_OVRVPUBUSY_MASK | /* for MX32 */
1123 1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for
1124 MX32, but still required to be set */
1125 MXC_CCM_CGR2);
1126
1127 clk_disable(&cko1_clk);
1128 clk_disable(&usb_pll_clk);
1129
1130 pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));
1131
1132 clk_enable(&gpt_clk);
1133 clk_enable(&emi_clk);
1134 clk_enable(&iim_clk);
1135
1136 clk_enable(&serial_pll_clk);
1137
1138 if (mx31_revision() >= CHIP_REV_2_0) {
1139 reg = __raw_readl(MXC_CCM_PMCR1);
1140 /* No PLL restart on DVFS switch; enable auto EMI handshake */
1141 reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
1142 __raw_writel(reg, MXC_CCM_PMCR1);
1143 }
1144
1145 return 0;
1146}
1147
diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-mx3/crm_regs.h
new file mode 100644
index 000000000000..4a0e0ede23bb
--- /dev/null
+++ b/arch/arm/mach-mx3/crm_regs.h
@@ -0,0 +1,401 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ARCH_ARM_MACH_MX3_CRM_REGS_H__
21#define __ARCH_ARM_MACH_MX3_CRM_REGS_H__
22
23#define CKIH_CLK_FREQ 26000000
24#define CKIH_CLK_FREQ_27MHZ 27000000
25#define CKIL_CLK_FREQ 32768
26
27#define MXC_CCM_BASE IO_ADDRESS(CCM_BASE_ADDR)
28
29/* Register addresses */
30#define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00)
31#define MXC_CCM_PDR0 (MXC_CCM_BASE + 0x04)
32#define MXC_CCM_PDR1 (MXC_CCM_BASE + 0x08)
33#define MXC_CCM_RCSR (MXC_CCM_BASE + 0x0C)
34#define MXC_CCM_MPCTL (MXC_CCM_BASE + 0x10)
35#define MXC_CCM_UPCTL (MXC_CCM_BASE + 0x14)
36#define MXC_CCM_SRPCTL (MXC_CCM_BASE + 0x18)
37#define MXC_CCM_COSR (MXC_CCM_BASE + 0x1C)
38#define MXC_CCM_CGR0 (MXC_CCM_BASE + 0x20)
39#define MXC_CCM_CGR1 (MXC_CCM_BASE + 0x24)
40#define MXC_CCM_CGR2 (MXC_CCM_BASE + 0x28)
41#define MXC_CCM_WIMR (MXC_CCM_BASE + 0x2C)
42#define MXC_CCM_LDC (MXC_CCM_BASE + 0x30)
43#define MXC_CCM_DCVR0 (MXC_CCM_BASE + 0x34)
44#define MXC_CCM_DCVR1 (MXC_CCM_BASE + 0x38)
45#define MXC_CCM_DCVR2 (MXC_CCM_BASE + 0x3C)
46#define MXC_CCM_DCVR3 (MXC_CCM_BASE + 0x40)
47#define MXC_CCM_LTR0 (MXC_CCM_BASE + 0x44)
48#define MXC_CCM_LTR1 (MXC_CCM_BASE + 0x48)
49#define MXC_CCM_LTR2 (MXC_CCM_BASE + 0x4C)
50#define MXC_CCM_LTR3 (MXC_CCM_BASE + 0x50)
51#define MXC_CCM_LTBR0 (MXC_CCM_BASE + 0x54)
52#define MXC_CCM_LTBR1 (MXC_CCM_BASE + 0x58)
53#define MXC_CCM_PMCR0 (MXC_CCM_BASE + 0x5C)
54#define MXC_CCM_PMCR1 (MXC_CCM_BASE + 0x60)
55#define MXC_CCM_PDR2 (MXC_CCM_BASE + 0x64)
56
57/* Register bit definitions */
58#define MXC_CCM_CCMR_WBEN (1 << 27)
59#define MXC_CCM_CCMR_CSCS (1 << 25)
60#define MXC_CCM_CCMR_PERCS (1 << 24)
61#define MXC_CCM_CCMR_SSI1S_OFFSET 18
62#define MXC_CCM_CCMR_SSI1S_MASK (0x3 << 18)
63#define MXC_CCM_CCMR_SSI2S_OFFSET 21
64#define MXC_CCM_CCMR_SSI2S_MASK (0x3 << 21)
65#define MXC_CCM_CCMR_LPM_OFFSET 14
66#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
67#define MXC_CCM_CCMR_FIRS_OFFSET 11
68#define MXC_CCM_CCMR_FIRS_MASK (0x3 << 11)
69#define MXC_CCM_CCMR_UPE (1 << 9)
70#define MXC_CCM_CCMR_SPE (1 << 8)
71#define MXC_CCM_CCMR_MDS (1 << 7)
72#define MXC_CCM_CCMR_SBYCS (1 << 4)
73#define MXC_CCM_CCMR_MPE (1 << 3)
74#define MXC_CCM_CCMR_PRCS_OFFSET 1
75#define MXC_CCM_CCMR_PRCS_MASK (0x3 << 1)
76
77#define MXC_CCM_PDR0_CSI_PODF_OFFSET 26
78#define MXC_CCM_PDR0_CSI_PODF_MASK (0x3F << 26)
79#define MXC_CCM_PDR0_CSI_PRDF_OFFSET 23
80#define MXC_CCM_PDR0_CSI_PRDF_MASK (0x7 << 23)
81#define MXC_CCM_PDR0_PER_PODF_OFFSET 16
82#define MXC_CCM_PDR0_PER_PODF_MASK (0x1F << 16)
83#define MXC_CCM_PDR0_HSP_PODF_OFFSET 11
84#define MXC_CCM_PDR0_HSP_PODF_MASK (0x7 << 11)
85#define MXC_CCM_PDR0_NFC_PODF_OFFSET 8
86#define MXC_CCM_PDR0_NFC_PODF_MASK (0x7 << 8)
87#define MXC_CCM_PDR0_IPG_PODF_OFFSET 6
88#define MXC_CCM_PDR0_IPG_PODF_MASK (0x3 << 6)
89#define MXC_CCM_PDR0_MAX_PODF_OFFSET 3
90#define MXC_CCM_PDR0_MAX_PODF_MASK (0x7 << 3)
91#define MXC_CCM_PDR0_MCU_PODF_OFFSET 0
92#define MXC_CCM_PDR0_MCU_PODF_MASK 0x7
93
94#define MXC_CCM_PDR0_HSP_DIV_1 (0x0 << 11)
95#define MXC_CCM_PDR0_HSP_DIV_2 (0x1 << 11)
96#define MXC_CCM_PDR0_HSP_DIV_3 (0x2 << 11)
97#define MXC_CCM_PDR0_HSP_DIV_4 (0x3 << 11)
98#define MXC_CCM_PDR0_HSP_DIV_5 (0x4 << 11)
99#define MXC_CCM_PDR0_HSP_DIV_6 (0x5 << 11)
100#define MXC_CCM_PDR0_HSP_DIV_7 (0x6 << 11)
101#define MXC_CCM_PDR0_HSP_DIV_8 (0x7 << 11)
102
103#define MXC_CCM_PDR0_IPG_DIV_1 (0x0 << 6)
104#define MXC_CCM_PDR0_IPG_DIV_2 (0x1 << 6)
105#define MXC_CCM_PDR0_IPG_DIV_3 (0x2 << 6)
106#define MXC_CCM_PDR0_IPG_DIV_4 (0x3 << 6)
107
108#define MXC_CCM_PDR0_MAX_DIV_1 (0x0 << 3)
109#define MXC_CCM_PDR0_MAX_DIV_2 (0x1 << 3)
110#define MXC_CCM_PDR0_MAX_DIV_3 (0x2 << 3)
111#define MXC_CCM_PDR0_MAX_DIV_4 (0x3 << 3)
112#define MXC_CCM_PDR0_MAX_DIV_5 (0x4 << 3)
113#define MXC_CCM_PDR0_MAX_DIV_6 (0x5 << 3)
114#define MXC_CCM_PDR0_MAX_DIV_7 (0x6 << 3)
115#define MXC_CCM_PDR0_MAX_DIV_8 (0x7 << 3)
116
117#define MXC_CCM_PDR0_NFC_DIV_1 (0x0 << 8)
118#define MXC_CCM_PDR0_NFC_DIV_2 (0x1 << 8)
119#define MXC_CCM_PDR0_NFC_DIV_3 (0x2 << 8)
120#define MXC_CCM_PDR0_NFC_DIV_4 (0x3 << 8)
121#define MXC_CCM_PDR0_NFC_DIV_5 (0x4 << 8)
122#define MXC_CCM_PDR0_NFC_DIV_6 (0x5 << 8)
123#define MXC_CCM_PDR0_NFC_DIV_7 (0x6 << 8)
124#define MXC_CCM_PDR0_NFC_DIV_8 (0x7 << 8)
125
126#define MXC_CCM_PDR0_MCU_DIV_1 0x0
127#define MXC_CCM_PDR0_MCU_DIV_2 0x1
128#define MXC_CCM_PDR0_MCU_DIV_3 0x2
129#define MXC_CCM_PDR0_MCU_DIV_4 0x3
130#define MXC_CCM_PDR0_MCU_DIV_5 0x4
131#define MXC_CCM_PDR0_MCU_DIV_6 0x5
132#define MXC_CCM_PDR0_MCU_DIV_7 0x6
133#define MXC_CCM_PDR0_MCU_DIV_8 0x7
134
135#define MXC_CCM_PDR1_USB_PRDF_OFFSET 30
136#define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30)
137#define MXC_CCM_PDR1_USB_PODF_OFFSET 27
138#define MXC_CCM_PDR1_USB_PODF_MASK (0x7 << 27)
139#define MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET 24
140#define MXC_CCM_PDR1_FIRI_PRE_PODF_MASK (0x7 << 24)
141#define MXC_CCM_PDR1_FIRI_PODF_OFFSET 18
142#define MXC_CCM_PDR1_FIRI_PODF_MASK (0x3F << 18)
143#define MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET 15
144#define MXC_CCM_PDR1_SSI2_PRE_PODF_MASK (0x7 << 15)
145#define MXC_CCM_PDR1_SSI2_PODF_OFFSET 9
146#define MXC_CCM_PDR1_SSI2_PODF_MASK (0x3F << 9)
147#define MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET 6
148#define MXC_CCM_PDR1_SSI1_PRE_PODF_MASK (0x7 << 6)
149#define MXC_CCM_PDR1_SSI1_PODF_OFFSET 0
150#define MXC_CCM_PDR1_SSI1_PODF_MASK 0x3F
151
152/* Bit definitions for RCSR */
153#define MXC_CCM_RCSR_NF16B 0x80000000
154
155/* Bit definitions for both MCU, USB and SR PLL control registers */
156#define MXC_CCM_PCTL_BRM 0x80000000
157#define MXC_CCM_PCTL_PD_OFFSET 26
158#define MXC_CCM_PCTL_PD_MASK (0xF << 26)
159#define MXC_CCM_PCTL_MFD_OFFSET 16
160#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16)
161#define MXC_CCM_PCTL_MFI_OFFSET 10
162#define MXC_CCM_PCTL_MFI_MASK (0xF << 10)
163#define MXC_CCM_PCTL_MFN_OFFSET 0
164#define MXC_CCM_PCTL_MFN_MASK 0x3FF
165
166#define MXC_CCM_CGR0_SD_MMC1_OFFSET 0
167#define MXC_CCM_CGR0_SD_MMC1_MASK (0x3 << 0)
168#define MXC_CCM_CGR0_SD_MMC2_OFFSET 2
169#define MXC_CCM_CGR0_SD_MMC2_MASK (0x3 << 2)
170#define MXC_CCM_CGR0_GPT_OFFSET 4
171#define MXC_CCM_CGR0_GPT_MASK (0x3 << 4)
172#define MXC_CCM_CGR0_EPIT1_OFFSET 6
173#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 6)
174#define MXC_CCM_CGR0_EPIT2_OFFSET 8
175#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 8)
176#define MXC_CCM_CGR0_IIM_OFFSET 10
177#define MXC_CCM_CGR0_IIM_MASK (0x3 << 10)
178#define MXC_CCM_CGR0_ATA_OFFSET 12
179#define MXC_CCM_CGR0_ATA_MASK (0x3 << 12)
180#define MXC_CCM_CGR0_SDMA_OFFSET 14
181#define MXC_CCM_CGR0_SDMA_MASK (0x3 << 14)
182#define MXC_CCM_CGR0_CSPI3_OFFSET 16
183#define MXC_CCM_CGR0_CSPI3_MASK (0x3 << 16)
184#define MXC_CCM_CGR0_RNG_OFFSET 18
185#define MXC_CCM_CGR0_RNG_MASK (0x3 << 18)
186#define MXC_CCM_CGR0_UART1_OFFSET 20
187#define MXC_CCM_CGR0_UART1_MASK (0x3 << 20)
188#define MXC_CCM_CGR0_UART2_OFFSET 22
189#define MXC_CCM_CGR0_UART2_MASK (0x3 << 22)
190#define MXC_CCM_CGR0_SSI1_OFFSET 24
191#define MXC_CCM_CGR0_SSI1_MASK (0x3 << 24)
192#define MXC_CCM_CGR0_I2C1_OFFSET 26
193#define MXC_CCM_CGR0_I2C1_MASK (0x3 << 26)
194#define MXC_CCM_CGR0_I2C2_OFFSET 28
195#define MXC_CCM_CGR0_I2C2_MASK (0x3 << 28)
196#define MXC_CCM_CGR0_I2C3_OFFSET 30
197#define MXC_CCM_CGR0_I2C3_MASK (0x3 << 30)
198
199#define MXC_CCM_CGR1_HANTRO_OFFSET 0
200#define MXC_CCM_CGR1_HANTRO_MASK (0x3 << 0)
201#define MXC_CCM_CGR1_MEMSTICK1_OFFSET 2
202#define MXC_CCM_CGR1_MEMSTICK1_MASK (0x3 << 2)
203#define MXC_CCM_CGR1_MEMSTICK2_OFFSET 4
204#define MXC_CCM_CGR1_MEMSTICK2_MASK (0x3 << 4)
205#define MXC_CCM_CGR1_CSI_OFFSET 6
206#define MXC_CCM_CGR1_CSI_MASK (0x3 << 6)
207#define MXC_CCM_CGR1_RTC_OFFSET 8
208#define MXC_CCM_CGR1_RTC_MASK (0x3 << 8)
209#define MXC_CCM_CGR1_WDOG_OFFSET 10
210#define MXC_CCM_CGR1_WDOG_MASK (0x3 << 10)
211#define MXC_CCM_CGR1_PWM_OFFSET 12
212#define MXC_CCM_CGR1_PWM_MASK (0x3 << 12)
213#define MXC_CCM_CGR1_SIM_OFFSET 14
214#define MXC_CCM_CGR1_SIM_MASK (0x3 << 14)
215#define MXC_CCM_CGR1_ECT_OFFSET 16
216#define MXC_CCM_CGR1_ECT_MASK (0x3 << 16)
217#define MXC_CCM_CGR1_USBOTG_OFFSET 18
218#define MXC_CCM_CGR1_USBOTG_MASK (0x3 << 18)
219#define MXC_CCM_CGR1_KPP_OFFSET 20
220#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20)
221#define MXC_CCM_CGR1_IPU_OFFSET 22
222#define MXC_CCM_CGR1_IPU_MASK (0x3 << 22)
223#define MXC_CCM_CGR1_UART3_OFFSET 24
224#define MXC_CCM_CGR1_UART3_MASK (0x3 << 24)
225#define MXC_CCM_CGR1_UART4_OFFSET 26
226#define MXC_CCM_CGR1_UART4_MASK (0x3 << 26)
227#define MXC_CCM_CGR1_UART5_OFFSET 28
228#define MXC_CCM_CGR1_UART5_MASK (0x3 << 28)
229#define MXC_CCM_CGR1_OWIRE_OFFSET 30
230#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 30)
231
232#define MXC_CCM_CGR2_SSI2_OFFSET 0
233#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 0)
234#define MXC_CCM_CGR2_CSPI1_OFFSET 2
235#define MXC_CCM_CGR2_CSPI1_MASK (0x3 << 2)
236#define MXC_CCM_CGR2_CSPI2_OFFSET 4
237#define MXC_CCM_CGR2_CSPI2_MASK (0x3 << 4)
238#define MXC_CCM_CGR2_GACC_OFFSET 6
239#define MXC_CCM_CGR2_GACC_MASK (0x3 << 6)
240#define MXC_CCM_CGR2_EMI_OFFSET 8
241#define MXC_CCM_CGR2_EMI_MASK (0x3 << 8)
242#define MXC_CCM_CGR2_RTIC_OFFSET 10
243#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 10)
244#define MXC_CCM_CGR2_FIRI_OFFSET 12
245#define MXC_CCM_CGR2_FIRI_MASK (0x3 << 12)
246#define MXC_CCM_CGR2_IPMUX1_OFFSET 14
247#define MXC_CCM_CGR2_IPMUX1_MASK (0x3 << 14)
248#define MXC_CCM_CGR2_IPMUX2_OFFSET 16
249#define MXC_CCM_CGR2_IPMUX2_MASK (0x3 << 16)
250
251/* These new CGR2 bits are added in MX32 */
252#define MXC_CCM_CGR2_APMSYSCLKSEL_OFFSET 18
253#define MXC_CCM_CGR2_APMSYSCLKSEL_MASK (0x3 << 18)
254#define MXC_CCM_CGR2_APMSSICLKSEL_OFFSET 20
255#define MXC_CCM_CGR2_APMSSICLKSEL_MASK (0x3 << 20)
256#define MXC_CCM_CGR2_APMPERCLKSEL_OFFSET 22
257#define MXC_CCM_CGR2_APMPERCLKSEL_MASK (0x3 << 22)
258#define MXC_CCM_CGR2_MXCCLKENSEL_OFFSET 24
259#define MXC_CCM_CGR2_MXCCLKENSEL_MASK (0x1 << 24)
260#define MXC_CCM_CGR2_CHIKCAMPEN_OFFSET 25
261#define MXC_CCM_CGR2_CHIKCAMPEN_MASK (0x1 << 25)
262#define MXC_CCM_CGR2_OVRVPUBUSY_OFFSET 26
263#define MXC_CCM_CGR2_OVRVPUBUSY_MASK (0x1 << 26)
264#define MXC_CCM_CGR2_APMENA_OFFSET 30
265#define MXC_CCM_CGR2_AOMENA_MASK (0x1 << 30)
266
267/*
268 * LTR0 register offsets
269 */
270#define MXC_CCM_LTR0_DIV3CK_OFFSET 1
271#define MXC_CCM_LTR0_DIV3CK_MASK (0x3 << 1)
272#define MXC_CCM_LTR0_DNTHR_OFFSET 16
273#define MXC_CCM_LTR0_DNTHR_MASK (0x3F << 16)
274#define MXC_CCM_LTR0_UPTHR_OFFSET 22
275#define MXC_CCM_LTR0_UPTHR_MASK (0x3F << 22)
276
277/*
278 * LTR1 register offsets
279 */
280#define MXC_CCM_LTR1_PNCTHR_OFFSET 0
281#define MXC_CCM_LTR1_PNCTHR_MASK 0x3F
282#define MXC_CCM_LTR1_UPCNT_OFFSET 6
283#define MXC_CCM_LTR1_UPCNT_MASK (0xFF << 6)
284#define MXC_CCM_LTR1_DNCNT_OFFSET 14
285#define MXC_CCM_LTR1_DNCNT_MASK (0xFF << 14)
286#define MXC_CCM_LTR1_LTBRSR_MASK 0x400000
287#define MXC_CCM_LTR1_LTBRSR_OFFSET 22
288#define MXC_CCM_LTR1_LTBRSR 0x400000
289#define MXC_CCM_LTR1_LTBRSH 0x800000
290
291/*
292 * LTR2 bit definitions. x ranges from 0 for WSW9 to 6 for WSW15
293 */
294#define MXC_CCM_LTR2_WSW_OFFSET(x) (11 + (x) * 3)
295#define MXC_CCM_LTR2_WSW_MASK(x) (0x7 << \
296 MXC_CCM_LTR2_WSW_OFFSET((x)))
297#define MXC_CCM_LTR2_EMAC_OFFSET 0
298#define MXC_CCM_LTR2_EMAC_MASK 0x1FF
299
300/*
301 * LTR3 bit definitions. x ranges from 0 for WSW0 to 8 for WSW8
302 */
303#define MXC_CCM_LTR3_WSW_OFFSET(x) (5 + (x) * 3)
304#define MXC_CCM_LTR3_WSW_MASK(x) (0x7 << \
305 MXC_CCM_LTR3_WSW_OFFSET((x)))
306
307#define MXC_CCM_PMCR0_DFSUP1 0x80000000
308#define MXC_CCM_PMCR0_DFSUP1_SPLL (0 << 31)
309#define MXC_CCM_PMCR0_DFSUP1_MPLL (1 << 31)
310#define MXC_CCM_PMCR0_DFSUP0 0x40000000
311#define MXC_CCM_PMCR0_DFSUP0_PLL (0 << 30)
312#define MXC_CCM_PMCR0_DFSUP0_PDR (1 << 30)
313#define MXC_CCM_PMCR0_DFSUP_MASK (0x3 << 30)
314
315#define DVSUP_TURBO 0
316#define DVSUP_HIGH 1
317#define DVSUP_MEDIUM 2
318#define DVSUP_LOW 3
319#define MXC_CCM_PMCR0_DVSUP_TURBO (DVSUP_TURBO << 28)
320#define MXC_CCM_PMCR0_DVSUP_HIGH (DVSUP_HIGH << 28)
321#define MXC_CCM_PMCR0_DVSUP_MEDIUM (DVSUP_MEDIUM << 28)
322#define MXC_CCM_PMCR0_DVSUP_LOW (DVSUP_LOW << 28)
323#define MXC_CCM_PMCR0_DVSUP_OFFSET 28
324#define MXC_CCM_PMCR0_DVSUP_MASK (0x3 << 28)
325#define MXC_CCM_PMCR0_UDSC 0x08000000
326#define MXC_CCM_PMCR0_UDSC_MASK (1 << 27)
327#define MXC_CCM_PMCR0_UDSC_UP (1 << 27)
328#define MXC_CCM_PMCR0_UDSC_DOWN (0 << 27)
329
330#define MXC_CCM_PMCR0_VSCNT_1 (0x0 << 24)
331#define MXC_CCM_PMCR0_VSCNT_2 (0x1 << 24)
332#define MXC_CCM_PMCR0_VSCNT_3 (0x2 << 24)
333#define MXC_CCM_PMCR0_VSCNT_4 (0x3 << 24)
334#define MXC_CCM_PMCR0_VSCNT_5 (0x4 << 24)
335#define MXC_CCM_PMCR0_VSCNT_6 (0x5 << 24)
336#define MXC_CCM_PMCR0_VSCNT_7 (0x6 << 24)
337#define MXC_CCM_PMCR0_VSCNT_8 (0x7 << 24)
338#define MXC_CCM_PMCR0_VSCNT_OFFSET 24
339#define MXC_CCM_PMCR0_VSCNT_MASK (0x7 << 24)
340#define MXC_CCM_PMCR0_DVFEV 0x00800000
341#define MXC_CCM_PMCR0_DVFIS 0x00400000
342#define MXC_CCM_PMCR0_LBMI 0x00200000
343#define MXC_CCM_PMCR0_LBFL 0x00100000
344#define MXC_CCM_PMCR0_LBCF_4 (0x0 << 18)
345#define MXC_CCM_PMCR0_LBCF_8 (0x1 << 18)
346#define MXC_CCM_PMCR0_LBCF_12 (0x2 << 18)
347#define MXC_CCM_PMCR0_LBCF_16 (0x3 << 18)
348#define MXC_CCM_PMCR0_LBCF_OFFSET 18
349#define MXC_CCM_PMCR0_LBCF_MASK (0x3 << 18)
350#define MXC_CCM_PMCR0_PTVIS 0x00020000
351#define MXC_CCM_PMCR0_UPDTEN 0x00010000
352#define MXC_CCM_PMCR0_UPDTEN_MASK (0x1 << 16)
353#define MXC_CCM_PMCR0_FSVAIM 0x00008000
354#define MXC_CCM_PMCR0_FSVAI_OFFSET 13
355#define MXC_CCM_PMCR0_FSVAI_MASK (0x3 << 13)
356#define MXC_CCM_PMCR0_DPVCR 0x00001000
357#define MXC_CCM_PMCR0_DPVV 0x00000800
358#define MXC_CCM_PMCR0_WFIM 0x00000400
359#define MXC_CCM_PMCR0_DRCE3 0x00000200
360#define MXC_CCM_PMCR0_DRCE2 0x00000100
361#define MXC_CCM_PMCR0_DRCE1 0x00000080
362#define MXC_CCM_PMCR0_DRCE0 0x00000040
363#define MXC_CCM_PMCR0_DCR 0x00000020
364#define MXC_CCM_PMCR0_DVFEN 0x00000010
365#define MXC_CCM_PMCR0_PTVAIM 0x00000008
366#define MXC_CCM_PMCR0_PTVAI_OFFSET 1
367#define MXC_CCM_PMCR0_PTVAI_MASK (0x3 << 1)
368#define MXC_CCM_PMCR0_DPTEN 0x00000001
369
370#define MXC_CCM_PMCR1_DVGP_OFFSET 0
371#define MXC_CCM_PMCR1_DVGP_MASK (0xF)
372
373#define MXC_CCM_PMCR1_PLLRDIS (0x1 << 7)
374#define MXC_CCM_PMCR1_EMIRQ_EN (0x1 << 8)
375
376#define MXC_CCM_DCVR_ULV_MASK (0x3FF << 22)
377#define MXC_CCM_DCVR_ULV_OFFSET 22
378#define MXC_CCM_DCVR_LLV_MASK (0x3FF << 12)
379#define MXC_CCM_DCVR_LLV_OFFSET 12
380#define MXC_CCM_DCVR_ELV_MASK (0x3FF << 2)
381#define MXC_CCM_DCVR_ELV_OFFSET 2
382
383#define MXC_CCM_PDR2_MST2_PDF_MASK (0x3F << 7)
384#define MXC_CCM_PDR2_MST2_PDF_OFFSET 7
385#define MXC_CCM_PDR2_MST1_PDF_MASK 0x3F
386#define MXC_CCM_PDR2_MST1_PDF_OFFSET 0
387
388#define MXC_CCM_COSR_CLKOSEL_MASK 0x0F
389#define MXC_CCM_COSR_CLKOSEL_OFFSET 0
390#define MXC_CCM_COSR_CLKOUTDIV_MASK (0x07 << 6)
391#define MXC_CCM_COSR_CLKOUTDIV_OFFSET 6
392#define MXC_CCM_COSR_CLKOEN (1 << 9)
393
394/*
395 * PMCR0 register offsets
396 */
397#define MXC_CCM_PMCR0_LBFL_OFFSET 20
398#define MXC_CCM_PMCR0_DFSUP0_OFFSET 30
399#define MXC_CCM_PMCR0_DFSUP1_OFFSET 31
400
401#endif /* __ARCH_ARM_MACH_MX3_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
new file mode 100644
index 000000000000..5c0320fce5b6
--- /dev/null
+++ b/arch/arm/mach-mx3/devices.c
@@ -0,0 +1,180 @@
1/*
2 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
17 * Boston, MA 02110-1301, USA.
18 */
19
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/serial.h>
23#include <linux/gpio.h>
24#include <asm/hardware.h>
25#include <asm/arch/imx-uart.h>
26
27static struct resource uart0[] = {
28 {
29 .start = UART1_BASE_ADDR,
30 .end = UART1_BASE_ADDR + 0x0B5,
31 .flags = IORESOURCE_MEM,
32 }, {
33 .start = MXC_INT_UART1,
34 .end = MXC_INT_UART1,
35 .flags = IORESOURCE_IRQ,
36 },
37};
38
39static struct platform_device mxc_uart_device0 = {
40 .name = "imx-uart",
41 .id = 0,
42 .resource = uart0,
43 .num_resources = ARRAY_SIZE(uart0),
44};
45
46static struct resource uart1[] = {
47 {
48 .start = UART2_BASE_ADDR,
49 .end = UART2_BASE_ADDR + 0x0B5,
50 .flags = IORESOURCE_MEM,
51 }, {
52 .start = MXC_INT_UART2,
53 .end = MXC_INT_UART2,
54 .flags = IORESOURCE_IRQ,
55 },
56};
57
58static struct platform_device mxc_uart_device1 = {
59 .name = "imx-uart",
60 .id = 1,
61 .resource = uart1,
62 .num_resources = ARRAY_SIZE(uart1),
63};
64
65static struct resource uart2[] = {
66 {
67 .start = UART3_BASE_ADDR,
68 .end = UART3_BASE_ADDR + 0x0B5,
69 .flags = IORESOURCE_MEM,
70 }, {
71 .start = MXC_INT_UART3,
72 .end = MXC_INT_UART3,
73 .flags = IORESOURCE_IRQ,
74 },
75};
76
77static struct platform_device mxc_uart_device2 = {
78 .name = "imx-uart",
79 .id = 2,
80 .resource = uart2,
81 .num_resources = ARRAY_SIZE(uart2),
82};
83
84static struct resource uart3[] = {
85 {
86 .start = UART4_BASE_ADDR,
87 .end = UART4_BASE_ADDR + 0x0B5,
88 .flags = IORESOURCE_MEM,
89 }, {
90 .start = MXC_INT_UART4,
91 .end = MXC_INT_UART4,
92 .flags = IORESOURCE_IRQ,
93 },
94};
95
96static struct platform_device mxc_uart_device3 = {
97 .name = "imx-uart",
98 .id = 3,
99 .resource = uart3,
100 .num_resources = ARRAY_SIZE(uart3),
101};
102
103static struct resource uart4[] = {
104 {
105 .start = UART5_BASE_ADDR,
106 .end = UART5_BASE_ADDR + 0x0B5,
107 .flags = IORESOURCE_MEM,
108 }, {
109 .start = MXC_INT_UART5,
110 .end = MXC_INT_UART5,
111 .flags = IORESOURCE_IRQ,
112 },
113};
114
115static struct platform_device mxc_uart_device4 = {
116 .name = "imx-uart",
117 .id = 4,
118 .resource = uart4,
119 .num_resources = ARRAY_SIZE(uart4),
120};
121
122/*
123 * Register only those UARTs that physically exist
124 */
125int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata)
126{
127 switch (uart_no) {
128 case 0:
129 mxc_uart_device0.dev.platform_data = pdata;
130 platform_device_register(&mxc_uart_device0);
131 break;
132 case 1:
133 mxc_uart_device1.dev.platform_data = pdata;
134 platform_device_register(&mxc_uart_device1);
135 break;
136 case 2:
137 mxc_uart_device2.dev.platform_data = pdata;
138 platform_device_register(&mxc_uart_device2);
139 break;
140 case 3:
141 mxc_uart_device3.dev.platform_data = pdata;
142 platform_device_register(&mxc_uart_device3);
143 break;
144 case 4:
145 mxc_uart_device4.dev.platform_data = pdata;
146 platform_device_register(&mxc_uart_device4);
147 break;
148 default:
149 return -ENODEV;
150 }
151
152 return 0;
153}
154
155/* GPIO port description */
156static struct mxc_gpio_port imx_gpio_ports[] = {
157 [0] = {
158 .chip.label = "gpio-0",
159 .base = IO_ADDRESS(GPIO1_BASE_ADDR),
160 .irq = MXC_INT_GPIO1,
161 .virtual_irq_start = MXC_GPIO_INT_BASE
162 },
163 [1] = {
164 .chip.label = "gpio-1",
165 .base = IO_ADDRESS(GPIO2_BASE_ADDR),
166 .irq = MXC_INT_GPIO2,
167 .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN
168 },
169 [2] = {
170 .chip.label = "gpio-2",
171 .base = IO_ADDRESS(GPIO3_BASE_ADDR),
172 .irq = MXC_INT_GPIO3,
173 .virtual_irq_start = MXC_GPIO_INT_BASE + GPIO_NUM_PIN * 2
174 }
175};
176
177int __init mxc_register_gpios(void)
178{
179 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
180}
diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux.c
new file mode 100644
index 000000000000..adc51feefc1d
--- /dev/null
+++ b/arch/arm/mach-mx3/iomux.c
@@ -0,0 +1,111 @@
1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/module.h>
21#include <linux/spinlock.h>
22#include <linux/io.h>
23#include <linux/gpio.h>
24#include <asm/hardware.h>
25#include <asm/arch/gpio.h>
26#include <asm/arch/iomux-mx3.h>
27
28/*
29 * IOMUX register (base) addresses
30 */
31#define IOMUX_BASE IO_ADDRESS(IOMUXC_BASE_ADDR)
32#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000)
33#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004)
34#define IOMUXGPR (IOMUX_BASE + 0x008)
35#define IOMUXSW_MUX_CTL (IOMUX_BASE + 0x00C)
36#define IOMUXSW_PAD_CTL (IOMUX_BASE + 0x154)
37
38static DEFINE_SPINLOCK(gpio_mux_lock);
39
40#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
41/*
42 * set the mode for a IOMUX pin.
43 */
44int mxc_iomux_mode(unsigned int pin_mode)
45{
46 u32 reg, field, l, mode, ret = 0;
47
48 reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
49 field = pin_mode & 0x3;
50 mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
51
52 pr_debug("%s: reg offset = 0x%x field = %d mode = 0x%02x\n",
53 __func__, (pin_mode & IOMUX_REG_MASK), field, mode);
54
55 spin_lock(&gpio_mux_lock);
56
57 l = __raw_readl(reg);
58 l &= ~(0xff << (field * 8));
59 l |= mode << (field * 8);
60 __raw_writel(l, reg);
61
62 spin_unlock(&gpio_mux_lock);
63
64 return ret;
65}
66EXPORT_SYMBOL(mxc_iomux_mode);
67
68/*
69 * This function configures the pad value for a IOMUX pin.
70 */
71void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
72{
73 u32 reg, field, l;
74
75 reg = IOMUXSW_PAD_CTL + (pin + 2) / 3;
76 field = (pin + 2) % 3;
77
78 pr_debug("%s: reg offset = 0x%x field = %d\n",
79 __func__, (pin + 2) / 3, field);
80
81 spin_lock(&gpio_mux_lock);
82
83 l = __raw_readl(reg);
84 l &= ~(0x1ff << (field * 9));
85 l |= config << (field * 9);
86 __raw_writel(l, reg);
87
88 spin_unlock(&gpio_mux_lock);
89}
90EXPORT_SYMBOL(mxc_iomux_set_pad);
91
92/*
93 * This function enables/disables the general purpose function for a particular
94 * signal.
95 */
96void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
97{
98 u32 l;
99
100 spin_lock(&gpio_mux_lock);
101 l = __raw_readl(IOMUXGPR);
102 if (en)
103 l |= gp;
104 else
105 l &= ~gp;
106
107 __raw_writel(l, IOMUXGPR);
108 spin_unlock(&gpio_mux_lock);
109}
110EXPORT_SYMBOL(mxc_iomux_set_gpr);
111
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c
index 7e89bdc23a9f..eba3e0cd4283 100644
--- a/arch/arm/mach-mx3/mx31ads.c
+++ b/arch/arm/mach-mx3/mx31ads.c
@@ -26,9 +26,11 @@
26#include <asm/hardware.h> 26#include <asm/hardware.h>
27#include <asm/mach-types.h> 27#include <asm/mach-types.h>
28#include <asm/mach/arch.h> 28#include <asm/mach/arch.h>
29#include <asm/mach/time.h>
29#include <asm/memory.h> 30#include <asm/memory.h>
30#include <asm/mach/map.h> 31#include <asm/mach/map.h>
31#include <asm/arch/common.h> 32#include <asm/arch/common.h>
33#include <asm/arch/board-mx31ads.h>
32 34
33/*! 35/*!
34 * @file mx31ads.c 36 * @file mx31ads.c
@@ -126,6 +128,16 @@ static void __init mxc_board_init(void)
126 mxc_init_extuart(); 128 mxc_init_extuart();
127} 129}
128 130
131static void __init mx31ads_timer_init(void)
132{
133 mxc_clocks_init(26000000);
134 mxc_timer_init("ipg_clk.0");
135}
136
137struct sys_timer mx31ads_timer = {
138 .init = mx31ads_timer_init,
139};
140
129/* 141/*
130 * The following uses standard kernel macros defined in arch.h in order to 142 * The following uses standard kernel macros defined in arch.h in order to
131 * initialize __mach_desc_MX31ADS data structure. 143 * initialize __mach_desc_MX31ADS data structure.
@@ -138,5 +150,5 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS")
138 .map_io = mx31ads_map_io, 150 .map_io = mx31ads_map_io,
139 .init_irq = mxc_init_irq, 151 .init_irq = mxc_init_irq,
140 .init_machine = mxc_board_init, 152 .init_machine = mxc_board_init,
141 .timer = &mxc_timer, 153 .timer = &mx31ads_timer,
142MACHINE_END 154MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c
new file mode 100644
index 000000000000..1372c1a1fc3f
--- /dev/null
+++ b/arch/arm/mach-mx3/mx31lite.c
@@ -0,0 +1,107 @@
1/*
2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <linux/types.h>
22#include <linux/init.h>
23#include <linux/kernel.h>
24#include <linux/memory.h>
25
26#include <asm/hardware.h>
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/time.h>
30#include <asm/mach/map.h>
31#include <asm/arch/common.h>
32#include <asm/page.h>
33#include <asm/setup.h>
34#include <asm/arch/board-mx31lite.h>
35
36/*
37 * This file contains the board-specific initialization routines.
38 */
39
40/*
41 * This structure defines the MX31 memory map.
42 */
43static struct map_desc mx31lite_io_desc[] __initdata = {
44 {
45 .virtual = AIPS1_BASE_ADDR_VIRT,
46 .pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
47 .length = AIPS1_SIZE,
48 .type = MT_NONSHARED_DEVICE
49 }, {
50 .virtual = SPBA0_BASE_ADDR_VIRT,
51 .pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
52 .length = SPBA0_SIZE,
53 .type = MT_NONSHARED_DEVICE
54 }, {
55 .virtual = AIPS2_BASE_ADDR_VIRT,
56 .pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
57 .length = AIPS2_SIZE,
58 .type = MT_NONSHARED_DEVICE
59 }, {
60 .virtual = CS4_BASE_ADDR_VIRT,
61 .pfn = __phys_to_pfn(CS4_BASE_ADDR),
62 .length = CS4_SIZE,
63 .type = MT_DEVICE
64 }
65};
66
67/*
68 * Set up static virtual mappings.
69 */
70void __init mx31lite_map_io(void)
71{
72 mxc_map_io();
73 iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
74}
75
76/*
77 * Board specific initialization.
78 */
79static void __init mxc_board_init(void)
80{
81}
82
83static void __init mx31lite_timer_init(void)
84{
85 mxc_clocks_init(26000000);
86 mxc_timer_init("ipg_clk.0");
87}
88
89struct sys_timer mx31lite_timer = {
90 .init = mx31lite_timer_init,
91};
92
93/*
94 * The following uses standard kernel macros defined in arch.h in order to
95 * initialize __mach_desc_MX31LITE data structure.
96 */
97
98MACHINE_START(MX31LITE, "LogicPD MX31 LITEKIT")
99 /* Maintainer: Freescale Semiconductor, Inc. */
100 .phys_io = AIPS1_BASE_ADDR,
101 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
102 .boot_params = PHYS_OFFSET + 0x100,
103 .map_io = mx31lite_map_io,
104 .init_irq = mxc_init_irq,
105 .init_machine = mxc_board_init,
106 .timer = &mx31lite_timer,
107MACHINE_END
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c
new file mode 100644
index 000000000000..a34ae6de266f
--- /dev/null
+++ b/arch/arm/mach-mx3/pcm037.c
@@ -0,0 +1,130 @@
1/*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#include <linux/types.h>
20#include <linux/init.h>
21
22#include <linux/platform_device.h>
23#include <linux/mtd/physmap.h>
24#include <linux/memory.h>
25
26#include <asm/hardware.h>
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/time.h>
30#include <asm/mach/map.h>
31#include <asm/arch/common.h>
32#include <asm/arch/imx-uart.h>
33#include <asm/arch/iomux-mx3.h>
34#include <asm/arch/board-pcm037.h>
35
36static struct physmap_flash_data pcm037_flash_data = {
37 .width = 2,
38};
39
40static struct resource pcm037_flash_resource = {
41 .start = 0xa0000000,
42 .end = 0xa1ffffff,
43 .flags = IORESOURCE_MEM,
44};
45
46static struct platform_device pcm037_flash = {
47 .name = "physmap-flash",
48 .id = 0,
49 .dev = {
50 .platform_data = &pcm037_flash_data,
51 },
52 .resource = &pcm037_flash_resource,
53 .num_resources = 1,
54};
55
56static struct imxuart_platform_data uart_pdata = {
57 .flags = 0,
58};
59
60static struct platform_device *devices[] __initdata = {
61 &pcm037_flash,
62};
63
64/*
65 * Board specific initialization.
66 */
67static void __init mxc_board_init(void)
68{
69 platform_add_devices(devices, ARRAY_SIZE(devices));
70
71 mxc_iomux_mode(MX31_PIN_CTS1__CTS1);
72 mxc_iomux_mode(MX31_PIN_RTS1__RTS1);
73 mxc_iomux_mode(MX31_PIN_TXD1__TXD1);
74 mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
75
76 imx_init_uart(0, &uart_pdata);
77
78 mxc_iomux_mode(MX31_PIN_CSPI3_MOSI__RXD3);
79 mxc_iomux_mode(MX31_PIN_CSPI3_MISO__TXD3);
80
81 imx_init_uart(2, &uart_pdata);
82}
83
84/*
85 * This structure defines static mappings for the pcm037 board.
86 */
87static struct map_desc pcm037_io_desc[] __initdata = {
88 {
89 .virtual = AIPS1_BASE_ADDR_VIRT,
90 .pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
91 .length = AIPS1_SIZE,
92 .type = MT_DEVICE
93 }, {
94 .virtual = AIPS2_BASE_ADDR_VIRT,
95 .pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
96 .length = AIPS2_SIZE,
97 .type = MT_DEVICE
98 },
99};
100
101/*
102 * Set up static virtual mappings.
103 */
104void __init pcm037_map_io(void)
105{
106 mxc_map_io();
107 iotable_init(pcm037_io_desc, ARRAY_SIZE(pcm037_io_desc));
108}
109
110static void __init pcm037_timer_init(void)
111{
112 mxc_clocks_init(26000000);
113 mxc_timer_init("ipg_clk.0");
114}
115
116struct sys_timer pcm037_timer = {
117 .init = pcm037_timer_init,
118};
119
120MACHINE_START(PCM037, "Phytec Phycore pcm037")
121 /* Maintainer: Pengutronix */
122 .phys_io = AIPS1_BASE_ADDR,
123 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
124 .boot_params = PHYS_OFFSET + 0x100,
125 .map_io = pcm037_map_io,
126 .init_irq = mxc_init_irq,
127 .init_machine = mxc_board_init,
128 .timer = &pcm037_timer,
129MACHINE_END
130
diff --git a/arch/arm/mach-mx3/time.c b/arch/arm/mach-mx3/time.c
deleted file mode 100644
index fb565c98dbfb..000000000000
--- a/arch/arm/mach-mx3/time.c
+++ /dev/null
@@ -1,148 +0,0 @@
1/*
2 * System Timer Interrupt reconfigured to run in free-run mode.
3 * Author: Vitaly Wool
4 * Copyright 2004 MontaVista Software Inc.
5 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 */
7
8/*
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14/*!
15 * @file time.c
16 * @brief This file contains OS tick and wdog timer implementations.
17 *
18 * This file contains OS tick and wdog timer implementations.
19 *
20 * @ingroup Timers
21 */
22
23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <asm/hardware.h>
28#include <asm/mach/time.h>
29#include <asm/io.h>
30#include <asm/arch/common.h>
31
32/*!
33 * This is the timer interrupt service routine to do required tasks.
34 * It also services the WDOG timer at the frequency of twice per WDOG
35 * timeout value. For example, if the WDOG's timeout value is 4 (2
36 * seconds since the WDOG runs at 0.5Hz), it will be serviced once
37 * every 2/2=1 second.
38 *
39 * @param irq GPT interrupt source number (not used)
40 * @param dev_id this parameter is not used
41 * @return always returns \b IRQ_HANDLED as defined in
42 * include/linux/interrupt.h.
43 */
44static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
45{
46 unsigned int next_match;
47
48 if (__raw_readl(MXC_GPT_GPTSR) & GPTSR_OF1) {
49 do {
50 timer_tick();
51 next_match = __raw_readl(MXC_GPT_GPTOCR1) + LATCH;
52 __raw_writel(GPTSR_OF1, MXC_GPT_GPTSR);
53 __raw_writel(next_match, MXC_GPT_GPTOCR1);
54 } while ((signed long)(next_match -
55 __raw_readl(MXC_GPT_GPTCNT)) <= 0);
56 }
57
58 return IRQ_HANDLED;
59}
60
61/*!
62 * This function is used to obtain the number of microseconds since the last
63 * timer interrupt. Note that interrupts is disabled by do_gettimeofday().
64 *
65 * @return the number of microseconds since the last timer interrupt.
66 */
67static unsigned long mxc_gettimeoffset(void)
68{
69 unsigned long ticks_to_match, elapsed, usec, tick_usec, i;
70
71 /* Get ticks before next timer match */
72 ticks_to_match =
73 __raw_readl(MXC_GPT_GPTOCR1) - __raw_readl(MXC_GPT_GPTCNT);
74
75 /* We need elapsed ticks since last match */
76 elapsed = LATCH - ticks_to_match;
77
78 /* Now convert them to usec */
79 /* Insure no overflow when calculating the usec below */
80 for (i = 1, tick_usec = tick_nsec / 1000;; i *= 2) {
81 tick_usec /= i;
82 if ((0xFFFFFFFF / tick_usec) > elapsed)
83 break;
84 }
85 usec = (unsigned long)(elapsed * tick_usec) / (LATCH / i);
86
87 return usec;
88}
89
90/*!
91 * The OS tick timer interrupt structure.
92 */
93static struct irqaction timer_irq = {
94 .name = "MXC Timer Tick",
95 .flags = IRQF_DISABLED | IRQF_TIMER,
96 .handler = mxc_timer_interrupt
97};
98
99/*!
100 * This function is used to initialize the GPT to produce an interrupt
101 * based on HZ. It is called by start_kernel() during system startup.
102 */
103void __init mxc_init_time(void)
104{
105 u32 reg, v;
106 reg = __raw_readl(MXC_GPT_GPTCR);
107 reg &= ~GPTCR_ENABLE;
108 __raw_writel(reg, MXC_GPT_GPTCR);
109 reg |= GPTCR_SWR;
110 __raw_writel(reg, MXC_GPT_GPTCR);
111
112 while ((__raw_readl(MXC_GPT_GPTCR) & GPTCR_SWR) != 0)
113 cpu_relax();
114
115 reg = GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ;
116 __raw_writel(reg, MXC_GPT_GPTCR);
117
118 /* TODO: get timer rate from clk driver */
119 v = 66500000;
120
121 __raw_writel((v / CLOCK_TICK_RATE) - 1, MXC_GPT_GPTPR);
122
123 if ((v % CLOCK_TICK_RATE) != 0) {
124 pr_info("\nWARNING: Can't generate CLOCK_TICK_RATE at %d Hz\n",
125 CLOCK_TICK_RATE);
126 }
127 pr_info("Actual CLOCK_TICK_RATE is %d Hz\n",
128 v / ((__raw_readl(MXC_GPT_GPTPR) & 0xFFF) + 1));
129
130 reg = __raw_readl(MXC_GPT_GPTCNT);
131 reg += LATCH;
132 __raw_writel(reg, MXC_GPT_GPTOCR1);
133
134 setup_irq(MXC_INT_GPT, &timer_irq);
135
136 reg = __raw_readl(MXC_GPT_GPTCR);
137 reg =
138 GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ | GPTCR_STOPEN | GPTCR_DOZEN |
139 GPTCR_WAITEN | GPTCR_ENMOD | GPTCR_ENABLE;
140 __raw_writel(reg, MXC_GPT_GPTCR);
141
142 __raw_writel(GPTIR_OF1IE, MXC_GPT_GPTIR);
143}
144
145struct sys_timer mxc_timer = {
146 .init = mxc_init_time,
147 .offset = mxc_gettimeoffset,
148};
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index a2c8b006d710..3a6c8ec34cd9 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -180,8 +180,21 @@ config CPU_ARM925T
180# ARM926T 180# ARM926T
181config CPU_ARM926T 181config CPU_ARM926T
182 bool "Support ARM926T processor" 182 bool "Support ARM926T processor"
183 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI 183 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || \
184 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI 184 MACH_VERSATILE_AB || ARCH_OMAP730 || \
185 ARCH_OMAP16XX || MACH_REALVIEW_EB || \
186 ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \
187 ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \
188 ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \
189 ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \
190 ARCH_NS9XXX || ARCH_DAVINCI
191 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || \
192 ARCH_OMAP730 || ARCH_OMAP16XX || \
193 ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || \
194 ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || \
195 ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || \
196 ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || \
197 ARCH_NS9XXX || ARCH_DAVINCI || ARCH_MX2
185 select CPU_32v5 198 select CPU_32v5
186 select CPU_ABRT_EV5TJ 199 select CPU_ABRT_EV5TJ
187 select CPU_PABRT_NOIFAR 200 select CPU_PABRT_NOIFAR
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index bb6e12738fb3..e14eaad11dd5 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -3,9 +3,14 @@ if ARCH_MXC
3menu "Freescale MXC Implementations" 3menu "Freescale MXC Implementations"
4 4
5choice 5choice
6 prompt "MXC/iMX System Type" 6 prompt "MXC/iMX Base Type"
7 default ARCH_MX3 7 default ARCH_MX3
8 8
9config ARCH_MX2
10 bool "MX2-based"
11 help
12 This enables support for systems based on the Freescale i.MX2 family
13
9config ARCH_MX3 14config ARCH_MX3
10 bool "MX3-based" 15 bool "MX3-based"
11 help 16 help
@@ -13,6 +18,7 @@ config ARCH_MX3
13 18
14endchoice 19endchoice
15 20
21source "arch/arm/mach-mx2/Kconfig"
16source "arch/arm/mach-mx3/Kconfig" 22source "arch/arm/mach-mx3/Kconfig"
17 23
18endmenu 24endmenu
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index f96dc0362068..db66e9ae8414 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -3,4 +3,6 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := irq.o 6obj-y := irq.o clock.o gpio.o time.o
7
8obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
new file mode 100644
index 000000000000..1aa86fd60d71
--- /dev/null
+++ b/arch/arm/plat-mxc/clock.c
@@ -0,0 +1,331 @@
1/*
2 * Based on arch/arm/plat-omap/clock.c
3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
7 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
8 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301, USA.
23 */
24
25/* #define DEBUG */
26
27#include <linux/clk.h>
28#include <linux/err.h>
29#include <linux/errno.h>
30#include <linux/init.h>
31#include <linux/io.h>
32#include <linux/kernel.h>
33#include <linux/list.h>
34#include <linux/module.h>
35#include <linux/mutex.h>
36#include <linux/platform_device.h>
37#include <linux/proc_fs.h>
38#include <linux/semaphore.h>
39#include <linux/string.h>
40#include <linux/version.h>
41
42#include <asm/arch/clock.h>
43
44static LIST_HEAD(clocks);
45static DEFINE_MUTEX(clocks_mutex);
46
47/*-------------------------------------------------------------------------
48 * Standard clock functions defined in include/linux/clk.h
49 *-------------------------------------------------------------------------*/
50
51/*
52 * Retrieve a clock by name.
53 *
54 * Note that we first try to use device id on the bus
55 * and clock name. If this fails, we try to use "<name>.<id>". If this fails,
56 * we try to use clock name only.
57 * The reference count to the clock's module owner ref count is incremented.
58 */
59struct clk *clk_get(struct device *dev, const char *id)
60{
61 struct clk *p, *clk = ERR_PTR(-ENOENT);
62 int idno;
63 const char *str;
64
65 if (id == NULL)
66 return clk;
67
68 if (dev == NULL || dev->bus != &platform_bus_type)
69 idno = -1;
70 else
71 idno = to_platform_device(dev)->id;
72
73 mutex_lock(&clocks_mutex);
74
75 list_for_each_entry(p, &clocks, node) {
76 if (p->id == idno &&
77 strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
78 clk = p;
79 goto found;
80 }
81 }
82
83 str = strrchr(id, '.');
84 if (str) {
85 int cnt = str - id;
86 str++;
87 idno = simple_strtol(str, NULL, 10);
88 list_for_each_entry(p, &clocks, node) {
89 if (p->id == idno &&
90 strlen(p->name) == cnt &&
91 strncmp(id, p->name, cnt) == 0 &&
92 try_module_get(p->owner)) {
93 clk = p;
94 goto found;
95 }
96 }
97 }
98
99 list_for_each_entry(p, &clocks, node) {
100 if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
101 clk = p;
102 goto found;
103 }
104 }
105
106 printk(KERN_WARNING "clk: Unable to get requested clock: %s\n", id);
107
108found:
109 mutex_unlock(&clocks_mutex);
110
111 return clk;
112}
113EXPORT_SYMBOL(clk_get);
114
115static void __clk_disable(struct clk *clk)
116{
117 if (clk == NULL || IS_ERR(clk))
118 return;
119
120 __clk_disable(clk->parent);
121 __clk_disable(clk->secondary);
122
123 if (!(--clk->usecount) && clk->disable)
124 clk->disable(clk);
125}
126
127static int __clk_enable(struct clk *clk)
128{
129 if (clk == NULL || IS_ERR(clk))
130 return -EINVAL;
131
132 __clk_enable(clk->parent);
133 __clk_enable(clk->secondary);
134
135 if (clk->usecount++ == 0 && clk->enable)
136 clk->enable(clk);
137
138 return 0;
139}
140
141/* This function increments the reference count on the clock and enables the
142 * clock if not already enabled. The parent clock tree is recursively enabled
143 */
144int clk_enable(struct clk *clk)
145{
146 int ret = 0;
147
148 if (clk == NULL || IS_ERR(clk))
149 return -EINVAL;
150
151 mutex_lock(&clocks_mutex);
152 ret = __clk_enable(clk);
153 mutex_unlock(&clocks_mutex);
154
155 return ret;
156}
157EXPORT_SYMBOL(clk_enable);
158
159/* This function decrements the reference count on the clock and disables
160 * the clock when reference count is 0. The parent clock tree is
161 * recursively disabled
162 */
163void clk_disable(struct clk *clk)
164{
165 if (clk == NULL || IS_ERR(clk))
166 return;
167
168 mutex_lock(&clocks_mutex);
169 __clk_disable(clk);
170 mutex_unlock(&clocks_mutex);
171}
172EXPORT_SYMBOL(clk_disable);
173
174/* Retrieve the *current* clock rate. If the clock itself
175 * does not provide a special calculation routine, ask
176 * its parent and so on, until one is able to return
177 * a valid clock rate
178 */
179unsigned long clk_get_rate(struct clk *clk)
180{
181 if (clk == NULL || IS_ERR(clk))
182 return 0UL;
183
184 if (clk->get_rate)
185 return clk->get_rate(clk);
186
187 return clk_get_rate(clk->parent);
188}
189EXPORT_SYMBOL(clk_get_rate);
190
191/* Decrement the clock's module reference count */
192void clk_put(struct clk *clk)
193{
194 if (clk && !IS_ERR(clk))
195 module_put(clk->owner);
196}
197EXPORT_SYMBOL(clk_put);
198
199/* Round the requested clock rate to the nearest supported
200 * rate that is less than or equal to the requested rate.
201 * This is dependent on the clock's current parent.
202 */
203long clk_round_rate(struct clk *clk, unsigned long rate)
204{
205 if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
206 return 0;
207
208 return clk->round_rate(clk, rate);
209}
210EXPORT_SYMBOL(clk_round_rate);
211
212/* Set the clock to the requested clock rate. The rate must
213 * match a supported rate exactly based on what clk_round_rate returns
214 */
215int clk_set_rate(struct clk *clk, unsigned long rate)
216{
217 int ret = -EINVAL;
218
219 if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
220 return ret;
221
222 mutex_lock(&clocks_mutex);
223 ret = clk->set_rate(clk, rate);
224 mutex_unlock(&clocks_mutex);
225
226 return ret;
227}
228EXPORT_SYMBOL(clk_set_rate);
229
230/* Set the clock's parent to another clock source */
231int clk_set_parent(struct clk *clk, struct clk *parent)
232{
233 int ret = -EINVAL;
234
235 if (clk == NULL || IS_ERR(clk) || parent == NULL ||
236 IS_ERR(parent) || clk->set_parent == NULL)
237 return ret;
238
239 mutex_lock(&clocks_mutex);
240 ret = clk->set_parent(clk, parent);
241 if (ret == 0)
242 clk->parent = parent;
243 mutex_unlock(&clocks_mutex);
244
245 return ret;
246}
247EXPORT_SYMBOL(clk_set_parent);
248
249/* Retrieve the clock's parent clock source */
250struct clk *clk_get_parent(struct clk *clk)
251{
252 struct clk *ret = NULL;
253
254 if (clk == NULL || IS_ERR(clk))
255 return ret;
256
257 return clk->parent;
258}
259EXPORT_SYMBOL(clk_get_parent);
260
261/*
262 * Add a new clock to the clock tree.
263 */
264int clk_register(struct clk *clk)
265{
266 if (clk == NULL || IS_ERR(clk))
267 return -EINVAL;
268
269 mutex_lock(&clocks_mutex);
270 list_add(&clk->node, &clocks);
271 mutex_unlock(&clocks_mutex);
272
273 return 0;
274}
275EXPORT_SYMBOL(clk_register);
276
277/* Remove a clock from the clock tree */
278void clk_unregister(struct clk *clk)
279{
280 if (clk == NULL || IS_ERR(clk))
281 return;
282
283 mutex_lock(&clocks_mutex);
284 list_del(&clk->node);
285 mutex_unlock(&clocks_mutex);
286}
287EXPORT_SYMBOL(clk_unregister);
288
289#ifdef CONFIG_PROC_FS
290static int mxc_clock_read_proc(char *page, char **start, off_t off,
291 int count, int *eof, void *data)
292{
293 struct clk *clkp;
294 char *p = page;
295 int len;
296
297 list_for_each_entry(clkp, &clocks, node) {
298 p += sprintf(p, "%s-%d:\t\t%lu, %d", clkp->name, clkp->id,
299 clk_get_rate(clkp), clkp->usecount);
300 if (clkp->parent)
301 p += sprintf(p, ", %s-%d\n", clkp->parent->name,
302 clkp->parent->id);
303 else
304 p += sprintf(p, "\n");
305 }
306
307 len = (p - page) - off;
308 if (len < 0)
309 len = 0;
310
311 *eof = (len <= count) ? 1 : 0;
312 *start = page + off;
313
314 return len;
315}
316
317static int __init mxc_setup_proc_entry(void)
318{
319 struct proc_dir_entry *res;
320
321 res = create_proc_read_entry("cpu/clocks", 0, NULL,
322 mxc_clock_read_proc, NULL);
323 if (!res) {
324 printk(KERN_ERR "Failed to create proc/cpu/clocks\n");
325 return -ENOMEM;
326 }
327 return 0;
328}
329
330late_initcall(mxc_setup_proc_entry);
331#endif
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
new file mode 100644
index 000000000000..4a7736717d86
--- /dev/null
+++ b/arch/arm/plat-mxc/gpio.c
@@ -0,0 +1,253 @@
1/*
2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * Based on code from Freescale,
6 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 */
21
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/irq.h>
25#include <linux/gpio.h>
26#include <asm/hardware.h>
27#include <asm-generic/bug.h>
28
29static struct mxc_gpio_port *mxc_gpio_ports;
30static int gpio_table_size;
31
32/* Note: This driver assumes 32 GPIOs are handled in one register */
33
34static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
35{
36 __raw_writel(1 << index, port->base + GPIO_ISR);
37}
38
39static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
40 int enable)
41{
42 u32 l;
43
44 l = __raw_readl(port->base + GPIO_IMR);
45 l = (l & (~(1 << index))) | (!!enable << index);
46 __raw_writel(l, port->base + GPIO_IMR);
47}
48
49static void gpio_ack_irq(u32 irq)
50{
51 u32 gpio = irq_to_gpio(irq);
52 _clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f);
53}
54
55static void gpio_mask_irq(u32 irq)
56{
57 u32 gpio = irq_to_gpio(irq);
58 _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0);
59}
60
61static void gpio_unmask_irq(u32 irq)
62{
63 u32 gpio = irq_to_gpio(irq);
64 _set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1);
65}
66
67static int gpio_set_irq_type(u32 irq, u32 type)
68{
69 u32 gpio = irq_to_gpio(irq);
70 struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
71 u32 bit, val;
72 int edge;
73 void __iomem *reg = port->base;
74
75 switch (type) {
76 case IRQT_RISING:
77 edge = GPIO_INT_RISE_EDGE;
78 break;
79 case IRQT_FALLING:
80 edge = GPIO_INT_FALL_EDGE;
81 break;
82 case IRQT_LOW:
83 edge = GPIO_INT_LOW_LEV;
84 break;
85 case IRQT_HIGH:
86 edge = GPIO_INT_HIGH_LEV;
87 break;
88 default: /* this includes IRQT_BOTHEDGE */
89 return -EINVAL;
90 }
91
92 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
93 bit = gpio & 0xf;
94 val = __raw_readl(reg) & ~(0x3 << (bit << 1));
95 __raw_writel(val | (edge << (bit << 1)), reg);
96 _clear_gpio_irqstatus(port, gpio & 0x1f);
97
98 return 0;
99}
100
101/* handle n interrupts in one status register */
102static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
103{
104 u32 gpio_irq_no;
105
106 gpio_irq_no = port->virtual_irq_start;
107 for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) {
108
109 if ((irq_stat & 1) == 0)
110 continue;
111
112 BUG_ON(!(irq_desc[gpio_irq_no].handle_irq));
113 irq_desc[gpio_irq_no].handle_irq(gpio_irq_no,
114 &irq_desc[gpio_irq_no]);
115 }
116}
117
118#ifdef CONFIG_ARCH_MX3
119/* MX3 has one interrupt *per* gpio port */
120static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
121{
122 u32 irq_stat;
123 struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
124
125 irq_stat = __raw_readl(port->base + GPIO_ISR) &
126 __raw_readl(port->base + GPIO_IMR);
127 BUG_ON(!irq_stat);
128 mxc_gpio_irq_handler(port, irq_stat);
129}
130#endif
131
132#ifdef CONFIG_ARCH_MX2
133/* MX2 has one interrupt *for all* gpio ports */
134static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
135{
136 int i;
137 u32 irq_msk, irq_stat;
138 struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
139
140 /* walk through all interrupt status registers */
141 for (i = 0; i < gpio_table_size; i++) {
142 irq_msk = __raw_readl(port[i].base + GPIO_IMR);
143 if (!irq_msk)
144 continue;
145
146 irq_stat = __raw_readl(port[i].base + GPIO_ISR) & irq_msk;
147 if (irq_stat)
148 mxc_gpio_irq_handler(&port[i], irq_stat);
149 }
150}
151#endif
152
153static struct irq_chip gpio_irq_chip = {
154 .ack = gpio_ack_irq,
155 .mask = gpio_mask_irq,
156 .unmask = gpio_unmask_irq,
157 .set_type = gpio_set_irq_type,
158};
159
160static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
161 int dir)
162{
163 struct mxc_gpio_port *port =
164 container_of(chip, struct mxc_gpio_port, chip);
165 u32 l;
166
167 l = __raw_readl(port->base + GPIO_GDIR);
168 if (dir)
169 l |= 1 << offset;
170 else
171 l &= ~(1 << offset);
172 __raw_writel(l, port->base + GPIO_GDIR);
173}
174
175static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
176{
177 struct mxc_gpio_port *port =
178 container_of(chip, struct mxc_gpio_port, chip);
179 void __iomem *reg = port->base + GPIO_DR;
180 u32 l;
181
182 l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset);
183 __raw_writel(l, reg);
184}
185
186static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
187{
188 struct mxc_gpio_port *port =
189 container_of(chip, struct mxc_gpio_port, chip);
190
191 return (__raw_readl(port->base + GPIO_DR) >> offset) & 1;
192}
193
194static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
195{
196 _set_gpio_direction(chip, offset, 0);
197 return 0;
198}
199
200static int mxc_gpio_direction_output(struct gpio_chip *chip,
201 unsigned offset, int value)
202{
203 _set_gpio_direction(chip, offset, 1);
204 mxc_gpio_set(chip, offset, value);
205 return 0;
206}
207
208int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
209{
210 int i, j;
211
212 /* save for local usage */
213 mxc_gpio_ports = port;
214 gpio_table_size = cnt;
215
216 printk(KERN_INFO "MXC GPIO hardware\n");
217
218 for (i = 0; i < cnt; i++) {
219 /* disable the interrupt and clear the status */
220 __raw_writel(0, port[i].base + GPIO_IMR);
221 __raw_writel(~0, port[i].base + GPIO_ISR);
222 for (j = port[i].virtual_irq_start;
223 j < port[i].virtual_irq_start + 32; j++) {
224 set_irq_chip(j, &gpio_irq_chip);
225 set_irq_handler(j, handle_edge_irq);
226 set_irq_flags(j, IRQF_VALID);
227 }
228
229 /* register gpio chip */
230 port[i].chip.direction_input = mxc_gpio_direction_input;
231 port[i].chip.direction_output = mxc_gpio_direction_output;
232 port[i].chip.get = mxc_gpio_get;
233 port[i].chip.set = mxc_gpio_set;
234 port[i].chip.base = i * 32;
235 port[i].chip.ngpio = 32;
236
237 /* its a serious configuration bug when it fails */
238 BUG_ON( gpiochip_add(&port[i].chip) < 0 );
239
240#ifdef CONFIG_ARCH_MX3
241 /* setup one handler for each entry */
242 set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
243 set_irq_data(port[i].irq, &port[i]);
244#endif
245 }
246
247#ifdef CONFIG_ARCH_MX2
248 /* setup one handler for all GPIO interrupts */
249 set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
250 set_irq_data(port[0].irq, port);
251#endif
252 return 0;
253}
diff --git a/arch/arm/plat-mxc/iomux-mx1-mx2.c b/arch/arm/plat-mxc/iomux-mx1-mx2.c
new file mode 100644
index 000000000000..1985571eb40c
--- /dev/null
+++ b/arch/arm/plat-mxc/iomux-mx1-mx2.c
@@ -0,0 +1,156 @@
1/*
2 * arch/arm/mach-mxc/generic.c
3 *
4 * author: Sascha Hauer
5 * Created: april 20th, 2004
6 * Copyright: Synertronixx GmbH
7 *
8 * Common code for i.MX machines
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26#include <linux/errno.h>
27#include <linux/init.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/string.h>
31#include <linux/gpio.h>
32
33#include <asm/hardware.h>
34#include <asm/mach/map.h>
35#include <asm/arch/iomux-mx1-mx2.h>
36
37void mxc_gpio_mode(int gpio_mode)
38{
39 unsigned int pin = gpio_mode & GPIO_PIN_MASK;
40 unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
41 unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
42 unsigned int tmp;
43
44 /* Pullup enable */
45 tmp = __raw_readl(VA_GPIO_BASE + MXC_PUEN(port));
46 if (gpio_mode & GPIO_PUEN)
47 tmp |= (1 << pin);
48 else
49 tmp &= ~(1 << pin);
50 __raw_writel(tmp, VA_GPIO_BASE + MXC_PUEN(port));
51
52 /* Data direction */
53 tmp = __raw_readl(VA_GPIO_BASE + MXC_DDIR(port));
54 if (gpio_mode & GPIO_OUT)
55 tmp |= 1 << pin;
56 else
57 tmp &= ~(1 << pin);
58 __raw_writel(tmp, VA_GPIO_BASE + MXC_DDIR(port));
59
60 /* Primary / alternate function */
61 tmp = __raw_readl(VA_GPIO_BASE + MXC_GPR(port));
62 if (gpio_mode & GPIO_AF)
63 tmp |= (1 << pin);
64 else
65 tmp &= ~(1 << pin);
66 __raw_writel(tmp, VA_GPIO_BASE + MXC_GPR(port));
67
68 /* use as gpio? */
69 tmp = __raw_readl(VA_GPIO_BASE + MXC_GIUS(port));
70 if (gpio_mode & (GPIO_PF | GPIO_AF))
71 tmp &= ~(1 << pin);
72 else
73 tmp |= (1 << pin);
74 __raw_writel(tmp, VA_GPIO_BASE + MXC_GIUS(port));
75
76 if (pin < 16) {
77 tmp = __raw_readl(VA_GPIO_BASE + MXC_OCR1(port));
78 tmp &= ~(3 << (pin * 2));
79 tmp |= (ocr << (pin * 2));
80 __raw_writel(tmp, VA_GPIO_BASE + MXC_OCR1(port));
81
82 tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFA1(port));
83 tmp &= ~(3 << (pin * 2));
84 tmp |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2);
85 __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFA1(port));
86
87 tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFB1(port));
88 tmp &= ~(3 << (pin * 2));
89 tmp |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2);
90 __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFB1(port));
91 } else {
92 pin -= 16;
93
94 tmp = __raw_readl(VA_GPIO_BASE + MXC_OCR2(port));
95 tmp &= ~(3 << (pin * 2));
96 tmp |= (ocr << (pin * 2));
97 __raw_writel(tmp, VA_GPIO_BASE + MXC_OCR2(port));
98
99 tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFA2(port));
100 tmp &= ~(3 << (pin * 2));
101 tmp |= ((gpio_mode >> GPIO_AOUT_SHIFT) & 3) << (pin * 2);
102 __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFA2(port));
103
104 tmp = __raw_readl(VA_GPIO_BASE + MXC_ICONFB2(port));
105 tmp &= ~(3 << (pin * 2));
106 tmp |= ((gpio_mode >> GPIO_BOUT_SHIFT) & 3) << (pin * 2);
107 __raw_writel(tmp, VA_GPIO_BASE + MXC_ICONFB2(port));
108 }
109}
110EXPORT_SYMBOL(mxc_gpio_mode);
111
112int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
113 int alloc_mode, const char *label)
114{
115 const int *p = pin_list;
116 int i;
117 unsigned gpio;
118 unsigned mode;
119
120 for (i = 0; i < count; i++) {
121 gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
122 mode = *p & ~(GPIO_PIN_MASK | GPIO_PORT_MASK);
123
124 if (gpio >= (GPIO_PORT_MAX + 1) * 32)
125 goto setup_error;
126
127 if (alloc_mode & MXC_GPIO_ALLOC_MODE_RELEASE)
128 gpio_free(gpio);
129 else if (!(alloc_mode & MXC_GPIO_ALLOC_MODE_NO_ALLOC))
130 if (gpio_request(gpio, label)
131 && !(alloc_mode & MXC_GPIO_ALLOC_MODE_TRY_ALLOC))
132 goto setup_error;
133
134 if (!(alloc_mode & (MXC_GPIO_ALLOC_MODE_ALLOC_ONLY |
135 MXC_GPIO_ALLOC_MODE_RELEASE)))
136 mxc_gpio_mode(gpio | mode);
137
138 p++;
139 }
140 return 0;
141
142setup_error:
143 if (alloc_mode & (MXC_GPIO_ALLOC_MODE_NO_ALLOC |
144 MXC_GPIO_ALLOC_MODE_TRY_ALLOC))
145 return -EINVAL;
146
147 while (p != pin_list) {
148 p--;
149 gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
150 gpio_free(gpio);
151 }
152
153 return -EINVAL;
154}
155EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
156
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 2ad5a6917b3f..1fbe01da6925 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -1,24 +1,59 @@
1/* 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
3 */ 18 */
4 19
5/* 20#include <linux/irq.h>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/device.h>
15#include <linux/errno.h>
16#include <asm/hardware.h>
17#include <asm/io.h> 21#include <asm/io.h>
18#include <asm/irq.h>
19#include <asm/mach/irq.h>
20#include <asm/arch/common.h> 22#include <asm/arch/common.h>
21 23
24#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
25#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
26#define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */
27#define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */
28#define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */
29#define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */
30#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */
31#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */
32#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */
33#define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */
34#define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */
35#define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */
36#define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */
37#define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */
38#define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */
39#define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */
40#define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */
41#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */
42#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */
43#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */
44#define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */
45#define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */
46#define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */
47#define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */
48#define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */
49#define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */
50#define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */
51
52#define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20)
53#define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24)
54#define IIM_PROD_REV_SH 3
55#define IIM_PROD_REV_LEN 5
56
22/* Disable interrupt number "irq" in the AVIC */ 57/* Disable interrupt number "irq" in the AVIC */
23static void mxc_mask_irq(unsigned int irq) 58static void mxc_mask_irq(unsigned int irq)
24{ 59{
@@ -32,7 +67,7 @@ static void mxc_unmask_irq(unsigned int irq)
32} 67}
33 68
34static struct irq_chip mxc_avic_chip = { 69static struct irq_chip mxc_avic_chip = {
35 .mask_ack = mxc_mask_irq, 70 .ack = mxc_mask_irq,
36 .mask = mxc_mask_irq, 71 .mask = mxc_mask_irq,
37 .unmask = mxc_unmask_irq, 72 .unmask = mxc_unmask_irq,
38}; 73};
@@ -71,5 +106,8 @@ void __init mxc_init_irq(void)
71 reg |= (0xF << 28); 106 reg |= (0xF << 28);
72 __raw_writel(reg, AVIC_NIPRIORITY6); 107 __raw_writel(reg, AVIC_NIPRIORITY6);
73 108
109 /* init architectures chained interrupt handler */
110 mxc_register_gpios();
111
74 printk(KERN_INFO "MXC IRQ initialized\n"); 112 printk(KERN_INFO "MXC IRQ initialized\n");
75} 113}
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
new file mode 100644
index 000000000000..3bf86343fdf4
--- /dev/null
+++ b/arch/arm/plat-mxc/time.c
@@ -0,0 +1,228 @@
1/*
2 * linux/arch/arm/plat-mxc/time.c
3 *
4 * Copyright (C) 2000-2001 Deep Blue Solutions
5 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
6 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
7 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
21 * MA 02110-1301, USA.
22 */
23
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/clockchips.h>
27#include <linux/clk.h>
28
29#include <asm/hardware.h>
30#include <asm/mach/time.h>
31#include <asm/arch/common.h>
32#include <asm/arch/mxc_timer.h>
33
34static struct clock_event_device clockevent_mxc;
35static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
36
37/* clock source for the timer */
38static struct clk *timer_clk;
39
40/* clock source */
41
42static cycle_t mxc_get_cycles(void)
43{
44 return __raw_readl(TIMER_BASE + MXC_TCN);
45}
46
47static struct clocksource clocksource_mxc = {
48 .name = "mxc_timer1",
49 .rating = 200,
50 .read = mxc_get_cycles,
51 .mask = CLOCKSOURCE_MASK(32),
52 .shift = 20,
53 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
54};
55
56static int __init mxc_clocksource_init(void)
57{
58 unsigned int clock;
59
60 clock = clk_get_rate(timer_clk);
61
62 clocksource_mxc.mult = clocksource_hz2mult(clock,
63 clocksource_mxc.shift);
64 clocksource_register(&clocksource_mxc);
65
66 return 0;
67}
68
69/* clock event */
70
71static int mxc_set_next_event(unsigned long evt,
72 struct clock_event_device *unused)
73{
74 unsigned long tcmp;
75
76 tcmp = __raw_readl(TIMER_BASE + MXC_TCN) + evt;
77 __raw_writel(tcmp, TIMER_BASE + MXC_TCMP);
78
79 return (int)(tcmp - __raw_readl(TIMER_BASE + MXC_TCN)) < 0 ?
80 -ETIME : 0;
81}
82
83#ifdef DEBUG
84static const char *clock_event_mode_label[] = {
85 [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
86 [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
87 [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
88 [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED"
89};
90#endif /* DEBUG */
91
92static void mxc_set_mode(enum clock_event_mode mode,
93 struct clock_event_device *evt)
94{
95 unsigned long flags;
96
97 /*
98 * The timer interrupt generation is disabled at least
99 * for enough time to call mxc_set_next_event()
100 */
101 local_irq_save(flags);
102
103 /* Disable interrupt in GPT module */
104 gpt_irq_disable();
105
106 if (mode != clockevent_mode) {
107 /* Set event time into far-far future */
108 __raw_writel(__raw_readl(TIMER_BASE + MXC_TCN) - 3,
109 TIMER_BASE + MXC_TCMP);
110 /* Clear pending interrupt */
111 gpt_irq_acknowledge();
112 }
113
114#ifdef DEBUG
115 printk(KERN_INFO "mxc_set_mode: changing mode from %s to %s\n",
116 clock_event_mode_label[clockevent_mode],
117 clock_event_mode_label[mode]);
118#endif /* DEBUG */
119
120 /* Remember timer mode */
121 clockevent_mode = mode;
122 local_irq_restore(flags);
123
124 switch (mode) {
125 case CLOCK_EVT_MODE_PERIODIC:
126 printk(KERN_ERR"mxc_set_mode: Periodic mode is not "
127 "supported for i.MX\n");
128 break;
129 case CLOCK_EVT_MODE_ONESHOT:
130 /*
131 * Do not put overhead of interrupt enable/disable into
132 * mxc_set_next_event(), the core has about 4 minutes
133 * to call mxc_set_next_event() or shutdown clock after
134 * mode switching
135 */
136 local_irq_save(flags);
137 gpt_irq_enable();
138 local_irq_restore(flags);
139 break;
140 case CLOCK_EVT_MODE_SHUTDOWN:
141 case CLOCK_EVT_MODE_UNUSED:
142 case CLOCK_EVT_MODE_RESUME:
143 /* Left event sources disabled, no more interrupts appear */
144 break;
145 }
146}
147
148/*
149 * IRQ handler for the timer
150 */
151static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
152{
153 struct clock_event_device *evt = &clockevent_mxc;
154 uint32_t tstat;
155
156 tstat = __raw_readl(TIMER_BASE + MXC_TSTAT);
157
158 gpt_irq_acknowledge();
159
160 evt->event_handler(evt);
161
162 return IRQ_HANDLED;
163}
164
165static struct irqaction mxc_timer_irq = {
166 .name = "i.MX Timer Tick",
167 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
168 .handler = mxc_timer_interrupt,
169};
170
171static struct clock_event_device clockevent_mxc = {
172 .name = "mxc_timer1",
173 .features = CLOCK_EVT_FEAT_ONESHOT,
174 .shift = 32,
175 .set_mode = mxc_set_mode,
176 .set_next_event = mxc_set_next_event,
177 .rating = 200,
178};
179
180static int __init mxc_clockevent_init(void)
181{
182 unsigned int clock;
183
184 clock = clk_get_rate(timer_clk);
185
186 clockevent_mxc.mult = div_sc(clock, NSEC_PER_SEC,
187 clockevent_mxc.shift);
188 clockevent_mxc.max_delta_ns =
189 clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
190 clockevent_mxc.min_delta_ns =
191 clockevent_delta2ns(0xff, &clockevent_mxc);
192
193 clockevent_mxc.cpumask = cpumask_of_cpu(0);
194
195 clockevents_register_device(&clockevent_mxc);
196
197 return 0;
198}
199
200void __init mxc_timer_init(const char *clk_timer)
201{
202 timer_clk = clk_get(NULL, clk_timer);
203 if (!timer_clk) {
204 printk(KERN_ERR"Cannot determine timer clock. Giving up.\n");
205 return;
206 }
207
208 clk_enable(timer_clk);
209
210 /*
211 * Initialise to a known state (all timers off, and timing reset)
212 */
213 __raw_writel(0, TIMER_BASE + MXC_TCTL);
214 __raw_writel(0, TIMER_BASE + MXC_TPRER); /* see datasheet note */
215
216 __raw_writel(TCTL_FRR | /* free running */
217 TCTL_VAL | /* set clocksource and arch specific bits */
218 TCTL_TEN, /* start the timer */
219 TIMER_BASE + MXC_TCTL);
220
221 /* init and register the timer to the framework */
222 mxc_clocksource_init();
223 mxc_clockevent_init();
224
225 /* Make irqs happen */
226 setup_irq(TIMER_INTERRUPT, &mxc_timer_irq);
227}
228
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 22:21:38 -0500