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authorWill Deacon <will.deacon@arm.com>2011-09-29 10:29:02 -0400
committerWill Deacon <will.deacon@arm.com>2011-12-02 10:16:16 -0500
commit4d301512ab368f83f774f414213a5e6cf3641632 (patch)
tree7fb850540cfe7cae91e8063b97a7c2896f3783ef /arch/arm
parent5611cc4572e889b62a7b4c72a413536bf6a9c416 (diff)
ARM: perf: clean and update ARMv7 event numbers
This patch updates the ARMv7 perf event numbers so that: (1) A consistent naming scheme is used between different CPUs. (2) Only events actually used by Linux are described. (3) Where possible, architected events are used in preference to CPU-specific events. This results in the removal of a load of unused, hardcoded data and makes it more clear as to which events are supported on each PMU. Cc: Jean Pihet <j-pihet@ti.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/kernel/perf_event_v7.c358
1 files changed, 125 insertions, 233 deletions
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 1ef6d0034b85..d2361e7dd884 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -28,165 +28,84 @@ static struct arm_pmu armv7pmu;
28 * they are not available. 28 * they are not available.
29 */ 29 */
30enum armv7_perf_types { 30enum armv7_perf_types {
31 ARMV7_PERFCTR_PMNC_SW_INCR = 0x00, 31 ARMV7_PERFCTR_PMNC_SW_INCR = 0x00,
32 ARMV7_PERFCTR_IFETCH_MISS = 0x01, 32 ARMV7_PERFCTR_L1_ICACHE_REFILL = 0x01,
33 ARMV7_PERFCTR_ITLB_MISS = 0x02, 33 ARMV7_PERFCTR_ITLB_REFILL = 0x02,
34 ARMV7_PERFCTR_DCACHE_REFILL = 0x03, /* L1 */ 34 ARMV7_PERFCTR_L1_DCACHE_REFILL = 0x03,
35 ARMV7_PERFCTR_DCACHE_ACCESS = 0x04, /* L1 */ 35 ARMV7_PERFCTR_L1_DCACHE_ACCESS = 0x04,
36 ARMV7_PERFCTR_DTLB_REFILL = 0x05, 36 ARMV7_PERFCTR_DTLB_REFILL = 0x05,
37 ARMV7_PERFCTR_DREAD = 0x06, 37 ARMV7_PERFCTR_MEM_READ = 0x06,
38 ARMV7_PERFCTR_DWRITE = 0x07, 38 ARMV7_PERFCTR_MEM_WRITE = 0x07,
39 ARMV7_PERFCTR_INSTR_EXECUTED = 0x08, 39 ARMV7_PERFCTR_INSTR_EXECUTED = 0x08,
40 ARMV7_PERFCTR_EXC_TAKEN = 0x09, 40 ARMV7_PERFCTR_EXC_TAKEN = 0x09,
41 ARMV7_PERFCTR_EXC_EXECUTED = 0x0A, 41 ARMV7_PERFCTR_EXC_EXECUTED = 0x0A,
42 ARMV7_PERFCTR_CID_WRITE = 0x0B, 42 ARMV7_PERFCTR_CID_WRITE = 0x0B,
43 /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS. 43
44 /*
45 * ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
44 * It counts: 46 * It counts:
45 * - all branch instructions, 47 * - all (taken) branch instructions,
46 * - instructions that explicitly write the PC, 48 * - instructions that explicitly write the PC,
47 * - exception generating instructions. 49 * - exception generating instructions.
48 */ 50 */
49 ARMV7_PERFCTR_PC_WRITE = 0x0C, 51 ARMV7_PERFCTR_PC_WRITE = 0x0C,
50 ARMV7_PERFCTR_PC_IMM_BRANCH = 0x0D, 52 ARMV7_PERFCTR_PC_IMM_BRANCH = 0x0D,
51 ARMV7_PERFCTR_PC_PROC_RETURN = 0x0E, 53 ARMV7_PERFCTR_PC_PROC_RETURN = 0x0E,
52 ARMV7_PERFCTR_UNALIGNED_ACCESS = 0x0F, 54 ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS = 0x0F,
55 ARMV7_PERFCTR_PC_BRANCH_MIS_PRED = 0x10,
56 ARMV7_PERFCTR_CLOCK_CYCLES = 0x11,
57 ARMV7_PERFCTR_PC_BRANCH_PRED = 0x12,
53 58
54 /* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */ 59 /* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
55 ARMV7_PERFCTR_PC_BRANCH_MIS_PRED = 0x10, 60 ARMV7_PERFCTR_MEM_ACCESS = 0x13,
56 ARMV7_PERFCTR_CLOCK_CYCLES = 0x11, 61 ARMV7_PERFCTR_L1_ICACHE_ACCESS = 0x14,
57 ARMV7_PERFCTR_PC_BRANCH_PRED = 0x12, 62 ARMV7_PERFCTR_L1_DCACHE_WB = 0x15,
58 ARMV7_PERFCTR_MEM_ACCESS = 0x13, 63 ARMV7_PERFCTR_L2_CACHE_ACCESS = 0x16,
59 ARMV7_PERFCTR_L1_ICACHE_ACCESS = 0x14, 64 ARMV7_PERFCTR_L2_CACHE_REFILL = 0x17,
60 ARMV7_PERFCTR_L1_DCACHE_WB = 0x15, 65 ARMV7_PERFCTR_L2_CACHE_WB = 0x18,
61 ARMV7_PERFCTR_L2_DCACHE_ACCESS = 0x16, 66 ARMV7_PERFCTR_BUS_ACCESS = 0x19,
62 ARMV7_PERFCTR_L2_DCACHE_REFILL = 0x17, 67 ARMV7_PERFCTR_MEM_ERROR = 0x1A,
63 ARMV7_PERFCTR_L2_DCACHE_WB = 0x18, 68 ARMV7_PERFCTR_INSTR_SPEC = 0x1B,
64 ARMV7_PERFCTR_BUS_ACCESS = 0x19, 69 ARMV7_PERFCTR_TTBR_WRITE = 0x1C,
65 ARMV7_PERFCTR_MEMORY_ERROR = 0x1A, 70 ARMV7_PERFCTR_BUS_CYCLES = 0x1D,
66 ARMV7_PERFCTR_INSTR_SPEC = 0x1B, 71
67 ARMV7_PERFCTR_TTBR_WRITE = 0x1C, 72 ARMV7_PERFCTR_CPU_CYCLES = 0xFF
68 ARMV7_PERFCTR_BUS_CYCLES = 0x1D,
69
70 ARMV7_PERFCTR_CPU_CYCLES = 0xFF
71}; 73};
72 74
73/* ARMv7 Cortex-A8 specific event types */ 75/* ARMv7 Cortex-A8 specific event types */
74enum armv7_a8_perf_types { 76enum armv7_a8_perf_types {
75 ARMV7_PERFCTR_WRITE_BUFFER_FULL = 0x40, 77 ARMV7_A8_PERFCTR_L2_CACHE_ACCESS = 0x43,
76 ARMV7_PERFCTR_L2_STORE_MERGED = 0x41, 78 ARMV7_A8_PERFCTR_L2_CACHE_REFILL = 0x44,
77 ARMV7_PERFCTR_L2_STORE_BUFF = 0x42, 79 ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS = 0x50,
78 ARMV7_PERFCTR_L2_ACCESS = 0x43,
79 ARMV7_PERFCTR_L2_CACH_MISS = 0x44,
80 ARMV7_PERFCTR_AXI_READ_CYCLES = 0x45,
81 ARMV7_PERFCTR_AXI_WRITE_CYCLES = 0x46,
82 ARMV7_PERFCTR_MEMORY_REPLAY = 0x47,
83 ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY = 0x48,
84 ARMV7_PERFCTR_L1_DATA_MISS = 0x49,
85 ARMV7_PERFCTR_L1_INST_MISS = 0x4A,
86 ARMV7_PERFCTR_L1_DATA_COLORING = 0x4B,
87 ARMV7_PERFCTR_L1_NEON_DATA = 0x4C,
88 ARMV7_PERFCTR_L1_NEON_CACH_DATA = 0x4D,
89 ARMV7_PERFCTR_L2_NEON = 0x4E,
90 ARMV7_PERFCTR_L2_NEON_HIT = 0x4F,
91 ARMV7_PERFCTR_L1_INST = 0x50,
92 ARMV7_PERFCTR_PC_RETURN_MIS_PRED = 0x51,
93 ARMV7_PERFCTR_PC_BRANCH_FAILED = 0x52,
94 ARMV7_PERFCTR_PC_BRANCH_TAKEN = 0x53,
95 ARMV7_PERFCTR_PC_BRANCH_EXECUTED = 0x54,
96 ARMV7_PERFCTR_OP_EXECUTED = 0x55,
97 ARMV7_PERFCTR_CYCLES_INST_STALL = 0x56,
98 ARMV7_PERFCTR_CYCLES_INST = 0x57,
99 ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL = 0x58,
100 ARMV7_PERFCTR_CYCLES_NEON_INST_STALL = 0x59,
101 ARMV7_PERFCTR_NEON_CYCLES = 0x5A,
102
103 ARMV7_PERFCTR_PMU0_EVENTS = 0x70,
104 ARMV7_PERFCTR_PMU1_EVENTS = 0x71,
105 ARMV7_PERFCTR_PMU_EVENTS = 0x72,
106}; 80};
107 81
108/* ARMv7 Cortex-A9 specific event types */ 82/* ARMv7 Cortex-A9 specific event types */
109enum armv7_a9_perf_types { 83enum armv7_a9_perf_types {
110 ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC = 0x40, 84 ARMV7_A9_PERFCTR_INSTR_CORE_RENAME = 0x68,
111 ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC = 0x41,
112 ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC = 0x42,
113
114 ARMV7_PERFCTR_COHERENT_LINE_MISS = 0x50,
115 ARMV7_PERFCTR_COHERENT_LINE_HIT = 0x51,
116
117 ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES = 0x60,
118 ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES = 0x61,
119 ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62,
120 ARMV7_PERFCTR_STREX_EXECUTED_PASSED = 0x63,
121 ARMV7_PERFCTR_STREX_EXECUTED_FAILED = 0x64,
122 ARMV7_PERFCTR_DATA_EVICTION = 0x65,
123 ARMV7_PERFCTR_ISSUE_STAGE_NO_INST = 0x66,
124 ARMV7_PERFCTR_ISSUE_STAGE_EMPTY = 0x67,
125 ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE = 0x68,
126
127 ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E,
128
129 ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST = 0x70,
130 ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71,
131 ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST = 0x72,
132 ARMV7_PERFCTR_FP_EXECUTED_INST = 0x73,
133 ARMV7_PERFCTR_NEON_EXECUTED_INST = 0x74,
134
135 ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80,
136 ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES = 0x81,
137 ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES = 0x82,
138 ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES = 0x83,
139 ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES = 0x84,
140 ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES = 0x85,
141 ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES = 0x86,
142
143 ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES = 0x8A,
144 ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B,
145
146 ARMV7_PERFCTR_ISB_INST = 0x90,
147 ARMV7_PERFCTR_DSB_INST = 0x91,
148 ARMV7_PERFCTR_DMB_INST = 0x92,
149 ARMV7_PERFCTR_EXT_INTERRUPTS = 0x93,
150
151 ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED = 0xA0,
152 ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED = 0xA1,
153 ARMV7_PERFCTR_PLE_FIFO_FLUSH = 0xA2,
154 ARMV7_PERFCTR_PLE_RQST_COMPLETED = 0xA3,
155 ARMV7_PERFCTR_PLE_FIFO_OVERFLOW = 0xA4,
156 ARMV7_PERFCTR_PLE_RQST_PROG = 0xA5
157}; 85};
158 86
159/* ARMv7 Cortex-A5 specific event types */ 87/* ARMv7 Cortex-A5 specific event types */
160enum armv7_a5_perf_types { 88enum armv7_a5_perf_types {
161 ARMV7_PERFCTR_IRQ_TAKEN = 0x86, 89 ARMV7_A5_PERFCTR_PREFETCH_LINEFILL = 0xc2,
162 ARMV7_PERFCTR_FIQ_TAKEN = 0x87, 90 ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP = 0xc3,
163
164 ARMV7_PERFCTR_EXT_MEM_RQST = 0xc0,
165 ARMV7_PERFCTR_NC_EXT_MEM_RQST = 0xc1,
166 ARMV7_PERFCTR_PREFETCH_LINEFILL = 0xc2,
167 ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP = 0xc3,
168 ARMV7_PERFCTR_ENTER_READ_ALLOC = 0xc4,
169 ARMV7_PERFCTR_READ_ALLOC = 0xc5,
170
171 ARMV7_PERFCTR_STALL_SB_FULL = 0xc9,
172}; 91};
173 92
174/* ARMv7 Cortex-A15 specific event types */ 93/* ARMv7 Cortex-A15 specific event types */
175enum armv7_a15_perf_types { 94enum armv7_a15_perf_types {
176 ARMV7_PERFCTR_L1_DCACHE_READ_ACCESS = 0x40, 95 ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ = 0x40,
177 ARMV7_PERFCTR_L1_DCACHE_WRITE_ACCESS = 0x41, 96 ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE = 0x41,
178 ARMV7_PERFCTR_L1_DCACHE_READ_REFILL = 0x42, 97 ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ = 0x42,
179 ARMV7_PERFCTR_L1_DCACHE_WRITE_REFILL = 0x43, 98 ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE = 0x43,
180 99
181 ARMV7_PERFCTR_L1_DTLB_READ_REFILL = 0x4C, 100 ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ = 0x4C,
182 ARMV7_PERFCTR_L1_DTLB_WRITE_REFILL = 0x4D, 101 ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE = 0x4D,
183 102
184 ARMV7_PERFCTR_L2_DCACHE_READ_ACCESS = 0x50, 103 ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ = 0x50,
185 ARMV7_PERFCTR_L2_DCACHE_WRITE_ACCESS = 0x51, 104 ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE = 0x51,
186 ARMV7_PERFCTR_L2_DCACHE_READ_REFILL = 0x52, 105 ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ = 0x52,
187 ARMV7_PERFCTR_L2_DCACHE_WRITE_REFILL = 0x53, 106 ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE = 0x53,
188 107
189 ARMV7_PERFCTR_SPEC_PC_WRITE = 0x76, 108 ARMV7_A15_PERFCTR_PC_WRITE_SPEC = 0x76,
190}; 109};
191 110
192/* 111/*
@@ -199,11 +118,11 @@ enum armv7_a15_perf_types {
199static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = { 118static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
200 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 119 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
201 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 120 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
202 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, 121 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
203 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, 122 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
204 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 123 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
205 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 124 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
206 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, 125 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
207}; 126};
208 127
209static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 128static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -217,12 +136,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
217 * combined. 136 * combined.
218 */ 137 */
219 [C(OP_READ)] = { 138 [C(OP_READ)] = {
220 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, 139 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
221 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, 140 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
222 }, 141 },
223 [C(OP_WRITE)] = { 142 [C(OP_WRITE)] = {
224 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, 143 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
225 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, 144 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
226 }, 145 },
227 [C(OP_PREFETCH)] = { 146 [C(OP_PREFETCH)] = {
228 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 147 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -231,12 +150,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
231 }, 150 },
232 [C(L1I)] = { 151 [C(L1I)] = {
233 [C(OP_READ)] = { 152 [C(OP_READ)] = {
234 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST, 153 [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
235 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS, 154 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
236 }, 155 },
237 [C(OP_WRITE)] = { 156 [C(OP_WRITE)] = {
238 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST, 157 [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
239 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS, 158 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
240 }, 159 },
241 [C(OP_PREFETCH)] = { 160 [C(OP_PREFETCH)] = {
242 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 161 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -245,12 +164,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
245 }, 164 },
246 [C(LL)] = { 165 [C(LL)] = {
247 [C(OP_READ)] = { 166 [C(OP_READ)] = {
248 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS, 167 [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
249 [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS, 168 [C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
250 }, 169 },
251 [C(OP_WRITE)] = { 170 [C(OP_WRITE)] = {
252 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS, 171 [C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
253 [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS, 172 [C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
254 }, 173 },
255 [C(OP_PREFETCH)] = { 174 [C(OP_PREFETCH)] = {
256 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 175 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -274,11 +193,11 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
274 [C(ITLB)] = { 193 [C(ITLB)] = {
275 [C(OP_READ)] = { 194 [C(OP_READ)] = {
276 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 195 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
277 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, 196 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
278 }, 197 },
279 [C(OP_WRITE)] = { 198 [C(OP_WRITE)] = {
280 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 199 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
281 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, 200 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
282 }, 201 },
283 [C(OP_PREFETCH)] = { 202 [C(OP_PREFETCH)] = {
284 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 203 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -287,14 +206,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
287 }, 206 },
288 [C(BPU)] = { 207 [C(BPU)] = {
289 [C(OP_READ)] = { 208 [C(OP_READ)] = {
290 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, 209 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
291 [C(RESULT_MISS)] 210 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
292 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
293 }, 211 },
294 [C(OP_WRITE)] = { 212 [C(OP_WRITE)] = {
295 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, 213 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
296 [C(RESULT_MISS)] 214 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
297 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
298 }, 215 },
299 [C(OP_PREFETCH)] = { 216 [C(OP_PREFETCH)] = {
300 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 217 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -322,13 +239,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
322 */ 239 */
323static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = { 240static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
324 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 241 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
325 [PERF_COUNT_HW_INSTRUCTIONS] = 242 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME,
326 ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE, 243 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
327 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_DCACHE_ACCESS, 244 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
328 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_DCACHE_REFILL,
329 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 245 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
330 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 246 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
331 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, 247 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
332}; 248};
333 249
334static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 250static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -342,12 +258,12 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
342 * combined. 258 * combined.
343 */ 259 */
344 [C(OP_READ)] = { 260 [C(OP_READ)] = {
345 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, 261 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
346 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, 262 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
347 }, 263 },
348 [C(OP_WRITE)] = { 264 [C(OP_WRITE)] = {
349 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS, 265 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
350 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL, 266 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
351 }, 267 },
352 [C(OP_PREFETCH)] = { 268 [C(OP_PREFETCH)] = {
353 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 269 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -357,11 +273,11 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
357 [C(L1I)] = { 273 [C(L1I)] = {
358 [C(OP_READ)] = { 274 [C(OP_READ)] = {
359 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 275 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
360 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, 276 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
361 }, 277 },
362 [C(OP_WRITE)] = { 278 [C(OP_WRITE)] = {
363 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 279 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
364 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, 280 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
365 }, 281 },
366 [C(OP_PREFETCH)] = { 282 [C(OP_PREFETCH)] = {
367 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 283 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -399,11 +315,11 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
399 [C(ITLB)] = { 315 [C(ITLB)] = {
400 [C(OP_READ)] = { 316 [C(OP_READ)] = {
401 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 317 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
402 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, 318 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
403 }, 319 },
404 [C(OP_WRITE)] = { 320 [C(OP_WRITE)] = {
405 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 321 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
406 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, 322 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
407 }, 323 },
408 [C(OP_PREFETCH)] = { 324 [C(OP_PREFETCH)] = {
409 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 325 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -412,14 +328,12 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
412 }, 328 },
413 [C(BPU)] = { 329 [C(BPU)] = {
414 [C(OP_READ)] = { 330 [C(OP_READ)] = {
415 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, 331 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
416 [C(RESULT_MISS)] 332 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
417 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
418 }, 333 },
419 [C(OP_WRITE)] = { 334 [C(OP_WRITE)] = {
420 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE, 335 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
421 [C(RESULT_MISS)] 336 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
422 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
423 }, 337 },
424 [C(OP_PREFETCH)] = { 338 [C(OP_PREFETCH)] = {
425 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 339 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -448,8 +362,8 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
448static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = { 362static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = {
449 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 363 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
450 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 364 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
451 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, 365 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
452 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, 366 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
453 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 367 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
454 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 368 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
455 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED, 369 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
@@ -460,42 +374,34 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
460 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 374 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
461 [C(L1D)] = { 375 [C(L1D)] = {
462 [C(OP_READ)] = { 376 [C(OP_READ)] = {
463 [C(RESULT_ACCESS)] 377 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
464 = ARMV7_PERFCTR_DCACHE_ACCESS, 378 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
465 [C(RESULT_MISS)]
466 = ARMV7_PERFCTR_DCACHE_REFILL,
467 }, 379 },
468 [C(OP_WRITE)] = { 380 [C(OP_WRITE)] = {
469 [C(RESULT_ACCESS)] 381 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
470 = ARMV7_PERFCTR_DCACHE_ACCESS, 382 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
471 [C(RESULT_MISS)]
472 = ARMV7_PERFCTR_DCACHE_REFILL,
473 }, 383 },
474 [C(OP_PREFETCH)] = { 384 [C(OP_PREFETCH)] = {
475 [C(RESULT_ACCESS)] 385 [C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
476 = ARMV7_PERFCTR_PREFETCH_LINEFILL, 386 [C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
477 [C(RESULT_MISS)]
478 = ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,
479 }, 387 },
480 }, 388 },
481 [C(L1I)] = { 389 [C(L1I)] = {
482 [C(OP_READ)] = { 390 [C(OP_READ)] = {
483 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 391 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
484 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, 392 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
485 }, 393 },
486 [C(OP_WRITE)] = { 394 [C(OP_WRITE)] = {
487 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 395 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
488 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, 396 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
489 }, 397 },
490 /* 398 /*
491 * The prefetch counters don't differentiate between the I 399 * The prefetch counters don't differentiate between the I
492 * side and the D side. 400 * side and the D side.
493 */ 401 */
494 [C(OP_PREFETCH)] = { 402 [C(OP_PREFETCH)] = {
495 [C(RESULT_ACCESS)] 403 [C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
496 = ARMV7_PERFCTR_PREFETCH_LINEFILL, 404 [C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
497 [C(RESULT_MISS)]
498 = ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,
499 }, 405 },
500 }, 406 },
501 [C(LL)] = { 407 [C(LL)] = {
@@ -529,11 +435,11 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
529 [C(ITLB)] = { 435 [C(ITLB)] = {
530 [C(OP_READ)] = { 436 [C(OP_READ)] = {
531 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 437 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
532 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, 438 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
533 }, 439 },
534 [C(OP_WRITE)] = { 440 [C(OP_WRITE)] = {
535 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 441 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
536 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, 442 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
537 }, 443 },
538 [C(OP_PREFETCH)] = { 444 [C(OP_PREFETCH)] = {
539 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 445 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -543,13 +449,11 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
543 [C(BPU)] = { 449 [C(BPU)] = {
544 [C(OP_READ)] = { 450 [C(OP_READ)] = {
545 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 451 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
546 [C(RESULT_MISS)] 452 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
547 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
548 }, 453 },
549 [C(OP_WRITE)] = { 454 [C(OP_WRITE)] = {
550 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 455 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
551 [C(RESULT_MISS)] 456 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
552 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
553 }, 457 },
554 [C(OP_PREFETCH)] = { 458 [C(OP_PREFETCH)] = {
555 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 459 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -564,9 +468,9 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
564static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = { 468static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = {
565 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 469 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
566 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 470 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
567 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED, 471 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
568 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED, 472 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
569 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_SPEC_PC_WRITE, 473 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A15_PERFCTR_PC_WRITE_SPEC,
570 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 474 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
571 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, 475 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES,
572}; 476};
@@ -576,16 +480,12 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
576 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 480 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
577 [C(L1D)] = { 481 [C(L1D)] = {
578 [C(OP_READ)] = { 482 [C(OP_READ)] = {
579 [C(RESULT_ACCESS)] 483 [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ,
580 = ARMV7_PERFCTR_L1_DCACHE_READ_ACCESS, 484 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ,
581 [C(RESULT_MISS)]
582 = ARMV7_PERFCTR_L1_DCACHE_READ_REFILL,
583 }, 485 },
584 [C(OP_WRITE)] = { 486 [C(OP_WRITE)] = {
585 [C(RESULT_ACCESS)] 487 [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE,
586 = ARMV7_PERFCTR_L1_DCACHE_WRITE_ACCESS, 488 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE,
587 [C(RESULT_MISS)]
588 = ARMV7_PERFCTR_L1_DCACHE_WRITE_REFILL,
589 }, 489 },
590 [C(OP_PREFETCH)] = { 490 [C(OP_PREFETCH)] = {
591 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 491 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -601,11 +501,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
601 */ 501 */
602 [C(OP_READ)] = { 502 [C(OP_READ)] = {
603 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 503 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
604 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, 504 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
605 }, 505 },
606 [C(OP_WRITE)] = { 506 [C(OP_WRITE)] = {
607 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 507 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
608 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS, 508 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
609 }, 509 },
610 [C(OP_PREFETCH)] = { 510 [C(OP_PREFETCH)] = {
611 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 511 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -614,16 +514,12 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
614 }, 514 },
615 [C(LL)] = { 515 [C(LL)] = {
616 [C(OP_READ)] = { 516 [C(OP_READ)] = {
617 [C(RESULT_ACCESS)] 517 [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ,
618 = ARMV7_PERFCTR_L2_DCACHE_READ_ACCESS, 518 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ,
619 [C(RESULT_MISS)]
620 = ARMV7_PERFCTR_L2_DCACHE_READ_REFILL,
621 }, 519 },
622 [C(OP_WRITE)] = { 520 [C(OP_WRITE)] = {
623 [C(RESULT_ACCESS)] 521 [C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE,
624 = ARMV7_PERFCTR_L2_DCACHE_WRITE_ACCESS, 522 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE,
625 [C(RESULT_MISS)]
626 = ARMV7_PERFCTR_L2_DCACHE_WRITE_REFILL,
627 }, 523 },
628 [C(OP_PREFETCH)] = { 524 [C(OP_PREFETCH)] = {
629 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 525 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -633,13 +529,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
633 [C(DTLB)] = { 529 [C(DTLB)] = {
634 [C(OP_READ)] = { 530 [C(OP_READ)] = {
635 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 531 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
636 [C(RESULT_MISS)] 532 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ,
637 = ARMV7_PERFCTR_L1_DTLB_READ_REFILL,
638 }, 533 },
639 [C(OP_WRITE)] = { 534 [C(OP_WRITE)] = {
640 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 535 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
641 [C(RESULT_MISS)] 536 [C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE,
642 = ARMV7_PERFCTR_L1_DTLB_WRITE_REFILL,
643 }, 537 },
644 [C(OP_PREFETCH)] = { 538 [C(OP_PREFETCH)] = {
645 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 539 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -649,11 +543,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
649 [C(ITLB)] = { 543 [C(ITLB)] = {
650 [C(OP_READ)] = { 544 [C(OP_READ)] = {
651 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 545 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
652 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, 546 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
653 }, 547 },
654 [C(OP_WRITE)] = { 548 [C(OP_WRITE)] = {
655 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 549 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
656 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS, 550 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL,
657 }, 551 },
658 [C(OP_PREFETCH)] = { 552 [C(OP_PREFETCH)] = {
659 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 553 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
@@ -663,13 +557,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
663 [C(BPU)] = { 557 [C(BPU)] = {
664 [C(OP_READ)] = { 558 [C(OP_READ)] = {
665 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 559 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
666 [C(RESULT_MISS)] 560 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
667 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
668 }, 561 },
669 [C(OP_WRITE)] = { 562 [C(OP_WRITE)] = {
670 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 563 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED,
671 [C(RESULT_MISS)] 564 [C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
672 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
673 }, 565 },
674 [C(OP_PREFETCH)] = { 566 [C(OP_PREFETCH)] = {
675 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED, 567 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-02 11:35:51 -0400