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authorBenoit Cousson <b-cousson@ti.com>2010-12-21 23:08:33 -0500
committerPaul Walmsley <paul@pwsan.com>2010-12-21 23:08:33 -0500
commit3b54baad8a79cc252e9d6a5ccc796b4c8b2b7173 (patch)
tree933b994384512bdf03adca8c384b4e2cecc0cfe3 /arch/arm
parent65ae65c9058eb41e9566ffd12699607c68b23e5f (diff)
OMAP4: hwmod data: Fix hwmod entries order
The original OMAP4 hwmod data files is fully generated from HW database. But since the file is introduced incrementaly along with driver that uses the data, it has to be splitted by the driver owner and then re-merged by the maintainer. Because of the similarity of the data, git is completely lost during such merge and thus the data does not look like the original one at the end. Re-order properly the structures to stay in sync with original data set. This makes it much easier to diff the autogenerated script output with what's in mainline, see differences, and generate patches for those diffs. The goal is to stay in sync with the autogenerated data from now on. Add a comment that does contain all the IPs that can have a hwmod, but do not have it in the file for the moment. It gives a good indication of the progress. Signed-off-by: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: updated to apply against current core integration branch, commit message slightly amplified; fixed opt_clks_cnt whitespace] Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Govindraj.R <govindraj.raja@ti.com> Cc: Charulatha V <charu@ti.com> Cc: Kevin Hilman <khilman@deeprootsystems.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c1003
1 files changed, 553 insertions, 450 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 4afd52ef59c1..121a5429585a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -173,6 +173,7 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
173 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 173 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
174}; 174};
175 175
176/* l3_main_1 interface data */
176/* l3_main_2 -> l3_main_1 */ 177/* l3_main_2 -> l3_main_1 */
177static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { 178static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
178 .master = &omap44xx_l3_main_2_hwmod, 179 .master = &omap44xx_l3_main_2_hwmod,
@@ -398,6 +399,464 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
398}; 399};
399 400
400/* 401/*
402 * 'mpu_bus' class
403 * instance(s): mpu_private
404 */
405static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
406 .name = "mpu_bus",
407};
408
409/* mpu_private interface data */
410/* mpu -> mpu_private */
411static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
412 .master = &omap44xx_mpu_hwmod,
413 .slave = &omap44xx_mpu_private_hwmod,
414 .clk = "l3_div_ck",
415 .user = OCP_USER_MPU | OCP_USER_SDMA,
416};
417
418/* mpu_private slave ports */
419static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
420 &omap44xx_mpu__mpu_private,
421};
422
423static struct omap_hwmod omap44xx_mpu_private_hwmod = {
424 .name = "mpu_private",
425 .class = &omap44xx_mpu_bus_hwmod_class,
426 .slaves = omap44xx_mpu_private_slaves,
427 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
428 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
429};
430
431/*
432 * Modules omap_hwmod structures
433 *
434 * The following IPs are excluded for the moment because:
435 * - They do not need an explicit SW control using omap_hwmod API.
436 * - They still need to be validated with the driver
437 * properly adapted to omap_hwmod / omap_device
438 *
439 * aess
440 * bandgap
441 * c2c
442 * c2c_target_fw
443 * cm_core
444 * cm_core_aon
445 * counter_32k
446 * ctrl_module_core
447 * ctrl_module_pad_core
448 * ctrl_module_pad_wkup
449 * ctrl_module_wkup
450 * debugss
451 * dma_system
452 * dmic
453 * dsp
454 * dss
455 * dss_dispc
456 * dss_dsi1
457 * dss_dsi2
458 * dss_hdmi
459 * dss_rfbi
460 * dss_venc
461 * efuse_ctrl_cust
462 * efuse_ctrl_std
463 * elm
464 * emif1
465 * emif2
466 * fdif
467 * gpmc
468 * gpu
469 * hdq1w
470 * hsi
471 * ipu
472 * iss
473 * iva
474 * kbd
475 * mailbox
476 * mcasp
477 * mcbsp1
478 * mcbsp2
479 * mcbsp3
480 * mcbsp4
481 * mcpdm
482 * mcspi1
483 * mcspi2
484 * mcspi3
485 * mcspi4
486 * mmc1
487 * mmc2
488 * mmc3
489 * mmc4
490 * mmc5
491 * mpu_c0
492 * mpu_c1
493 * ocmc_ram
494 * ocp2scp_usb_phy
495 * ocp_wp_noc
496 * prcm
497 * prcm_mpu
498 * prm
499 * scrm
500 * sl2if
501 * slimbus1
502 * slimbus2
503 * smartreflex_core
504 * smartreflex_iva
505 * smartreflex_mpu
506 * spinlock
507 * timer1
508 * timer10
509 * timer11
510 * timer2
511 * timer3
512 * timer4
513 * timer5
514 * timer6
515 * timer7
516 * timer8
517 * timer9
518 * usb_host_fs
519 * usb_host_hs
520 * usb_otg_hs
521 * usb_phy_cm
522 * usb_tll_hs
523 * usim
524 */
525
526/*
527 * 'gpio' class
528 * general purpose io module
529 */
530
531static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
532 .rev_offs = 0x0000,
533 .sysc_offs = 0x0010,
534 .syss_offs = 0x0114,
535 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
536 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
537 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
538 .sysc_fields = &omap_hwmod_sysc_type1,
539};
540
541static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
542 .name = "gpio",
543 .sysc = &omap44xx_gpio_sysc,
544 .rev = 2,
545};
546
547/* gpio dev_attr */
548static struct omap_gpio_dev_attr gpio_dev_attr = {
549 .bank_width = 32,
550 .dbck_flag = true,
551};
552
553/* gpio1 */
554static struct omap_hwmod omap44xx_gpio1_hwmod;
555static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
556 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
557};
558
559static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
560 {
561 .pa_start = 0x4a310000,
562 .pa_end = 0x4a3101ff,
563 .flags = ADDR_TYPE_RT
564 },
565};
566
567/* l4_wkup -> gpio1 */
568static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
569 .master = &omap44xx_l4_wkup_hwmod,
570 .slave = &omap44xx_gpio1_hwmod,
571 .addr = omap44xx_gpio1_addrs,
572 .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs),
573 .user = OCP_USER_MPU | OCP_USER_SDMA,
574};
575
576/* gpio1 slave ports */
577static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
578 &omap44xx_l4_wkup__gpio1,
579};
580
581static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
582 { .role = "dbclk", .clk = "sys_32k_ck" },
583};
584
585static struct omap_hwmod omap44xx_gpio1_hwmod = {
586 .name = "gpio1",
587 .class = &omap44xx_gpio_hwmod_class,
588 .mpu_irqs = omap44xx_gpio1_irqs,
589 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
590 .main_clk = "gpio1_ick",
591 .prcm = {
592 .omap4 = {
593 .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
594 },
595 },
596 .opt_clks = gpio1_opt_clks,
597 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
598 .dev_attr = &gpio_dev_attr,
599 .slaves = omap44xx_gpio1_slaves,
600 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
601 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
602};
603
604/* gpio2 */
605static struct omap_hwmod omap44xx_gpio2_hwmod;
606static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
607 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
608};
609
610static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
611 {
612 .pa_start = 0x48055000,
613 .pa_end = 0x480551ff,
614 .flags = ADDR_TYPE_RT
615 },
616};
617
618/* l4_per -> gpio2 */
619static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
620 .master = &omap44xx_l4_per_hwmod,
621 .slave = &omap44xx_gpio2_hwmod,
622 .addr = omap44xx_gpio2_addrs,
623 .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
624 .user = OCP_USER_MPU | OCP_USER_SDMA,
625};
626
627/* gpio2 slave ports */
628static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
629 &omap44xx_l4_per__gpio2,
630};
631
632static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
633 { .role = "dbclk", .clk = "sys_32k_ck" },
634};
635
636static struct omap_hwmod omap44xx_gpio2_hwmod = {
637 .name = "gpio2",
638 .class = &omap44xx_gpio_hwmod_class,
639 .mpu_irqs = omap44xx_gpio2_irqs,
640 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
641 .main_clk = "gpio2_ick",
642 .prcm = {
643 .omap4 = {
644 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
645 },
646 },
647 .opt_clks = gpio2_opt_clks,
648 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
649 .dev_attr = &gpio_dev_attr,
650 .slaves = omap44xx_gpio2_slaves,
651 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
652 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
653};
654
655/* gpio3 */
656static struct omap_hwmod omap44xx_gpio3_hwmod;
657static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
658 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
659};
660
661static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
662 {
663 .pa_start = 0x48057000,
664 .pa_end = 0x480571ff,
665 .flags = ADDR_TYPE_RT
666 },
667};
668
669/* l4_per -> gpio3 */
670static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
671 .master = &omap44xx_l4_per_hwmod,
672 .slave = &omap44xx_gpio3_hwmod,
673 .addr = omap44xx_gpio3_addrs,
674 .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
675 .user = OCP_USER_MPU | OCP_USER_SDMA,
676};
677
678/* gpio3 slave ports */
679static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
680 &omap44xx_l4_per__gpio3,
681};
682
683static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
684 { .role = "dbclk", .clk = "sys_32k_ck" },
685};
686
687static struct omap_hwmod omap44xx_gpio3_hwmod = {
688 .name = "gpio3",
689 .class = &omap44xx_gpio_hwmod_class,
690 .mpu_irqs = omap44xx_gpio3_irqs,
691 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
692 .main_clk = "gpio3_ick",
693 .prcm = {
694 .omap4 = {
695 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
696 },
697 },
698 .opt_clks = gpio3_opt_clks,
699 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
700 .dev_attr = &gpio_dev_attr,
701 .slaves = omap44xx_gpio3_slaves,
702 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
703 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
704};
705
706/* gpio4 */
707static struct omap_hwmod omap44xx_gpio4_hwmod;
708static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
709 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
710};
711
712static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
713 {
714 .pa_start = 0x48059000,
715 .pa_end = 0x480591ff,
716 .flags = ADDR_TYPE_RT
717 },
718};
719
720/* l4_per -> gpio4 */
721static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
722 .master = &omap44xx_l4_per_hwmod,
723 .slave = &omap44xx_gpio4_hwmod,
724 .addr = omap44xx_gpio4_addrs,
725 .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs),
726 .user = OCP_USER_MPU | OCP_USER_SDMA,
727};
728
729/* gpio4 slave ports */
730static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
731 &omap44xx_l4_per__gpio4,
732};
733
734static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
735 { .role = "dbclk", .clk = "sys_32k_ck" },
736};
737
738static struct omap_hwmod omap44xx_gpio4_hwmod = {
739 .name = "gpio4",
740 .class = &omap44xx_gpio_hwmod_class,
741 .mpu_irqs = omap44xx_gpio4_irqs,
742 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
743 .main_clk = "gpio4_ick",
744 .prcm = {
745 .omap4 = {
746 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
747 },
748 },
749 .opt_clks = gpio4_opt_clks,
750 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
751 .dev_attr = &gpio_dev_attr,
752 .slaves = omap44xx_gpio4_slaves,
753 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
754 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
755};
756
757/* gpio5 */
758static struct omap_hwmod omap44xx_gpio5_hwmod;
759static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
760 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
761};
762
763static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
764 {
765 .pa_start = 0x4805b000,
766 .pa_end = 0x4805b1ff,
767 .flags = ADDR_TYPE_RT
768 },
769};
770
771/* l4_per -> gpio5 */
772static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
773 .master = &omap44xx_l4_per_hwmod,
774 .slave = &omap44xx_gpio5_hwmod,
775 .addr = omap44xx_gpio5_addrs,
776 .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs),
777 .user = OCP_USER_MPU | OCP_USER_SDMA,
778};
779
780/* gpio5 slave ports */
781static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
782 &omap44xx_l4_per__gpio5,
783};
784
785static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
786 { .role = "dbclk", .clk = "sys_32k_ck" },
787};
788
789static struct omap_hwmod omap44xx_gpio5_hwmod = {
790 .name = "gpio5",
791 .class = &omap44xx_gpio_hwmod_class,
792 .mpu_irqs = omap44xx_gpio5_irqs,
793 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
794 .main_clk = "gpio5_ick",
795 .prcm = {
796 .omap4 = {
797 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
798 },
799 },
800 .opt_clks = gpio5_opt_clks,
801 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
802 .dev_attr = &gpio_dev_attr,
803 .slaves = omap44xx_gpio5_slaves,
804 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
805 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
806};
807
808/* gpio6 */
809static struct omap_hwmod omap44xx_gpio6_hwmod;
810static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
811 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
812};
813
814static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
815 {
816 .pa_start = 0x4805d000,
817 .pa_end = 0x4805d1ff,
818 .flags = ADDR_TYPE_RT
819 },
820};
821
822/* l4_per -> gpio6 */
823static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
824 .master = &omap44xx_l4_per_hwmod,
825 .slave = &omap44xx_gpio6_hwmod,
826 .addr = omap44xx_gpio6_addrs,
827 .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
828 .user = OCP_USER_MPU | OCP_USER_SDMA,
829};
830
831/* gpio6 slave ports */
832static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
833 &omap44xx_l4_per__gpio6,
834};
835
836static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
837 { .role = "dbclk", .clk = "sys_32k_ck" },
838};
839
840static struct omap_hwmod omap44xx_gpio6_hwmod = {
841 .name = "gpio6",
842 .class = &omap44xx_gpio_hwmod_class,
843 .mpu_irqs = omap44xx_gpio6_irqs,
844 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
845 .main_clk = "gpio6_ick",
846 .prcm = {
847 .omap4 = {
848 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
849 },
850 },
851 .opt_clks = gpio6_opt_clks,
852 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
853 .dev_attr = &gpio_dev_attr,
854 .slaves = omap44xx_gpio6_slaves,
855 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
856 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
857};
858
859/*
401 * 'i2c' class 860 * 'i2c' class
402 * multimaster high-speed i2c controller 861 * multimaster high-speed i2c controller
403 */ 862 */
@@ -405,9 +864,9 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
405static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { 864static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
406 .sysc_offs = 0x0010, 865 .sysc_offs = 0x0010,
407 .syss_offs = 0x0090, 866 .syss_offs = 0x0090,
408 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 867 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
409 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SOFTRESET | 868 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
410 SYSC_HAS_AUTOIDLE), 869 SYSC_HAS_SOFTRESET),
411 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 870 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
412 .sysc_fields = &omap_hwmod_sysc_type1, 871 .sysc_fields = &omap_hwmod_sysc_type1,
413}; 872};
@@ -630,36 +1089,6 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
630}; 1089};
631 1090
632/* 1091/*
633 * 'mpu_bus' class
634 * instance(s): mpu_private
635 */
636static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
637 .name = "mpu_bus",
638};
639
640/* mpu_private interface data */
641/* mpu -> mpu_private */
642static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
643 .master = &omap44xx_mpu_hwmod,
644 .slave = &omap44xx_mpu_private_hwmod,
645 .clk = "l3_div_ck",
646 .user = OCP_USER_MPU | OCP_USER_SDMA,
647};
648
649/* mpu_private slave ports */
650static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
651 &omap44xx_mpu__mpu_private,
652};
653
654static struct omap_hwmod omap44xx_mpu_private_hwmod = {
655 .name = "mpu_private",
656 .class = &omap44xx_mpu_bus_hwmod_class,
657 .slaves = omap44xx_mpu_private_slaves,
658 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
659 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
660};
661
662/*
663 * 'mpu' class 1092 * 'mpu' class
664 * mpu sub-system 1093 * mpu sub-system
665 */ 1094 */
@@ -700,22 +1129,6 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
700}; 1129};
701 1130
702/* 1131/*
703 * 'wd_timer' class
704 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
705 * overflow condition
706 */
707
708static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
709 .rev_offs = 0x0000,
710 .sysc_offs = 0x0010,
711 .syss_offs = 0x0014,
712 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
713 SYSC_HAS_SOFTRESET),
714 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
715 .sysc_fields = &omap_hwmod_sysc_type1,
716};
717
718/*
719 * 'uart' class 1132 * 'uart' class
720 * universal asynchronous receiver/transmitter (uart) 1133 * universal asynchronous receiver/transmitter (uart)
721 */ 1134 */
@@ -724,32 +1137,12 @@ static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
724 .rev_offs = 0x0050, 1137 .rev_offs = 0x0050,
725 .sysc_offs = 0x0054, 1138 .sysc_offs = 0x0054,
726 .syss_offs = 0x0058, 1139 .syss_offs = 0x0058,
727 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 1140 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
728 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 1141 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
729 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1142 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
730 .sysc_fields = &omap_hwmod_sysc_type1, 1143 .sysc_fields = &omap_hwmod_sysc_type1,
731}; 1144};
732 1145
733static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
734 .name = "wd_timer",
735 .sysc = &omap44xx_wd_timer_sysc,
736 .pre_shutdown = &omap2_wd_timer_disable
737};
738
739/* wd_timer2 */
740static struct omap_hwmod omap44xx_wd_timer2_hwmod;
741static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
742 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
743};
744
745static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
746 {
747 .pa_start = 0x4a314000,
748 .pa_end = 0x4a31407f,
749 .flags = ADDR_TYPE_RT
750 },
751};
752
753static struct omap_hwmod_class omap44xx_uart_hwmod_class = { 1146static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
754 .name = "uart", 1147 .name = "uart",
755 .sysc = &omap44xx_uart_sysc, 1148 .sysc = &omap44xx_uart_sysc,
@@ -826,51 +1219,6 @@ static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
826 }, 1219 },
827}; 1220};
828 1221
829/* l4_wkup -> wd_timer2 */
830static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
831 .master = &omap44xx_l4_wkup_hwmod,
832 .slave = &omap44xx_wd_timer2_hwmod,
833 .clk = "l4_wkup_clk_mux_ck",
834 .addr = omap44xx_wd_timer2_addrs,
835 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
836 .user = OCP_USER_MPU | OCP_USER_SDMA,
837};
838
839/* wd_timer2 slave ports */
840static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
841 &omap44xx_l4_wkup__wd_timer2,
842};
843
844static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
845 .name = "wd_timer2",
846 .class = &omap44xx_wd_timer_hwmod_class,
847 .mpu_irqs = omap44xx_wd_timer2_irqs,
848 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
849 .main_clk = "wd_timer2_fck",
850 .prcm = {
851 .omap4 = {
852 .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
853 },
854 },
855 .slaves = omap44xx_wd_timer2_slaves,
856 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
857 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
858};
859
860/* wd_timer3 */
861static struct omap_hwmod omap44xx_wd_timer3_hwmod;
862static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
863 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
864};
865
866static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
867 {
868 .pa_start = 0x40130000,
869 .pa_end = 0x4013007f,
870 .flags = ADDR_TYPE_RT
871 },
872};
873
874/* l4_per -> uart2 */ 1222/* l4_per -> uart2 */
875static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { 1223static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
876 .master = &omap44xx_l4_per_hwmod, 1224 .master = &omap44xx_l4_per_hwmod,
@@ -923,25 +1271,6 @@ static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
923 }, 1271 },
924}; 1272};
925 1273
926/* l4_abe -> wd_timer3 */
927static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
928 .master = &omap44xx_l4_abe_hwmod,
929 .slave = &omap44xx_wd_timer3_hwmod,
930 .clk = "ocp_abe_iclk",
931 .addr = omap44xx_wd_timer3_addrs,
932 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
933 .user = OCP_USER_MPU,
934};
935
936/* l4_abe -> wd_timer3 (dma) */
937static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
938 {
939 .pa_start = 0x49030000,
940 .pa_end = 0x4903007f,
941 .flags = ADDR_TYPE_RT
942 },
943};
944
945/* l4_per -> uart3 */ 1274/* l4_per -> uart3 */
946static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { 1275static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
947 .master = &omap44xx_l4_per_hwmod, 1276 .master = &omap44xx_l4_per_hwmod,
@@ -995,37 +1324,6 @@ static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
995 }, 1324 },
996}; 1325};
997 1326
998static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
999 .master = &omap44xx_l4_abe_hwmod,
1000 .slave = &omap44xx_wd_timer3_hwmod,
1001 .clk = "ocp_abe_iclk",
1002 .addr = omap44xx_wd_timer3_dma_addrs,
1003 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
1004 .user = OCP_USER_SDMA,
1005};
1006
1007/* wd_timer3 slave ports */
1008static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
1009 &omap44xx_l4_abe__wd_timer3,
1010 &omap44xx_l4_abe__wd_timer3_dma,
1011};
1012
1013static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
1014 .name = "wd_timer3",
1015 .class = &omap44xx_wd_timer_hwmod_class,
1016 .mpu_irqs = omap44xx_wd_timer3_irqs,
1017 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
1018 .main_clk = "wd_timer3_fck",
1019 .prcm = {
1020 .omap4 = {
1021 .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
1022 },
1023 },
1024 .slaves = omap44xx_wd_timer3_slaves,
1025 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
1026 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1027};
1028
1029/* l4_per -> uart4 */ 1327/* l4_per -> uart4 */
1030static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { 1328static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
1031 .master = &omap44xx_l4_per_hwmod, 1329 .master = &omap44xx_l4_per_hwmod,
@@ -1060,337 +1358,136 @@ static struct omap_hwmod omap44xx_uart4_hwmod = {
1060}; 1358};
1061 1359
1062/* 1360/*
1063 * 'gpio' class 1361 * 'wd_timer' class
1064 * general purpose io module 1362 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1363 * overflow condition
1065 */ 1364 */
1066 1365
1067static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { 1366static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
1068 .rev_offs = 0x0000, 1367 .rev_offs = 0x0000,
1069 .sysc_offs = 0x0010, 1368 .sysc_offs = 0x0010,
1070 .syss_offs = 0x0114, 1369 .syss_offs = 0x0014,
1071 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 1370 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1072 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 1371 SYSC_HAS_SOFTRESET),
1073 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 1372 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1074 .sysc_fields = &omap_hwmod_sysc_type1, 1373 .sysc_fields = &omap_hwmod_sysc_type1,
1075}; 1374};
1076 1375
1077static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { 1376static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
1078 .name = "gpio", 1377 .name = "wd_timer",
1079 .sysc = &omap44xx_gpio_sysc, 1378 .sysc = &omap44xx_wd_timer_sysc,
1080 .rev = 2, 1379 .pre_shutdown = &omap2_wd_timer_disable
1081};
1082
1083/* gpio dev_attr */
1084static struct omap_gpio_dev_attr gpio_dev_attr = {
1085 .bank_width = 32,
1086 .dbck_flag = true,
1087}; 1380};
1088 1381
1089/* gpio1 */ 1382/* wd_timer2 */
1090static struct omap_hwmod omap44xx_gpio1_hwmod; 1383static struct omap_hwmod omap44xx_wd_timer2_hwmod;
1091static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { 1384static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
1092 { .irq = 29 + OMAP44XX_IRQ_GIC_START }, 1385 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
1093}; 1386};
1094 1387
1095static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { 1388static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
1096 { 1389 {
1097 .pa_start = 0x4a310000, 1390 .pa_start = 0x4a314000,
1098 .pa_end = 0x4a3101ff, 1391 .pa_end = 0x4a31407f,
1099 .flags = ADDR_TYPE_RT 1392 .flags = ADDR_TYPE_RT
1100 }, 1393 },
1101}; 1394};
1102 1395
1103/* l4_wkup -> gpio1 */ 1396/* l4_wkup -> wd_timer2 */
1104static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { 1397static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
1105 .master = &omap44xx_l4_wkup_hwmod, 1398 .master = &omap44xx_l4_wkup_hwmod,
1106 .slave = &omap44xx_gpio1_hwmod, 1399 .slave = &omap44xx_wd_timer2_hwmod,
1107 .addr = omap44xx_gpio1_addrs, 1400 .clk = "l4_wkup_clk_mux_ck",
1108 .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs), 1401 .addr = omap44xx_wd_timer2_addrs,
1109 .user = OCP_USER_MPU | OCP_USER_SDMA, 1402 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
1110};
1111
1112/* gpio1 slave ports */
1113static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1114 &omap44xx_l4_wkup__gpio1,
1115};
1116
1117static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1118 { .role = "dbclk", .clk = "sys_32k_ck" },
1119};
1120
1121static struct omap_hwmod omap44xx_gpio1_hwmod = {
1122 .name = "gpio1",
1123 .class = &omap44xx_gpio_hwmod_class,
1124 .mpu_irqs = omap44xx_gpio1_irqs,
1125 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
1126 .main_clk = "gpio1_ick",
1127 .prcm = {
1128 .omap4 = {
1129 .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1130 },
1131 },
1132 .opt_clks = gpio1_opt_clks,
1133 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1134 .dev_attr = &gpio_dev_attr,
1135 .slaves = omap44xx_gpio1_slaves,
1136 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
1137 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1138};
1139
1140/* gpio2 */
1141static struct omap_hwmod omap44xx_gpio2_hwmod;
1142static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1143 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1144};
1145
1146static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1147 {
1148 .pa_start = 0x48055000,
1149 .pa_end = 0x480551ff,
1150 .flags = ADDR_TYPE_RT
1151 },
1152};
1153
1154/* l4_per -> gpio2 */
1155static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1156 .master = &omap44xx_l4_per_hwmod,
1157 .slave = &omap44xx_gpio2_hwmod,
1158 .addr = omap44xx_gpio2_addrs,
1159 .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
1160 .user = OCP_USER_MPU | OCP_USER_SDMA,
1161};
1162
1163/* gpio2 slave ports */
1164static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1165 &omap44xx_l4_per__gpio2,
1166};
1167
1168static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1169 { .role = "dbclk", .clk = "sys_32k_ck" },
1170};
1171
1172static struct omap_hwmod omap44xx_gpio2_hwmod = {
1173 .name = "gpio2",
1174 .class = &omap44xx_gpio_hwmod_class,
1175 .mpu_irqs = omap44xx_gpio2_irqs,
1176 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
1177 .main_clk = "gpio2_ick",
1178 .prcm = {
1179 .omap4 = {
1180 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1181 },
1182 },
1183 .opt_clks = gpio2_opt_clks,
1184 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1185 .dev_attr = &gpio_dev_attr,
1186 .slaves = omap44xx_gpio2_slaves,
1187 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
1188 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1189};
1190
1191/* gpio3 */
1192static struct omap_hwmod omap44xx_gpio3_hwmod;
1193static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1194 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1195};
1196
1197static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1198 {
1199 .pa_start = 0x48057000,
1200 .pa_end = 0x480571ff,
1201 .flags = ADDR_TYPE_RT
1202 },
1203};
1204
1205/* l4_per -> gpio3 */
1206static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1207 .master = &omap44xx_l4_per_hwmod,
1208 .slave = &omap44xx_gpio3_hwmod,
1209 .addr = omap44xx_gpio3_addrs,
1210 .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
1211 .user = OCP_USER_MPU | OCP_USER_SDMA, 1403 .user = OCP_USER_MPU | OCP_USER_SDMA,
1212}; 1404};
1213 1405
1214/* gpio3 slave ports */ 1406/* wd_timer2 slave ports */
1215static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = { 1407static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
1216 &omap44xx_l4_per__gpio3, 1408 &omap44xx_l4_wkup__wd_timer2,
1217};
1218
1219static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1220 { .role = "dbclk", .clk = "sys_32k_ck" },
1221}; 1409};
1222 1410
1223static struct omap_hwmod omap44xx_gpio3_hwmod = { 1411static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
1224 .name = "gpio3", 1412 .name = "wd_timer2",
1225 .class = &omap44xx_gpio_hwmod_class, 1413 .class = &omap44xx_wd_timer_hwmod_class,
1226 .mpu_irqs = omap44xx_gpio3_irqs, 1414 .mpu_irqs = omap44xx_wd_timer2_irqs,
1227 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs), 1415 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
1228 .main_clk = "gpio3_ick", 1416 .main_clk = "wd_timer2_fck",
1229 .prcm = { 1417 .prcm = {
1230 .omap4 = { 1418 .omap4 = {
1231 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL, 1419 .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
1232 }, 1420 },
1233 }, 1421 },
1234 .opt_clks = gpio3_opt_clks, 1422 .slaves = omap44xx_wd_timer2_slaves,
1235 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 1423 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
1236 .dev_attr = &gpio_dev_attr,
1237 .slaves = omap44xx_gpio3_slaves,
1238 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
1239 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1424 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1240}; 1425};
1241 1426
1242/* gpio4 */ 1427/* wd_timer3 */
1243static struct omap_hwmod omap44xx_gpio4_hwmod; 1428static struct omap_hwmod omap44xx_wd_timer3_hwmod;
1244static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { 1429static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
1245 { .irq = 32 + OMAP44XX_IRQ_GIC_START }, 1430 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
1246}; 1431};
1247 1432
1248static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { 1433static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
1249 { 1434 {
1250 .pa_start = 0x48059000, 1435 .pa_start = 0x40130000,
1251 .pa_end = 0x480591ff, 1436 .pa_end = 0x4013007f,
1252 .flags = ADDR_TYPE_RT 1437 .flags = ADDR_TYPE_RT
1253 }, 1438 },
1254}; 1439};
1255 1440
1256/* l4_per -> gpio4 */ 1441/* l4_abe -> wd_timer3 */
1257static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { 1442static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
1258 .master = &omap44xx_l4_per_hwmod, 1443 .master = &omap44xx_l4_abe_hwmod,
1259 .slave = &omap44xx_gpio4_hwmod, 1444 .slave = &omap44xx_wd_timer3_hwmod,
1260 .addr = omap44xx_gpio4_addrs, 1445 .clk = "ocp_abe_iclk",
1261 .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs), 1446 .addr = omap44xx_wd_timer3_addrs,
1262 .user = OCP_USER_MPU | OCP_USER_SDMA, 1447 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
1263}; 1448 .user = OCP_USER_MPU,
1264
1265/* gpio4 slave ports */
1266static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1267 &omap44xx_l4_per__gpio4,
1268};
1269
1270static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1271 { .role = "dbclk", .clk = "sys_32k_ck" },
1272};
1273
1274static struct omap_hwmod omap44xx_gpio4_hwmod = {
1275 .name = "gpio4",
1276 .class = &omap44xx_gpio_hwmod_class,
1277 .mpu_irqs = omap44xx_gpio4_irqs,
1278 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
1279 .main_clk = "gpio4_ick",
1280 .prcm = {
1281 .omap4 = {
1282 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1283 },
1284 },
1285 .opt_clks = gpio4_opt_clks,
1286 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1287 .dev_attr = &gpio_dev_attr,
1288 .slaves = omap44xx_gpio4_slaves,
1289 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
1290 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1291};
1292
1293/* gpio5 */
1294static struct omap_hwmod omap44xx_gpio5_hwmod;
1295static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1296 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1297}; 1449};
1298 1450
1299static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { 1451static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
1300 { 1452 {
1301 .pa_start = 0x4805b000, 1453 .pa_start = 0x49030000,
1302 .pa_end = 0x4805b1ff, 1454 .pa_end = 0x4903007f,
1303 .flags = ADDR_TYPE_RT 1455 .flags = ADDR_TYPE_RT
1304 }, 1456 },
1305}; 1457};
1306 1458
1307/* l4_per -> gpio5 */ 1459/* l4_abe -> wd_timer3 (dma) */
1308static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { 1460static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
1309 .master = &omap44xx_l4_per_hwmod, 1461 .master = &omap44xx_l4_abe_hwmod,
1310 .slave = &omap44xx_gpio5_hwmod, 1462 .slave = &omap44xx_wd_timer3_hwmod,
1311 .addr = omap44xx_gpio5_addrs, 1463 .clk = "ocp_abe_iclk",
1312 .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs), 1464 .addr = omap44xx_wd_timer3_dma_addrs,
1313 .user = OCP_USER_MPU | OCP_USER_SDMA, 1465 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
1314}; 1466 .user = OCP_USER_SDMA,
1315
1316/* gpio5 slave ports */
1317static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1318 &omap44xx_l4_per__gpio5,
1319}; 1467};
1320 1468
1321static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { 1469/* wd_timer3 slave ports */
1322 { .role = "dbclk", .clk = "sys_32k_ck" }, 1470static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
1471 &omap44xx_l4_abe__wd_timer3,
1472 &omap44xx_l4_abe__wd_timer3_dma,
1323}; 1473};
1324 1474
1325static struct omap_hwmod omap44xx_gpio5_hwmod = { 1475static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
1326 .name = "gpio5", 1476 .name = "wd_timer3",
1327 .class = &omap44xx_gpio_hwmod_class, 1477 .class = &omap44xx_wd_timer_hwmod_class,
1328 .mpu_irqs = omap44xx_gpio5_irqs, 1478 .mpu_irqs = omap44xx_wd_timer3_irqs,
1329 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs), 1479 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
1330 .main_clk = "gpio5_ick", 1480 .main_clk = "wd_timer3_fck",
1331 .prcm = { 1481 .prcm = {
1332 .omap4 = { 1482 .omap4 = {
1333 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL, 1483 .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
1334 }, 1484 },
1335 }, 1485 },
1336 .opt_clks = gpio5_opt_clks, 1486 .slaves = omap44xx_wd_timer3_slaves,
1337 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), 1487 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
1338 .dev_attr = &gpio_dev_attr,
1339 .slaves = omap44xx_gpio5_slaves,
1340 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
1341 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 1488 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1342}; 1489};
1343 1490
1344/* gpio6 */
1345static struct omap_hwmod omap44xx_gpio6_hwmod;
1346static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1347 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1348};
1349
1350static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1351 {
1352 .pa_start = 0x4805d000,
1353 .pa_end = 0x4805d1ff,
1354 .flags = ADDR_TYPE_RT
1355 },
1356};
1357
1358/* l4_per -> gpio6 */
1359static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1360 .master = &omap44xx_l4_per_hwmod,
1361 .slave = &omap44xx_gpio6_hwmod,
1362 .addr = omap44xx_gpio6_addrs,
1363 .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
1364 .user = OCP_USER_MPU | OCP_USER_SDMA,
1365};
1366
1367/* gpio6 slave ports */
1368static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
1369 &omap44xx_l4_per__gpio6,
1370};
1371
1372static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1373 { .role = "dbclk", .clk = "sys_32k_ck" },
1374};
1375
1376static struct omap_hwmod omap44xx_gpio6_hwmod = {
1377 .name = "gpio6",
1378 .class = &omap44xx_gpio_hwmod_class,
1379 .mpu_irqs = omap44xx_gpio6_irqs,
1380 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
1381 .main_clk = "gpio6_ick",
1382 .prcm = {
1383 .omap4 = {
1384 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1385 },
1386 },
1387 .opt_clks = gpio6_opt_clks,
1388 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1389 .dev_attr = &gpio_dev_attr,
1390 .slaves = omap44xx_gpio6_slaves,
1391 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
1392 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1393};
1394 1491
1395/* 1492/*
1396 * 'dma' class 1493 * 'dma' class
@@ -1481,13 +1578,16 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
1481static __initdata struct omap_hwmod *omap44xx_hwmods[] = { 1578static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
1482 /* dmm class */ 1579 /* dmm class */
1483 &omap44xx_dmm_hwmod, 1580 &omap44xx_dmm_hwmod,
1581
1484 /* emif_fw class */ 1582 /* emif_fw class */
1485 &omap44xx_emif_fw_hwmod, 1583 &omap44xx_emif_fw_hwmod,
1584
1486 /* l3 class */ 1585 /* l3 class */
1487 &omap44xx_l3_instr_hwmod, 1586 &omap44xx_l3_instr_hwmod,
1488 &omap44xx_l3_main_1_hwmod, 1587 &omap44xx_l3_main_1_hwmod,
1489 &omap44xx_l3_main_2_hwmod, 1588 &omap44xx_l3_main_2_hwmod,
1490 &omap44xx_l3_main_3_hwmod, 1589 &omap44xx_l3_main_3_hwmod,
1590
1491 /* l4 class */ 1591 /* l4 class */
1492 &omap44xx_l4_abe_hwmod, 1592 &omap44xx_l4_abe_hwmod,
1493 &omap44xx_l4_cfg_hwmod, 1593 &omap44xx_l4_cfg_hwmod,
@@ -1497,11 +1597,6 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
1497 /* dma class */ 1597 /* dma class */
1498 &omap44xx_dma_system_hwmod, 1598 &omap44xx_dma_system_hwmod,
1499 1599
1500 /* i2c class */
1501 &omap44xx_i2c1_hwmod,
1502 &omap44xx_i2c2_hwmod,
1503 &omap44xx_i2c3_hwmod,
1504 &omap44xx_i2c4_hwmod,
1505 /* mpu_bus class */ 1600 /* mpu_bus class */
1506 &omap44xx_mpu_private_hwmod, 1601 &omap44xx_mpu_private_hwmod,
1507 1602
@@ -1513,17 +1608,25 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
1513 &omap44xx_gpio5_hwmod, 1608 &omap44xx_gpio5_hwmod,
1514 &omap44xx_gpio6_hwmod, 1609 &omap44xx_gpio6_hwmod,
1515 1610
1611 /* i2c class */
1612 &omap44xx_i2c1_hwmod,
1613 &omap44xx_i2c2_hwmod,
1614 &omap44xx_i2c3_hwmod,
1615 &omap44xx_i2c4_hwmod,
1616
1516 /* mpu class */ 1617 /* mpu class */
1517 &omap44xx_mpu_hwmod, 1618 &omap44xx_mpu_hwmod,
1518 /* wd_timer class */
1519 &omap44xx_wd_timer2_hwmod,
1520 &omap44xx_wd_timer3_hwmod,
1521 1619
1522 /* uart class */ 1620 /* uart class */
1523 &omap44xx_uart1_hwmod, 1621 &omap44xx_uart1_hwmod,
1524 &omap44xx_uart2_hwmod, 1622 &omap44xx_uart2_hwmod,
1525 &omap44xx_uart3_hwmod, 1623 &omap44xx_uart3_hwmod,
1526 &omap44xx_uart4_hwmod, 1624 &omap44xx_uart4_hwmod,
1625
1626 /* wd_timer class */
1627 &omap44xx_wd_timer2_hwmod,
1628 &omap44xx_wd_timer3_hwmod,
1629
1527 NULL, 1630 NULL,
1528}; 1631};
1529 1632
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-28 00:31:28 -0500